1 TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor

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1  TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor | Manualzz

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

7.18 TSIP Peripheral

The telecom serial interface port (TSIP) module provides a glueless interface to common telecom serial data streams.

For more information, see the Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

7.18.1 TSIP Electrical Data/Timing

Table 7-74

(see Figure 7-51 )

Timing Requirements for TSIP 2x Mode

(1)

No.

1

2

3

4

5

6

7

8 t c

(CLK) t w

(CLKL) t w

(CLKH) t t

(CLK) t su

(FS-CLK) t h

(CLK-FS) t su

(TR-CLK) t h

(CLK-TR)

9 t d

(CLKL-TX)

10 t dis

(CLKH-TXZ)

End of Table 7-74

Cycle time, CLK rising edge to next CLK rising edge

Pulse duration, CLK low

Pulse duration, CLK high

Transition time, CLK high to low or CLK low to high

Setup time, FS valid before rising CLK

Hold time, FS valid after rising CLK

Setup time, TR valid before rising CLK

Hold time, TR valid after rising CLK

Delay time, CLK low to TX valid

Disable time, CLK low to TX Hi-Z

Min

0.4×t c

0.4×t c

61

(2)

(CLK)

(CLK)

5

5

5

5

1

2

Max

2

12

10

1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 1b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.

ns ns ns ns

Unit

ns ns ns ns ns ns

Figure 7-51

1

CLKA/B

TSIP 2x Timing Diagram

2

(1)

3

5

6

FSA/B

8

TR[n]

ts127-3 ts127-2

7

ts127-1 ts127-0

9

ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

TX[n]

ts127-3 ts127-2 ts127-1 ts127-0 ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1 and a XMTDATD=1

Copyright 2014 Texas Instruments Incorporated

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Peripheral Information and Electrical Specifications 213

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 7-75

(see Figure 7-52 )

Timing Requirements for TSIP 1x Mode

(1)

No.

11

12

13

14

15

16

17

18 t c

(CLK) t w

(CLKL) t w

(CLKH) t t

(CLK) t su

(FS-CLK) t h

(CLK-FS) t su

(TR-CLK) t h

(CLK-TR)

19 t d

(CLKL-TX)

20 t dis

(CLKH-TXZ)

End of Table 7-75

Cycle time, CLK rising edge to next CLK rising edge

Pulse duration, CLK low

Pulse duration, CLK high

Transition time, CLK high to low or CLK low to high

Setup time, FS valid before rising CLK

Hold time, FS valid after rising CLK

Setup time, TR valid before rising CLK

Hold time, TR valid after rising CLK

Delay time, CLK low to TX valid

Disable time, CLK low to TX Hi-Z

Min

122.1

0.4×t c

0.4×t c

(2)

(CLK)

(CLK)

5

5

5

5

1

2

Max

2

12

10

1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.

ns ns ns ns

Unit

ns ns ns ns ns ns

Figure 7-52 TSIP 1x Timing Diagram

(1)

11 12 13

CLKA/B

16

15

FSA/B

TR[n]

ts127-3 ts127-2 ts127-1 ts127-0

17

18

ts000-7

19

ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

TX[n]

ts127-3 ts127-2 ts127-1 ts127-0 ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.

214 Peripheral Information and Electrical Specifications Copyright 2014 Texas Instruments Incorporated

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