16-Bit, 8-Channel, 500 kSPS PulSAR ADC AD7699

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

REF

REFIN

GND

GND

4

5

1

2

3

AD7699

TOP VIEW

(Not to Scale)

15 VIO

14

13

SDO

SCK

12

11

DIN

CNV

AD7699

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type 1 Description

1, 20

2

3

4, 5

6 to 9

10

11

12

13

14

15

16 to 19

VDD

REF

REFIN

GND P

IN4 to IN7 AI

COM AI

CNV

DIN

P Power Supply. Nominally 4.5 to 5.5 V and should be decoupled with 10 μF and 100 nF capacitors.

AI/O

Reference Input/Output. See the Voltage Reference Output/Input section.

When the internal reference is enabled, this pin produces 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin

(VDD – 0.5 V maximum) useful when using low cost, low power references.

For improved drift performance, connect a precision reference to REF (0.5 V to VDD).

For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as

close to REF as possible. See the Reference Decoupling section.

AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section.

When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor.

When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as previously described.

DI

DI

Power Supply Ground.

Analog Input Channel 4, Analog Input Channel 5, Analog Input Channel 6, and Analog Input Channel 7.

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or V

REF

/2 V.

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled.

Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

SCK

SDO

VIO

IN0 to IN3

DI

DO

P

AI

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an

MSB first fashion.

Serial Data Output. The conversion result is output on this pin and synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,

3 V, or 5 V).

Analog Input Channel 0, Analog Input Channel 1, Analog Input Channel 2, and Analog Input Channel 3.

21 (EPAD) Exposed

Paddle

(EPAD)

The exposed paddle is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the GND plane.

1

AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.

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