ATMEGA8L-8MU-T скачать даташит

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16-bit

Timer/Counter1

The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are:

True 16-bit Design (i.e., allows 16-bit PWM)

Two Independent Output Compare Units

Double Buffered Output Compare Registers

One Input Capture Unit

Input Capture Noise Canceler

Clear Timer on Compare Match (Auto Reload)

Glitch-free, Phase Correct Pulse Width Modulator (PWM)

Variable PWM Period

Frequency Generator

External Event Counter

Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Overview

Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in

Figure 32

. For the actual

placement of I/O pins, refer to “Pin Configurations” on page 2 . CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “16-bit Timer/Counter Register Description” on page 96 .

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Registers

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Figure 32. 16-bit Timer/Counter Block Diagram

(1)

Count

Clear

Direction

Control Logic clk

Tn

TOP BOTTOM

Timer/Counter

TCNTn

= =

0

=

OCRnA

=

OCRnB

ICRn

TCCRnA

TOVn

(Int. Req.)

Clock Select

Edge

Detector

( From Prescaler )

Tn

OCFnA

(Int. Req.)

Waveform

Generation

OCnA

Fixed

TOP

Values

TCCRnB

ICFn (Int.Req.)

Edge

Detector

OCFnB

(Int.Req.)

Waveform

Generation

OCnB

( From Analog

Comparator Ouput )

Noise

Canceler

ICPn

Note:

1. Refer to “Pin Configurations” on page 2 ,

Table 22 on page 58

, and Table 28 on page 63

for

Timer/Counter1 pin placement and description.

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-

ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16bit registers. These procedures are described in the section

“Accessing 16-bit Registers” on page 79

. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer

Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk

T 1

).

The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B).

See “Output Compare Units” on page 84.

The Compare Match event will also set the Compare Match

Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.

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Definitions

Compatibility

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see

“Analog Comparator” on page 193). The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using

OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output.

The following definitions are used extensively throughout the document:

Table 35. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFFFF (decimal

65535).

The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.

The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit

AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding:

• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt

Registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and register location:

• PWM10 is changed to WGM10.

• PWM11 is changed to WGM11.

• CTC1 is changed to WGM12.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• FOC1A and FOC1B are added to TCCR1A.

• WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.

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Accessing 16-bit

Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.

The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation. When the Low byte of a

16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read.

Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16bit registers does not involve using the temporary register.

To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the

Low byte must be read before the High byte.

The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.

Assembly Code Example

(1)

...

; Set TCNT1 to 0x01FF

ldi

r17,0x01

ldi

r16,0xFF

out

TCNT1H,r17

out

TCNT1L,r16

; Read TCNT1 into r17:r16

in

r16,TCNT1L

in

r17,TCNT1H

...

C Code Example

(1)

unsigned int

i;

...

/* Set TCNT1 to 0x01FF */

TCNT

1 = 0x1FF;

/* Read TCNT1 into i */ i = TCNT

1;

...

Note:

1. See “About Code Examples” on page 8.

The assembly code example returns the TCNT1 value in the r17:r16 Register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNT1 Register contents.

Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Example

(1)

TIM16_ReadTCNT1:

; Save Global Interrupt Flag

in

r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in

r16,TCNT1L

in

r17,TCNT1H

; Restore Global Interrupt Flag

out

SREG,r18

ret

C Code Example

(1)

unsigned int

TIM16_ReadTCNT1( void )

{

unsigned char

sreg;

unsigned int

i;

/* Save Global Interrupt Flag */ sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */ i = TCNT

1;

/* Restore Global Interrupt Flag */

SREG = sreg;

return

i;

}

Note:

1. See “About Code Examples” on page 8.

The assembly code example returns the TCNT1 value in the r17:r16 Register pair.

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The following code examples show how to do an atomic write of the TCNT1 Register contents.

Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Example

(1)

TIM16_WriteTCNT1:

; Save Global Interrupt Flag

in

r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

out

TCNT1H,r17

out

TCNT1L,r16

; Restore Global Interrupt Flag

out

SREG,r18

ret

C Code Example

(1)

void

TIM16_WriteTCNT1( unsigned int i )

{

unsigned char

sreg;

unsigned int

i;

/* Save Global Interrupt Flag */ sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TCNT

1 = i;

/* Restore Global Interrupt Flag */

SREG = sreg;

}

Note:

1. See “About Code Examples” on page 8.

The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNT1.

Reusing the

Temporary High Byte

Register

If writing to more than one 16-bit register where the High byte is the same for all registers written, then the High byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case.

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Timer/Counter

Clock Sources

Counter Unit

82

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see

“Timer/Counter0 and Timer/Counter1 Prescalers” on page 74 .

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 33 shows a block diagram of the counter and its surroundings.

Figure 33. Counter Unit Block Diagram

DATA BUS

(8-bit)

TOVn

(Int. Req.)

TEMP (8-bit)

TCNTnH (8-bit) TCNTnL (8-bit)

TCNTn (16-bit Counter) count clear direction

Control Logic clk

Tn

Clock Select

Edge

Detector

Tn

( From Prescaler )

TOP BOTTOM

Signal description (internal signals):

count

Increment or decrement TCNT1 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT1 (set all bits to zero).

clk

T 1

TOP

Timer/Counter clock.

Signalize that TCNT1 has reached maximum value.

BOTTOM

Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the High byte temporary register

(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk

T 1

). The clk

T 1

can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clk

T 1

is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).

There are close connections between how the counter behaves (counts) and how waveforms

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are generated on the Output Compare Outputs OC1x. For more details about advanced count-

ing sequences and waveform generation, see “Modes of Operation” on page 88 .

The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit.

The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 34 . The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number.

Figure 34. Input Capture Unit Block Diagram

DATA BUS

(8-bit)

TEMP (8-bit)

ICRnH (8-bit)

WRITE

ICRnL (8-bit)

ICRn (16-bit Register)

TCNTnH (8-bit) TCNTnL (8-bit)

TCNTn (16-bit Counter)

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ACO*

Analog

Comparator

ACIC* ICNC

Noise

Canceler

ICES

Edge

Detector

ICFn (Int. Req.)

ICPn

When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 =

1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register.

The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-

83

Input Capture Pin

Source

Noise Canceler

Using the Input

Capture Unit

Output Compare

Units

tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1

Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O location before the Low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to

“Accessing 16-bit Registers” on page 79 .

The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter

1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator

Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change.

Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin (

Figure 30 on page 74 ). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in

Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the

ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler.

The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1

Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used).

The 16-bit comparator continuously compares TCNT1 with the Output Compare Register

(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output

Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-

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ing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode

(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (

See “Modes of Operation” on page 88.

)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.

counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator.

Figure 35

shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output

Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output

Compare unit are gray shaded.

Figure 35. Output Compare Unit, Block Diagram

DATA BUS

(8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit)

OCRnx Buffer (16-bit Register)

TCNTnH (8-bit) TCNTnL (8-bit)

TCNTn (16-bit Counter)

OCRnxH (8-bit) OCRnxL (8-bit)

OCRnx (16-bit Register)

TOP

BOTTOM

=

(16-bit Comparator )

OCFnx (Int.Req.)

Waveform Generator

WGMn3:0 COMnx1:0

OCnx

The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare

Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)

Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The High byte (OCR1xH) has to be

85

Force Output

Compare

Compare Match

Blocking by TCNT1

Write

Using the Output

Compare Unit

written first. When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the Low byte (OCR1xL) is written to the lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 79 .

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the

OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real Compare

Match had occurred (the COM1x1:0 bits settings define whether the OC1x pin is set, cleared or toggled).

All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNT1 equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to

0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

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Compare Match

Output Unit

The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match.

Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 36 shows a simplified

schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the

OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x Register is reset to “0”.

Figure 36. Compare Match Output Unit, Schematic

COMnx1

COMnx0

FOCnx

Waveform

Generator

D Q

OCnx

D Q

1

0

PORT

D Q

OCnx

Pin

DDR

clk

I/O

The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to

Table 36 , Table 37

and Table 38 for details.

The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of oper-

ation. See “16-bit Timer/Counter Register Description” on page 96.

The COM1x1:0 bits have no effect on the Input Capture unit.

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Compare Output Mode and Waveform

Generation

The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the

OC1x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to

Table 36 on page 97 . For fast PWM mode refer to Table 37 on page 97

, and for phase correct and phase and frequency correct PWM refer to Table 38 on page

98

.

A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC1x strobe bits.

Modes of

Operation

Normal Mode

The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output

mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a Compare

Match.

See “Compare Match Output Unit” on page 87.

For detailed timing information refer to

“Timer/Counter Timing Diagrams” on page 95

.

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

Clear Timer on

Compare Match (CTC)

Mode

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =

12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in

Figure 37 . The counter value (TCNT1)

increases until a Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.

88

ATmega8(L)

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Figure 37. CTC Mode, Timing Diagram

ATmega8(L)

OCnA Interrupt Flag Set or ICFn Interrupt Flag Set

(Interrupt on TOP)

Fast PWM Mode

TCNTn

OCnA

(Toggle)

Period

1 2 3 4

(COMnA1:0 = 1)

An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of

TCNT1, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur.

In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode

(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of f

OC

1

A

= f clk_I/O

/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation:

f

OCnA

=

2

N

(

f

1 +

OCRnA

)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000.

The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare

Output mode output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or

OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max-

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2486W–AVR–02/10

imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:

R

FPWM

= log

TOP 1 log 2

+

)

In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =

14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 38 . The figure shows

fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs.

Figure 38. Fast PWM Mode, Timing Diagram

OCRnx / TOP Update and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnx

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

Period

1 2 3 4 5 6 7 8

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new

ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.

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Phase Correct PWM

Mode

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.

Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See

Table 37 on page 97

. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

OCnxPWM

=

f

N

⋅ (

1 +

TOP

)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the

COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of f

OC

1

A

= f clk_I/O

/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the

Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:

R

PCPWM

= log

TOP 1 log 2

+

)

In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1

(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on

Figure 39 . The figure

shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

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2486W–AVR–02/10

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs.

Figure 39. Phase Correct PWM Mode, Timing Diagram

OCRnx / TOP Update and

OCnA Interrupt Flag Set or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

92

TCNTn

OCnx

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

Period

1 2 3 4

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCR1x Registers are written. As the third period shown in Figure 39

illustrates, changing the

TOP actively while the Timer/Counter is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.

It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM1x1:0 to 3. See

Table 38 on page 98

. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when

ATmega8(L)

2486W–AVR–02/10

ATmega8(L)

the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

f

OCnxPCPWM

=

f

----------------------------

2 clk_I/O

N TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

If OCR1A is used to define the TOP value (WMG13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

Phase and Frequency

Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 39

and

Figure 40

).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation:

R

PFCPWM

= log

TOP 1 log 2

+

)

In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on

Figure 40 . The figure shows phase and frequency correct PWM

mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs.

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Figure 40. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set or

ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx / TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

94

TCNTn

OCnx

OCnx

Period

1 2 3 4

(COMnx1:0 = 2)

(COMnx1:0 = 3)

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x

Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.

The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x.

As Figure 40

shows the output generated is, in contrast to the Phase Correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See

Table 38 on page

98

. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the

OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and

TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation:

f

OCnxPFCPWM

=

f

----------------------------

2

N TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the

ATmega8(L)

2486W–AVR–02/10

ATmega8(L)

Timer/Counter

Timing Diagrams

output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values.

If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

The Timer/Counter is a synchronous design and the timer clock (clk

T1

) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).

Figure 41 shows a timing diagram for the setting of OCF1x.

Figure 41. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clk

I/O

clk

Tn

(clk

I/O

/1)

TCNTn

OCRnx

OCRnx - 1 OCRnx

OCRnx Value

OCRnx + 1 OCRnx + 2

OCFnx

Figure 42 shows the same timing data, but with the prescaler enabled.

Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk_I/O

/8)

clk

I/O

clk

(clk

I/O

Tn

/8)

TCNTn

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCRnx

OCFnx

OCRnx Value

Figure 43 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams

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2486W–AVR–02/10

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOV1 Flag at BOTTOM.

Figure 43. Timer/Counter Timing Diagram, no Prescaling clk

I/O clk

Tn

(clk

I/O

/1)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn

(FPWM) and ICFn

(if used as TOP)

OCRnx

(Update at TOP)

TOP - 1

TOP - 1

Old OCRnx Value

TOP

TOP

BOTTOM

TOP - 1

BOTTOM + 1

New OCRnx Value

TOP - 2

Figure 44 shows the same timing data, but with the prescaler enabled.

Figure 44. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O

/8) clk

I/O clk

(clk

Tn

I/O

/8)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn

(FPWM) and ICFn

(if used as TOP)

OCRnx

(Update at TOP)

TOP - 1

TOP - 1

Old OCRnx Value

TOP

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

New OCRnx Value

16-bit

Timer/Counter

Register

Description

Timer/Counter 1

Control Register A –

TCCR1A

96

Bit

Read/Write

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

FOC1A

W

2

FOC1B

W

1

WGM11

R/W

0

WGM10

R/W

TCCR1A

ATmega8(L)

2486W–AVR–02/10

2486W–AVR–02/10

ATmega8(L)

Initial Value 0 0 0 0 0 0

• Bit 7:6 – COM1A1:0: Compare Output Mode for channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for channel B

0 0

The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting.

Table 36

shows the COM1x1:0 bit functionality when the

WGM13:0 bits are set to a normal or a CTC mode (non-PWM).

Table 36. Compare Output Mode, Non-PWM

COM1A1/

COM1B1

COM1A0/

COM1B0 Description

1

1

0

0

0

1

0

1

Normal port operation, OC1A/OC1B disconnected.

Toggle OC1A/OC1B on Compare Match

Clear OC1A/OC1B on Compare Match (Set output to low level)

Set OC1A/OC1B on Compare Match (Set output to high level)

Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM

mode.

Table 37. Compare Output Mode, Fast PWM

(1)

COM1A1/

COM1B1

COM1A0/

COM1B0 Description

0

0

0

1

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.

1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at

BOTTOM, (non-inverting mode)

1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at

BOTTOM, (inverting mode)

Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the Compare Match is ignored, but the set or clear is done at BOTTOM.

See “Fast

PWM Mode” on page 89.

for more details.

97

Table 38

shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode.

Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

(1)

COM1A1/

COM1B1

0

COM1A0/

COM1B0 Description

0 Normal port operation, OC1A/OC1B disconnected.

0

1

1

0

WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match when up-counting. Set

OC1A/OC1B on Compare Match when downcounting.

1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear

OC1A/OC1B on Compare Match when downcounting.

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See

“Phase Correct PWM Mode” on page 91.

for more details.

• Bit 3 – FOC1A: Force Output Compare for channel A

• Bit 2 – FOC1B: Force Output Compare for channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.

However, for ensuring compatibility with future devices, these bits must be set to zero when

TCCR1A is written when operating in a PWM mode. When writing a logical one to the

FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit.

The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the

FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the

COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP.

The FOC1A/FOC1B bits are always read as zero.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see

Table 39 . Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (

See “Modes of Operation” on page 88.

)

Table 39. Waveform Generation Mode Bit Description

Mode WGM13

WGM12

(CTC1)

WGM11

(PWM11)

WGM10

(PWM10)

Timer/Counter Mode of

Operation

(1)

4

5

6

2

3

0

1

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

1

1

1

0

0

0

1

0

0

1

0

1

Normal

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

PWM, Phase Correct, 10-bit

CTC

Fast PWM, 8-bit

Fast PWM, 9-bit

TOP

Update of

OCR1 x

TOV1 Flag

Set on

0xFFFF Immediate MAX

0x00FF TOP BOTTOM

0x01FF TOP

0x03FF TOP

BOTTOM

BOTTOM

OCR1A Immediate MAX

0x00FF BOTTOM TOP

0x01FF BOTTOM TOP

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Table 39. Waveform Generation Mode Bit Description

Mode WGM13

7 0

10

11

8

9

12

13

1

1

1

1

1

1

WGM12

(CTC1)

1

0

0

0

0

1

1

WGM11

(PWM11)

1

1

1

0

0

0

0

WGM10

(PWM10)

1

0

1

0

1

0

1

Timer/Counter Mode of

Operation

(1)

Fast PWM, 10-bit

TOP

Update of

OCR1 x

0x03FF BOTTOM

TOV1 Flag

Set on

TOP

PWM, Phase and Frequency Correct ICR1 BOTTOM

PWM, Phase and Frequency Correct OCR1A BOTTOM

PWM, Phase Correct

PWM, Phase Correct

ICR1

OCR1A

TOP

TOP

CTC

(Reserved)

ICR1

BOTTOM

BOTTOM

BOTTOM

BOTTOM

Immediate MAX

– –

14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP

15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP

Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the

WGM

12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.

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Timer/Counter 1

Control Register B –

TCCR1B

Bit

Read/Write

Initial Value

7

ICNC1

R/W

0

6

ICES1

R/W

0

R

0

5

4

WGM13

R/W

0

3

WGM12

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

0

CS10

R/W

0

TCCR1B

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into the

Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter, see

Figure

41

and

Figure 42 .

Table 40. Clock Select Bit Description

CS12 CS11 CS10 Description

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

No clock source. (Timer/Counter stopped) clk

I/O

/1 (No prescaling) clk

I/O

/8 (From prescaler) clk

I/O

/64 (From prescaler) clk

I/O

/256 (From prescaler) clk

I/O

/1024 (From prescaler)

External clock source on T1 pin. Clock on falling edge.

External clock source on T1 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.

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Timer/Counter 1 –

TCNT1H and TCNT1L

Bit

Read/Write

Initial Value

7

R/W

0

6

R/W

0

5

R/W

0

4 3

TCNT1[15:8]

TCNT1[7:0]

R/W R/W

0 0

2

R/W

0

1

R/W

0

0

R/W

0

TCNT1H

TCNT1L

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers.

See “Accessing 16-bit

Registers” on page 79.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock for all compare units.

Output Compare

Register 1 A –

OCR1AH and OCR1AL

Bit

Read/Write

Initial Value

7

R/W

0

6

R/W

0

5

R/W

0

4 3

OCR1A[15:8]

OCR1A[7:0]

R/W R/W

0 0

2

R/W

0

1

R/W

0

0

R/W

0

OCR1AH

OCR1AL

Output Compare

Register 1 B –

OCR1BH and OCR1BL

Bit

Read/Write

Initial Value

7

R/W

0

6

R/W

0

5

R/W

0

4 3

OCR1B[15:8]

OCR1B[7:0]

R/W R/W

0 0

2

R/W

0

1

R/W

0

0

R/W

0

OCR1BH

OCR1BL

The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the

other 16-bit registers. See “Accessing 16-bit Registers” on page 79.

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Input Capture Register

1 – ICR1H and ICR1L

Bit

Read/Write

Initial Value

7

R/W

0

6

R/W

0

5

R/W

0

4

ICR1[15:8]

3

ICR1[7:0]

R/W R/W

0 0

2

R/W

0

1

R/W

0

0

R/W

0

ICR1H

ICR1L

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 79.

Timer/Counter

Interrupt Mask

Register – TIMSK

(1)

Bit

Read/Write

Initial Value

7

OCIE2

R/W

0

6

TOIE2

R/W

0

5

TICIE1

R/W

0

4

OCIE1A

R/W

0

3

OCIE1B

R/W

0

2

TOIE1

R/W

0

R

0

1

0

TOIE0

R/W

0

TIMSK

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.

• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 46) is executed when the ICF1 Flag, located in TIFR, is set.

• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1A Flag, located in

TIFR, is set.

• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1B Flag, located in

TIFR, is set.

• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector

(see “Interrupts” on page 46) is executed when the TOV1 Flag, located in TIFR, is set.

Timer/Counter

Interrupt Flag Register

– TIFR

(1)

Bit

Read/Write

Initial Value

7

OCF2

R/W

0

6

TOV2

R/W

0

5

ICF1

R/W

0

4

OCF1A

R/W

0

3

OCF1B

R/W

0

2

TOV1

R/W

0

R

0

1

0

TOV0

R/W

0

TIFR

Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

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This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 2 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the

TOV1 Flag is set when the timer overflows. Refer to

Table 39 on page 98

for the TOV1 Flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

103

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