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USART

Overview

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ATmega8(L)

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly-flexible serial communication device. The main features are:

Full Duplex Operation (Independent Serial Receive and Transmit Registers)

Asynchronous or Synchronous Operation

Master or Slave Clocked Synchronous Operation

High Resolution Baud Rate Generator

Supports Serial Frames with 5, 6, 7, 8, or 9 Databits and 1 or 2 Stop Bits

Odd or Even Parity Generation and Parity Check Supported by Hardware

Data OverRun Detection

Framing Error Detection

Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

Multi-processor Communication Mode

Double Speed Asynchronous Communication Mode

A simplified block diagram of the USART Transmitter is shown in Figure 61 . CPU accessible I/O

Registers and I/O pins are shown in bold.

Figure 61. USART Block Diagram

(1)

Clock Generator

UBRR[H:L]

BAUD RATE GENERATOR

OSC

SYNC LOGIC

UDR (Transmit)

TRANSMIT SHIFT REGISTER

PARITY

GENERATOR

RECEIVE SHIFT REGISTER

UDR (Receive)

CLOCK

RECOVERY

DATA

RECOVERY

PARITY

CHECKER

PIN

CONTROL

Transmitter

TX

CONTROL

XCK

PIN

CONTROL

Receiver

RX

CONTROL

TxD

PIN

CONTROL

RxD

UCSRA UCSRB UCSRC

Note:

1. Refer to “Pin Configurations” on page 2 ,

Table 30 on page 64 , and Table 29 on page 64

for

USART pin placement.

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AVR USART vs. AVR

UART – Compatibility

The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all units.

The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (transfer clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial

Shift Register, Parity Generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The

Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.

The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers.

• Baud Rate Generation.

• Transmitter Operation.

• Transmit Buffer Functionality.

• Receiver Operation.

However, the receive buffering has two improvements that will affect the compatibility in some special cases:

• A second Buffer Register has been added. The two Buffer Registers operate as a circular

FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error Flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost.

• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see

Figure 61 ) if the Buffer Registers are

full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun

(DOR) error conditions.

The following control bits have changed name, but have same functionality and register location:

• CHR9 is changed to UCSZ2.

• OR is changed to DOR.

Clock Generation

The clock generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: normal asynchronous, double speed asynchronous, Master synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation.

Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin

(DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode.

Figure 62 shows a block diagram of the clock generation logic.

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Figure 62. Clock Generation Logic, Block Diagram

UBRR

Prescaling

Down-Counter fosc

UBRR+1

/ 2

OSC

Sync

Register

Edge

Detector

XCK

Pin xcki xcko

DDR_XCK UCPOL

/ 4 / 2

U2X

0

1

DDR_XCK

0

1

0

1 txclk

UMSEL

1

0 rxclk

Internal Clock

Generation – The

Baud Rate Generator

Signal description:

txclk

Transmitter clock. (Internal Signal)

rxclk

Receiver base clock. (Internal Signal)

xcki

Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master operation.

fosc

XTAL pin frequency (System Clock).

Internal clock generation is used for the asynchronous and the Synchronous Master modes of

operation. The description in this section refers to Figure 62 .

The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock

(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the

UMSEL, U2X and DDR_XCK bits.

Table 52 contains equations for calculating the baud rate (in bits per second) and for calculating

the UBRR value for each mode of operation using an internally generated clock source.

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Double Speed

Operation (U2X)

External Clock

Table 52. Equations for Calculating Baud Rate Register Setting

Equation for Calculating

Baud Rate

(1)

Equation for Calculating

UBRR Value Operating Mode

Asynchronous Normal mode

(U2X = 0)

Asynchronous Double Speed

Mode (U2X = 1)

Synchronous Master Mode

BAUD

=

f

---------------------------------------

16

(

UBRR 1

)

BAUD

=

f

-----------------------------------

8

(

UBRR 1

)

BAUD

=

f

-----------------------------------

2

(

UBRR 1

)

UBRR

= ------------------------

16

f

BAUD

– 1

UBRR

= --------------------

8

f

BAUD

– 1

UBRR

= --------------------

2

f

BAUD

1

Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD Baud rate (in bits per second, bps) f

OSC

System Oscillator clock frequency

UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)

Some examples of UBRR values for some system clock frequencies are found in

Table 60 (see page 159

).

The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides.

External clocking is used by the Synchronous Slave modes of operation. The description in this

section refers to Figure 62 for details.

External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation:

f

XCK

<

f

-----------

4

Note that f osc

depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations.

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Synchronous Clock

Operation

Frame Formats

When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed.

Figure 63. Synchronous Mode XCK Timing

UCPOL = 1 XCK

RxD / TxD

Sample

UCPOL = 0 XCK

RxD / TxD

Sample

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As

Figure 63 shows, when UCPOL is zero the data will be changed at ris-

ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.

A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 64

illustrates the possible combinations of the frame formats. Bits inside brackets are optional.

Figure 64. Frame Formats

FRAME

(IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE)

St

(n)

P

Sp

Start bit, always low.

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

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IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero.

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows:

P even

P odd

=

=

d d

⊕ … ⊕

d

d

⊕ ⊕

d

⊕ … ⊕

d

3

3

d

2

2

d d

1

1

d

0

0

0

1

P even

P odd

Parity bit using even parity.

Parity bit using odd parity.

d n

Data bit n of the character.

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

USART

Initialization

The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the

Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data in the receive buffer. Note that the TXC Flag must be cleared before each transmission (before UDR is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling

(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.

For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC.

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Assembly Code Example

(1)

USART_Init:

; Set baud rate

out

UBRRH, r17

out

UBRRL, r16

; Enable receiver and transmitter

ldi

r16, (1<<RXEN)|(1<<TXEN)

out

UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi

r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)

out

UCSRC,r16

ret

C Code Example

(1)

#define FOSC 1843200// Clock Speed

#define BAUD 9600

#define MYUBRR FOSC/16/BAUD-1

void

main( void )

{

...

USART_Init ( MYUBRR );

...

}

void

USART_Init( unsigned int ubrr)

{

/* Set baud rate */

UBRRH = (unsigned char)(ubrr>>8);

UBRRL = (unsigned char)ubrr;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);

}

Note:

1. See “About Code Examples” on page 8.

More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the Baud and

Control Registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules.

139

Data Transmission

– The USART

Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB

Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock.

Sending Frames with

5 to 8 Data Bits

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The

CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,

U2X bit or by XCK depending on mode of operation.

The following code examples show a simple USART transmit function based on polling of the

Data Register Empty (UDRE) Flag. When using frames with less than eight bits, the most significant bits written to the UDR are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register

R16

Assembly Code Example

(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis

UCSRA,UDRE

rjmp

USART_Transmit

; Put data (r16) into buffer, sends the data

out

UDR,r16

ret

C Code Example

(1)

void

USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while

( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

Note:

1. See “About Code Examples” on page 8.

The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty Interrupt is utilized, the interrupt routine writes the data into the buffer.

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Sending Frames with

9 Data Bits

If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.

Assembly Code Example

(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis

UCSRA,UDRE

rjmp

USART_Transmit

; Copy ninth bit from r17 to TXB8

cbi

UCSRB,TXB8

sbrc

r17,0

sbi

UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out

UDR,r16

ret

C Code Example

(1)

void

USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while

( !( UCSRA & (1<<UDRE)) )

;

/* Copy ninth bit to TXB8 */

UCSRB &= ~(1<<TXB8); if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

Note: 1. These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRB is static. I.e. only the TXB8 bit of the UCSRB Register is used after initialization.

The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other protocol handling as for example synchronization.

Transmitter Flags and

Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register Empty

(UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts.

The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register.

When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register empty Interrupt routine must either write new data to

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Parity Generator

Disabling the

Transmitter

UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The

TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC Flag is useful in half-duplex communication interfaces (like the RS485 standard), where a transmitting application must enter Receive mode and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit

Complete Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC Flag, this is done automatically when the interrupt is executed.

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPM1 = 1), the Transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent.

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted). When disabled, the Transmitter will no longer override the TxD pin.

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Data Reception –

The USART

Receiver

The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.

Receiving Frames with

5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received (i.e., a complete serial frame is present in the Receive Shift Register), the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location.

The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used.

Assembly Code Example

(1)

USART_Receive:

; Wait for data to be received

sbis

UCSRA, RXC

rjmp

USART_Receive

; Get and return received data from buffer

in

r16, UDR

ret

C Code Example

(1)

unsigned char

USART_Receive( void )

{

/* Wait for data to be received */

while

( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return

UDR;

}

Note:

1. See “About Code Examples” on page 8.

The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value.

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Receiving Frames with

9 Data Bits

If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB

before reading the low bits from the UDR. This rule applies to the FE, DOR and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change.

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The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits.

Assembly Code Example

(1)

USART_Receive:

; Wait for data to be received

sbis

UCSRA, RXC

rjmp

USART_Receive

; Get status and ninth bit, then data from buffer

in

r18, UCSRA

in

r17, UCSRB

in

r16, UDR

; If error, return -1

andi

r18,(1<<FE)|(1<<DOR)|(1<<PE)

breq

USART_ReceiveNoError

ldi

r17, HIGH(-1)

ldi

r16, LOW(-1)

USART_ReceiveNoError:

; Filter the ninth bit, then return

lsr

r17

andi

r17, 0x01

ret

C Code Example

(1)

unsigned int

USART_Receive( void )

{

unsigned char

status, resh, resl;

/* Wait for data to be received */

while

( !(UCSRA & (1<<RXC)) )

;

/* Get status and ninth bit, then data */

/* from buffer */ status = UCSRA; resh = UCSRB; resl = UDR;

/* If error, return -1 */

if

( status & (1<<FE)|(1<<DOR)|(1<<PE) )

return

-1;

/* Filter the ninth bit, then return */ resh = (resh >> 1) & 0x01;

return

((resh << 8) | resl);

}

Note:

1. See “About Code Examples” on page 8.

The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible.

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Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero.

When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive

Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags

The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity

Error (PE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future

USART implementations. None of the error flags can generate interrupts.

The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to

UCSRA.

The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data

OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from

UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA.

The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer.

The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see

“Parity Bit Calculation” on page 138

and

“Parity Checker” on page 147

.

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Parity Checker

The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity

Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error.

The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read.

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive

Buffer

The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer.

Assembly Code Example

(1)

USART_Flush:

sbis

UCSRA, RXC

ret in

r16, UDR

rjmp

USART_Flush

C Code Example

(1)

void

USART_Flush( void )

{

unsigned char

dummy;

while

( UCSRA & (1<<RXC) ) dummy = UDR;

}

Note:

1. See “About Code Examples” on page 8.

Asynchronous

Data Reception

Asynchronous Clock

Recovery

The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

The clock recovery logic synchronizes internal clock to the incoming serial frames.

Figure 65

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity).

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Figure 65. Start Bit Sampling

RxD IDLE START BIT 0

Sample

(U2X = 0)

Sample

(U2X = 1)

0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

0 1 2 3 4 5 6 7 8 1 2

Asynchronous Data

Recovery

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.

When the Receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode.

Figure 66 shows the sampling of the data bits and the

parity bit. Each of the samples is given a number that is equal to the state of the recovery unit.

Figure 66. Sampling of Data and Parity Bit

RxD BIT n

Sample

(U2X = 0)

Sample

(U2X = 1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1

1 2 3 4 5 6 7 8 1

The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the Receiver only uses the first stop bit of a frame.

Figure 67 shows the sampling of the stop bit and the earliest possible beginning of the start bit of

the next frame.

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Figure 67. Stop Bit Sampling and Next Start Bit Sampling

RxD STOP 1

(A)

Sample

(U2X = 0)

Sample

(U2X = 1)

(B)

1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1

1 2 3 4 5 6 0/1

(C)

Asynchronous

Operational Range

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 67

. For Double Speed mode the first low level must be delayed to (B).

(C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver.

The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see

Table 53

) base frequency, the Receiver will not be able to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and internal

Receiver baud rate.

R slow

=

D 1

+

)S

D S

+

S

F

R fast

=

(

+

)S

+

M

D

S

Sum of character size and parity size (D = 5- to 10-bit)

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.

S

S

F

M

First sample number used for majority voting. S

F

= 8 for Normal Speed and S

F

= 4 for Double Speed mode.

Middle sample number used for majority voting. S

M

= 9 for Normal Speed and S

M

= 5 for Double Speed mode.

R slow is the ratio of the slowest incoming data rate that can be accepted in relation to the

Receiver baud rate. R fast

is the ratio of the fastest incoming data rate that can be accepted in relation to the Receiver baud rate.

Table 53 and Table 54

list the maximum Receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations.

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Table 53. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X =

0)

D#

(Data+Parity Bit)

5

R slow

(%) R fast

(%)

93,20 106,67

Max Total

Error (%)

+6.67/-6.8

Recommended Max

Receiver Error (%)

± 3.0

8

9

6

7

10

94,12

94,81

95,36

95,81

96,17

105,79

105,11

104,58

104,14

103,78

+5.79/-5.88

+5.11/-5.19

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

± 2.0

± 2.0

± 2.0

± 1.5

± 1.5

Table 54. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X =

1)

D#

(Data+Parity Bit) R slow

(%) R fast

(%)

5 94,12 105,66

Max Total

Error (%)

+5.66/-5.88

Recommended Max

Receiver Error (%)

± 2.5

8

9

6

7

10

94,92

95,52

96,00

96,39

96,70

104,92

104,35

103,90

103,53

103,23

+4.92/-5.08

+4.35/-4.48

+3.90/-4.00

+3.53/-3.61

+3.23/-3.30

± 2.0

± 1.5

± 1.5

± 1.5

± 1.0

The recommendations of the maximum Receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error.

There are two possible sources for the Receivers Baud Rate error. The Receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the temperature range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible.

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Multi-processor

Communication

Mode

Using MPCM

Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCM setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several Slave MCUs to receive data from a

Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other Slave MCUs will ignore the received frames until another address frame is received.

For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ = 7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame

(TXB = 0) is being transmitted. The Slave MCUs must in this case be set to use a 9-bit character frame format.

The following procedure should be used to exchange data in Multi-processor Communication mode:

1.

All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set).

2.

The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal.

3.

Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting.

4.

The addressed MCU will receive all data frames until a new address frame is received.

The other Slave MCUs, which still have the MPCM bit set, will ignore the data frames.

5.

When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCM bit and waits for a new address frame from Master. The process then repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using n and n+1 character frame formats. This makes fullduplex operation difficult since the Transmitter and Receiver uses the same character size setting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit

(USBS = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The

MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions.

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Accessing

UBRRH/UCSRC

Registers

Write Access

The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location.

When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC setting will be updated.

The following code examples show how to access the two registers.

Assembly Code Examples

(1)

...

; Set UBRRH to 2

ldi

r16,0x02

out

UBRRH,r16

...

; Set the USBS and the UCSZ1 bit to one, and

; the remaining bits to zero.

ldi

r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)

out

UCSRC,r16

...

C Code Examples

(1)

...

/* Set UBRRH to 2 */

UBRRH = 0x02;

...

/* Set the USBS and the UCSZ1 bit to one, and */

/* the remaining bits to zero. */

UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);

...

Note:

1. See “About Code Examples” on page 8.

As the code examples illustrate, write accesses of the two registers are relatively unaffected of the sharing of I/O location.

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Read Access

Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers.

The read access is controlled by a timed sequence. Reading the I/O location once returns the

UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents. Note that the timed sequence for reading the UCSRC is an atomic operation. Interrupts must therefore be controlled

(e.g., by disabling interrupts globally) during the read operation.

The following code example shows how to read the UCSRC Register contents.

Assembly Code Example

(1)

USART_ReadUCSRC:

; Read UCSRC

in

r16,UBRRH

in

r16,UCSRC

ret

C Code Example

(1)

unsigned char

USART_ReadUCSRC( void )

{

unsigned char

ucsrc;

/* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc;

}

Note:

1. See “About Code Examples” on page 8.

The assembly code example returns the UCSRC value in r16.

Reading the UBRRH contents is not an atomic operation and therefore it can be read as an ordinary register, as long as the previous instruction did not access the register location.

USART Register

Description

USART I/O Data

Register – UDR

Bit

Read/Write

Initial Value

7

R/W

0

6

R/W

0

5

R/W

0

4 3

R/W

0

RXB[7:0]

TXB[7:0]

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

UDR (Read)

UDR (Write)

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location. Reading the

UDR Register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When

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data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-

Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions

(SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and

Status Register A –

UCSRA

Bit

Read/Write

Initial Value

7

RXC

R

0

6

TXC

R/W

0

5

UDRE

R

1

4

FE

R

0

3

DOR

R

0

2

PE

R

0

1

U2X

R/W

0

0

MPCM

R/W

0

UCSRA

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e. does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC bit will become zero. The RXC Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR). The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see description of the TXCIE bit).

• Bit 5 – UDRE: USART Data Register Empty

The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data

Register Empty interrupt (see description of the UDRIE bit).

UDRE is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received (i.e., when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 2 – PE: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer

(UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART transmission speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.

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Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

• Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed

information see “Multi-processor Communication Mode” on page 151

.

USART Control and

Status Register B –

UCSRB

Bit

Read/Write

Initial Value

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

UCSZ2

R/W

0

1

RXB8

R

0

0

TXB8

R/W

0

UCSRB

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set.

• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE, DOR and PE Flags.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the

Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted).

When disabled, the Transmitter will no longer override the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR.

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USART Control and

Status Register C –

UCSRC

Bit

Read/Write

Initial Value

7 6

URSEL UMSEL

R/W

1

R/W

0

5

UPM1

R/W

0

4

UPM0

R/W

0

3

USBS

R/W

0

2

UCSZ1

R/W

1

1

UCSZ0

R/W

1

0

UCPOL

R/W

0

UCSRC

The UCSRC Register shares the same I/O location as the UBRRH Register. See the

“Accessing

UBRRH/UCSRC Registers” on page 152

section which describes how to access this register.

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between Asynchronous and Synchronous mode of operation.

Table 55. UMSEL Bit Settings

UMSEL Mode

0

1

Asynchronous Operation

Synchronous Operation

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• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.

If a mismatch is detected, the PE Flag in UCSRA will be set.

Table 56. UPM Bits Settings

UPM1 UPM0

1

1

0

0

0

1

0

1

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the trAnsmitter. The Receiver ignores this setting.

Table 57. USBS Bit Settings

USBS

0

1

Stop Bit(s)

1-bit

2-bit

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use.

Table 58. UCSZ Bits Settings

UCSZ2 UCSZ1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

UCSZ0

0

1

0

1

0

1

0

1

Character Size

5-bit

6-bit

7-bit

8-bit

Reserved

Reserved

Reserved

9-bit

• Bit 0 – UCPOL: Clock Polarity

157

This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).

Table 59. UCPOL Bit Settings

UCPOL

0

Transmitted Data Changed (Output of

TxD Pin)

Rising XCK Edge

1 Falling XCK Edge

Received Data Sampled (Input on

RxD Pin)

Falling XCK Edge

Rising XCK Edge

USART Baud Rate

Registers – UBRRL and UBRRHs

Bit

Read/Write

Initial Value

15

URSEL

7

R/W

R/W

0

0

14

6

R

R/W

0

0

13

5

R

R/W

0

0

R

R/W

0

0

12

11

4

UBRR[7:0]

3

R/W

R/W

0

0

10 9

UBRR[11:8]

2

R/W

R/W

0

0

1

R/W

R/W

0

0

8

0

R/W

R/W

0

0

UBRRH

UBRRL

The UBRRH Register shares the same I/O location as the UCSRC Register. See the

“Accessing

UBRRH/UCSRC Registers” on page 152

section which describes how to access this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.

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Examples of Baud

Rate Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-

chronous operation can be generated by using the UBRR settings in Table 60

. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see

“Asynchronous Operational

Range” on page 149

). The error values are calculated using the following equation:

Error[%]

=

BaudRate

--------------------------------------------------------

BaudRate

1

100%

Table 60. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

f osc

= 1.0000 MHz

U2X = 0 U2X = 1 f osc

= 1.8432 MHz

U2X = 0 U2X = 1

Baud

Rate

(bps)

2400

UBRR

25

Error

0.2%

UBRR

51

Error

0.2%

UBRR

47

Error

0.0%

UBRR

95

Error

0.0%

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

Max

(1)

0

1

1

12

6

3

2

62.5 kbps

0.2%

-7.0%

8.5%

8.5%

8.5%

-18.6%

8.5%

1

1

3

2

8

6

25

12

0

8.5%

125 kbps

0.2%

0.2%

-3.5%

-7.0%

8.5%

8.5%

8.5%

-18.6%

1

1

3

2

23

11

7

5

0

0.0%

– –

115.2 kbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

-25.0%

3

2

7

5

47

23

15

11

1

0

0.0%

0.0%

– –

230.4 kbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

1.

UBRR = 0, Error = 0.0%

25

12

8

6

f osc

= 2.0000 MHz

U2X = 0 U2X = 1

UBRR

51

Error

0.2%

UBRR

103

Error

0.2%

0.2%

0.2%

-3.5%

-7.0%

51

25

16

12

0.2%

0.2%

2.1%

0.2%

1

1

3

2

8.5%

8.5%

8.5%

-18.6%

0

8.5%

-

125 kbps

8

6

3

2

1

0

-3.5%

-7.0%

8.5%

8.5%

8.5%

0.0%

250 kbps

159

2486W–AVR–02/10

Table 61. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps) f osc

= 3.6864 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error f osc

= 4.0000 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error f osc

= 7.3728 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

11

7

5

3

95

47

23

15

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

76.8k

115.2k

230.4k

250k

2

1

0

0

0.0%

0.0%

0.0%

-7.8%

1.

0.5M

1M

Max

(1)

230.4 kbps

UBRR = 0, Error = 0.0%

23

15

11

7

191

95

47

31

1

1

5

3

0.0%

0.0%

0.0%

-7.8%

0

-7.8%

460.8 kbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

12

8

6

3

103

51

25

16

0

0

2

1

8.5%

8.5%

8.5%

0.0%

250 kbps

0.2%

0.2%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

25

16

12

8

207

103

51

34

1

1

6

3

-7.0%

8.5%

8.5%

0.0%

0

0.0%

0.5 Mbps

0.2%

0.2%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

23

15

11

7

191

95

47

31

1

1

5

3

0.0%

0.0%

0.0%

-7.8%

0

-7.8%

460.8 kbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

47

31

23

15

383

191

95

63

11

7

3

3

0.0%

0.0%

0.0%

-7.8%

1

0

-7.8%

-7.8%

921.6 kbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

160

ATmega8(L)

2486W–AVR–02/10

ATmega8(L)

Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps) f osc

= 8.0000 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error f osc

=

11.0592

MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error f osc

= 14.7456 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

25

16

12

8

207

103

51

34

0.2%

0.2%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

76.8k

115.2k

230.4k

250k

6

3

1

1

-7.0%

8.5%

8.5%

0.0%

12

8

3

3

1.

0.5M

1M

Max

(1)

0

0.0%

1

0

0.5 Mbps

UBRR = 0, Error = 0.0%

1 Mbps

51

34

25

16

416

207

103

68

0.2%

-3.5%

8.5%

0.0%

0.0%

0.0%

-0.1%

0.2%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

35

23

17

11

287

143

71

47

2

2

8

5

691.2 kbps

0.0%

0.0%

0.0%

-7.8%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

71

47

35

23

575

287

143

95

17

11

5

5

0.0%

0.0%

0.0%

-7.8%

2

1.3824 Mbps

-7.8%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

47

31

23

15

383

191

95

63

11

7

3

3

0.0%

0.0%

0.0%

-7.8%

1

0

921.6 kbps

-7.8%

-7.8%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

95

63

47

31

767

383

191

127

23

15

7

6

0.0%

0.0%

0.0%

5.3%

3

1

1.8432 Mbps

-7.8%

-7.8%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

161

2486W–AVR–02/10

Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps) f osc

= 16.0000 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error f osc

= 18.4320 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error f osc

= 20.0000 MHz

U2X = 0 U2X = 1

UBRR Error UBRR Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

51

34

25

16

416

207

103

68

-0.1%

0.2%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

103

68

51

34

832

416

207

138

76.8k

115.2k

230.4k

250k

12

8

3

3

0.2%

-3.5%

8.5%

0.0%

1.

0.5M

1M

Max

(1)

1

0

0.0%

0.0%

1 Mbps

UBRR = 0, Error = 0.0%

8

7

25

16

0.2%

2.1%

-3.5%

0.0%

3

1

0.0%

0.0%

2 Mbps

0.0%

-0.1%

0.2%

-0.1%

0.2%

0.6%

0.2%

-0.8%

59

39

29

19

479

239

119

79

14

9

4

4

0.0%

0.0%

0.0%

-7.8%

1.152 Mbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

119

79

59

39

959

479

239

159

29

19

9

8

0.0%

0.0%

0.0%

2.4%

4

-7.8%

2.304 Mbps

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

64

42

32

21

520

259

129

86

15

10

4

4

1.7%

-1.4%

8.5%

0.0%

1.25 Mbps

0.0%

0.2%

0.2%

-0.2%

0.2%

0.9%

-1.4%

-1.4%

1041

520

259

173

129

86

64

42

32

21

10

9

-1.4%

-1.4%

-1.4%

0.0%

4

2.5 Mbps

0.0%

0.0%

0.0%

0.2%

-0.2%

0.2%

-0.2%

0.2%

0.9%

162

ATmega8(L)

2486W–AVR–02/10

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