ATMEGA8L-8MU-T скачать даташит

ATMEGA8L-8MU-T скачать даташит

Memory

Programming

Program And Data

Memory Lock Bits

The ATmega8 provides six Lock Bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in

Table 86

. The Lock Bits can only be erased to “1” with the Chip Erase command.

Table 85. Lock Bit Byte

Lock Bit Byte Bit No.

7

6

Description

Default Value

(1)

1 (unprogrammed)

1 (unprogrammed)

BLB12

BLB11

BLB02

BLB01

5

4

3

2

Boot lock bit

Boot lock bit

Boot lock bit

Boot lock bit

1 (unprogrammed)

1 (unprogrammed)

1 (unprogrammed)

1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit

Note: 1. “1” means unprogrammed, “0” means programmed

1 (unprogrammed)

Table 86. Lock Bit Protection Modes

(2)

Memory Lock Bits Protection Type

LB Mode

1

LB2

1

LB1

1

2

3

1

0

0

0

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The

Fuse Bits are locked in both Serial and Parallel

Programming mode.

(1)

Further programming and verification of the Flash and

EEPROM is disabled in parallel and Serial Programming mode. The Fuse Bits are locked in both Serial and Parallel

Programming modes.

(1)

BLB0 Mode BLB02 BLB01

1

2

3

4

1

1

0

0

1

0

0

1

No restrictions for SPM or LPM accessing the Application section.

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and

LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.

LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.

BLB1 Mode BLB12 BLB11

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Fuse Bits

ATmega8(L)

Table 86. Lock Bit Protection Modes

(2)

(Continued)

Memory Lock Bits Protection Type

1

2

3

1

1

0

1

0

0

No restrictions for SPM or LPM accessing the Boot Loader section.

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.

4 0 1

LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.

Notes: 1. Program the Fuse Bits before programming the Lock Bits.

2. “1” means unprogrammed, “0” means programmed

The ATmega8 has two fuse bytes.

Table 87

and

Table 88 describe briefly the functionality of all

the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.

Table 87. Fuse High Byte

Fuse High

Byte

Bit

No.

Description

RSTDISBL

(4)

7

Select if PC6 is I/O pin or RESET pin

Default Value

1 (unprogrammed, PC6 is

RESET-pin)

WDTON 6

WDT always on

1 (unprogrammed, WDT enabled by WDTCR)

SPIEN

(1)

5

Enable Serial Program and Data

Downloading

0 (programmed, SPI prog. enabled)

CKOPT

(2)

EESAVE

4

3

Oscillator options

EEPROM memory is preserved through the Chip Erase

1 (unprogrammed)

1 (unprogrammed,

EEPROM not preserved)

BOOTSZ1 2

Select Boot Size (see Table 82

for details)

Select Boot Size (see Table 82

for details)

0 (programmed)

(3)

BOOTSZ0 1

0 (programmed)

(3)

BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Notes: 1. The SPIEN Fuse is not accessible in Serial Programming mode.

2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits, see “Clock Sources” on page 26 for details.

3. The default value of BOOTSZ1..0 results in maximum Boot Size. See

Table 82 on page 220 .

4. When programming the RSTDISBL Fuse Parallel Programming has to be used to change fuses or perform further programming.

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Latching of Fuses

Table 88. Fuse Low Byte

Fuse Low

Byte

BODLEVEL

Bit

No.

7

Description Default Value

Brown out detector trigger level 1 (unprogrammed)

BODEN

SUT1

SUT0

6

5

4

Brown out detector enable

Select start-up time

Select start-up time

1 (unprogrammed, BOD disabled)

1 (unprogrammed)

(1)

0 (programmed)

(1)

CKSEL3

CKSEL2

3

2

Select Clock source

Select Clock source

0 (programmed)

(2)

0 (programmed)

(2)

CKSEL1 1 Select Clock source

0 (programmed)

(2)

CKSEL0 0 Select Clock source 1 (unprogrammed)

(2)

Notes:

1. The default value of SUT1..0 results in maximum start-up time. See Table 10 on page 30 for

details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 1MHz. See

Table 2 on page 26 for details.

The status of the Fuse Bits is not affected by Chip Erase. Note that the Fuse Bits are locked if lock bit1 (LB1) is programmed. Program the Fuse Bits before programming the Lock Bits.

The fuse values are latched when the device enters Programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

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ATmega8(L)

Signature Bytes

Calibration Byte

All Atmel microcontrollers have a 3-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked. The three bytes reside in a separate address space.

For the ATmega8 the signature bytes are:

1.

0x000: 0x1E (indicates manufactured by Atmel).

2.

0x001: 0x93 (indicates 8KB Flash memory).

3.

0x002: 0x07 (indicates ATmega8 device).

The ATmega8 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row High byte of the addresses 0x0000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 Mhz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded

manually, see “Oscillator Calibration Register – OSCCAL” on page 31 for details.

Page Size

Table 89. No. of Words in a Page and no. of Pages in the Flash

Flash Size

4K words (8K bytes)

Page Size PCWORD

32 words PC[4:0]

No. of Pages

128

PCPAGE

PC[11:5]

PCMSB

11

Table 90. No. of Words in a Page and no. of Pages in the EEPROM

EEPROM Size

512 bytes

Page Size

4 bytes

PCWORD

EEA[1:0]

No. of Pages

128

PCPAGE

EEA[8:2]

EEAMSB

8

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Parallel

Programming

Parameters, Pin

Mapping, and

Commands

Signal Names

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock Bits, and Fuse Bits in the ATmega8. Pulses are assumed to be at least 250 ns unless otherwise noted.

In this section, some pins of the ATmega8 are referenced by signal names describing their func-

tionality during parallel programming, see Figure 104 and Table 91 . Pins not described in the

following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 93

.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in

Table 94 .

Figure 104. Parallel Programming

RDY/BSY

OE

WR

BS1

XA0

XA1

PAGEL

+12 V

BS2

+5V

PD1

PD2

VCC

PD3

AVCC

PD4

PC[1:0]:PB[5:0]

PD5

PD6

PD7

RESET

PC2

XTAL1

GND

+5V

DATA

Table 91. Pin Name Mapping

Signal Name in

Programming Mode Pin Name

RDY/BSY

OE

WR

BS1

XA0

XA1

PD1

PD2

PD3

PD4

PD5

PD6

I/O Function

O

0: Device is busy programming, 1: Device is ready for new command

I Output Enable (Active low)

I

I Write Pulse (Active low)

Byte Select 1 (“0” selects Low byte, “1” selects High byte)

I XTAL Action Bit 0

I XTAL Action Bit 1

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ATmega8(L)

Table 91. Pin Name Mapping (Continued)

Signal Name in

Programming Mode

PAGEL

BS2

DATA

Pin Name

PD7

PC2

{PC[1:0]: PB[5:0]}

I/O Function

I

Program memory and EEPROM Data

Page Load

I

I/O

Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte)

Bi-directional Data bus (Output when OE is low)

Table 92. Pin Values used to Enter Programming Mode

Pin Symbol

PAGEL

XA1

XA0

BS1

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

Value

0

0

0

0

Table 93. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1)

0

1

1

1

0

1

Load Data (High or Low data byte for Flash determined by BS1)

Load Command

No Action, Idle

Table 94. Command Byte Bit Coding

Command Byte Command Executed

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Chip Erase

Write Fuse Bits

Write Lock Bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock Bits

Read Flash

Read EEPROM

227

Parallel

Programming

Enter Programming

Mode

The following algorithm puts the device in Parallel Programming mode:

1.

Apply 4.5 - 5.5V between V

CC

and GND, and wait at least 100 µs.

2.

Set RESET to “0” and toggle XTAL1 at least 6 times

3.

Set the Prog_enable pins listed in Table 92 on page 227 to “0000” and wait at least 100

ns.

4.

Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Programming mode.

Note, if the RESET pin is disabled by programming the RSTDISBL Fuse, it may not be possible to follow the proposed algorithm above. The same may apply when External Crystal or External

RC configuration is selected because it is not possible to apply qualified XTAL1 pulses. In such cases, the following algorithm should be followed:

1.

Set Prog_enable pins listed in

Table 92 on page 227 to “0000”.

2.

Apply 4.5 - 5.5V between V

CC

and GND simultaneously as 11.5 - 12.5V is applied to

RESET.

3.

Wait 100 ns.

4.

Re-program the fuses to ensure that External Clock is selected as clock source

(CKSEL3:0 = 0’b0000) and RESET pin is activated (RSTDISBL unprogrammed). If Lock

Bits are programmed, a chip erase command must be executed before changing the fuses.

5.

Exit Programming mode by power the device down or by bringing RESET pin to 0’b0.

6.

Entering Programming mode with the original algorithm, as described above.

Considerations for

Efficient Programming

The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.

Chip Erase

The Chip Erase will erase the Flash and EEPROM

(1)

memories plus Lock Bits. The Lock Bits are

not reset until the Program memory has been completely erased. The Fuse Bits are not changed. A Chip Erase must be performed before the Flash and/or the EEPROM are reprogrammed.

Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is programmed.

Load Command “Chip Erase”

1.

Set XA1, XA0 to “10”. This enables command loading.

2.

Set BS1 to “0”.

3.

Set DATA to “1000 0000”. This is the command for Chip Erase.

4.

Give XTAL1 a positive pulse. This loads the command.

5.

Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6.

Wait until RDY/BSY goes high before loading a new command.

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Programming the

Flash

ATmega8(L)

The Flash is organized in pages, see

Table 89 on page 225 . When programming the Flash, the

program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory:

A. Load Command “Write Flash”

1.

Set XA1, XA0 to “10”. This enables command loading.

2.

Set BS1 to ”0”.

3.

Set DATA to “0001 0000”. This is the command for Write Flash.

4.

Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1.

Set XA1, XA0 to “00”. This enables address loading.

2.

Set BS1 to “0”. This selects low address.

3.

Set DATA = Address Low byte (0x00 - 0xFF).

4.

Give XTAL1 a positive pulse. This loads the address Low byte.

C. Load Data Low byte

1.

Set XA1, XA0 to “01”. This enables data loading.

2.

Set DATA = Data Low byte (0x00 - 0xFF).

3.

Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High byte

1.

Set BS1 to “1”. This selects high data byte.

2.

Set XA1, XA0 to “01”. This enables data loading.

3.

Set DATA = Data High byte (0x00 - 0xFF).

4.

Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1.

Set BS1 to “1”. This selects high data byte.

2.

Give PAGEL a positive pulse. This latches the data bytes. (See

Figure 106 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in

Figure 105 on page 230 . Note that if less than

eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address Low byte are used to address the page when performing a page write.

G. Load Address High byte

1.

Set XA1, XA0 to “00”. This enables address loading.

2.

Set BS1 to “1”. This selects high address.

3.

Set DATA = Address High byte (0x00 - 0xFF).

4.

Give XTAL1 a positive pulse. This loads the address High byte.

H. Program Page

1.

Set BS1 = “0”

2.

Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.

3.

Wait until RDY/BSY goes high. (See

Figure 106

for signal waveforms)

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I. Repeat B through H until the entire Flash is programmed or until all data has been programmed.

J. End Page Programming

1.

Set XA1, XA0 to “10”. This enables command loading.

2.

Set DATA to “0000 0000”. This is the command for No Operation.

3.

Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.

Figure 105. Addressing the Flash which is Organized in Pages

(1)

PROGRAM

COUNTER

PCMSB

PCPAGE

PAGEMSB

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note: 1. PCPAGE and PCWORD are listed in

Table 89 on page 225 .

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Programming the

EEPROM

ATmega8(L)

Figure 106. Programming the Flash Waveforms

(1)

F

A

0x10

B C D

ADDR. LOW DATA LOW DATA HIGH

E

XX

B C D

ADDR. LOW DATA LOW DATA HIGH

E

XX

G

ADDR. HIGH

H

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note: 1. “XX” is don’t care. The letters refer to the programming description above.

The EEPROM is organized in pages, see

Table 90 on page 225

. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to

“Programming the Flash” on page 229

for details on Command, Address and

Data loading):

1.

A: Load Command “0001 0001”.

2.

G: Load Address High byte (0x00 - 0xFF).

3.

B: Load Address Low byte (0x00 - 0xFF).

4.

C: Load Data (0x00 - 0xFF).

5.

E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page.

1.

Set BS1 to “0”.

2.

Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.

3.

Wait until to RDY/BSY goes high before programming the next page.

(See Figure 107

for signal waveforms).

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Figure 107. Programming the EEPROM Waveforms

K

A

0x11

G B

ADDR. HIGH ADDR. LOW

C E

DATA

XX

B

ADDR. LOW

C

DATA XX

E L

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

DATA

XA1

XA0

BS1

Reading the Flash

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to

“Programming the Flash” on page 229 for details on Command and Address loading):

1.

A: Load Command “0000 0011”.

2.

G: Load Address High byte (0x00 - 0xFF).

3.

B: Load Address Low byte (0x00 - 0xFF).

4.

Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5.

Set OE to “1”.

Programming the

Fuse Low Bits

The algorithm for reading the Flash memory is as follows (refer to

“Programming the Flash” on page 229

for details on Command and Address loading):

1.

A: Load Command “0000 0010”.

2.

G: Load Address High byte (0x00 - 0xFF).

3.

B: Load Address Low byte (0x00 - 0xFF).

4.

Set OE to “0”, and BS1 to “0”. The Flash word Low byte can now be read at DATA.

5.

Set BS1 to “1”. The Flash word High byte can now be read at DATA.

6.

Set OE to “1”.

The algorithm for programming the Fuse Low bits is as follows (refer to

“Programming the Flash” on page 229 for details on Command and Data loading):

1.

A: Load Command “0100 0000”.

2.

C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3.

Set BS1 and BS2 to “0”.

4.

Give WR a negative pulse and wait for RDY/BSY to go high.

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ATmega8(L)

Programming the

Fuse High Bits

The algorithm for programming the Fuse high bits is as follows (refer to

“Programming the Flash” on page 229 for details on Command and Data loading):

1.

A: Load Command “0100 0000”.

2.

C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3.

Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4.

Give WR a negative pulse and wait for RDY/BSY to go high.

5.

Set BS1 to “0”. This selects low data byte.

Programming the Lock

Bits

The algorithm for programming the Lock Bits is as follows (refer to “Programming the Flash” on page 229

for details on Command and Data loading):

1.

A: Load Command “0010 0000”.

2.

C: Load Data Low byte. Bit n = “0” programs the Lock bit.

3.

Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock Bits can only be cleared by executing Chip Erase.

Reading the Fuse and

Lock Bits

The algorithm for reading the Fuse and Lock Bits is as follows (refer to “Programming the Flash” on page 229 for details on Command loading):

1.

A: Load Command “0000 0100”.

2.

Set OE to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed).

3.

Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed).

4.

Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock Bits can now be read at

DATA (“0” means programmed).

5.

Set OE to “1”.

Figure 108. Mapping Between BS1, BS2 and the Fuse- and Lock Bits During Read

Fuse low byte 0

DATA

Lock bits

0

1

Fuse high byte

1

BS2

BS1

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Reading the Signature

Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 229

for details on Command and Address loading):

1.

A: Load Command “0000 1000”.

2.

B: Load Address Low byte (0x00 - 0x02).

3.

Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.

4.

Set OE to “1”.

Reading the

Calibration Byte

The algorithm for reading the Calibration bytes is as follows (refer to

“Programming the Flash” on page 229

for details on Command and Address loading):

1.

A: Load Command “0000 1000”.

2.

B: Load Address Low byte, (0x00 - 0x03).

3.

Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.

Set OE to “1”.

Parallel Programming

Characteristics

Figure 109. Parallel Programming Timing, Including some General Timing Requirements t

XLWL

XTAL1 t

XHXL t

DVXH t

XLDX

Data & Contol

(DATA, XA0/1, BS1, BS2) t

BVPH t

PLBX t

BVWL t

WLBX

PAGEL t

PHPL t

WL WH

WR t

PLWL

WLRL

RDY/BSY t

WLRH

Figure 110. Parallel Programming Timing, Loading Sequence with Timing Requirements

(1)

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE) t

XLXH t

XLPH t

PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 109

(i.e., t

DVXH ing operation.

, t

XHXL

, and t

XLDX

) also apply to load-

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ATmega8(L)

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ATmega8(L)

Figure 111. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements

(1)

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE) t

XLOL

XTAL1 t

BVDV

BS1 t

OLDV

OE t

OHDZ

DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 109

(i.e., t

DVXH

, t ing operation.

XHXL

, and t

XLDX

) also apply to read-

Table 95. Parallel Programming Characteristics, V

CC

= 5V ± 10%

Symbol Parameter Min Typ Max Units

t

PLXH t

BVPH t

PHPL t

PLBX t

WLBX t

PLWL t

BVWL t

WLWH

V

PP

I

PP t

DVXH t

XLXH t

XHXL t

XLDX t

XLWL t

XLPH t

WLRL t

WLRH t

WLRH_CE t

XLOL

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

BS1 Valid to WR Low

WR Pulse Width Low

WR Low to RDY/BSY Low

WR Low to RDY/BSY High

(1)

WR Low to RDY/BSY High for Chip Erase

(2)

XTAL1 Low to OE Low

11.5

67

150

0

3.7

150

67

67

67

7.5

0

0

0

150

67

67

200

150

67

12.5

250

1

4.5

9 ns ns ns ns

μs ms ms ns ns ns ns ns ns ns ns ns

V

μA ns ns

235

Table 95. Parallel Programming Characteristics, V

CC

= 5V ± 10% (Continued)

Symbol Parameter Min Typ Max Units

t

BVDV t

OLDV

BS1 Valid to DATA valid

OE Low to DATA Valid

0 250

250 ns ns t

OHDZ

OE High to DATA Tri-stated

Notes: 1. t

WLRH

250 ns is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands.

2. t

WLRH_CE is valid for the Chip Erase command.

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ATmega8(L)

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ATmega8(L)

Serial

Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in

Table 96 on page 237

, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

Serial

Programming Pin

Mapping

Table 96. Pin Mapping Serial Programming

Symbol Pins I/O

MOSI

MISO

SCK

PB3

PB4

PB5

I

O

I

Figure 112. Serial Programming and Verify

(1)

Description

Serial data in

Serial data out

Serial clock

MOSI

MISO

SCK

PB3

PB4

PB5

XTAL1

+2.7 - 5.5V

VCC

+2.7 - 5.5V

(2)

AVCC

RESET

GND

Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V

CC

- 0.3 <

AV

CC

< V

CC

+ 0.3, however,

AV

CC

should always be within 2.7 - 5.5V.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the Serial Clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f ck

< 12 MHz, 3 CPU clock cycles for f ck

12 MHz

High:> 2 CPU clock cycles for f ck

< 12 MHz, 3 CPU clock cycles for f ck

12 MHz

237

2486W–AVR–02/10

Serial Programming

Algorithm

When writing serial data to the ATmega8, data is clocked on the rising edge of SCK.

When reading data from the ATmega8, data is clocked on the falling edge of SCK. See

Figure

113 for timing details.

To program and verify the ATmega8 in the Serial Programming mode, the following sequence is

recommended (See four byte instruction formats in Table 98

):

1.

Power-up sequence:

Apply power between V

CC

and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.

Wait for at least 20 ms and enable Serial Programming by sending the Programming

Enable serial instruction to pin MOSI.

3.

The Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.

The Flash is programmed one page at a time. The page size is found in

Table 89 on page 225 . The memory page is loaded one byte at a time by supplying the 5 LSB of the

address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program memory Page is stored by loading the Write

Program memory Page instruction with the 7 MSB of the address. If polling is not used, the user must wait at least t

WD_FLASH

before issuing the next page. (See Table 97 ).

Note: If other commands than polling (read) are applied before any write operation (FLASH,

EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming.

5.

The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least t

WD_EEPROM

before issuing the next byte. (See Table 97 on page 239 ). In a chip

erased device, no 0xFFs in the data file(s) need to be programmed.

6.

Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.

At the end of the programming session, RESET can be set high to commence normal operation.

8.

Power-off sequence (if needed):

Set RESET to “1”.

Turn V

CC

power off

Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least t

WD_FLASH

before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 97 for t

WD_FLASH

value.

Data Polling EEPROM

When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for

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ATmega8(L)

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2486W–AVR–02/10

ATmega8(L)

a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is Re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value

0xFF, and the user will have to wait at least t

WD_EEPROM

Table 97 for t

WD_EEPROM

value.

before programming the next byte. See

Table 97. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

t

WD_FUSE t

WD_FLASH t

WD_EEPROM t

WD_ERASE

4.5 ms

4.5 ms

9.0 ms

9.0 ms

Figure 113. Serial Programming Waveforms

SERIAL DATA INPUT

(MOSI)

MSB LSB

SERIAL DATA OUTPUT

(MISO)

SERIAL CLOCK INPUT

(SCK)

SAMPLE

MSB LSB

239

Table 98. Serial Programming Instruction Set

Instruction

Programming Enable

Byte 1

1010 1100

Instruction Format

Byte 2

0101 0011

Byte 3

xxxx xxxx

Chip Erase

Read Program Memory

1010 1100

0010 H000

100x xxxx

0000 aaaa xxxx xxxx

bbbb bbbb

Load Program Memory

Page

Write Program Memory

Page

Read EEPROM Memory

Write EEPROM Memory

Read Lock Bits

Write Lock Bits

Read Signature Byte

Write Fuse Bits

Write Fuse High Bits

Read Fuse Bits

Read Fuse High Bits

0100 H000 0000 xxxx xxxb bbbb

0100 1100

1010 0000

1100 0000

0101 1000

0000 aaaa

00xx xxxa

00xx xxxa

0000 0000

bbbx xxxx

bbbb bbbb bbbb bbbb

xxxx xxxx

1010 1100 111x xxxx xxxx xxxx

0011 0000

1010 1100

00xx xxxx

1010 0000 xxxx xxbb xxxx xxxx

1010 1100 1010 1000 xxxx xxxx

0101 0000 0000 0000 xxxx xxxx

0101 1000 0000 1000 xxxx xxxx

Read Calibration Byte

0011 1000

Note: a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High byte

o = data out

i = data in x = don’t care

00xx xxxx 0000 00bb

Byte4 Operation

xxxx xxxx

Enable Serial Programming after

RESET goes low.

xxxx xxxx

Chip Erase EEPROM and Flash.

oooo oooo

Read H (high or low) data o from

Program memory at word address

a:b.

iiii iiii

Write H (high or low) data i to

Program memory page at word address b. Data Low byte must be loaded before Data High byte is applied within the same address.

xxxx xxxx

Write Program memory Page at address a:b.

oooo oooo

Read data o from EEPROM memory at address a:b.

iiii iiii

Write data i to EEPROM memory at address a:b.

xxoo oooo

Read Lock Bits. “0” = programmed,

“1” = unprogrammed. See

Table

85 on page 222

for details.

11ii iiii

Write Lock Bits. Set bits = “0” to program Lock Bits. See

Table 85 on page 222

for details.

oooo oooo

Read Signature Byte o at address

b.

iiii iiii

Set bits = “0” to program, “1” to unprogram. See

Table 88 on page 224

for details.

iiii iiii

Set bits = “0” to program, “1” to unprogram. See

Table 87 on page 223

for details.

oooo oooo

Read Fuse Bits. “0” = programmed,

“1” = unprogrammed. See

Table

88 on page 224

for details.

oooo oooo

Read Fuse high bits. “0” = programmed, “1” = unprogrammed.

See

Table 87 on page 223

for details.

oooo oooo

Read Calibration Byte

240

ATmega8(L)

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SPI Serial

Programming

Characteristics

ATmega8(L)

For characteristics of the SPI module, see

“SPI Timing Characteristics” on page 246

.

2486W–AVR–02/10

241

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