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Micrel, Inc. KSZ8873MLL/FLL/RLL

The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate

(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors.

For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission.

The KSZ8873MLL/FLL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the

KSZ8873MLL/FLL. So, for PHY mode operation, if the device interfacing with the KSZ8873MLL/FLL has an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8873MLL/FLL has an

MTXER input pin, it also needs to be tied low.

The KSZ8873MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status. If the host is power down, pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2 will be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out.

Turbo MII Interface Operation

The switch MII interface also supports the turbo MII mode with 200Mbps rate (200Base-TX) by setting the register 2 bit[6]=1. When use the Turbo MII mode, the other side of the MII should also support 200Mbps rate. The Turbo MII can be configured to PHY mode or MAC mode by the configuration pins. In PHY mode, the pins SMTXC and SMRXC will be 50

MHz clock output. In MAC mode, the pins SMTXC and SMRXC should be 50 MHz clock input.

RMII Interface Operation

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

1. ports 10Mbps and 100Mbps data rates.

2. Uses a single 50 MHz clock reference (provided internally or externally).

3. Provides independent 2-bit wide (di-bit) transmit and receive data paths.

4. Contains two distinct groups of signals: one for transmission and the other for reception

When EN_REFCLKO_3 is high, KSZ8873RLL will output a 50MHz in REFCLKO_3. Register 198 bit[3] is used to select internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8873RLL will be provided by the KSZ8873RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the clock will provide to KSZ8873RLL via REFCLKI_3.

Note: If the reference clock is not provided by the KSZ8873RLL, this 50MHz reference clock has to be used in X1 pin instead of the 25MHz crystal since the clock skew of these two clock sources will impact on the RMII timing. The SPIQ clock selection strapping option pin is connected to low to select the 50MHz input.

0 0 External 50MHz OSC input to REFCLKI_3

Note

EN_REFCLKO_3 = 0 to Disable

REFCLKO_3 for better

EMI

0 1

1 1

1 0

Feedback to

REFCLKI_3

Internal Clock Source

REFCLKI_3 is unconnected to Enable

REFCLKO_3

EN_REFCLKO_3 = 1 to Enable

REFCLKO_3

Table 5. RMII Clock Setting

The RMII provided by the KSZ8873RLL is connected to the device’s third MAC. It complies with the RMII Specification.

The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal description.

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Micrel, Inc.

RMII

Signal Name

Direction

(with respect to the PHY)

Direction

(with respect to the MAC)

RMII

Signal Description

REF_CLK Input

Input or

Output

CRS_DV Output Input

RXD1

RXD0

Output

Output

Input

Input

Synchronous 50 MHz clock reference for receive, transmit and control interface

Carrier sense/

Receive data valid

Receive data bit 1

Receive data bit 0

TXD1

TXD0

Input

Input

Output

Output

Input

RX_ER Output

(not required)

Transmit data bit 1

Transmit data bit 0

Receive error

KSZ8873MLL/FLL/RLL

KSZ8873RLL

RMII Signal (direction)

REFCLKI_3 (input)

SMRXDV3 (output)

SMRXD31 (output)

SMRXD30 (output)

SMTXEN3 (input)

SMTXD31 (input)

SMTXD30 (input)

(not used)

SMTXER3* (input)

* Connects to RX_ER signal of RMII PHY device

Table 6. RMII Signal Description

The KSZ8873RLL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from

RMII PHY devices, the SMTXER3 input signal of the KSZ8873RLL is connected to the RXER output signal of the RMII

PHY device.

Collision detection is implemented in accordance with the RMII Specification.

In RMII mode, tie MII signals, SMTXD3[3:2] and SMTXER3, to ground if they are not used.

The KSZ8873RLL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8873RLL devices to be connected back-to-back. The following table shows the KSZ8873RLL RMII pin connections with an external RMII

PHY and an external RMII MAC, such as another KSZ8873RLL device.

KSZ8873RLL

PHY-MAC Connections

External

PHY Signals

KSZ8873RLL

MAC Signals

REF_CLK

TX_EN

TXD1

TXD0

Pin

Descriptions

KSZ8873RLL

MAC-MAC Connections

KSZ8873RLL

MAC Signals

External

MAC Signals

REFCLKI_3 Reference REFCLKI_3 REF_CLK

SMRXDV3

SMRXD31

SMRXD30

Carrier sense/

Receive data valid

Receive data bit 1

Receive data bit 0

SMRXDV3 CRS_DV

SMRXD31 RXD1

SMRXD30 RXD0

CRS_DV

RXD1

RXD0

RX_ER

SMTXEN3 Transmit SMTXEN3 TX_EN

SMTXD31

SMTXD30

Transmit data bit 1

Transmit data bit 0

SMTXD31 TXD1

SMTXD30 TXD0

(not used) (not used)

Table 7. RMII Signal Connections

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