SEMICONDUCTOR DATA. Kenwood TS-2000 X
The TS-2000 X is an all-mode multi-band transceiver that incorporates an IF/AF DSP for satellite communication. It also features an independent FM/AM sub-receiver for the VHF and UHF bands. The main band side has an independent front end for each of the HF, 50MHz, 144MHz, 430MHz and 1.2GHz bands. The sub-band receiver is not used during satellite operation, but it can receive signals while the main band receiver is sending a signal. In addition to the standard features of a transceiver, the TS-2000 X also includes features such as a noise blanker, a digital IF filter, and a digital AGC. It also has a speaker separation function that allows you to output the audio to two separate speakers or headphones. The TS-2000 X is a powerful and versatile transceiver that is suitable for a wide variety of applications, including satellite communication, HF and VHF/UHF operation, and contesting.
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TS-2000/X
SEMICONDUCTOR DATA
34
Main CPU : 64F2633xxxx (Control unit IC8)
■ Pin function
No.
Name I/O Function
30
31
32
33
26
27
28
29
39
40
41
34 PSW
35,36 NC
37
38
CLOCK
MRBK
SRBK
MABK
SABK
TXD2
RXD2
RES
Vss
BEEP
PCK
PDA
DATA
21
22
23
24
17
18
19
20
1
2
3,4
5~8
9
10
MD1
MD2
NC
HA0~HA3 O Address bus.
Vss
HA4
I Operation mode setting pin 1.
Connect to Vcc.
I Operation mode setting pin 2.
Connect to Vcc.
–
–
O
GND.
Address bus.
11 Vcc I 3.3V.
12~14 HA5~HA7 O Address bus.
15
16
Vss
ADC1
–
O
GND.
Analog switch control signal.
PVcc
ADC2
PSC
DASH
DOT
STSC
CKY
CTS2
I
O
O
I
I
O
O
I
5V.
Analog switch control signal.
Power relay control.
Electronic key dash signal.
Electronic key dot signal.
RS-232 IC start instruction.
Transmission power output specification.
UART operation instruction input from
25 RTS2 personal computer control.
O UART operation instruction output to personal computer control.
O Data output to PC/IF.
I Data input from PC/IF.
O Peripheral equipment reset input.
– GND.
O Beep pattern output to DSP.
O PLL unit common clock output.
O PLL unit common data output.
O Common data output.
I Power switch interrupt.
–
O Common clock output.
O Main RBK output.
O Sub RBK output.
O Main ABK output.
O Sub ABK output.
45
46
47
48
No.
42
43
44
Name I/O
DRES O
Function
DSP reset output.
ULK
12ULK I
I Main/sub common unlock signal.
1.2GHz band unlock signal.
DREN
ESCK
ESI
Vss
O
O
O
–
DRU-3 enable.
EEPROM clock output.
EEPROM data output.
GND.
59
60
61
49
50
HD0
PVcc
O Data bus.
I 5V.
51~57 HD1~HD7 O Data bus.
58 TXD0 O Data output to main unit panel.
RXD0
PVcc
START
I
I
I Data input from main unit panel.
5V. Power supply pin for pin 52~61.
Interrupt for returning from sleep mode.
(PC/mobile head)
78
79
80
81
82
62
63
64
65
Vss
TXD1
RXD1
BOVR
– GND.
O Data output to mobile head.
I Data input from mobile head.
I Over voltage detection interrupt.
72
73
74
75
66 TTO
67,68 NC
69
70
71
TSO
TTI
AMD
76
77
O
I
–
O
AT-300 control signal.
AT-300 control signal.
AT-300 control signal.
CSD2
CSD1
TSI
NC
I Amplitude comparison detection instruction input.
O
O
DSP control chip select 2
DSP control chip select 1.
I AT-300 control signal.
O
PLLVcc
PLLCAP I
I Internal PLL oscillator power 3.3V.
83
PLLVss
RESET
NMI
STBY
FWE
XTAL
I
I
I
– Internal PLL oscillator GND.
Hard reset input.
Normally H.
Hardware standby pin. Normally : H
I Flash light enable.
Normally : L, During writing : H
I Crystal oscillator 11.0592MHz.
TS-2000/X
SEMICONDUCTOR DATA
103
104
105
106
107
No.
84
85
86
Name I/O
Vcc I 3.3V.
EXTAL
Vss –
I
Function
Crystal oscillator 11.0592MHz.
GND.
87,88 NC
89 PVcc
90 PHD
I
I
I
3.3V.
Phase comparison detection instruction input.
91
92
93
94
95
96
97
98 FEN1
99,100 NC
101
102
Avcc
VREF
Vss
NC
HRD
– GND.
O
O External address space lead pin.
Normally : H
HWR O External space write strobe (D15~D8).
BACKUP I Voltage reduction interrupt.
WAIT
FEN2
I
O
Bus cycle wait state request.
Final serial-parallel enable 2 (AT).
O
–
I
I
Final serial-parallel enable 1 (LPF).
5V.
5V.
MSM
SSM
AXC
AYC
AZC
I Main SM voltage input.
I Sub SM voltage input.
I SW (VSF/MALT).
I SW (VSR/SALT).
I SW (MSQ/SMQ).
120
121
122
123
116
117
118
119
124
125
111
112
113
114
115
No.
108
109
110
126
127
128
Name I/O
BXC I
Function
SW (MPU/MDN/ALC/Reserve).
BYC I SW (THHF/THU/TH12/TEST).
PCHECK I Panel CPU connection check input signal.
DTDT
NAR
EOM
KYS
CTS0
I
I
I
I DTMF decoder data input.
VS-3 serial data input permission judgment.
DRU-3 message end judgment.
Key jack connection judgment.
KEY
PKSA
SS
AVss
LICS
LOCS
DTSTD
EDA
EEN
RST0
O Input latch control chip select.
O Output latch control chip select.
I
I
I
I UART operation instruction input from main unit panel.
I Key down instruction.
I Packet transmission instruction input.
–
PTT transmission instruction input.
GND.
DTMF decoder analysis end signal.
EEPROM data input.
O EEPROM enable.
O UART operation instruction output to
RXD3
TXD3
MD0 main unit panel.
I Data input from TNC.
O Data output to TNC.
I Operation mode setting pin 0.
Connect to Vss.
35
TS-2000/X
SEMICONDUCTOR DATA
20
21
22
23
MAB
RITA
RITB
MUL2
24
25
LOW2
HI2
26~28 –
29 CON
30
31
32
33
STA
9.6K
–
TXD0
34
35
RXD0
RTS0
36 CTS0
37~40 –
41~44 –
45 DIM
46 SRX
Panel CPU : 30624FGAGxxxxx (TX-RX 1 unit IC801)
■ Pin function
No.
Name I/O Function No.
1,2
5
6
3
4
7
8,9
10
11
12
13
14
15
16
17
18
19
KEY
–
–
–
LSUB
MULTI
–
RES
XOUT
Vss
XIN
Vcc
–
MUL1
LOW1
HI1
MAA
O Key illumination LED control signal.
– Pull up to Vcc.
O Sub LED control signal.
O Multi LED control signal.
– Vss connection.
– Pull down to Vss.
– Pull up to Vcc.
I Reset.
O System clock.
– Vss.
I System clock.
– Vcc.
– Pull up to Vcc.
I Multi/CH encoder interrupt port.
I Low encoder interrupt port.
I High encoder interrupt port.
I Main encoder A.
47
48
49
50
51
Name I/O
STX O
Function
Sub TX LED control signal.
MRX
MTX
52
53
54
55
FUNC
LINH
LMO
LCK
56
57
58
59
LDA
LCS1
LCS2
LCS3
60
61
62 Vss
63~65 –
LCS4
LCS5
Vcc
LRES
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
Main RX LED control signal.
Main TX LED control signal.
FUNC LED control signal.
LCD segment display off control output.
LCD driver control output.
Common clock output.
Common data output.
LDC (segment) driver 1 chip select output.
LCD (segment) driver 2 chip select output.
LCD (dot) driver chip select output.
Serial-parallel IC chip select output.
Reserve.
Vcc.
LCD driver reset control signal.
Vss.
Pull up to Vcc.
I Main encoder B.
I RIT encoder A.
I RIT encoder B.
I Multi/CH encoder data input.
I Low encoder data input.
I High encoder data input.
– Pull up to Vcc.
O CON LED control signal.
O STA LED control signal.
O 9.6K KED control signal.
– Pull down to Vss.
O UART data transmission port to main CPU.
I UART data reception port from main CPU.
O RTS output to main CPU.
I RTS input from main CPU.
– Pull down to Vss.
– Pull up to Vcc.
O LED dimmer control signal.
O Sub RX LED control signal.
92
93
94
95
88
89
90
91
66~70 S0~S4
71 PBKC
72
73
KC
KB
74 KA
75,76 –
77~86 K9~K0
87 SUBS
96
97
98~100 –
VREF
AVcc
MAF
MSQL
CWBC
MRF
SAF
SSQL
AVss
–
O Key scan output bit 0~4
I Backup processing start signal.
I Key input C.
I Key input B.
I Key input A.
– Pull up to Vcc.
I Key input 9~0.
I Sub on/off changover.
I Main AF.
I Main SQL.
I CW BC.
I Main RF.
I Sub AF.
I Sub SQL.
– Vss connection.
– Pull up to Vcc.
– ADC reference voltage. Vcc connection.
– ADC circuit power. Vcc connection.
– Pull up to Vcc.
36
TS-2000/X
SEMICONDUCTOR DATA
Extended I/O Port
■ Final unit (X45-360)
Pin No.
Port name Pin name
IC205 : BU2099FV, Enable : FEN1
Function
7
6
5
11
10
9
8
7
6
9
8
10
11
12
13
8
9
6
7
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
5 Q8
IC801 : UPD6345GS
12
11
Q1
Q2
FAN1
FAN2
ANT2
ATS
50RL
28RL
21RL
14RL
Low & High speed FAN1
High speed FAN2
HF ANT2 switching relay
In/Through switching relay
50M LPF relay
24/28M LPF relay
18/21M LPF relay
(10/) 14M LPF relay
14
15
16
17
Q8
Q9
Q10
Q11
10RL
7RL
4RL
2RL
(5 or 10M) LPF relay
7M LPF relay
3.5M LPF relay
1.8M LPF relay
IC803 : UPD6345GS, Enable : FEN2
12 Q1 L (1) 50M coil
11
10
Q2
Q3
L (2)
L (3)
28M coil
24.9M coil
L (4)
L (5)
L (6)
L (7)
L (8)
21M coil
14M coil
10M coil
7M coil
3.5M coil
10
9
8
7
6
5
Q3
Q4
Q5
Q6
Q7
Q8
IC802 : UPD6345GS
12 Q1
CI (1)
CI (2)
CI (3)
CI (4)
CI (5)
CI (6)
CI (7)
CI (8)
2.5p capacitor switching
5p capacitor switching
10p capacitor switching
18p capacitor switching
39p capacitor switching
75p capacitor switching
150p capacitor switching
300p capacitor switching
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CO (1)
CO (2)
CO (3)
CO (4)
CO (5)
CO (6)
CO (7)
CO (8)
2.5p capacitor switching
5p capacitor switching
10p capacitor switching
18p capacitor switching
39p capacitor switching
75p capacitor switching
150p capacitor switching
300p capacitor switching
Active level
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
30.0
≤
f
≤
60.0 (MHz)
25.50
≤
f < 30.0 (MHz)
21.50
≤
f < 25.50 (MHz)
14.50
≤
f < 21.50 (MHz)
10.50
≤
f < 14.50 (MHz)
7.50
≤
f < 10.50 (MHz)
4.70
≤
f < 7.50 (MHz)
2.50
≤
f < 4.70 (MHz)
Condition
K
K
(H : ANT1) : K
(H : Through) : K
30.0
≤
f
≤
60.0 (MHz)
21.50
≤
f < 30.0 (MHz)
14.50
≤
f < 21.50 (MHz)
7.50
≤
f < 14.50 (MHz) : K
4.70
≤
f < 5.50 (MHz) : K
5.50
≤
f < 7.50 (MHz) : K
2.50
≤
f < 4.70 (MHz) f < 2.50 (MHz)
10.50
≤
f < 14.50 (MHz) : E
7.50
≤
f < 10.50 (MHz) : E
4.70
≤
f < 7.50 (MHz) : E
Phase error correction C1 On : Active, Off : Inactive
Phase error correction C2 On : Active, Off : Inactive
Phase error correction C3 On : Active, Off : Inactive
Phase error correction C4 On : Active, Off : Inactive
Phase error correction C5 On : Active, Off : Inactive
Phase error correction C6 On : Active, Off : Inactive
Phase error correction C7 On : Active, Off : Inactive
Phase error correction C8 On : Active, Off : Inactive
Amplitude error correction C1 On : Active, Off : Inactive
Amplitude error correction C2 On : Active, Off : Inactive
Amplitude error correction C3 On : Active, Off : Inactive
Amplitude error correction C4 On : Active, Off : Inactive
Amplitude error correction C5 On : Active, Off : Inactive
Amplitude error correction C6 On : Active, Off : Inactive
Amplitude error correction C7 On : Active, Off : Inactive
Amplitude error correction C8 On : Active, Off : Inactive
37
TS-2000/X
SEMICONDUCTOR DATA
■ Control unit (X53-391)
Pin No. Port name Pin name I/O
16
15
14
13
IC25 : TC74VHC573FT
19 Q0 PENA
18
17
Q1
Q2
PEN1
PEN2
Q3
Q4
Q5
Q6
PEN3
PEN4
PEN5
PEN6
17
16
15
14
12 Q7 DSPW
IC24 : TC74VHC573FT
19
18
Q0
Q1
DEN1
DEN2
Q2
Q3
Q4
Q5
DEN3
DEN4
DEN5
DEN6
18
17
16
15
13
12
Q6 12EN1
Q7 12EN2
IC22 : TC74VHC573FT
19 Q0 IEN1
Q1
Q2
Q3
Q4
IEN2
IEN3
IEN4
EIN5
19
18
17
14
13
Q5 DTCLK
Q6 REN1
12 Q7 VCS
IC21 : TC74VHC573FT
Q0
Q1
Q2
SRXC
DSPEN1
DSPEN2
Function
O PLL serial-parallel enable A
O PLL enable 1
O PLL enable 2
O PLL enable 3
O PLL enable 4
O PLL enable 5
O PLL enable 6
O DSP control signal
O DDS enable 1
O DDS enable 2
O DDS enable 3
O DDS enable 4
O DDS enable 5
O DDS enable 6
O 1.2G enable 1
O 1.2G enable 2
O IF serial-parallel enable 1
O IF serial-parallel enable 2
O IF serial-parallel enable 3
O IF DAC enable 5
O IF DAC enable 6
O DTMF clock
O RF serial-parallel enable 1
O VS-3 chip select
O DSP control signal
O DSP control signal
O DSP CODEC enable
15
14
13
12
19
18
17
16
Pin No. Port name Pin name I/O
16
15
Q3
Q4
AMU
12EN3
O
O
Function
AF mute signal
1.2G enable 3
14
13
12
Q5
Q6
Q7
SQC
ISTBY
RTS3
IC23 : TC74VHC573FT
O For TNC
O STBY for TNC
O For tNC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
HFTXC
HFRXC
VTXC
VRXC
UTXC
URXC
12TXC
12RXC
O
O
O
O
O
O
O
O
HF TX power start instruction
HF RX power start instruction
VHF TX power start instruction
VHF RX power start instruction
UHF TX power start instruction
UHF RX power start instruction
1.2G TX power start instruction
1.2G RX power start instruction
7
8
5
6
IC20 : TC74VHC573FT
2 D0 SPS
3
4
D1
D2
PKSI
S9600
D3
D4
D5
D6
PMUTE
12OP
CTS3
STA
6
7
4
5
9 D7 CON
IC19 : TC74VHC573FT
2
3
D0
D1
SIM0
SIM1
8
9
D2
D3
D4
D5
D6
D7
SIM2
SIM3
SIM4
SIM5
SIM6
SIM7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SP2 connection detection
PKS for TNC
For TNC
Mute instruction from modem IC
1.2G unit connection detection
For TNC
STA instruction from modem IC
CON instruction from modem IC
Type setting 0
Type setting 1
Type setting 2
Type setting 3
Type setting 4
Type setting 5
Type setting 6
Type setting 7
38
IC530 : BU2099FV, Enable : DSPEN2
Pin No.
Port name Pin name
6
7
Q0
Q1
MIC
ACC12
8
9
10
11
Q2
Q3
Q4
Q5
TNC12
DRU
RX12
M.REM
12
13
14
15
16
17
Q6
Q7
Q8
Q9
Q10
Q11
S.REM
M.TNC
S.TNC
MIC.REM
TNC96
NOT96
Function
TX input (Microphone selection)
TX input (ACC 1200 bps)
TX input (TNC 1200 bps)
TX input (DRU selection)
RX ACC outut (1200 bps)
Remote input (Main)
Remote input (Sub)
RX TNC selection (Main)
RX TNC selection (Sub)
Remote input (Microphone)
TX input (TNC 9600 bps)
TX data speed (Other than 9600 bps)
Active level
H
H
H
H
H
H
H
H
H
H
H
H
TX from microphone
Condition
TX 1200 bps from ACC (PKD)
TX 1200 bps from built-in TNC
TX from DRU
ACC uses menu 1200 bps
External trasceiver remote function (Reserved)
When the external transceiver remote function is on
TNC band (Main)
TNC band (Sub)
When the microphone remote function is on
9600 bps TX data from built-in TNC.
Other than 9600 bps is selected to transmit
TS-2000/X
SEMICONDUCTOR DATA
■ TX-RX 1 unit (X57-605)
Pin No.
Port name Pin name
15
16
17
11
12
13
14
IC5 : BU2099FV, Enable : IEN1
6 Q0 BPF12
7
8
Q1
Q2
BPF11
BPF10
9
10
11
12
Q3
Q4
Q5
Q6
BPF9
BPF8
BPF7
BPF6
13
14
15
16
Q7
Q8
Q9
Q10
BPF5
BPF4
BPF3
BPF2
17 Q11 BPF1
IC16 : BU2099FV, Enable : IEN2
6
7
Q0
Q1
FIL1
FIL2
12
13
14
15
8
9
10
11
Q6
Q7
Q8
Q9
Q2
Q3
Q4
Q5
FIL3
TCS
455FIL1
455FIL2
455FIL3
HFRGC
50RGC
NC
16
17
Q10
Q11
MSQS
SSQS
IC17 : BU2099FV, Enable : IEN3
6 Q0 UATT
7
8
9
10
Q1
Q2
Q3
Q4
VATT
ATT
RXANT
PREAMP
Q5
Q6
Q7
Q8
Q9
Q10
Q11
MCFSW
AMC
PKDSW
NFMT*
NFMR*
RLSW
LINEAR
Function
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
BPF selection
10.695M filter 12k
10.695M filter 2.7k
10.695M filter through
AT tune switch
455k filter 15k
455k filter 9k
455k filter 2.7k
HF RX gain adjustment
50M RX gain adjustment
Main SQL
Sub SQL
UHF ATT switch
VHF ATT switch
HF ATT switch
RX ANT switch
Pre-amplifier on/off
MCF switch
AM switch
PKD TX switch
Not FM TX
Not FM RX
TX-B output switch
Linear switch
NFMT*
FM
AM, CW
SSB, FSK
TX
L
H
H
RX
L
L
L
NFMR*
FM
AM, CW
SSB, FSK
TX
L
L
L
H
H/L
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Active level Condition
49.0MHz
≤
f < 54.0MHz
30MHz
≤
f < 49MHz, 54MHz
≤
f
≤
60MHz
21.5MHz
≤
f < 30.0MHz
14.5MHz
≤
f < 21.5MHz
13.9MHz
≤
f < 14.5MHz
10.5MHz
≤
f < 13.9MHz
7.50MHz
≤
f < 10.5MHz
6.90MHz
≤
f < 7.50MHz
4.10MHz
≤
f < 6.90MHz
2.50MHz
≤
f < 4.10MHz
1.705MHz
≤
f < 2.50MHz
f
≤
1.705MHz
H/L
H/L
10.695M filter 12k
10.695M filter 2.7k
10.695M filter through
Auto tune
455k filter 15k
455k filter 9k
455k filter 2.7k
21.5MHz
≤
f < 30.0MHz & Pre-amplifier : On
30.0MHz
≤
f
≤
60MHz & Pre-amplifier : On
BUSY : H, Not BUSY : L
BUSY : H, Not BUSY : L
UHF & ATT on
VHF & ATT on
HF & ATT on, or V/U/1.2G
f
≤
30.0MHz & EXT. RX. ANT. on
HF & Pre-amplifier on
75M : H, 69M : L
50ms after AM TX is initiated
When 9600 bps data is transmitted from ACC (PKD)
When the transmission mode is other than FM
When the reception mode is other than FM f
≤
30.0MHz or 50MHz Linear ON
Linear ON
RX
L
H
H
39
TS-2000/X
SEMICONDUCTOR DATA
■ TX-RX 2 unit (X57-606)
Pin No.
Port name Pin name
IC2 : BU2099FV
10
11
12
13
8
9
6
7
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
AMSW
W/NSW
R43S
R14S
8RS1
8RS1/2
UPRE
VPRE
14
15
16
17
Q8
Q9
Q10
Q11
IMS
R50S
NC
R20S
IC404 : BU4094BCFV
4 Q1 HF VCO1
Function
AM power switch
Wide/Narrow selection switch
Front end selection switch for sub UHF
SUB VHF power switch
SLO1 amplifier switch
SLO1 prescaler (1/2) switch
UHF pre-amplifier switch
VHF pre-amplifier switch
VHF pre-amplifier through switch
Front end selection switch for sub UHF
Front end selection switch for sub VHF
VCO1 selection for HF band
Active level
L
H
L
L
L
L
L
L
L
L
L
L
5
6
7
14
13
12
11
Q2
Q3
Q4
Q5
Q6
Q7
Q8
HF VCO2
HF VCO3
USW
VSW
BSW2
BSW1
VPRE
VCO2 selection for HF band
VCO3 selection for HF band
VCO selection for VHF band
VCO selection for UHF band
VCO selection for sub VHF band
VCO selection for sub UHF band
VCO oscillator range selection for sub band
H
H
H
H
H
H
H/L
Condition
When the sub AM is selected for receiving
When the sub FM narrow is selected for receiving
When the sub UHF is selected for receiving
When the sub VHF is selected for receiving
When the sub VHF is selected for receiving
When the sub UHF is selected for receiving
When the UHF receiver and pre-amplifier is off
When the VHF receiver and pre-amplifier is off
When the sub UHF is selected for receiving
When the sub VHF is selected for receiving
When the frequency range of
0.03~17.0MHz is selected
When the frequency range of
17.0~37.0MHz is selected
When the frequency range of
37.0~60.0MHz is selected
When the main band VHF is selected
When the main band UHF is selected
When the sub band RX VHF is selected
When the sub band RX UHF is selected
When the sub band is selected for receiving
40
Conversion Between 5V and 3V :
TC74LVX4245FS (Control unit IC9~11)
■ Block diagram
VCCA VCCB
DIR
OE
A1
Logic
Level
Converter
B1
A8 Same as above block B8
■ Logic symbol
OE
(22)
DIR
(2)
A1
(3)
A2
(4)
A3
(5)
A4
(6)
A5
(7)
A6
(8)
A7
(9)
A8
(10)
G3
3EN1 (BA)
3EN2 (AB)
1
2
(21)
B1
(20)
B2
(19)
B3
(18)
B4
(17)
B5
(16)
B6
(15)
B7
(14)
B8
TS-2000/X
SEMICONDUCTOR DATA
Serial-Parallel : BU2099FV
(Final unit IC205, Control unit IC530,
Display unit IC4, TX-RX 1 unit IC5,16,17,
TX-RX 2 unit IC2)
■ Block diagram
VSS
1
NC
2
DATA
3
CLOCK 4
LCK
5
Q0
6
Q1 7
Q2 8
Q3 9
Q4 10
LPF
Control circuit
14 Q8
13 Q7
12 Q6
11
Q5
20 VDD
19 OE
18 SO
17
Q11
16
Q10
15
Q9
■ Pin description
No.
3
4
1
2
Name
Vss
NC
DATA
CLOCK
I/O Description
I
I
– GND
– NC
Serial data input.
Shift register shift clock
5 LCK I
(rising edge trigger).
Storage register latch clock
(rising edge trigger).
6~17 Q0~Q11 O Paralle data output
(Qx) (Nch open drain FET).
Latch data
Output FET
L
On
H
Off
18
19
20
SO
OE
VDD
O Serial data output.
I Output enable control input.
– Power
D flip-flop : TC7WH74FU (Filter unit IC2)
■ Logic diagram
PR
(7)
CK
(1)
D
(2)
(6)
CLR
S
D
C
R
(5)
Q
(3)
Q
■ Truth table
Input
CLR
L
H
L
H
H
H
X : Don‘t care
H
H
H
PR
H
L
L
L
H
X
X
X
D
X
CK
X
X
X
↑
↑
↓
L
H
Qn
H
H
Q
L
Output
H
L
Qn
L
H
Q
H
Function
Clear
Preset
–
–
–
No change
Analog Switch : TC74HC4052AFT (Control unit IC6)
Analog Switch : TC74HC4053AFT (Control unit IC5)
Mixer : TC74HC4053AFT (TX-RX 1 unit IC3)
■ Logic diagram
TC74HC4052AFT TC74HC4053AFT
A
(10)
B
(9)
INH
(6)
X-COM
(13)
Y-COM
(3)
MUXDMUX
0
1
4 x
0
3
G4
0...3
0
1
2
3
(12)
0X
(14)
1X
(15)
2X
(11)
3X
(1)
0Y
(5)
1Y
(2)
2Y
(4)
3Y
INH
(6)
A
(11)
X-COM
(14)
(10)
B
Y-COM
(15)
(9)
C
Z-COM
(4)
MUXDMUX
G2
2 x 0
2 x 1
0,1
0
1
(12)
0X
(13)
1X
(2)
0Y
(1)
1Y
(5)
0Z
(3)
1Z
■ Truth table
Control inputs
L
L
L
L
Inhibit
L
L
L
C*
L
L
L
L
H
H
H
B
L
L
H
H
L
L
H
L
H
H
X
H
X
H
X
X : Don‘t care, * : Except HC4052A
H
L
H
L
H
L
A
L
“ON” channel
HC4052A HC4053A
0X, 0Y
1X, 1Y
0X, 0Y, 0Z
1X, 0Y, 0Z
2X, 2Y
3X, 3Y
– –
– –
0X, 1Y, 0Z
1X, 1Y, 0Z
0X, 0Y, 1Z
1X, 0Y, 1Z
– –
– –
None
0X, 1Y, 1Z
1X, 1Y, 1Z
None
41
TS-2000/X
SEMICONDUCTOR DATA
Flash ROM for DSP : 29LV800B (Control unit IC504,508)
■ Block diagram
Vcc
Vss
WE
BYTE
RESET
CE
OE
RY/BY buffer
RY/BY
Erase circuit
Control circuit
(Command register)
Write circuit
DQ0~DQ15
Input/output buffer
Chip enable output enable circuit
STB
Data latch
A0~A18
A-1
Low Vcc detection
Write/Erase pulse timer
STB
Y decoder
X decoder
Y gate
8,388,608 cell matrix
■ Pin description
No.
Name
19
20
21
22
23
15
16
17
18
11
12
13
14
1~3
4~8
9
10
A13~A15
A12~A8
NC
WE
RESET
Vcc
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
A16
BYTE
Vss
DQ15/A–1
Description
Address Input.
Address input.
No connection.
Write enable.
Hardware reset.
Power (2.7~3.6V).
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Address input.
8 bit/16 bit mode changeover.
Ground.
Data input/output/Address input.
No.
32
33
34
35
36
37
38,39
40~43
44~46
28
29
30
31
24
25
26
27
DQ9
DQ2
DQ10
DQ3
DQ11
NC
RY/BY
A18,A17
A7~A4
A1~A3
OE
Name
Vss
CE
A0
DQ0
DQ8
DQ1
Description
Output enable.
Ground.
Chip enable.
Address input.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
No connection.
Ready/Busy output.
Address input.
Address input.
Address input.
42
TS-2000/X
SEMICONDUCTOR DATA
DSP : 320VC5402PGE (Control unit IC515,516)
■ Pin description
Pin name Type* Description
Data signal
A19~A0 O/Z Parallel address bus A19 (MSB) to A0 (LSB). The low-order 16 bits (A0 to A15) of the address pin are multiplexed to address to external memory (data, program) or I/O. The high-order 4 bits (A16 to A19) are used to address to external program space. These pins are high impedance when in hold mode or when OFF is low.
D15~D0 I/O/Z Parallel data bus D15 (MSB) to D0 (LSB). D15 to D0 are multiplexed to transfer data between the core CPU and external data/program memory or I/O device. The data bus becomes high impedance when data is not output or
RS or HOLD is low. It also becomes high impedance when OFF is low.
The data bus has a bus holder to reduce power consumption of unused pins. When there is a bus holder, external bias resistors for unused pins are not necessary. When '5402 does not drive the data bus, the bus holder retains the
IACK
INT0~
INT3
NMI preceding logic level pin. The '5402 data bus holder is disabled on reset, and enabled/disabled through the BH bit of the bank switching control register (BSCR).
Initialization, interrupt and reset operation
O/Z Interrupt signal. Interrupt reception and interrupt vector specified by A15 to A0 are fetched by the program counter.
I
I
It becomes high impedance when OFF is low.
External user interrupt input. INT0 to INT3 have priorities and can be masked by interrupt mask resister (IMR) and interrupt mode bit. Polling and reset can be performed by the interrupt flag register (IFR).
Interrupt signal that cannot be masked. This external interrupt cannot be masked by INTM or IMR.
RS
MP/MC
BIO
XF
DS
PS
IS
MSTRB
READY
R/W
I
I
When NMI is low, the vector is trapped.
Reset. RS stops DSP operation and initializes the CPU and peripheral. When RS goes high, execution starts from
0FF80h address of the program memory. RS affects various registers and status bits.
Microprocessor/microcomputer mode selection. If it is low on reset, the microcomputer mode is selected, and the internal program ROM is mapped to the high-order 4K words of the program memory space. If it is high on reset, the microprocessor mode is selected and the onchip ROM is erased from the program space. This pin is sampled only on reset, and when the MP/MC bit of the processor mode status (PMST) register is reset, the selected mode is made invalid.
Multi-processing signal
I Branch control. When BIO is active, a conditional branch can be executed. When it is low, the processor executes a conditional branch. The XC instruction samples BIO condition in the pipeline decode phase. Other instructions sample
BIO in the read phase.
O/Z External flag output (latch signal that can be changed by software). It is set to high by SSBX XF instruction, and set to low by loading an RSBX XF instruction or ST1. This signal is used as a communication or general output signal when several DSPs are used. It becomes high impedance when OFF signal is at low level, and is set to high level on reset.
Memory control signal
O/Z Data, program, or I/O space select signal. It is always at high level, except when it is driven at low level to access a specific external memory space. It is active while the address is effective. In hold mode, it becomes high impedance when the OFF signal is at low level.
O/Z Memory strobe signal. It is always at high level, except when accessing data or program memory through an external bus. In hold mode, it becomes high impedance when the OFF signal is at low level.
I Data ready signal. It indicates that an external device has finished preparing accessing a bus.
If it is not ready (READY is at low level), it waits one cycle and checks the READY signal again. At least two software wait states must be programmed for the processor to detect a READY signal. The READY signal is not sampled until software wait states are complete.
O/Z Read/write signal. It indicates the direction of data transfer with an external device. It is normally at high level (read mode) except when it goes low to execute a write operation. In hold mode, it becomes high impedance when the
OFF signal is at low level.
43
TS-2000/X
SEMICONDUCTOR DATA
Pin name Type*
IOSTRB O/Z
Description
I/O strobe signal. It is always at high level (read mode) except when accessing an I/O device through an external bus.
HOLD I
In hold mode, it becomes high impedance when the OFF signal is at low level.
Hold input signal. Address, data, or control signal control input signal. When this signal is accepted, the address,
HOLDA data, or control signal becomes high impedance.
O/Z Hold response signal. It notifies the external circuits that the processor is in hold state and the address, data and control signals are high impedance so that they can be used by the external circuits. It becomes high impedance when the OFF signal is at low level.
MSC O/Z Microstate completion signal. MSC indicates that all software wait states are complete. When several software wait states are enabled, MSC becomes active at the beginning of the first software wait state and becomes inactive high at the beginning of the last software wait state. When READY input is connected, MSC inserts an external wait state forcibly after completion of the last internal wait state. It becomes high impedance when the OFF signal is at low level.
IAQ O/Z Instruction capture signal. It becomes active low when an instruction address is on the address bus. It becomes high
impedance when the OFF signal is at low level.
Oscillator/timer signal
CLKOUT O/Z Master/clock output signal. A signal with the same frequency as the CPU machine cycle is output. The internal machine
CLKMD1
~
CLKMD3
X2/CLKIN
X1
TOUT0
I cycle is delimited at a rising edge of this signal. It becomes high impedance when the OFF signal is at low level.
Clock mode select signal. These input signals are used to select a mode that is initialized after the clock generator is reset. The CLKMD1 to CLKMD3 logic level is latched when the reset pin is low and the clock mode register is initialized in the selected mode. The clock mode is changed by software after reset, but the clock mode select signal
I is not affected until the device is reset again.
Oscillator input. This is an input to the onchip oscillator. If an internal oscillator is not used, X2/CLKIN functions as a clock input and is driven by the external clock source.
Output pin from crystal internal oscillator. If the internal oscillator is not used, do not connect this pin. It does not O become high impedance when the OFF signal is at low level.
O/Z Timer 0 output. When onchip timer 0 count exceeds 0, a pulse is output. It has the same pulse width as CLKOUT.
TOUT1
It becomes high impedance when the OFF signal is at low level.
O/Z Timer 1 output. When onchip timer 1 count exceeds 0, a pulse is output. It has the same pulse width as CLKOUT.
TOUT1 is output from the HPI HINT pin. It is disabled when HPI is disabled. It does not become high impedance when the OFF signal is at low level.
Multi-channel buffered serial port signal
BCLKR0 I/O/Z Receive clock input. BCLKR can be used as input and output, and becomes input after reset. It is a serial shift clock
BCLKR1
BDR0 I of the receive side buffered serial port.
Serial data reception input.
BDR1
BFSR0
BFSR1
I/O/Z Reception input frame synchronous pulse. BFSR can be used as input and output, and becomes input after reset.
The BFSR pulse ends BDR and initializes data reception.
BCLKX0 I/O/Z Transmission clock. BCLKX is a McBSP transmission serial shift clock. BCLKX can be used as input and output, and
BCLKX1
BDX0 O/Z becomes input after reset. It becomes high impedance when the OFF signal is at low level.
Serial data transmission output. BDX becomes high impedance when transmission is not performed, RS is low, or
BDX1
BFSX0
BFSX1
NC
I/O/Z
OFF is low.
Transmission I/O frame synchronizing pulse. The BFSX pulse initializes data transmission. It can be used as input and output, and becomes input after reset. It becomes high impedance when the OFF signal is low.
No connection.
Other signals
44
TS-2000/X
SEMICONDUCTOR DATA
Pin name Type*
HD0~
HD7
Description
Host port interface (HPI) signal
I/O/Z Parallel bi-directional data bus. The HPI data bus is used by the host device bus to exchange data with the HPI register.
It becomes high impedance when data is not output or OFF is low. The HPI data bus has a bus holder to reduce power
HCNTL0
HCNTL1
HBIL I
I consumption of unused pins. When the DSP does not drive the HPI data bus, the bus holder retains the preceding logic level. The HPI data bus holder is disabled on reset, and can be enabled/disabled through the HBH bit of the BSCR.
Control signal. HCNTL0 and HCNTL1 select one of three HPI registers for accessing the host. Control input includes an internal pull-up register that is enabled only when HPIENA = 0.
HCS I
Byte recognition signal. HBIL recognizes the first or second byte to be transmitted. HBIL input includes an internal pull-up register that is enabled only when HPIENA = 0.
Chip select signal. HCS selects HPI input and is driven to low during access. The chip select signal includes an internal pull-up register that is enabled only when HPIENA = 0.
HDS1
HDS2
HAS
HR/W
HRDY
HINT
I
I
Data strobe signal. HDS1 and HDS2 are driven by host read and write strobe for the control signal.
There is an internal pull-up register that is enabled only when HPIENA = 0.
Address strobe signal. HAS is necessary for the host with multiplexed address and data pins to latch an address with the HPIA register. There is an internal pull-up register that is enabled only when HPIENA = 0.
I Read/write. HR/W controls HPI transfer direction. There is an internal pull-up register that is enabled only when HPIENA = 0.
O/Z Ready signal. Ready output notifies the host that the HPI is ready to transmit. It becomes high impedance when the
OFF signal is low.
O/Z Host interrupt signal. This output is used to interrupt the host. When the DSP is reset, it goes high. HINT can be
HPIENA
CVDD
DVDD
Vss
TCK
TDI
TDO
I
S
S
S used as timer 1 output (TOUT1) when HPI is disabled. It becomes high impedance when the OFF signal is low.
HPI module select signal. To enable HPI, this pin must be made high on reset. The internal pulldown register is always active and the HPIENA pin is sampled at a rising edge of RS. When HPIENA is open or low on reset, the HPI module is disabled. The HPIENA pin is not affected until the DSP is reset.
Power supply pins
+VDD. CPU core 1.8V power supply.
+VDD. I/O pin 3.3V power supply.
Ground.
I
Test pins
IEEE standard 1149.1 test clock. Normally, clock input with a duty ratio of 50%. When the input signal (TMS, TDI) changes on the TAP (test access port), it is loaded into the TAP controller, instruction register, and test data register at a rising edge of TCK. The TAP output signal (TDO) data changes at a falling edge of TCK.
I IEEE standard 1149.1 test data input pin with an internal pull-up device. TDI data is loaded into a register (instruction or data) at a rising edge of TCK.
O/Z IEEE standard 1149.1 test data output pin. The contents of a register (instruction or data) are output from TDO at a falling edge of TCK. TDO is high impedance except during data scan processing. It also becomes high impedance
TMS
TRST
EMU0
EMU1/
OFF
I when the OFF signal is low.
IEEE standard 1149.1 test mode select pin with an internal pull-up device. The serial control input is loaded into the
TAP controller at a rising edge of TCK.
IEEE standard 1149.1 test reset pin with internal pulldown device. When it is high, the device enters the IEEE I standard 1149.1 scan system control mode. If it is low or not connected, the IEEE standard 1149.1 signal is ignored.
I/O/Z Emulator pin 0. When the TRST pin is low, this pin must be high . When the TRST pin is high, this pin is used as an interrupt for the emulator system and becomes an I/O for the IEEE standard 1149.1 scan.
I/O/Z Emulator 1 pin/output control pin. When the TRST pin is high, this pin is used as an interrupt for the emulator system and becomes an I/O for the IEEE standard 1149.1 scan system. When the TRST pin is low, all outputs are high impedance. Note that the OFF pin is exclusive for test and emulation. (They cannot be executed at the same time.)
OFF conditions are as follows; TRST = L, EMU0 = H, EMU1/OFF = L.
* I = Input, O = Output, Z = High impedance, S = Supply
45
TS-2000/X
SEMICONDUCTOR DATA
CODEC (24 bit) : AK4524 (Control unit IC518)
■ Block diagram
AINL
3
AINR 2
VCOM 1
AOUTL+ 26
AOUTL–
25
AOUTR+ 28
AOUTR–
27
Control Register I/F
17 16 15 18
CS CCLK CDTI CIF
ADC
DAC
HPF
DATT
DATT
SMUTE
Audio I/F
Controller
Clock Gen. & Divider
21 8 9 10
CLKO XTO XTI XTALE
23 VD
22
VT
24 DGND
19 PD
4
6
5
11
LRCK
12
BICK
13 SDTO
14 SDTI
20 M/S
VREF
VA
AGND
46
■ Pin function
No.
Name
1 VCOM
I/O Function
O Common voltage output pin, VA/2.
15
16
17
18
11
12
13
14
9
10
7
8
5
6
2
3
4
19
AINR
AINL
VREF
LRCK
BICK
SDTO
SDTI
CDTI
CCLK
CS
CIF
AGND
VA
TEST
XTO
XTI
XTALE
PD
I
I
I
Bias voltage os ADC inputs and DAC outputs.
Rch analog input pin.
Lch analog input pin.
Voltage reference input pin, VA.
Used as a voltage reference by ADC
& DAC, VREF is connected externally to filtered VA.
–
–
Analog ground pin.
Analog power supply pin, 4.75~5.25V
I Test pin. (Internal pull-down pin)
O X’tal output pin.
I
I X’tal/master clock input pin.
X’tal osc enable pin.
“H” : Enable, “L” : Disable
I/O Input/output channel clock pin.
I
I
I
I
I
I/O Audio serial data clock pin.
O Audio serial data output pin.
Audio serial data input pin.
Control data input pin.
Control data clock pin.
Chip select pin.
Control data I/F format pin.
“H” : CS falling trigger,
I
“L” : CS rising trigger
Power down mode in.
“H” : Power up, “L” : Power down reset and initialize the control register.
No.
20
21
22
23
24
25
26
Name
M/S
I/O
I
Function
Master/slave mode pin.
“H” : Master mode, “L” : Slave mode
O Master clock output pin.
CLKO
VT
VD
DGND
– Output buffer power supply pin,
2.7~5.25V.
–
–
Digital power supply pin, 4.75~5.25V.
Digital ground pin.
AOUTL– O Lch negative analog output pin.
AOUTL+ O Lch positive analog output pin.
27
28
AOUTR–
AOUTR+
O
O
Rch negative analog output pin.
Rch positive analog output pin.
Note : All input pins except pull-down pins should not be left floating.
Mixer : TA4101F (TX-RX 1 unit IC6)
■ Equivalent circuit
R1
RB1
RB2
2 : Vcc
RL1
R2
Q1
3 : OSC in
Q2 Q3
RL2
Q4
RB3
R3
RB4
Q5
5 : Base
RE1
R4
RE2
Q6
8 : Collector
1 : IF out
4 : Base
6 : Base
7 : GND
TS-2000/X
SEMICONDUCTOR DATA
CODEC (16 bit) : AK4518
(Control unit IC522,523)
■ Block diagram
AINL
VCML
6
5
AINR
VCMR
3
VRAD
VRDA
VCOM 21
4
2
1
AOUTL
19
AOUTR 20
∆∑
Modulator
∆∑
Modulator
Decimation
Filter
Decimation
Filter
Clock
Divider
9
16
MCLK
CMODE
LPF
LPF
24
VA
Common
Voltage
Serial I/O
Interface
∆∑
Modulator
∆∑
Modulator
22
AGND
8x
Interpolator
23
VB
8x
Interpolator
14
VD
13
DGND
10 LRCK
11
SCLK
12 SDTO
15 SDTI
7
8
PWAD
PWDA
17 DEM1
18 DEM0
■ Pin function
No.
Name
1 VRDA
2 VRAD
3 AINR
4 VCMR
I/O
I
I
Function
Voltage reference input pin for DAC, VA.
I
Voltage reference input pin for ADC, VA.
Rch analog input pin.
O Rch common voltage output pin,
0.45 x VA. Connect a 4.7
µ
F electrolytic capacitor and 0.1
µ
F ceramic capacitor between this pin and AGND.
5 VCML
6 AINL
7 PWAD
8 PWDA
9 MCLK
10 LRCK
11 SCLK
12 SDTO
13 DGND
14 VD
15 SDTI
16 CMODE
I
I
O Lch common voltage output pin,
0.45 x VA. Connect a 4.7
µ
F electrolytic capacitor and 0.1
µ
F ceramic capacitor between this pin and AGND.
Lch analog input pin.
ADC power down mode pin.
I
“L” : Power down
DAC power down mode pin.
I
I
“L” : Power down
Master clock input pin.
I
Input/output channel clock pin.
Audio serial data clock pin.
O Audio serial data output pin.
I
I
– Digital ground pin.
– Digital power supply pin.
Audio serial data input pin.
Master clock select pin.
“H” : 384fs or 512fs, “L” : 256fs
No.
Name
17 DEM1
18 DEM0
19 AOUTL
20 AOUTR
21 VCOM
22
23
24
AGND
VB
VA
I/O
I
Function
De-emphasis frequency select pin.
I De-emphasis frequency select pin.
O Lch analog output pin.
O Rch analog output pin.
O Common voltage output pin, 0.45 x VA.
Connect a 4.7
µ
F electrolytic capacitor and 0.1
µ
F ceramic capacitor between this pin and AGND.
– Analog ground pin.
– Substrate pin.
– Analog power supply pin.
Amplifier : UPC2709TB
(TX-RX 2 unit IC405, 415,416, TX-RX 3 unit IC1)
■ Equivalent circuit
6 : Vcc
4 : OUT
1 : IN
3 : GND 2,5 : GND
47
TS-2000/X
SEMICONDUCTOR DATA
DDS : AD9835 (TX-RX 1 unit IC601~603,
TX-RX 2 unit IC406~408)
■ Block diagram
DVDD
4
MCLK
6
FSELECT
BIT
FSELECT
10
DGND
5
AVDD
15
SELSRC
AGND
13
REFOUT
3
FS ADJUST
1
REFIN
2
ON-Board
Reference
Full-Scale
Control
16 COMP
SYNC
FREQ0 REG
FREQ1 REG
MUX
Phase
Accumulator
(32 bit)
SYNC
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
16-bit Data Register
8 MSBs 8 LSBs
Defer
Register
MUX
SYNC
SELSRC
∑
12
COS
ROM
10-bit
DAC
SYNC
Decode Logic
Serial Register
9
FSYNC
7
SCLK
8
SDATA
Control Register
FSELECT/PSEL
Register
PSEL0
BIT
PSEL1
BIT
11
PSEL0
12
PSEL1
14 IOUT
■ Pin function
No.
Symbol Function
Analog signal and reference
1 FS ADJUST Full-scale adjust control.
9
10
7
8
11
12
14
16
2
3
REFIN
REFOUT
IOUT
COMP
Voltage reference input.
Voltage reference output.
Current output.
Compensation pin.
Power supply
4
5
13
15
DVDD
DGND
AGND
AVDD
Positive power supply for the digital section.
Digital ground.
Analog ground.
Positive power suply fot the analog section.
Digital interface and control
6 MCLK Digital clock input.
SCLK
SDATA
FSYNC
FSELECT
PSEL0
PSEL1
Serial clock, logic input.
Serial data in, logic input.
Data synchronization signal, logic input.
Frequency select input.
Phase select input.
DAC : M62363FP (TX-RX 1 unit IC14)
■ Block diagram
DI
8
CLK
7
12-bit shift register
RESET
19 8-bit latch
VDD
5
D-A converter
20 1 2
GND VIN1 VOUT1
Address decoder
17
DO
6 LD
8-bit latch
D-A converter
24 23
VIN8 VOUT8
18 VDAref
12
13
4
9
23
5
20
1
16
21
24
18
11
14
15
22
19
2
3
10
■ Pin function
No.
Symbol
8 DI
Function
Serial data input terminal.
17 DO Serial data output terminal.
7
6
VOUT5
VOUT6
VOUT7
VOUT8
VDD
GND
VIN1
VIN2
CLK
LD
Serial clock input terminal.
LD terminal input high level then latch circuit data load.
RESET Reset terminal.
VOUT1 8-bit resolution D-A output.
VOUT2
VOUT3
VOUT4
Power supply terminal.
GND terminal.
D-A converter input terminal.
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VDAref D-A converter reference voltage input terminal.
VO = (VIN – VDAref) x n / 256 + VDAref
48
TS-2000/X
SEMICONDUCTOR DATA
PLL : LMX2306TMX (TX-RX 2 unit IC401,409~412,414)
PLL : LMX2316TMX (TX-RX 2 unit IC402, TX-RX 3 unit IC5)
■ Block diagram
OSC
IN
OSC
14-bit
R counter
Phase
Comp.
Charge
Pump
CPo
CLOCK
LE
DATA f
IN
Prescaler
21-bit
Data Register
18-bit
Function
Latch
18-bit
N counter
Lock
Detect
FoLD
MUX
Fast
Lock
FLo
FoLD
■ Pin description
No.
Name I/O
1 FLo
Description
O FastLock output. For connection of
2
3
4
5
6
7
8
9 f f
CPo
GND
GND
IN
IN parallel resistor to the loop filter.
O Charge pump output. For connection to a loop filter for driving the input of an external VCO.
– Charge pump ground.
– Analog ground.
I RF prescaler complementary input.
A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane.
The complementary input can be left unbypassed, with some degradation in
RF sensitivity.
I RF prescaler input. Small signal input from the VCO.
– Analog power supply voltage input.
Vcc1
Input may range from 2.3V to 5.5V.
Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane.
Vcc1 must equal Vcc2.
OSC
IN
I Oscillator input. This input is a CMOS input with a threshold of approximately
Vcc/2 and an equivalent 100k input
GND resistance. The oscillator input is driven from a reference oscillator.
– Digital ground.
No.
Name I/O
10 CE I
Description
Chip enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output. Taking CE HIGH will power
11 Clock up the device depending on the status of the power down bit F2.
I High impedance CMOS clock input. Data for the various counters is clocked in on
12
13
Data
LE the rising edge into the 21-bit shift register.
I Binary serial data input. Data entered
MSB first. The last two bits are the control bits. High impedance CMOS input.
I Load enable CMOS input. When LE goes high, data stored in the shift registers is loaded into one of the 3 appropriate
14
15
16 latches (control bit dependent).
Fo/LD O Multiplexed output of the RF programmable of reference dividers and lock detect. CMOS output.
Vcc2 – Digital power supply voltage input. Input may range from 2.3V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected
Vp directly to the ground plane. Vcc1 must equal Vcc2.
– Power supply for charge pump.
Must be
≥
Vcc.
49
TS-2000/X
DDS : AD9851BRS (TX-RX 3 unit IC4)
■ Block diagram
+Vs
GND
Ref
Clock in
Master
Reset
6 x REFCLK
Multiplier
High
Speed
DDS
10-bit
DAC
DAC R
SET
Analog out
Frequency
Update/Data
Register
Reset
32-bit
Tuning
Word
Phase and
Control
Words
Frequency/Phase
Data Register
Word Load
Clock
Data Input Register
Serial
Load
Parallel
Load
1 bit x
40 Loads
8 bits x
5 Loads
Frequency, Phase and Control Data Input
Analog in
+
–
Comparator
Clock out
Clock out
■ Pin function
No.
Name
1~4 D3~D0
Function
8-bit data input. The data port for loading
25~28
5
6
7
8
9
D7~D4
PGND
PVCC
W CLK
FQ UD the 32-bit frequency and 8-bit phase/control words. D7 = MSB, D0 = LSB. D7, pin 25, also serves as the input pin 40-bit serial data word.
6 x REFCLK multiplier ground connection.
6 x REFCLK multiplier positive supply voltage pin.
Word load clock. Rising edge loads the parallel or serial frequency/phase/control words asynchronously into the 40-bit input register.
Frequency update. Arising edge asynchronously transfers the contents of the 40-bit input register to be acted upon by the DDS core. FQ UD should be issued when the contents of the input register are known to contain only valid, allowable data.
REFCLOCK Reference clock input. CMOS/TTL level pulse train, direct or via the 6 x REFCLK multiplier. In direct mode, this is also the
SYSTEM CLOCK. If the 6 x REFCLK multiplier is engaged, then the output of the multiplier is the SYSTEM CLOCK. The rising edge of the SYSTEM CLOCK initiates operations.
SEMICONDUCTOR DATA
No.
10,19
11,18
12
13
14
15
16
17
Name
AGND
AVDD
RSET output current available from IOUT and
IOUTB. RSET = 39.93/IOUT.
VOUTN Voltage output negative. The comparator’s
“complementary” CMOS logic level output.
VOUTP Voltage output positive. The comparator’s
“true” CMOS logic level output.
VINN
VINP
Voltage input negative. The comparator’s inverting input.
Voltage input positive. The comparator’s noninverting input.
DACBP
Function
Analog ground. The ground return for the analog circuitry (DAC and comparator).
Positive supply voltage for analog circuitry
(DAC and comparator, pin 18) and bandgap voltage reference (pin 11).
The DAC’s external RSET connection– nominally a 3.92k
Ω
resistor to ground for
10mA out. This sets the DAC full-scale
20 IOUTB
DAC bypass connection. This is he DAC voltage reference bypass connection normally NC (no connect) for optimum
SFDR performance.
The “complementary” DAC output with same characteristics as IOUT except that
IOUTB = (full-scale output – IOUT). Output load should equal that of IOUT for best
21
22
23
24
IOUT
RESET
DVDD
DGND
SFDR performance.
The “true” output of the balanced DAC.
Current is “sourcing” and requires current to voltage conversion, usually a resistor or transformer referenced to GND.
IOUT = (full-scale output – IOUTB).
Master reset pin, active high, clears DDS accumulator and phase offset register to achieve 0Hz and 0
°
output phase.
Sets programming to parallel mode and disengages the 6 x REFCLK multiplier.
Reset does mot clear the 40-bit input register. On power up, asserting RESET should be the first priority before programming commences.
Positive supply voltage pin for digital circuitry.
Digital ground. The ground return pin for the digital circuitry.
50
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Key features
- Satellite communication
- Independent FM/AM sub-receiver
- Noise blanker
- Digital IF filter
- Digital AGC
- Speaker separation function
- IF/AF DSP
- Triple conversion
- Quadruple conversion
