ADM7151 (Rev. A)

ADM7151

APPLICATIONS INFORMATION

MODEL SELECTION

The ADM7151 is available in two models to allow the user to select the best combination of power dissipation and PSRR performance for a given application.

CAPACITOR SELECTION

Output Capacitor

The ADM7151 is designed for operation with ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the

LDO control loop. A minimum of 10 μF capacitance with an

ESR of 0.2 Ω or less is recommended to ensure the stability of the ADM7151 . Output capacitance also affects transient response to changes in load current. Using a larger value of output capacitance improves the transient response of the

ADM7151

to large changes in load current. Figure 51 shows the

transient responses for an output capacitance value of 10 μF.

T

1

Data Sheet

Input and VREG Capacitor

Connecting a 10 μF capacitor from VIN to GND reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance are encountered.

To maintain the best possible stability and PSRR performance, connect a 10 μF capacitor from VREG to GND. When more than 10 μF of output capacitance is required, increase the input and VREG capacitors to match it.

REF Capacitor

The REF capacitor is necessary to stabilize the reference amplifier.

Connect a capacitor of at least 1 μF between REF and GND.

2

CH1 500mA Ω

B

W

CH2 10mV

B

W

M4µs

T 11.0%

A CH1 200mA

Figure 51. Output Transient Response, V

OUT

= 5 V, C

OUT

= 10 μF

Table 6. Model Selection Guide for PSRR

Model V

OUT

Range (V)

ADM7151-02 1.5 to 4.0

ADM7151-04 1.5 to 5.1

PSRR (dB) at 800 mA, 1.2 V Headroom

10 kHz 100 kHz 1 MHz

91

84

91

84

50

53

PSRR (dB) at 400 mA, 1 V Headroom

10 kHz 100 kHz 1 MHz

94

94

94

94

58

67

Table 7. Model Selection Guide for Input Voltage

Model V

OUT

Range (V)

ADM7151-02 1.5 to 4.0

ADM7151-04 1.5 to 5.1

Minimum V

IN

at 800 mA Load Minimum V

IN

at 400 mA Load

V

OUT

< 3.3 V V

OUT

< 5 V V

OUT

≥ 3.3 V V

OUT

≥ 5 V V

OUT

< 3.3 V V

OUT

< 5 V V

OUT

≥ 3.3 V V

OUT

≥ 5 V

4.5 V N/A

1

V

OUT

+ 1.2 V N/A

1

V N/A

1

V

OUT

+ 1.0 V N/A

1

N/A 1 6.2 N/A 1 V

OUT

+ 1.2 V N/A 1 6 1 V

OUT

+ 1.0 V

1

N/A = not applicable.

Rev. A | Page 16 of 24

Data Sheet

BYP Capacitor

The BYP capacitor is necessary to filter the reference buffer. A

1 µF capacitor is typically connected between BYP and GND.

Capacitors as small as 0.1 µF can be used; however, the output noise voltage of the LDO increases as a result.

In addition, the BYP capacitor can be increased to reduce the noise below 1 kHz at the expense of increasing the start-up time of the LDO. Very large values of C

BYP

significantly reduce the noise below 10 Hz. Tantalum capacitors are recommended for capacitors larger than about 33 µF. A 1 µF ceramic capacitor in parallel with the larger tantalum capacitor is required to retain good noise performance at higher frequencies.

100k

10k

1k

C

BYP

= 1µF

C

BYP

= 4.7µF

C

BYP

= 10µF

C

BYP

= 22µF

C

BYP

= 47µF

C

BYP

= 100µF

C

BYP

= 470µF

C

BYP

= 1mF

ADM7151

X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V are recommended. However, Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics.

Figure 54 depicts the capacitance vs. dc bias voltage of a 1206,

10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.

12

10

8

6

4

100

2

10

1

0.1

1 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 52. Noise Spectral Density vs. Frequency, C

BYP

= 1 µF to 1 mF

10k

1k

100

10

1Hz

10Hz

100Hz

400Hz

3Hz

30Hz

300Hz

1kHz

1

1 10 100 1000

C

BYP

(µF)

Figure 53. Noise Spectral Density vs. C

BYP

for Different Frequencies

Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADM7151 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions.

0

0 2 4 6

DC BIAS VOLTAGE (V)

8

Figure 54. Capacitance vs. DC Bias Voltage

10

Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage.

C

EFF

= C

BIAS

× (1 − TEMPCO) × (1 − TOL) (1) where:

C

BIAS

is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

C

BIAS

is 9.72 µF at 5 V, as shown in Figure 54.

Substituting these values in Equation 1 yields

C

EFF

= 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF

Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADM7151 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.

Rev. A | Page 17 of 24

ADM7151

ENABLE (EN) AND UNDERVOLTAGE LOCKOUT

(UVLO)

The ADM7151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 55, when a rising voltage on EN crosses the upper threshold,

VOUT turns on. When a falling voltage on EN crosses the lower threshold, VOUT turns off. The hysteresis varies as a function of the input voltage. For example, the EN hysteresis is approximately 200 mV with an input voltage of 4.5 V.

3.5

1.5

1.0

0.5

3.0

2.5

2.0

VOUT_EN_FALL

VOUT_EN_RISE

0

1.0

1.1

1.2

1.3

1.4

1.5

1.6

V

EN

(V)

Figure 55. Typical V

OUT

Response to EN Pin Operation, V

OUT

= 3.3 V, V

IN

= 5 V

3.2

2.2

2.0

1.8

1.6

3.0

2.8

2.6

2.4

–40°C

+125°C

+25°C

1.4

6 8 10 12 14 16

V

IN

(V)

Figure 56. Typical EN Rise Threshold vs. Input Voltage (V

Temperatures

IN

) for Various

Data Sheet

2.4

2.2

2.0

1.8

1.6

1.4

1.2

–40°C

+25°C

+125°C

1.0

6 8 10 12 14 16

V

IN

(V)

Figure 57. Typical EN Fall Threshold vs. Input Voltage (V

IN

Temperatures

) for Various

The ADM7151 also incorporates an internal undervoltage lockout circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. The upper and lower thresholds are internally fixed with approximately 300 mV of hysteresis.

3.5

3.0

2.5

2.0

1.5

1.0

VOUT_VIN_FALL

VOUT_VIN_RISE

0.5

0

4.0

4.1

4.2

4.3

4.4

V

IN

(V)

Figure 58. Typical UVLO Hysteresis, V

OUT

= 3.3 V

4.5

Figure 58 shows the typical hysteresis of the UVLO function.

This hysteresis prevents on/off oscillations that can occur due to noise on the input voltage as it passes through the threshold points.

Rev. A | Page 18 of 24

Data Sheet

START-UP TIME

The ADM7151 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for a 5 V output is approximately 3 ms from the time the EN active threshold is crossed to when the output reaches 90% of its final value.

The rise time of the output voltage (10% to 90%) is approximately

0.0012 × C

BYP

seconds where C

BYP

is in microfarads.

6

5

ENABLE

C

BYP

C

BYP

C

BYP

= 1µF

= 4.7µF

= 10µF

4

3

2

1

0

0 0.002

0.004

0.006

0.008

0.010

0.012

0.014

0.016

0.018

0.020

TIME (Seconds)

Figure 59. Typical Start-Up Behavior with C

BYP

= 1 µF to 10 µF

6

5

4

3

2

1

ENABLE

C

BYP

C

BYP

C

BYP

= 10µF

= 47µF

= 330µF

0

0 0.02

0.04

0.06

0.08

0.10

0.12

TIME (Seconds)

0.14

0.16

0.18

0.20

Figure 60. Typical Start-Up Behavior with C

BYP

= 10 µF to 330 µF

REF, BYP, AND VREG PINS

REF, BYP, and VREG are internally generated voltages that require external bypass capacitors for proper operation. Do not, under any circumstances, connect any loads to these pins because doing so compromises the noise and PSRR performance of the ADM7151 . Using larger values of C

BYP

, C

REF

, and C

REG

is acceptable but can increase the start-up time, as described in

the Start-Up Time section.

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADM7151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADM7151 is designed to current limit when the

Rev. A | Page 19 of 24

ADM7151

output load reaches 1.3 A (typical). When the output load exceeds 1.3 A, the output voltage is reduced to maintain a constant current limit.

Thermal overload protection is included, which limits the junction temperature to a maximum of 155°C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 155°C, the output is turned off, reducing the output current to zero. When the junction temperature drops below

140°C, the output is turned on again, and output current is restored to its operating value.

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADM7151 current limits, so that only 1.3 A is conducted into the short. If self heating of the junction is great enough to cause its temperature to rise above 155°C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 140°C, the output turns on and conducts 1.3 A into the short, again causing the junction temperature to rise above

155°C. This thermal oscillation between 140°C and 155°C causes a current oscillation between 1.3 A and 0 mA that continues as long as the short remains at the output.

Current-limit and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 150°C.

THERMAL CONSIDERATIONS

In applications with low input to output voltage differential, the

ADM7151 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package can become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 150°C.

When the junction temperature exceeds 155°C, the converter enters thermal shutdown. It recovers only after the junction temperature decreases below 140°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions.

The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2.

To guarantee reliable operation, the junction temperature of the

ADM7151 must not exceed 150°C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θ

JA

). The θ

JA

number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pin and exposed pad to the PCB.

ADM7151

Table 8 shows typical θ

JA

values of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes.

Table 9 shows the typical Ψ

JB

values of the 8-lead SOIC and

8-lead LFCSP.

Table 8. Typical θ

JA

Values

Copper Size (mm

2

)

θ

JA

(°C/W)

8-Lead LFCSP 8-Lead SOIC

25 1

100

500

1000

6400

165.1

125.8

68.1

56.4

42.1

1 Device soldered to minimum size pin traces.

Table 9. Typical Ψ

JB

Values

Package Ψ

JB

(°C/W)

8-Lead LFCSP

8-Lead SOIC

15.1

17.9

165

126.4

69.8

57.8

43.6

The junction temperature of the ADM7151 is calculated from the following equation:

T

J

= T

A

+ (P

D

× θ

JA

) (2) where:

T

A

is the ambient temperature.

P

D

is the power dissipation in the die, given by

P

D

= [(V

IN

V

OUT

) × I

LOAD

] + (V

IN

× I

GND

) where:

V

IN

and V

I

LOAD

I

GND

OUT

are thinput and output voltages, respectively.

is the load current.

is the groune d current.

(3)

Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following:

T

J

= T

A

+ {[(V

IN

V

OUT

) × I

LOAD

] × θ

JA

} (4)

As shown in Equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 150°C.

The heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad of the ADM7151 . Adding thermal planes under the package

also improves thermal performance. However, as listed in Table 8, a

point of diminishing returns is eventually reached, beyond which an increase in the copper area does not yield significant reduction in the junction to ambient thermal resistance.

Rev. A | Page 20 of 24

Data Sheet

Figure 61 to Figure 66 show junction temperature calculations for

different ambient temperatures, power dissipation, and areas of

PCB copper.

155

145

135

125

115

105

95

85

75

65

55

6400mm

2

45 500mm

2

25mm

2

35

T

J

MAX

25

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

TOTAL POWER DISSIPATION (W)

Figure 61. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, T

A

= 25°C

160

150

140

130

120

110

100

90

80

70

60

6400mm

2

500mm

2

25mm

2

T

J

MAX

50

0 0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

TOTAL POWER DISSIPATION (W)

Figure 62. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, T

A

= 50°C

155

145

135

125

115

105

95

85

75

6400mm

2

500mm

2

25mm

2

T

J

MAX

65

0 0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8 0.9 1.0 1.1 1.2 1.3 1.4

1.5

TOTAL POWER DISSIPATION (W)

Figure 63. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, T

A

= 85°C

Data Sheet

115

102

95

85

75

155

145

135

125

65

55

45

35

25

0

6400mm

2

500mm

2

25mm

2

T

J

MAX

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

TOTAL POWER DISSIPATION (W)

Figure 64. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T

A

= 25°C

160

150

140

130

120

110

100

90

80

70

60

6400mm

2

500mm

2

25mm

2

T

J

MAX

50

0 0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

TOTAL POWER DISSIPATION (W)

Figure 65. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T

A

= 50°C

155

145

135

125

115

105

95

85

75

6400mm

2

500mm

2

25mm

2

T

J

MAX

65

0 0.2

0.4

0.6

0.8

1.0

1.2

1.4

TOTAL POWER DISSIPATION (W)

1.6

1.8

2.0

Figure 66. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T

A

= 85°C

Rev. A | Page 21 of 24

Thermal Characterization Parameter (Ψ

JB

)

When the board temperature is known, use the thermal characterization parameter, Ψ

JB

, to estimate the junction

temperature rise (see Figure 67 and Figure 68). Maximum

junction temperature (T

J

) is calculated from the board temperature (T

B

) and power dissipation (P

D

) using the following formula:

T

J

= T

B

+ (P

D

× Ψ

JB

) (5)

The typical value of Ψ

JB

is 15.1°C/W for the 8-lead LFCSP package and 17.9°C/W for the 8-lead SOIC package.

160

140

120

100

80

60

40

20

T

B

= 25°C

T

B

= 50°C

T

B

= 65°C

T

B

= 85°C

T

J

MAX

0

0 0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

TOTAL POWER DISSIPATION (W)

Figure 67. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP

160

140

120

100

80

ADM7151

60

40

20

T

B

= 25°C

T

B

= 50°C

T

B

= 65°C

T

B

= 85°C

T

J

MAX

0

0 0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

TOTAL POWER DISSIPATION (W)

Figure 68. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC

ADM7151

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Place the bypass capacitors for V

REG

,

V

REF

, and V

BYP

close to the respective pins and GND. Use of an

0805, 0603, or 0402 size capacitor achieves the smallest possible footprint solution on boards where area is limited.

Data Sheet

Figure 69. Example 8-Lead LFCSP PCB Layout

Figure 70. Example 8-Lead SOIC PCB Layout

Rev. A | Page 22 of 24

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