System Features
Power Supply
P
OWER
C
ONNECTORS
Main power is applied to the VL-EPM-35 through a 10-pin connector at either location JN8 (top board) or JS8 (bottom board). The table below shows the pinout for both connectors.
Note:
Only one power connector should be used at a time. If both JN8 and JS8 are used at the same time, a ground loop may result.
Warning!
To prevent possibly irreparable damage to the system, it is critical that the power connectors are wired correctly. Make sure to use all +5VDC pins and all ground pins to prevent excess voltage drop. Some manufacturers include a pin-1 indicator
on the crimp housing that corresponds to pin-10 of the pinout shown in Figure 14.
Table 4: Main Power Connector Pinout
JN8/JS8
Pin
1
2
3
4
5
6
7
8
9
10
Signal
Name Description
GND
+5VDC
GND
+12VDC
Ground
Power Input
Ground
Power Input
GND
-12VDC
Ground
Power Input
+3.3VDC Power Input
+5VDC
GND
+5VDC
Power Input
Ground
Power Input
Figure 14 shows the VersaLogic standard pin numbering for this type of 10-pin power connector
and the corresponding mating connector.
JN8/JS8
Some manufacturers include a pin-1 indicator that corresponds to pin-10 of the power connector pinout
2 4
6 8
10
10
8
6
4
2
1 3
5 7
9
9
7
5
3
1
Figure 14. JN8/JS8 and VL-CBR-1008 Pin Numbering
VL-CBR-1008
VL-EPM-35 Reference Manual 23
Physical Details
Note:
The +3.3VDC, +12VDC and -12VDC inputs are required only for expansion modules that require these voltages.
P
OWER
R
EQUIREMENTS
The VL-EPM-35 requires only +5 volts (±5%) for proper operation. The higher voltages required for the RS-232 ports are generated with as needed on-board. Low-voltage supply circuits provide the many power rails required by the CPU and other on-board devices.
The exact power requirement of the VL-EPM-35 depends on several factors, including memory configuration, CPU speed, peripheral connections, type and number of expansion modules and attached devices. For example, driving long RS-232 lines at high speed can increase power demand, and USB devices can draw considerable power depending on the device.
The VL-EPM-35 is equipped with a voltage sensing reset circuit. The system will reset if voltage drops below 4.63V typically (4.50V min./4.75V max.).
P
OWER
D
ELIVERY
C
ONSIDERATIONS
The VL-EPM-35 draws up to 28.5W (5.7A) as measured on a typical time averaging ammeter.
The board can experience large, short-term current transients during operation, so care must be taken to provide robust power to the board. A good power delivery method eliminates such problems as voltage drop and lead inductance. Using the VersaLogic approved power supply and power cable will ensure high quality power delivery to the board. Customers who design their own power delivery methods should take into consideration the guidelines below to ensure good power connections.
Also note that the 5V @ 21.3W (models S, SR) or 15.5W (models E, ER) typical operating current does not include any off-board power usage that may be fed through the VL- EPM-35 power connector. PC/104 boards on the expansion site and USB devices plugged into the board will source additional 5V power through the VL- EPM-35 power connector.
Do not use wire smaller than 22 AWG. Use high quality UL 1007 compliant stranded wire.
The length of the wire should not exceed 12".
Avoid using any additional connectors in the power delivery system.
The power and ground leads should be twisted together, or as close together as possible to reduce lead inductance.
A separate conductor must be used for each of the power pins.
All 5V pins and all ground pins must be independently connected between the power source and the power connector.
Implement the remote sense feature on your power supply if it has one. Connect the remote sense lines in tandem with one of the power connector 5V and ground pins. This is done at the connector to compensate for losses in the power wires.
Use a high quality power supply that can supply a stable voltage while reacting to widely varying current draws.
VL-EPM-35 Reference Manual 24
Physical Details
L
ITHIUM
B
ATTERY
A lithium battery is mounted on the bottom board of the VL-EPM-35. The I/O connector at JN2 provides a second battery interface. Installing the VL-CBR-3406 breakout board adds a secondary battery, effectively doubling the battery life of the VL-EPM-35. Both batteries are diode protected, so if one is damaged or drained, the other will not be affected.
Warning!
To prevent shorting, premature failure, or damage to the lithium battery, do not place the board on a conductive surface such as metal, black conductive foam, or the outside surface of a metalized ESD protective pouch. The lithium battery may explode if mistreated. Do not recharge, disassemble or dispose of in fire. Dispose of used batteries promptly.
Normal battery voltage should be at least +3V. If the voltage drops below +2V, contact the factory for a replacement (part number HB3/0-1). The life expectancy under normal use is approximately 10 years.
The battery interface uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
CPU
The Intel Core 2 Duo processor combines fast performance, using Intel’s 45nm technology, with advanced power savings features. The SP9300 model used on the VL-EPM-35 has a maximum clock rate of 2.26 GHz and a front side bus speed of 1066 MHz, and features 6 MB of L2 cache.
Other features include DDR3 SDRAM support and an integrated display controller. For more
CPU information see the VL-EPM-35 support page.
VL-EPM-35 Reference Manual 25
Physical Details
System RAM
The VL-EPM-35 has one DDR3 SO-DIMM socket with the following characteristics:
Storage Capacity Up to 4GB
Voltage
Type
1.5V
800 MHz PC3-6400 or 1067 MHz PC3-8500
CMOS RAM
C
LEARING
CMOS RAM
You can install a jumper at VN1 pins 5-6 for a minimum of three seconds to erase the contents of the CMOS RAM and the real-time clock. When clearing CMOS RAM:
1. Power off the VL-EPM-35.
2. Install a jumper on VN1[5-6] and leave it for three seconds.
3. Remove the jumper.
4.
Power on the VL-EPM-35.
CMOS Setup Defaults
The VL-EPM-35 permits users to modify CMOS Setup defaults. This allows the system to boot up with user-defined settings from cleared or corrupted CMOS RAM, battery failure or batteryless operation. All CMOS setup defaults can be changed, except the time and date. CMOS Setup defaults can be updated with the BIOS Update Utility. See the General BIOS Information page for details.
Note:
If CMOS Setup default settings make the system unbootable and prevent the user from entering CMOS Setup, the system can be recovered by switching to the
Backup BIOS.
D
EFAULT
CMOS RAM S
ETUP
V
ALUES
After CMOS RAM is cleared, the system will load default CMOS RAM parameters the next time the board is powered on. The default CMOS RAM setup values will be used in order to boot the system whenever the main CMOS RAM values are blank, or when the system battery is dead or has been removed from the board.
Primary and Backup BIOS
The Primary system BIOS is field upgradeable using the BIOS upgrade utility (see the VL-EPM-
35 Support Page for more information). The Backup BIOS is available if the Primary BIOS becomes corrupted. Jumper VN1[1-2] controls whether the system uses the Primary or Backup
BIOS. By default the Primary BIOS is selected (jumper removed).
VL-EPM-35 Reference Manual 26
Physical Details
Real Time Clock
The VL-EPM-35 features a year 2000-compliant, battery-backed 146818-compatible real-time clock/calendar chip. Under normal battery conditions, the clock maintains accurate timekeeping functions when the board is powered off.
S
ETTING THE
C
LOCK
The CMOS Setup utility (accessed by pressing the Delete key during the early boot cycle) can be used to set the time and date of the real time clock.
Watchdog Timer
A watchdog timer circuit is included on the VL-EPM-35 board to reset the CPU if proper software execution fails or a hardware malfunction occurs.
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire (1000 ms minimum). Writing 5Ah to the WDHOLD register
resets the watchdog timeout period. (See "Special Control Register" and "Watchdog Hold
Register.")
Fan/Tachometer Monitor
The VL-EPM-35 includes a fan/tachometer indicator circuit that can generate an interrupt if the
CPU fan speed drops below 1 Hz. Bit D0 of the FANTACH register enables or disables the fan interrupt. Bit D7 indicates whether the fan is running at or above 1 Hz or below 1Hz. See
"Fan/Tachometer Control Register" for more information.
F
AN
/T
ACH
IRQ C
ODE
E
XAMPLE
#include <stdio.h>
#include <conio.h>
#include <stdlib.h>
#include <graph.h>
#include <dos.h>
//Definitions
#define TRUE 1
#define FALSE 0
#define ESC 27
#define FANREG1 0xC94
#define FANREG2 0xCA4
#define FANIRQEN 0x01
#define SLOWFAN 0x80
//Global Variables
volatile int
int_hit ;
//Function Prototypes
void
( __interrupt __far * old_isr )();
// holds old interrupt handler
void
__interrupt __far chain_isr (
void
);
VL-EPM-35 Reference Manual 27
Physical Details
//Main
void
main ()
{
char
keypressed = 0 ;
int
irq_count = 0 ;
_clearscreen ( _GCLEARSCREEN );
_settextposition ( 2 , 1 ); printf ( "FANTACH IRQ DEMO -- Stop the spinning fan to perform test...\n" );
_settextposition ( 4 , 1 ); printf ( "Setting new ISR for IRQ 7...\n" ); outp ( 0x20 , 0x20 );
//Clear any pending IRQs
old_isr = _dos_getvect ( 0x0F );
//Assign function ptr to old_isr
_dos_setvect ( 0x0F , chain_isr );
//Set new ISR function ptr
outp ( 0x21 , inp ( 0x21 ) & 0x7F );
//unmask IRQ 7 in the PIC
//Ensure slow fan status bit is cleared...
outp ( FANREG1 , inp ( FANREG1 ) | SLOWFAN ); outp ( FANREG2 , inp ( FANREG2 ) | SLOWFAN );
//Enable Slow/Stalled Fan Interrupt output...
outp ( FANREG1 , inp ( FANREG1 ) | FANIRQEN ); outp ( FANREG2 , inp ( FANREG2 ) | FANIRQEN );
_settextposition ( 5 , 1 ); printf ( "Listening for IRQ7...(press ESC to quit)\n" );
while
( keypressed != ESC )
{
if
( kbhit ())
{ keypressed = getch ();
}
//Check for IRQ...
if
( int_hit )
{
_settextposition ( 6 , 1 ); irq_count ++; printf ( "%d Slow/Stalled Fan IRQs Detected!\n" , irq_count ); int_hit = FALSE ;
}
}
_settextposition ( 7 , 1 ); printf ( "Original IRQ7 ISR restored...\n\n" );
_dos_setvect ( 0x0F , old_isr );
//restore original ISR
//Turn off Slow/Stalled Fan IRQ output...
outp ( FANREG1 , inp ( FANREG1 ) & !
FANIRQEN ); outp ( FANREG2 , inp ( FANREG2 ) & !
FANIRQEN ); exit ( 0 );
}
void
__interrupt __far chain_isr (
void
)
VL-EPM-35 Reference Manual 28
Physical Details
{ int_hit = TRUE ;
//clear slow fan status bit...(this will trigger a new IRQ,
//if the fan is still stalled.)
outp ( FANREG1 , inp ( FANREG1 ) | SLOWFAN ); outp ( FANREG2 , inp ( FANREG2 ) | SLOWFAN ); outp ( 0x20 , 0x20 );
//EOI
(* old_isr )();
//call old isr
}
VL-EPM-35 Reference Manual 29
