Hitachi SH7032
Manuals and User Guides for Hitachi SH7032. We found 2 manuals for free downloads User manual
Below you will find brief information for SH7032 and SH7034HD6417032, HD6477034, HD6437034, HD6417034, HD6437034B, HD6417034B. These microprocessors integrate peripheral functions with a 32-bit SH1-DSP CPU core. Features include interrupt controller, timers, serial interfaces, user break controller, bus state controller, DMA controller, and I/O ports. Ideal for high-speed and low-power electronic devices, offering versatile functionalities for diverse application needs.
Key Features
32-bit SH1-DSP CPU core
Integrated interrupt controller
On-chip timers and serial communication interfaces
Direct Memory Access Controller (DMAC)
User Break Controller (UBC)
Bus State Controller (BSC)
Pages: 690 Hitachi SH7032 User manual
Brand: Hitachi Size: 3 MB
Languages: English
Table of contents
- 46 Pin Functions
- 50 Pin Layout by Mode
- 52 Register Configuration
- 52 General Registers (Rn)
- 53 Control Registers
- 54 System Registers
- 54 Initial Values of Registers
- 55 Data Formats
- 55 Data Format in Registers
- 55 Data Format in Memory
- 56 Immediate Data Format
- 56 Instruction Features
- 56 RISC-Type Instruction Set
- 59 Addressing Modes
- 62 Instruction Formats
- 66 Instruction Set
- 66 Instruction Set by Classification
- 77 Operation Code Map
- 80 CPU State
- 80 State Transitions
- 83 Power-Down State
- 84 Types of Operating Modes and Their Selection
- 84 Operating Mode Descriptions
- 84 Mode 0 (MCU Mode 0)
- 84 Mode 1 (MCU Mode 1)
- 84 Mode 2 (MCU Mode 2)
- 84 Mode 7 (PROM Mode)
- 86 Overview
- 86 Exception Handling Types and Priorities
- 88 Exception Handling Operation
- 89 Exception Vector Table
- 91 Resets
- 91 Reset Types
- 92 Power-On Reset
- 92 Manual Reset
- 93 Address Errors
- 93 Address Error Sources
- 93 Address Error Exception Handling
- 94 Interrupts
- 94 Interrupt Sources
- 94 Interrupt Priority Rankings
- 95 Interrupt Exception Handling
- 96 Instruction Exceptions
- 96 Types of Instruction Exceptions
- 96 Trap Instruction
- 97 Illegal Slot Instruction
- 97 General Illegal Instructions
- 98 Cases in which Exceptions are Not Accepted
- 98 Immediately after Delayed Branch Instruction
- 98 Immediately after Interrupt-Disabling Instruction
- 99 Stack Status after Exception Handling
- 100 Notes
- 100 Value of the Stack Pointer (SP)
- 100 Value of the Vector Base Register (VBR)
- 100 Exception Handling
- 102 Overview
- 102 Features
- 102 Block Diagram
- 104 Pin Configuration
- 104 Registers
- 105 Interrupt Sources
- 105 NMI Interrupts
- 105 User Break Interrupt
- 105 IRQ Interrupts
- 106 On-Chip Interrupts
- 106 Interrupt Exception Vectors and Priority Rankings
- 109 Register Descriptions
- 109 Interrupt Priority Registers A–E (IPRA–IPRE)
- 110 Interrupt Control Register (ICR)
- 111 Interrupt Operation
- 111 Interrupt Sequence
- 113 Stack after Interrupt Exception Handling
- 114 Interrupt Response Time
- 115 Usage Notes
- 116 Overview
- 116 Features
- 117 Block Diagram
- 118 Register Configuration
- 119 Register Descriptions
- 119 Break Address Registers (BAR)
- 120 Break Address Mask Register (BAMR)
- 121 Break Bus Cycle Register (BBR)
- 123 Operation
- 123 Flow of User Break Operation
- 125 Break on Instruction Fetch Cycles to On-Chip Memory
- 125 Processing
- 126 Setting User Break Conditions
- 127 Notes
- 127 On-Chip Memory Instruction Fetch
- 127 Instruction Fetch at Branches
- 128 Instruction Fetch Break
- 130 Overview
- 130 Clock Source
- 130 Connecting a Crystal Resonator
- 132 External Clock Input
- 133 Usage Notes
- 136 Overview
- 136 Features
- 137 Block Diagram
- 138 Pin Configuration
- 139 Register Configuration
- 140 Overview of Areas
- 142 Register Descriptions
- 142 Bus Control Register (BCR)
- 144 Wait State Control Register 1 (WCR1)
- 146 Wait State Control Register 2 (WCR2)
- 148 Wait State Control Register 3 (WCR3)
- 149 DRAM Area Control Register (DCR)
- 152 Refresh Control Register (RCR)
- 153 Refresh Timer Control/Status Register (RTCSR)
- 155 Refresh Timer Counter (RTCNT)
- 155 Refresh Time Constant Register (RTCOR)
- 156 8.2.10 Parity Control Register (PCR)
- 158 8.2.11 Notes on Register Access
- 159 Address Space Subdivision
- 159 Address Spaces and Areas
- 161 Bus Width
- 162 Shadows
- 164 Area Descriptions
- 171 Accessing External Memory Space
- 171 Basic Timing
- 173 Wait State Control
- 176 Byte Access Control
- 177 DRAM Interface Operation
- 177 DRAM Address Multiplexing
- 179 Basic Timing
- 181 Wait State Control
- 183 Byte Access Control
- 185 DRAM Burst Mode
- 190 Refresh Control
- 194 Address/Data Multiplexed I/O Space Access
- 194 Basic Timing
- 195 Wait State Control
- 195 Byte Access Control
- 196 Parity Check and Generation
- 197 Warp Mode
- 198 Wait State Control
- 201 8.10 Bus Arbitration
- 202 8.10.1 Operation of Bus Arbitration
- 203 Operation
- 204 8.11 Usage Notes
- 204 8.11.1 Usage Notes on Manual Reset
- 207 8.11.2 Usage Notes on Parity Data Pins DPH and DPL
- 207 Input to Bus Release
- 277 10.2.9 Timer Control Register (TCR)
- 279 10.2.10 Timer I/O Control Register (TIOR)
- 281 10.2.11 Timer Status Register (TSR)
- 282 10.2.12 Timer Interrupt Enable Register (TIER)
- 284 10.3 CPU Interface
- 284 10.3.1 16-Bit Accessible Registers
- 286 10.3.2 8-Bit Accessible Registers
- 287 10.4 Operation
- 287 10.4.1 Overview
- 288 10.4.2 Basic Functions
- 297 10.4.3 Synchronizing Mode
- 299 10.4.4 PWM Mode
- 303 10.4.5 Reset-Synchronized PWM Mode
- 306 10.4.6 Complementary PWM Mode
- 313 10.4.7 Phase Counting Mode
- 315 10.4.8 Buffer Mode
- 320 10.4.9 ITU Output Timing
- 321 10.5 Interrupts
- 321 10.5.1 Timing of Setting Status Flags
- 323 10.5.2 Status Flag Clear Timing
- 324 10.5.3 Interrupt Sources and DMAC Activation
- 325 10.6 Notes and Precautions
- 325 10.6.1 Contention between TCNT Write and Clear
- 326 10.6.2 Contention between TCNT Word Write and Increment
- 327 10.6.3 Contention between TCNT Byte Write and Increment
- 328 10.6.4 Contention between GR Write and Compare Match
- 329 10.6.5 Contention between TCNT Write and Overflow/Underflow
- 330 10.6.6 Contention between General Register Read and Input Capture
- 331 Counter Increment
- 332 10.6.8 Contention between General Register Write and Input Capture
- 332 10.6.9 Note on Waveform Cycle Setting
- 333 10.6.10 Contention between BR Write and Input Capture
- 334 10.6.11 Note on Writing in Synchronizing Mode
- 334 PWM Mode
- 335 10.6.13 Clearing Complementary PWM Mode
- 335 10.6.14 Note on Counter Clearing by Input Capture
- 336 10.6.15 ITU Operating Modes
- 344 11.1 Overview
- 344 11.1.1 Features
- 382 12.4.5 Internal Reset With Watchdog Timer
- 384 13.1 Overview
- 384 13.1.1 Features
- 385 13.1.2 Block Diagram
- 386 13.1.3 Input/Output Pins
- 386 13.1.4 Register Configuration
- 387 13.2 Register Descriptions
- 387 13.2.1 Receive Shift Register
- 387 13.2.2 Receive Data Register
- 388 13.2.3 Transmit Shift Register
- 388 13.2.4 Transmit Data Register
- 389 13.2.5 Serial Mode Register
- 391 13.2.6 Serial Control Register
- 394 13.2.7 Serial Status Register
- 398 13.2.8 Bit Rate Register (BRR)
- 407 13.3 Operation
- 407 13.3.1 Overview
- 409 13.3.2 Operation in Asynchronous Mode
- 420 13.3.3 Multiprocessor Communication
- 428 13.3.4 Synchronous Operation
- 438 13.4 SCI Interrupt Sources and the DMAC
- 438 13.5 Usage Notes
- 442 14.1 Overview
- 442 14.1.1 Features
- 443 14.1.2 Block Diagram
- 444 14.1.3 Configuration of Input Pins
- 445 14.1.4 Configuration of A/D Registers
- 445 14.2 Register Descriptions
- 445 14.2.1 A/D Data Registers A–D (ADDRA–ADDRD)
- 446 14.2.2 A/D Control/Status Register (ADCSR)
- 448 14.2.3 A/D Control Register (ADCR)
- 449 14.3 CPU Interface
- 451 14.4 Operation
- 451 14.4.1 Single Mode (SCAN = 0)
- 453 14.4.2 Scan Mode (SCAN = 1)
- 455 14.4.3 Input Sampling Time and A/D Conversion Time
- 456 14.4.4 A/D Conversion Start by External Trigger Input
- 456 14.5 Interrupts and DMA Transfer Requests
- 457 14.6 Definitions of A/D Conversion Accuracy
- 458 14.7 A/D Converter Usage Notes
- 458 14.7.1 Setting Analog Input Voltage
- 458 14.7.2 Handling of Analog Input Pins
- 459 14.7.3 Switchover between Analog Input and General Port Functions
- 460 15.1 Overview
- 462 15.2 Register Configuration
- 462 15.3 Register Descriptions
- 462 15.3.1 Port A I/O Register (PAIOR)
- 463 15.3.2 Port A Control Registers (PACR1 and PACR2)
- 468 15.3.3 Port B I/O Register (PBIOR)
- 469 15.3.4 Port B Control Registers (PBCR1 and PBCR2)
- 474 15.3.5 Column Address Strobe Pin Control Register (CASCR)
- 476 16.1 Overview
- 476 16.2 Port A
- 476 16.2.1 Register Configuration
- 477 16.2.2 Port A Data Register (PADR)
- 478 16.3 Port B
- 478 16.3.1 Register Configuration
- 479 16.3.2 Port B Data Register (PBDR)
- 480 16.4 Port C
- 480 16.4.1 Register Configuration
- 481 16.4.2 Port C Data Register (PCDR)
- 482 17.1 Overview
- 483 17.2 PROM Mode
- 483 17.2.1 Setting PROM Mode
- 483 17.2.2 Socket Adapter Pin Correspondence and Memory Map
- 485 17.3 PROM Programming
- 485 17.3.1 Selecting the Programming Mode
- 486 17.3.2 Write/Verify and Electrical Characteristics
- 490 17.3.3 Notes on Writing
- 491 17.3.4 Reliability after Writing
- 492 18.1 Overview
- 493 18.2 Operation
- 494 19.1 Overview
- 494 19.1.1 Power-Down Modes
- 495 19.1.2 Register
- 495 19.2 Standby Control Register (SBYCR)
- 496 19.3 Sleep Mode
- 496 19.3.1 Transition to Sleep Mode
- 496 19.3.2 Exiting Sleep Mode
- 496 19.4 Standby Mode
- 496 19.4.1 Transition to Standby Mode
- 498 19.4.2 Exiting Standby Mode
- 498 19.4.3 Standby Mode Application
- 500 20.1 SH7032 and SH7034 Electrical Characteristics
- 500 20.1.1 Absolute Maximum Ratings
- 500 20.1.2 DC Characteristics
- 507 20.1.3 AC Characteristics
- 507 Clock Timing
- 509 Control Signal Timing
- 512 Bus Timing
- 542 DMAC Timing
- 544 16-bit Integrated Timer Pulse Unit Timing
- 545 Programmable Timing Pattern Controller and I/O Port Timing
- 546 Watchdog Timer Timing
- 547 Serial Communication Interface Timing
- 548 A/D Converter Timing
- 550 AC Characteristics Test Conditions
- 551 20.1.4 A/D Converter Characteristics
- 552 20.2 SH7034B 3.3 V 12.5 MHz Version and 20 MHz Version Electrical Characteristics
- 552 20.2.1 Absolute Maximum Ratings
- 552 20.2.2 DC Characteristics
- 557 20.2.3 AC Characteristics
- 557 Clock Timing
- 559 Control Signal Timing
- 562 Bus Timing
- 581 DMAC Timing
- 582 16-bit Integrated Timer Pulse Unit Timing
- 583 Programmable Timing Pattern Controller and I/O Port Timing
- 584 Watchdog Timer Timing
- 585 Serial Communication Interface Timing
- 586 A/D Converter Timing
- 588 AC Characteristics Test Conditions
- 589 20.2.4 A/D Converter Characteristics
- 590 A.1List of Registers
- 600 Register Tables
- 600 A.2.1 Serial Mode Register (SMR) SCI
- 601 A.2.2 Bit Rate Register (BRR) SCI
- 601 A.2.3 Serial Control Register (SCR) SCI
- 603 A.2.4 Transmit Data Register (TDR) SCI
- 603 A.2.5 Serial Status Register (SSR) SCI
- 605 A.2.6 Receive Data Register (RDR) SCI
- 606 A.2.7 A/D Data Register AH–DL (ADDRAH–ADDRL) A/D
- 606 A.2.8 A/D Control/Status Register (ADCSR) A/D
- 608 A.2.9 A/D Control Register (ADCR) A/D
- 608 A.2.10 Timer Start Register (TSTR) ITU
- 609 A.2.11 Timer Synchronization Register (TSNC) ITU
- 611 A.2.12 Timer Mode Register (TMDR) ITU
- 612 A.2.13 Timer Function Control Register (TFCR) ITU
- 613 A.2.14 Timer Control Registers 0–4 (TCR0–TCR4) ITU
- 614 A.2.15 Timer I/O Control Registers 0–4 (TIOR0–TIOR4) ITU
- 615 A.2.16 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4) ITU
- 616 A.2.17 Timer Status Registers 0–4 (TSR0–TSR4) ITU
- 617 A.2.18 Timer Counter 0–4 (TCNT0–TCNT4) ITU
- 618 A.2.19 General Registers A0–4 (GRA0–GRA4) ITU
- 619 A.2.20 General Registers B0–4 (GRB0–GRB4) ITU
- 620 A.2.21 Buffer Registers A3, 4 (BRA3, BRA4) ITU
- 621 A.2.22 Buffer Registers B3, 4 (BRB3, BRB4) ITU
- 622 A.2.23 Timer Output Control Register (TOCR) ITU
- 623 A.2.24 DMA Source Address Registers 0–3 (SAR0–SAR3) DMAC
- 624 A.2.25 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMAC
- 625 A.2.26 DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMAC
- 626 A.2.27 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMAC
- 629 A.2.28 DMA Operation Registers (DMAOR) DMAC
- 630 A.2.29 Interrupt Priority Setting Register A (IPRA) INTC
- 631 A.2.30 Interrupt Priority Setting Register B (IPRB) INTC
- 632 A.2.31 Interrupt Priority Setting Register C (IPRC) INTC
- 633 A.2.32 Interrupt Priority Setting Register D (IPRD) INTC
- 634 A.2.33 Interrupt Priority Setting Register E (IPRE) INTC
- 635 A.2.34 Interrupt Control Register (ICR) INTC
- 636 A.2.35 Break Address Register H (BARH) UBC
- 637 A.2.36 Break Address Register L (BARL) UBC
- 638 A.2.37 Break Address Mask Register H (BAMRH) UBC
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Frequently Answers and Questions
What is the purpose of the Bus State Controller (BSC)?
The BSC manages memory space division, DRAM interface, refresh operations, wait state control, and parity control.
What are the key features of the Interrupt Controller (INTC)?
The INTC supports NMI interrupts, user break interrupts, IRQ interrupts, and on-chip module interrupts.
What type of memory chips does it support?
It supports flash memory and SRAM, but does not support DRAM.
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