Mentor Graphics 6.2g ModelSim
Manuals and User Guides for Mentor Graphics 6.2g ModelSim. We found 1 manuals for free downloads User's manual
Below you will find brief information for 6.2g ModelSim. It is a simulation software, which allows you to test and verify your hardware designs before implementation. It supports multiple hardware description languages (HDLs) including VHDL, Verilog and SystemVerilog, and provides features like waveform visualization, debugging tools, and advanced simulation capabilities.
Key Features
Supports VHDL, Verilog and SystemVerilog
Waveform visualization
Debugging tools
Advanced simulation capabilities
Project management
Design library management
Standard Delay Format (SDF) timing annotation
Pages: 450 Mentor Graphics 6.2g ModelSim User's manual
Brand: Mentor Graphics Category: Software Size: 3 MB
Languages: English
Table of contents
- 3 Table of Contents
- 14 List of Examples
- 15 List of Figures
- 18 List of Tables
- 21 Chapter 1 Introduction
- 21 Tool Structure and Flow
- 22 Simulation Task Overview
- 23 Basic Steps for Simulation
- 24 Step 1 - Collecting Files and Mapping Libraries
- 24 Providing Stimulus to the Design
- 24 What is a Library?
- 24 Working and Resource Libraries
- 25 Creating the Logical Library (vlib)
- 25 Mapping the Logical Work to the Physical Work Directory (vmap)
- 25 Step 2 - Compiling the Design (vlog, vcom, sccom)
- 25 Compiling Verilog (vlog)
- 25 Compiling VHDL (vcom)
- 26 Step 3 - Loading the Design for Simulation
- 26 vsim topLevelModule
- 26 Using SDF
- 26 Step 4 - Simulating the Design
- 26 Step 5 - Debugging the Design
- 27 Modes of Operation
- 27 Command Line Mode
- 28 Batch Mode
- 28 Standards Supported
- 29 Assumptions
- 29 Sections In This Document
- 30 What is an "Object"
- 31 Text Conventions
- 31 Installation Directory Pathnames
- 33 Chapter 2 Simulator Windows
- 35 Design Object Icons and Their Meaning
- 35 Setting Fonts
- 35 Font Scaling
- 36 Controlling Fonts in an X-session
- 36 Main Window
- 37 Workspace
- 38 Transcript
- 39 Saving the Transcript File
- 39 Using the Saved Transcript as a Macro (DO file)
- 39 Changing the Number of Lines Saved in the Transcript Window
- 39 Disabling Creation of the Transcript File
- 39 Automatic Command Help
- 40 Message Viewer
- 40 Controlling the Message Viewer Data
- 40 Message Viewer Interface and Tasks
- 41 Multiple Document Interface (MDI) Frame
- 42 Organizing Windows with Tab Groups
- 43 Navigating in the Main Window
- 44 Main Window Status Bar
- 45 Main Window Toolbar
- 47 Active Processes Pane
- 48 Process Status
- 48 Call Stack Pane
- 49 Dataflow Window
- 50 Dataflow Window Toolbar
- 53 List Window
- 55 Locals Pane
- 56 Memory Panes
- 57 Associative Arrays in Verilog/SystemVerilog
- 57 Viewing Single and Multidimensional Memories
- 57 Viewing Packed Arrays
- 57 Viewing Memory Contents
- 57 Viewing Multiple Memory Instances
- 58 Saving Memory Formats in a DO File
- 58 Direct Address Navigation
- 58 Splitting the Memory Contents Pane
- 60 Objects Pane
- 60 Filtering the Objects List
- 60 Filtering by Name
- 61 Filtering by Signal Type
- 62 Source Window
- 62 Opening Source Files
- 63 Displaying Multiple Source Files
- 63 Dragging and Dropping Objects into the Wave and List Windows
- 64 Setting your Context by Navigating Source Files
- 65 Language Templates
- 67 Setting File-Line Breakpoints
- 67 Checking Object Values and Descriptions
- 68 Marking Lines with Bookmarks
- 68 Customizing the Source Window
- 70 Watch Pane
- 70 Adding Objects to the Pane
- 70 Expanding Objects to Show Individual Bits
- 71 Grouping and Ungrouping Objects
- 71 Saving and Reloading Format Files
- 72 Wave Window
- 75 Wave Window Panes
- 75 Pathname Pane
- 75 Value Pane
- 75 Waveform Pane
- 76 Cursor Panes
- 76 Wave Window Toolbar
- 81 Chapter 3 Projects
- 81 What are Projects?
- 81 What are the Benefits of Projects?
- 82 Project Conversion Between Versions
- 82 Getting Started with Projects
- 83 Step 1 - Creating a New Project
- 84 Step 2 - Adding Items to the Project
- 84 Create New File
- 85 Add Existing File
- 85 Step 3 - Compiling the Files
- 86 Step 4 - Simulating a Design
- 88 Other Basic Project Operations
- 88 Open an Existing Project
- 88 Close a Project
- 88 The Project Tab
- 89 Sorting the List
- 89 Changing Compile Order
- 90 Auto-Generating Compile Order
- 90 Grouping Files
- 91 Creating a Simulation Configuration
- 92 Organizing Projects with Folders
- 92 Adding a Folder
- 94 Specifying File Properties and Project Settings
- 94 File Compilation Properties
- 96 Project Settings
- 96 Converting Pathnames to Softnames for Location Mapping
- 97 Accessing Projects from the Command Line
- 99 Chapter 4 Design Libraries
- 99 Design Library Overview
- 99 Design Unit Information
- 99 Working Library Versus Resource Libraries
- 100 The Library Named "work"
- 100 Archives
- 100 Working with Design Libraries
- 101 Creating a Library
- 101 Managing Library Contents
- 102 Assigning a Logical Name to a Design Library
- 103 Library Mappings with the GUI
- 103 Library Mapping from the Command Line
- 104 Unix Symbolic Links
- 104 Library Search Rules
- 104 Moving a Library
- 104 Setting Up Libraries for Group Use
- 105 Specifying the Resource Libraries
- 105 Verilog Resource Libraries
- 105 VHDL Resource Libraries
- 105 Predefined Libraries
- 106 Alternate IEEE Libraries Supplied
- 106 Regenerating Your Design Libraries
- 107 Maintaining 32- and 64-bit Versions in the Same Library
- 107 Importing FPGA Libraries
- 109 Chapter 5 VHDL Simulation
- 109 Basic VHDL Flow
- 109 Compiling VHDL Files
- 109 Creating a Design Library for VHDL
- 110 Invoking the VHDL Compiler
- 110 Dependency Checking
- 110 Range and Index Checking
- 110 Subprogram Inlining
- 111 mti_inhibit_inline Attribute
- 111 Differences Between Language Versions
- 114 Simulating VHDL Designs
- 114 Simulator Resolution Limit (VHDL)
- 114 Overriding the Resolution
- 115 Choosing the Resolution for VHDL
- 115 Default Binding
- 115 Default Binding Rules
- 116 Disabling Default Binding
- 116 Delta Delays
- 118 Detecting Infinite Zero-Delay Loops
- 118 Using the TextIO Package
- 119 Syntax for File Declaration
- 119 Using STD_INPUT and STD_OUTPUT Within the Tool
- 120 TextIO Implementation Issues
- 120 Writing Strings and Aggregates
- 121 Reading and Writing Hexadecimal Numbers
- 121 Dangling Pointers
- 121 The ENDLINE Function
- 122 The ENDFILE Function
- 122 Using Alternative Input/Output Files
- 122 Flushing the TEXTIO Buffer
- 122 Providing Stimulus
- 123 VITAL Specification and Source Code
- 123 VITAL Packages
- 124 VITAL Compliance
- 124 VITAL Compliance Checking
- 124 Compiling and Simulating with Accelerated VITAL Packages
- 124 Util Package
- 125 get_resolution
- 125 init_signal_driver()
- 125 init_signal_spy()
- 126 signal_force()
- 126 signal_release()
- 126 to_real()
- 127 to_time()
- 128 Modeling Memory
- 129 VHDL87 and VHDL93 Example
- 132 VHDL02 example
- 136 Affecting Performance by Cancelling Scheduled Events
- 136 Converting an Integer Into a bit_vector
- 139 Chapter 6 Verilog and SystemVerilog Simulation
- 139 Terminology
- 139 Basic Verilog Flow
- 139 Compiling Verilog Files
- 140 Creating a Working Library
- 140 Invoking the Verilog Compiler
- 140 Parsing SystemVerilog Keywords
- 141 Incremental Compilation
- 143 Automatic Incremental Compilation with -incr
- 144 Library Usage
- 144 Library Search Rules for vlog
- 144 Handling Sub-Modules with Common Names
- 145 SystemVerilog Multi-File Compilation Issues
- 145 Declarations in Compilation Unit Scope
- 146 Macro Definitions and Compiler Directives in Compilation Unit Scope
- 146 Verilog-XL Compatible Compiler Arguments
- 147 Arguments Supporting Source Libraries
- 147 Verilog-XL uselib Compiler Directive
- 148 -compile_uselibs Argument
- 149 uselib is Persistent
- 149 Verilog Configurations
- 150 Configurations and the Library Named work
- 150 Verilog Generate Statements
- 150 Name Visibility in Generate Statements
- 151 Simulating Verilog Designs
- 151 Simulator Resolution Limit (Verilog)
- 152 Modules Without Timescale Directives
- 153 -timescale Option
- 153 Multiple Timescale Directives
- 153 timescale, -t, and Rounding
- 154 Choosing the Resolution for Verilog
- 154 Event Ordering in Verilog Designs
- 154 Event Queues
- 156 Controlling Event Queues with Blocking or Non-Blocking Assignments
- 156 Blocking Assignments
- 157 Non-Blocking Assignments
- 157 Debugging Event Order Issues
- 158 Hazard Detection
- 158 Hazard Detection and Optimization Levels
- 158 Limitations of Hazard Detection
- 159 Negative Timing Check Limits
- 159 Negative Timing Constraint Algorithm
- 159 Using Delayed Inputs for Timing Checks
- 160 Verilog-XL Compatible Simulator Arguments
- 161 Using Escaped Identifiers
- 162 Cell Libraries
- 162 SDF Timing Annotation
- 162 Delay Modes
- 163 Distributed Delay Mode
- 163 Path Delay Mode
- 163 Unit Delay Mode
- 163 Zero Delay Mode
- 163 System Tasks and Functions
- 164 IEEE Std 1364 System Tasks and Functions
- 166 SystemVerilog System Tasks and Functions
- 167 System Tasks and Functions Specific to the Tool
- 168 Verilog-XL Compatible System Tasks and Functions
- 168 Supported Tasks and Functions Mentioned in IEEE Std 1364
- 168 Supported Tasks not Described in the IEEE Std 1364
- 169 Supported Tasks that Have Been Extended
- 170 Unsupported Verilog-XL System Tasks
- 171 Compiler Directives
- 171 IEEE Std 1364 Compiler Directives
- 172 Verilog-XL Compatible Compiler Directives
- 173 Verilog PLI/VPI and SystemVerilog DPI
- 175 Chapter 7 WLF Files (Datasets) and Virtuals
- 176 Saving a Simulation to a WLF File
- 177 WLF File Parameter Overview
- 178 Opening Datasets
- 179 Viewing Dataset Structure
- 179 Structure Tab Columns
- 180 Managing Multiple Datasets
- 180 GUI
- 180 Command Line
- 181 Restricting the Dataset Prefix Display
- 182 Saving at Intervals with Dataset Snapshot
- 182 Collapsing Time and Delta Steps
- 183 Virtual Objects
- 184 Virtual Signals
- 185 Implicit and Explicit Virtuals
- 185 Virtual Functions
- 186 Virtual Regions
- 186 Virtual Types
- 187 Chapter 8 Waveform Analysis
- 187 Objects You Can View
- 187 Wave Window Overview
- 190 List Window Overview
- 191 Adding Objects to the Wave or List Window
- 191 Adding Objects with Drag and Drop
- 191 Adding Objects with a Menu Command
- 191 Adding Objects with a Command
- 192 Adding Objects with a Window Format File
- 192 Measuring Time with Cursors in the Wave Window
- 193 Working with Cursors
- 194 Shortcuts for Working with Cursors
- 194 Understanding Cursor Behavior
- 195 Jumping to a Signal Transition
- 195 Setting Time Markers in the List Window
- 195 Working with Markers
- 196 Zooming the Wave Window Display
- 196 Zooming with the Menu, Toolbar and Mouse
- 197 Saving Zoom Range and Scroll Position with Bookmarks
- 197 Managing Bookmarks
- 197 Adding Bookmarks
- 198 Editing Bookmarks
- 198 Searching in the Wave and List Windows
- 198 Finding Signal Names
- 199 Searching for Values or Transitions
- 200 Using the Expression Builder for Expression Searches
- 201 Saving an Expression to a Tcl Variable
- 201 Searching for when a Signal Reaches a Particular Value
- 202 Evaluating Only on Clock Edges
- 202 Operators
- 202 Formatting the Wave Window
- 202 Setting Wave Window Display Preferences
- 203 Hiding/Showing Path Hierarchy
- 203 Setting the Timeline to Count Clock Cycles
- 204 Formatting Objects in the Wave Window
- 205 Changing Radix (base) for the Wave Window
- 206 Dividing the Wave Window
- 207 Working with Dividers
- 207 Splitting Wave Window Panes
- 208 The Active Split
- 208 Wave Groups
- 208 Creating a Wave Group
- 210 Deleting or Ungrouping a Wave Group
- 210 Adding Items to an Existing Wave Group
- 210 Removing Items from an Existing Wave Group
- 210 Miscellaneous Wave Group Features
- 211 Formatting the List Window
- 211 Setting List Window Display Properties
- 211 Formatting Objects in the List Window
- 211 Changing Radix (base) for the List Window
- 213 Saving the Window Format
- 214 Printing and Saving Waveforms in the Wave window
- 214 Saving a .eps Waveform File and Printing in UNIX
- 214 Printing from the Wave Window on Windows Platforms
- 214 Printer Page Setup
- 214 Saving List Window Data to a File
- 215 Combining Objects into Buses
- 217 Configuring New Line Triggering in the List Window
- 219 Using Gating Expressions to Control Triggering
- 219 Trigger Gating Example Using the Expression Builder
- 220 Trigger Gating Example Using Commands
- 221 Sampling Signals at a Clock Change
- 221 Miscellaneous Tasks
- 221 Examining Waveform Values
- 221 Displaying Drivers of the Selected Waveform
- 222 Sorting a Group of Objects in the Wave Window
- 222 Creating and managing breakpoints
- 222 Signal breakpoints
- 222 Setting signal breakpoints from the command line
- 222 Setting signal breakpoints from the GUI
- 222 File-line breakpoints
- 222 Setting file-line breakpoints from the command line
- 222 Setting file-line breakpoints from the GUI
- 225 Chapter 9 Tracing Signals with the Dataflow Window
- 225 Dataflow Window Overview
- 225 Objects You Can View in the Dataflow Window
- 226 Adding Objects to the Window
- 226 Links to Other Windows
- 227 Exploring the Connectivity of the Design
- 228 Tracking Your Path Through the Design
- 228 The Embedded Wave Viewer
- 229 Zooming and Panning
- 230 Panning with the Mouse
- 230 Tracing Events (Causality)
- 231 Tracing the Source of an Unknown State (StX)
- 232 Finding Objects by Name in the Dataflow Window
- 233 Printing and Saving the Display
- 233 Saving a .eps File and Printing the Dataflow Display from UNIX
- 234 Printing from the Dataflow Display on Windows Platforms
- 235 Configuring Page Setup
- 235 Symbol Mapping
- 236 User-defined symbols
- 237 Configuring Window Options
- 239 Chapter 10 Signal Spy
- 239 Designed for Testbenches
- 241 disable_signal_spy
- 242 enable_signal_spy
- 243 init_signal_driver
- 245 init_signal_spy
- 248 signal_force
- 250 signal_release
- 252 $disable_signal_spy
- 253 $enable_signal_spy
- 254 $init_signal_driver
- 256 $init_signal_spy
- 258 $signal_force
- 260 $signal_release
- 263 Chapter 11 Standard Delay Format (SDF) Timing Annotation
- 263 Specifying SDF Files for Simulation
- 263 Instance Specification
- 264 SDF Specification with the GUI
- 264 Errors and Warnings
- 265 VHDL VITAL SDF
- 265 SDF to VHDL Generic Matching
- 265 Resolving Errors
- 266 Verilog SDF
- 267 $sdf_annotate
- 268 SDF to Verilog Construct Matching
- 271 Optional Edge Specifications
- 272 Optional Conditions
- 273 Rounded Timing Values
- 273 SDF for Mixed VHDL and Verilog Designs
- 273 Interconnect Delays
- 274 Disabling Timing Checks
- 274 Troubleshooting
- 274 Specifying the Wrong Instance
- 274 VHDL Testbench
- 275 Verilog Testbench
- 275 Mistaking a Component or Module Name for an Instance Label
- 275 Forgetting to Specify the Instance
- 277 Chapter 12 Value Change Dump (VCD) Files
- 277 Creating a VCD File
- 277 Flow for Four-State VCD File
- 278 Flow for Extended VCD File
- 278 Case Sensitivity
- 278 Using Extended VCD as Stimulus
- 278 Simulating with Input Values from a VCD File
- 280 Replacing Instances with Output Values from a VCD File
- 280 Port Order Issues
- 281 VCD Commands and VCD Tasks
- 282 Compressing Files with VCD Tasks
- 282 VCD File from Source To Output
- 282 VHDL Source Code
- 283 VCD Simulator Commands
- 283 VCD Output
- 286 Capturing Port Driver Data
- 286 Driver States
- 287 Driver Strength
- 288 Identifier Code
- 288 Resolving Values
- 288 Default Behavior
- 289 Ignoring Strength Ranges
- 289 Extended $dumpports Syntax
- 293 Chapter 13 Tcl and Macros (DO Files)
- 293 Tcl Features
- 293 Tcl References
- 293 Tcl Commands
- 294 Tcl Command Syntax
- 297 If Command Syntax
- 297 Command Substitution
- 298 Command Separator
- 298 Multiple-Line Commands
- 298 Evaluation Order
- 298 Tcl Relational Expression Evaluation
- 299 Variable Substitution
- 299 System Commands
- 300 List Processing
- 300 Simulator Tcl Commands
- 301 Simulator Tcl Time Commands
- 302 Conversions
- 302 Relations
- 303 Arithmetic
- 303 Tcl Examples
- 307 Macros (DO Files)
- 307 Creating DO Files
- 308 Using Parameters with DO Files
- 308 Deleting a File from a .do Script
- 309 Making Macro Parameters Optional
- 309 Example 1
- 309 Example 2
- 309 Example 3
- 310 Useful Commands for Handling Breakpoints and Errors
- 311 Error Action in DO Files
- 311 Using the Tcl Source Command with DO Files
- 313 Appendix A Simulator Variables
- 313 Variable Settings Report
- 313 Environment Variables
- 313 Environment Variable Expansion
- 314 Setting Environment Variables
- 314 DOPATH
- 314 EDITOR
- 314 HOME
- 314 HOME_0IN
- 315 LD_LIBRARY_PATH
- 315 LD_LIBRARY_PATH_32
- 315 LD_LIBRARY_PATH_64
- 315 LM_LICENSE_FILE
- 315 MODEL_TECH
- 315 MODEL_TECH_TCL
- 315 MGC_LOCATION_MAP
- 315 MODELSIM
- 316 MODELSIM_PREFERENCES
- 316 MODELSIM_TCL
- 316 MTI_COSIM_TRACE
- 316 MTI_TF_LIMIT
- 316 MTI_RELEASE_ON_SUSPEND
- 317 MTI_USELIB_DIR
- 317 NOMMAP
- 317 PLIOBJS
- 317 STDOUT
- 317 TMP
- 317 TMPDIR
- 317 Creating Environment Variables in Windows
- 318 Library Mapping with Environment Variables
- 318 Referencing Environment Variables
- 319 Removing Temp Files (VSOUT)
- 319 Simulator Control Variables
- 319 Library Path Variables
- 319 ieee
- 320 modelsim_lib
- 320 std
- 320 std_developerskit
- 320 synopsys
- 320 sv_std
- 320 verilog
- 321 vital2000
- 321 others
- 321 Verilog Compiler Control Variables
- 321 DisableOpt
- 321 GenerateLoopIterationMax
- 321 GenerateRecursionDepthMax
- 322 Hazard
- 322 Incremental
- 322 MultiFileCompilationUnit
- 322 NoDebug
- 322 Quiet
- 323 Show_BadOptionWarning
- 323 Show_Lint
- 323 Show_WarnCantDoCoverage
- 323 Show_WarnMatchCadence
- 323 Show_source
- 323 vlog95compat
- 324 VHDL Compiler Control Variables
- 324 BindAtCompile
- 324 CheckSynthesis
- 324 DisableOpt
- 324 Explicit
- 324 IgnoreVitalErrors
- 325 NoCaseStaticError
- 325 NoDebug
- 325 NoIndexCheck
- 325 NoOthersStaticError
- 325 NoRangeCheck
- 325 NoVital
- 326 NoVitalCheck
- 326 Optimize_1164
- 326 PedanticErrors
- 326 Quiet
- 326 RequireConfigForAllDefaultBinding
- 326 Show_Lint
- 326 Show_source
- 327 Show_VitalChecksOpt
- 327 Show_VitalChecksWarnings
- 327 Show_WarnCantDoCoverage
- 327 Show_Warning1
- 327 Show_Warning2
- 327 Show_Warning3
- 328 Show_Warning4
- 328 Show_Warning5
- 328 Show_Warning9
- 328 Show_Warning10
- 328 Show_WarnLocallyStaticError
- 328 VHDL93
- 329 Simulation Control Variables
- 329 AssertFile
- 329 AssertionDebug
- 329 AssertionFormat
- 330 AssertionFormatBreak
- 330 AssertionFormatError
- 330 AssertionFormatFail
- 330 AssertionFormatFatal
- 330 AssertionFormatNote
- 331 AssertionFormatWarning
- 331 BreakOnAssertion
- 331 CheckPlusargs
- 331 CheckpointCompressMode
- 331 CommandHistory
- 332 ConcurrentFileLimit
- 332 DatasetSeparator
- 332 DefaultForceKind
- 332 DefaultRadix
- 333 DefaultRestartOptions
- 333 DelayFileOpen
- 333 DumpportsCollapse
- 333 GenerateFormat
- 333 GlobalSharedObjectsList
- 333 IgnoreError
- 334 IgnoreFailure
- 334 IgnoreNote
- 334 IgnoreWarning
- 334 IterationLimit
- 335 License
- 335 LockedMemory
- 335 MaxReportRhsCrossProducts
- 336 NumericStdNoWarnings
- 336 OnFinish
- 336 PathSeparator
- 336 PrintSimStats
- 337 Resolution
- 337 RunLength
- 337 ShowFunctions
- 337 SignalSpyPathSeparator
- 338 Startup
- 338 StdArithNoWarnings
- 338 ToggleMaxIntValues
- 338 TranscriptFile
- 338 UnbufferedOutput
- 338 UseCsupV2
- 339 UserTimeUnit
- 339 Veriuser
- 339 WarnConstantChange
- 339 WaveSignalNameWidth
- 339 WLFCacheSize
- 340 WLFCollapseMode
- 340 WLFCompress
- 340 WLFDeleteOnQuit
- 340 WLFFilename
- 340 WLFOptimize
- 340 WLFSaveAllRegions
- 341 WLFSizeLimit
- 341 WLFTimeLimit
- 342 Setting Simulator Control Variables With The GUI
- 344 Message System Variables
- 345 error
- 345 fatal
- 345 note
- 345 suppress
- 345 warning
- 345 msgmode
- 346 Commonly Used INI Variables
- 346 Common Environment Variables
- 346 Hierarchical Library Mapping
- 346 Creating a Transcript File
- 347 Using a Startup File
- 347 Turning Off Assertion Messages
- 347 Turning off Warnings from Arithmetic Packages
- 348 Force Command Defaults
- 348 Restart Command Defaults
- 348 VHDL Standard
- 348 Opening VHDL Files
- 349 Variable Precedence
- 349 Simulator State Variables
- 349 argc
- 349 architecture
- 349 configuration
- 349 delta
- 349 entity
- 349 library
- 350 MacroNestingLevel
- 350 n
- 350 Now
- 350 now
- 350 resolution
- 350 Referencing Simulator State Variables
- 350 Special Considerations for the now Variable
- 353 Appendix B Location Mapping
- 353 Referencing Source Files with Location Maps
- 353 Using Location Mapping
- 354 Pathname Syntax
- 354 How Location Mapping Works
- 354 Mapping with TCL Variables
- 355 Appendix C Error and Warning Messages
- 355 Message System
- 355 Message Format
- 355 Getting More Information
- 356 Changing Message Severity Level
- 356 Suppressing Warning Messages
- 356 Suppressing VCOM Warning Messages
- 357 Suppressing VLOG Warning Messages
- 357 Suppressing VSIM Warning Messages
- 357 Exit Codes
- 359 Miscellaneous Messages
- 362 Enforcing Strict 1076 Compliance
- 365 Appendix D Verilog PLI/VPI/DPI
- 365 Implementation Information
- 365 g++ Compiler Support for use with PLI/VPI/DPI
- 365 Specifying Your Own g++ Compiler
- 366 Registering PLI Applications
- 367 Registering VPI Applications
- 369 Using PLI and VPI Together
- 369 Registering DPI Applications
- 370 DPI Use Flow
- 371 When Your DPI Export Function is Not Getting Called
- 371 Simplified Import of FLI / PLI / C Library Functions
- 372 Use Model for Read-Only Work Libraries
- 373 Compiling and Linking C Applications for PLI/VPI/DPI
- 374 For all UNIX Platforms
- 374 app.so
- 374 Correct Linking of Shared Libraries with -Bsymbolic
- 374 Windows Platforms
- 375 DPI Imports on Windows Platforms
- 375 DPI Flow for Exported Tasks and Functions on Windows Platforms
- 376 32-bit Linux Platform
- 376 64-bit Linux for IA64 Platform
- 376 64-bit Linux for Opteron/Athlon 64 and EM64T Platforms
- 377 32-bit Solaris Platform
- 377 64-bit Solaris Platform
- 377 32-bit HP700 Platform
- 378 64-bit HP Platform
- 378 64-bit HP for IA64 Platform
- 378 32-bit IBM RS/6000 Platform
- 379 DPI Imports on 32-bit IBM RS/6000 Platform
- 379 DPI Flow for Exported Tasks and Functions on 32-bit IBM RS/6000 Platform
- 379 64-bit IBM RS/6000 Platform
- 379 DPI Imports on 64-bit IBM RS/6000 Platform
- 380 DPI Flow for Exported Tasks and Functions on 64-bit IBM RS/6000 Platform
- 380 Compiling and Linking C++ Applications for PLI/VPI/DPI
- 380 For PLI/VPI only
- 381 Windows Platforms
- 381 DPI Imports on Windows Platforms
- 381 DPI Special Flow for Exported Tasks and Functions
- 382 32-bit Linux Platform
- 382 64-bit Linux for IA64 Platform
- 382 64-bit Linux for Opteron/Athlon 64 and EM64T Platforms
- 383 32-bit Solaris Platform
- 383 64-bit Solaris Platform
- 383 32-bit HP700 Platform
- 384 64-bit HP Platform
- 384 64-bit HP for IA64 Platform
- 384 32-bit IBM RS/6000 Platform
- 385 For DPI Imports
- 385 DPI Special Flow for Exported Tasks and Functions
- 385 64-bit IBM RS/6000 Platform
- 385 For DPI Imports
- 385 DPI Special Flow for Exported Tasks and Functions
- 386 Specifying Application Files to Load
- 386 PLI/VPI file loading
- 387 DPI File Loading
- 387 Loading Shared Objects with Global Symbol Visibility
- 387 PLI Example
- 388 VPI Example
- 389 DPI Example
- 390 The PLI Callback reason Argument
- 391 The sizetf Callback Function
- 392 PLI Object Handles
- 392 Third Party PLI Applications
- 393 Support for VHDL Objects
- 395 IEEE Std 1364 ACC Routines
- 397 IEEE Std 1364 TF Routines
- 397 SystemVerilog DPI Access Routines
- 398 Verilog-XL Compatible Routines
- 398 64-bit Support for PLI
- 398 Using 64-bit ModelSim with 32-bit Applications
- 398 PLI/VPI Tracing
- 399 The Purpose of Tracing Files
- 399 Invoking a Trace
- 399 Syntax
- 399 Arguments
- 399 Examples
- 400 Debugging PLI/VPI/DPI Application Code
- 400 Troubleshooting a Missing DPI Import Function
- 401 HP-UX Specific Warnings
- 403 Appendix E Command and Keyboard Shortcuts
- 403 Command Shortcuts
- 403 Command History Shortcuts
- 404 Main and Source Window Mouse and Keyboard Shortcuts
- 407 List Window Keyboard Shortcuts
- 408 Wave Window Mouse and Keyboard Shortcuts
- 411 Appendix F Setting GUI Preferences
- 411 Customizing the Simulator GUI Layout
- 411 Layouts and Modes of Operation
- 411 Custom Layouts
- 411 Creating Custom Layouts
- 412 Assigning Layouts to Modes
- 413 Automatic Saving of Layouts
- 413 Resetting Layouts to Their Defaults
- 413 Navigating the Graphic User Interface
- 413 Manipulating Panes
- 414 Moving Panes
- 414 Docking and Undocking Panes
- 414 Zooming Panes
- 415 Columnar Information Display
- 415 Quick Access Toolbars
- 415 Simulator GUI Preferences
- 416 Setting Preference Variables from the GUI
- 417 Saving GUI Preferences
- 417 The modelsim.tcl File
- 419 Appendix G System Initialization
- 419 Files Accessed During Startup
- 420 Environment Variables Accessed During Startup
- 421 Initialization Sequence
- 425 Index
- 443 Third-Party Information
- 447 End-User License Agreement
Frequently Answers and Questions
What hardware description languages does ModelSim support?
ModelSim supports VHDL, Verilog and SystemVerilog.
What are the key features of ModelSim?
ModelSim provides features like waveform visualization, debugging tools, and advanced simulation capabilities. It also has features for project management, design library management, and Standard Delay Format (SDF) timing annotation.
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