Motorola MC9S12GC-Family
Manuals and User Guides for Motorola MC9S12GC-Family. We found 2 manuals for free downloads: Reference manual, User Guide
Motorola MC9S12C-Family User guide
Brand: Motorola Size: 2 MB Pages: 136
Languages: English
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Freescale Semiconductor MC9S12C Family Reference Manual
Brand: Motorola Size: 4 MB Pages: 691
Languages: English
Table of contents
- 5 Port Integration Module (PIM9C32)
- 41 Module Mapping Control (MMCV4)
- 61 Multiplexed External Bus Interface (MEBIV3)
- 89 Interrupt (INTV1)
- 97 Background Debug Module (BDMV4)
- 123 Debug Module (DBGV1)
- 155 Analog-to-Digital Converter (ATD10B8C)
- 183 Clocks and Reset Generator (CRGV4)
- 219 Scalable Controller Area Network (S12MSCANV2)
- 275 Oscillator (OSCV2)
- 279 Pulse-Width Modulator (PWM8B6CV1)
- 315 Serial Communications Interface (S12SCIV2)
- 345 Serial Peripheral Interface (SPIV3)
- 367 Timer Module (TIM16B8CV1)
- 395 Dual Output Voltage Regulator (VREG3V3V2)
- 403 16 Kbyte Flash Module (S12FTS16KV1)
- 435 32 Kbyte Flash Module (S12FTS32KV1)
- 469 64 Kbyte Flash Module (S12FTS64KV4)
- 507 96 Kbyte Flash Module (S12FTS96KV1)
- 545 128 Kbyte Flash Module (S12FTS128K1V1)
- 579 Appendix A Electrical Characteristics
- 611 Appendix B Emulation Information
- 613 Appendix C Package Information
- 617 Appendix D Derivative Differences
- 17 Introduction
- 17 Features
- 19 Modes of Operation
- 20 Block Diagram
- 21 Memory Map and Registers
- 21 Device Memory Map
- 27 Detailed Register Map
- 44 Part ID Assignments
- 45 Signal Description
- 45 Device Pinouts
- 48 Signal Properties Summary
- 49 Pin Initialization for 48- and 52-Pin LQFP Bond Out Versions
- 50 Detailed Signal Descriptions
- 55 Power Supply Pins
- 57 System Clock Description
- 57 Modes of Operation
- 57 Chip Configuration Summary
- 58 Security
- 59 Low-Power Modes
- 60 Resets and Interrupts
- 60 Vectors
- 62 Resets
- 62 Device Specific Information and Module Dependencies
- 62 PPAGE
- 63 BDM Alternate Clock
- 63 Extended Address Range Emulation Implications
- 64 VREGEN
- 64 Clock Reset Generator And VREG Interface
- 64 Analog-to-Digital Converter
- 64 MODRR Register Port T And Port P Mapping
- 64 Port AD Dependency On PIM And ATD Registers
- 65 Recommended Printed Circuit Board Layout
- 73 Introduction
- 73 Features
- 74 Block Diagram
- 76 Signal Description
- 77 Memory Map and Registers
- 77 Module Memory Map
- 80 Register Descriptions
- 104 Functional Description
- 104 Registers
- 105 Port Descriptions
- 107 Port A, B, E and BKGD Pin
- 107 External Pin Descriptions
- 107 Low Power Options
- 107 Initialization Information
- 107 Reset Initialization
- 108 Interrupts
- 108 Interrupt Sources
- 108 Recovery from STOP
- 108 Application Information
- 109 Introduction
- 110 Features
- 110 Modes of Operation
- 110 External Signal Description
- 110 Memory Map and Register Definition
- 110 Module Memory Map
- 112 Register Descriptions
- 122 Functional Description
- 122 Bus Control
- 122 Address Decoding
- 124 Memory Expansion
- 129 Introduction
- 129 Features
- 131 Modes of Operation
- 131 External Signal Description
- 133 Memory Map and Register Definition
- 134 Module Memory Map
- 134 Register Descriptions
- 150 Functional Description
- 150 Detecting Access Type from External Signals
- 151 Stretched Bus Cycles
- 151 Modes of Operation
- 156 Internal Visibility
- 156 Low-Power Options
- 157 Introduction
- 158 Features
- 158 Modes of Operation
- 159 External Signal Description
- 159 Memory Map and Register Definition
- 159 Module Memory Map
- 159 Register Descriptions
- 161 Functional Description
- 162 Low-Power Modes
- 162 Resets
- 162 Interrupts
- 162 Interrupt Registers
- 162 Highest Priority I-Bit Maskable Interrupt
- 163 Interrupt Priority Decoder
- 163 Exception Priority
- 165 Introduction
- 165 Features
- 166 Modes of Operation
- 167 External Signal Description
- 167 BKGD — Background Interface Pin
- 167 TAGHI — High Byte Instruction Tagging Pin
- 167 TAGLO — Low Byte Instruction Tagging Pin
- 168 Memory Map and Register Definition
- 168 Module Memory Map
- 169 Register Descriptions
- 174 Functional Description
- 174 Security
- 174 Enabling and Activating BDM
- 175 BDM Hardware Commands
- 176 Standard BDM Firmware Commands
- 177 BDM Command Structure
- 179 BDM Serial Interface
- 182 Serial Interface Hardware Handshake Protocol
- 184 Hardware Handshake Abort Procedure
- 187 SYNC — Request Timed Reference Pulse
- 187 6.4.10 Instruction Tracing
- 188 6.4.11 Instruction Tagging
- 188 6.4.12 Serial Communication Time-Out
- 189 6.4.13 Operation in Wait Mode
- 189 6.4.14 Operation in Stop Mode
- 191 Introduction
- 191 Features
- 193 Modes of Operation
- 193 Block Diagram
- 195 External Signal Description
- 196 Memory Map and Register Definition
- 196 Module Memory Map
- 196 Register Descriptions
- 212 Functional Description
- 212 DBG Operating in BKP Mode
- 214 DBG Operating in DBG Mode
- 221 Breakpoints
- 222 Resets
- 222 Interrupts
- 223 Introduction
- 223 Features
- 223 Modes of Operation
- 224 Block Diagram
- 225 Signal Description
- 225 AN7 / ETRIG / PAD
- 225 AN6 / PAD
- 225 AN5 / PAD
- 225 AN4 / PAD
- 225 AN3 / PAD
- 225 AN2 / PAD
- 225 AN1 / PAD
- 225 AN0 / PAD
- 226 Memory Map and Registers
- 226 Module Memory Map
- 230 Register Descriptions
- 245 Functional Description
- 245 Analog Sub-block
- 246 Digital Sub-block
- 247 Initialization/Application Information
- 247 Setting up and starting an A/D conversion
- 248 Aborting an A/D conversion
- 248 Resets
- 249 Interrupts
- 251 Introduction
- 251 Features
- 252 Modes of Operation
- 252 Block Diagram
- 253 External Signal Description
- 253 — PLL Operating Voltage, PLL Ground
- 253 XFC — PLL Loop Filter Pin
- 254 RESET — Reset Pin
- 254 Memory Map and Register Definition
- 254 Module Memory Map
- 255 Register Descriptions
- 266 Functional Description
- 266 Phase Locked Loop (PLL)
- 269 System Clocks Generator
- 270 Clock Monitor (CM)
- 270 Clock Quality Checker
- 272 Computer Operating Properly Watchdog (COP)
- 272 Real-Time Interrupt (RTI)
- 273 Modes of Operation
- 274 Low-Power Operation in Run Mode
- 274 Low-Power Operation in Wait Mode
- 278 9.4.10 Low-Power Operation in Stop Mode
- 282 Resets
- 284 Clock Monitor Reset
- 284 Computer Operating Properly Watchdog (COP) Reset
- 285 Power-On Reset, Low Voltage Reset
- 286 Interrupts
- 286 Real-Time Interrupt
- 286 PLL Lock Interrupt
- 286 Self-Clock Mode Interrupt
- 287 10.1 Introduction
- 287 10.1.1 Glossary
- 288 10.1.2 Block Diagram
- 288 10.1.3 Features
- 289 10.1.4 Modes of Operation
- 289 10.2 External Signal Description
- 289 10.2.1 RXCAN — CAN Receiver Input Pin
- 289 10.2.2 TXCAN — CAN Transmitter Output Pin
- 289 10.2.3 CAN System
- 290 10.3 Memory Map and Register Definition
- 290 10.3.1 Module Memory Map
- 292 10.3.2 Register Descriptions
- 314 10.3.3 Programmer’s Model of Message Storage
- 323 10.4 Functional Description
- 323 10.4.1 General
- 324 10.4.2 Message Storage
- 327 10.4.3 Identifier Acceptance Filter
- 333 10.4.4 Modes of Operation
- 334 10.4.5 Low-Power Options
- 339 10.4.6 Reset Initialization
- 339 10.4.7 Interrupts
- 341 10.5 Initialization/Application Information
- 341 10.5.1 MSCAN initialization
- 343 11.1 Introduction
- 343 11.1.1 Features
- 343 11.1.2 Modes of Operation
- 344 11.2 External Signal Description
- 344 — PLL Operating Voltage, PLL Ground
- 344 11.2.2 EXTAL and XTAL — Clock/Crystal Source Pins
- 345 11.2.3 XCLKS — Colpitts/Pierce Oscillator Selection Signal
- 346 11.3 Memory Map and Register Definition
- 346 11.4 Functional Description
- 346 11.4.1 Amplitude Limitation Control (ALC)
- 346 11.4.2 Clock Monitor (CM)
- 346 11.5 Interrupts
- 347 12.1 Introduction
- 347 12.1.1 Features
- 347 12.1.2 Modes of Operation
- 348 12.1.3 Block Diagram
- 348 12.2 External Signal Description
- 348 12.2.1 PWM5 — Pulse Width Modulator Channel 5 Pin
- 348 12.2.2 PWM4 — Pulse Width Modulator Channel 4 Pin
- 348 12.2.3 PWM3 — Pulse Width Modulator Channel 3 Pin
- 349 12.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin
- 349 12.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin
- 349 12.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin
- 349 12.3 Memory Map and Register Definition
- 349 12.3.1 Module Memory Map
- 351 12.3.2 Register Descriptions
- 371 12.4 Functional Description
- 371 12.4.1 PWM Clock Select
- 374 12.4.2 PWM Channel Timers
- 381 12.5 Resets
- 381 12.6 Interrupts
- 383 13.1 Introduction
- 383 13.1.1 Glossary
- 383 13.1.2 Features
- 384 13.1.3 Modes of Operation
- 385 13.1.4 Block Diagram
- 385 13.2 External Signal Description
- 385 13.2.1 TXD-SCI Transmit Pin
- 385 13.2.2 RXD-SCI Receive Pin
- 386 13.3 Memory Map and Registers
- 386 13.3.1 Module Memory Map
- 386 13.3.2 Register Descriptions
- 394 13.4 Functional Description
- 395 13.4.1 Data Format
- 396 13.4.2 Baud Rate Generation
- 397 13.4.3 Transmitter
- 400 13.4.4 Receiver
- 409 13.4.5 Single-Wire Operation
- 409 13.4.6 Loop Operation
- 409 13.5 Initialization Information
- 409 13.5.1 Reset Initialization
- 410 13.5.2 Interrupt Operation
- 411 13.5.3 Recovery from Wait Mode
- 413 14.1 Introduction
- 413 14.1.1 Features
- 413 14.1.2 Modes of Operation
- 414 14.1.3 Block Diagram
- 414 14.2 External Signal Description
- 414 14.2.1 MOSI — Master Out/Slave In Pin
- 415 14.2.2 MISO — Master In/Slave Out Pin
- 415 14.2.3 SS — Slave Select Pin
- 415 14.2.4 SCK — Serial Clock Pin
- 415 14.3 Memory Map and Register Definition
- 415 14.3.1 Module Memory Map
- 416 14.3.2 Register Descriptions
- 423 14.4 Functional Description
- 424 14.4.1 Master Mode
- 425 14.4.2 Slave Mode
- 426 14.4.3 Transmission Formats
- 429 14.4.4 SPI Baud Rate Generation
- 430 14.4.5 Special Features
- 431 14.4.6 Error Conditions
- 432 14.4.7 Operation in Run Mode
- 432 14.4.8 Operation in Wait Mode
- 432 14.4.9 Operation in Stop Mode
- 433 14.5 Reset
- 433 14.6 Interrupts
- 433 14.6.1 MODF
- 433 14.6.2 SPIF
- 433 14.6.3 SPTEF
- 435 15.1 Introduction
- 435 15.1.1 Features
- 436 15.1.2 Modes of Operation
- 436 15.1.3 Block Diagrams
- 438 15.2 External Signal Description
- 438 15.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin
- 438 15.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin
- 438 15.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin
- 438 15.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin
- 438 15.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin
- 439 15.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin
- 439 15.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin
- 439 15.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin
- 439 15.3 Memory Map and Register Definition
- 439 15.3.1 Module Memory Map
- 441 15.3.2 Register Descriptions
- 457 15.4 Functional Description
- 458 15.4.1 Prescaler
- 459 15.4.2 Input Capture
- 459 15.4.3 Output Compare
- 460 15.4.4 Pulse Accumulator
- 460 15.4.5 Event Counter Mode
- 461 15.4.6 Gated Time Accumulation Mode
- 461 15.5 Resets
- 461 15.6 Interrupts
- 461 15.6.1 Channel [7:0] Interrupt (C[7:0]F)
- 462 15.6.2 Pulse Accumulator Input Interrupt (PAOVI)
- 462 15.6.3 Pulse Accumulator Overflow Interrupt (PAOVF)
- 462 15.6.4 Timer Overflow Interrupt (TOF)
- 463 16.1 Introduction
- 463 16.1.1 Features
- 463 16.1.2 Modes of Operation
- 464 16.1.3 Block Diagram
- 465 16.2 External Signal Description
- 465 — Regulator Power Input
- 465 — Regulator Reference Supply
- 466 — Regulator Output1 (Core Logic)
- 466 — Regulator Output2 (PLL)
- 466 — Optional Regulator Enable
- 466 16.3 Memory Map and Register Definition
- 466 16.3.1 Module Memory Map
- 467 16.3.2 Register Descriptions
- 467 16.4 Functional Description
- 468 16.4.1 REG — Regulator Core
- 468 16.4.2 Full-Performance Mode
- 468 16.4.3 Reduced-Power Mode
- 468 16.4.4 LVD — Low-Voltage Detect
- 468 16.4.5 POR — Power-On Reset
- 468 16.4.6 LVR — Low-Voltage Reset
- 468 16.4.7 CTRL — Regulator Control
- 469 16.5 Resets
- 469 16.5.1 Power-On Reset
- 469 16.5.2 Low-Voltage Reset
- 469 16.6 Interrupts
- 469 16.6.1 LVI — Low-Voltage Interrupt
- 471 17.1 Introduction
- 471 17.1.1 Glossary
- 471 17.1.2 Features
- 472 17.1.3 Modes of Operation
- 472 17.1.4 Block Diagram
- 472 17.2 External Signal Description
- 473 17.3 Memory Map and Registers
- 473 17.3.1 Module Memory Map
- 475 17.3.2 Register Descriptions
- 486 17.4 Functional Description
- 486 17.4.1 Flash Command Operations
- 500 17.4.2 Operating Modes
- 500 17.4.3 Flash Module Security
- 502 17.4.4 Flash Reset Sequence
- 502 17.4.5 Interrupts
- 503 18.1 Introduction
- 503 18.1.1 Glossary
- 503 18.1.2 Features
- 504 18.1.3 Modes of Operation
- 504 18.1.4 Block Diagram
- 504 18.2 External Signal Description
- 505 18.3 Memory Map and Registers
- 505 18.3.1 Module Memory Map
- 508 18.3.2 Register Descriptions
- 520 18.4 Functional Description
- 520 18.4.1 Flash Command Operations
- 534 18.4.2 Operating Modes
- 534 18.4.3 Flash Module Security
- 536 18.4.4 Flash Reset Sequence
- 536 18.4.5 Interrupts
- 537 19.1 Introduction
- 537 19.1.1 Glossary
- 537 19.1.2 Features
- 538 19.1.3 Modes of Operation
- 538 19.1.4 Block Diagram
- 539 19.2 External Signal Description
- 539 19.3 Memory Map and Registers
- 539 19.3.1 Module Memory Map
- 545 19.3.2 Register Descriptions
- 557 19.4 Functional Description
- 557 19.4.1 Flash Command Operations
- 571 19.4.2 Operating Modes
- 571 19.4.3 Flash Module Security
- 573 19.4.4 Flash Reset Sequence
- 573 19.4.5 Interrupts
- 575 20.1 Introduction
- 575 20.1.1 Glossary
- 575 20.1.2 Features
- 576 20.1.3 Modes of Operation
- 576 20.1.4 Block Diagram
- 577 20.2 External Signal Description
- 577 20.3 Memory Map and Registers
- 577 20.3.1 Module Memory Map
- 583 20.3.2 Register Descriptions
- 595 20.4 Functional Description
- 595 20.4.1 Flash Command Operations
- 609 20.4.2 Operating Modes
- 609 20.4.3 Flash Module Security
- 611 20.4.4 Flash Reset Sequence
- 611 20.4.5 Interrupts
- 613 21.1 Introduction
- 613 21.1.1 Glossary
- 613 21.1.2 Features
- 614 21.1.3 Modes of Operation
- 614 21.1.4 Block Diagram
- 614 21.2 External Signal Description
- 615 21.3 Memory Map and Registers
- 615 21.3.1 Module Memory Map
- 618 21.3.2 Register Descriptions
- 630 21.4 Functional Description
- 630 21.4.1 Flash Command Operations
- 644 21.4.2 Operating Modes
- 644 21.4.3 Flash Module Security
- 646 21.4.4 Flash Reset Sequence
- 646 21.4.5 Interrupts
- 647 General
- 658 ATD Characteristics
- 663 MSCAN
- 663 Reset, Oscillator and PLL
- 669 NVM, Flash, and EEPROM
- 677 Voltage Regulator
- 679 General