ST STM32L552ME
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ST STM32L552xx and STM32L562xx advanced Arm®-based 32-bit MCUs are designed to provide excellent performance and flexibility for embedded applications requiring high speed, low power consumption, and advanced security features. These MCUs are ideal for a wide range of applications, including industrial automation, healthcare, consumer electronics, and IoT devices. The STM32L552xx and STM32L562xx MCUs are based on the Arm® Cortex®-M33 core, which offers high performance and energy efficiency. These MCUs also feature a rich set of peripherals, including high-speed interfaces, timers, and analog peripherals. Additionally, these MCUs feature advanced security features, such as TrustZone® technology, to protect sensitive data and applications from unauthorized access.
Key Features
Based on the Arm® Cortex®-M33 core for high performance and energy efficiency
Feature a rich set of peripherals, including high-speed interfaces, timers, and analog peripherals
Advanced security features, such as TrustZone® technology, to protect sensitive data and applications from unauthorized access
Suitable for a wide range of applications, including industrial automation, healthcare, consumer electronics, and IoT devices
Pages: 2194 ST STM32L552ME Reference manual
Brand: ST Category: Development boards Size: 42 MB
Languages: English
Table of contents
- 76 Documentation conventions
- 76 General information
- 76 List of abbreviations for registers
- 77 Glossary
- 77 Availability of peripherals
- 78 Memory and bus architecture
- 78 System architecture
- 79 Fast C-bus
- 79 Slow C-bus
- 79 S-bus
- 80 DMA-bus
- 80 SDMMC controller DMA bus
- 80 BusMatrix
- 80 security architecture
- 83 Default TrustZone security state
- 83 TrustZone peripheral classification
- 87 Memory organization
- 87 Introduction
- 88 Memory map and register boundary addresses
- 94 Embedded SRAM
- 94 SRAM2 parity check
- 95 SRAM2 Write protection
- 97 SRAM2 Read protection
- 97 SRAM2 Erase
- 97 Flash memory overview
- 98 Boot configuration
- 101 System security
- 101 Introduction
- 102 Key security features
- 102 Secure install
- 103 Secure boot
- 103 Introduction
- 103 Unique boot entry and BOOT_LOCK
- 104 Immutable root of trust in system Flash memory
- 104 Secure update
- 104 Introduction
- 105 security architecture
- 106 Memory and peripheral allocation using IDAU/SAU
- 108 Memory and peripheral allocation using GTZC
- 111 -aware peripherals
- 118 security
- 119 Other resource isolations
- 119 Temporal isolation using secure hide protection (HDP)
- 120 Secure execution
- 120 Introduction
- 120 Memory protection unit (MPU)
- 121 Embedded Flash memory write protection
- 121 Tamper detection and response
- 123 Secure storage
- 123 Introduction
- 123 Unique ID
- 123 Crypto engines
- 123 Introduction
- 124 Crypto engines features
- 125 On-the-fly decryption engine (OTFDEC)
- 125 Product Lifecycle
- 125 Introduction
- 127 Lifecycle management with readout protection (RDP)
- 128 Recommended option byte settings
- 128 Access controlled debug
- 128 Introduction
- 128 Debug protection with readout protection (RDP)
- 129 Introduction
- 129 readout protection (RDP)
- 130 Software intellectual property protection with OTFDEC
- 132 Other software intellectual property protections
- 133 controller (GTZC)
- 133 GTZC introduction
- 133 GTZC main features
- 133 GTZC TrustZone system architecture
- 135 GTZC functional description
- 135 GTZC block diagram
- 136 Illegal access definition
- 137 TrustZone security controller (TZSC)
- 137 Memory protection controller - block based (MPCBB)
- 138 TrustZone illegal access controller (TZIC)
- 138 Power-on/reset state
- 138 DMA requests
- 138 GTZC events
- 139 GTZC_TZSC registers
- 139 GTZC_TZSC control register (GTZC_TZSC_CR)
- 140 (GTZC_TZSC_SECCFGR1)
- 143 (GTZC_TZSC_SECCFGR2)
- 145 (GTZC_TZSC_PRIVCFGR1)
- 148 (GTZC_TZSC_PRIVCFGR2)
- 150 (GTZC_TZSC_MPCWMxANSR)
- 150 (GTZC_TZSC_MPCWMxBNSR)
- 151 GTZC_TZSC register map and reset values
- 153 GTZC_MPCBB registers
- 153 GTZC_MPCBBx control register (GTZC_MPCBBx_CR) (x = 1 to 2)
- 154 GTZC_MPCBB1 lock register 1(GTZC_MPCBB1_LCKVTR1)
- 154 (GTZC_MPCBB2_LCKVTR1)
- 155 (GTZC_MPCBBx_VCTRy) (x = 1 to 2)
- 156 GTZC_MPCBB1 register map and reset values
- 156 GTZC_MPCBB2 register map and reset values
- 157 GTZC_TZIC registers
- 157 GTZC_TZIC interrupt enable register 1 (GTZC_TZIC_IER1)
- 160 GTZC_TZIC interrupt enable register 2 (GTZC_TZIC_IER2)
- 162 GTZC_TZIC interrupt enable register 3 (GTZC_TZIC_IER3)
- 163 GTZC_TZIC status register 1 (GTZC_TZIC_SR1)
- 166 GTZC_TZIC status register 2 (GTZC_TZIC_SR2)
- 168 GTZC_TZIC status register 3 (GTZC_TZIC_SR3)
- 169 GTZC_TZIC flag clear register 1 (GTZC_TZIC_FCR1)
- 172 GTZC_TZIC flag clear register 2 (GTZC_TZIC_FCR2)
- 174 GTZC_TZIC flag clear register 3 (GTZC_TZIC_FCR3)
- 175 GTZC_TZIC register map and reset values
- 177 Embedded Flash memory (FLASH)
- 177 Introduction
- 177 FLASH main features
- 178 Flash memory functional description
- 178 Flash memory organization
- 180 Error code correction (ECC)
- 181 Read access latency
- 182 Low-voltage read
- 182 Flash program and erase operations
- 187 Flash main memory programming sequences
- 188 Flash errors flags
- 190 (DBANK = 1)
- 192 Flash memory option bytes
- 192 Option bytes description
- 193 Option bytes programming
- 195 Flash TrustZone security and privilege protections
- 195 TrustZone security protection
- 197 Secure watermark-based area protection
- 197 Secure hide protection (HDP)
- 198 Secure block-based area (SECBB) protection
- 199 Forcing boot from a secure memory address
- 199 Flash security attribute state
- 200 Flash registers privileged and unprivileged modes
- 200 Secure system memory
- 200 Introduction
- 200 RSS allocates resource to bootloader
- 202 RSSLIB functions
- 204 FLASH memory protection
- 204 Write protection (WRP)
- 206 Readout protection (RDP)
- 214 FLASH interrupts
- 215 FLASH registers
- 215 Flash access control register (FLASH_ACR)
- 216 Flash power-down key register (FLASH_PDKEYR)
- 217 Flash non-secure key register (FLASH_NSKEYR)
- 217 Flash secure key register (FLASH_SECKEYR)
- 218 Flash option key register (FLASH_OPTKEYR)
- 218 Flash low voltage key register (FLASH_LVEKEYR)
- 219 Flash status register (FLASH_NSSR)
- 220 Flash status register (FLASH_SECSR)
- 222 Flash non-secure control register (FLASH_NSCR)
- 224 Flash secure control register (FLASH_SECCR)
- 225 Flash ECC register (FLASH_ECCR)
- 227 Flash option register (FLASH_OPTR)
- 230 Flash secure boot address 0 register (FLASH_SECBOOTADD0R)
- 231 Flash bank 1 secure watermak1 register (FLASH_SECWM1R1)
- 232 Flash secure watermak1 register 2 (FLASH_SECWM1R2)
- 233 Flash WPR1 area A address register (FLASH_WRP1AR)
- 234 Flash WPR1 area B address register (FLASH_WRP1BR)
- 235 Flash secure watermak2 register (FLASH_SECWM2R1)
- 236 Flash secure watermak2 register 2 (FLASH_SECWM2R2)
- 237 Flash WPR2 area A address register (FLASH_WRP2AR)
- 238 Flash WPR2 area B address register (FLASH_WRP2BR)
- 239 (where x=1..4)
- 240 FLASH secure HDP control register (FLASH_SECHDPCR)
- 240 FLASH privilege configuration register (FLASH_PRIVCFGR)
- 241 FLASH register map and reset values
- 244 Instruction cache (ICACHE)
- 244 Introduction
- 244 ICACHE main features
- 245 ICACHE implementation
- 245 ICACHE functional description
- 246 ICACHE block diagram
- 246 ICACHE reset and clocks
- 247 ICACHE TAG memory
- 248 Direct mapped ICACHE (1-way cache)
- 249 ICACHE enable
- 249 Cacheable and non-cacheable traffic
- 250 Address remapping
- 252 Cacheable accesses
- 253 Dual master cache
- 254 ICACHE security
- 254 ICACHE maintenance
- 254 ICACHE performance monitoring
- 254 ICACHE Boot
- 255 ICACHE low-power modes
- 255 ICACHE error management and interrupts
- 256 ICACHE registers
- 256 ICACHE control register (ICACHE_CR)
- 257 ICACHE status register (ICACHE_SR)
- 257 ICACHE interrupt enable register (ICACHE_IER)
- 258 ICACHE flag clear register (ICACHE_FCR)
- 259 ICACHE hit monitor register (ICACHE_HMONR)
- 259 ICACHE miss monitor register (ICACHE_MMONR)
- 259 ICACHE region x configuration register (ICACHE_CRRx)
- 260 ICACHE register map
- 262 Power control (PWR)
- 262 Power supplies and supply domains
- 267 Independent analog peripherals supply
- 267 Independent I/O supply rail
- 267 Independent USB transceivers supply
- 268 Battery backup domain
- 269 System supply voltage regulation
- 269 Voltage regulator
- 270 Embedded SMPS step down converter
- 271 SMPS step down converter power supply scheme
- 272 SMPS step down converter versus low-power mode
- 273 Dynamic voltage scaling management
- 274 VDD12 domain and external SMPS
- 276 Power supply supervision
- 276 brown-out reset (BOR)
- 277 Programmable voltage detector (PVD)
- 278 Peripheral voltage monitoring (PVM)
- 279 Upper voltage threshold monitoring
- 280 Temperature threshold monitoring
- 280 Power management
- 280 Power modes
- 287 Run mode
- 287 Low-power run mode (LP run)
- 288 Low-power modes
- 289 Sleep mode
- 290 Low-power sleep mode (LP sleep)
- 291 Stop 0 mode
- 293 Stop 1 mode
- 294 Stop 2 mode
- 296 Standby mode
- 299 Shutdown mode
- 300 Auto-wakeup from a low-power mode
- 300 PWR TrustZone security
- 302 PWR Privileged and Unprivileged modes
- 302 PWR registers
- 303 Power control register 1 (PWR_CR1)
- 304 Power control register 2 (PWR_CR2)
- 305 Power control register 3 (PWR_CR3)
- 307 Power control register 4 (PWR_CR4)
- 308 Power status register 1 (PWR_SR1)
- 310 Power status register 2 (PWR_SR2)
- 311 Power status clear register (PWR_SCR)
- 312 Power Port A pull-up control register (PWR_PUCRA)
- 312 Power Port A pull-down control register (PWR_PDCRA)
- 313 Power Port B pull-up control register (PWR_PUCRB)
- 314 Power Port B pull-down control register (PWR_PDCRB)
- 314 Power Port C pull-up control register (PWR_PUCRC)
- 315 Power Port C pull-down control register (PWR_PDCRC)
- 315 Power Port D pull-up control register (PWR_PUCRD)
- 316 Power Port D pull-down control register (PWR_PDCRD)
- 317 Power Port E pull-up control register (PWR_PUCRE)
- 317 Power Port E pull-down control register (PWR_PDCRE)
- 318 Power Port F pull-up control register (PWR_PUCRF)
- 318 Power Port F pull-down control register (PWR_PDCRF)
- 319 Power Port G pull-up control register (PWR_PUCRG)
- 320 Power Port G pull-down control register (PWR_PDCRG)
- 320 Power Port H pull-up control register (PWR_PUCRH)
- 321 Power Port H pull-down control register (PWR_PDCRH)
- 321 Power secure configuration register (PWR_SECCFGR)
- 323 Power privilege configuration register (PWR_PRIVCFGR)
- 324 PWR register map and reset values
- 327 Reset and clock control (RCC)
- 327 Reset
- 327 Power reset
- 327 System reset
- 329 Backup domain reset
- 329 RCC pins and internal signals
- 329 Clocks
- 333 HSE clock
- 334 HSI16 clock
- 335 MSI clock
- 336 HSI48 clock
- 337 LSE clock
- 337 LSE system clock
- 338 LSI clock
- 338 System clock (SYSCLK) selection
- 339 Clock source frequency versus voltage scaling
- 339 Clock security system (CSS)
- 339 Clock security system on LSE
- 340 ADC clock
- 340 RTC clock
- 340 Timer clock
- 341 Watchdog clock
- 341 Clock-out capability
- 341 Internal/external clock measurement with TIM15/TIM16/TIM
- 344 (RCC_AHBxENR, RCC_APBxENRy)
- 344 Low-power modes
- 345 security
- 347 RCC Privileged and Unprivileged mode
- 347 RCC interrupts
- 349 RCC registers
- 349 RCC clock control register (RCC_CR)
- 352 RCC internal clock sources calibration register (RCC_ICSCR)
- 353 RCC clock configuration register (RCC_CFGR)
- 356 RCC PLL configuration register (RCC_PLLCFGR)
- 359 RCC PLLSAI1 configuration register (RCC_PLLSAI1CFGR)
- 362 RCC PLLSAI2 configuration register (RCC_PLLSAI2CFGR)
- 364 RCC clock interrupt enable register (RCC_CIER)
- 365 RCC clock interrupt flag register (RCC_CIFR)
- 367 RCC clock interrupt clear register (RCC_CICR)
- 368 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 369 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 371 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
- 372 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)
- 374 RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)
- 375 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 377 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 378 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 380 RCC AHB3 peripheral clock enable register(RCC_AHB3ENR)
- 381 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
- 383 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
- 385 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 386 (RCC_AHB1SMENR)
- 388 (RCC_AHB2SMENR)
- 390 (RCC_AHB3SMENR)
- 391 register 1 (RCC_APB1SMENR1)
- 394 register 2 (RCC_APB1SMENR2)
- 395 (RCC_APB2SMENR)
- 397 (RCC_CCIPR1)
- 399 RCC Backup domain control register (RCC_BDCR)
- 402 RCC control/status register (RCC_CSR)
- 404 RCC clock recovery RC register (RCC_CRRCR)
- 405 (RCC_CCIPR2)
- 406 OCTOSPI delay configuration register (RCC_DLYCFGR)
- 407 RCC secure configuration register (RCC_SECCFGR)
- 409 RCC secure status register (RCC_SECSR)
- 411 RCC AHB1 security status register (RCC_AHB1SECSR)
- 412 RCC AHB2 security status register (RCC_AHB2SECSR)
- 414 RCC AHB3 security status register (RCC_AHB3SECSR)
- 415 RCC APB1 security status register 1 (RCC_APB1SECSR1)
- 418 RCC APB1 security status register 2 (RCC_APB1SECSR2)
- 419 RCC APB2 security status register (RCC_APB2SECSR)
- 421 RCC register map
- 428 Clock recovery system (CRS)
- 428 Introduction
- 428 CRS main features
- 428 CRS implementation
- 429 CRS functional description
- 429 CRS block diagram
- 429 Synchronization input
- 430 Frequency error measurement
- 431 Frequency error evaluation and automatic trimming
- 431 CRS initialization and configuration
- 432 CRS low-power modes
- 432 CRS interrupts
- 433 CRS registers
- 433 CRS control register (CRS_CR)
- 434 CRS configuration register (CRS_CFGR)
- 435 CRS interrupt and status register (CRS_ISR)
- 437 CRS interrupt flag clear register (CRS_ICR)
- 438 CRS register map
- 439 General-purpose I/Os (GPIO)
- 439 Introduction
- 439 GPIO main features
- 439 GPIO functional description
- 442 General-purpose I/O (GPIO)
- 442 I/O pin alternate function multiplexer and mapping
- 443 I/O port control registers
- 443 I/O port data registers
- 443 I/O data bitwise handling
- 444 GPIO locking mechanism
- 444 I/O alternate function input/output
- 444 External interrupt/wakeup lines
- 445 Input configuration
- 445 11.3.10 Output configuration
- 446 11.3.11 Alternate function configuration
- 447 11.3.12 Analog configuration
- 447 11.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 447 11.3.14 Using the GPIO pins in the RTC supply domain
- 448 11.3.15 Using PH3 as GPIO
- 448 TrustZone security
- 449 Privileged and Unprivileged modes
- 450 GPIO registers
- 450 (x =A to H)
- 450 (x = A to H)
- 456 11.6.11 GPIO port bit reset register (GPIOx_BRR) (x = A to H)
- 458 11.6.13 GPIO register map
- 459 System configuration controller (SYSCFG)
- 459 SYSCFG main features
- 459 SYSCFG TrustZone security and privilege
- 461 SYSCFG registers
- 461 SYSCFG secure configuration register (SYSCFG_SECCFGR)
- 461 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 463 FPU interrupt mask register (SYSCFG_FPUIMR)
- 464 SYSCFG CPU non-secure lock register (SYSCFG_ CNSLCKR)
- 464 SYSCFG CPU secure lock register (SYSCFG _CSLOCKR)
- 465 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 466 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)
- 467 SYSCFG SRAM2 key register (SYSCFG_SKR)
- 468 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
- 468 12.3.10 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)
- 469 12.3.11 SYSCFG RSS command register (SYSCFG_RSSCMDR)
- 470 12.3.12 SYSCFG register map
- 472 Peripherals interconnect matrix
- 472 Introduction
- 472 Connection summary
- 473 Interconnection details
- 473 timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15)
- 474 (ADC1/ADC2)
- 474 From ADC1/ADC2 to timer (TIM1/TIM8)
- 475 (DAC1/DAC2)
- 475 and EXTI to DFSDM
- 476 From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17)
- 476 (TIM2/TIM15/TIM16/TIM17)
- 477 (LPTIM1/LPTIM2/LPTIM3)
- 477 (COMP1/COMP2)
- 477 13.3.10 From ADC (ADC1) to ADC (ADC2)
- 478 13.3.11 From USB to timer (TIM2)
- 478 (OPAMP1/OPAM2)
- 478 (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17)
- 479 13.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17)
- 479 13.3.15 From timers (TIM16/TIM17) to IRTIM
- 480 13.3.16 From ADC (ADC1/ADC2) to DFSDM
- 481 Direct memory access controller (DMA)
- 481 Introduction
- 481 DMA main features
- 482 DMA implementation
- 482 DMA1 and DMA
- 482 DMA request mapping
- 483 DMA functional description
- 483 DMA block diagram
- 484 DMA pins and internal signals
- 484 DMA transfers
- 485 DMA arbitration
- 486 DMA channels
- 491 DMA data width, alignment and endianness
- 492 DMA error management
- 493 DMA interrupts
- 493 DMA registers
- 493 DMA interrupt status register (DMA_ISR)
- 497 DMA interrupt flag clear register (DMA_IFCR)
- 498 DMA channel x configuration register (DMA_CCRx)
- 504 DMA channel x peripheral address register (DMA_CPARx)
- 504 DMA channel x memory 0 address register (DMA_CM0ARx)
- 505 DMA channel x memory 1 address register (DMA_CM1ARx)
- 505 DMA register map
- 509 DMA request multiplexer (DMAMUX)
- 509 Introduction
- 510 DMAMUX main features
- 510 DMAMUX implementation
- 510 DMAMUX instantiation
- 511 DMAMUX mapping
- 514 DMAMUX functional description
- 514 DMAMUX block diagram
- 515 DMAMUX signals
- 515 DMAMUX channels
- 516 DMAMUX secure/non-secure channels
- 516 DMAMUX privileged / unprivileged channels
- 516 DMAMUX request line multiplexer
- 519 DMAMUX request generator
- 520 DMAMUX interrupts
- 522 DMAMUX registers
- 522 (DMAMUX_CxCR)
- 523 (DMAMUX_CSR)
- 523 (DMAMUX_CCFR)
- 524 (DMAMUX_RGxCR)
- 525 (DMAMUX_RGSR)
- 526 (DMAMUX_RGCFR)
- 527 DMAMUX register map
- 529 Nested vectored interrupt controller (NVIC)
- 529 NVIC main features
- 529 SysTick calibration value register
- 530 Interrupt and exception vectors
- 534 Extended interrupts and event controller (EXTI)
- 534 EXTI main features
- 535 EXTI block diagram
- 536 EXTI connections between peripherals and CPU
- 536 EXTI interrupt/event mapping
- 538 EXTI functional description
- 538 EXTI configurable event input wakeup
- 540 EXTI direct event input wakeup
- 540 EXTI mux selection
- 541 EXTI functional behavior
- 542 EXTI event protection
- 542 EXTI security protection
- 543 EXTI privilege protection
- 544 EXTI registers
- 544 EXTI rising trigger selection register (EXTI_RTSR1)
- 545 EXTI falling trigger selection register (EXTI_FTSR1)
- 546 EXTI software interrupt event register (EXTI_SWIER1)
- 547 EXTI rising edge pending register (EXTI_RPR1)
- 548 EXTI falling edge pending register (EXTI_FPR1)
- 549 EXTI security configuration register (EXTI_SECCFGR1)
- 550 EXTI privilege configuration register (EXTI_PRIVCFGR1)
- 550 EXTI rising trigger selection register (EXTI_RTSR2)
- 551 EXTI falling trigger selection register (EXTI_FTSR2)
- 552 17.6.10 EXTI software interrupt event register (EXTI_SWIER2)
- 552 17.6.11 EXTI rising edge pending register (EXTI_RPR2)
- 553 17.6.12 EXTI falling edge pending register (EXTI_FPR2)
- 554 17.6.13 EXTI security enable register (EXTI_SECCFGR2)
- 554 17.6.14 EXTI privilege enable register (EXTI_PRIVCFGR2)
- 555 17.6.15 EXTI external interrupt selection register (EXTI_EXTICRn)
- 558 17.6.16 EXTI lock register (EXTI_LOCKR)
- 558 17.6.17 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)
- 559 17.6.18 EXTI CPU wakeup with event mask register (EXTI_EMR1)
- 560 17.6.19 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2)
- 560 17.6.20 EXTI CPU wakeup with event mask register (EXTI_EMR2)
- 561 17.6.21 EXTI register map
- 564 Cyclic redundancy check calculation unit (CRC)
- 564 Introduction
- 564 CRC main features
- 565 CRC functional description
- 565 CRC block diagram
- 565 CRC internal signals
- 565 CRC operation
- 567 CRC registers
- 567 CRC data register (CRC_DR)
- 567 CRC independent data register (CRC_IDR)
- 568 CRC control register (CRC_CR)
- 569 CRC initial value (CRC_INIT)
- 569 CRC polynomial (CRC_POL)
- 570 CRC register map
- 571 Flexible static memory controller (FSMC)
- 571 Introduction
- 571 FMC main features
- 572 FMC block diagram
- 573 AHB interface
- 573 Supported memories and transactions
- 574 External device address mapping
- 575 NOR/PSRAM address mapping
- 576 NAND Flash memory address mapping
- 577 NOR Flash/PSRAM controller
- 578 External memory interface signals
- 580 Supported memories and transactions
- 581 General timing rules
- 582 NOR Flash/PSRAM controller asynchronous transactions
- 599 Synchronous transactions
- 606 NOR/PSRAM controller registers
- 614 NAND Flash controller
- 615 External memory interface signals
- 617 NAND Flash supported memories and transactions
- 617 Timing diagrams for NAND Flash memory
- 618 NAND Flash operations
- 619 NAND Flash prewait functionality
- 620 in NAND Flash memory
- 621 NAND Flash controller registers
- 627 FMC register map
- 629 Octo-SPI interface (OCTOSPI)
- 629 Introduction
- 629 OCTOSPI main features
- 630 OCTOSPI implementation
- 631 OCTOSPI functional description
- 631 OCTOSPI block diagram
- 632 OCTOSPI interface to memory modes
- 632 OCTOSPI Regular-command protocol
- 636 OCTOSPI Regular-command protocol signal interface
- 639 HyperBus protocol
- 643 Specific features
- 644 OCTOSPI operating modes introduction
- 644 OCTOSPI Indirect mode
- 646 OCTOSPI Automatic status-polling mode
- 647 20.4.10 OCTOSPI Memory-mapped mode
- 647 20.4.11 OCTOSPI configuration introduction
- 648 20.4.12 OCTOSPI system configuration
- 648 20.4.13 OCTOSPI device configuration
- 649 20.4.14 OCTOSPI Regular-command mode configuration
- 652 20.4.15 OCTOSPI HyperBus protocol configuration
- 653 20.4.16 OCTOSPI error management
- 653 20.4.17 OCTOSPI BUSY and ABORT
- 654 20.4.18 OCTOSPI reconfiguration or deactivation
- 654 20.4.19 NCS behavior
- 656 Address alignment and data number
- 657 OCTOSPI interrupts
- 657 OCTOSPI registers
- 657 OCTOSPI control register (OCTOSPI_CR)
- 660 OCTOSPI device configuration register 1 (OCTOSPI_DCR1)
- 661 OCTOSPI device configuration register 2 (OCTOSPI_DCR2)
- 662 OCTOSPI device configuration register 3 (OCTOSPI_DCR3)
- 663 OCTOSPI device configuration register 4 (OCTOSPI_DCR4)
- 663 OCTOSPI status register (OCTOSPI_SR)
- 664 OCTOSPI flag clear register (OCTOSPI_FCR)
- 665 OCTOSPI data length register (OCTOSPI_DLR)
- 666 OCTOSPI address register (OCTOSPI_AR)
- 666 20.7.10 OCTOSPI data register (OCTOSPI_DR)
- 667 20.7.11 OCTOSPI polling status mask register (OCTOSPI_PSMKR)
- 667 20.7.12 OCTOSPI polling status match register (OCTOSPI_PSMAR)
- 668 20.7.13 OCTOSPI polling interval register (OCTOSPI_PIR)
- 668 20.7.14 OCTOSPI communication configuration register (OCTOSPI_CCR)
- 670 20.7.15 OCTOSPI timing configuration register (OCTOSPI_TCR)
- 671 20.7.16 OCTOSPI instruction register (OCTOSPI_IR)
- 672 20.7.17 OCTOSPI alternate bytes register (OCTOSPI_ABR)
- 672 20.7.18 OCTOSPI low-power timeout register (OCTOSPI_LPTR)
- 673 (OCTOSPI_WPCCR)
- 675 20.7.20 OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR)
- 676 20.7.21 OCTOSPI wrap instruction register (OCTOSPI_WPIR)
- 676 20.7.22 OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR)
- 677 (OCTOSPI_WCCR)
- 679 20.7.24 OCTOSPI write timing configuration register (OCTOSPI_WTCR)
- 679 20.7.25 OCTOSPI write instruction register (OCTOSPI_WIR)
- 680 20.7.26 OCTOSPI write alternate bytes register (OCTOSPI_WABR)
- 680 (OCTOSPI_HLCR)
- 681 20.7.28 OCTOSPI register map
- 684 Analog-to-digital converters (ADC)
- 684 Introduction
- 685 ADC main features
- 686 ADC implementation
- 687 ADC functional description
- 687 ADC block diagram
- 688 ADC pins and internal signals
- 689 ADC clocks
- 691 ADC1/2 connectivity
- 693 Slave AHB interface
- 693 (ADVREGEN)
- 693 Single-ended and differential input channels
- 694 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)
- 697 ADC on-off control (ADEN, ADDIS, ADRDY)
- 698 21.4.10 Constraints when writing the ADC control bits
- 699 21.4.11 Channel selection (SQRx, JSQRx)
- 700 21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)
- 700 21.4.13 Single conversion mode (CONT=0)
- 701 21.4.14 Continuous conversion mode (CONT=1)
- 702 21.4.15 Starting conversions (ADSTART, JADSTART)
- 703 21.4.16 ADC timing
- 703 21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)
- 705 (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
- 707 21.4.19 Injected channel management
- 709 21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)
- 710 21.4.21 Queue of context for injected conversions
- 718 21.4.22 Programmable resolution (RES) - Fast conversion mode
- 719 21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
- 719 21.4.24 End of conversion sequence (EOS, JEOS)
- 720 hardware/software triggers)
- 722 21.4.26 Data management
- 727 21.4.27 Managing conversions using the DFSDM
- 728 21.4.28 Dynamic low-power features
- 733 AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
- 737 21.4.30 Oversampler
- 743 21.4.31 Dual ADC modes
- 756 21.4.32 Temperature sensor
- 758 21.4.33 VBAT supply monitoring
- 759 21.4.34 Monitoring the internal voltage reference
- 760 ADC interrupts
- 762 ADC registers (for each ADC)
- 762 ADC interrupt and status register (ADC_ISR)
- 764 ADC interrupt enable register (ADC_IER)
- 766 ADC control register (ADC_CR)
- 769 ADC configuration register (ADC_CFGR)
- 773 ADC configuration register 2 (ADC_CFGR2)
- 775 ADC sample time register 1 (ADC_SMPR1)
- 776 ADC sample time register 2 (ADC_SMPR2)
- 777 ADC watchdog threshold register 1 (ADC_TR1)
- 777 ADC watchdog threshold register 2 (ADC_TR2)
- 778 21.6.10 ADC watchdog threshold register 3 (ADC_TR3)
- 779 21.6.11 ADC regular sequence register 1 (ADC_SQR1)
- 780 21.6.12 ADC regular sequence register 2 (ADC_SQR2)
- 781 21.6.13 ADC regular sequence register 3 (ADC_SQR3)
- 782 21.6.14 ADC regular sequence register 4 (ADC_SQR4)
- 782 21.6.15 ADC regular data register (ADC_DR)
- 783 21.6.16 ADC injected sequence register (ADC_JSQR)
- 785 21.6.17 ADC offset y register (ADC_OFRy)
- 786 21.6.18 ADC injected channel y data register (ADC_JDRy)
- 786 21.6.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR)
- 787 21.6.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR)
- 787 21.6.21 ADC differential mode selection register (ADC_DIFSEL)
- 788 21.6.22 ADC calibration factors (ADC_CALFACT)
- 788 ADC common registers
- 788 ADC common status register (ADC_CSR)
- 790 ADC common control register (ADC_CCR)
- 793 ADC common regular data register for dual mode (ADC_CDR)
- 793 ADC register map
- 797 Digital-to-analog converter (DAC)
- 797 Introduction
- 797 DAC main features
- 798 DAC implementation
- 799 DAC functional description
- 799 DAC block diagram
- 800 DAC channel enable
- 800 DAC data format
- 802 DAC conversion
- 802 DAC output voltage
- 803 DAC trigger selection
- 804 DMA requests
- 804 Noise generation
- 806 Triangle-wave generation
- 807 22.4.10 DAC channel modes
- 810 22.4.11 DAC channel buffer calibration
- 811 available)
- 815 DAC low-power modes
- 816 DAC interrupts
- 817 DAC registers
- 817 DAC control register (DAC_CR)
- 820 DAC software trigger register (DAC_SWTRGR)
- 821 (DAC_DHR12R1)
- 821 (DAC_DHR12L1)
- 822 (DAC_DHR8R1)
- 822 (DAC_DHR12R2)
- 823 (DAC_DHR12L2)
- 823 (DAC_DHR8R2)
- 824 (DAC_DHR12RD)
- 824 (DAC_DHR12LD)
- 825 (DAC_DHR8RD)
- 825 22.7.12 DAC channel1 data output register (DAC_DOR1)
- 826 22.7.13 DAC channel2 data output register (DAC_DOR2)
- 826 22.7.14 DAC status register (DAC_SR)
- 828 22.7.15 DAC calibration control register (DAC_CCR)
- 828 22.7.16 DAC mode control register (DAC_MCR)
- 830 (DAC_SHSR1)
- 830 (DAC_SHSR2)
- 831 22.7.19 DAC sample and hold time register (DAC_SHHR)
- 831 22.7.20 DAC sample and hold refresh time register (DAC_SHRR)
- 833 22.7.21 DAC register map
- 835 Voltage reference buffer (VREFBUF)
- 835 Introduction
- 835 VREFBUF functional description
- 835 VREFBUF trimming
- 837 VREFBUF registers
- 837 VREFBUF control and status register (VREFBUF_CSR)
- 838 VREFBUF calibration control register (VREFBUF_CCR)
- 838 VREFBUF register map
- 839 Comparator (COMP)
- 839 Introduction
- 839 COMP main features
- 840 COMP functional description
- 840 COMP block diagram
- 840 COMP pins and internal signals
- 841 COMP reset and clocks
- 841 Comparator LOCK mechanism
- 842 Window comparator
- 842 Hysteresis
- 843 Comparator output blanking function
- 844 COMP power and speed modes
- 844 COMP low-power modes
- 844 COMP interrupts
- 845 COMP registers
- 845 Comparator 1 control and status register (COMP1_CSR)
- 847 Comparator 2 control and status register (COMP2_CSR)
- 850 COMP register map
- 851 Operational amplifiers (OPAMP)
- 851 Introduction
- 851 OPAMP main features
- 851 OPAMP functional description
- 851 OPAMP reset and clocks
- 852 Initial configuration
- 852 Signal routing
- 853 OPAMP modes
- 856 Calibration
- 858 OPAMP low-power modes
- 859 OPAMP registers
- 859 OPAMP1 control/status register (OPAMP1_CSR)
- 860 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR)
- 860 (OPAMP1_LPOTR)
- 861 OPAMP2 control/status register (OPAMP2_CRS)
- 862 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR)
- 862 (OPAMP2_LPOTR)
- 863 OPAMP register map
- 864 Digital filter for sigma delta modulators (DFSDM)
- 864 Introduction
- 865 DFSDM main features
- 866 DFSDM implementation
- 867 DFSDM functional description
- 867 DFSDM block diagram
- 868 DFSDM pins and internal signals
- 869 DFSDM reset and clocks
- 870 Serial channel transceivers
- 879 Configuring the input serial interface
- 879 Parallel data inputs
- 881 Channel selection
- 882 Digital filter configuration
- 883 Integrator unit
- 884 26.4.10 Analog watchdog
- 886 26.4.11 Short-circuit detector
- 887 26.4.12 Extreme detector
- 887 26.4.13 Data unit block
- 888 26.4.14 Signed data format
- 889 26.4.15 Launching conversions
- 889 26.4.16 Continuous and fast continuous modes
- 890 26.4.17 Request precedence
- 891 26.4.18 Power optimization in run mode
- 891 DFSDM interrupts
- 893 DFSDM DMA transfer
- 893 DFSDM channel y registers (y=0..3)
- 893 DFSDM channel y configuration register (DFSDM_CHyCFGR1)
- 895 DFSDM channel y configuration register (DFSDM_CHyCFGR2)
- 896 (DFSDM_CHyAWSCDR)
- 897 (DFSDM_CHyWDATR)
- 897 DFSDM channel y data input register (DFSDM_CHyDATINR)
- 898 DFSDM channel y delay register (DFSDM_CHyDLYR)
- 899 DFSDM filter x module registers (x=0..3)
- 899 DFSDM filter x control register 1 (DFSDM_FLTxCR1)
- 902 DFSDM filter x control register 2 (DFSDM_FLTxCR2)
- 903 DFSDM filter x interrupt and status register (DFSDM_FLTxISR)
- 905 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR)
- 906 (DFSDM_FLTxJCHGR)
- 906 DFSDM filter x control register (DFSDM_FLTxFCR)
- 907 (DFSDM_FLTxJDATAR)
- 908 (DFSDM_FLTxRDATAR)
- 909 (DFSDM_FLTxAWHTR)
- 909 (DFSDM_FLTxAWLTR)
- 910 (DFSDM_FLTxAWSR)
- 911 (DFSDM_FLTxAWCFR)
- 911 (DFSDM_FLTxEXMAX)
- 912 (DFSDM_FLTxEXMIN)
- 912 26.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)
- 913 26.8.16 DFSDM register map
- 921 Touch sensing controller (TSC)
- 921 Introduction
- 921 TSC main features
- 922 TSC functional description
- 922 TSC block diagram
- 922 Surface charge transfer acquisition overview
- 924 Reset and clocks
- 925 Charge transfer acquisition sequence
- 926 Spread spectrum feature
- 926 Max count error
- 927 Sampling capacitor I/O and channel I/O mode selection
- 928 Acquisition mode
- 928 I/O hysteresis and analog switch control
- 929 TSC low-power modes
- 929 TSC interrupts
- 930 TSC registers
- 930 TSC control register (TSC_CR)
- 932 TSC interrupt enable register (TSC_IER)
- 933 TSC interrupt clear register (TSC_ICR)
- 934 TSC interrupt status register (TSC_ISR)
- 934 TSC I/O hysteresis control register (TSC_IOHCR)
- 935 TSC I/O analog switch control register (TSC_IOASCR)
- 935 TSC I/O sampling control register (TSC_IOSCR)
- 936 TSC I/O channel control register (TSC_IOCCR)
- 936 TSC I/O group control status register (TSC_IOGCSR)
- 937 27.6.10 TSC I/O group x counter register (TSC_IOGxCR)
- 938 27.6.11 TSC register map
- 940 True random number generator (RNG)
- 940 Introduction
- 940 RNG main features
- 941 RNG functional description
- 941 RNG block diagram
- 941 RNG internal signals
- 942 Random number generation
- 945 RNG initialization
- 946 RNG operation
- 947 RNG clocking
- 947 Error management
- 948 RNG low-power usage
- 948 RNG interrupts
- 949 RNG processing time
- 949 RNG entropy source validation
- 949 Introduction
- 949 Validation conditions
- 950 Data collection
- 951 RNG registers
- 951 RNG control register (RNG_CR)
- 953 RNG status register (RNG_SR)
- 954 RNG data register (RNG_DR)
- 954 RNG health test control register (RNG_HTCR)
- 955 RNG register map
- 956 AES hardware accelerator (AES)
- 956 Introduction
- 956 AES main features
- 957 AES implementation
- 957 AES functional description
- 957 AES block diagram
- 957 AES internal signals
- 958 AES cryptographic core
- 963 AES procedure to perform a cipher operation
- 966 AES decryption round key preparation
- 966 AES ciphertext stealing and data padding
- 967 AES task suspend and resume
- 967 AES basic chaining modes (ECB, CBC)
- 972 AES counter (CTR) mode
- 974 29.4.10 AES Galois/counter mode (GCM)
- 979 29.4.11 AES Galois message authentication code (GMAC)
- 981 29.4.12 AES counter with CBC-MAC (CCM)
- 987 29.4.13 AES data registers and data swapping
- 989 29.4.14 AES key registers
- 989 29.4.15 AES initialization vector registers
- 989 29.4.16 AES DMA interface
- 991 29.4.17 AES error management
- 991 AES interrupts
- 992 AES processing latency
- 993 AES registers
- 993 AES control register (AES_CR)
- 995 AES status register (AES_SR)
- 996 AES data input register (AES_DINR)
- 997 AES data output register (AES_DOUTR)
- 998 AES key register 0 (AES_KEYR0)
- 998 AES key register 1 (AES_KEYR1)
- 999 AES key register 2 (AES_KEYR2)
- 999 AES key register 3 (AES_KEYR3)
- 999 AES initialization vector register 0 (AES_IVR0)
- 1000 29.7.10 AES initialization vector register 1 (AES_IVR1)
- 1000 29.7.11 AES initialization vector register 2 (AES_IVR2)
- 1000 29.7.12 AES initialization vector register 3 (AES_IVR3)
- 1001 29.7.13 AES key register 4 (AES_KEYR4)
- 1001 29.7.14 AES key register 5 (AES_KEYR5)
- 1001 29.7.15 AES key register 6 (AES_KEYR6)
- 1002 29.7.16 AES key register 7 (AES_KEYR7)
- 1002 29.7.17 AES suspend registers (AES_SUSPxR)
- 1003 29.7.18 AES register map
- 1005 Hash processor (HASH)
- 1005 Introduction
- 1005 HASH main features
- 1006 HASH implementation
- 1006 HASH functional description
- 1006 HASH block diagram
- 1007 HASH internal signals
- 1007 About secure hash algorithms
- 1007 Message data feeding
- 1009 Message digest computing
- 1010 Message padding
- 1012 HMAC operation
- 1014 HASH suspend/resume operations
- 1016 HASH DMA interface
- 1016 30.4.10 HASH error management
- 1016 HASH interrupts
- 1017 HASH processing time
- 1018 HASH registers
- 1018 HASH control register (HASH_CR)
- 1020 HASH data input register (HASH_DIN)
- 1021 HASH start register (HASH_STR)
- 1022 HASH digest registers
- 1023 HASH interrupt enable register (HASH_IMR)
- 1024 HASH status register (HASH_SR)
- 1024 HASH context swap registers
- 1026 HASH register map
- 1028 On-the-fly decryption engine (OTFDEC)
- 1028 Introduction
- 1028 OTFDEC main features
- 1029 OTFDEC functional description
- 1029 OTFDEC block diagram
- 1029 OTFDEC internal signals
- 1030 OTFDEC on-the-fly decryption
- 1031 AES in counter mode decryption
- 1032 Flow control management
- 1032 OTFDEC error management
- 1033 OTFDEC interrupts
- 1033 OTFDEC application information
- 1033 OTFDEC initialization process
- 1035 OTFDEC and power management
- 1035 Encrypting for OTFDEC
- 1036 OTFDEC key CRC source code
- 1037 OTFDEC registers
- 1037 OTFDEC control register (OTFDEC_CR)
- 1037 (OTFDEC_PRIVCFGR)
- 1038 OTFDEC region x configuration register (OTFDEC_RxCFGR)
- 1039 (OTFDEC_RxSTARTADDR)
- 1040 OTFDEC region x end address register (OTFDEC_RxENDADDR)
- 1041 OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0)
- 1041 OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1)
- 1042 OTFDEC region x key register 0 (OTFDEC_RxKEYR0)
- 1042 OTFDEC region x key register 1 (OTFDEC_RxKEYR1)
- 1043 31.6.10 OTFDEC region x key register 2 (OTFDEC_RxKEYR2)
- 1043 31.6.11 OTFDEC region x key register 3 (OTFDEC_RxKEYR3)
- 1044 31.6.12 OTFDEC interrupt status register (OTFDEC_ISR)
- 1045 31.6.13 OTFDEC interrupt clear register (OTFDEC_ICR)
- 1046 31.6.14 OTFDEC interrupt enable register (OTFDEC_IER)
- 1047 31.6.15 OTFDEC register map
- 1050 Public key accelerator (PKA)
- 1050 Introduction
- 1050 PKA main features
- 1050 PKA functional description
- 1050 PKA block diagram
- 1051 PKA internal signals
- 1051 PKA reset and clocks
- 1051 PKA public key acceleration
- 1053 Typical applications for PKA
- 1055 PKA procedure to perform an operation
- 1056 PKA error management
- 1056 PKA operating modes
- 1056 Introduction
- 1057 Montgomery parameter computation
- 1058 Modular addition
- 1058 Modular subtraction
- 1059 Modular and Montgomery multiplication
- 1060 Modular exponentiation
- 1060 Modular inversion
- 1061 Modular reduction
- 1061 Arithmetic addition
- 1061 32.4.10 Arithmetic subtraction
- 1062 32.4.11 Arithmetic multiplication
- 1062 32.4.12 Arithmetic comparison
- 1063 32.4.13 RSA CRT exponentiation
- 1063 32.4.14 Point on elliptic curve Fp check
- 1064 32.4.15 ECC Fp scalar multiplication
- 1065 32.4.16 ECDSA sign
- 1067 32.4.17 ECDSA verification
- 1068 Example of configurations and processing times
- 1068 Supported elliptic curves
- 1070 Computation times
- 1071 PKA interrupts
- 1072 PKA registers
- 1072 PKA control register (PKA_CR)
- 1073 PKA status register (PKA_SR)
- 1074 PKA clear flag register (PKA_CLRFR)
- 1074 PKA RAM
- 1075 PKA register map
- 1076 Advanced-control timers (TIM1/TIM8)
- 1076 TIM1/TIM8 introduction
- 1076 TIM1/TIM8 main features
- 1078 TIM1/TIM8 functional description
- 1078 Time-base unit
- 1080 Counter modes
- 1091 Repetition counter
- 1093 External trigger input
- 1094 Clock selection
- 1098 Capture/compare channels
- 1100 Input capture mode
- 1101 PWM input mode
- 1102 Forced output mode
- 1103 33.3.10 Output compare mode
- 1104 33.3.11 PWM mode
- 1107 33.3.12 Asymmetric PWM mode
- 1108 33.3.13 Combined PWM mode
- 1109 33.3.14 Combined 3-phase PWM mode
- 1110 33.3.15 Complementary outputs and dead-time insertion
- 1112 33.3.16 Using the break function
- 1118 33.3.17 Bidirectional break inputs
- 1119 33.3.18 Clearing the OCxREF signal on an external event
- 1121 33.3.19 6-step PWM generation
- 1122 33.3.20 One-pulse mode
- 1123 33.3.21 Retriggerable one pulse mode
- 1124 33.3.22 Encoder interface mode
- 1126 33.3.23 UIF bit remapping
- 1127 33.3.24 Timer input XOR function
- 1127 33.3.25 Interfacing with Hall sensors
- 1130 33.3.26 Timer synchronization
- 1134 33.3.27 ADC synchronization
- 1134 33.3.28 DMA burst mode
- 1135 33.3.29 Debug mode
- 1136 TIM1/TIM8 registers
- 1136 TIMx control register 1 (TIMx_CR1)(x = 1, 8)
- 1137 TIMx control register 2 (TIMx_CR2)(x = 1, 8)
- 1140 TIMx slave mode control register (TIMx_SMCR)(x = 1, 8)
- 1142 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8)
- 1144 TIMx status register (TIMx_SR)(x = 1, 8)
- 1146 TIMx event generation register (TIMx_EGR)(x = 1, 8)
- 1147 (TIMx_CCMR1)(x = 1, 8)
- 1151 (TIMx_CCMR2)(x = 1, 8)
- 1154 (TIMx_CCER)(x = 1, 8)
- 1157 33.4.12 TIMx counter (TIMx_CNT)(x = 1, 8)
- 1157 33.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8)
- 1157 33.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8)
- 1158 33.4.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8)
- 1158 33.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8)
- 1159 33.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8)
- 1159 33.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8)
- 1160 33.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8)
- 1160 (TIMx_BDTR)(x = 1, 8)
- 1164 33.4.21 TIMx DMA control register (TIMx_DCR)(x = 1, 8)
- 1165 (TIMx_DMAR)(x = 1, 8)
- 1166 33.4.23 TIM1 option register 1 (TIM1_OR1)
- 1166 33.4.24 TIM8 option register 1 (TIM8_OR1)
- 1167 (TIMx_CCMR3)(x = 1, 8)
- 1168 33.4.26 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8)
- 1169 33.4.27 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8)
- 1169 33.4.28 TIM1 option register 2 (TIM1_OR2)
- 1171 33.4.29 TIM1 option register 3 (TIM1_OR3)
- 1172 33.4.30 TIM8 option register 2 (TIM8_OR2)
- 1174 33.4.31 TIM8 option register 3 (TIM8_OR3)
- 1176 33.4.32 TIM1 register map
- 1178 33.4.33 TIM8 register map
- 1181 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
- 1181 TIM2/TIM3/TIM4/TIM5 introduction
- 1181 TIM2/TIM3/TIM4/TIM5 main features
- 1183 TIM2/TIM3/TIM4/TIM5 functional description
- 1183 Time-base unit
- 1185 Counter modes
- 1195 Clock selection
- 1199 Capture/Compare channels
- 1201 Input capture mode
- 1202 PWM input mode
- 1203 Forced output mode
- 1204 Output compare mode
- 1205 PWM mode
- 1208 34.3.10 Asymmetric PWM mode
- 1209 34.3.11 Combined PWM mode
- 1210 34.3.12 Clearing the OCxREF signal on an external event
- 1212 34.3.13 One-pulse mode
- 1213 34.3.14 Retriggerable one pulse mode
- 1214 34.3.15 Encoder interface mode
- 1216 34.3.16 UIF bit remapping
- 1216 34.3.17 Timer input XOR function
- 1217 34.3.18 Timers and external trigger synchronization
- 1220 34.3.19 Timer synchronization
- 1225 34.3.20 DMA burst mode
- 1226 34.3.21 Debug mode
- 1227 TIM2/TIM3/TIM4/TIM5 registers
- 1227 TIMx control register 1 (TIMx_CR1)(x = 2 to 5)
- 1228 TIMx control register 2 (TIMx_CR2)(x = 2 to 5)
- 1230 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5)
- 1233 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5)
- 1234 TIMx status register (TIMx_SR)(x = 2 to 5)
- 1235 TIMx event generation register (TIMx_EGR)(x = 2 to 5)
- 1236 (x = 2 to 5)
- 1240 (x = 2 to 5)
- 1242 (TIMx_CCER)(x = 2 to 5)
- 1243 34.4.12 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5)
- 1244 34.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5)
- 1244 34.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5)
- 1245 34.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5)
- 1245 34.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5)
- 1246 34.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5)
- 1246 34.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5)
- 1247 34.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5)
- 1248 34.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 5)
- 1248 34.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5)
- 1248 34.4.22 TIM2 option register 1 (TIM2_OR1)
- 1249 34.4.23 TIM3 option register 1 (TIM3_OR1)
- 1249 34.4.24 TIM2 option register 2 (TIM2_OR2)
- 1250 34.4.25 TIM3 option register 2 (TIM3_OR2)
- 1251 34.4.26 TIMx register map
- 1254 General-purpose timers (TIM15/TIM16/TIM17)
- 1254 TIM15/TIM16/TIM17 introduction
- 1254 TIM15 main features
- 1255 TIM16/TIM17 main features
- 1258 TIM15/TIM16/TIM17 functional description
- 1258 Time-base unit
- 1260 Counter modes
- 1264 Repetition counter
- 1265 Clock selection
- 1267 Capture/compare channels
- 1269 Input capture mode
- 1270 PWM input mode (only for TIM15)
- 1271 Forced output mode
- 1272 Output compare mode
- 1273 35.4.10 PWM mode
- 1274 35.4.11 Combined PWM mode (TIM15 only)
- 1275 35.4.12 Complementary outputs and dead-time insertion
- 1277 35.4.13 Using the break function
- 1282 35.4.14 Bidirectional break inputs
- 1284 35.4.15 One-pulse mode
- 1286 35.4.16 Retriggerable one pulse mode (TIM15 only)
- 1286 35.4.17 UIF bit remapping
- 1288 35.4.18 Timer input XOR function (TIM15 only)
- 1289 35.4.19 External trigger synchronization (TIM15 only)
- 1291 35.4.20 Slave mode – combined reset + trigger mode
- 1291 35.4.21 DMA burst mode
- 1293 35.4.22 Timer synchronization (TIM15)
- 1293 35.4.23 Using timer output as trigger for other timers (TIM16/TIM17)
- 1293 35.4.24 Debug mode
- 1294 TIM15 registers
- 1294 TIM15 control register 1 (TIM15_CR1)
- 1295 TIM15 control register 2 (TIM15_CR2)
- 1297 TIM15 slave mode control register (TIM15_SMCR)
- 1298 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 1299 TIM15 status register (TIM15_SR)
- 1301 TIM15 event generation register (TIM15_EGR)
- 1302 (TIM15_CCMR1)
- 1306 TIM15 capture/compare enable register (TIM15_CCER)
- 1309 35.5.10 TIM15 counter (TIM15_CNT)
- 1309 35.5.11 TIM15 prescaler (TIM15_PSC)
- 1309 35.5.12 TIM15 auto-reload register (TIM15_ARR)
- 1310 35.5.13 TIM15 repetition counter register (TIM15_RCR)
- 1310 35.5.14 TIM15 capture/compare register 1 (TIM15_CCR1)
- 1311 35.5.15 TIM15 capture/compare register 2 (TIM15_CCR2)
- 1311 35.5.16 TIM15 break and dead-time register (TIM15_BDTR)
- 1314 35.5.17 TIM15 DMA control register (TIM15_DCR)
- 1314 35.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)
- 1315 35.5.19 TIM15 option register 1 (TIM15_OR1)
- 1315 35.5.20 TIM15 option register 2 (TIM15_OR2)
- 1317 35.5.21 TIM15 register map
- 1320 TIM16/TIM17 registers
- 1320 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)
- 1321 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)
- 1322 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)
- 1323 TIMx status register (TIMx_SR)(x = 16 to 17)
- 1324 TIMx event generation register (TIMx_EGR)(x = 16 to 17)
- 1325 (x = 16 to 17)
- 1330 TIMx counter (TIMx_CNT)(x = 16 to 17)
- 1331 35.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)
- 1331 35.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)
- 1332 35.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)
- 1332 35.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)
- 1333 35.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)
- 1335 35.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17)
- 1336 35.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17)
- 1336 35.6.17 TIM16 option register 1 (TIM16_OR1)
- 1337 35.6.18 TIM16 option register 2 (TIM16_OR2)
- 1338 35.6.19 TIM17 option register 1 (TIM17_OR1)
- 1339 35.6.20 TIM17 option register 2 (TIM17_OR2)
- 1341 35.6.21 TIM16/TIM17 register map
- 1343 Basic timers (TIM6/TIM7)
- 1343 TIM6/TIM7 introduction
- 1343 TIM6/TIM7 main features
- 1344 TIM6/TIM7 functional description
- 1344 Time-base unit
- 1346 Counting mode
- 1349 UIF bit remapping
- 1349 Clock source
- 1350 Debug mode
- 1350 TIM6/TIM7 registers
- 1350 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)
- 1352 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)
- 1352 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)
- 1353 TIMx status register (TIMx_SR)(x = 6 to 7)
- 1353 TIMx event generation register (TIMx_EGR)(x = 6 to 7)
- 1353 TIMx counter (TIMx_CNT)(x = 6 to 7)
- 1354 TIMx prescaler (TIMx_PSC)(x = 6 to 7)
- 1354 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)
- 1355 TIMx register map
- 1356 Low-power timer (LPTIM)
- 1356 Introduction
- 1356 LPTIM main features
- 1357 LPTIM implementation
- 1357 LPTIM functional description
- 1357 LPTIM block diagram
- 1358 LPTIM pins and internal signals
- 1358 LPTIM trigger mapping
- 1359 LPTIM reset and clocks
- 1360 Glitch filter
- 1361 Prescaler
- 1361 Trigger multiplexer
- 1362 Operating mode
- 1364 Timeout function
- 1364 37.4.10 Waveform generation
- 1365 37.4.11 Register update
- 1366 37.4.12 Counter mode
- 1366 37.4.13 Timer enable
- 1367 37.4.14 Timer counter reset
- 1367 37.4.15 Encoder mode
- 1369 37.4.16 Repetition Counter
- 1370 37.4.17 Debug mode
- 1371 LPTIM low-power modes
- 1371 LPTIM interrupts
- 1372 LPTIM registers
- 1372 LPTIM interrupt and status register (LPTIM_ISR)
- 1373 LPTIM interrupt clear register (LPTIM_ICR)
- 1374 LPTIM interrupt enable register (LPTIM_IER)
- 1375 LPTIM configuration register (LPTIM_CFGR)
- 1378 LPTIM control register (LPTIM_CR)
- 1379 LPTIM compare register (LPTIM_CMP)
- 1379 LPTIM autoreload register (LPTIM_ARR)
- 1380 LPTIM counter register (LPTIM_CNT)
- 1380 LPTIM1 option register (LPTIM1_OR)
- 1381 37.7.10 LPTIM2 option register (LPTIM2_OR)
- 1381 37.7.11 LPTIM3 option register (LPTIM3_OR)
- 1382 37.7.12 LPTIM repetition register (LPTIM_RCR)
- 1383 37.7.13 LPTIM register map
- 1385 Infrared interface (IRTIM)
- 1386 Independent watchdog (IWDG)
- 1386 Introduction
- 1386 IWDG main features
- 1386 IWDG functional description
- 1386 IWDG block diagram
- 1387 Window option
- 1388 Hardware watchdog
- 1388 Low-power freeze
- 1388 Register access protection
- 1388 Debug mode
- 1389 IWDG registers
- 1389 IWDG key register (IWDG_KR)
- 1390 IWDG prescaler register (IWDG_PR)
- 1391 IWDG reload register (IWDG_RLR)
- 1392 IWDG status register (IWDG_SR)
- 1393 IWDG window register (IWDG_WINR)
- 1394 IWDG register map
- 1395 System window watchdog (WWDG)
- 1395 Introduction
- 1395 WWDG main features
- 1395 WWDG functional description
- 1396 WWDG block diagram
- 1396 Enabling the watchdog
- 1396 Controlling the down-counter
- 1396 How to program the watchdog timeout
- 1397 Debug mode
- 1398 WWDG interrupts
- 1398 WWDG registers
- 1398 WWDG control register (WWDG_CR)
- 1399 WWDG configuration register (WWDG_CFR)
- 1399 WWDG status register (WWDG_SR)
- 1399 WWDG register map
- 1401 Real-time clock (RTC)
- 1401 Introduction
- 1401 RTC main features
- 1402 RTC functional description
- 1402 RTC block diagram
- 1404 RTC pins and internal signals
- 1405 GPIOs controlled by the RTC and TAMP
- 1407 RTC secure protection modes
- 1409 RTC privilege protection modes
- 1410 Clock and prescalers
- 1411 Real-time clock and calendar
- 1411 Calendar ultra-low power mode
- 1411 Programmable alarms
- 1412 41.3.10 Periodic auto-wakeup
- 1413 41.3.11 RTC initialization and configuration
- 1415 41.3.12 Reading the calendar
- 1416 41.3.13 Resetting the RTC
- 1416 41.3.14 RTC synchronization
- 1417 41.3.15 RTC reference clock detection
- 1418 41.3.16 RTC smooth digital calibration
- 1420 41.3.17 Timestamp function
- 1420 41.3.18 Calibration clock output
- 1421 41.3.19 Tamper and alarm output
- 1422 RTC low-power modes
- 1423 RTC interrupts
- 1425 RTC registers
- 1425 RTC time register (RTC_TR)
- 1426 RTC date register (RTC_DR)
- 1427 RTC sub second register (RTC_SSR)
- 1427 RTC initialization control and status register (RTC_ICSR)
- 1429 RTC prescaler register (RTC_PRER)
- 1430 RTC wakeup timer register (RTC_WUTR)
- 1430 RTC control register (RTC_CR)
- 1434 RTC privilege mode control register (RTC_PRIVCR)
- 1435 RTC secure mode control register (RTC_SMCR)
- 1437 41.6.10 RTC write protection register (RTC_WPR)
- 1437 41.6.11 RTC calibration register (RTC_CALR)
- 1439 41.6.12 RTC shift control register (RTC_SHIFTR)
- 1440 41.6.13 RTC timestamp time register (RTC_TSTR)
- 1441 41.6.14 RTC timestamp date register (RTC_TSDR)
- 1442 41.6.15 RTC timestamp sub second register (RTC_TSSSR)
- 1442 41.6.16 RTC alarm A register (RTC_ALRMAR)
- 1444 41.6.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 1445 41.6.18 RTC alarm B register (RTC_ALRMBR)
- 1446 41.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)
- 1447 41.6.20 RTC status register (RTC_SR)
- 1448 41.6.21 RTC non-secure masked interrupt status register (RTC_MISR)
- 1449 41.6.22 RTC secure masked interrupt status register (RTC_SMISR)
- 1450 41.6.23 RTC status clear register (RTC_SCR)
- 1451 41.6.24 RTC register map
- 1453 Tamper and backup registers (TAMP)
- 1453 Introduction
- 1453 TAMP main features
- 1454 TAMP functional description
- 1454 TAMP block diagram
- 1455 TAMP pins and internal signals
- 1456 TAMP register write protection
- 1456 TAMP secure protection modes
- 1457 TAMP privilege protection modes
- 1457 Tamper detection
- 1461 TAMP low-power modes
- 1462 TAMP interrupts
- 1462 TAMP registers
- 1462 TAMP control register 1 (TAMP_CR1)
- 1464 TAMP control register 2 (TAMP_CR2)
- 1467 TAMP control register 3 (TAMP_CR3)
- 1468 TAMP filter control register (TAMP_FLTCR)
- 1469 TAMP active tamper control register 1 (TAMP_ATCR1)
- 1472 TAMP active tamper seed register (TAMP_ATSEEDR)
- 1472 TAMP active tamper output register (TAMP_ATOR)
- 1473 TAMP active tamper control register 2 (TAMP_ATCR2)
- 1476 TAMP secure mode register (TAMP_SMCR)
- 1477 42.6.10 TAMP privilege mode control register (TAMP_PRIVCR)
- 1478 42.6.11 TAMP interrupt enable register (TAMP_IER)
- 1479 42.6.12 TAMP status register (TAMP_SR)
- 1481 42.6.13 TAMP non-secure masked interrupt status register (TAMP_MISR)
- 1482 42.6.14 TAMP secure masked interrupt status register (TAMP_SMISR)
- 1483 42.6.15 TAMP status clear register (TAMP_SCR)
- 1485 42.6.16 TAMP monotonic counter register (TAMP_COUNTR)
- 1485 42.6.17 TAMP configuration register (TAMP_CFGR)
- 1486 42.6.18 TAMP backup x register (TAMP_BKPxR)
- 1487 42.6.19 TAMP register map
- 1489 Inter-integrated circuit (I2C) interface
- 1489 Introduction
- 1489 I2C main features
- 1490 I2C implementation
- 1490 I2C functional description
- 1491 I2C block diagram
- 1492 I2C pins and internal signals
- 1492 I2C clock requirements
- 1493 Mode selection
- 1493 I2C initialization
- 1498 Software reset
- 1499 Data transfer
- 1501 I2C slave mode
- 1510 I2C master mode
- 1522 43.4.10 I2C_TIMINGR register configuration examples
- 1523 43.4.11 SMBus specific features
- 1526 43.4.12 SMBus initialization
- 1528 43.4.13 SMBus: I2C_TIMEOUTR register configuration examples
- 1529 43.4.14 SMBus slave mode
- 1536 43.4.15 Wakeup from Stop mode on address match
- 1536 43.4.16 Error conditions
- 1538 43.4.17 DMA requests
- 1539 43.4.18 Debug mode
- 1539 I2C low-power modes
- 1540 I2C interrupts
- 1541 I2C registers
- 1541 I2C control register 1 (I2C_CR1)
- 1544 I2C control register 2 (I2C_CR2)
- 1546 I2C own address 1 register (I2C_OAR1)
- 1547 I2C own address 2 register (I2C_OAR2)
- 1548 I2C timing register (I2C_TIMINGR)
- 1549 I2C timeout register (I2C_TIMEOUTR)
- 1550 I2C interrupt and status register (I2C_ISR)
- 1552 I2C interrupt clear register (I2C_ICR)
- 1553 I2C PEC register (I2C_PECR)
- 1554 43.7.10 I2C receive data register (I2C_RXDR)
- 1554 43.7.11 I2C transmit data register (I2C_TXDR)
- 1554 43.7.12 I2C hardware configuration register (I2C_HWCFGR)
- 1555 43.7.13 I2C version register (I2C_VERR)
- 1555 43.7.14 I2C identification register (I2C_IPIDR)
- 1556 43.7.15 I2C size identification register (I2C_SIDR)
- 1557 43.7.16 I2C register map
- 1559 transmitter (USART/UART)
- 1559 USART introduction
- 1560 USART main features
- 1561 USART extended features
- 1561 USART implementation
- 1562 USART functional description
- 1562 USART block diagram
- 1563 USART signals
- 1564 USART character description
- 1566 USART FIFOs and thresholds
- 1566 USART transmitter
- 1570 USART receiver
- 1577 USART baud rate generation
- 1578 Tolerance of the USART receiver to clock deviation
- 1580 USART Auto baud rate detection
- 1582 44.5.10 USART multiprocessor communication
- 1584 44.5.11 USART Modbus communication
- 1585 44.5.12 USART parity control
- 1586 44.5.13 USART LIN (local interconnection network) mode
- 1588 44.5.14 USART synchronous mode
- 1592 44.5.15 USART single-wire Half-duplex communication
- 1592 44.5.16 USART receiver timeout
- 1593 44.5.17 USART Smartcard mode
- 1597 44.5.18 USART IrDA SIR ENDEC block
- 1600 44.5.19 Continuous communication using USART and DMA
- 1602 44.5.20 RS232 Hardware flow control and RS485 Driver Enable
- 1605 44.5.21 USART low-power management
- 1608 USART in low-power modes
- 1609 USART interrupts
- 1610 USART registers
- 1610 USART control register 1 [alternate] (USART_CR1)
- 1617 USART control register 2 (USART_CR2)
- 1621 USART control register 3 (USART_CR3)
- 1626 USART baud rate register (USART_BRR)
- 1626 USART guard time and prescaler register (USART_GTPR)
- 1627 USART receiver timeout register (USART_RTOR)
- 1628 USART request register (USART_RQR)
- 1629 USART interrupt and status register [alternate] (USART_ISR)
- 1635 44.8.10 USART interrupt and status register [alternate] (USART_ISR)
- 1640 44.8.11 USART interrupt flag clear register (USART_ICR)
- 1642 44.8.12 USART receive data register (USART_RDR)
- 1642 44.8.13 USART transmit data register (USART_TDR)
- 1643 44.8.14 USART prescaler register (USART_PRESC)
- 1644 44.8.15 USART register map
- 1646 transmitter (LPUART)
- 1646 LPUART introduction
- 1647 LPUART main features
- 1648 LPUART implementation
- 1649 LPUART functional description
- 1649 LPUART block diagram
- 1650 LPUART signals
- 1650 LPUART character description
- 1651 LPUART FIFOs and thresholds
- 1652 LPUART transmitter
- 1655 LPUART receiver
- 1659 LPUART baud rate generation
- 1660 Tolerance of the LPUART receiver to clock deviation
- 1661 LPUART multiprocessor communication
- 1663 45.4.10 LPUART parity control
- 1664 45.4.11 LPUART single-wire Half-duplex communication
- 1664 45.4.12 Continuous communication using DMA and LPUART
- 1667 45.4.13 RS232 Hardware flow control and RS485 Driver Enable
- 1669 45.4.14 LPUART low-power management
- 1672 LPUART in low-power modes
- 1673 LPUART interrupts
- 1674 LPUART registers
- 1674 LPUART control register 1 [alternate] (LPUART_CR1)
- 1680 LPUART control register 2 (LPUART_CR2)
- 1682 LPUART control register 3 (LPUART_CR3)
- 1685 LPUART baud rate register (LPUART_BRR)
- 1686 LPUART request register (LPUART_RQR)
- 1686 LPUART interrupt and status register [alternate] (LPUART_ISR)
- 1694 LPUART interrupt flag clear register (LPUART_ICR)
- 1695 45.7.10 LPUART receive data register (LPUART_RDR)
- 1695 45.7.11 LPUART transmit data register (LPUART_TDR)
- 1696 45.7.12 LPUART prescaler register (LPUART_PRESC)
- 1697 45.7.13 LPUART register map
- 1699 Serial peripheral interface (SPI)
- 1699 Introduction
- 1699 SPI main features
- 1699 SPI implementation
- 1700 SPI functional description
- 1700 General description
- 1701 Communications between one master and one slave
- 1703 Standard multi-slave communication
- 1704 Multi-master communication
- 1705 Slave select (NSS) pin management
- 1706 Communication formats
- 1708 Configuration of SPI
- 1709 Procedure for enabling SPI
- 1709 Data transmission and reception procedures
- 1719 46.4.10 SPI status flags
- 1720 46.4.11 SPI error flags
- 1721 46.4.12 NSS pulse mode
- 1721 46.4.13 TI mode
- 1722 46.4.14 CRC calculation
- 1724 SPI interrupts
- 1725 SPI registers
- 1725 SPI control register 1 (SPIx_CR1)
- 1727 SPI control register 2 (SPIx_CR2)
- 1729 SPI status register (SPIx_SR)
- 1730 SPI data register (SPIx_DR)
- 1731 SPI CRC polynomial register (SPIx_CRCPR)
- 1731 SPI Rx CRC register (SPIx_RXCRCR)
- 1731 SPI Tx CRC register (SPIx_TXCRCR)
- 1733 SPI register map
- 1734 Serial audio interface (SAI)
- 1734 Introduction
- 1734 SAI main features
- 1735 SAI implementation
- 1735 SAI functional description
- 1735 SAI block diagram
- 1737 SAI pins and internal signals
- 1737 Main SAI modes
- 1738 SAI synchronization mode
- 1739 Audio data size
- 1740 Frame synchronization
- 1743 Slot configuration
- 1745 SAI clock generator
- 1748 Internal FIFOs
- 1750 47.4.10 PDM Interface
- 1758 47.4.11 AC’97 link controller
- 1760 47.4.12 SPDIF output
- 1763 47.4.13 Specific features
- 1767 47.4.14 Error flags
- 1770 47.4.15 Disabling the SAI
- 1770 47.4.16 SAI DMA interface
- 1771 SAI interrupts
- 1773 SAI registers
- 1773 SAI global configuration register (SAI_GCR)
- 1773 SAI configuration register 1 (SAI_ACR1)
- 1776 SAI configuration register 1 (SAI_BCR1)
- 1779 SAI configuration register 2 (SAI_ACR2)
- 1781 SAI configuration register 2 (SAI_BCR2)
- 1783 SAI frame configuration register (SAI_AFRCR)
- 1784 SAI frame configuration register (SAI_BFRCR)
- 1785 SAI slot register (SAI_ASLOTR)
- 1786 SAI slot register (SAI_BSLOTR)
- 1787 47.6.10 SAI interrupt mask register (SAI_AIM)
- 1789 47.6.11 SAI interrupt mask register (SAI_BIM)
- 1790 47.6.12 SAI status register (SAI_ASR)
- 1792 47.6.13 SAI status register (SAI_BSR)
- 1794 47.6.14 SAI clear flag register (SAI_ACLRFR)
- 1795 47.6.15 SAI clear flag register (SAI_BCLRFR)
- 1796 47.6.16 SAI data register (SAI_ADR)
- 1797 47.6.17 SAI data register (SAI_BDR)
- 1797 47.6.18 SAI PDM control register (SAI_PDMCR)
- 1798 47.6.19 SAI PDM delay register (SAI_PDMDLY)
- 1801 47.6.20 SAI register map
- 1803 Secure digital input/output MultiMediaCard interface (SDMMC)
- 1803 SDMMC main features
- 1803 SDMMC bus topology
- 1805 SDMMC operation modes
- 1806 SDMMC functional description
- 1806 SDMMC block diagram
- 1807 SDMMC pins and internal signals
- 1807 General description
- 1809 SDMMC adapter
- 1831 SDMMC AHB slave interface
- 1831 SDMMC AHB master interface
- 1833 AHB and SDMMC_CK clock relation
- 1834 Card functional description
- 1834 SD I/O mode
- 1842 CMD12 send timing
- 1845 Sleep (CMD5)
- 1846 Interrupt mode (Wait-IRQ)
- 1847 Boot operation
- 1850 Response R1b handling
- 1851 Reset and card cycle power
- 1852 Hardware flow control
- 1853 Ultra-high-speed phase I (UHS-I) voltage switch
- 1856 SDMMC interrupts
- 1858 SDMMC registers
- 1858 SDMMC power control register (SDMMC_POWER)
- 1859 SDMMC clock control register (SDMMC_CLKCR)
- 1861 SDMMC argument register (SDMMC_ARGR)
- 1861 SDMMC command register (SDMMC_CMDR)
- 1863 SDMMC command response register (SDMMC_RESPCMDR)
- 1864 SDMMC response x register (SDMMC_RESPxR)
- 1864 SDMMC data timer register (SDMMC_DTIMER)
- 1865 SDMMC data length register (SDMMC_DLENR)
- 1866 SDMMC data control register (SDMMC_DCTRL)
- 1867 48.9.10 SDMMC data counter register (SDMMC_DCNTR)
- 1868 48.9.11 SDMMC status register (SDMMC_STAR)
- 1871 48.9.12 SDMMC interrupt clear register (SDMMC_ICR)
- 1873 48.9.13 SDMMC mask register (SDMMC_MASKR)
- 1876 48.9.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER)
- 1876 48.9.15 SDMMC data FIFO registers x (SDMMC_FIFORx)
- 1877 48.9.16 SDMMC DMA control register (SDMMC_IDMACTRLR)
- 1878 48.9.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER)
- 1878 (SDMMC_IDMABASE0R)
- 1879 (SDMMC_IDMABASE1R)
- 1880 48.9.20 SDMMC register map
- 1883 FD controller area network (FDCAN)
- 1883 Introduction
- 1885 FDCAN main features
- 1886 FDCAN functional description
- 1887 Bit timing
- 1888 Operating modes
- 1897 Message RAM
- 1905 FIFO acknowledge handling
- 1906 FDCAN Rx FIFO element
- 1908 FDCAN Tx buffer element
- 1910 FDCAN Tx event FIFO element
- 1911 FDCAN Standard message ID Filter element
- 1912 FDCAN Extended message ID filter element
- 1913 FDCAN registers
- 1913 FDCAN core release register (FDCAN_CREL)
- 1913 FDCAN endian register (FDCAN_ENDN)
- 1914 FDCAN data bit timing and prescaler register (FDCAN_DBTP)
- 1915 FDCAN test register (FDCAN_TEST)
- 1915 FDCAN RAM watchdog register (FDCAN_RWD)
- 1916 FDCAN CC control register (FDCAN_CCCR)
- 1918 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP)
- 1920 FDCAN timestamp counter value register (FDCAN_TSCV)
- 1921 49.4.10 FDCAN timeout counter configuration register (FDCAN_TOCC)
- 1921 49.4.11 FDCAN timeout counter value register (FDCAN_TOCV)
- 1922 49.4.12 FDCAN error counter register (FDCAN_ECR)
- 1922 49.4.13 FDCAN protocol status register (FDCAN_PSR)
- 1925 49.4.14 FDCAN transmitter delay compensation register (FDCAN_TDCR)
- 1925 49.4.15 FDCAN interrupt register (FDCAN_IR)
- 1928 49.4.16 FDCAN interrupt enable register (FDCAN_IE)
- 1930 49.4.17 FDCAN interrupt line select register (FDCAN_ILS)
- 1931 49.4.18 FDCAN interrupt line enable register (FDCAN_ILE)
- 1931 49.4.19 FDCAN global filter configuration register (FDCAN_RXGFC)
- 1933 49.4.20 FDCAN extended ID and mask register (FDCAN_XIDAM)
- 1933 49.4.21 FDCAN high-priority message status register (FDCAN_HPMS)
- 1934 49.4.22 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S)
- 1935 49.4.23 CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A)
- 1935 49.4.24 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S)
- 1936 49.4.25 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A)
- 1936 49.4.26 FDCAN Tx buffer configuration register (FDCAN_TXBC)
- 1937 49.4.27 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS)
- 1938 49.4.28 FDCAN Tx buffer request pending register (FDCAN_TXBRP)
- 1939 49.4.29 FDCAN Tx buffer add request register (FDCAN_TXBAR)
- 1939 49.4.30 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR)
- 1940 49.4.32 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF)
- 1941 (FDCAN_TXBTIE)
- 1941 (FDCAN_ TXBCIE)
- 1942 49.4.35 FDCAN Tx event FIFO status register (FDCAN_TXEFS)
- 1942 49.4.36 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA)
- 1943 49.4.37 FDCAN CFG clock divider register (FDCAN_CKDIV)
- 1944 49.4.38 FDCAN register map
- 1948 Universal serial bus full-speed device interface (USB)
- 1948 Introduction
- 1948 USB main features
- 1948 USB implementation
- 1949 USB functional description
- 1950 Description of USB blocks
- 1951 Programming considerations
- 1951 Generic USB device programming
- 1952 System and power-on reset
- 1957 Double-buffered endpoints
- 1959 Isochronous transfers
- 1960 Suspend/Resume events
- 1963 USB and USB SRAM registers
- 1963 Common registers
- 1976 Buffer descriptor table
- 1979 USB register map
- 1981 USB Type-C™ / USB Power Delivery interface (UCPD)
- 1981 Introduction
- 1981 UCPD main features
- 1981 UCPD implementation
- 1982 UCPD functional description
- 1983 UCPD block diagram
- 1984 UCPD reset and clocks
- 1985 Physical layer protocol
- 1992 UCPD BMC transmitter
- 1993 UCPD BMC receiver
- 1995 UCPD Type-C pull-ups (Rp) and pull-downs (Rd)
- 1995 UCPD Type-C voltage monitoring and de-bouncing
- 1995 UCPD fast role swap (FRS) signaling and detection
- 1996 UCPD DMA Interface
- 1996 51.4.10 Wakeup from Stop mode
- 1996 51.4.11 UCPD programming sequences
- 2000 UCPD low-power modes
- 2001 UCPD interrupts
- 2002 UCPD registers
- 2002 UCPD configuration register 1 (UCPD_CFGR1)
- 2004 UCPD configuration register 2 (UCPD_CFGR2)
- 2004 UCPD configuration register 3 (UCPD_CFGR3)
- 2005 UCPD control register (UCPD_CR)
- 2007 UCPD interrupt mask register (UCPD_IMR)
- 2009 UCPD status register (UCPD_SR)
- 2012 UCPD interrupt clear register (UCPD_ICR)
- 2013 UCPD Tx ordered set type register (UCPD_TX_ORDSETR)
- 2013 UCPD Tx payload size register (UCPD_TX_PAYSZR)
- 2014 51.7.10 UCPD Tx data register (UCPD_TXDR)
- 2014 51.7.11 UCPD Rx ordered set register (UCPD_RX_ORDSETR)
- 2015 51.7.12 UCPD Rx payload size register (UCPD_RX_PAYSZR)
- 2016 51.7.13 UCPD receive data register (UCPD_RXDR)
- 2016 (UCPD_RX_ORDEXTR1)
- 2017 (UCPD_RX_ORDEXTR2)
- 2017 51.7.16 UCPD register map
- 2020 Debug support (DBG)
- 2020 Introduction
- 2021 DBG functional description
- 2021 DBG block diagram
- 2021 DBG pins and internal signals
- 2022 DBG reset and clocks
- 2022 DBG power domains
- 2022 Debug and low-power modes
- 2023 Security
- 2024 Serial-wire and JTAG debug port (SWJ-DP)
- 2025 JTAG debug port
- 2027 Serial-wire debug port
- 2028 52.2.10 Debug port registers
- 2036 52.2.11 Debug port register map and reset values
- 2037 Access ports
- 2037 Access port registers
- 2042 Access port register map and reset values
- 2043 ROM tables
- 2046 MCU ROM table registers
- 2051 MCU ROM table register map and reset values
- 2052 Processor ROM table registers
- 2057 Processor ROM table register map and reset values
- 2058 Data watchpoint and trace unit (DWT)
- 2059 DWT registers
- 2074 DWT register map and reset values
- 2076 Instrumentation trace macrocell (ITM)
- 2077 ITM registers
- 2086 ITM register map and reset values
- 2087 Breakpoint unit (BPU)
- 2088 BPU registers
- 2095 BPU register map and reset values
- 2096 Embedded Trace Macrocell™ (ETM)
- 2097 ETM registers
- 2123 ETM register map and reset values
- 2127 Trace port interface unit (TPIU)
- 2128 TPIU registers
- 2139 TPIU register map and reset values
- 2141 52.10 Cross-trigger interface (CTI)
- 2142 52.10.1 CTI registers
- 2154 52.10.2 CTI register map and reset values
- 2156 52.11 Microcontroller debug unit (DBGMCU)
- 2157 52.11.1 DBGMCU registers
- 2162 52.11.2 DBGMCU register map and reset values
- 2163 52.12 References
- 2164 Device electronic signature
- 2165 Unique device ID register (96 bits)
- 2166 Flash size data register
- 2167 Package data register
- 2168 Revision history
Frequently Answers and Questions
What is the Arm® Cortex®-M33 core?
The Arm® Cortex®-M33 core is a high-performance, energy-efficient processor core designed for embedded applications.
What are the benefits of using TrustZone® technology?
TrustZone® technology provides advanced security features to protect sensitive data and applications from unauthorized access.
What types of applications are suitable for the STM32L552xx and STM32L562xx MCUs?
The STM32L552xx and STM32L562xx MCUs are suitable for a wide range of applications, including industrial automation, healthcare, consumer electronics, and IoT devices.
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