STMicroelectronics ST10R272L
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Pages: 321 STMicroelectronics ST10R272L User manual
Brand: STMicroelectronics Category: Processors Size: 1 MB
Languages: English
Table of contents
- 10 1 INTRODUCTION
- 11 2 ARCHITECTURAL OVERVIEW
- 12 BASIC CPU CONCEPTS
- 13 2.1.1 High instruction bandwidth / fast execution
- 13 2.1.2 High function 8-bit and 16-bit arithmetic and logic unit
- 14 2.1.3 Extended bit processing and peripheral control
- 14 2.1.4 High performance branch, call, and loop processing
- 15 2.1.5 Instruction formats
- 15 2.1.6 Programmable multiple priority interrupt system
- 16 ON-CHIP SYSTEM RESOURCES
- 16 2.2.1 Peripheral event controller (PEC) and interrupt control
- 16 2.2.2 Memory areas
- 17 2.2.3 External bus interface
- 18 SYSTEM CLOCK GENERATOR
- 20 2.3.1 PLL operation
- 20 2.3.2 Prescaler operation
- 20 2.3.3 Direct drive
- 21 2.3.4 Oscillator watchdog (OWD)
- 21 ON-CHIP PERIPHERAL BLOCKS
- 21 2.4.1 Peripheral interfaces
- 22 2.4.2 Peripheral timing
- 22 2.4.3 Programming hints
- 23 2.4.4 Reserved bits
- 23 2.4.5 Parallel ports
- 23 2.4.6 Serial channels
- 24 2.4.7 General purpose timer (GPT)
- 24 2.4.8 Watchdog timer
- 24 PROTECTED BITS
- 26 3 MEMORY ORGANIZATION
- 28 INTERNAL RAM AND SFR AREA
- 30 3.1.1 System stack
- 31 3.1.2 General purpose registers
- 32 3.1.3 PEC source and destination pointers
- 33 3.1.4 Special function registers
- 34 EXTERNAL MEMORY SPACE
- 35 CROSSING MEMORY BOUNDARIES
- 37 4 CENTRAL PROCESSING UNIT
- 39 INSTRUCTION PIPELINING
- 39 4.1.1 Sequential instruction processing
- 40 4.1.2 Standard branch instruction processing
- 41 4.1.3 Jump cache instruction processing
- 42 4.1.4 Pipeline effects
- 46 BIT-HANDLING AND BIT-PROTECTION
- 47 INSTRUCTION EXECUTION TIME
- 48 CPU SPECIAL FUNCTION REGISTERS
- 48 4.4.1 The system configuration register SYSCON
- 68 5 MULTIPLY-ACCUMULATE UNIT (MAC)
- 69 MAC FEATURES
- 70 MAC OPERATION
- 70 5.2.1 Instruction pipelining
- 71 5.2.2 Address generation
- 73 5.2.3 16 x 16 signed/unsigned parallel multiplier
- 73 5.2.4 40-bit signed arithmetic unit
- 74 5.2.5 40-bit accumulator register
- 74 5.2.6 Data limiter
- 75 5.2.7 Accumulator shifter
- 75 5.2.8 Repeat unit
- 76 5.2.9 MAC interrupt
- 77 5.2.10Number representation & rounding
- 78 MAC REGISTER SET
- 78 5.3.1 Address registers
- 78 5.3.2 Accumulator & control registers
- 82 MAC INSTRUCTION SET SUMMARY
- 84 6 INTERRUPT AND TRAP FUNCTIONS
- 84 INTERRUPT SYSTEM STRUCTURE
- 85 6.1.1 Interrupt sources
- 86 6.1.2 Normal interrupt processing and PEC service
- 87 6.1.3 Interrupt system registers
- 87 6.1.4 Interrupt control registers
- 90 6.1.5 Interrupt control functions in the PSW
- 92 OPERATION OF THE PEC CHANNELS
- 95 PRIORITIZING INTERRUPT AND PEC SERVICE REQUESTS
- 96 INTERRUPT CLASS MANAGEMENT
- 97 SAVING THE STATUS DURING INTERRUPT SERVICE
- 98 6.5.1 Context switching
- 99 INTERRUPT RESPONSE TIMES
- 101 PEC RESPONSE TIMES
- 103 EXTERNAL INTERRUPTS
- 104 6.8.1 Fast external interrupts
- 106 TRAPS
- 106 6.9.1 Software traps
- 106 6.9.2 Hardware traps
- 107 6.9.3 Trap flag register
- 109 6.9.4 External NMI trap
- 109 6.9.5 Stack overflow trap
- 109 6.9.6 Stack underflow trap
- 110 6.9.7 Undefined opcode trap
- 110 6.9.8 Protection fault trap
- 110 6.9.9 Illegal word operand access trap
- 110 6.9.10Illegal instruction access trap
- 110 6.9.11Illegal external bus access trap
- 111 6.9.12MAC interrupt on condition
- 112 7 PARALLEL PORTS
- 117 7.1.1 Alternate functions of PORT
- 120 7.2.1 Alternate functions of PORT
- 122 7.3.1 Alternate functions of port
- 126 7.4.1 Alternate functions of Port
- 131 7.5.1 Alternate functions of Port
- 135 7.6.1 Alternate functions of port
- 137 7.7.1 Alternate functions of Port
- 142 7.8.1 Alternate functions of Port
- 144 8 DEDICATED PINS
- 146 9 EXTERNAL BUS INTERFACE
- 147 SINGLE CHIP MODE
- 147 EXTERNAL BUS MODES
- 148 9.2.1 Multiplexed bus modes
- 149 9.2.2 Demultiplexed bus modes
- 150 9.2.3 Switching between bus modes
- 152 9.2.4 External data bus width
- 153 9.2.5 Disable/enable control for pin BHE (BYTDIS)
- 153 9.2.6 Segment address generation
- 154 9.2.7 CS signal generation
- 155 9.2.8 Segment address versus chip select
- 156 PROGRAMMABLE BUS CHARACTERISTICS
- 157 9.3.1 ALE length control
- 158 9.3.2 Programmable memory cycle time
- 159 9.3.3 Programmable memory tri-state time
- 160 9.3.4 Read/write delay time
- 163 9.3.6 Programmable chip select timing control
- 164 CONTROLLING THE EXTERNAL BUS CONTROLLER
- 165 9.4.1 Registers
- 170 9.4.2 Defining address areas
- 170 9.4.3 Prioritizing address areas
- 173 9.4.4 Precautions and hints
- 173 EBC IDLE STATE
- 173 EXTERNAL BUS ARBITRATION
- 174 9.6.1 Entering the hold state
- 175 9.6.2 Exiting the hold state
- 176 THE XBUS INTERFACE
- 178 10 PWM MODULE
- 179 10.1 OPERATING MODES
- 180 10.1.1Mode 0 - standard PWM generation (edge aligned PWM)
- 182 10.1.2Mode 1 - symmetrical PWM generation (center aligned)
- 183 10.1.3Single shot mode
- 186 10.2 PWM MODULE REGISTERS
- 186 10.2.1Up/down counter PT
- 186 10.2.2Period register PP
- 187 10.2.3Pulse width register PW
- 187 10.2.4PWM control register PWMCON
- 188 10.2.5PWM control register PWMCON
- 189 10.3 INTERRUPT REQUEST GENERATION
- 190 10.4 PWM OUTPUT SIGNALS
- 191 11 GENERAL PURPOSE TIMER UNITS
- 191 11.1 TIMER BLOCK GPT
- 193 11.1.1GPT1 core timer T
- 202 11.1.2GPT1 auxiliary timers T2 and T
- 209 11.1.3Interrupt control for GPT1 timers
- 211 11.2 TIMER BLOCK GPT
- 212 11.2.1GPT2 core timer T
- 218 11.2.2GPT2 Auxiliary Timer T
- 226 11.2.3Interrupt control for GPT2 timers and CAPREL
- 227 12 ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
- 232 12.2 SYNCHRONOUS OPERATION
- 234 12.3 HARDWARE ERROR DETECTION CAPABILITIES
- 235 12.4 ASC0 BAUD RATE GENERATION
- 235 12.4.1Asynchronous mode baud rates
- 236 12.4.2Synchronous mode baud rates
- 236 12.5 ASC0 INTERRUPT CONTROL
- 237 12.6 USING THE ASC0 INTERRUPTS
- 239 13 SYNCHRONOUS SERIAL PORT
- 240 13.1 XBUS IMPLEMENTATION
- 240 13.2 SSP REGISTERS
- 241 13.2.1SSP control register 0 - SSPCON
- 243 13.2.2SSP Control Register 1 - SSPCON
- 244 13.2.3SSP transmit buffer registers - SSPTBx
- 245 13.2.4Initialization
- 245 13.2.5Starting a transfer
- 246 13.2.6Performing a Write Operation
- 248 13.2.7Chip enable lines
- 249 13.2.8Using the SSP chip enable and clock lines for output functions
- 249 13.2.9Continuous transfer modes
- 251 13.2.10Interrupt control for the SSP
- 252 13.2.11SSP input/output pins
- 252 13.2.12Accessing the on-chip SSP
- 254 13.2.13Visibility of accesses to the SSP
- 254 13.2.14Single chip mode
- 254 13.2.15External bus mode
- 255 13.2.16Accessing the SSP in hold mode
- 255 13.2.17Power down mode
- 256 14 WATCHDOG TIMER
- 257 14.1 WATCHDOG TIMER OPERATION
- 259 15 SYSTEM RESET
- 260 15.1 ASYNCHRONOUS HARDWARE RESET
- 262 15.2 SYNCHRONOUS HARDWARE RESET (WARM RESET)
- 267 15.3 SOFTWARE RESET
- 267 15.4 WATCHDOG TIMER RESET
- 268 15.5 PINS AFTER RESET
- 269 15.5.1RESET input pin
- 270 15.5.2RESET output pin
- 270 15.6 WATCHDOG TIMER OPERATION AFTER RESET
- 271 15.8 INTERNAL RAM AFTER RESET
- 272 15.10APPLICATION SPECIFIC INITIALIZATION ROUTINE
- 273 15.10.1System start-up configuration
- 274 15.10.2Emulation mode
- 275 15.10.3Adapt mode
- 275 15.10.4System clock configuration
- 275 15.10.5External bus type
- 276 15.10.6Chip select lines
- 276 15.10.7Segment address lines
- 276 15.10.8BHE pin configuration
- 277 16 REGISTER SET
- 277 16.1 REGISTER DESCRIPTION FORMAT
- 278 16.2 GENERAL PURPOSE REGISTERS (GPRS)
- 280 16.3 SPECIAL FUNCTION REGISTERS ORDERED BY NAME
- 285 16.4 SPECIAL FUNCTION REGISTERS ORDERED BY ADDRESS
- 291 16.5 IDENTIFICATION REGISTERS
- 294 17 POWER REDUCTION MODES
- 294 17.1 IDLE MODE
- 296 17.2 POWER DOWN MODE
- 296 17.2.1Protected power down mode
- 297 17.2.2Interruptible power down mode
- 298 17.2.3Exiting interruptible power down mode
- 301 17.2.4Selecting R and C values
- 304 18 SYSTEM PROGRAMMING
- 304 18.1 INSTRUCTIONS PROVIDED AS SUBSETS OF INSTRUCTIONS
- 304 18.2 BCD CALCULATIONS
- 305 18.3 STACK OPERATIONS
- 305 18.3.1Internal system stack
- 306 18.3.2Circular (virtual) Stack
- 309 18.3.3Linear stack
- 309 18.3.4User stacks
- 309 18.4 REGISTER BANKING
- 310 18.5 CALL PROCEDURE ENTRY-AND-EXIT
- 310 18.5.1Passing parameters on the system stack
- 310 18.5.2Cross segment subroutine calls
- 311 18.5.3Providing local registers for subroutines
- 312 18.6 TABLE SEARCHING
- 313 18.7 PERIPHERAL CONTROL AND INTERFACE
- 313 18.8 FLOATING POINT SUPPORT
- 314 18.9 TRAP/INTERRUPT ENTRY AND EXIT
- 314 18.10INSEPARABLE INSTRUCTION SEQUENCES
- 314 18.11OVERRIDING THE DPP ADDRESSING MECHANISM
- 315 18.12SHORT ADDRESSING IN THE EXTENDED SFR (ESFR) SPACE
- 317 19 INDEX OF REGISTERS
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