STMicroelectronics STM32H7A3AI
Manuals and User Guides for STMicroelectronics STM32H7A3AI. We found 6 manuals for free downloads Reference manual, Data Sheet, Programming Manual, User manual
Below you will find brief information for STM32H7A3/7B3 and STM32H7B0. This reference manual provides complete information on how to use the STM32H7A3/7B3 and STM32H7B0 microcontroller memory and peripherals. These microcontrollers offer different memory sizes, packages, and peripherals, incorporating advanced ST patented technology.
Key Features
Advanced Arm-based 32-bit MCUs
Different memory sizes and packages
Advanced ST patented technology
Pages: 2973 STMicroelectronics STM32H7A3AI Reference manual
Brand: STMicroelectronics Category: Processors Size: 57 MB
Languages: English
Table of contents
- 98 Documentation conventions
- 98 General information
- 98 List of abbreviations for registers
- 99 Glossary
- 99 Availability of peripherals
- 99 Availability of security features
- 100 Memory and bus architecture
- 100 System architecture
- 103 Bus matrices
- 103 TCM buses
- 103 Bus-to-bus bridges
- 104 Domain and inter-domain buses
- 104 CPU buses
- 105 Bus master peripherals
- 106 Clocks to functional blocks
- 106 AXI interconnect matrix (AXIM)
- 106 AXI introduction
- 106 AXI interconnect main features
- 107 AXI interconnect functional description
- 109 AXI interconnect registers
- 118 AXI interconnect register map
- 129 Memory organization
- 129 Introduction
- 130 Memory map and register boundary addresses
- 136 Embedded SRAM
- 137 Flash memory overview
- 137 Boot configuration
- 139 RAM ECC monitoring (RAMECC)
- 139 Introduction
- 139 RAMECC main features
- 139 RAMECC functional description
- 139 RAMECC block diagram
- 141 RAMECC internal signals
- 141 RAMECC monitor mapping
- 142 RAMECC registers
- 142 RAMECC interrupt enable register (RAMECC_IER)
- 143 RAMECC monitor x configuration register (RAMECC_MxCR)
- 143 RAMECC monitor x status register (RAMECC_MxSR)
- 144 RAMECC monitor x failing address register (RAMECC_MxFAR)
- 144 RAMECC monitor x failing data low register (RAMECC_MxFDRL)
- 145 RAMECC monitor x failing data high register (RAMECC_MxFDRH)
- 145 RAMECC_MxFECR)
- 146 RAMECC register map
- 147 Embedded Flash memory (FLASH)
- 147 Introduction
- 147 FLASH main features
- 148 FLASH functional description
- 148 FLASH block diagram
- 149 FLASH internal signals
- 149 FLASH architecture and integration in the system
- 151 Flash memory architecture and usage
- 156 FLASH system performance enhancements
- 156 FLASH data protection schemes
- 157 Overview of FLASH operations
- 158 FLASH read operations
- 162 FLASH program operations
- 166 FLASH erase operations
- 169 FLASH parallel operations
- 169 Flash memory error protections
- 171 FLASH one-time programmable area
- 172 FLASH read-only area
- 173 Flash bank and register swapping (STM32H7A3/7B3 only)
- 177 FLASH reset and clocks
- 177 FLASH option bytes
- 177 About option bytes
- 178 Option byte loading
- 178 Option byte modification
- 180 Option bytes overview
- 184 Description of user and system option bytes
- 185 Description of data protection option bytes
- 186 Description of boot address option bytes
- 186 FLASH protection mechanisms
- 186 FLASH configuration protection
- 188 Write protection
- 189 Readout protection (RDP)
- 193 Proprietary code readout protection (PCROP)
- 194 Secure access mode (STM32H7B0 and STM32H7B3 only)
- 196 FLASH low-power modes
- 196 Introduction
- 196 Managing the FLASH domain switching to DStop or Standby
- 197 FLASH error management
- 197 Introduction
- 197 Write protection error (WRPERR)
- 198 Programming sequence error (PGSERR)
- 199 Strobe error (STRBERR)
- 199 Inconsistency error (INCERR)
- 200 Error correction code error (SNECCERR/DBECCERR)
- 200 Read protection error (RDPERR)
- 201 Read secure error (RDSERR)
- 201 CRC read error (CRCRDERR)
- 202 Option byte change error (OPTCHANGEERR)
- 202 Miscellaneous HardFault errors
- 202 FLASH interrupts
- 205 FLASH registers
- 205 FLASH access control register (FLASH_ACR)
- 205 FLASH key register for bank 1 (FLASH_KEYR1)
- 206 FLASH option key register (FLASH_OPTKEYR)
- 206 FLASH control register for bank 1 (FLASH_CR1)
- 210 FLASH status register for bank 1 (FLASH_SR1)
- 213 FLASH clear control register for bank 1 (FLASH_CCR1)
- 214 FLASH option control register (FLASH_OPTCR)
- 215 FLASH option status register (FLASH_OPTSR_CUR)
- 218 FLASH option status register (FLASH_OPTSR_PRG)
- 220 FLASH option clear control register (FLASH_OPTCCR)
- 221 FLASH protection address for bank 1 (FLASH_PRAR_CUR1)
- 221 FLASH protection address for bank 1 (FLASH_PRAR_PRG1)
- 222 FLASH secure address for bank 1 (FLASH_SCAR_CUR1)
- 223 FLASH secure address for bank 1 (FLASH_SCAR_PRG1)
- 223 (FLASH_WPSGN_CUR1R)
- 224 (FLASH_WPSGN_PRG1R)
- 225 FLASH register boot address (FLASH_BOOT_CURR)
- 225 FLASH register boot address FLASH_BOOT_PRGR)
- 226 FLASH CRC control register for bank 1 (FLASH_CRCCR1)
- 227 (FLASH_CRCSADD1R)
- 228 (FLASH_CRCEADD1R)
- 228 FLASH CRC data register (FLASH_CRCDATAR)
- 229 FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R)
- 229 FLASH OTP block lock (FLASH_OTPBL_CUR)
- 230 FLASH OTP block lock (FLASH_OTPBL_PRG)
- 230 FLASH key register for bank 2 (FLASH_KEYR2)
- 231 FLASH control register for bank 2 (FLASH_CR2)
- 235 FLASH status register for bank 2 (FLASH_SR2)
- 238 FLASH clear control register for bank 2 (FLASH_CCR2)
- 239 FLASH protection address for bank 2 (FLASH_PRAR_CUR2)
- 239 FLASH protection address for bank 2 (FLASH_PRAR_PRG2)
- 240 FLASH secure address for bank 2 (FLASH_SCAR_CUR2)
- 241 FLASH secure address for bank 2 (FLASH_SCAR_PRG2)
- 242 (FLASH_WPSGN_CUR2R)
- 242 (FLASH_WPSGN_PRG2R)
- 243 FLASH CRC control register for bank 2 (FLASH_CRCCR2)
- 244 (FLASH_CRCSADD2R)
- 245 (FLASH_CRCEADD2R)
- 245 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R)
- 246 FLASH register map and reset values
- 252 Secure memory management (SMM)
- 252 Introduction
- 252 Glossary
- 253 Secure access mode
- 254 Associated features
- 254 Boot state machine
- 255 Secure access mode configuration
- 255 Root secure services (RSS)
- 256 Secure area setting service
- 257 Secure area exiting service
- 257 OTFDEC encryption service
- 257 Secure user software
- 257 Access rules
- 258 Setting secure user memory areas
- 259 Summary of Flash protection mechanisms
- 260 Power control (PWR)
- 260 Introduction
- 260 PWR main features
- 261 PWR block diagram
- 263 Power supplies
- 269 System supply startup
- 273 Core domain
- 273 Voltage regulators
- 275 PWR external supply
- 275 Backup domain
- 277 VBAT battery charging
- 277 Analog supply
- 278 USB regulator
- 279 Power supply supervision
- 279 Power-on reset (POR)/power-down reset (PDR)
- 280 Brownout reset (BOR)
- 281 Programmable voltage detector (PVD)
- 282 Analog voltage detector (AVD)
- 283 Battery voltage thresholds
- 284 Temperature thresholds
- 284 maximum voltage level detector
- 285 Power management
- 287 System operating modes
- 290 Voltage scaling
- 291 Power control modes
- 293 Power management examples
- 301 Low-power modes
- 301 Slowing down system clocks
- 301 Controlling peripheral clocks
- 301 Entering low-power modes
- 302 Exiting from low-power modes
- 303 System Run and CSleep modes
- 303 System Autonomous mode
- 305 Stop mode
- 308 Standby mode
- 310 Monitoring low-power modes
- 311 PWR registers
- 311 PWR control register 1 (PWR_CR1)
- 313 PWR control status register 1 (PWR_CSR1)
- 315 PWR control register 2 (PWR_CR2)
- 316 PWR control register 3 (PWR_CR3)
- 318 PWR CPU control register (PWR_CPUCR)
- 319 PWR SmartRun domain control register (PWR_SRDCR)
- 320 PWR wakeup clear register (PWR_WKUPCR)
- 320 PWR wakeup flag register (PWR_WKUPFR)
- 321 PWR wakeup enable and polarity register (PWR_WKUPEPR)
- 322 PWR register map
- 323 Low-power SRD domain application example
- 323 Introduction
- 323 EXTI, RCC and PWR interconnections
- 325 Interrupts and wakeup
- 325 Block interactions
- 326 Role of DMAMUX2 in SRD domain
- 327 LPUART1 transmission
- 327 Memory retention
- 327 Memory-to-peripheral transfer using LPUART1 interface
- 332 LPUART1 transmission
- 333 Alternate implementations
- 334 Other low-power applications
- 335 Reset and clock control (RCC)
- 335 RCC main features
- 336 RCC block diagram
- 336 RCC pins and internal signals
- 338 RCC reset block functional description
- 338 Power-on/off reset
- 339 System reset
- 340 Local resets
- 340 Reset source identification
- 341 Low-power mode security reset (lpwr_rst)
- 342 Backup domain reset
- 342 Power-on and wakeup sequences
- 345 RCC clock block functional description
- 347 Clock naming convention
- 347 Oscillators description
- 353 Clock security system (CSS)
- 354 Clock output generation (MCO1/MCO2)
- 354 PLL description
- 361 Handling clock generators in Stop and Standby modes
- 362 Kernel clock selection
- 374 General clock concept overview
- 378 Peripheral allocation
- 379 Peripheral clock gating control
- 384 CPU and bus matrix clock gating control
- 385 RCC interrupts
- 386 RCC registers
- 386 RCC source control register (RCC_CR)
- 390 RCC HSI calibration register (RCC_HSICFGR)
- 390 RCC clock recovery RC register (RCC_CRRCR)
- 391 RCC CSI calibration register (RCC_CSICFGR)
- 392 RCC clock configuration register (RCC_CFGR)
- 394 RCC CPU domain clock configuration register 1 (RCC_CDCFGR1)
- 396 RCC CPU domain clock configuration register 2 (RCC_CDCFGR2)
- 396 (RCC_SRDCFGR)
- 397 RCC PLLs clock source selection register (RCC_PLLCKSELR)
- 399 RCC PLLs configuration register (RCC_PLLCFGR)
- 401 RCC PLL1 dividers configuration register (RCC_PLL1DIVR)
- 403 RCC PLL1 fractional divider register (RCC_PLL1FRACR)
- 403 RCC PLL2 dividers configuration register (RCC_PLL2DIVR)
- 405 RCC PLL2 fractional divider register (RCC_PLL2FRACR)
- 405 RCC PLL3 dividers configuration register (RCC_PLL3DIVR)
- 407 RCC PLL3 fractional divider register (RCC_PLL3FRACR)
- 407 (RCC_CDCCIPR)
- 408 (RCC_CDCCIP1R)
- 411 (RCC_CDCCIP2R)
- 413 (RCC_SRDCCIPR)
- 415 RCC clock source interrupt enable register (RCC_CIER)
- 416 RCC clock source interrupt flag register (RCC_CIFR)
- 418 RCC clock source interrupt clear register (RCC_CICR)
- 420 RCC Backup domain control register (RCC_BDCR)
- 422 RCC clock control and status register (RCC_CSR)
- 422 RCC AHB3 reset register (RCC_AHB3RSTR)
- 424 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 425 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 426 RCC AHB4 peripheral reset register (RCC_AHB4RSTR)
- 428 RCC APB3 peripheral reset register (RCC_APB3RSTR)
- 428 RCC APB1 peripheral reset register (RCC_APB1LRSTR)
- 431 RCC APB1 peripheral reset register (RCC_APB1HRSTR)
- 432 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 434 RCC APB4 peripheral reset register (RCC_APB4RSTR)
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Frequently Answers and Questions
What does this reference manual target?
This reference manual targets application developers.
What information does this manual provide?
It provides complete information on how to use the STM32H7A3/7B3 and STM32H7B0 microcontroller memory and peripherals.
What are the STM32H7A3/7B3 and STM32H7B0?
They are microcontrollers with different memory sizes, packages and peripherals.
Questions & Answers
S S M
Is the random number generated using the device's hardware a true random number or a pseudo-random number?
The device includes an integrated analog circuit that functions as a true random number generator (RNG), providing 32-bit random numbers with full entropy outputs. Therefore, any random number created using the device's RNG peripheral would be a true random number.
T T M
Does the STM32H7A3xI/G device utilize a True Random Number Generator (RNG)?
Yes, the STM32H7A3xI/G devices embed a True Random Number Generator (RNG). It uses an integrated analog circuit to generate 32-bit random numbers, providing full entropy outputs to the application.
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