Silicon Laboratories SI5316
Manuals and User Guides for Silicon Laboratories SI5316. We found 1 manuals for free downloads Reference manual
Silicon Laboratories C8051F344 Two
Brand: Silicon Laboratories Category: Wall clocks Size: 2 MB Pages: 180
Languages: English
Table of contents
- 12 1. Any-Frequency Precision Clock Product Family Overview
- 16 2. Narrowband vs. Wideband Overview
- 17 3. Any-Frequency Clock Family Members
- 17 3.1. Si
- 18 3.2. Si
- 19 3.3. Si
- 20 3.4. Si
- 21 3.5. Si
- 22 3.6. Si
- 23 3.7. Si
- 24 3.8. Si
- 25 3.9. Si
- 26 3.10. Si
- 27 3.11. Si
- 28 3.12. Si
- 29 3.13. Si
- 29 3.14. Si5374/75 Compared to Si
- 30 3.15. Si
- 31 3.16. Si
- 32 4. Device Specifications
- 46 5. DSPLL (All Devices)
- 47 5.1. Clock Multiplication
- 48 5.2. PLL Performance
- 48 5.2.1. Jitter Generation
- 48 5.2.2. Jitter Transfer
- 49 5.2.3. Jitter Tolerance
- 50 6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
- 50 6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)
- 50 6.1.1. Clock Multiplication (Si5316)
- 52 6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366)
- 64 6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366)
- 64 6.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366)
- 64 6.1.5. Jitter Tolerance (Si5316, Si5323, Si5366)
- 64 6.1.6. Narrowband Performance (Si5316, Si5323, Si5366)
- 64 6.1.7. Input-to-Output Skew (Si5316, Si5323, Si5366)
- 64 6.1.8. Wideband Performance (Si5322 and Si5365)
- 64 6.1.9. Lock Detect (Si5322 and Si5365)
- 64 6.1.10. Input-to-Output Skew (Si5322 and Si5365)
- 65 6.2. PLL Self-Calibration
- 65 (Si5316, Si5322, Si5323, Si5365, Si5366)
- 65 6.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366)
- 67 6.3. Pin Control Input Clock Control
- 67 6.3.1. Manual Clock Selection
- 68 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)
- 69 6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366)
- 70 6.4. Digital Hold/VCO Freeze
- 70 6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366)
- 70 6.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366)
- 70 6.4.3. Wideband VCO Freeze (Si5322, Si5365)
- 70 6.5. Frame Synchronization (Si5366)
- 71 6.6. Output Phase Adjust (Si5323, Si5366)
- 71 6.6.1. FSYNC Realignment (Si5366)
- 71 6.6.2. Including FSYNC Inputs in Clock Selection (Si5366)
- 71 6.6.3. FS_OUT Polarity and Pulse Width Control (Si5366)
- 71 6.6.4. Using FS_OUT as a Fifth Output Clock (Si5366)
- 72 6.6.5. Disabling FS_OUT (Si5366)
- 72 6.7. Output Clock Drivers
- 72 6.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366)
- 73 6.8. PLL Bypass Mode
- 73 6.9. Alarms
- 73 6.9.1. Loss-of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366)
- 73 6.9.2. FOS Alarms (Si5365 and Si5366)
- 74 6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L)
- 74 6.9.4. C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323)
- 74 6.9.5. C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366)
- 75 6.10. Device Reset
- 75 6.11. DSPLLsim Configuration Software
- 76 Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 76 7.1. Clock Multiplication
- 76 Si5369, Si5374 and Si5375)
- 76 7.1.2. Wideband Parts (Si5325, Si5367)
- 77 Si5368, Si5369, Si5374, Si5375)
- 79 7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368, Si5375)
- 79 7.1.5. Lock Detect (Si5319, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 79 7.2. PLL Self-Calibration
- 79 7.2.1. Initiating Internal Self-Calibration
- 80 7.2.2. Input Clock Stability during Internal Self-Calibration
- 80 7.2.3. Self-Calibration Caused by Changes in Input Frequency
- 80 Si5368, Si5369, Si5374, Si5375)
- 80 7.2.5. Clock Output Behavior Before and During ICAL
- 81 7.3. Input Clock Configurations (Si5367 and Si5368)
- 81 7.4. Input Clock Control
- 82 Si5368, Si5369, Si5374)
- 85 and Si5375 Free Run Mode
- 85 7.5.1. Free Run Mode Programming Procedure
- 85 7.5.2. Clock Control Logic in Free Run Mode
- 86 7.5.3. Free Run Reference Frequency Constraints
- 86 7.5.4. Free Run Reference Frequency Constraints
- 87 7.6. Digital Hold
- 87 7.6.1. Narrowband Digital Hold (Si5316, Si5324, Si5326, Si5368, Si5369, Si5374)
- 89 7.6.2. History Settings for Low Bandwidth Devices (Si5324, Si5327, Si5369, Si5374)
- 89 7.6.3. Recovery from Digital Hold (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)
- 89 7.6.4. VCO Freeze (Si5319, Si5325, Si5367, Si5375)
- 89 7.6.5. Digital Hold versus VCO Freeze
- 90 7.7. Output Phase Adjust (Si5326, Si5368)
- 90 7.7.1. Coarse Skew Control (Si5326, Si5368)
- 90 7.7.2. Fine Skew Control (Si5326, Si5368)
- 91 7.7.3. Independent Skew (Si5324, Si5326, Si5368, Si5369, Si5374)
- 91 7.7.4. Output-to-output Skew (Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)
- 91 7.7.5. Input-to-Output Skew (All Devices)
- 91 7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)
- 93 7.8.1. FSYNC Realignment (Si5368)
- 94 7.8.2. FSYNC Skew Control (Si5368)
- 94 7.8.3. Including FSYNC Inputs in Clock Selection (Si5368)
- 94 7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)
- 94 7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368)
- 95 Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 95 7.9.1. Disabling CKOUTn
- 95 7.9.2. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)
- 96 Si5367, Si5368, Si5369, Si5374, Si5375)
- 96 Si5368, Si5369, Si5374, Si5375)
- 96 Si5367, Si5368, Si5369, Si5374, Si5375)
- 97 7.11.2. FOS Algorithm (Si5324, Si5325, Si5326, Si5368, Si5369, Si5374)
- 99 7.11.3. C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5374, Si5375)
- 99 7.11.4. LOS (Si5319, Si5375)
- 99 7.11.5. C1B, C2B, C3B, ALRMOUT (Si5367, Si5368, Si5369 [CK_CONFIG_REG = 0])
- 100 7.11.6. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1])
- 100 Si5327, Si5368, Si5369, Si5374, Si5375)
- 100 7.11.8. LOL (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 101 7.11.9. Device Interrupts
- 101 7.12. Device Reset
- 102 C Serial Microprocessor Interface
- 103 7.14. Serial Microprocessor Interface (SPI)
- 104 7.14.1. Default Device Configuration
- 104 7.15. Register Descriptions
- 104 7.16. DSPLLsim Configuration Software
- 105 8. High-Speed I/O
- 105 8.1. Input Clock Buffers
- 107 8.2. Output Clock Drivers
- 107 8.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)
- 107 8.2.2. Typical Output Circuits
- 109 8.2.3. Typical Clock Output Scope Shots
- 110 8.3. Typical Scope Shots for SFOUT Options
- 113 Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, and Si5375)
- 115 8.5. Three-Level (3L) Input Pins (No External Resistors)
- 116 8.6. Three-Level (3L) Input Pins (With External Resistors)
- 117 9. Power Supply
- 118 10. Packages and Ordering Guide
- 119 Appendix A—Narrowband References
- 121 Si5374, Si5375)
- 126 Appendix C—Typical Phase Noise Plots
- 144 Appendix D—Alarm Structure
- 147 Appendix E—Internal Pullup, Pulldown by Pin
- 154 Output Format Jitter
- 162 Appendix G—Near Integer Ratios
- 164 Appendix H—Jitter Attenuation and Loop BW
- 169 Appendix I—Si5374 and Si5375 PCB Layout Recommendations
- 173 Appendix J—Si5374 and Si5375 Crosstalk
- 178 Document Change List
- 180 Contact Information