ST STM32G030K6
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ST STM32G0x0 advanced Arm®-based 32-bit MCUs are designed for embedded applications that demand high performance, low power consumption, and advanced features. These MCUs are based on the Arm® Cortex®-M0+ core and offer a wide range of memory options, peripherals, and connectivity options. With their combination of performance, efficiency, and versatility, ST STM32G0x0 MCUs are ideal for a variety of applications, including industrial automation, medical devices, consumer electronics, and more.
Key Features
Based on the Arm® Cortex®-M0+ core
High performance and low power consumption
Extensive selection of memory options including Flash and SRAM
Rich set of peripherals for connectivity, sensing, and control
Advanced security features for protecting data and code
Pages: 989 ST STM32G030K6 Reference manual
Brand: ST Category: Electrical equipment & supplies Size: 12 MB
Languages: English
Table of contents
- 39 Documentation conventions
- 39 General information
- 39 List of abbreviations for registers
- 40 Glossary
- 40 Availability of peripherals
- 42 Memory and bus architecture
- 42 System architecture
- 44 Memory organization
- 44 Introduction
- 45 Memory map and register boundary addresses
- 49 Embedded SRAM
- 50 Flash memory overview
- 51 Boot configuration
- 53 Embedded Flash memory (FLASH)
- 53 FLASH Introduction
- 53 FLASH main features
- 53 FLASH functional description
- 53 FLASH memory organization
- 55 FLASH empty check
- 55 FLASH error code correction (ECC)
- 56 FLASH read access latency
- 57 FLASH memory acceleration
- 58 FLASH program and erase operations
- 59 FLASH Main memory programming sequences
- 62 Read-while-write (RWW) function
- 63 FLASH option bytes
- 63 FLASH option byte description
- 68 FLASH option byte programming
- 69 FLASH memory protection
- 69 FLASH read protection (RDP)
- 72 FLASH write protection (WRP)
- 73 FLASH interrupts
- 74 FLASH registers
- 74 FLASH access control register (FLASH_ACR)
- 75 FLASH key register (FLASH_KEYR)
- 75 FLASH option key register (FLASH_OPTKEYR)
- 75 FLASH status register (FLASH_SR)
- 77 FLASH control register (FLASH_CR)
- 79 FLASH ECC register (FLASH_ECCR)
- 80 FLASH ECC register 2 (FLASH_ECCR2)
- 80 FLASH option register (FLASH_OPTR)
- 82 FLASH WRP area A address register (FLASH_WRP1AR)
- 82 FLASH WRP area B address register (FLASH_WRP1BR)
- 83 FLASH WRP2 area A address register (FLASH_WRP2AR)
- 84 FLASH WRP2 area B address register (FLASH_WRP2BR)
- 85 FLASH register map
- 86 Power control (PWR)
- 86 Power supplies
- 87 ADC reference voltage
- 87 Battery backup of RTC domain
- 89 Voltage regulator
- 89 Dynamic voltage scaling management
- 90 Power supply supervisor
- 90 Power-on reset (POR) / power-down reset (PDR)
- 91 Low-power modes
- 95 Run mode
- 95 Low-power run mode (LP run)
- 96 Low-power modes
- 97 Sleep mode
- 98 Low-power sleep mode (LP sleep)
- 99 Stop 0 mode
- 101 Stop 1 mode
- 102 Standby mode
- 103 Auto-wakeup from low-power mode
- 104 PWR registers
- 104 Power control register 1 (PWR_CR1)
- 105 Power control register 2 (PWR_CR2)
- 106 Power control register 3 (PWR_CR3)
- 107 Power control register 4 (PWR_CR4)
- 108 Power status register 1 (PWR_SR1)
- 109 Power status register 2 (PWR_SR2)
- 110 Power status clear register (PWR_SCR)
- 111 Power Port A pull-up control register (PWR_PUCRA)
- 111 Power Port A pull-down control register (PWR_PDCRA)
- 112 Power Port B pull-up control register (PWR_PUCRB)
- 112 Power Port B pull-down control register (PWR_PDCRB)
- 113 Power Port C pull-up control register (PWR_PUCRC)
- 113 Power Port C pull-down control register (PWR_PDCRC)
- 114 Power Port D pull-up control register (PWR_PUCRD)
- 114 Power Port D pull-down control register (PWR_PDCRD)
- 115 Power Port E pull-up control register (PWR_PUCRE)
- 115 Power Port E pull-down control register (PWR_PDCRE)
- 115 Power Port F pull-up control register (PWR_PUCRF)
- 116 Power Port F pull-down control register (PWR_PDCRF)
- 117 PWR register map
- 119 Reset and clock control (RCC)
- 119 Reset
- 119 Power reset
- 119 System reset
- 121 RTC domain reset
- 121 Clocks
- 125 HSE clock
- 126 HSI16 clock
- 127 LSE clock
- 128 LSI clock
- 128 System clock (SYSCLK) selection
- 128 Clock source frequency versus voltage scaling
- 129 Clock security system (CSS)
- 129 Clock security system for LSE clock (LSECSS)
- 130 ADC clock
- 130 RTC clock
- 130 Timer clock
- 130 Watchdog clock
- 131 Clock-out capability
- 131 Internal/external clock measurement with TIM14/TIM16/TIM
- 134 Peripheral clock enable registers
- 134 Low-power modes
- 135 RCC registers
- 135 Clock control register (RCC_CR)
- 136 Internal clock source calibration register (RCC_ICSCR)
- 137 Clock configuration register (RCC_CFGR)
- 140 PLL configuration register (RCC_PLLCFGR)
- 143 Clock interrupt enable register (RCC_CIER)
- 143 Clock interrupt flag register (RCC_CIFR)
- 145 Clock interrupt clear register (RCC_CICR)
- 146 I/O port reset register (RCC_IOPRSTR)
- 147 AHB peripheral reset register (RCC_AHBRSTR)
- 148 APB peripheral reset register 1 (RCC_APBRSTR1)
- 150 APB peripheral reset register 2 (RCC_APBRSTR2)
- 151 I/O port clock enable register (RCC_IOPENR)
- 152 AHB peripheral clock enable register (RCC_AHBENR)
- 153 APB peripheral clock enable register 1 (RCC_APBENR1)
- 155 APB peripheral clock enable register 2(RCC_APBENR2)
- 157 I/O port in Sleep mode clock enable register (RCC_IOPSMENR)
- 158 (RCC_AHBSMENR)
- 159 (RCC_APBSMENR1)
- 161 (RCC_APBSMENR2)
- 164 (RCC_CCIPR2)
- 165 RTC domain control register (RCC_BDCR)
- 167 Control/status register (RCC_CSR)
- 169 RCC register map
- 173 General-purpose I/Os (GPIO)
- 173 Introduction
- 173 GPIO main features
- 173 GPIO functional description
- 175 General-purpose I/O (GPIO)
- 175 I/O pin alternate function multiplexer and mapping
- 176 I/O port control registers
- 176 I/O port data registers
- 177 I/O data bitwise handling
- 177 GPIO locking mechanism
- 177 I/O alternate function input/output
- 178 External interrupt/wakeup lines
- 178 Input configuration
- 179 Output configuration
- 179 Alternate function configuration
- 180 Analog configuration
- 181 Using the HSE or LSE oscillator pins as GPIOs
- 181 Using the GPIO pins in the RTC domain
- 182 GPIO registers
- 182 (x =A to F)
- 182 (x = A to F)
- 187 GPIO port bit reset register (GPIOx_BRR) (x = A to F)
- 188 GPIO register map
- 189 System configuration controller (SYSCFG)
- 189 SYSCFG registers
- 189 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 192 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 194 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)
- 194 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)
- 195 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)
- 195 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)
- 196 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)
- 196 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)
- 196 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)
- 197 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8)
- 197 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)
- 198 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)
- 198 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)
- 199 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)
- 199 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)
- 199 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)
- 200 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)
- 200 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)
- 200 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)
- 201 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)
- 201 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)
- 201 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)
- 202 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)
- 202 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)
- 202 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)
- 203 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)
- 203 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)
- 204 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)
- 204 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)
- 204 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)
- 205 SYSCFG register map
- 208 Interconnect matrix
- 208 Introduction
- 208 Connection summary
- 209 Interconnection details
- 209 to TIM1, TIM3, TIM4, and TIM
- 210 From TIM1, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC
- 210 From ADC to TIM
- 211 TIM16, and TIM
- 211 and TIM
- 212 From TIM16, TIM17, USART1, and USART4, to IRTIM
- 212 From TIM14 to DMAMUX
- 213 Direct memory access controller (DMA)
- 213 Introduction
- 213 DMA main features
- 214 DMA implementation
- 214 DMA request mapping
- 214 DMA functional description
- 214 DMA block diagram
- 215 DMA pins and internal signals
- 215 DMA transfers
- 216 DMA arbitration
- 217 DMA channels
- 220 DMA data width, alignment and endianness
- 222 DMA error management
- 222 DMA interrupts
- 222 DMA registers
- 223 DMA interrupt status register (DMA_ISR)
- 225 DMA interrupt flag clear register (DMA_IFCR)
- 226 DMA channel x configuration register (DMA_CCRx)
- 230 DMA channel x peripheral address register (DMA_CPARx)
- 230 DMA channel x memory address register (DMA_CMARx)
- 231 DMA register map
- 234 DMA request multiplexer (DMAMUX)
- 234 Introduction
- 235 DMAMUX main features
- 235 DMAMUX implementation
- 235 DMAMUX instantiation
- 235 DMAMUX mapping
- 238 DMAMUX functional description
- 238 DMAMUX block diagram
- 239 DMAMUX signals
- 239 DMAMUX channels
- 239 DMAMUX request line multiplexer
- 242 DMAMUX request generator
- 243 DMAMUX interrupts
- 244 DMAMUX registers
- 244 (DMAMUX_CxCR)
- 245 (DMAMUX_CSR)
- 245 (DMAMUX_CFR)
- 246 (DMAMUX_RGxCR)
- 247 (DMAMUX_RGSR)
- 247 (DMAMUX_RGCFR)
- 248 DMAMUX register map
- 250 Nested vectored interrupt controller (NVIC)
- 250 Main features
- 250 SysTick calibration value register
- 250 Interrupt and exception vectors
- 253 Extended interrupt and event controller (EXTI)
- 253 EXTI main features
- 253 EXTI block diagram
- 255 EXTI connections between peripherals and CPU
- 255 EXTI functional description
- 256 EXTI configurable event input wakeup
- 256 EXTI direct event input wakeup
- 257 EXTI mux
- 258 EXTI functional behavior
- 259 EXTI registers
- 259 EXTI rising trigger selection register (EXTI_RTSR1)
- 260 EXTI falling trigger selection register 1 (EXTI_FTSR1)
- 260 EXTI software interrupt event register 1 (EXTI_SWIER1)
- 261 EXTI rising edge pending register 1 (EXTI_RPR1)
- 261 EXTI falling edge pending register 1 (EXTI_FPR1)
- 262 EXTI external interrupt selection register (EXTI_EXTICRx)
- 263 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)
- 264 EXTI CPU wakeup with event mask register (EXTI_EMR1)
- 265 EXTI register map
- 267 Cyclic redundancy check calculation unit (CRC)
- 267 Introduction
- 267 CRC main features
- 268 CRC functional description
- 268 CRC block diagram
- 268 CRC internal signals
- 268 CRC operation
- 270 CRC registers
- 270 CRC data register (CRC_DR)
- 270 CRC independent data register (CRC_IDR)
- 271 CRC control register (CRC_CR)
- 272 CRC initial value (CRC_INIT)
- 272 CRC polynomial (CRC_POL)
- 273 CRC register map
- 274 Analog-to-digital converter (ADC)
- 274 Introduction
- 275 ADC main features
- 276 ADC functional description
- 276 ADC pins and internal signals
- 277 ADC voltage regulator (ADVREGEN)
- 278 Calibration (ADCAL)
- 279 ADC on-off control (ADEN, ADDIS, ADRDY)
- 281 ADC clock (CKMODE, PRESC[3:0])
- 283 ADC connectivity
- 284 Configuring the ADC
- 284 Channel selection (CHSEL, SCANDIR, CHSELRMOD)
- 285 Programmable sampling time (SMPx[2:0])
- 286 14.3.10 Single conversion mode (CONT = 0)
- 286 14.3.11 Continuous conversion mode (CONT = 1)
- 287 14.3.12 Starting conversions (ADSTART)
- 288 14.3.13 Timings
- 289 14.3.14 Stopping an ongoing conversion (ADSTP)
- 289 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)
- 290 Discontinuous mode (DISCEN)
- 290 Programmable resolution (RES) - Fast conversion mode
- 291 End of conversion, end of sampling phase (EOC, EOSMP flags)
- 291 End of conversion sequence (EOS flag)
- 292 hardware/software triggers)
- 294 Low frequency trigger mode
- 294 Data management
- 294 Data register and data alignment (ADC_DR, ALIGN)
- 294 ADC overrun (OVR, OVRMOD)
- 296 Managing a sequence of data converted without using the DMA
- 296 Managing converted data without using the DMA without overrun
- 296 Managing converted data using the DMA
- 297 Low-power features
- 297 Wait mode conversion
- 298 Auto-off mode (AUTOFF)
- 300 ADC_AWDxCR, ADC_AWDxTR)
- 300 Description of analog watchdog
- 301 Description of analog watchdog 2 and
- 301 ADC_AWDx_OUT output signal generation
- 303 Analog Watchdog threshold control
- 304 Oversampler
- 306 ADC operating modes supported when oversampling
- 306 Analog watchdog
- 306 Triggered mode
- 307 Temperature sensor and internal reference voltage
- 309 14.10 Battery voltage monitoring
- 310 14.11 ADC interrupts
- 312 14.12 ADC registers
- 312 14.12.1 ADC interrupt and status register (ADC_ISR)
- 314 14.12.2 ADC interrupt enable register (ADC_IER)
- 316 14.12.3 ADC control register (ADC_CR)
- 318 14.12.4 ADC configuration register 1 (ADC_CFGR1)
- 322 14.12.5 ADC configuration register 2 (ADC_CFGR2)
- 323 14.12.6 ADC sampling time register (ADC_SMPR)
- 324 14.12.7 ADC watchdog threshold register (ADC_AWD1TR)
- 325 14.12.8 ADC watchdog threshold register (ADC_AWD2TR)
- 326 14.12.9 ADC channel selection register [alternate] (ADC_CHSELR)
- 327 14.12.10 ADC channel selection register [alternate] (ADC_CHSELR)
- 329 14.12.11 ADC watchdog threshold register (ADC_AWD3TR)
- 329 14.12.12 ADC data register (ADC_DR)
- 330 14.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)
- 330 14.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)
- 331 14.12.15 ADC Calibration factor (ADC_CALFACT)
- 331 14.12.16 ADC common configuration register (ADC_CCR)
- 333 14.13 ADC register map
- 335 Advanced-control timer (TIM1)
- 335 TIM1 introduction
- 336 TIM1 main features
- 338 TIM1 functional description
- 338 Time-base unit
- 340 Counter modes
- 351 Repetition counter
- 353 External trigger input
- 354 Clock selection
- 358 Capture/compare channels
- 360 Input capture mode
- 361 PWM input mode
- 362 Forced output mode
- 363 15.3.10 Output compare mode
- 364 15.3.11 PWM mode
- 367 15.3.12 Asymmetric PWM mode
- 368 15.3.13 Combined PWM mode
- 369 15.3.14 Combined 3-phase PWM mode
- 370 15.3.15 Complementary outputs and dead-time insertion
- 372 15.3.16 Using the break function
- 378 15.3.17 Bidirectional break inputs
- 380 15.3.18 Clearing the OCxREF signal on an external event
- 381 15.3.19 6-step PWM generation
- 382 15.3.20 One-pulse mode
- 383 15.3.21 Retriggerable one pulse mode
- 384 15.3.22 Encoder interface mode
- 386 15.3.23 UIF bit remapping
- 387 15.3.24 Timer input XOR function
- 387 15.3.25 Interfacing with Hall sensors
- 390 15.3.26 Timer synchronization
- 394 15.3.27 ADC synchronization
- 394 15.3.28 DMA burst mode
- 395 15.3.29 Debug mode
- 396 TIM1 registers
- 396 TIM1 control register 1 (TIM1_CR1)
- 397 TIM1 control register 2 (TIM1_CR2)
- 400 TIM1 slave mode control register (TIM1_SMCR)
- 402 TIM1 DMA/interrupt enable register (TIM1_DIER)
- 404 TIM1 status register (TIM1_SR)
- 406 TIM1 event generation register (TIM1_EGR)
- 407 (TIM1_CCMR1)
- 411 (TIM1_CCMR2)
- 414 (TIM1_CCER)
- 417 15.4.12 TIM1 counter (TIM1_CNT)
- 417 15.4.13 TIM1 prescaler (TIM1_PSC)
- 417 15.4.14 TIM1 auto-reload register (TIM1_ARR)
- 418 15.4.15 TIM1 repetition counter register (TIM1_RCR)
- 418 15.4.16 TIM1 capture/compare register 1 (TIM1_CCR1)
- 419 15.4.17 TIM1 capture/compare register 2 (TIM1_CCR2)
- 419 15.4.18 TIM1 capture/compare register 3 (TIM1_CCR3)
- 420 15.4.19 TIM1 capture/compare register 4 (TIM1_CCR4)
- 420 (TIM1_BDTR)
- 424 15.4.21 TIM1 DMA control register (TIM1_DCR)
- 425 (TIM1_DMAR)
- 426 (TIM1_CCMR3)
- 427 15.4.24 TIM1 capture/compare register 5 (TIM1_CCR5)
- 428 15.4.25 TIM1 capture/compare register 6 (TIM1_CCR6)
- 428 15.4.26 TIM1 alternate function option register 1 (TIM1_AF1)
- 429 15.4.27 TIM1 Alternate function register 2 (TIM1_AF2)
- 430 15.4.28 TIM1 timer input selection register (TIM1_TISEL)
- 431 15.4.29 TIM1 register map
- 434 General-purpose timers (TIM3/TIM4)
- 434 TIM3/TIM4 introduction
- 434 TIM3/TIM4 main features
- 436 TIM3/TIM4 functional description
- 436 Time-base unit
- 438 Counter modes
- 448 Clock selection
- 452 Capture/Compare channels
- 454 Input capture mode
- 455 PWM input mode
- 456 Forced output mode
- 456 Output compare mode
- 457 PWM mode
- 461 16.3.10 Asymmetric PWM mode
- 461 16.3.11 Combined PWM mode
- 462 16.3.12 Clearing the OCxREF signal on an external event
- 464 16.3.13 One-pulse mode
- 465 16.3.14 Retriggerable one pulse mode
- 466 16.3.15 Encoder interface mode
- 468 16.3.16 UIF bit remapping
- 468 16.3.17 Timer input XOR function
- 469 16.3.18 Timers and external trigger synchronization
- 472 16.3.19 Timer synchronization
- 477 16.3.20 DMA burst mode
- 478 16.3.21 Debug mode
- 479 TIM3/TIM4 registers
- 479 TIMx control register 1 (TIMx_CR1)(x = 3 to 4)
- 480 TIMx control register 2 (TIMx_CR2)(x = 3 to 4)
- 482 TIMx slave mode control register (TIMx_SMCR)(x = 3 to 4)
- 485 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 3 to 4)
- 486 TIMx status register (TIMx_SR)(x = 3 to 4)
- 488 TIMx event generation register (TIMx_EGR)(x = 3 to 4)
- 489 (x = 3 to 4)
- 495 (TIMx_CCER)(x = 3 to 4)
- 496 16.4.12 TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4)
- 497 16.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4)
- 497 16.4.14 TIMx prescaler (TIMx_PSC)(x = 3 to 4)
- 498 16.4.15 TIMx auto-reload register (TIMx_ARR)(x = 3 to 4)
- 498 16.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 3 to 4)
- 499 16.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 3 to 4)
- 499 16.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 3 to 4)
- 500 16.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 3 to 4)
- 501 16.4.20 TIMx DMA control register (TIMx_DCR)(x = 3 to 4)
- 501 16.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 3 to 4)
- 502 16.4.22 TIM3 alternate function option register 1 (TIM3_AF1)
- 502 16.4.23 TIM4 alternate function option register 1 (TIM4_AF1)
- 502 16.4.24 TIM3 timer input selection register (TIM3_TISEL)
- 503 16.4.25 TIM4 timer input selection register (TIM4_TISEL)
- 505 16.4.26 TIMx register map
- 508 Basic timers (TIM6/TIM7)
- 508 TIM6/TIM7 introduction
- 508 TIM6/TIM7 main features
- 509 TIM6/TIM7 functional description
- 509 Time-base unit
- 511 Counting mode
- 514 UIF bit remapping
- 514 Clock source
- 515 Debug mode
- 515 TIM6/TIM7 registers
- 515 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)
- 517 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)
- 517 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)
- 518 TIMx status register (TIMx_SR)(x = 6 to 7)
- 518 TIMx event generation register (TIMx_EGR)(x = 6 to 7)
- 518 TIMx counter (TIMx_CNT)(x = 6 to 7)
- 519 TIMx prescaler (TIMx_PSC)(x = 6 to 7)
- 519 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)
- 520 TIMx register map
- 521 General-purpose timers (TIM14)
- 521 TIM14 introduction
- 521 TIM14 main features
- 523 TIM14 functional description
- 523 Time-base unit
- 525 Counter modes
- 528 Clock selection
- 529 Capture/compare channels
- 530 Input capture mode
- 531 Forced output mode
- 532 Output compare mode
- 533 PWM mode
- 534 One-pulse mode
- 534 18.3.10 UIF bit remapping
- 535 18.3.11 Using timer output as trigger for other timers (TIM14)
- 535 18.3.12 Debug mode
- 536 TIM14 registers
- 536 TIM14 control register 1 (TIM14_CR1)
- 537 TIM14 Interrupt enable register (TIM14_DIER)
- 537 TIM14 status register (TIM14_SR)
- 538 TIM14 event generation register (TIM14_EGR)
- 542 TIM14 capture/compare enable register (TIM14_CCER)
- 543 TIM14 counter (TIM14_CNT)
- 544 TIM14 prescaler (TIM14_PSC)
- 544 18.4.10 TIM14 auto-reload register (TIM14_ARR)
- 544 18.4.11 TIM14 capture/compare register 1 (TIM14_CCR1)
- 545 18.4.12 TIM14 timer input selection register (TIM14_TISEL)
- 545 18.4.13 TIM14 register map
- 547 General-purpose timers (TIM15/TIM16/TIM17)
- 547 TIM15/TIM16/TIM17 introduction
- 547 TIM15 main features
- 548 TIM16/TIM17 main features
- 551 TIM15/TIM16/TIM17 functional description
- 551 Time-base unit
- 553 Counter modes
- 557 Repetition counter
- 558 Clock selection
- 560 Capture/compare channels
- 562 Input capture mode
- 563 PWM input mode (only for TIM15)
- 564 Forced output mode
- 565 Output compare mode
- 566 19.4.10 PWM mode
- 567 19.4.11 Combined PWM mode (TIM15 only)
- 568 19.4.12 Complementary outputs and dead-time insertion
- 570 19.4.13 Using the break function
- 575 19.4.14 Bidirectional break inputs
- 577 19.4.15 One-pulse mode
- 579 19.4.16 Retriggerable one pulse mode (TIM15 only)
- 579 19.4.17 UIF bit remapping
- 581 19.4.18 Timer input XOR function (TIM15 only)
- 582 19.4.19 External trigger synchronization (TIM15 only)
- 584 19.4.20 Slave mode – combined reset + trigger mode
- 584 19.4.21 DMA burst mode
- 586 19.4.22 Timer synchronization (TIM15)
- 586 19.4.23 Using timer output as trigger for other timers (TIM16/TIM17)
- 586 19.4.24 Debug mode
- 587 TIM15 registers
- 587 TIM15 control register 1 (TIM15_CR1)
- 588 TIM15 control register 2 (TIM15_CR2)
- 590 TIM15 slave mode control register (TIM15_SMCR)
- 591 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 592 TIM15 status register (TIM15_SR)
- 594 TIM15 event generation register (TIM15_EGR)
- 595 (TIM15_CCMR1)
- 599 TIM15 capture/compare enable register (TIM15_CCER)
- 602 19.5.10 TIM15 counter (TIM15_CNT)
- 602 19.5.11 TIM15 prescaler (TIM15_PSC)
- 602 19.5.12 TIM15 auto-reload register (TIM15_ARR)
- 603 19.5.13 TIM15 repetition counter register (TIM15_RCR)
- 603 19.5.14 TIM15 capture/compare register 1 (TIM15_CCR1)
- 604 19.5.15 TIM15 capture/compare register 2 (TIM15_CCR2)
- 604 19.5.16 TIM15 break and dead-time register (TIM15_BDTR)
- 607 19.5.17 TIM15 DMA control register (TIM15_DCR)
- 607 19.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)
- 608 19.5.19 TIM15 alternate register 1 (TIM15_AF1)
- 608 19.5.20 TIM15 input selection register (TIM15_TISEL)
- 609 19.5.21 TIM15 register map
- 612 TIM16/TIM17 registers
- 612 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)
- 613 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)
- 614 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)
- 615 TIMx status register (TIMx_SR)(x = 16 to 17)
- 616 TIMx event generation register (TIMx_EGR)(x = 16 to 17)
- 617 (x = 16 to 17)
- 620 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)
- 622 TIMx counter (TIMx_CNT)(x = 16 to 17)
- 623 19.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)
- 623 19.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)
- 624 19.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)
- 624 19.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)
- 625 19.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)
- 628 19.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17)
- 628 19.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17)
- 629 19.6.17 TIM16 alternate function register 1 (TIM16_AF1)
- 629 19.6.18 TIM16 input selection register (TIM16_TISEL)
- 630 19.6.19 TIM17 alternate function register 1 (TIM17_AF1)
- 630 19.6.20 TIM17 input selection register (TIM17_TISEL)
- 632 19.6.21 TIM16/TIM17 register map
- 634 Infrared interface (IRTIM)
- 635 Independent watchdog (IWDG)
- 635 Introduction
- 635 IWDG main features
- 635 IWDG functional description
- 635 IWDG block diagram
- 636 Window option
- 637 Hardware watchdog
- 637 Register access protection
- 637 Debug mode
- 638 IWDG registers
- 638 IWDG key register (IWDG_KR)
- 639 IWDG prescaler register (IWDG_PR)
- 640 IWDG reload register (IWDG_RLR)
- 641 IWDG status register (IWDG_SR)
- 642 IWDG window register (IWDG_WINR)
- 643 IWDG register map
- 644 System window watchdog (WWDG)
- 644 Introduction
- 644 WWDG main features
- 644 WWDG functional description
- 645 WWDG block diagram
- 645 Enabling the watchdog
- 645 Controlling the down-counter
- 645 How to program the watchdog timeout
- 647 Debug mode
- 647 WWDG interrupts
- 647 WWDG registers
- 647 WWDG control register (WWDG_CR)
- 648 WWDG configuration register (WWDG_CFR)
- 649 WWDG status register (WWDG_SR)
- 649 WWDG register map
- 650 Real-time clock (RTC)
- 650 Introduction
- 650 RTC main features
- 651 RTC functional description
- 651 RTC block diagram
- 652 RTC pins and internal signals
- 653 GPIOs controlled by the RTC and TAMP
- 655 Clock and prescalers
- 656 Real-time clock and calendar
- 657 Programmable alarms
- 657 Periodic auto-wakeup
- 658 RTC initialization and configuration
- 660 Reading the calendar
- 661 23.3.10 Resetting the RTC
- 661 23.3.11 RTC synchronization
- 662 23.3.12 RTC reference clock detection
- 662 23.3.13 RTC smooth digital calibration
- 664 23.3.14 Timestamp function
- 665 23.3.15 Calibration clock output
- 665 23.3.16 Tamper and alarm output
- 666 RTC low-power modes
- 666 RTC interrupts
- 667 RTC registers
- 667 RTC time register (RTC_TR)
- 668 RTC date register (RTC_DR)
- 669 RTC sub second register (RTC_SSR)
- 669 RTC initialization control and status register (RTC_ICSR)
- 671 RTC prescaler register (RTC_PRER)
- 672 RTC wakeup timer register (RTC_WUTR)
- 672 RTC control register (RTC_CR)
- 675 RTC write protection register (RTC_WPR)
- 676 RTC calibration register (RTC_CALR)
- 677 23.6.10 RTC shift control register (RTC_SHIFTR)
- 678 23.6.11 RTC timestamp time register (RTC_TSTR)
- 678 23.6.12 RTC timestamp date register (RTC_TSDR)
- 679 23.6.13 RTC timestamp sub second register (RTC_TSSSR)
- 680 23.6.14 RTC alarm A register (RTC_ALRMAR)
- 681 23.6.15 RTC alarm A sub second register (RTC_ALRMASSR)
- 682 23.6.16 RTC alarm B register (RTC_ALRMBR)
- 683 23.6.17 RTC alarm B sub second register (RTC_ALRMBSSR)
- 683 23.6.18 RTC status register (RTC_SR)
- 684 23.6.19 RTC masked interrupt status register (RTC_MISR)
- 685 23.6.20 RTC status clear register (RTC_SCR)
- 687 23.6.21 RTC register map
- 689 Tamper and backup registers (TAMP)
- 689 Introduction
- 689 TAMP main features
- 690 TAMP functional description
- 690 TAMP block diagram
- 691 TAMP pins and internal signals
- 691 TAMP register write protection
- 692 Tamper detection
- 694 TAMP low-power modes
- 694 TAMP interrupts
- 694 TAMP registers
- 695 TAMP control register 1 (TAMP_CR1)
- 696 TAMP control register 2 (TAMP_CR2)
- 697 TAMP filter control register (TAMP_FLTCR)
- 698 TAMP interrupt enable register (TAMP_IER)
- 699 TAMP status register (TAMP_SR)
- 700 TAMP masked interrupt status register (TAMP_MISR)
- 701 TAMP status clear register (TAMP_SCR)
- 702 TAMP backup x register (TAMP_BKPxR)
- 703 TAMP register map
- 704 Inter-integrated circuit (I2C) interface
- 704 Introduction
- 704 I2C main features
- 705 I2C implementation
- 705 I2C functional description
- 706 I2C1 block diagram
- 707 I2C2 block diagram
- 708 I2C pins and internal signals
- 708 I2C clock requirements
- 708 Mode selection
- 709 I2C initialization
- 714 Software reset
- 715 Data transfer
- 717 I2C slave mode
- 726 25.4.10 I2C master mode
- 738 25.4.11 I2C_TIMINGR register configuration examples
- 739 25.4.12 SMBus specific features
- 742 25.4.13 SMBus initialization
- 744 25.4.14 SMBus: I2C_TIMEOUTR register configuration examples
- 745 25.4.15 SMBus slave mode
- 753 25.4.16 Wakeup from Stop mode on address match
- 753 25.4.17 Error conditions
- 755 25.4.18 DMA requests
- 756 25.4.19 Debug mode
- 756 I2C low-power modes
- 757 I2C interrupts
- 758 I2C registers
- 758 I2C control register 1 (I2C_CR1)
- 761 I2C control register 2 (I2C_CR2)
- 764 I2C own address 1 register (I2C_OAR1)
- 765 I2C own address 2 register (I2C_OAR2)
- 766 I2C timing register (I2C_TIMINGR)
- 767 I2C timeout register (I2C_TIMEOUTR)
- 768 I2C interrupt and status register (I2C_ISR)
- 770 I2C interrupt clear register (I2C_ICR)
- 771 I2C PEC register (I2C_PECR)
- 772 25.7.10 I2C receive data register (I2C_RXDR)
- 772 25.7.11 I2C transmit data register (I2C_TXDR)
- 773 25.7.12 I2C register map
- 775 Universal synchonous receiver transmitter (USART)
- 775 USART introduction
- 776 USART main features
- 777 USART extended features
- 777 USART implementation
- 779 USART functional description
- 779 USART block diagram
- 780 USART signals
- 781 USART character description
- 783 USART FIFOs and thresholds
- 783 USART transmitter
- 787 USART receiver
- 794 USART baud rate generation
- 795 Tolerance of the USART receiver to clock deviation
- 797 USART Auto baud rate detection
- 799 26.5.10 USART multiprocessor communication
- 801 26.5.11 USART Modbus communication
- 802 26.5.12 USART parity control
- 803 26.5.13 USART LIN (local interconnection network) mode
- 805 26.5.14 USART synchronous mode
- 809 26.5.15 USART single-wire Half-duplex communication
- 809 26.5.16 USART receiver timeout
- 810 26.5.17 USART Smartcard mode
- 814 26.5.18 USART IrDA SIR ENDEC block
- 817 26.5.19 Continuous communication using USART and DMA
- 819 26.5.20 RS232 Hardware flow control and RS485 Driver Enable
- 822 26.5.21 USART low-power management
- 825 USART in low-power modes
- 826 USART interrupts
- 827 USART registers
- 827 USART control register 1 [alternate] (USART_CR1)
- 834 USART control register 2 (USART_CR2)
- 838 USART control register 3 (USART_CR3)
- 843 USART baud rate register (USART_BRR)
- 843 USART guard time and prescaler register (USART_GTPR)
- 844 USART receiver timeout register (USART_RTOR)
- 845 USART request register (USART_RQR)
- 846 USART interrupt and status register [alternate] (USART_ISR)
- 852 26.8.10 USART interrupt and status register [alternate] (USART_ISR)
- 857 26.8.11 USART interrupt flag clear register (USART_ICR)
- 859 26.8.12 USART receive data register (USART_RDR)
- 859 26.8.13 USART transmit data register (USART_TDR)
- 860 26.8.14 USART prescaler register (USART_PRESC)
- 861 26.8.15 USART register map
- 863 Serial peripheral interface / integrated interchip sound (SPI/I2S)
- 863 Introduction
- 863 SPI main features
- 864 I2S main features
- 864 SPI/I2S implementation
- 865 SPI functional description
- 865 General description
- 866 Communications between one master and one slave
- 868 Standard multi-slave communication
- 869 Multi-master communication
- 870 Slave select (NSS) pin management
- 871 Communication formats
- 873 Configuration of SPI
- 874 Procedure for enabling SPI
- 874 Data transmission and reception procedures
- 884 27.5.10 SPI status flags
- 885 27.5.11 SPI error flags
- 886 27.5.12 NSS pulse mode
- 886 27.5.13 TI mode
- 887 27.5.14 CRC calculation
- 889 SPI interrupts
- 890 I2S functional description
- 890 I2S general description
- 891 Supported audio protocols
- 898 Start-up description
- 900 Clock generator
- 903 S master mode
- 904 S slave mode
- 906 I2S status flags
- 907 I2S error flags
- 908 DMA features
- 908 I2S interrupts
- 909 SPI and I2S registers
- 909 SPI control register 1 (SPIx_CR1)
- 911 SPI control register 2 (SPIx_CR2)
- 913 SPI status register (SPIx_SR)
- 914 SPI data register (SPIx_DR)
- 915 SPI CRC polynomial register (SPIx_CRCPR)
- 915 SPI Rx CRC register (SPIx_RXCRCR)
- 915 SPI Tx CRC register (SPIx_TXCRCR)
- 916 SPIx_I2S configuration register (SPIx_I2SCFGR)
- 918 SPIx_I2S prescaler register (SPIx_I2SPR)
- 919 27.9.10 SPI/I2S register map
- 920 Universal serial bus full-speed host/device interface (USB)
- 920 Introduction
- 920 USB main features
- 920 USB implementation
- 921 USB functional description
- 923 Description of USB blocks used in both Device and Host modes
- 924 Description of host frame scheduler (HFS) specific to Host mode
- 925 Programming considerations for Device and Host modes
- 925 Generic USB Device programming
- 925 System and power-on reset
- 932 Double-buffered endpoints and usage in Device mode
- 934 Double buffered channels: usage in Host mode
- 935 Isochronous transfers in Device mode
- 937 Isochronous transfers in Host mode
- 937 Suspend/resume events
- 941 USB and USB SRAM registers
- 941 Common registers
- 960 Buffer descriptor table
- 964 USB register map
- 966 Debug support (DBG)
- 966 Overview
- 967 Reference Arm documentation
- 967 Pinout and debug port pins
- 967 SWD port pins
- 967 SW-DP pin assignment
- 968 Internal pull-up & pull-down on SWD pins
- 968 ID codes and locking mechanism
- 968 SWD port
- 968 SWD protocol introduction
- 968 SWD protocol sequence
- 969 SW-DP state machine (reset, idle states, ID code)
- 970 DP and AP read/write accesses
- 970 SW-DP registers
- 971 SW-AP registers
- 972 Core debug
- 972 BPU (Break Point Unit)
- 973 BPU functionality
- 973 DWT (Data Watchpoint)
- 973 DWT functionality
- 973 DWT Program Counter Sample Register
- 973 MCU debug component (DBG)
- 973 Debug support for low-power modes
- 974 29.10 DBG registers
- 974 29.10.1 DBG device ID code register (DBG_IDCODE)
- 975 29.10.2 DBG configuration register (DBG_CR)
- 975 29.10.3 DBG APB freeze register 1 (DBG_APB_FZ1)
- 977 29.10.4 DBG APB freeze register 2 (DBG_APB_FZ2)
- 978 29.10.5 DBG register map
- 980 Device electronic signature
- 980 Flash memory size data register
- 980 Package data register
- 982 Revision history
Frequently Answers and Questions
What is the key difference between Cortex®-M0+ core and Cortex®-M0 core?
The Cortex®-M0+ core has a number of enhancements over the Cortex®-M0 core, including a higher operating frequency, a larger instruction cache, and a more powerful floating-point unit. These enhancements make the Cortex®-M0+ core ideal for applications that require more performance or that use floating-point calculations.
What memory options are available for ST STM32G0x0 MCUs?
ST STM32G0x0 MCUs offer a wide range of memory options, including Flash memory, SRAM, and EEPROM. The amount and type of memory available varies depending on the specific device.
What peripherals are available on ST STM32G0x0 MCUs?
ST STM32G0x0 MCUs offer a rich set of peripherals for connectivity, sensing, and control, including GPIOs, timers, ADCs, DACs, and communication interfaces such as UART, I2C, and SPI.
Questions & Answers
2025-03-24
L L V
What is Slave mode – combined reset + trigger mode for TIM15 timer?
The document mentions "Slave mode – combined reset + trigger mode" in the context of the TIM15 timer. This mode seems to relate to timer synchronization, specifically using a combination of reset and trigger signals to control the timer's operation, but the document does not describe it in detail.
2025-04-28
G G U
What are the purposes of the FLASH_WRP1AR and FLASH_WRP1BR registers, and what distinguishes them?
The FLASH_WRP1AR and FLASH_WRP1BR registers are related to FLASH write protection (WRP). FLASH_WRP1AR is the FLASH WRP area A address register, and FLASH_WRP1BR is the FLASH WRP area B address register. They define different write-protected areas (Area A and Area B), used to define the start and end addresses of the memory areas that are write-protected.
2026-05-31
H H S
What do the End-of-conversion (EOC) and End of conversion sequence (EOS) flags designate?
The EOC flag indicates that an Analog-to-Digital Converter (ADC) conversion is complete, while the EOS flag indicates that the entire sequence of ADC conversions has finished.
2026-05-31
H H S
What do the End-of-conversion (EOC) and End of conversion sequence (EOS) flags signify in the ADC?
The End-of-conversion (EOC) flag indicates that an analog-to-digital conversion has completed. The End of conversion sequence (EOS) flag indicates that the entire sequence of ADC conversions has finished.
2026-05-31
I I S
What is the function of the End of Conversion (EOC) event?
The EOC event is a status flag used by the Analog-to-digital converter (ADC) to indicate that a conversion process has finished and the resulting data is ready.
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