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CYRF6936
WirelessUSB™ LP 2.4GHz Radio SoC
1.0
Features 2.0
Applications
• 2.4-GHz Direct Sequence Spread Spectrum (DSSS) radio transceiver
• Operates in the unlicensed worldwide Industrial, Scientific and Medical (ISM) band (2.400 GHz–2.483 GHz)
• 21mA operating current (Transmit @ –5 dBm)
• Transmit power up to +4 dBm
• Receive sensitivity up to –97 dBm
• Sleep Current <1
µA
• Operating range: 10m+
• DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps
• Low external component count
• Auto Transaction Sequencer (ATS) - no MCU intervention
• Framing, Length, CRC16, and Auto ACK
• Power Management Unit (PMU) for MCU/Sensor
• Fast Startup and Fast Channel Changes
• Separate 16-byte Transmit and Receive FIFOs
• AutoRate™ - dynamic data rate reception
• Receive Signal Strength Indication (RSSI)
• Serial Peripheral Interface (SPI) control while in sleep mode
• 4-MHz SPI microcontroller interface
• Battery Voltage Monitoring Circuitry
• Supports coin-cell operated applications
• Operating voltage from 1.8V to 3.6V
• Operating temperature from 0 to 70°C
• Space saving 40-pin QFN 6x6 mm package
V
IO
• Wireless Keyboards and Mice
• Wireless Gamepads
• Remote Controls
• Toys
• VOIP and Wireless Headsets
• White Goods
• Consumer Electronics
• Home Automation
• Automatic Meter Readers
• Personal Health & Entertainment
3.0
See www.cypress.com for development tools, reference designs, and application notes.
4.0
Applications Support
Functional Description
The CYRF6936 WirelessUSB™ LP radio is a second generation member of Cypress’s WirelessUSB Radio System-On-
Chip (SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data rate options, and reduced crystal start-up, synthesizer settling and link turn-around times.
V
BAT
Figure 4-1. CYRF6936 Simplified Block Diagram
L/D
V
REG
V
DD
V
CC
PACTL
Power Management
IRQ
SS
SCK
MISO
MOSI
SPI
Data
Interface and
Sequencer
DSSS
Baseband
& Framer
GFSK
Modulator
GFSK
Demodulator
RF
P
RF
N
RF
BIAS
RSSI
Xtal Osc
Synthesizer
RST
Block Diagram
GND
XTAL XO
Cypress Semiconductor Corporation
Document #: 38-16015 Rev. *F
• 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Revised July 18, 2006
CYRF6936
5.0
Pin Descriptions
37
40
35
13
11
10
30
1
29
27
24
26
34
25
28
Pin #
6, 8, 38
3, 7, 16
33
19
2, 4, 5, 9, 14, 15, 18, 17, 20,
21, 22, 23, 32, 36, 39, 31
12
E-PAD
GND
GND
Name Type Default
RF
N
RF
P
I/O
I/O
RF
BIAS
O
PACTL I/O
I
I
O
O
XTAL I I
XOUT I/O O
SCK
MISO
MOSI
SS
IRQ
RST
L/D
V
REG
V
DD
V
BAT
V
CC
V
IO
RESV
NC
I
I/O
I/O
I
I/O
I
O
Pwr
Pwr
Pwr
Pwr
Pwr
I
NC
I
O
I
I
I
Z
Description
Differential RF signal to/from antenna
Differential RF signal to/from antenna
RF I/O 1.8V reference voltage
Control signal for external PA, T/R switch, or GPIO
12-MHz crystal
Buffered 0.75, 1.5, 3, 6 or 12 MHz clock, PACTL, or GPIO.
Tristates in sleep mode (recommend configure as GPIO drive low).
SPI clock
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tristates when SPI 3PIN=0 and SS deasserted.
SPI data input pin (Master Out Slave In), or SDAT
SPI enable, active low assertion - enables and frames transfers.
Interrupt output (configurable active high or low), or GPIO
Device reset. Internal 10k-ohm pull-down resistor. Active HIGH, typically connect via 0.1-
µF capacitor to V
BAT
PMU inductor/diode connection
PMU boosted output voltage feedback
Decoupling pin for 1.8V logic regulator, connect via 0.47-
µF capacitor to GND
V
BAT
= 1.8V to 3.6V. Main supply.
V
CC
= 2.4V to 3.6V. Typically connected to V
REG
I/O interface voltage, 1.8–3.6V
Must be connected to GND
Recommend to connect to GND
GND
GND
Ground
Ground
Figure 5-1. CYRF6936, 40 QFN – Top Vie
CYRF6936
Top View*
XTAL
NC
1
2
V
CC
NC
3
4
V
NC
BAT
V
CC
V
BAT
NC
5
6
9
7
8
RF
BIAS
10
CYRF6936
40-lead QFN
30 PACTL / GPIO
29
28
XOUT / GPIO
MISO / GPIO
27 MOSI / SDAT
26
25
IRQ / GPIO
SCK
24
SS
23 NC
22
21
NC
NC
* E-PAD BOTTOM SIDE
Document #: 38-16015 Rev. *F Page 2 of 39
CYRF6936
6.0
Functional Overview
The CYRF6936 IC provides a complete WirelessUSB SPI to antenna wireless MODEM. The SoC is designed to implement wireless device links operating in the worldwide 2.4-GHz ISM frequency band. It is intended for systems compliant with world-wide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15
(USA and Industry Canada) and TELEC ARIB_T66_March,
2003 (Japan).
The SoC contains a 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and
SPI interface for data transfer and device configuration.
The radio supports 98 discrete 1-MHz channels (regulations may limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates enabling the implementation of mixed-rate systems in which different devices use different data rates.
This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low-moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments.
In addition, the CYRF6936 IC has a Power Management Unit
(PMU) which allows direct connection of the device to any battery voltage in the range 1.8V to 3.6V. The PMU conditions the battery voltage to provide the supply voltages required by the device, and may supply external devices.
Data Transmission Modes
The SoC supports four different data transmission modes:
• In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
• In 8DR mode, 8 bits are encoded in each derived code symbol transmitted.
• In DDR mode, 2-bits are encoded in each derived code symbol transmitted. (As in the CYWUSB6934 DDR mode).
• In SDR mode, 1 bit is encoded in each derived code symbol transmitted. (As in the CYWUSB6934 standard modes.)
Both 64-chip and 32-chip Pseudo-Noise (PN) Codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, lower data rates reduce packet error rate in any given environment.
Link Layer Modes
The CYRF6936 IC device supports the following data packet framing features:
SOP – Packets begin with a 2-symbol Start of Packet (SOP)
marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode; if framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The
SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link.
Length – There are two options for detecting the end of a
packet. If SOP is enabled, then the length field should be enabled. GFSK and 8DR must enable the length field. This is the first 8-bits after the SOP symbol, and is transmitted at the payload data rate. When the length field is enabled, an End of
Packet (EOP) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16 (when enabled—see below). The alternative to using the length field is to infer an EOP condition from a configurable number of successive non-correlations; this option is not available in GFSK mode and is only recommended to enable when using SDR mode.
CRC16 – The device may be configured to append a 16-bit
CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver will verify the calculated CRC16 for the payload data against the received value in the CRC16 field.
The seed value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 will be checked against both the configured and zero CRC16 seeds.
CRC16 detects the following errors:
• Any one bit in error
• Any two bits in error (no matter how far apart, which column, and so on)
• Any odd number of bits in error (no matter where they are)
• An error burst as wide as the checksum itself
Figure 6-1 shows an example packet with SOP, CRC16 and
lengths fields enabled, and Figure 6-2 shows a standard ACK
packet.
Figure 6-1. Example Packet Format
P re a m b le n x 1 6 u s
2 n d F ra m in g
S y m b o l*
P S O P 1 S O P 2 P a y lo a d D a ta C R C 1 6
1 s t F ra m in g
S y m b o l*
L e n g th
P a c k e t le n g th
1 B y te
P e rio d
*N o te :3 2 o r 6 4 u s
Document #: 38-16015 Rev. *F Page 3 of 39
CYRF6936
P r e a m b le n x 1 6 u s
P S O P 1
1 s t F r a m in g
S y m b o l*
Figure 6-2. Example ACK Packet Format
2 n d F r a m in g
S y m b o l*
S O P 2 C R C 1 6
C R C f ie ld f r o m r e c e iv e d p a c k e t .
2 B y t e p e r io d s
Packet Buffers
All data transmission and reception utilizes the 16-byte packet buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16-bytes of payload data to be loaded in one burst SPI transaction, and then transmitted with no further MCU intervention. Similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete.
The CYRF6936 IC supports packets up to 255 bytes, however, actual maximum packet length will depend on accuracy of the clock on each end of the link and the data mode; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16-bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the
FIFO periodically during packet reception to prevent it from overflowing.
Auto Transaction Sequencer (ATS)
The CYRF6936 IC provides automated support for transmission and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
• starts the crystal and synthesizer
• enters transmit mode
• transmits the packet in the transmit buffer
• transitions to receive mode and waits for an ACK packet
• transitions to the transaction end state when either an ACK packet is received, or a timeout period expires
Similarly, when receiving in transaction mode, the device automatically:
• waits in receive mode for a valid packet to be received
• transitions to transmit mode, transmits an ACK packet
• transitions to the transaction end state (receive mode to await the next packet, etc.)
The contents of the packet buffers are not affected by the transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without any need for MCU firmware action (providing packets of 16 bytes or less are used); to transmit data the MCU simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply needs to retrieve the fully
* N o t e : 3 2 o r 6 4 u s received packet in response to an interrupt request indicating reception of a packet.
Backward Compatibility
The CYRF6936 IC is fully interoperable with the main modes of the first generation devices. The 62.5-kbps mode is supported by selecting 32-chip DDR mode. Similarly, the
15.675-kbps mode is supported by selecting 64-chip SDR mode.
In this way, a suitably configured CYRF6936 IC device may transmit data to and/or receive data from a first generation device. Disabling the SOP, length, and CRC16 fields is required for backwards compatibility.
Data Rates
By combining the PN code lengths and data transmission modes described above, the CYRF6936 IC supports the following data rates:
• 1000-kbps (GFSK)
• 250-kbps (32-chip 8DR)
• 125-kbps (64-chip 8DR)
• 62.5-kbps (32-chip DDR)
• 31.25-kbps (64-chip DDR)
• 15.625-kbps (64-chip SDR)
7.0
Functional Block Overview
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in 7 steps. The supply current of the device is reduced as the RF output power is reduced.
Table 7-1. Internal PA Output Power Step Table
PA Setting Typical Output Power (dBm)
7
6
+4
0
3
2
5
4
1
0
–5
–13
–18
–24
–30
–35
Document #: 38-16015 Rev. *F Page 4 of 39
CYRF6936
Table 7-2. Typical Range Observed Table
Environment Typical Range (meters)
Outdoor
Office
Home
30
20
15
Note: Range observed with CY4636 WirelessUSB LP KBM v1.0 (Keyboard)
Frequency Synthesizer
Before transmission or reception may commence, it is necessary for the frequency synthesizer to settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100-
µs.
The “fast channels” (<100-
µs settling time) are every 3 rd channel, starting at 0 up to and including 72 (i.e.,
0,3,6,9…….69 & 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, as well as EOP detection and length field.
Packet Buffers and Radio Configuration
Registers
Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet (as in the CYWUSB6934). Configuration registers are provided to allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, etc.
SPI Interface
The CYRF6936 IC has a SPI interface supporting communications between an application MCU and one or more slave devices (including the CYRF6936). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or
3-pin interfacing. The SPI communications interface consists of Slave Select (SS), Serial Clock (SCK), and Master Out-
Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
The SPI communications is as follows:
• Command Direction (bit 7) = “1” enables SPI write transaction. A “0” enables SPI read transactions.
• Command Increment (bit 6) = “1” enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed.
• Six bits of address.
• Eight bits of data.
The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active-low Slave Select (SS) pin must be asserted to initiate an SPI transfer.
The application MCU can initiate SPI data transfers via a multibyte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes as shown in
Figure 7-1 through Figure 7-4.
The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as desired. A burst transaction is terminated by deasserting the slave select (SS = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 7-2 and Figure 7-3, respec-
tively.
The SPI communications interface single write and burst write
sequences are shown in Figure 7-4 and Figure 7-5, respec-
tively.
This interface may optionally be operated in a 3-pin mode with the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware should ensure that the MOSI pin on the MCU is in a highimpedance state except when MOSI is actively transmitting data.
The device registers may be written to or read from 1 byte at a time, or several sequential register locations may be written/read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the device includes register files; register files are FIFOs written to and read from using non-incrementing burst SPI transactions.
The IRQ pin function may optionally be multiplexed onto the
MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware should ensure that the MOSI pin on the
MCU is in a high impedance state whenever the SS pin is high.
The SPI interface is not dependent on the internal 12-MHz clock, and registers may therefore be read from or written to while the device is in sleep mode, and the 12-MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate voltage reference pin (V
IC supply voltage.
IO
), enabling the device to interface directly to MCUs operating at voltages below the CYRF6936
Document #: 38-16015 Rev. *F Page 5 of 39
CYRF6936
SCK
SS
MOSI
MISO
SCK
SS
MOSI
MISO
Bit #
Bit Name
7
DIR
6
INC
Figure 7-1. SPI Transaction Format
Byte 1
[5:0]
Address
Figure 7-2. SPI Single Read Sequence
cmd
DIR
0
INC A5 A4 A3 addr
A2 A1 A0
D7 D6 D5 data to mcu
D4 D3 D2 D1 D0
Figure 7-3. SPI Incrementing Burst Read Sequence
SCK
SS
MOSI
MISO
Byte 1+N
[7:0]
Data cmd
DIR
0
INC A5 A4 A3 addr
A2 A1 A0
D7 D6 D5 data to mcu
1
D4 D3 D2 D1 D0 D7 D6 data to mcu
1+N
D5 D4 D3 D2 D1 D0
Figure 7-4. SPI Single Write Sequence
cmd
DIR
1
INC A5 A4 A3 addr
A2 A1 A0 D7 D6 D5 data from mcu
D4 D3 D2 D1 D0
Figure 7-5. SPI Incrementing Burst Write Sequence
SCK
SS
MOSI
MISO cmd
DIR
1
INC A5 A4 addr
A3 A2 A1 A0 D7 D6 data from mcu
1
D5 D4 D3 D2 D1 D0 D7 D6 data from mcu
1+N
D5 D4 D3 D2 D1 D0
Document #: 38-16015 Rev. *F Page 6 of 39
CYRF6936
Interrupts
The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events.
The IRQ pin may be programmed to be either active high or active low, and be either a CMOS or open drain output. A full description of all the available interrupts can be found in
The CYRF6936 IC features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled.
The contents of the enable registers are preserved when switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without making use of the IRQ pin by polling the status register(s) to wait for an event, rather than using the
IRQ pin.
Clocks
A 12-MHz crystal (30-ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75-, 1.5-, 3-, 6-, or 12-MHz. This output may be used to clock an external microcontroller (MCU) or
ASIC. This output is enabled by default, but may be disabled.
Below are the requirements for the crystal to be directly connected to XTAL pin and GND:
• Nominal Frequency: 12 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Initial Stability: ±30 ppm
• Series Resistance: <60 ohms
• Load Capacitance: 10 pF
• Drive Level: 10
µW–100 µW
Power Management
The operating voltage of the device is 1.8V to 3.6V DC, which is applied to the V
BAT
pin. The device can be shutdown to a fully static sleep mode by writing to the FRC END = 1 and END
STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device will enter sleep mode within 35-
µs after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device will wake from sleep mode automatically when the device is commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device may be configured to assert the
IRQ pin when the oscillator has stabilized.
The output voltage (V
REG
) of the Power Management Unit
(PMU) is configurable to several minimum values between
2.4V and 2.7V. V
REG
may be used to provide up to 15 mA
(average load) to external devices. It is possible to disable the
PMU, and to provide an externally regulated DC supply voltage to the device’s main supply in the range 2.4V to 3.6V.
The PMU also provides a regulated 1.8V supply to the logic.
The PMU has been designed to provide high boost efficiency
(74–85% depending on input voltage, output voltage and load) when using a Schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. However, reasonable efficiencies (69-82% depending on input voltage, output voltage and load) may be achieved when using low cost components such as SOT23 diodes and 0805 inductors.
The PMU also provides a configurable low battery detection function which may be read over the SPI interface. One of seven thresholds between 1.8V and 2.7V may be selected.
The interrupt pin may be configured to assert when the voltage on the V
BAT
pin falls below the configured threshold. LV IRQ is not a latched event. Battery monitoring is disabled when the device is in sleep mode.
Low Noise Amplifier (LNA) and Received
Signal Strength Indication (RSSI)
The gain of the receiver may be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. When the LNA bit is cleared, the receiver gain is reduced by approximately 20 dB, allowing accurate reception of very strong received signals (for example when operating a receiver very close to the transmitter). Approximately 30 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit; this allows data reception to be limited to devices at very short ranges.
Disabling AGC and enabling LNA is recommended unless receiving from a device using external PA.
When the device is in receive mode the RSSI_ADR register returns the relative signal strength of the on-channel signal power.
When receiving, the device will automatically measure and store the relative strength of the signal being received as a 5bit value. An RSSI reading is taken automatically when the
SOP is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI_ADR register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read when no signal is being received. A new reading can occur as fast as once every 12
µs.
Document #: 38-16015 Rev. *F Page 7 of 39
8.0
Application Examples
Figure 8-1. Recommended circuit for systems where V
BAT
may fall below 2.4V.
CYRF6936
2
1
0402
0402
0402
0402
0402
0402
0402
0402
6
8
38
33
40
7
3
16
35
VIO
VDD
VCC2
VCC3
VCC1
VREG
VBAT1
VBAT2
VBAT0
E-PAD
GND1
12
41
27
5
VDD2
VDD1
VSS2
VSS1
44
24
Document #: 38-16015 Rev. *F Page 8 of 39
CYRF6936
Figure 8-2. Recommended bill of materials for systems where V
BAT
may fall below 2.4V.
Bill of Materials
TITLE
PCA #
SCH #
DATE
LP RDK Keyboard
121-265 04
REF-13288
3/17/2005
Item Qty
12
13
14
15
9
10
7
8
11
5
6
3
4
1
2
16
17
18
19
20
21
22
23
CY Part Number
1 NA
1 200-?????
1 730-10012
1 730-11955
1 730-11398
1 730-13322
2 730-13037
1 730-13400
6 730-13404
1 730-11952
1 710-13201
2 730-10794
1 800-13317
1 NA
1 420-11496
1 420-11964
1 800-13401
1 800-11651
1 800-10594
1 630-11356
1 610-13402
1 800-13368
1 CYRF6936-40LFC
1 CY7C60123-PVXC
24
25
26
27
28
1 800-13259
1
1
1
PDC-9265-*B
NO LOAD COMPONENTS - DO NOT INSTALL
29 1 730-13403 C6
30
31
1 630-10242
1 730-13404
R2
C7
32
33
1 420-10921
1 620-10519
J4
R1
Reference
J3
L1
L2
L3
R2
R3
S1
U1
U2
ANT1
BH1
C1
C3
C4
C5
C12, C7
C8
C9,C10,C11,C13,C15,C16
C17
C18
C20,C19
D1
J1
J2
Y1
PCB
LABEL1
LABEL2
Revision
**
Revision
*C
Description
2.5GHZ H-STUB WIGGLE ANTENNA FOR
63MIL PCB
BATTERY CLIPS 2AA CELL CHICONY KB
CAP 15PF 50V CERAMIC NPO 0402
CAP 2.0 PF 50V CERAMIC NPO 0402
CAP 1.5PF 50V CERAMIC NPO 0402 SMD
CAP 0.47 uF 50V CERAMIC X5R 0402
CAP CERAMIC 10UF 6.3V X5R 0805
CAP 1 uF 6.3V CERAMIC X5R 0402
CAP 0.047 uF 16V CERAMIC X5R 0402
CAP 0.1 uF 50V CERAMIC X5R 0402
CAP 100UF 10V ELECT FC
CAP 10000PF 16V CERAMIC 0402 SMD
DIODE SCHOTTKY 0.5A 40V SOT23
PCB COPPER PADS
CONN HDR BRKWAY 5POS STR AU PCB
HEADER 1 POS 0.230 HT MODII .100CL
INDUCTOR 22NH 2% FIXED 0603 SMD
INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD
COIL 10UH 1100MA CHOKE 0805
RES 1.00 OHM 1/8W 1% 0805 SMD
RES 47 OHM 1/16W 5% 0402 SMD
LT SWITCH 6MM 100GF H=7MM TH
IC, LP 2.4 GHz RADIO SoC QFN-40
IC WIRELESS EnCore II CONTROLLER
SSOP48
CRYSTAL 12.00MHZ HC49 SMD
PRINTED CIRCUIT BOARD
Serial Number
PCA #
Manufacturer
NA
CHICONY
Panasonic
Kamet
PANASONIC
Murata
Kamet
Panasonic
AVX
Kamet
Panasonic - ECG
Panasonic - ECG
DIODES INC
NONE
AMP Division of TYCO
AMP/Tyco
Panasonic - ECG
Panasonic - ECG
Newark
Yageo
Panasonic - ECG
Panasonic - ECG
Cypress Semiconductor
Cypress Semiconductor eCERA
Cypress Semiconductor
XXXXXX
121-26504 **
Mfr Part Number
NA
KBR0108
ECJ-0EC1H150J
C0402C209C5GACTU
ECJ-0EC1H1R5C
GRM155R60J474KE19D
C0805C106K9PACTU
ECJ-0EB0J105M
0402YD473KAT2A
C0402C104K8PACTU
EEU-FC1A101S
ECJ-0EB1C103K
BAT400D-7-F
103185-5
103185-1
ELJ-RE22NGF2
ELJ-RF1N8DF
30K5421
9C08052A1R00FKHFT
ERJ-2GEJ470X
EVQ-PAC07K
CYRF6936 Rev A5
CY7C60123-PVXC
GF-1200008
PDC-9265-*B
CAP 47UF 6.3V CERAMIC X5R 1210
RES CHIP 0.0 OHM 1/10W 5% 0805 SMD
CAP 0.047 uF 50V CERAMIC X5R 0402
HEADER 3POS FRIC STRGHT MTA 100
RES ZERO OHM 1/16W 5% 0603 SMD
Panasonic
Phycomp USA Inc
AVX
AMP/Tyco
Panasonic - ECG
ECJ-4YB0J476M
9C08052A0R00JLHFT
0402YD473KAT2A
644456-3
ERJ-3GEY0R00V
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Page 1 of 1
Document #: 38-16015 Rev. *F Page 9 of 39
CYRF6936
Figure 8-3. Recommended circuit for systems where V
BAT
is 2.4V to 3.6V (PMU disabled).
0402
33
40
6
8
38
7
3
16
35
VIO
VDD
VCC2
VCC3
VCC1
VREG
VBAT1
VBAT2
VBAT0
2
1
0402
0402
E-PAD
GND1
12
41
0402
11
VCC VSS
8
0402
Document #: 38-16015 Rev. *F Page 10 of 39
CYRF6936
Figure 8-4. Recommended bill of materials for systems where V
BAT
is 2.4V to 3.6V (PMU disabled).
Bill of Materials
TITLE
PCA #
SCH #
DATE
LP RDK Dongle II
121-263 05
REF-13287
3/24/2005
Revision
**
Revision
*A
9
14
15
16
17
10
11
12
13
18
19
20
21
22
Item Qty
5
6
7
8
1
2
3
4
CY Part Number
1 NA
1 730-10012
1 730-11955
1 730-11398
1 730-13322
6 730-13404
1 730-11953
1 730-13400
1 730-12003
1 800-13333
1 420-13046
1 800-13401
1 800-11651
1 610-10343
1 610-13472
1 200-13471
1 CYRF6936-40LFC
1 CY7C63803-SXC
1 800-13259
1 PDC-9263-*B
1
1
Reference
ANT1
C1
C3
C4
C5
C6,C7,C8,C9,C10,C11
C12
C13
C14
D1
J1
L1
L2
R1
R2
S1
U1
U2
Y1
PCB
LABEL1
LABEL2
Description
2.5GHZ H-STUB WIGGLE ANTENNA FOR
32MIL PCB
CAP 15PF 50V CERAMIC NPO 0402
CAP 2.0 PF 50V CERAMIC NPO 0402
CAP 1.5PF 50V CERAMIC NPO 0402 SMD
CAP 0.47 uF 50V CERAMIC X5R 0402
CAP 0.047 uF 50V CERAMIC X5R 0402
CAP 1500PF 50V CERAMIC X7R 0402
CAP CERAMIC 4.7UF 6.3V XR5 0805
CAP CER 2.2UF 10V 10% X7R 0805
LED GREEN/RED BICOLOR 1210 SMD
CONN USB PLUG TYPE A PCB SMT
INDUCTOR 22NH 2% FIXED 0603 SMD
INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD
RES ZERO OHM 1/16W 0402 SMD
RES CHIP 620 OHM 1/16W 5% 0402 SMD
SWITCH LT 3.5MMX2.9MM 160GF SMD
IC, LP 2.4 GHz RADIO SoC QFN-40
IC LOW-SPEED USB ENCORE II
CONTROLLER SOIC16
CRYSTAL 12.00MHZ HC49 SMD
PRINTED CIRCUIT BOARD
Serial Number
PCA #
Manufacturer Mfr Part Number
NA
Panasonic
Kemet
PANASONIC
Murata
AVX
Kemet
Kemet
Murata Electronics North
America
LITEON
ACON
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Cypress Semiconductor
NA
ECJ-0EC1H150J
C0402C209C5GACTU
ECJ-0EC1H1R5C
GRM155R60J474KE19D
0402YD473KAT2A
C0402C152K5RACTU
C0805C475K9PACTU
GRM21BR71A225KA01L
LTST-C155KGJRKT
UAR72-4N5J10
ELJ-RE22NGF2
ELJ-RF1N8DF
ERJ-2GE0R00X
ERJ-2GEJ621X
EVQ-P7J01K
CYRF6936 Rev A5
Cypress Semiconductor eCERA
Cypress Semiconductor
XXXXXX
121-26305 **
CY7C63803-SXC
GF-1200008
PDC-9263-*B
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Page 1 of 1
Document #: 38-16015 Rev. *F Page 11 of 39
CYRF6936
9.0
Register Descriptions
All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential groups.
Table 9-1. Register Map Summary
Address
0x00
0x01
Mnemonic
CHANNEL_ADR
TX_LENGTH_ADR
b7
Not Used
0x02
0x03
0x04
0x05
0x06
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x26
TX_CTRL_ADR
TX_CFG_ADR
TX_IRQ_STATUS_ADR
RX_CTRL_ADR
RX_CFG_ADR
RX_IRQ_STATUS_ADR
RX_STATUS_ADR
RX_COUNT_ADR
RX_LENGTH_ADR
PWR_CTRL_ADR
XTAL_CTRL_ADR
IO_CFG_ADR
GPIO_CTRL_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
DATA32_THOLD_ADR
DATA64_THOLD_ADR
RSSI_ADR
EOP_CTRL_ADR
CRC_SEED_LSB_ADR
CRC_SEED_MSB_ADR
TX_CRC_LSB_ADR
TX_CRC_MSB_ADR
RX_CRC_LSB_ADR
RX_CRC_MSB_ADR
TX_OFFSET_LSB_ADR
TX_OFFSET_MSB_ADR
MODE_OVERRIDE_ADR
RX_OVERRIDE_ADR
TX_OVERRIDE_ADR
XTAL_CFG_ADR
TX GO
Not Used
OS
IRQ
RX GO
AGC EN
RXOW
IRQ
RX ACK
Not Used
RSVD
ACK RX
ACK TX
RSVD
b6
TX CLR
Not Used
LV
IRQ
RSVD
LNA
SOPDET
IRQ
PKT ERR
PMU EN LVIRQ EN
XOUT FN
IRQ OD
XOUT OP
IRQ POL
MISO OP
ACK EN
SOP EN
Not Used
Not Used
SOP
HEN
Not Used
SOP LEN
Not Used
Not Used
Not Used
Not Used
RSVD
b5
TXB15
IRQEN
DATA CODE
LENGTH
TXB15
IRQ
RXB16
IRQEN
ATT
RXB16
IRQ
EOP ERR
PMU SEN
XSIRQ EN
MISO OD
PACTL OP
FRC END
LEN EN
Not Used
Not Used
LNA
b4
TXB8
IRQEN
b3
Channel
TX Length
TXB0
IRQEN
b2
TXBERR
IRQEN
b1
TXC
IRQEN
b0
TXE
IRQEN
DATA MODE
TXB8
IRQ
TXB0
IRQ
RXB8
IRQEN
HILO
RXB1
IRQEN
FAST TURN
EN
TXBERR
IRQ
RXBERR
IRQEN
RXB8
IRQ
CRC0
RXB1
IRQ
Bad CRC
RX Count
RX Length
Not Used
Not Used Not Used
LVI TH
Not Used
RXBERR
IRQ
RX Code
PA SETTING
TXC
IRQ
RXC
IRQEN
RXOW EN
RXC
IRQ
TXE
IRQ
RXE
IRQEN
VLD EN
RXE
IRQ
RX Data Mode
XOUT OD PACTL OD PACTL GPIO
IRQ OP XOUT IP MISO IP
END STATE
Not Used
SOP TH
TH32
TH64
SPI 3PIN
PACTL IP
ACK TO
IRQ GPIO
IRQ IP
RSSI
PMU OUTV
FREQ
Not Used
FRC SEN
RXTX DLY MAN RXACK
FRC PRE
RSVD
RSVD
RSVD
CRC SEED LSB
CRC SEED MSB
CRC LSB
CRC MSB
CRC LSB
CRC MSB
STRIM LSB
Not Used
FRC AWAKE
FRC
RXDR DIS CRC0
STRIM MSB
Not Used
DIS RXCRC
Not Used
ACE
MAN
TXACK OVRD ACK DIS TXCRC
RSVD START DLY RSVD
RSVD
RSVD
RST
Not Used
TX INV
RSVD
Default
-1001000
Access
-bbbbbbb
00000000 bbbbbbbb
00000011 bbbbbbbb
--000101
--------
--bbbbbb rrrrrrrr
00000111 bbbbbbbb
10010-10
-------bbbbb-bb brrrrrrr
--------
00000000
00000000 rrrrrrrr rrrrrrrr rrrrrrrr
10100000
000--100 bbb-bbbb bbb--bbb
00000000 bbbbbbbb
0000---bbbbrrrr
1-000000 b-bbbbbb
10100101 bbbbbbbb
----0100
---01010
0-100000
----bbbb
---bbbbb r-rrrrrr
00000000 bbbbbbbb
00000000 bbbbbbbb
--------
-------rrrrrrrr rrrrrrrr
11111111
11111111 rrrrrrrr rrrrrrrr
00000000 bbbbbbbb
----0000 ----bbbb
00000--0 wwwww--w
0000000bbbbbbb-
00000000 bbbbbbbb
0x27
0x28
0x29
0x32
0x35
0x39
CLK_OVERRIDE_ADR
CLK_EN_ADR
RX_ABORT_ADR
AUTO_CAL_TIME_ADR
AUTO_CAL_OFFSET_ADR
ANALOG_CTRL_ADR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
ABORT EN
RSVD
RSVD
RSVD
RSVD
AUTO_CAL_TIME
AUTO_CAL_OFFSET
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RXF
RSVD
RX INV
RSVD
RSVD
RSVD
ALL SLOW
00000000 wwwwwww w
00000000 wwwwwww w
00000000 wwwwwww w
00000000 wwwwwww w
00000011 wwwwwww w
00000000 wwwwwww w
00000000 wwwwwww w
Register Files
0x20 TX_BUFFER_ADR TX Buffer File --------
0x21
0x22
0x23
0x24
0x25
RX_BUFFER_ADR
SOP_CODE_ADR
DATA_CODE_ADR
PREAMBLE_ADR
MFG_ID_ADR
RX Buffer File
SOP Code File
Data Code File
Preamble File
MFG ID File
Notes
1. b = read/write, r = read only, w = write only, - = not used, default value is undefined.
2. SOP_CODE_ADR default = 0x17FF9E213690C782.
3. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
4. PREAMBLE_ADR default = 0x333302.
--------
NA wwwwwww w rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
Document #: 38-16015 Rev. *F Page 12 of 39
CYRF6936
Bit
Mnemonic
Default
Read/Write
Function
7
-
-
Not Used
6
1
R/W
CHANNEL_ADR
5
0
R/W
4
0
R/W
3
1
R/W
Channel
2
0
R/W
Address
1
0
R/W
0
0
R/W
0x00
Bit 7
Bits 6:0
Not Used.
This field selects the channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 are not valid. The default channel is a fast channel above the frequency typically used in non-overlapping WiFi systems. Any write to this register will impact the time it takes the synthesizer to settle.
fast (100-
µs) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96 medium (180
−µs) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94 slow (270-
µs) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97
Usable channels subject to regulation.
Bit
Mnemonic
Default
Read/Write
Function
7
0
R/W
6
0
R/W
TX_LENGTH_ADR
5
0
R/W
4
0
R/W
TX Length
3
0
R/W
2
0
R/W
Address
1
0
R/W
0
0
R/W
0x01
Bits 7:0 This register sets the length of the packet to be transmitted. A length of zero is valid, and will transmit a packet with SOP, length and CRC16 fields (if enabled), but no data field. Packet lengths of more than 16 bytes will require that some data bytes be written after transmission of the packet has begun. Typically, length is updated prior to setting TX GO. The maximum packet length for all packets is 40 bytes except for framed 64-chip DDR where the maximum packet length is 16 bytes.
Maximum packet length is limited by the delta between the transmitter and receiver crystals of 60-ppm or better.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit
Mnemonic
Default
Read/Write
Function
Bit 7
Bit 6
Bit 0
7
0
R/W
6
0
R/W
TX CLR
TX_CTRL_ADR
5
0
R/W
TXB15
IRQEN
4
0
R/W
TXB8
IRQEN
3
0
R/W
TXB0
IRQEN
2
0
R/W
TXBERR
IRQEN
Address
1
1
R/W
TXC
IRQEN
0x02
0
1
R/W
TXE
IRQEN TX GO
Start Transmission. Setting this bit triggers the transmission of a packet. Writing a 0 to this flag has no effect. This bit is cleared automatically at the end of packet transmission. The transmit buffer may be loaded either before or after setting this bit. If data is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth), the length of the SOP code, the length of preamble, and the packet data rate. For example, if starting from idle mode on a fast channel in 8DR mode with 32 chip SOP codes the time available is 100
µs (synth start) + 32 µs (preamble) + 64 µs (SOP length) + 32
µs (length byte) = 228 µs. If there are no bytes in the TX buffer at the end of transmission of the length field, a
TXBERR IRQ will occur and transmission will abort.
Clear TX Buffer. Writing a 1 to this register clears the transmit buffer. Writing a 0 to this bit has no effect. The previous packet
(16 or fewer bytes) may be retransmitted by setting TX GO and not setting this bit. If a new transmit packet is to be loaded before/after the TX GO bit has been set, then this bit should be set before loading a new transmit packet to the buffer.
Buffer Not Full Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Buffer Half Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Buffer Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Buffer Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Transmission Complete Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for description.
Transmit Error Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for description.
Document #: 38-16015 Rev. *F Page 13 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bit 5
Bits 4:3
Bits 2:0
7
-
-
6
-
-
TX_CFG_ADR
5
0
R/W
Data Code
Length
4
0
R/W
3
0
R/W
2
1
R/W
Address
1
0
R/W
0
1
R/W
0x03
Not Used Not Used Data Mode PA Setting
Data Code Length. This bit selects the length of the DATA_CODE_ADR code for the data portion of the packet. This bit is ignored when the data mode is set to GFSK. 1 = 64 chip codes. 0 = 32 chip codes.
Data Mode. This field sets the data transmission mode. 00 = 1-Mbps GFSK. 01 = 8DR Mode. 10 = DDR Mode. 11 = SDR Mode.
It is recommended that firmware sets the ALL SLOW bit in register ANALOG_CTRL_ADR when using GFSK data rate mode.
PA Setting. This field sets the transmit signal strength. 0 = –30 dBm, 1 = –25 dBm, 2 = –20 dBm, 3 = –15 dBm, 4 = –10 dBm,
5 = –5 dBm, 6 = 0 dBm, 7 = +4 dBm.
Mnemonic
Bit
Default
Read/Write
Function
7
-
R
OS IRQ
TX_IRQ_STATUS_ADR
6
-
R
LV IRQ
5
-
R
TXB15 IRQ
4
-
R
TXB8 IRQ
3
-
R
TXB0 IRQ
2
-
R
TXBERR IRQ
Address
1
-
R
TXC IRQ
0
-
R
0x04
TXE IRQ
The state of all IRQ status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7 Oscillator Stable IRQ Status. This bit is set when the internal crystal oscillator has settled (synthesizer sequence starts).
Bit 6
Bit 5
Low Voltage Interrupt Status. This bit is set when the voltage on V
BAT
is below the LVI threshold (see PWR_CTL_ADR). This interrupt is automatically disabled whenever the PMU is disabled. When enabled, this bit reflects the voltage on V
BAT
.
Buffer Not Full Interrupt Status. This bit is set whenever there are 15 or fewer bytes remaining in the transmit buffer.
Bit 4
Bit 3
Bit 2
Buffer Half Empty Interrupt Status. This bit is set whenever there are 8 or fewer bytes remaining in the transmit buffer.
Buffer Empty Interrupt Status. This bit is set at any time that the transmit buffer is empty.
Bit 1
Buffer Error Interrupt Status. This IRQ is triggered by either of two events: (1) When the transmit buffer (TX_BUFFER_ADR) is empty and the number of bytes remaining to be transmitted is greater than zero. (2) When a byte is written to the transmit buffer and the buffer is already full. This IRQ is cleared by setting bit TX CLR in TX_CTRL_ADR.
Transmission Complete Interrupt Status. This IRQ is triggered when transmission is complete. If transaction mode is not enabled then this interrupt is triggered immediately after transmission of the last bit of the CRC16. If transaction mode is enabled, this interrupt is triggered at the end of a transaction. Reading this register clears this bit. TXC IRQ and TXE IRQ flags may change value at different times in response to a single event. If transaction mode is enabled and the first read of this register returns TXC IRQ=1 and TXE IRQ=0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of TXE. There can be a case when this bit is not triggered when ACK EN = 1 and there is an error in transmission. If the first read of this register returns TXC IRQ = 1 and TXE IRQ = 1 then the firmware must not execute a second read to this register for a given transaction. If an ACK is received RXC IRQ and RXE IRQ may be asserted instead of
TXC IRQ and TXE IRQ.
Bit 0 Transmit Error Interrupt Status. This IRQ is triggered when there is an error in transmission. This interrupt is only applicable to transaction mode. It is triggered whenever no valid ACK packet is received within the ACK timeout period. Reading this register clears this bit. See TXC IRQ, above.
Document #: 38-16015 Rev. *F Page 14 of 39
CYRF6936
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Bit
Default
Read/Write
Function
Bit 7
7
0
R/W
RX GO
6
0
R/W
RSVD
RX_CTRL_ADR
5
0
R/W
RXB16
IRQEN
4
0
R/W
RXB8
IRQEN
3
0
R/W
RXB1
IRQEN
2
1
R/W
RXBERR
IRQEN
Address
1
1
R/W
RXC
IRQEN
0
1
0x05
R/W
RXE
IRQEN
Start Receive. Setting this bit causes the device to transition to receive mode. If necessary, the crystal oscillator and synthesizer will start automatically after this bit is set. Firmware must never clear this bit. This bit must not be set again until after it self clears. The recommended method to exit receive mode when an error has occurred is to force END STATE and then dummy read all RX_COUNT_ADR bytes from RX_BUFFER_ADR or poll RSSI_ADR.SOP (bit 7) until set. See XACT_CFG_ADR and
RX_ABORT_ADR for description.
Reserved. Must be zero.
Buffer Full Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Buffer Half Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Buffer Not Empty Interrupt Enable. RXB1 IRQEN must not be set when RXB8 IRQEN is set and vice versa. See
RX_IRQ_STATUS_ADR for description.
Buffer Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Packet Reception Complete Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Receive Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Document #: 38-16015 Rev. *F Page 15 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
1
R/W
AGC EN
6
0
R/W
LNA
RX_CFG_ADR
5
0
R/W
ATT
4
1
R/W
HILO
3
0
R/W
FAST TURN
EN
2
-
-
Not Used
Address
1
1
R/W
RXOW EN
0
0
0x06
R/W
VLD EN
Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Automatic Gain Control (AGC) Enable. When this bit is set, AGC is enabled, and the LNA is controlled by the AGC circuit.
When this bit is cleared the LNA is controlled manually using the LNA bit. Typical applications will clear this bit during initialization. It is recommended that this bit be cleared and bit 6 (LNA) be set unless the device will be used in a system where it may receive data from a device using an external PA to transmit signals at >+4 dBm.
Low Noise Amplifier (LNA) Manual Control. When AGC EN (Bit 7) is cleared, this bit controls the state of the receiver LNA; when AGC EN is set, this bit has no effect. Setting this bit enables the LNA; clearing this bit disables the LNA. Device current in receive mode is slightly lower when the LNA is disabled. Typical applications will set this bit during initialization.
Receive Attenuator Enable. Setting this bit enables the receiver attenuator. The receiver attenuator may be used to de-sensitize the receiver so that only very strong signals may be received. This bit should only be set when the AGC EN is disabled and the LNA is manually disabled.
HILO. When FAST TURN EN is set, this bit is used to select whether the device will use the high frequency for the channel selected, or the low frequency. 1 = hi; 0 = lo. When FAST TURN EN is not enabled this also controls the highlow bit to the receiver and should be left at the default value of 1 for high side receive injection. Typical applications will clear this bit during initialization.
Fast Turn Mode Enable. When this bit is set, the HILO bit determines whether the device receives data transmitted 1MHz above the RX Synthesizer frequency or 1 MHz below the receiver synthesizer frequency. Use of this mode allows for very fast turn-around, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthesizer resettling period between transmit and receive. Note that when this bit is set, and the HILO bit is cleared, received data bits are automatically inverted to compensate for the inversion of data received on the “image” frequency. Typical applications will set this bit during initialization.
Overwrite Enable. When this bit is set, if an SOP is detected while the receive buffer is not empty, then the existing contents of receive buffer are lost, and the new packet is loaded into the receive buffer. When this bit is set, the RXOW IRQ is enabled. If this bit is cleared, then the receive buffer may not be over-written by a new packet, and whenever the receive buffer is not empty SOP conditions are ignored, and it is not possible to receive data until the previously received packet has been completely read from the receive buffer.
Valid Flag Enable. When this bit is set, the receive buffer can store up to 8 bytes of data interleaved with valids (data0, valids0, data1, valids1,...). Typically, this bit is set only when interoperability with first generation devices is desired. See
RX_BUFFER_ADR for more detail.
Document #: 38-16015 Rev. *F Page 16 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
-
R/W
RX_IRQ_STATUS_ADR
6
-
R
5
-
R
4
-
R
RXOW IRQ SOPDET IRQ RXB16 IRQ RXB8 IRQ
3
-
R
RXB1 IRQ
2
-
R
RXBERR IRQ
Address
1
-
R
RXC IRQ
0
-
R
0x07
RXE IRQ
The state of all IRQ Status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags may change value at different times in response to a single event). In particular, standard error handling is only effective if the premature termination of a transmission due to an exception does not leave the device in an inconsistent state.
Receive Overwrite Interrupt Status. This IRQ is triggered when the receive buffer is over-written by a packet being received before the previous packet has been read from the buffer. This bit is cleared by writing any value to this register. This condition is only possible when the RXOW EN bit in RX_CFG_ADR is set. This bit must be written “1” by firmware before the new packet may be read from the receive buffer.
Start of packet detect. This bit is set whenever the start of packet symbol is detected.
Receive Buffer Full Interrupt Status. This bit is set whenever the receive buffer is full, and cleared otherwise.
Receive Buffer Half Full Interrupt Status. This bit is set whenever there are 8 or more bytes remaining in the receive buffer.
Firmware must read exactly eight bytes when reading RXB8 IRQ.
Receive Buffer Not Empty Interrupt Status. This bit is set at any time that there are 1 or more bytes in the receive buffer., and cleared when the receive buffer is empty. It is possible, in rare cases, that the last byte of a packet may remain in the buffer even though the RXB1 IRQ flag has cleared. This can ONLY happen on the last byte of a packet and only if the packet data is being read out of the buffer while the packet is still being received. The flag is trustworthy under all other conditions, and for all bytes prior to the last. When using RXB1 IRQ and unloading the packet data during reception, the user should be sure to check the RX_COUNT_ADR value after the RXC IRQ/RXE IRQ is set and unload the last remaining bytes if the number of bytes unloaded is less than the reported count, eventhough the RXB1 IRQ is not set.
Receive Buffer Error Interrupt Status. This IRQ is triggered in one of two ways: (1) When the receive buffer is empty and there is an attempt to read data. (2) When the receive buffer is full and more data is received. This flag is cleared when RX GO is set and a SOP is received.
Packet Receive Complete Interrupt Status. This IRQ is triggered when a packet has been received. If transaction mode is enabled, then this bit is not set until after transmission of the ACK. If transaction mode is not enabled then this bit is set as soon as a valid packet is received. This bit is cleared when this register is read. RXC IRQ and RXE IRQ flags may change value at different times in response to a single event. There are cases when this bit is not triggered when ACK EN = 1 and there is an error in reception. Therefore, firmware should examine RXC IRQ, RXE IRQ, and CRC 0 to determine receive status. If the first read of this register returns RXC IRQ = 1 and RXE IRQ = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of RXE IRQ. If the first read of this register returns RXC IRQ = 1 and RXE IRQ
= 1 then the firmware must not execute a second read to this register for a given transaction.
Receive Error Interrupt Status. This IRQ is triggered when there is an error in reception. It is triggered whenever a packet is received with a bad CRC16, an unexpected EOP is detected, a packet type (data or ACK) mismatch, or a packet is dropped because the receive buffer is still not empty when the next packet starts. The exact cause of the error may be determined by reading RX_STATUS_ADR. This bit is cleared when this register is read.
Document #: 38-16015 Rev. *F Page 17 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
-
R
RX ACK
6
-
R
PKT ERR
RX_STATUS_ADR
5
-
R
EOP ERR
4
-
R
CRC0
3
-
R
Bad CRC
2
-
R
RX Code
Address
1
-
R R
RX Data Mode
0
-
0x08
It is expected that firmware does not read this register until after RX GO self clears. Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7 RX Packet Type. This bit is set when the received packet is an ACK packet, and cleared when the received packet is a standard packet.
Bit 6
Bit 5
Receive Packet Type Error. This bit is set when the packet type received is what not was expected and cleared when the packet type received was as expected. For example, if a data packet is expected and an ACK is received, this bit will be set.
Unexpected EOP. This bit is set when an EOP is detected before the expected data length and CRC16 fields have been received. This bit is cleared when SOP pattern for the next packet has been received. This includes the case where there are invalid bits detected in the length field and the length field is forced to 0.
Bit 4
Bit 3
Bit 2
Bits 1:0
Zero-seed CRC16. This bit is set whenever the CRC16 of the last received packet has a zero seed.
Bad CRC16. This bit is set when the CRC16 of the last received packet is incorrect.
Receive Code Length. This bit indicates the DATA_CODE_ADR code length used in the last correctly received packet. 1 = 64chip code, 0 = 32-chip code.
Receive Data Mode. These bits indicate the data mode of the last correctly received packet. 00 = 1-Mbps GFSK 01 = 8DR 10 =
DDR. 11 = Not Valid. These bits do not apply to unframed packets.
Mnemonic
Bit
Default
Read/Write
7
0
R
6
0
R
RX_COUNT_ADR
Function
Count bits are non-atomic (updated at different times).
5
0
R
Bits 7:0
4
0
R
RX Count
3
0
R
2
0
R
Address
1
0
R
0
0
R
0x09
This register contains the total number of payload bytes received during reception of the current packet. After packet reception is complete, this register will match the value in RX_LENGTH_ADR unless there was a packet error. This register is cleared when RX_LENGTH_ADR is automatically loaded, if length is enabled, after the SOP. Count should not be read when
RX_GO=1 during a transaction.
Mnemonic
Bit
Default
Read/Write
7
0
R
6
0
R
RX_LENGTH_ADR
5
0
R
4
0
R
3
0
R
2
0
R
Address
1
0
R
0
0
R
0x0A
Function RX Length
Length bits are non-atomic (different flags may change value at different times in response to a single event).
Bits 7:0 This register contains the length field which is updated with the reception of a new length field (shortly after start of packet detected). If there is an error in the received length field, 0x00 is loaded instead, except when using GFSK datarate, and an error is flagged.
Document #: 38-16015 Rev. *F Page 18 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bit 7
Bit 6
Bit 5
Bits 3:2
Bits 1:0
7
1
R/W
PMU EN
6
0
R/W
PWR_CTRL_ADR
5
LVIRQ EN
1
R/W
PMU SEN
4
-
-
Not Used
3
0
R/W
2
0
R/W
Address
1
0
R/W
0
0
0x0B
PMU OUTV
R/W
LVI TH
Power Management Unit (PMU) Enable. Setting this bit enables the PMU. When the PMU is disabled, or if the PMU is enabled and the V
BAT
voltage is above the value set in Bits 1:0 of this register, the V
REG
PMU is enabled and the V
BAT not less than the value set by PMU OUTV.
pin is internally connected to the V
voltage is below the value set by PMU OUTV, then the PMU will boost the V
REG
BAT
pin. if the pin to a voltage
Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the V
BAT
voltage falls below the threshold set by LVI TH, then a low voltage interrupt will be generated. The LVI is not available when the device is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
PMU Sleep Mode Enable. If this bit is set, the PMU will continue to operate normally when the device is in sleep mode. If this bit is not set, then the PMU is disabled when the device is in sleep mode. In this case, if V
BAT
is below the PMU OUTV voltage and
PMU EN is set, when the device enters sleep mode the V
REG
voltage falls to the V
BAT
voltage as the V
REG capacitors discharge.
Low Voltage Interrupt Threshold. This field sets the voltage on V
BAT
at which the LVI is triggered. 11 = 1.8V; 10 = 2.0V;
01 = 2.2V; 00 = PMU OUTV voltage.
PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V; 10 = 2.5V; 01 = 2.6V; 00 = 2.7V. When the PMU is active, the voltage output by the PMU on V
REG will never be less than this voltage provided that the total load on the
V
REG
pin is less than the specified maximum value, and the voltage in V
BAT
is greater than the specified minimum value.
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:6
Bit 5
Bits 2:0
7
0
R/W
XOUT FN
6
0
R/W
XTAL_CTRL_ADR
5
0
R/W
XSIRQ EN
4
-
-
Not Used
3
-
-
Not Used
2
1
R/W
Address
1
0
R/W
FREQ
0
0
0x0C
R/W
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire mode then the MISO pin will output a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to
GPIO mode, and set the GPIO state in IO_CFG_ADR.
Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event when the crystal has stabilized after the device has woken from sleep mode. This event is cleared by writing zero to this bit.
XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz; 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
Document #: 38-16015 Rev. *F Page 19 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
0
R/W
IRQ OD
6
0
R/W
IRQ POL
IO_CFG_ADR
5
0
R/W
MISO OD
4
0
R/W
XOUT OD
3
0
R/W
PACTL OD
2
0
R/W
PACTL GPIO
Address
1
0
R/W
SPI 3PIN
0
0
R/W
0x0D
IRQ GPIO
To use a GPIO pin as an input, the output mode must be set to open drain, and a “1” written to the corresponding output register bit.
Bit 7 IRQ Pin Drive Strength. Setting this bit configures the IRQ pin as an open drain output. Clearing this bit configures the IRQ pin as a standard CMOS output, with the output “1” drive voltage being equal to the V
IO pin voltage.
Bit 6 IRQ Polarity. Setting this bit configures the IRQ signal polarity to be active HIGH. Clearing this bit configures the IRQ signal polarity to be active low.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MISO Pin Drive Strength. Setting this bit configures the MISO pin as an open drain output. Clearing this bit configures the
MISO pin as a standard CMOS output, with the output “1” drive voltage being equal to the V
IO
pin voltage.
XOUT Pin Drive Strength. Setting this bit configures the XOUT pin as an open drain output. Clearing this bit configures the
XOUT pin as a standard CMOS output, with the output “1” drive voltage being equal to the V
IO
pin voltage.
PACTL Pin Drive Strength. Setting this bit configures the PACTL pin as an open drain output. Clearing this bit configures the
PACTL pin as a standard CMOS output, with the output “1” drive voltage being equal to the V
IO
pin voltage.
PACTL Pin Function. When this bit is set the PACTL pin is available for use as a GPIO.
SPI Mode. When this bit is cleared, the SPI interface acts as a standard 4-wire SPI Slave interface. When this bit is set, the SPI interface operates in “3-Wire Mode” combining MISO and MOSI on the same pin (SDAT), and the MISO pin is available as a
GPIO pin.
Bit 0 IRQ Pin Function. When this bit is cleared, the IRQ pin is asserted when an IRQ is active; the polarity of this IRQ signal is configurable in IRQ POL. When this bit is set, the IRQ pin is available for use as a GPIO pin, and the IRQ function is multiplexed onto the MOSI pin. In this case the IRQ signal state is presented on the MOSI pin whenever the SS signal is inactive (HIGH).
Mnemonic
Bit
Default
Read/Write
Function
7
0
R/W
XOUT OP
6
0
R/W
GPIO_CTRL_ADR
MISO OP
5
0
R/W
PACTL OP
4
0
R/W
IRQ OP
3
-
R
XOUT IP
2
-
R
MISO IP
Address
1
-
R
PACTL IP
0
-
R
0x0E
IRQ IP
To use a GPIO pin as an input, the output mode must be set to open drain, and a “1” written to the corresponding output register bit.
Bit 7 XOUT Output. When the XOUT pin is configured to be a GPIO, the state of this bit sets the output state of the XOUT pin.
Bit 6
Bit 5
Bit 4
MISO Output. When the MISO pin is configured to be a GPIO, the state of this bit sets the output state of the MISO pin.
PACTL Output. When the PACTL pin is configured to be a GPIO, the state of this bit sets the output state of the PACTL pin.
IRQ Output. When the IRQ pin is configured to be a GPIO, the state of this bit sets the output state of the IRQ pin.
Bit 3
Bit 2
Bit 1
Bit 0
XOUT Input. The state of this bit reflects the voltage on the XOUT pin.
MISO Input. The state of this bit reflects the voltage on the MISO pin.
PACTL Input. The state of this bit reflects the voltage on the PACTL pin.
IRQ Input. The state of this bit reflects the voltage on the IRQ pin.
Document #: 38-16015 Rev. *F Page 20 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bit 7
Bit 5
Bits 4:2
Bits 1:0
7
1
R/W
ACK EN
6
-
-
Not Used
XACT_CFG_ADR
5
0
R/W
FRC END
4
0
R/W
3
0
R/W
END STATE
2
0
R/W
Address
1
0
R/W
ACK TO
0
0
R/W
0x0F
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the end of packet transmission. This bit affects both transmitting and receiving devices.
Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit is automatically cleared upon completion. Firmware MUST never try to force END STATE while TX GO is set, nor when RX GO is set and a SOP has already been received (packet reception already in progress).
Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000
= Sleep Mode; 001 = Idle Mode; 010 = Synth Mode (TX); 011 = Synth Mode (RX); 100 = RX Mode. In normal use, this field will typically be set to 000 or 001 when the device is transmitting packets, and 100 when the device is receiving packets. Note that when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the device can begin receiving data. If the system only support packets <=16 bytes then firmware should examine RXC IRQ and
RXE IRQ to determine the status of the packet. If the system supports packets > 16 bytes ensure that END STATE is not sleep, force RXF=1, perform receive operation, force RXF=0, and if necessary set END STATE back to sleep.
ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period is this value multiplied by 64
µs and if SOP LEN is cleared then the timeout is this value multiplied by 32 µs. 00 = 4x; 01 = 8x,
10 = 12x; 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for
8DR) + Preamble Length + SOP Code Length (x2).
Mnemonic
Bit
Default
Read/Write
Function
Bit 7
Bit 6
Bit 5
Bits 4:0
7
1
R/W
SOP EN
FRAMING_CFG_ADR
6 5
0
R/W
SOP LEN
1
R/W
LEN EN
4
0
R/W
3
0
R/W
2
1
R/W
SOP TH
Address
1
0
R/W
0
1
R/W
0x10
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid
SOP field will be received. If this bit is cleared, no SOP field will be generated when a packet is transmitted, and packet reception will begin whenever two successive correlations against the DATA_CODE_ADR code are detected.
SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the
SOP_CODE_ADR code length is 32 chips.
Packet Length Enable. When this bit is set the 8-bit value contained in TX_LENGTH_ADR is transmitted immediately after the
SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (LEN EN setting is ignored). GFSK requires user set LEN EN = 1.
SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There is a single threshold for the SOP_CODE_ADR code. This threshold is applied independently to each of SOP1 and SOP2 fields.
When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Document #: 38-16015 Rev. *F Page 21 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:4
Bits 3:0
7
-
-
Not Used
-
-
DATA32_THOLD_ADR
6 5
Not Used
-
-
Not Used
4
-
-
Not Used
3
0
R/W
2
1
R/W
Address
1
0
R/W
0
0
R/W
TH32
Not Used.
32 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when DATA
CODE LENGTH (see TX_CFG_ADR) is set to 32. Typical applications configure TH32 = 05h.
0x11
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:5
Bits 4:0
7
-
-
Not Used
-
-
DATA64_THOLD_ADR
6 5
Not Used
-
-
Not Used
4
0
R/W
3
1
R/W
2
0
R/W
TH64
Address
1
1
R/W
0
0
R/W
0x12
Not Used.
64 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when the DATA
CODE LENGTH (see TX_CFG_ADR) is set to 64. Typical applications configure TH64 = 0Eh.
Mnemonic
Bit
Default
Read/Write
Function
7
0
R
SOP
6
-
-
Not Used
RSSI_ADR
5
1
R
LNA
4
0
R
3
0
R
2
0
R
RSSI
Address
1
0
R
0
0
R
0x13
A Received Signal Strength Indicator (RSSI) reading is taken automatically when an SOP symbol is detected. In addition, an RSSI reading is taken whenever RSSI_ADR is read. The contents of this register are not valid after the device is configured for receive mode until either a SOP symbol is detected, or the register is (re)read. The conversion can occur as often as once every 12-
µs. The approximate slope of the curve is
1.9 dB/count, but is not guaranteed.
If it is desired to measure the background RF signal strength on a channel before a packet has been received then the MCU should perform a “dummy” read of this register, the results of which should be discarded. This “dummy” read will cause an RSSI measurement to be taken, and therefore subsequent readings of the register will yield valid data.
Bit 7 SOP RSSI Reading. When set, this bit indicates that the reading in the RSSI field was taken when a SOP symbol was detected. When cleared, this bit indicates that the reading stored in the RSSI field was triggered by a previous SPI read of this register.
Bit 5 LNA State. This bit indicates the LNA state when the RSSI reading was taken. When cleared, this bit indicates that the LNA was disabled when the RSSI reading was taken; if set this bit indicates that the LNA was enabled when the RSSI reading was taken.
Bits 4:0 RSSI Reading. This field indicates the instantaneous strength of the RF signal being received at the time that the RSSI reading was taken. A larger value indicates a stronger signal. The signal strength measured is for the RF signal on the configured channel, and is measured after the LNA stage.
Document #: 38-16015 Rev. *F Page 22 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
1
R/W
HEN
6
0
R/W
EOP_CTRL_ADR
5
1
R/W
HINT
4
0
R/W
3
0
R/W
2
1
R/W
EOP
Address
1
0
R/W
0
0
R/W
0x14
If the LEN EN bit is set, then the contents of this register have no effect. If the LEN EN bit is cleared, then this register is used to configure how an EOP (end of packet) condition is detected.
Bit 7 EOP Hint Enable. When set, this bit will cause an EOP to be detected if no correlations have been detected for the number of symbol periods set by the HINT field and the last two received bytes match the calculated CRC16 for all previously received bytes. Use of this mode reduces the chance of non-correlations in the middle of a packet from being detected as an EOP condition.
Bits 6:4
Bits 4:0
EOP Hint Symbol Count. The minimum number of symbols of consecutive non-correlations at which the last two bytes are checked against the calculated CRC16 to detect an EOP condition.
EOP Symbol Count. An EOP condition is deemed to exist when the number of consecutive non-correlations is detected.
Mnemonic
Bit
Default
Read/Write
Function
7
0
R/W
CRC_SEED_LSB_ADR
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
CRC SEED LSB
2
0
R/W
Address
1
0
R/W
0
0
R/W
0x15
The CRC16 seed allows different devices to generate or recognize different CRC16s for the same payload data. If a transmitter and receiver use a randomly selected CRC16 seed, the probability of correctly receiving data intended for a different receiver is 1/65535, even if the other transmitter/receiver are using the same SOP_CODE_ADR codes and channel.
Bits 7:0 CRC16 Seed Least Significant Byte. The LSB of the starting value of the CRC16 calculation.
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:0
7
0
R/W
CRC_SEED_MSB_ADR
6
0
R/W
5
0
R/W
4
0
3
0
R/W R/W
CRC SEED MSB
2
0
R/W
CRC16 Seed Most Significant Byte. The MSB of the starting value of the CRC16 calculation.
Address
1
0
R/W
0
0
R/W
0x16
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:0
7
-
R
6
-
R
TX_CRC_LSB_ADR
5
-
R
4
-
R
TX CRC LSB
3
-
R
2
-
R
Address
1
-
R
0
-
R
0x17
Calculated CRC16 LSB. The LSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after packet transmission is complete.
Document #: 38-16015 Rev. *F Page 23 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:0
7
-
R
6
-
R
TX_CRC_MSB_ADR
5
-
R
4
-
R
TX CRC MSB
R
3
-
2
-
R
Address
1
-
R
0
-
R
0x18
Calculated CRC16 MSB. The MSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after packet transmission is complete.
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:0
7
1
R
6
1
R
RX_CRC_LSB_ADR
5
1
R
4
1
R
RX CRC LSB
R
3
1
2
1
R
Address
1
1
R
0
1
R
0x19
Received CRC16 LSB. The LSB of the CRC16 field extracted from the last received packet. This value is valid whether or not the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:0
7
1
R
6
1
R
RX_CRC_MSB_ADR
5
1
R
4
1
R
RX CRC MSB
R
3
1
2
1
R
Address
1
1
R
0
1
R
0x1A
Received CRC16 MSB. The MSB of the CRC16 field extracted from the last received packet. This value is valid whether or not the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic
Bit
Default
Read/Write
Function
7
0
R/W
TX_OFFSET_LSB_ADR
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
Address
1
0
R
0
0
R
0x1B
STRIM LSB
Bits 7:0 The least significant 8 bits of the synthesizer offset value. This is a 12-bit 2’s complement signed number which may be used to offset the transmit frequency of the device by up to ±1.5 MHz. A positive value increases the transmit frequency, and a negative value reduces the transmit frequency. A value of +1 increases the transmit frequency by 732.6 Hz; a value of –1 decreases the transmit frequency by 732.6 Hz. A value of 0x0555 increases the transmit frequency by 1 MHz; a value of 0xAAB decreases the transmit frequency by 1 MHz. Typically, this register is loaded with 0x55 during initialization. Typically this feature is used to avoid the need to change the synthesizer frequency when switching between TX and RX. As the IF = 1 MHz the RX frequency is offset 1 MHz from the synthesizer frequency; therefore, transmitting with a 1 MHz offset allows the same synthesizer frequency to be used for both transmit and receive.
Synthesizer offset has no effect on receive frequency.
Document #: 38-16015 Rev. *F Page 24 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:4
Bits 3:0
7
-
-
Not Used
TX_OFFSET_MSB_ADR
6
-
-
Not Used
5
-
-
Not Used
4
-
-
Not Used
3
0
R/W
2
0
Address
R/W
STRIM MSB
1
0
R/W
Not Used.
The most significant 4 bits of the synthesizer trim value. Typically, this register is loaded with 0x05 during initialization.
0
0
R/W
0x1C
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:6
Bit 5
Bits 4:3
Bits 2:1
Bit 0
7
0
W
RSVD
MODE_OVERRIDE_ADR
6 5
0
W
RSVD
0
W
FRC SEN
4
0
W
FRC AWAKE
3
0
W
2
-
-
Not Used
Address
1
-
-
Not Used
0
0
0x1D
W
RST
Reserved. Must be zero.
Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate correctly, the oscillator must be running before this bit is set.
Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times regardless of the END STATE setting. Clearing both of these bits disables this function.
Not Used.
Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect.
Mnemonic
Bit
Default
Read/Write
Function
7
0
R/W
ACK RX
6
0
RX_OVERRIDE_ADR
R/W
5
0
R/W
4
0
R/W
RXTX DLY MAN RXACK FRC RXDR
3
0
R/W
DIS CRC0
2
0
R/W
DIS RXCRC
Address
1
0
R/W
ACE
0
-
-
0x1E
Not Used
This register provides the ability to over-ride some automatic features of the device.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the given channel when automatically entering receive mode.
When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20
µs.
Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an
ACK packet at the data rate defined in TX_CFG_ADR.
Force Receive Data Rate. When this bit is set, the receiver will ignore the data rate encoded in the SOP symbol, and will receive data at the data rate defined in TX_CFG_ADR.
Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR.
Bit 2
Bit 1
Bit 0
The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 will be treated as payload data and stored in the receive buffer.
Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in
CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16.
Not Used.
Document #: 38-16015 Rev. *F Page 25 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
0
R/W
ACK TX
6
0
TX_OVERRIDE_ADR
R/W
FRC PRE
5
0
R/W
RSVD
4
0
R/W
MAN TXACK
3
0
R/W
OVRD ACK
2
0
R/W
DIS TXCRC
Address
1
0
R/W
RSVD
0
0
R/W
0x1F
TX INV
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the ability to over-ride some automatic features of the device.
Bit 7 When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the given channel when automatically entering transmit mode.
Bit 6
Bit 5
Force Preamble. When this bit is set, the device will transmit a continuous repetition of the preamble pattern (see
PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Firmware should set bit
RST of MODE_OVERRIDE_ADR to exit this mode.
Reserved. Must be zero.
Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set.
ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet.
Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets.
Reserved. Must be zero.
TX Data Invert. When this bit is set the transmit bitstream is inverted.
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
RSVD
6
0
W
RSVD
XTAL_CFG_ADR
5
0
W
RSVD
4
0
W
RSVD
3
0
W
START DLY
2
0
W
RSVD
Address
1
0
W
RSVD
0
0
W
0x26
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:4 Reserved. Must be zero.
Bit 3
Bits 2:0
Crystal Startup Delay. Setting this bit, sets the crystal startup delay to 150uSec to handle warm restarts of the crystal. Firmware
MUST set this bit during initialization.
Reserved. Must be zero.
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
RSVD
CLK_OVERRIDE_ADR
6
0
W
RSVD
5
0
W
RSVD
4
0
W
RSVD
3
0
W
RSVD
2
0
W
RSVD
Address
1
0
W
RXF
This register provides the ability to override some automatic features of the device.
Bits 7:2
Bit 1
Bit 0
Reserved. Must be zero.
Force Receive Clock. Streaming applications MUST set this bit during receive mode, otherwise this bit is cleared.
Reserved. Must be zero.
0x27
0
0
W
RSVD
Document #: 38-16015 Rev. *F Page 26 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
RSVD
6
0
W
RSVD
CLK_EN_ADR
5
0
W
RSVD
4
0
W
RSVD
3
0
W
RSVD
2
0
W
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:2 Reserved. Must be zero.
Bit 1
Bit 0
Force Receive Clock Enable. Streaming applications MUST set this bit during initialization.
Reserved. Must be zero.
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
AUTO_CAL_OFFSET_ADR
6
0
W
5
0
W
4
0
W
3
0
W
AUTO_CAL_OFFSET
This register provides the ability to override some automatic features of the device.
Bits 7:0 Auto Cal Offset. Firmware MUST write 14h to this register during initialization.
2
0
W
Address
1
0
W
RXF
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
RSVD
6
0
W
RSVD
RX_ABORT_ADR
5
0
W
ABORT EN
4
0
W
RSVD
3
0
W
RSVD
2
0
W
RSVD
Address
1
0
W
RSVD
0
0
W
0x29
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:6
Bit 5
Bits 4:0
Reserved. Must be zero.
Receive Abort Enable. Typical applications will disrupt any pending receive by first setting this bit, otherwise this bit is cleared.
Reserved. Must be zero.
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
AUTO_CAL_TIME_ADR
6
0
W
5
0
W
4
0
W
3
0
W
AUTO_CAL_TIME
This register provides the ability to override some automatic features of the device.
Bits 7:0 Auto Cal Time. Firmware MUST write 3Ch to this register during initialization.
2
0
W
Address
1
1
W
0
1
W
0x32
Address
1
0
W
0
0
W
RSVD
0
0
W
0x28
0x35
Document #: 38-16015 Rev. *F Page 27 of 39
CYRF6936
Mnemonic
Bit
Default
Read/Write
Function
7
0
W
RSVD
ANALOG_CTRL_ADR
6
0
W
RSVD
5
0
W
RSVD
4
0
W
RSVD
3
0
W
RSVD
2
0
W
RSVD
Address
1
0
W
RX INV
0
0
W
0x39
ALL SLOW
This register provides the ability to override some automatic features of the device.
Bits 7:2
Bit 1
Reserved. Must be zero.
Receive Invert. When set, the incoming receive data is inverted. Firmware MUST set this bit when interoperability with first generation devices is desired.
Bit 0 All Slow. When set, the synth settling time for all channels is the same as for slow channels. It is recommended that firmware set this bit when using GFSK data rate mode.
Document #: 38-16015 Rev. *F Page 28 of 39
CYRF6936
Register Files
Files are written to or read from using non-incrementing burst read or write transactions. In most cases accessing a file may be destructive; the file must be completely read/written, otherwise the contents may be altered. When accessing file registers, the bytes are presented to the bus least significant byte first.
Mnemonic
Length
Default
TX_BUFFER_ADR
16 Bytes
0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Address
R/W
0x20
W
The transmit buffer is a FIFO. Writing to this file adds a byte to the packet being sent. Writing more bytes to this file than the packet length in
TX_LENGTH_ADR will have no effect, and these bytes will be lost. The FIFO accumulates data until it is reset via TX CLR in TX_CTRL_ADR.
A previously sent packet, of 16 bytes or less, can be transmitted if TX_GO is set without resetting the FIFO. The contents of TX_BUFFER_ADR is not affected by the transmission of an Auto ACK.
Mnemonic
Length
RX_BUFFER_ADR
16 Bytes
Address
R/W
0x21
R
Default
0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The receive buffer is a FIFO. Received bytes may be read from this file register at any time that it is not empty, but when reading from this file register before a packet has been completely received care must be taken to ensure that error packets (for example with bad CRC16) are handled correctly.
When the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if the receive buffer is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overwritten by a newly received packet while this file register is being read.
When the VLD EN bit in RX_CFG_ADR is set, the bytes in this file register alternate—the first byte read is data, the second byte is a valid flag for each bit in the first byte, the third byte is data, the fourth byte valid flags, etc. In SDR and DDR modes the valid flag for a bit is set if the correlation coefficient for the bit exceeded the correlator threshold, and is cleared if it did not. In 8DR mode, the MSB of a valid flags byte indicates whether or not the correlation coefficient of the corresponding received symbol exceeded the threshold. The seven LSBs contain the number of erroneous chips received for the data.
Mnemonic
Length
SOP_CODE_ADR
8 Bytes
Address
R/W
0x22
R/W
Default
0x17FF9E213690C782
When using 32 chip SOP_CODE_ADR codes, only the first four bytes of this register are used; in order to complete the file write process, these four bytes must be followed by four bytes of “dummy” data. However, a class of codes known as “multiplicative codes” may be used; there are
64 chip codes with good auto-correlation and cross-correlation properties where the least significant 32 chips themselves have good autocorrelation and cross-correlation properties when used as 32-chip codes. In this case the same eight-byte value may be loaded into this file and used for both 32 chip and 64 chip SOP symbols.
When reading this file, all eight bytes must be read; if fewer than eight bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well.
Recommended SOP Codes:
0x91CCF8E291CC373C
0x0FA239AD0FA1C59B
0x2AB18FD22AB064EF
0x507C26DD507CCD66
0x44F616AD44F6E15C
0x46AE31B646AECC5A
0x3CDC829E3CDC78A1
0x7418656F74198EB9
0x49C1DF6249C0B1DF
0x72141A7F7214E597
Document #: 38-16015 Rev. *F Page 29 of 39
CYRF6936
Mnemonic DATA_CODE_ADR
Length
Default
16 Bytes
0x02F9939702FA5CE3012BF1DB0132BE6F
In GFSK mode, this file register is ignored.
Address
R/W
In 64-SDR mode, only the first eight bytes are used.
In 32-DDR mode, only eight bytes are used. The format for these eight bytes: 0x00000000BBBBBBBB00000000AAAAAAAA, where “0” represents unused locations. Example: 0x00000000B2BB092B00000000B86BC0DC; where “B86BC0DC” represents AAAAAAAA,
“00000000“ represents unused locations, “B2BB092B“ represents BBBBBBBB, and “00000000“ represents unused locations.
In 64-DDR and 8DR modes, all sixteen bytes are used.
0x23
R/W
When reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well.
Certain sixteen-byte sequences have been calculated that provide excellent auto-correlation and cross-correlation properties, and it is recommended that such sequences be used; the default value of this register is one such sequence. In typical applications, all devices use the same
DATA_CODE_ADR codes, and devices and systems are addressed by using different SOP_CODE_ADR codes; in such cases it may never be necessary to change the contents of this register from the default value.
Typical applications should use the default code.
Mnemonic
Length
Default
PREAMBLE_ADR
3 Bytes
0x333302
Address
R/W
0x24
R/W
1st byte – The number of repetitions of the preamble sequence that are to be transmitted. The preamble may be disabled by writing 0x00 to this byte.
2nd byte – Least significant eight chips of the preamble sequence
3rd byte – Most significant eight chips of the preamble sequence
If using 64-SDR to communicate with CYWUSB69xx devices, set number of repetitions to four for optimum performance
When reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well.
Mnemonic
Length
Default
MFG_ID_ADR
6 Bytes
NA
Address
R
0x25
R
To minimize ~190
µA of current consumption (default), execute a “dummy” single-byte SPI write to this address with a zero data stage after the contents have been read. Non-zero to enable reading of fuses. Zero to disable reading fuses.
Document #: 38-16015 Rev. *F Page 30 of 39
CYRF6936
10.0
Absolute Maximum Ratings
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with Power Applied ..–55°C to +125°C
Supply Voltage on any power supply pin relative to V
SS to +3.9V
–0.3V
DC Voltage to Logic Inputs
................... –0.3V to V
IO
+0.3V
DC Voltage applied to Outputs in High-Z State .. –0.3V to V
IO
+0.3V
Static Discharge Voltage (Digital)
............................>2000V
Static Discharge Voltage (RF)
................................. 1100V
Latch-up Current......................................+200 mA, –200 mA
11.0
Operating Conditions
V
CC
.....................................................................2.4V to 3.6V
V
IO
......................................................................1.8V to 3.6V
V
BAT
....................................................................1.8V to 3.6V
T
A
(Ambient Temperature Under Bias) ............. 0°C to +70°C
Ground Voltage.................................................................. 0V
F
OSC
(Crystal Frequency)............................ 12MHz ±30 ppm
12.0
DC Characteristics
(T = 25
°C, V
BAT
= 2.4V, PMU disabled, f
OSC
= 12.000000MHz)
Parameter
V
BAT
V
V
V
REG
REG
IO
V
CC
V
OH1
V
OH2
V
OL
V
IH
V
IL
I
IL
C
IN
I
CC
(GFSK)
I
CC
(32-8DR)
I
SB
I
SB
IDLE I
CC
I synth
TX I
CC
TX I
CC
TX I
CC
RX I
CC
RX I
CC
Boost Eff
Description
Battery Voltage
PMU Output Voltage
PMU Output Voltage
V
IO
Voltage
V
CC
Voltage
Output High Voltage condition 1
Output High Voltage condition 2
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
0–70
2.4V mode
2.7V mode
0–70
°C
°C
At I
OH
= –100.0 µA
At I
OH
= –2.0 mA
At I
OL
= 2.0 mA
0 < V
IN
< V
IO
Pin Input Capacitance except XTAL, RF
N
, RF
P
, RF
BIAS
Average TX Icc, 1Mbps, slow channel PA = 5, 2-way, 4-bytes/10 ms
Average TX Icc, 250kbps, fast channel PA = 5, 2-way, 4-bytes/10 ms
Sleep Mode Icc
Sleep Mode Icc
Radio off, XTAL Active
I
CC
during Synth Start
I
CC
during Transmit
I
CC
during Transmit
I
CC
during Transmit
I
CC
during Receive
I
CC
during Receive
PMU Boost Converter Efficiency
PMU enabled
XOUT disabled
PA = 5 (–5 dBm)
PA = 6 (0 dBm)
PA = 7 (+4 dBm)
LNA off, ATT on
LNA on, ATT off
V
BAT
I
LOAD
Conditions
= 2.5V, V
REG
= 20 mA
= 2.73V,
Min.
1.8
Typ.
Max.
Unit
3.6
V
2.4
2.7
0.7V
IO
0
–1
2.43
2.73
1.8
2.4
V
IO
– 0.2
V
IO
V
IO
– 0.4
V
IO
0
0.26
3.6
3.6
0.45
V
IO
0.3V
IO
+1
10
V
V
V
V
V
V
µA
V
V
V
3.5
0.87
1.2
pF mA mA
10 0.8
31.4
1.0
8.4
20.8
26.2
34.1
µA
µA mA mA mA mA mA
18.4
21.2
81 mA mA
%
Notes
5. It is permissible to connect voltages above V
IO
to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.
6. Human Body Model (HBM).
7. V
REG depends on battery input voltage.
8. In sleep mode, the I/O interface voltage reference is V
9. In sleep mode, V
CC
BAT
.
min. can go as low as 1.8v
10. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving
ACK handshake. Device is in sleep except during this transaction.
11. ISB is not guaranteed if any I/O pin is connected to voltages higher than V
IO
.
Document #: 38-16015 Rev. *F Page 31 of 39
CYRF6936
SCK nSS
MOSI input
MISO
MOSI output
12.0
Parameter
I
LOAD_EXT
I
LOAD_EXT
DC Characteristics
(T = 25
°C, V
BAT
= 2.4V, PMU disabled, f
OSC
= 12.000000MHz)
(continued)
Description Conditions
Average PMU External Load current V
BAT
= 1.8V, V
REG
= 2.73V,
0–50
°C, RX Mode
Average PMU External Load current V
BAT
= 1.8V, V
REG
50–70
°C, RX Mode
= 2.73V,
Min.
Typ.
Max.
Unit
15 mA
10 mA
13.0
AC Characteristics
Table 13-1. SPI Interface
[12]
Parameter
t
SCK_CYC t
SCK_HI t
SCK_LO t
DAT_SU t
DAT_HLD t
DAT_VAL t
DAT_VAL_TRI t
SS_SU t
SS_HLD t
SS_PW t
SCK_SU t
SCK_HLD t
RESET
SPI Clock Period
SPI Clock High Time
SPI Clock Low Time
SPI Input Data Set-up Time
Description
SPI Input Data Hold Time
SPI Output Data Valid Time
SPI Output Data Tri-state (MOSI from Slave Select Deassert)
SPI Slave Select Set-up Time before first positive edge of SCK
SPI Slave Select Hold Time after last negative edge of SCK
SPI Slave Select Minimum Pulse Width
SPI Slave Select Set-up Time
SPI SCK Hold Time
Minimum RST pin pulse width
Figure 13-1. SPI Timing
Min.
238.1
100
100
25
10
0
10
10
20
10
10
10
Typ.
Max.
Unit
ns ns ns
50
20 ns ns ns ns ns ns ns ns ns ns t
SCK_HI t
SCK_SU t
SS_SU t
DAT_SU t
DAT_HLD t
SCK_CYC t
SCK_LO t
SS_HLD t
SCK_HLD t
DAT_VAL t
DAT_VAL_TRI
Notes
12. AC values are not guaranteed if voltage on any pin exceed V
IO
.
13. C
LOAD
= 30 pF.
14. SCK must start low at the time SS goes low, otherwise the success of SPI transactions are not guaranteed.
Document #: 38-16015 Rev. *F Page 32 of 39
CYRF6936
14.0
RF Characteristics
Table 14-1. Radio Parameters
Parameter Description
RF Frequency Range
Receiver
(T = 25°C, V
CC
= 3.0V, f
OSC
= 12.000000MHz, BER < 1E-3)
Sensitivity 125kbps 64-8DR BER 1E-3
Conditions
Sensitivity 250-kbps 32-8DR
Sensitivity
Sensitivity GFSK
LNA gain
BER 1E-3
CER 1E-3
BER 1E-3, ALL SLOW = 1
ATT gain
Maximum Received Signal
RSSI value for PWR in
–60 dBm
RSSI slope
Interference Performance
(CER 1E-3)
Co-channel Interference rejection
Carrier-to-Interference (C/I)
Adjacent (±1 MHz) channel selectivity C/I 1 MHz
Adjacent (±2 MHz) channel selectivity C/I 2 MHz
LNA On
LNA On
C = –60 dBm
C = –60 dBm
C = –60 dBm
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz C = –67 dBm
Out-of-Band Blocking 30 MHz–12.75 MHz
C = –67 dBm
Intermodulation C = –64 dBm,
∆ f = 5,10 MHz
Receive Spurious Emission
800 MHz
1.6 GHz
3.2 GHz
Transmitter
(T = 25°C, V
CC
= 3.0V)
Maximum RF Transmit Power
Maximum RF Transmit Power
Maximum RF Transmit Power
Maximum RF Transmit Power
RF Power Control Range
RF Power Range Control Step Size
Frequency Deviation Min
Frequency Deviation Max
Error Vector Magnitude (FSK error)
Occupied Bandwidth
Transmit Spurious Emission
(PA = 7)
In-band Spurious Second Channel Power (±2 MHz)
In-band Spurious Third Channel Power (>3 MHz)
100-kHz ResBW
100-kHz ResBW
100-kHz ResBW
PA = 7
PA = 6
PA = 5
PA = 0 seven steps, monotonic
PN Code Pattern 10101010
PN Code Pattern 11110000
>0 dBm
–6 dBc, 100-kHz ResBW
+2
–2
–7
500
–79
–71
–65
39
5.6
270
323
4
0
–5
–35
10
876
–38
–44
Min.
2.400
Typ.
–80
–15
–97
–93
–87
–84
22.8
–31.7
–6
21
1.9
Max.
2.497
Unit
GHz dBm dBm dBm dBm dB dB dBm
Count dB/Count
9
3
–30
–38
–30
–36 dB dB dB dB dBm dBm
+6
+2
–3 dBm dBm dBm dBm dBm dBm dBm dB dB kHz kHz
%rms kHz dBm dBm
Notes
15. Subject to regulation.
16. Exceptions F/3 & 5C/3.
Document #: 38-16015 Rev. *F Page 33 of 39
CYRF6936
Table 14-1. Radio Parameters (continued)
Parameter Description
Non-Harmonically Related Spurs (800MHz)
Non-Harmonically Related Spurs (1.6GHz)
Non-Harmonically Related Spurs (3.2GHz)
Harmonic Spurs (Second Harmonic)
Harmonic Spurs (Third Harmonic)
Fourth and Greater Harmonics
Power Management
(Crystal PN# eCERA GF-1200008)
Crystal start to 10ppm
Crystal start to IRQ
Synth Settle
Synth Settle
Synth Settle
Link turn-around time
Link turn-around time
Link turn-around time
Link turn-around time
Max. packet length
Max. packet length
Conditions
XSIRQ EN = 1
Slow channels
Medium channels
Fast channels
GFSK
250 kbps
125 kbps
<125 kbps
<60ppm crystal-to-crystal all modes except 64-DDR
<60ppm crystal-to-crystal
64-DDR
Min.
Typ.
–38
–34
–47
–43
–48
–59
0.7
0.6
Max.
1.3
62
94
31
40
270
180
100
30
16
µs
µs
µs
µs ms ms
µs
µs
µs bytes bytes
Unit
dBm dBm dBm dBm dBm dBm
Document #: 38-16015 Rev. *F Page 34 of 39
CYRF6936
15.0
0
-2
-4
-6
6
4
2
-8
-10
-12
-14
0
Typical Operating Characteristics
Transmit Power vs. Temperature
(Vcc = 2.7v)
Transmit Power vs. Vcc
(PMU off)
PA7
PA6
PA5
PA4
20 40
Temp (deg C)
60
6
0
-2
4
2
-4
-6
-8
-10
-12
-14
2.4
2.6
2.8
PA7
PA6
PA5
PA4
3
Vcc
3.2
3.4
3.6
Typical RSSI Count vs Input Power
18
16
14
12
10
8
6
4
2
0
0
32
24
16
LNA ON
LNA OFF
ATT ON
LNA OFF
8
0
-120 -100 -80 -60 -40
Input Power (dBm)
-20
RSSI vs. Channel
(Rx signal = -70dBm)
20 40
Channel
60 80
Average RSSI vs. Temperature
(Rx signal = -70dBm)
19
18
17
16
15
14
13
12
0 20 40
Temp (deg C)
60
Rx Sensitivity vs. Vcc
(1Mbps CER)
-80
-82
-84
-86
-88
-90
-92
-94
2.4
CER
8DR32
2.6
2.8
3
Vcc
3.2
3.4
3.6
Receiver Sensitivity vs. Frequency Offset
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-150
GFSK
DDR32
8DR64
-100 -50 0 50
Crystal Offset (ppm)
100 150
-81
-83
-85
-87
-89
-91
-93
-95
0
Receiver Sensitivity vs Channel
(3.0v, Room Temp)
GFSK
CER
20
DDR32
8DR32
40
Channel
60 80
0
-2
-4
-6
-8
6
4
2
-10
-12
-14
0
Transmit Power vs. Channel
PA7
PA6
20
PA5
PA4
40
Channel
60 80
Average RSSI vs. Vcc
(Rx signal = -70dBm)
17
16
15
14
13
20
19
18
12
11
10
2.4
2.6
2.8
3
Vcc
3.2
3.4
3.6
-80
-82
-84
-86
-88
-90
-92
-94
0
Rx Sensitivity vs. Temperature
(1Mbps CER)
CER
8DR32
20 40
Temp (deg C)
60
20.0
10.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-10
Carrier to Interferer
(Narrow band, LP modulation)
-5 0
Channel Offset (MHz)
5 10
Note
17. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read, cross-checking RSSI with LNA off/on is recommended for accurate readings.
Document #: 38-16015 Rev. *F Page 35 of 39
CYRF6936
BER vs. Data Threshold (32-DDR)
(SOP Threshold = 5, C38 slow)
10
1
0.1
0.01
0.001
0.0001
6
3
1
0
0.00001
-100 -95 -90 -85 -80
Input Power (dBm)
-75 -70
ICC RX
(LNA OFF)
21
20.5
20
19.5
3.3V
3.0V
2.7V
2.4V
19
18.5
18
17.5
17
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX SYNTH
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
0
3.3V
3.0V
2.7V
2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA2
18
17.5
17
16.5
3.3V
3.0V
2.7V
2.4V
16
15.5
15
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
BER vs. Data Threshold (32-8DR)
(SOP Threshold = 5, C38 slow)
10
0 Thru 7
1
0.1
0.01
0.001
0.0001
0.00001
-100 -95 -90 -85 -80
Input Power (dBm)
-75 -70
ICC RX
(LNA ON)
25
24.5
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
0
3.3V
3.0V
2.7V
2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA0
17
16.5
16
15.5
3.3V
3.0V
2.7V
2.4V
15
14.5
14
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA3
19
18.5
18
3.3V
3.0V
2.7V
2.4V
17.5
17
16.5
16
15.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
GFSK vs. BER
(SOP Threshold = 5, C38 slow)
100
10
1
0.1
0.01
0.001
0.0001
0.00001
-100 -80 -60
GFSK
-40
Input Power (dBm)
-20 0
ICC RX SYNTH
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
0
3.3V
3.0V
2.7V
2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA1
17.5
17
16.5
16
3.3V
3.0V
2.7V
2.4V
15.5
15
14.5
14
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA4
20.5
20
19.5
19
18.5
18
3.3V
3.0V
2.7V
2.4V
17.5
17
16.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Document #: 38-16015 Rev. *F Page 36 of 39
CYRF6936
ICC TX @ PA5
23.5
23
22.5
22
21.5
21
20.5
20
3.3V
3.0V
2.7V
2.4V
19.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA6
30
29.5
29
28.5
28
27.5
27
26.5
26
25.5
25
24.5
0
3.3V
3.0V
2.7V
2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA7
40.5
40
39.5
39
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
32.5
3.3V
3.0V
2.7V
2.4V
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
16.0
AC Test Loads and Waveforms for Digital Pins
Figure 16-1. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Max
Parameter
R1
R2
R
TH
V
TH
V
CC
1071
937
500
1.4
3.00
Unit
Ω
Ω
Ω
V
V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
Typical
DC Test Load
V
CC
OUTPUT
R1
R2
V
CC
ALL INPUT PULSES
90%
10%
GND
Rise time: 1 V/ns
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
R
TH
V
TH
90%
10%
Fall time: 1 V/ns
17.0
Ordering Information
Table 17-1. Ordering Information
Part Number
CYRF6936-40LFXC
Radio
Transceiver
Package Name
40 QFN
Package Type Operating Range
40 Quad Flat Package No Leads Lead-Free Commercial
Document #: 38-16015 Rev. *F Page 37 of 39
CYRF6936
18.0
Package Description
Figure 18-1. 40-pin Lead-Free QFN 6x6 mm LY40
TOP VIEW SIDE VIEW
A
N
5.90[0.232]
6.10[0.240]
5.70[0.224]
5.80[0.228]
0.60[0.024]
DIA.
1
2
1.00[0.039] MAX.
0.80[0.031] MAX.
0.08[0.003] C
0.05[0.002] MAX.
0.20[0.008] REF.
0°-12°
C
SEATING
PLANE
0.30[0.012]
0.50[0.020]
BOTTOM VIEW
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0.18[0.007]
0.28[0.011]
N
1
2
PIN1 ID
0.20[0.008] R.
0.45[0.018]
0.24[0.009]
0.60[0.024]
(4X)
4.45[0.175]
4.55[0.179]
0.50[0.020]
51-85190-**
The recommended dimension of the PCB pad size for the E-
PAD underneath the QFN is 3.5 mm × 3.5 mm (width x length).
This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or technical support regarding Cypress WirelessUSB products please contact Cypress at www.cypress.com. WirelessUSB, PSoC, and enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-16015 Rev. *F Page 38 of 39
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYRF6936
Document History Page
Description Title: CYRF6936 WirelessUSB™ LP 2.4GHz Radio SoC
Document Number: 38-16015
REV.
ECN NO. Issue Date
Orig. of
Change
**
*A
307437
377574
See ECN
See ECN
TGE
TGE
New data sheet
Description of Change
Preliminary release–
- updated Section 1.0 - Features
- updated Section 2.0 - Applications
- added Section 3.0 - Applications Support
- updated Section 4.0 - Functional Descriptions
- updated Section 5.0 - Pin Description
- added Figure 5-1
- updated Section 6.0 - Functional Overview
- added Section 7.0 - Functional Block Overview
- added Section 9.0 - Register Descriptions
- updated Section 10.0 - Absolute Maximum Ratings
- updated Section 11.0 - Operating Conditions
- updated Section 12.0 - DC Characteristics
- updated Section 13.0 - AC Characteristics
- updated Section 14.0 - RF Characteristics
- added Section 16.0 - Ordering Information
*B 398756 See ECN TGE
*C
*D
412778
435578
See ECN
See ECN
TGE
TGE
ES-10 update-
- changed part no.
- updated Section 9.0 - Register Descriptions
- updated Section 12.0 - DC Characteristics
- updated Section 14.0 - RF Characteristics
ES-10 update-
- updated Section 4.0 - Functional Descriptions
- updated Section 5.0 - Pin Descriptions
- updated Section 6.0 - Functional Overview
- updated Section 7.0 - Functional Block Overview
- updated Section 9.0 - Register Descriptions
- updated Section 10.0 - Absolute Maximum Ratings
- updated Section 11.0 - Operating Conditions
- updated Section 14.0 - RF Characteristics
- updated Section 1.0 - Features
- updated Section 5.0 - Pin Descriptions
- updated Section 6.0 - Functional Overview
- updated Section 7.0 - Functional Block Overview
- updated Section 9.0 - Register Descriptions
- added Section 10.0 - Recommended Radio Circuit Schematic
- updated Section 11.0 - Absolute Maximum Ratings
- updated Section 12.0 - Operating Conditions
- updated Section 13.0 - DC Characteristics
- updated Section 14.0 - AC Characteristics
- updated Section 15.0 - RF Characteristics
*E
*F
460458
487261
See ECN
See ECN
BOO
TGE
Final data sheet - removed “Preliminary” notation
- updated Section 1.0 - Features
- updated Section 5.0 - Pin Descriptions
- updated Section 6.0 - Functional Overview
- updated Section 7.0 - Functional Block Overview
- updated Section 8.0 - Application Example
- updated Section 9.0 - Register Descriptions
- updated Section 12.0 - DC Characteristics
- updated Section 13.0 - AC Characteristics
- updated Section 14.0 - RF Characteristics
- added Section 15.0 - Typical Operating Characteristics
Document #: 38-16015 Rev. *F Page 39 of 39
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