Data Sheet | Cypress Semiconductor CY8C21234 Datasheet

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

PSoC

®

Programmable System-on-Chip™

PSoC® Programmable System-on-Chip™

Features

❐

❐

❐

❐

■ Powerful Harvard-architecture processor

❐

M8C processor speeds up to 24 MHz

Low power at high speed

Operating voltage: 2.4 V to 5.25 V

Operating voltages down to 1.0 V using on-chip switch mode pump (SMP)

Industrial temperature range: –40 °C to +85 °C

■ Advanced peripherals (PSoC

®

blocks)

❐ Four analog Type E PSoC blocks provide:

• Two comparators with digital-to-analog converter (DAC) references

❐

❐

• Single or dual 10-bit 28 channel analog-to-digital converters (ADC)

Four digital PSoC blocks provide:

• 8- to 32-bit timers, counters, and pulse width modulators

(PWMs)

• Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules

• Full-duplex universal asynchronous receiver transmitter

(UART), serial peripheral interface (SPI) master or slave

• Connectable to all general purpose I/O (GPIO) pins

Complex peripherals by combining blocks

❐

❐

❐

❐

■ Flexible on-chip memory

❐

❐

8 KB flash program storage 50,000 erase/write cycles

512 bytes static random access memory (SRAM) data storage

In-system serial programming (ISSP)

Partial flash updates

Flexible protection modes

EEPROM emulation in flash

❐

❐

❐

❐

❐

■ Complete development tools

Free development software (PSoC Designer™)

Full-featured, in-circuit emulator (ICE) and programmer

Full-speed emulation

Complex breakpoint structure

128-KB trace memory

■ Precision, programmable clocking

❐ Internal ±2.5% 24- / 48-MHz main oscillator

[1]

❐ Internal oscillator for watchdog and sleep

■ Programmable pin configurations

❐

❐

25-mA sink, 10-mA source on all GPIOs

Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs

❐

❐

Up to eight analog inputs on GPIOs

Configurable interrupt on all GPIOs

■

❐

❐

❐

Versatile analog mux

Common internal analog bus

Simultaneous connection of I/O combinations

Capacitive sensing application capability

■ Additional system resources

❐ I

2

C

[2]

master, slave, and multi-master to 400 kHz

❐

❐

Watchdog and sleep timers

User-configurable low-voltage detection (LVD)

❐

❐

Integrated supervisory circuit

On-chip precision voltage reference

Logic Block Diagram

Errata: For information on silicon errata, see

“Errata” on page 48. Details include trigger conditions, devices affected, and proposed workaround.

Notes

1. Errata : The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

2. Errata mode.

:The I 2 C block exhibits occasional data and bus corruption errors when the I 2 C master initiates transactions while the device is transitioning in to or out of sleep

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 38-12025 Rev. AB

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised July 25, 2013

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Contents

PSoC Functional Overview .............................................. 3

The PSoC Core ........................................................... 3

The Digital System ...................................................... 3

The Analog System ..................................................... 4

Additional System Resources ..................................... 4

PSoC Device Characteristics ...................................... 5

Getting Started .................................................................. 5

Application Notes ........................................................ 5

Development Kits ........................................................ 5

Training ....................................................................... 5

CYPros Consultants .................................................... 5

Solutions Library .......................................................... 5

Technical Support ....................................................... 5

Development Tools .......................................................... 6

PSoC Designer Software Subsystems ........................ 6

Designing with PSoC Designer ....................................... 7

Select User Modules ................................................... 7

Configure User Modules .............................................. 7

Organize and Connect ................................................ 7

Generate, Verify, and Debug ....................................... 7

Pin Information ................................................................. 8

16-pin Part Pinout ........................................................ 8

Pin Definitions ............................................................. 8

20-pin Part Pinout ........................................................ 9

Pin Definitions ............................................................. 9

28-pin Part Pinout ...................................................... 10

Pin Definitions ........................................................... 10

32-pin Part Pinout ...................................................... 11

Pin Definitions ........................................................... 12

56-pin Part Pinout ...................................................... 13

Pin Definitions ........................................................... 13

Register Reference ......................................................... 15

Register Conventions ................................................ 15

Register Mapping Tables .......................................... 15

Absolute Maximum Ratings .......................................... 18

Operating Temperature .................................................. 18

Electrical Specifications ................................................ 19

DC Electrical Characteristics ..................................... 19

AC Electrical Characteristics ..................................... 25

Packaging Information ................................................... 33

Thermal Impedances ................................................. 37

Solder Reflow Specifications ..................................... 37

Development Tool Selection ......................................... 38

Software .................................................................... 38

Development Kits ...................................................... 38

Evaluation Tools ........................................................ 38

Device Programmers ................................................. 39

Accessories (Emulation and Programming) .............. 39

Ordering Information ...................................................... 40

Ordering Code Definitions ......................................... 41

Acronyms ........................................................................ 42

Reference Documents .................................................... 42

Document Conventions ................................................. 43

Units of Measure ....................................................... 43

Numeric Conventions ................................................ 43

Glossary .......................................................................... 43

Errata ............................................................................... 48

Part Numbers Affected .............................................. 48

CY8C21234 Qualification Status ............................... 48

CY8C21234 Errata Summary .................................... 49

Document History Page ................................................. 50

Sales, Solutions, and Legal Information ...................... 53

Worldwide Sales and Design Support ....................... 53

Products .................................................................... 53

PSoC® Solutions ...................................................... 53

Cypress Developer Community ................................. 53

Technical Support ..................................................... 53

Document Number: 38-12025 Rev. AB Page 2 of 53

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory,

SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

The PSoC architecture, shown in Figure 1 , consists of four main

areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow combining all of the device resources into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects.

The PSoC Core

The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (IMO) and internal low speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to

24 MHz

[3]

. The M8C is a four-million instructions per second

(MIPS) 8-bit Harvard-architecture microprocessor.

System resources provide these additional capabilities:

■ Digital clocks for increased flexibility

■ I

2

C

[4]

functionality to implement an I

2

C master and slave

■ An internal voltage reference, multi-master, that provides an absolute value of 1.3 V to a number of PSoC subsystems

■ A SMP that generates normal operating voltages from a single battery cell

■ Various system resets supported by the M8C

The digital system consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIOs through a series of global buses. These buses can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller.

The analog system consists of four analog PSoC blocks, supporting comparators, and analog-to-digital conversion up to

10 bits of precision.

The Digital System

The digital system consists of four digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include:

■

PWMs (8- to 32-bit)

■

PWMs with dead band (8- to 32-bit)

■

Counters (8- to 32-bit)

■

Timers (8- to 32-bit)

■

UART 8- with selectable parity

■

Serial peripheral interface (SPI) master and slave

■

I

2

C slave and multi-master

[4]

■

CRC/generator (8-bit)

■

IrDA

■

PRS generators (8-bit to 32-bit)

The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family

resources are shown in Table 1 on page 5

.

Figure 1. Digital System Block Diagram

Port 3 Port 1

Port 2 Port 0

Digital Clocks

From Core

To System Bus

To Analog

System

DIGITAL SYSTEM

Digital PSoC Block Array

Row 0 4

DBB00 DBB01 DCB02 DCB03

4

8

8

8

8

GIE[7:0]

GIO[7:0]

Global Digital

Interconnect

GOE[7:0]

GOO[7:0]

Notes

3. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

4. Errata: mode.

The I 2 C block exhibits occasional data and bus corruption errors when the I 2 C master initiates transactions while the device is transitioning in to or out of sleep


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

The Analog System

The analog system consists of four configurable blocks that allow for the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are:

■

ADCs (single or dual, with 8-bit or 10-bit resolution)

■

Pin-to-pin comparator

■

Single-ended comparators (up to two) with absolute (1.3 V) reference or 8-bit DAC reference

■

1.3-V reference (as a system resource)

In most PSoC devices, analog blocks are provided in columns of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks. The CY8C21x34 devices provide limited functionality Type E analog blocks. Each column contains one

CT Type E block and one SC Type E block. Refer to the PSoC

Technical Reference Manual for detailed information on the

CY8C21x34’s Type E analog blocks.

Figure 2. Analog System Block Diagram

Array Input

Configuration

X

X

X

X

All I/O

X

ACI0[1:0] ACI1[1:0]

ACOL1MUX

Analog Mux Bus

ACE00

Array

ACE01

ASE10 ASE11

The Analog Multiplexer System

The analog mux bus can connect to every GPIO pin. Pins may be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.

Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Track pad, finger sensing

■ Chip-wide mux that allows analog input from any I/O pin

■ Crosspoint connection between any I/O pin combinations

Additional System Resources

System resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a switch-mode pump, low-voltage detection, and power-on-reset (POR).

■

Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■

The I

2

C

[5]

supported.

module provides 100- and 400-kHz communication over two wires. Slave, master, and multi-master modes are all

■

LVD interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor.

■

An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs.

■

An integrated switch-mode pump generates normal operating voltages from a single 1.2-V battery cell, providing a low cost boost converter.

■

Versatile analog multiplexer system.

Note

5. Errata: The I mode.

2 C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4

analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in Table 1

.

Table 1. PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C28xxx

Digital

I/O up to 64 up to 44

Digital

Rows

Digital

Blocks

Analog

Inputs

4 16 up to 12 up to 3 up to 12 up to 44

CY8C27x43

CY8C24x94

CY8C24x23A

CY8C23x33

CY8C22x45

CY8C21x45

CY8C21x34

CY8C21x23

CY8C20x34

CY8C20xx6 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36

1

0

1

1

0

2

1

2

1

1

4

0

4

4

0

8

4

8

4

4 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36

Analog

Outputs

4 up to 4

0

0

0

0

0

4

2

0

2

2

Analog

Columns

4 up to 6

2

0

4

2

0

4

2

4

2

2

Analog

Blocks

12 up to

12 + 4

[6]

12

6

6

4

6

[6]

6

[6]

4

[6]

4

[6]

3

[6,7]

3

[6,7]

SRAM

Size

2 K

1 K

256

1 K

256

256

1 K

512

512

256

512 up to 2 K

Flash

Size

32 K

16 K

16 K

16 K

4 K

8 K

16 K

8 K

8 K

4 K

8 K up to 32 K

Getting Started

For in-depth information, along with detailed programming details, see the PSoC

®

Technical Reference Manual .

For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web.

Application Notes

Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs.

Development Kits

PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and

Newark.

Training

Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com

, covers a wide variety of topics and skill levels to assist you in your designs.

CYPros Consultants

Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a

PSoC consultant go to the CYPros Consultants web site.

Solutions Library

Visit our growing library of solution focused designs . Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.

Technical Support

Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical

Support hotline at 1-800-541-4736.

Notes

6. Limited analog functionality .

7. Two analog blocks and one CapSense

®

.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Development Tools

PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes:

■

Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration

■

Extensive user module catalog

■

Integrated source-code editor (C and assembly)

■

Free C compiler with no size restrictions or time limits

■

Built-in debugger

■

In-circuit emulation

■

Built-in support for communication interfaces:

❐

❐

Hardware and software I

Full-speed USB 2.0

2

C

[8]

slaves and masters

❐

Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless

PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7.

PSoC Designer Software Subsystems

Design Entry

In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are ADCs, DACs, amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project.

This prepopulates your project with APIs and libraries that you can use to program your application.

The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC’s resources for an application.

Code Generation Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two.

Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Debugger

PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support Forum to aid the designer.

In-Circuit Emulator

A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices.

The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24 MHz) operation.

Note

8. Errata: The I mode.

2

C block exhibits occasional data and bus corruption errors when the I

2

C master initiates transactions while the device is transitioning in to or out of sleep


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Designing with PSoC Designer

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.

The PSoC development process is summarized in four steps:

1. Select User Modules .

2. Configure User Modules.

3. Organize and Connect.

4. Generate, Verify, and Debug.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple.

Configure User Modules

Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM

User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design.

Organize and Connect

You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate

Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces

(APIs) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed.

A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both.

The last step in the development process takes place inside

PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events.

These include monitoring address and data bus values, memory locations, and external signals.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Pin Information

The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, V

Digital I/O.

SS

, V

DD

, SMP, and XRES are not capable of

16-pin Part Pinout

Figure 3. CY8C21234 16-pin PSoC Device

A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

SMP

V

SS

M, I2C SCL, P1[1]

V

SS

4

5

6

7

8

1

2

3

SOIC

16

15

14

13

12

11

10

9

V

DD

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

P1[4], EXTCLK, M

P1[2], M

P1[0], I2C SDA, M

Pin Definitions

CY8C21234 16-pin SOIC

7

8

9

10

3

4

1

2

5

6

Pin No.

11

12

13

14

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Digital

Power

Power

I/O

Power

Type

Analog

I, M

I, M

I, M

I, M

M

M

M

M

I, M

I, M

I, M

P0[7]

P0[5]

P0[3]

P0[1]

SMP

V

SS

P1[1]

V

SS

P1[0]

P1[2]

P1[4]

P0[0]

P0[2]

P0[4]

Name

Analog column mux input


Description

Analog column mux input, integrating input


Switch-mode pump (SMP) connection to required external components

Ground connection

I

2

C serial clock (SCL), ISSP-SCLK

[9]

Ground connection

I

2

C serial data (SDA), ISSP-SDATA

[9]

Optional external clock input (EXTCLK)




15 I/O I, M P0[6] Analog column mux input

16 Power V

DD

Supply voltage

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Note

9. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234



A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

V

SS

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

V

SS

8

9

10

6

7

4

5

1

2

3

SSOP

17

16

15

14

13

12

20

19

18

11

V

DD

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

XRES

P1[6], M

P1[4], EXTCLK, M

P1[2], M

P1[0], I2C SDA, M

Pin Definitions

CY8C21334 20-pin SSOP

Pin No.

Type

Analog

I, M

I, M

I, M

I, M

M

M

M

M

Name





Ground connection

I

2

C SCL

I

2

C SDA

Description

11

12

13

14

7

8

9

10

5

6

3

4

1

2

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Power

Digital

I/O

I/O

I/O

I/O

Power

I/O

P0[7]

P0[5]

P0[3]

P0[1]

V

SS

P1[7]

P1[5]

P1[3]

P1[1]

V

SS

P1[0]

P1[2]

P1[4]

P1[6]

I

2

C SCL, ISSP-SCLK

[10]

Ground connection.

I

2

C SDA, ISSP-SDATA

[10]

M

M

M

M


15

16

17

18

Input

I/O

I/O

I/O

I, M

I, M

I, M

XRES Active high external reset with internal pull-down

P0[0]

P0[2]

P0[4]





20 Power V

DD

Supply voltage

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Note

10. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234



A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

V

SS

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

V

SS

10

11

7

8

9

12

13

14

1

2

3

4

5

6

SSOP

22

21

20

19

18

17

16

15

25

24

23

28

27

26

V

DD

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

P2[6], M

P2[4], M

P2[2], M

P2[0], M

XRES

P1[6], M

P1[4], EXTCLK, M

P1[2], M

P1[0], I2C SDA, M

Pin Definitions


1

2

3

4

7

8

9

5

6

10

11

12

13

14

15

16

17

18

Pin No.

I/O

Digital

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Power

I/O

I/O

I/O

I/O

Power

I/O

I/O

I/O

I/O

Type

I, M

I, M

I, M

I, M

M

M

I, M

I, M

M

M

M

M

Analog

Name

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

V

SS

P1[7]

P1[5]

P1[3]

P1[1]

V

SS

P1[0]

P1[2]

I

I


Description

Analog column mux input and column output

Analog column mux input and column output, integrating input


Direct switched capacitor block input


Ground connection

2

2

C SCL

C SDA

I

2

C SCL, ISSP-SCLK

[11]

Ground connection

I

2

C SDA, ISSP-SDATA

[11]

M

M

M

M

P1[4]

P1[6]


19

20

21

22

23

24

25

26

Input

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I, M

I, M

M

M

I, M

I, M

I, M

XRES

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

Active high external reset with internal pull-down







28 Power V

DD

Supply voltage

LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.

Note

11. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.




CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234


Figure 8. CY8C21434 32-pin Sawn PSoC Device Sawn Figure 9. CY8C21634 32-pin Sawn PSoC Device Sawn

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

M, P3[3]

M, P3[1]

M, I2C SCL, P1[7]

1

2

3

4

5

6

7

8

QFN

(Top View)

24

23

22

21

20

19

18

17

P0[0], A, I, M

P2[6], M

P2[4], M

P2[2], M

P2[0], M

P3[2], M

P3[0], M

XRES

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

SMP

Vss

M, I2C SCL, P1[7]

4

5

6

7

8

1

2

3

QFN

(Top View)

24

23

22

21

20

19

18

17

P0[0], A, I, M

P2[6], M

P2[4], M

P2[2], M

P2[0], M

P3[2], M

P3[0], M

XRES


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Pin Definitions

CY8C21434/CY8C21634 32-pin QFN

[12]

Pin No.

6

7

7

8

3

4

1

2

5

6

13

14

15

16

9

10

11

12

Digital

I/O

I/O

I/O

I/O

I/O

I/O

Power

I/O

Power

I/O

I/O

I/O

I/O

Power

Type

Analog

I, M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

P3[3]

SMP

P3[1]

V

SS

Name

P1[7]

P1[5]

P1[3]

P1[1]

V

SS

P1[0]

P1[2]

P1[4]

P1[6]

Description


In CY8C21434 part

SMP connection to required external components in CY8C21634 part

I

I

In CY8C21434 part

Ground connection in CY8C21634 part

2

2

C SCL

C SDA

I

2

C SCL, ISSP-SCLK

[13]

Ground connection

I

2

C SDA, ISSP-SDATA

[13]

17

18

19

20

I/O

I/O

I/O

I/O

Input

I/O

I/O

I/O

M

M

M

XRES

P3[0]

P3[2]

P2[0]



21

22

23

24

25

26

27

28

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Power

M

M

M

I, M

I, M

I, M

I, M

P2[2]

P2[4]

P2[6]

P0[0]

29

30

I/O

I/O

I, M

I, M

P0[2]

P0[4]

P0[6]

V

DD

P0[7]

P0[5]





Supply voltage



31 I/O I, M P0[3] Analog column mux input, integrating input

32 Power V

SS

Ground connection

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Notes

12. The center pad on the QFN package must be connected to ground (V

SS

) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal.

13. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234


The 56-pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.


V ss

V ss

P3[3]

P3[1]

N C

N C

I2C SC L, P1[7]

I2C S DA , P1[5]

NC

P1[3]

SC LK, I2C SC L, P1[1]

V ss

V ss

A I, P0[7]

A I, P0[5]

A I, P0[3]

A I, P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

NC

NC

N C

NC

O CD E

O C DO

S M P

11

12

13

14

15

16

17

18

19

20

21

22

23

9

10

7

8

5

6

3

4

1

2

24

25

26

27

28

SSO P

40

39

38

37

36

35

34

44

43

42

41

50

49

48

47

46

45

56

55

54

53

52

51

33

32

31

30

29

N C

P 3[2]

P 3[0]

C C LK

H C LK

XRE S

N C

N C

N C

N C

N C

V dd

P 0[6], AI

P 0[4], AI

P 0[2], AI

P 0[0], AI

P 2[6]

P 2[4]

P 2[2]

P 2[0]

N C

N C

P 1[6]

P 1[4], EXTC LK

P 1[2]

P 1[0], I2C S D A , SDA TA

N C

N C

10

11

12

13

14

15

6

7

8

9

16

17

18

19

1

2

3

4

5

Pin Definitions


Pin No.

I/O

I/O

I/O

I/O

I/O

I/O

Digital

Power

I/O

I/O

Type

I

I

I

I

I

I

Analog

OCD

OCD

Power

Power

Power

I/O

Pin Name

NC

NC

NC

NC

OCDE

OCDO

SMP

V

SS

V

SS

P3[3]

V

SS

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Description

Ground connection







No connection. Pin must be left floating




OCD even data I/O

OCD odd data output

SMP connection to required external components

Ground connection

Ground connection


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

50

51

52

53

46

47

48

49

54

55

56

42

43

44

45

38

39

40

41

34

35

36

37

30

31

32

33

26

27

28

29

20

21

22

23

24

25

Pin Definitions

(continued)


Pin No.

I/O

Digital

Type

Analog

I/O

I/O

I/O

I/O

Power

I/O

I/O

I/O

I/O

Input

OCD

OCD

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Power

I

I

I

I

I

I

Pin Name

NC

NC

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

NC

NC

NC

XRES

HCLK

CCLK

P3[0]

P3[2]

P0[4]

P0[6]

V

DD

NC

P1[0]

P1[2]

P1[4]

P1[6]

NC

NC

NC

P3[1]

NC

NC

P1[7]

P1[5]

NC

P1[3]

P1[1]

V

SS

NC



I

2

C SCL

I

2

C SDA


I

I

FMTEST

2

C SCL, ISSP-SCLK

[14]

Ground connection



I

2

C SDA, ISSP-SDATA

[14]

V

FMTEST









OCD high-speed clock output

OCD CPU clock output





Supply voltage

Description



LEGEND : A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.

Note

14. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Register Reference

This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, see the PSoC Technical Reference

Manual.

Register Conventions

The register conventions specific to this section are listed in Table 2

.

Table 2. Register Conventions

R

C

#

W

L

Convention Description

Read register or bit(s)

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the

XOI bit is set to 1, the user is in Bank 1.

Note In the following register mapping tables, blank fields are reserved and must not be accessed.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 3. Register Map 0 Table: User Space

Name

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

17

18

19

1A

13

14

15

16

0F

10

11

12

0B

0C

0D

0E

1F

20

21

22

23

1B

1C

1D

1E

07

08

09

0A

03

04

05

06

Addr (0,Hex) Access

00 RW

01

02

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

#

W

RW

#

Name

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

AMX_IN

AMUXCFG

PWM_CR

30

31

32

33

2C

2D

2E

2F

28

29

2A

2B

24

25

26

27

38

39

3A

3B

3C

34

35

36

37

#

W

RW

#

#

W

RW

#

#

W

RW

#

CMP_CR0

CMP_CR1

ADC0_CR

ADC1_CR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACE00CR1

ACE00CR2

ACE01CR1

ACE01CR2

3D

3E

3F

Blank fields are reserved and must not be accessed.

57

58

59

5A

53

54

55

56

4F

50

51

52

4B

4C

4D

4E

5F

60

61

62

63

5B

5C

5D

5E

47

48

49

4A

43

44

45

46


40

41

42

RW

RW

RW

#

70

71

72

73

6C

6D

6E

6F

68

69

6A

6B

64

65

66

67

78

79

7A

7B

7C

74

75

76

77

7D

7E

7F

RW

#

#

RW

RW

RW

RW

RW

RW

RW

RW

Name

ASE10CR0

ASE11CR0

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

BD

BE

BF

# Access is bit specific.

B0

B1

B2

B3

AC

AD

AE

AF

A8

A9

AA

AB

A4

A5

A6

A7

B8

B9

BA

BB

BC

B4

B5

B6

B7

97

98

99

9A

93

94

95

96

8F

90

91

92

8B

8C

8D

8E

9F

A0

A1

A2

A3

9B

9C

9D

9E

87

88

89

8A

83

84

85

86


80 RW

81

82

RW

RW

RW

RW

RW

RW

RW

RW

Name

CUR_PP

STK_PP

IDX_PP

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

INT_CLR3

INT_MSK3

INT_MSK0

INT_MSK1

INT_VC

RES_WDT

DEC_CR0

DEC_CR1

CPU_F

DAC_D

CPU_SCR1

CPU_SCR0


F0

F1

F2

F3

EC

ED

EE

EF

E8

E9

EA

EB

E4

E5

E6

E7

F8

F9

FA

FB

FC

F4

F5

F6

F7

FD

FE

FF

D7

D8

D9

DA

D3

D4

D5

D6

CF

D0

D1

D2

CB

CC

CD

CE

DF

E0

E1

E2

E3

DB

DC

DD

DE

C7

C8

C9

CA

C3

C4

C5

C6


C0

C1

C2

RW

RW

RW

RW

RW

RW

RC

W

RW

RW

RW

RW

#

RW

#

RW

RW

RW

RW

RL

RW

#

#

Page 16 of 53

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 4. Register Map 1 Table: Configuration Space

Name

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

17

18

19

1A

13

14

15

16

0F

10

11

12

0B

0C

0D

0E

1F

20

21

22

23

1B

1C

1D

1E

07

08

09

0A

03

04

05

06


00 RW

01

02

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Name

DBB00FN

DBB00IN

DBB00OU

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN DBB01FN

DBB01IN

DBB01OU

DCB02FN

DCB02IN

DCB02OU

DCB03FN

DCB03IN

DCB03OU

30

31

32

33

2C

2D

2E

2F

28

29

2A

2B

24

25

26

27

38

39

3A

3B

3C

34

35

36

37

RW

RW

RW

RW

RW

RW

RW

RW

RW

AMD_CR1

ALT_CR0

CLK_CR3

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACE00CR1

ACE00CR2

ACE01CR1

ACE01CR2

3D

3E

3F

Blank fields are reserved and must not be accessed.

57

58

59

5A

53

54

55

56

4F

50

51

52

4B

4C

4D

4E

5F

60

61

62

63

5B

5C

5D

5E

47

48

49

4A

43

44

45

46


40

41

42

RW

RW

RW

RW

RW

70

71

72

73

6C

6D

6E

6F

68

69

6A

6B

64

65

66

67

78

79

7A

7B

7C

74

75

76

77

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

7D

7E

7F

Name

ASE10CR0

ASE11CR0

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

B0

B1

B2

B3

AC

AD

AE

AF

A8

A9

AA

AB

A4

A5

A6

A7

B8

B9

BA

BB

BC

B4

B5

B6

B7

BD

BE

BF

# Access is bit specific.

97

98

99

9A

93

94

95

96

8F

90

91

92

8B

8C

8D

8E

9F

A0

A1

A2

A3

9B

9C

9D

9E

87

88

89

8A

83

84

85

86


80 RW

81

82

RW

RW

RW

RW

RW

RW

RW

RW

Name

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

VLT_CMP

ADC0_TR

ADC1_TR

IMO_TR

ILO_TR

BDG_TR

ECO_TR

CPU_F

FLS_PR1

DAC_CR

CPU_SCR1

CPU_SCR0


D7

D8

D9

DA

D3

D4

D5

D6

CF

D0

D1

D2

CB

CC

CD

CE

DF

E0

E1

E2

E3

DB

DC

DD

DE

C7

C8

C9

CA

C3

C4

C5

C6


C0

C1

C2

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

R

RW

RW

F0

F1

F2

F3

EC

ED

EE

EF

E8

E9

EA

EB

E4

E5

E6

E7

F8

F9

FA

FB

FC

F4

F5

F6

F7

W

W

RW

W

RL

RW

FD

FE

FF

RW

#

#

Page 17 of 53

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Absolute Maximum Ratings

Symbol

T

STG

Description

Storage temperature

T

BAKETEMP

Bake temperature t

BAKETIME

Bake time

T

A

V

DD

V

IO

V

IOZ

I

MIO

ESD

LU

Ambient temperature with power applied

Supply voltage on V

DD

relative to V

SS

DC input voltage

DC voltage applied to tri-state

Maximum current into any port pin

Electrostatic discharge voltage

Latch-up current

Min

–55

–

See package label

–40

–0.5

V

SS

– 0.5

V

SS

– 0.5

–25

2000

–

Typ

25

125

–

Max

+100

Units

°C

Notes

Higher storage temperatures reduce data retention time.

Recommended storage temperature is +25 °C ± 25 °C.

Extended duration storage temperatures above 65 °C degrade reliability.

°C See package label

72 Hours

–

–

–

–

–

–

–

+85

+6.0

V

DD

+ 0.5

V

DD

+ 0.5

+50

–

200

°C

V

V

V mA

V mA

Human body model ESD.

Operating Temperature

Symbol

T

A

T

J

Description

Ambient temperature

Junction temperature

Min

–40

–40

Typ

–

–

Max

+85

+100

Units

°C

°C

Notes

The temperature rise from ambient to junction is package specific. See

Table

29 on page 37 . You must limit the

power consumption to comply with this requirement.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up-to-date electrical specifications, visit the Cypress web site at http://www.cypress.com

.

Specifications are valid for –40 C  T

A

 85 C and T

J

 100 C as specified, except where noted.

Refer to

Table 16 on page 25 for the electrical specifications for the IMO using SLIMO mode.

Figure 11. Voltage versus CPU Frequency Figure 14. IMO Frequency Trim Options

5.25

5.25

SLIMO

Mode=1

SLIMO

Mode=0

4.75

O

R eg pe io n ra

Va lid tin g

4.75

3.60

3.00

3.00

SLIMO

Mode=1

SLIMO

Mode=1

SLIMO

Mode=1

SLIMO

Mode=0

2.40

2.40

93 kHz 3 MHz 12 MHz

CPU Frequency

24 MHz 93 kHz 6 MHz 12 MHz

IMO Frequency

24 MHz

DC Electrical Characteristics

DC Chip-Level Specifications

Table 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

A

 85 °C, respectively. Typical parameters

Table 5. DC Chip-level Specifications

Symbol

V

DD

I

DD

Description

Supply voltage

Supply current, IMO = 24 MHz

I

DD3

I

DD27

I

SB27

Supply current, IMO = 6 MHz using

SLIMO mode.

Supply current, IMO = 6 MHz using

SLIMO mode.

Min

2.40

–

–

–

–

Typ

–

3

1.2

1.1

2.6

Max

5.25

4

2

1.5

4

Units Notes

V See

Table 13 on page 23

mA Conditions are V

T

DD

= 5.0 V,

A

= 25 °C, CPU = 3 MHz,

48 MHz disabled. VC1 = 1.5 MHz,

VC2 = 93.75 kHz, VC3 = 0.366 kHz mA Conditions are V

T

DD

= 3.3 V,

A

= 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz mA Conditions are V

T

DD

= 2.55 V,

A

= 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz

µA V

DD

= 2.55 V, 0 °C T

A

 40 °C

I

SB

V

REF

Sleep (mode) current with POR, LVD, sleep timer, WDT, and internal slow oscillator active. Mid temperature range.

Sleep (mode) current with POR, LVD,

Sleep Timer, WDT, and internal slow oscillator active.

Reference voltage (Bandgap)

–

1.28

2.8

1.30

5

1.32

µA V

DD

= 3.3 V, –40 °C T

A

 85 °C

V

V

REF27

Reference voltage (Bandgap) 1.16

1.30

1.33

V

Trimmed for appropriate V

V

DD

= 3.0 V to 5.25 V

DD

Trimmed for appropriate V

V

DD

= 2.4 V to 3.0 V

DD

AGND Analog ground V

REF

– 0.003 V

REF

V

REF

+ 0.003

V


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 7. 2.7-V DC GPIO Specifications

Symbol

R

PU

R

PD

V

OH

Description

Pull-up resistor

Pull-down resistor

High output level

V

OL

I

OH

I

OL

V

IL

V

IH

V

H

I

IL

C

IN

C

OUT

DC General-Purpose I/O Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T

Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.

A

 85 °C, respectively.

V

OL

I

OH

I

OL

V

IL

V

IH

V

H

I

IL

C

IN

Table 6. 5-V and 3.3-V DC GPIO Specifications

Symbol

R

PU

R

PD

V

OH

Pull-up resistor

Pull-down resistor

High output level

Description

C

OUT

Low output level

High level source current

Low level sink current

Input low level

Input high level

Input hysteresis

Input leakage (absolute value)

Capacitive load on pins as input

Capacitive load on pins as output

Min

4

4

V

DD

– 1.0

–

10

25

–

2.1

–

–

–

–

–

–

60

1

3.5

Typ

5.6

5.6

–

–

–

–

3.5

Max

8

8

–

0.75

–

–

0.8

–

–

10

10

Units k  k 

V

Notes

V

I

OH

= 10 mA, V

DD

= 4.75 to 5.25 V

(8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])

I

OL

= 25 mA, V

DD

= 4.75 to 5.25 V

(8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])) mA V

OH

= V

DD

– 1.0 V, see the limitations of the total current in the note for V

OH mA V

OL

= 0.75 V, see the limitations of the total current in the note for V

OL

V V

DD

= 3.0 to 5.25

V V

DD

= 3.0 to 5.25

mV nA Gross tested to 1 µA pF Package and pin dependent

Temp = 25 °C pF Package and pin dependent

Temp = 25 °C

Low output level

High level source current

Low level sink current

Input low level

Input high level

Input hysteresis

Input leakage (absolute value)

Capacitive load on pins as input

Capacitive load on pins as output

Min

4

4

V

DD

– 0.4

Typ

5.6

5.6

–

–

2.5

10

–

2.0

–

–

–

–

–

–

–

90

1

3.5

3.5

–

–

Max

8

8

–

0.75

–

–

0.75

–

–

–

10

10

Units k 

Notes k 

V I

OH

= 2.5 mA (6.25 Typ), V combined I

OH

budget)

DD

= 2.4 to

3.0 V (16 mA maximum, 50 mA Typ

V I

OL

= 10 mA, V

DD

= 2.4 to 3.0 V (90 mA maximum combined I

OL

budget) mA V

OH

= V

DD

– 0.4 V, see the limitations of the total current in the note for V

OH mA V

OL

= 0.75 V, see the limitations of the total current in the note for V

OL

V V

DD

= 2.4 to 3.0

V V

DD

= 2.4 to 3.0

mV nA Gross tested to 1 µA pF Package and pin dependent

Temp = 25 °C pF Package and pin dependent

Temp = 25 °C


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC Operational Amplifier Specifications


5.25 V and –40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T

Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

A


Table 8. 5-V DC Operational Amplifier Specifications

Symbol

V

OSOA

TCV

OSOA

I

EBOA

I

EBOA00

C

INOA

Description

Input offset voltage (absolute value)

Average input offset voltage drift

Input leakage current (Port 0 analog pins 7-to-1)

Input leakage current (Port 0, Pin 0 analog pin)

Input capacitance (Port 0 analog pins)

Min

–

–

–

–

–

Typ

2.5

10

200

50

4.5

Max

15

–

–

–

9.5

Units mV

µV/°C pA nA pF

Notes

Gross tested to 1 µA


Package and pin dependent.

Temp = 25 °C

V

CMOA

Common mode voltage range 0.0

– V

DD

– 1.0

V

80

10

–

30 dB

µA

G

OLOA

I

SOA

Open loop gain

Amplifier supply current

–

–

Table 9. 3.3-V DC Operational Amplifier Specifications

Symbol

V

OSOA

TCV

OSOA

I

EBOA

I

EBOA00

C

INOA

Description



Input leakage current (Port 0 analog pins)



V

CMOA

G

OLOA

I

SOA

Common mode voltage range

Open loop gain


Min

–

–

–

–

–

0

–

–

Typ

2.5

10

200

50

4.5

–

80

10

Max

15

–

–

–

9.5

V

DD

– 1.0

–

30

Units mV

µV/°C pA nA pF

Notes




Temp = 25 °C

V dB

µA

Table 10. 2.7-V DC Operational Amplifier Specifications

Symbol

V

OSOA

TCV

OSOA

I

EBOA

I

EBOA00

C

INOA

Description



Input leakage current (Port 0 analog pins)



–

–

–

Min

–

–

V

CMOA

G

OLOA

I

SOA

Common mode voltage range

Open loop gain


0

–

–

Typ

2.5

10

200

50

4.5

–

80

10

Max

15

–

–

–

9.5

V

DD

– 1.0

–

30

Units mV

µV/°C pA nA pF

Notes




Temp = 25 °C

V dB

µA


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC Switch Mode Pump Specifications

Table 11

lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T

A

 85 C, 3.0 V to 3.6 V and –40 °C  T

A


A


Figure 12. Basic Switch Mode Pump Circuit

D1

Vdd

V

PUMP

V

BAT

+

L

1

Battery

SMP

Vss

PSoC

C1

Table 11. DC Switch Mode Pump (SMP) Specifications

Symbol

V

PUMP5V

V

V

E

PUMP3V

PUMP2V

Description

5 V output voltage from pump

3.3 V output voltage from pump

2.6 V output voltage from pump

I

PUMP

V

BAT5V

V

BAT3V

V

BAT2V

V

BATSTART

V

V

Available output current

V

BAT

= 1.8 V, V

BAT

BAT

= 1.5 V, V

= 1.3 V, V

PUMP

PUMP

PUMP

= 5.0 V

= 3.25 V

= 2.55 V

Input voltage range from battery



Minimum input voltage from battery to start pump

V

PUMP_Line

Line regulation (over Vi range)

5

8

8

1.8

1.0

1.0

1.2

–

V

V

3

PUMP_Load

PUMP_Ripple

Load regulation

Output voltage ripple (depends on cap/load)

Efficiency

Min

4.75

Typ

5.0

3.00

3.25

2.45

–

–

35

2.55

–

–

–

–

–

–

–

5

5

100

50

–

–

–

5.0

3.3

2.8

–

Max

5.25

3.60

2.80

–

–

–

–

Units

V

V

V mA mA mA

V

V

V

Notes

Configured as in Note 15

Average, neglecting ripple

SMP trip voltage is set to 5.0 V


Average, neglecting ripple.



Average, neglecting ripple.


Configured as in Note

15




Configured as in Note

15


Configured as in

Note 15


Configured as in

Note 15


V

%V

O

Configured as in

Note 15

0 C  T

T

A

A

 100. 1.25 V at

= –40 °C

Configured as in

Note 15

V

O

is the “V

DD

Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification,

Table 13 on page 23

%V

O

Configured as in

Note 15

V

O

is the “V

DD

Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification,

Table 13 on page 23

mVpp Configured as in Note 15

Load is 5 mA

%


Load is 5 mA. SMP trip voltage is set to 3.25 V

Note

15. L

1

= 2 mH inductor, C

1

= 10 mF capacitor, D

1

= Schottky diode. See

Figure 12 on page 22

.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 11. DC Switch Mode Pump (SMP) Specifications (continued)

E

2

Symbol

F

PUMP

DC

PUMP

Efficiency

Description

Switching frequency

Switching duty cycle

Min

35

–

–

Typ

80

1.3

50

Max

–

–

–

Units

%

Notes

For I load = 1mA, V

V

BAT

= 1.3 V,

PUMP

= 2.55 V,

10 µH inductor, 1 µF capacitor, and

Schottky diode

MHz

%

DC Analog Mux Bus Specifications

Table 12


–40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A


A


Table 12. DC Analog Mux Bus Specifications

Symbol

R

SW

Description

Switch resistance to common analog bus

R

VDD

Resistance of initialization switch to V

DD

Min

–

–

Typ

–

–

Max

400

800

800

Units



Notes

V

DD

 2.7 V

2.4 V V

DD

2.7 V



DC POR and LVD Specifications

Table 13


–40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A


A


Table 13. DC POR and LVD Specifications

Symbol

V

PPOR0

V

PPOR1

V

PPOR2

V

LVD0

V

LVD1

V

LVD2

V

LVD3

V

LVD4

V

LVD5

V

LVD6

V

LVD7

V

PUMP0

V

PUMP1

V

PUMP2

V

PUMP3

V

PUMP4

V

PUMP5

V

PUMP6

V

PUMP7

Description

V

DD

value for PPOR trip

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

V

DD

value for LVD trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

V

DD

value for pump trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

Min

–

–

–

2.45

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

Typ

2.36

2.82

4.55

2.55

3.02

3.10

3.25

4.64

4.73

4.82

5.00

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.51

[16]

2.99

[17]

3.09

3.20

4.55

4.75

4.83

4.95

2.62

[18]

3.09

3.16

3.32

[19]

4.74

4.83

4.92

5.12

Max Units

2.40

2.95

4.70

V

V

V

Notes

V

DD

must be greater than or equal to

2.5 V during startup, the reset from the XRES pin, or reset from watchdog

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Notes

16. Always greater than 50 mV above V

PPOR

(PORLEV = 00) for falling supply.


PPOR


LVD0


LVD3

.

.

(PORLEV = 01) for falling supply.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC Programming Specifications

Table 14


–40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A


A


Table 14. DC Programming Specifications

Symbol

V

DDP

Description

V

DD

for programming and erase

V

DDLV

V

DDHV

V

DDIWRITE

Low V

DD

for verify

High V

DD

for verify

Supply voltage for flash write operation

Min

4.5

2.4

5.1

2.7

Typ

5

2.5

5.2

Max

5.5

2.6

5.3

5.25

Units

V

V

V

V

Notes

This specification applies to the functional requirements of external programmer tools



This specification applies to this device when it is executing internal flash writes

I

DDP

V

ILP

V

IHP

I

ILP

I

IHP

V

OLV

V

OHV

Flash

ENPB

Flash

ENT

Flash

DR

Supply current during programming or verify

Input low voltage during programming or verify

Input high voltage during programming or verify

Input current when applying V

ILP

to P1[0] or

P1[1] during programming or verify

Input current when applying V

IHP

to P1[0] or

P1[1] during programming or verify

Output low voltage during programming or verify

Output high voltage during programming or verify

Flash endurance (per block)

Flash endurance (total)

[21]

Flash data retention

–

–

2.2

–

–

–

V

DD

– 1.0

50,000

[20]

1,800,000

10

5

–

–

–

–

–

–

–

–

25

0.8

–

0.2

1.5

– V

SS

+ 0.75

V

DD

–

–

– mA

V

V mA Driving internal pull-down resistor mA Driving internal pull-down resistor

V

V

–

–

Years

Erase/write cycles per block

Erase/write cycles

DC I

2

C Specifications

Table 15


–40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

 T

A


Table 15. DC I

2

C Specifications

[22]

Symbol

V

ILI2C

Input low level

Description

V

IHI2C

Input high level

Min

–

–

0.7 × V

DD

Typ Max

– 0.3 × V

DD

– 0.25 × V

DD

– –

Units

V

V

V

Notes

2.4 V V

DD

3.6 V

4.75 V V

DD

5.25 V

2.4 V V

DD

5.25 V

Notes

20. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V, and 4.75 V to 5.25 V.

21. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36×2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no single block ever sees more than 50,000 cycles). For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC

®

22. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I 2

Flash) for more information.

C GPIO pins also meet the above specs.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC Electrical Characteristics

AC Chip-Level Specifications


5.25 V and –40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T


A


Table 16. 5-V and 3.3-V AC Chip-Level Specifications

Symbol

F

IMO24

[23]

Description

IMO frequency for 24 MHz

Min

23.4

Typ

24

Max

24.6

[24,25]

F

IMO6

[23]

F

CPU1

F

CPU2

F

BLK5

F

BLK33

F

32K1

F

32K_U t

XRST

DC24M

DC

ILO

Step24M

Fout48M

External reset pulse width

24 MHz duty cycle

ILO duty cycle

24 MHz trim step size

48 MHz output frequency

F

MAX

SR

POWER_UP t

POWERUP

Maximum frequency of signal on row input or row output.

Power supply slew rate

Time from end of POR to CPU executing code t jit_IMO


CPU frequency (5 V nominal)

CPU frequency (3.3 V nominal)

Digital PSoC block frequency

0

(5 V nominal)

Digital PSoC block frequency (3.3 V nominal)

ILO frequency

ILO untrimmed frequency

24-MHz IMO cycle-to-cycle jitter (RMS)

[27]

24-MHz IMO long term N cycle-to-cycle jitter

(RMS)

[27]

24-MHz IMO period jitter (RMS)

[27]

5.52

–

–

–

0.091

0.091

0

0

15

5

10

40

20

–

46.8

–

–

–

6

24

32

–

–

50

50

50

48.0

–

–

16

200

300

100

24

12

48

6.48

[24,25]

24.6

[24]

12.3

[25]

49.2

[24,26]

24.6

[26]

64

100

–

60

80

–

49.2

[24,25]

12.3

250

100

700

900

400

Units Notes

MHz Trimmed for 5 V or 3.3 V operation using factory trim values. See

Figure 14 on page 19 . SLIMO mode = 0

MHz Trimmed for 5 V or 3.3 V operation using factory trim values. See

Figure 14 on page 19 . SLIMO mode = 1

MHz 24 MHz only for

SLIMO mode = 0

MHz SLIMO mode = 0

MHz Refer to

AC Digital Block

Specifications on page 28

MHz kHz kHz After a reset and before the

M8C starts to run, the ILO is not trimmed. See the system resets section of the PSoC

Technical Reference Manual for details on this timing

s

%

% kHz

MHz Trimmed. Using factory trim values

MHz

V/ms V

DD

slew rate during power-up ms Power-up from 0 V. See the

System Resets section of the

PSoC Technical Reference

Manual ps ps N = 32 ps

Notes


24. 4.75 V < V

DD

25. 3.0 V < V

DD

< 5.25 V.

< 3.6 V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3 V.

26. See the individual user module datasheets for information on maximum frequencies for user modules.

27. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at www.cypress.com

under Application Notes for more information.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 17. 2.7-V AC Chip-Level Specifications t

Symbol

F

IMO12

[28]

F

F

F

F

IMO6

[28]

CPU1

BLK27

32K1

F

32K_U jit_IMO t

XRST

DC

ILO

F

MAX

SR

POWER_UP t

POWERUP

Description



Min

11.04

5.52

CPU frequency (2.7 V nominal)

Digital PSoC block frequency (2.7 V nominal)

ILO frequency

ILO untrimmed frequency

0.093

0

8

5

External reset pulse width

IILO duty cycle

Maximum frequency of signal on row input or row output.

Power supply slew rate

Time from end of POR to CPU executing code

12 MHz IMO cycle-to-cycle jitter (RMS)

12 MHz IMO long term N cycle-to-cycle jitter

(RMS)

[31]

12 MHz IMO period jitter (RMS)

[31]

[31]

10

20

–

–

–

–

–

–

3

12

32

–

–

50

–

–

16

Typ

12

0

6

400

600

100

Max

12.96

[29, 30]

6.48

12.5

[29, 30]

3.15

96

[29]

[29,30]

100

–

80

12.3

250

100

1000

1300

500

Units Notes

MHz Trimmed for 2.7 V operation using factory trim values. See


. SLIMO mode = 1

MHz Trimmed for 2.7 V operation using factory trim values. See


. SLIMO mode = 1

MHz 12 MHz only for

SLIMO mode = 0

MHz Refer to

AC Digital Block

Specifications on page 28

kHz kHz After a reset and before the

M8C starts to run, the ILO is not trimmed. See the System

Resets section of the PSoC

Technical Reference Manual for details on this timing

µs

%

MHz

V/ms V

DD

slew rate during power-up ms Power-up from 0 V. See the

System Resets section of the

PSoC Technical Reference

Manual .

ps ps N = 32 ps

Notes


29. 2.4 V < V

DD

< 3.0 V.

30. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” available at http://www.cypress.com

for information on maximum frequency for user modules.

31. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at www.cypress.com

under Application Notes for more information.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC General Purpose I/O Specifications


5.25 V and –40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T


A


Table 18. 5-V and 3.3-V AC GPIO Specifications

Symbol

F

GPIO

TRiseF

TFallF

TRiseS

TFallS

Description

GPIO operating frequency

Rise time, normal strong mode, Cload = 50 pF

Fall time, normal strong mode, Cload = 50 pF

Rise time, slow strong mode, Cload = 50 pF

Fall time, slow strong mode, Cload = 50 pF

Min

0

3

2

7

7

Typ

–

–

–

27

22

Max

12

18

18

–

–

Units Notes

MHz Normal strong mode ns ns ns ns

V

DD

= 4.5 to 5.25 V, 10% to 90%

V

DD

= 4.5 to 5.25 V, 10% to 90%

V

DD

= 3 to 5.25 V, 10% to 90%

V

DD

= 3 to 5.25 V, 10% to 90%

Table 19. 2.7 V AC GPIO Specifications

Symbol

F

GPIO

TRiseF

TFallF

TRiseS

TFallS

Description

GPIO operating frequency

Rise time, normal strong mode, Cload = 50 pF

Fall time, normal strong mode, Cload = 50 pF

Rise time, slow strong mode, Cload = 50 pF

Fall time, slow strong mode, Cload = 50 pF

Min

0

6

6

18

18

Typ

–

–

–

40

40

Max

3

50

50

120

120

Figure 13. GPIO Timing Diagram

90%

Units Notes

MHz Normal strong mode ns ns ns ns

V

DD

= 2.4 to 3.0 V, 10% to 90%

V

DD

= 2.4 to 3.0 V, 10% to 90%

V

DD

= 2.4 to 3.0 V, 10% to 90%

V

DD

= 2.4 to 3.0 V, 10% to 90%

GPIO

Pin

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

AC Operational Amplifier Specifications

Table 20


–40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A


A


Table 20. AC Operational Amplifier Specifications

Symbol

T

COMP

Description

Comparator mode response time, 50 mV overdrive

Min

–

Typ

–

Max

100

200

Units ns ns

Notes

V

DD

 3.0 V

2.4 V < V

DD

< 3.0 V


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC Digital Block Specifications


5.25 V and –40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T


A


Table 21. 5-V and 3.3-V AC Digital Block Specifications

Function Description

All functions Block input clock frequency

Timer

V

DD

 4.75 V

V

DD

< 4.75 V

Input clock frequency

No capture, V

DD

4.75 V

No capture, V

DD

< 4.75 V

With capture

Counter

Capture pulse width


No enable input, V

DD

 4.75 V

No enable input, V

DD

< 4.75 V

With enable input

Enable input pulse width

Dead Band

CRCPRS

(PRS

Mode)

Kill pulse width

Asynchronous restart mode

Synchronous restart mode

Disable mode


V

DD

 4.75 V

V

DD

< 4.75 V


V

DD

 4.75 V

V

DD

< 4.75 V

Input clock frequency CRCPRS

(CRC

Mode)

SPIM Input clock frequency

Min

–

–

–

–

–

50

[32]

–

–

–

50

[32]

20

50

[32]

50

[32]

–

–

–

–

–

–

Typ

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Max

49.2

24.6

49.2

24.6

24.6

–

49.2

24.6

24.6

–

–

–

–

49.2

24.6

49.2

24.6

24.6

8.2

Unit

MHz

MHz

MHz

MHz

MHz ns

MHz

MHz

MHz ns ns ns ns

MHz

MHz

MHz

MHz

MHz

Notes

SPIS –

50

[32]

–

–

4.1

–

MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2.

MHz The input clock is the SPI SCLK in SPIS mode.

ns

Transmitter

Receiver

Input clock (SCLK) frequency

Width of SS_negated between transmissions


V

DD

 4.75 V, 2 stop bits

V

DD

 4.75 V, 1 stop bit

V

DD

< 4.75 V


–

–

–

–

–

–

49.2

24.6

24.6

MHz

MHz

MHz

The baud rate is equal to the input clock frequency divided by 8.

The baud rate is equal to the input clock frequency divided by 8.

V

DD

 4.75 V, 2 stop bits

V

DD

 4.75 V, 1 stop bit

V

DD

< 4.75 V

–

–

–

–

–

–

49.2

24.6

24.6

MHz

MHz

MHz

Note

32. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 22. 2.7-V AC Digital Block Specifications

Function

All functions

Timer

Description

Block input clock frequency

Counter

Dead Band

CRCPRS

(PRS Mode)

CRCPRS

(CRC Mode)

SPIM

SPIS

Transmitter

Receiver

Capture pulse width

Input clock frequency, with or without capture

Enable input pulse width

Input clock frequency, no enable input

Input clock frequency, enable input

Kill pulse width:

Asynchronous restart mode

Synchronous restart mode

Disable mode





Input clock (SCLK) frequency

Width of SS_ Negated between transmissions



–

–

20

100

100

–

–

Min

–

100

[33]

–

100

–

–

Typ

–

–

–

–

–

–

–

100

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

12.7

12.7

12.7

6.35

Max

12.7

–

12.7

–

12.7

12.7

4.1

–

12.7

12.7

Units Notes

MHz 2.4 V < V

DD

< 3.0 V ns

MHz ns

MHz

MHz ns ns ns

MHz

MHz

MHz

MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2.

MHz ns

MHz The baud rate is equal to the input clock frequency divided by 8.

MHz The baud rate is equal to the input clock frequency divided by 8.

AC External Clock Specifications


5.25 V and –40 °C  T

A

 85 °C, or 3.0 V to 3.6 V and –40 °C  T

3.3 V, or 2.7 V at 25 °C and are for design guidance only.

A

 85 °C, respectively. Typical parameters are measured at 5 V,

Table 23. 5-V AC External Clock Specifications

Symbol

F

OSCEXT

–

–

–

Description

Frequency

High period

Low period

Power-up IMO to switch

Min

0.093

20.6

20.6

150

Typ

–

–

–

–

Max

24.6

5300

–

–

Units

MHz ns ns

µs

Notes

Note

33. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 24. 3.3-V AC External Clock Specifications

–

–

–

Symbol

F

OSCEXT

Description

Frequency with CPU clock divide by 1

F

OSCEXT

Frequency with CPU clock divide by 2 or greater

High period with CPU clock divide by 1

Low period with CPU clock divide by 1


Min

0.093

Typ

–

0.186

41.7

41.7

150

–

–

–

–

Max

12.3

24.6

5300

–

–

Units Notes

MHz Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements

MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met ns ns

µs

–

–

–

Table 25. 2.7-V AC External Clock Specifications

Symbol

F

OSCEXT

Description

Frequency with CPU clock divide by 1

F

OSCEXT

Frequency with CPU clock divide by 2 or greater

High period with CPU clock divide by 1

Low period with CPU clock divide by 1


Min

0.093

Typ

–

0.186

160

160

150

–

–

–

–

Max

3.08

0

6.35

5300

–

–

Units Notes

MHz Maximum CPU frequency is 3 MHz at

2.7 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements

MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met ns ns

µs


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC Programming Specifications

Table 26


–40 °C  T

A

 85 °C, or 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 26. AC Programming Specifications

Symbol

T

RSCLK

T

FSCLK

T

SSCLK

T

HSCLK

F

SCLK

T

ERASEB

T

WRITE

T

DSCLK

T

DSCLK3

T

DSCLK2

T

ERASEALL

Description

Rise time of SCLK

Fall time of SCLK

Data setup time to falling edge of SCLK

Data hold time from falling edge of SCLK

Frequency of SCLK

Flash erase time (block)

Flash block write time

Data out delay from falling edge of SCLK



Flash erase time (Bulk)

T

PROGRAM_HOT

Flash block erase + flash block write time

T

PROGRAM_COLD

Flash block erase + flash block write time

–

–

–

–

Min

1

1

40

40

0

–

–

–

–

10

40

–

–

Typ

–

–

–

–

–

–

20

–

–

–

–

45

50

Max

20

20

–

–

8

70

–

100

[34]

200

[34]

Units ns ns ns ns

MHz ms ms ns ns ns ms ms ms

Notes

3.6  V

DD

3.0  V

DD

 3.6

2.4  V

DD

 3.0

Erase all blocks and protection fields at once

0 °C  Tj  100 °C

–40 °C  Tj  0 °C

AC I

2

C

[35]

Specifications


5.25 V and –40 °C  T

A

 85 °C, 3.0 V to 3.6 V and –40 °C  T

A

 85 °C, or 2.4 V to 3.0 V and –40 °C  T


A


Table 27. AC Characteristics of the I

2

C SDA and SCL Pins for V

DD

3.0 V

Symbol

F

SCLI2C

T

HDSTAI2C

T

LOWI2C

T

HIGHI2C

T

SUSTAI2C

T

HDDATI2C

T

SUDATI2C

T

SUSTOI2C

T

BUFI2C

T

SPI2C

Description

SCL clock frequency

Hold time (repeated) start condition. After this period, the first clock pulse is generated

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated start condition

Data hold time

Data setup time

Setup time for stop condition

Bus free time between a stop and start condition

Pulse width of spikes suppressed by the input filter.

Standard Mode

Min

0

4.0

Max

100

–

4.7

4.0

4.7

0

250

4.0

4.7

–

–

–

–

–

–

–

–

–

Fast Mode

Min

0

0.6

Max

400

–

1.3

0.6

0.6

0

100

[36]

0.6

1.3

0

–

–

–

–

–

–

–

50

Units kHz

µs

µs

µs

µs

µs ns

µs

µs ns

Notes

34. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC ®

35. Errata: The I 2 C block exhibits occasional data and bus corruption errors when the I 2 mode.

36. A Fast-Mode I 2 C-bus device may be used in a Standard-Mode I

Flash) for more information.

C master initiates transactions while the device is transitioning in to or out of sleep the device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T rmax

+ T

SU;DAT

2 C-bus system, but it must meet the requirement T

SU;DAT

 250 ns. This is automatically the case if

= 1000 + 250 = 1250 ns (according to the Standard-Mode I

2

C-bus specification) before the SCL line is released.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 28. 2.7-V AC Characteristics of the I

2

C SDA and SCL Pins (Fast Mode not Supported)

Symbol

F

SCLI2C

T

HDSTAI2C

T

LOWI2C

T

HIGHI2C

T

SUSTAI2C

T

HDDATI2C

T

SUDATI2C

T

SUSTOI2C

T

BUFI2C

T

SPI2C

Description

SCL clock frequency

Hold time (repeated) start condition. After this period, the first clock pulse is generated.

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated start condition

Data hold time

Data setup time

Setup time for stop condition

Bus free time between a stop and start condition

Pulse width of spikes are suppressed by the input filter.

4.7

4.0

4.7

0

250

4.0

4.7

Standard Mode

Min Max

0

4.0

100

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Min

–

–

Fast Mode

Max

–

–

– –

–

–

–

–

–

–

–

Figure 14. Definition for Timing for Fast/Standard Mode on the I

2

C Bus

I2C_SDA

T

SUDATI2C

T

HDSTAI2C

I2C_SCL

S

START Condition

T

HIGHI2C

T

LOWI2C

T

HDDATI2C

T

SUSTAI2C

Sr

Repeated START Condition

T

SPI2C

T

BUFI2C

T

SUSTOI2C

P

STOP Condition

S

Units kHz

µs

µs ns

µs

µs

µs

µs

µs ns


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Packaging Information

This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.

Figure 15. 16-pin SOIC (150 Mils) Package Outline, 51-85068

51-85068 *E


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Figure 16. 20-pin SSOP (210 Mils) Package Outline, 51-85077


51-85077 *E


51-85079 *E

Page 34 of 53

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Figure 18. 32-pin QFN (5 × 5 × 1.0 mm) Package Outline, 001-30999

001-30999 *D

Important Note For information on the preferred dimensions for mounting QFN packages, see the Application Notes for Surface

Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com

.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) Package Outline, 001-48913


001-48913 *C


51-85062 *F

Page 36 of 53

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Thermal Impedances

Table 29. Thermal Impedances per Package

Package

16-pin SOIC

20-pin SSOP

28-pin SSOP

32-pin QFN

[38]

5 × 5 mm 0.60 Max

32-pin QFN

[38]

5 × 5 mm 1.00 Max

56-pin SSOP

Typical 

JA

[37]

123 °C/W

117 °C/W

96 °C/W

27 °C/W

22 °C/W

48 °C/W

Typical 

JC

55 °C/W

41 °C/W

39 °C/W

15 °C/W

12 °C/W

24 °C/W

Solder Reflow Specifications

Table 30 shows the solder reflow temperature limits that must not be exceeded.

Table 30. Solder Reflow Specifications

16-pin SOIC

20-pin SSOP

28-pin SSOP

32-pin QFN

56-pin SSOP

Package Maximum Peak Temperature (T

C

)

260 °C

260 °C

260 °C

260 °C

260 °C

Maximum Time above T

C

– 5 °C

30 seconds

30 seconds

30 seconds

30 seconds

30 seconds

Notes

37. T

J

= T

A

+ Power × 

JA

38. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)

Packages available at http://www.amkor.com

.

39. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Development Tool Selection

This section presents the development tools available for all current PSoC device families including the CY8C21x34 family.

Software

PSoC Designer



At the core of the PSoC development software suite is

PSoC Designer, used to generate PSoC firmware applications.

PSoC Designer is available free of charge at http://www.cypress.com

and includes a free C compiler.

PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and

PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com.

Development Kits

All development kits can be purchased from the Cypress Online

Store.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with

PSoC Designer. This kit supports in-circuit emulation, and the software interface allows you to run, halt, and single step the processor, and view the content of specific memory locations.

Advance emulation features also supported through PSoC

Designer. The kit includes:

■

PSoC Designer software CD

■

ICE-Cube in-circuit emulator

■

ICE Flex-Pod for CY8C29x66 family

■

Cat-5 adapter

■

Mini-Eval programming board

■

110 ~ 240 V power supply, Euro-Plug adapter

■ iMAGEcraft C compiler

■

ISSP cable

■

USB 2.0 cable and Blue Cat-5 cable

■

Two CY8C29466-24PXI 28-PDIP chip samples

Evaluation Tools

All evaluation tools can be purchased from the Cypress Online

Store.

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows you to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes:

■

MiniProg programming unit

■

MiniEval socket programming and evaluation board

■

28-pin CY8C29466-24PXI PDIP PSoC device sample

■

28-pin CY8C27443-24PXI PDIP PSoC device sample

■


■

Getting Started guide

■

USB 2.0 cable

CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■

Evaluation board with LCD module

■


■

Two 28-pin CY8C29466-24PXI PDIP PSoC device samples

■


■


■

USB 2.0 cable

CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device.

The board includes both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■

PSoCEvalUSB board

■

LCD module

■

MIniProg programming unit

■

Mini USB cable

■

PSoC Designer and example projects CD

■


■

Wire pack


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Device Programmers

All device programmers can be purchased from the Cypress Online Store.

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■

Modular programmer base

■

Three programming module cards

■


■


■


■

USB 2.0 cable

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment.

Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■

CY3207 programmer unit

■

PSoC ISSP software CD

■

110 ~ 240 V power supply, Euro-Plug adapter

■

USB 2.0 cable

Accessories (Emulation and Programming)

Table 31. Emulation and Programming Accessories

Part Number Pin Package Flex-Pod Kit

[40]

CY8C21234-24SXI 16-pin SOIC CY3250-21X34

CY8C21334-24PVXI

CY8C21534-24PVXI

20-pin SSOP

28-pin SSOP

CY3250-21X34

CY3250-21X34

Foot Kit

[41]

CY3250-16SOIC-FK

CY3250-20SSOP-FK

CY3250-28SSOP-FK

Adapter

Adapters can be found at http://www.emulation.com

.

Notes

40. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

41. Foot kit includes surface mount feet that can be soldered to the target PCB.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Ordering Information

16-Pin (150-Mil) SOIC

16-Pin (150-Mil) SOIC

(Tape and Reel)

20-Pin (210-Mil) SSOP


(Tape and Reel)



(Tape and Reel)

32-Pin (5 × 5 mm 1.00 max)

Sawn QFN

32-Pin (5 × 5 mm 1.00 max)

Sawn QFN

[43]

(Tape and Reel)

32-Pin (5 × 5 mm 0.60 max)

Thin Sawn QFN

32-Pin (5 × 5 mm 0.60 max)

Thin Sawn QFN

(Tape and Reel)

32-Pin (5 × 5 mm 1.00 max)

Sawn QFN

[43]

32-Pin (5 × 5 mm 1.00 max)

Sawn QFN

[43]

(Tape and Reel)

56-Pin OCD SSOP

CY8C21234-24SXI

CY8C21234-24SXIT

8 K

8 K

512

512

Yes

Yes

–40 °C to +85 °C

–40 °C to +85 °C

4

4

CY8C21334-24PVXI 8 K 512 No –40 °C to +85 °C 4

CY8C21334-24PVXIT 8 K 512 No –40 °C to +85 °C 4

CY8C21534-24PVXI 8 K 512 No –40 °C to +85 °C 4

CY8C21534-24PVXIT 8 K 512 No –40 °C to +85 °C 4

CY8C21434-24LTXI

CY8C21001-24PVXI

8 K

CY8C21434-24LTXIT 8 K 512 No –40 °C to +85 °C 4

CY8C21434-24LQXI 512 No –40 °C to +85 °C 4

CY8C21434-24LQXIT 8 K 512 No –40 °C to +85 °C 4

CY8C21634-24LTXI

8 K

8 K

CY8C21634-24LTXIT 8 K 512 Yes –40 °C to +85 °C 4

8 K

512

512

512

No

Yes

Yes

–40 °C to +85 °C

–40 °C to +85 °C

–40 °C to +85 °C

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

12 12

[42]

12 12

[42]

16 16

[42]

16 16

[42]

24 24

[42]

24 24

[42]

28 28

[42]

28 28

[42]

28 28

[42]

28 28

[42]

26 26

[42]

26 26

[42]

26 26

[42]

0

0

No

No

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

0 Yes

Notes

42. All Digital I/O Pins also connect to the common analog mux.

43. Refer to the section 32-pin Part Pinout on page 11

for pin differences.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Ordering Code Definitions

CY 8 C 21 xxx -24 xx

Package Type:

PX = PDIP Pb-free

SX = SOIC Pb-free

PVX = SSOP Pb-free

LFX/LKX/LTX/LCX/LQX = QFN Pb-free

Thermal Rating:

C = Commercial

I = Industrial

E = Extended

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Acronyms

Table 32

lists the acronyms that are used in this document.

Table 32. Acronyms Used in this Datasheet

IMO

I/O

IrDA

ISSP

LCD

LED

LPC

LVD

MAC

MCU

Acronym

AC

ADC

API

CMOS

CPU

CRC

CT alternating current

Description analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit cyclic redundancy check continuous time

DAC

DC

DTMF

ECO digital-to-analog converter direct current dual-tone multi-frequency external crystal oscillator

EEPROM electrically erasable programmable read-only memory

GPIO

ICE

IDE

ILO general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output infrared data association in-system serial programming liquid crystal display light-emitting diode low power comparator low voltage detect multiply-accumulate microcontroller unit

Reference Documents

SRAM

SROM

SSOP

UART

USB

WDT

XRES

RTC

SAR

SC

SLIMO

SMP

SOIC

SPI

TM

Acronym

MIPS

OCD

PCB

PDIP

PGA

PLL

POR

PPOR

PRS

PSoC

®

PWM

QFN

Description million instructions per second on-chip debug printed circuit board plastic dual-in-line package programmable gain amplifier phase-locked loop power on reset precision power on reset pseudo-random sequence

Programmable System-on-Chip pulse width modulator quad flat no leads real time clock successive approximation switched capacitor slow IMO switch-mode pump small-outline integrated circuit serial peripheral interface static random access memory supervisory read only memory shrink small-outline package universal asynchronous receiver / transmitter universal serial bus watchdog timer external reset

CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,

CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC

Reference Manual (TRM) (001-14463)

®

Programmable System-on-Chip Technical

Design Aids – Reading and Writing PSoC

®

Flash - AN2015 (001-40459)

Adjusting PSoC

®

Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)

Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)

Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com

.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document Conventions

Units of Measure

Table 33

lists the units of measures.

Table 33. Units of Measure

Symbol kB dB

°C

µF fF pF kHz

MHz rt-Hz k 



µA mA nA pA mH

Unit of Measure

1024 bytes decibels degree Celsius microfarad femto farad picofarad kilohertz megahertz root hertz kilo ohm ohm microampere milliampere nano ampere pico ampere millihenry mVpp nV

V

µW

W mm ppm

%

Symbol

µH

µs ms ns ps

µV mV micro henry microsecond

Unit of Measure millisecond nanosecond picosecond microvolt millivolts millivolts peak-to-peak nano volt volt microwatt watt millimeter parts per million percent

Numeric Conventions

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).

Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.

Glossary

active high 1. A logic signal having its asserted state as the logic 1 state.

2. A logic signal having the logic 1 state as the higher voltage of the two states.

analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.

These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.

analog-to-digital

(ADC)

A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.

Application programming interface (API) asynchronous bandgap reference bandwidth

A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications.

A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.

A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.

1. The frequency range of a message or information processing system measured in hertz.

2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary

(continued) bias block buffer bus clock

1. A systematic deviation of a value from a reference value.

2. The amount by which the average of a set of values departs from a reference value.

3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device.

1. A functional unit that performs a single function, such as an oscillator.

2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block.

1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written.

2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device.

3. An amplifier used to lower the output impedance of a system.

1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns.

2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0].

3. One or more conductors that serve as a common connection for a group of related devices.

The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks.

comparator compiler

An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements.

A program that translates a high level language, such as C, into machine language.

configuration space

In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.

crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components.

cyclic redundancy check (CRC)

A calculation used to detect errors in data communications, typically performed using a linear feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression.

data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.

debugger dead band

A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory.

A period of time when neither of two or more signals are in their active state or in transition.

digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI.

digital-to-analog

(DAC)

A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary

(continued) duty cycle emulator

External Reset

(XRES)

Flash

Flash block

The relationship of a clock period high time to its low time, expressed as a percent.

Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system.

An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state.

An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is

OFF.

The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes.

The number of cycles or events per unit of time, for a periodic function.

frequency gain

I

2

C

The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB.

A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated

Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.

ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer).

input/output (I/O) A device that introduces data into or extracts data from a system.

interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed.

interrupt service routine (ISR)

A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution.

jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams.

2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.

low-voltage detect

(LVD)

A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.

M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space.

master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary

(continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor.

mixed-signal The reference to a circuit containing both analog and digital techniques and components.

modulator noise

A device that imposes a signal on a carrier.

1. A disturbance that affects a signal and that may distort the information carried by the signal.

2. The random variations of one or more characteristics of any entity such as voltage, current, or data.

A circuit that may be crystal controlled and is used to generate a clock frequency.

oscillator parity

Phase-locked loop (PLL) pinouts

A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).

An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal.

The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names.

A group of pins, usually eight.

port

Power on reset

(POR)

A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset.

PSoC

®

Semiconductor’s of Cypress.

PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.

pulse width modulator (PWM)

An output in the form of duty cycle which varies as a function of the applied measurand

RAM register reset

ROM

An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in.

A storage device with a specific capacity, such as a bit or byte.

A means of bringing a system back to a know state. See hardware reset and software reset.

An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial settling time

1. Pertaining to a process in which all events occur one after the other.

2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel.

The time it takes for an output signal or value to stabilize after the input has changed from one value to another.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary

(continued) shift register slave device

SRAM

SROM stop bit synchronous tri-state

UART user modules

A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.

A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device.

An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device.

An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash.

A signal following a character or block that prepares the receiving device to receive the next character or block.

1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.

2. A system whose operation is synchronized by a clock signal.

A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net.

A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.

Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming

Interface) for the peripheral function.

user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program.

V

DD

A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.

V

SS

A name for a power net meaning "voltage source." The most negative power supply signal.

watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Errata

This section describes the errata for the PSoC

®

Programmable System-on-Chip CY8C21234. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CY8C21234

Ordering Information

CY8C21234-24SXI

CY8C21234-24SXIT

CY8C21334-24PVXI

CY8C21334-24PVXIT

CY8C21534-24PVXI

CY8C21534-24PVXIT

CY8C21434-24LFXI

CY8C21434-24LFXIT

CY8C21434-24LKXI

CY8C21434-24LKXIT

CY8C21634-24LFXI

CY8C21634-24LFXIT

CY8C21434-24LTXI

CY8C21434-24LTXIT

CY8C21434-24LQXI

CY8C21434-24LQXIT

CY8C21634-24LTXI

CY8C21634-24LTXIT

CY8C21001-24PVXI

CY8C21234 Qualification Status

Product Status: Production


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

CY8C21234 Errata Summary

The following table defines the errata applicability to available CY8C21234 family devices. An "X" indicates that the errata pertains to the selected device.

Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.

Items

[1.]. Internal Main Oscillator (IMO)

Tolerance Deviation at Temperature

Extremes

[2]. I2C Errors

Part Number

CY8C21234

CY8C21234

Silicon Revision

A

Fix Status

No fix is currently planned.

A No fix is currently planned.

1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes

■

■

■

■

■

■

Problem Definition

Asynchronous Digital Communications Interfaces may fail framing beyond 0 °C to 70 °C. This problem does not affect end-product usage between 0 °C and 70 °C.

Parameters Affected

The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

Trigger Condition(S)

The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the datasheet limit of ±2.5% when operated beyond the temperature range of 0 °C to +70 °C.

Scope of Impact

This problem may affect UART, IrDA, and FSK implementations.

Workaround

Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.

Fix Status

No fix is currently planned.

2. I

2

C Errors

■

■

Problem Definition

The I

2

C block exhibits occasional data and bus corruption errors when the I transitioning in to or out of sleep mode.

2

C master initiates transactions while the device is

Parameters Affected

Affects reliability of I

2

C communication to device, between I

2

C master, and third party I

2

C slaves.

■

■

■

■

Trigger Condition(S)

Triggered by transitions into and out of the device's sleep mode.

Scope of Impact

This problem may affect UART, IrDA, and FSK implementations.

Workaround

Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I

2 bus prior to going to sleep modes. I

2 device prior to the I

2

C transaction

C block from the

C transactions during sleep are supported by a protocol in which the master wakes the

Fix Status

Will not be fixed.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document History Page

Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC

®

Document Number: 38-12025

Programmable System-on-Chip™

Rev.

**

*A

ECN

227340

235992

Orig. of

Change

HMT

SFV

Submission

Date

See ECN Updated Overview and Electrical Spec. chapters, along with revisions to the

24-Pin pinout part. Revised the register mapping tables. Added a SSOP 28-Pin part.

Description of Change

See ECN New silicon and document (Revision **).

*B 248572 SFV

*C 277832 HMT

See ECN Changed title to include all part #s. Changed 28-Pin SSOP from CY8C21434 to CY8C21534. Changed pin 9 on the 28-Pin SSOP from SMP pin to Vss pin.

Added SMP block to architecture diagram. Update Electrical Specifications.

Added another 32-Pin MLF part: CY8C21634.

See ECN Verify datasheet standards from SFV memo. Add Analog Input Mux to applicable pin outs. Update PSoC Characteristics table. Update diagrams and specs. Final.

*D

*E

*F

285293

301739

329104

HMT

HMT

HMT

*G

*H

*I

352736

390152

413404

HMT

HMT

HMT

See ECN Update 2.7 V DC GPIO spec. Add Reflow Peak Temp. table.

See ECN DC Chip-Level Specification changes. Update links to new CY.com Portal.

See ECN Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature.

Update Electrical Specifications. Update Reflow Peak Temp. table. Add 32

MLF E-PAD dimensions. Add ThetaJC to Thermal Impedance table. Fix 20-Pin package order number. Add CY logo. Update CY copyright.

See ECN Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications.

See ECN Clarify MLF thermal pad connection info. Replace 16-Pin 300-MIL SOIC with correct 150-MIL.

See ECN Update 32-Pin QFN E-Pad dimensions and rev. *A. Update CY branding and

QFN convention.

*J

*K

*L

*M

*N

430185

677717

2147847

2273246

2618124

HMT

HMT

UVS /

PYRS

UVS /

AESA

OGNE /

PYRS

See ECN Add new 32-Pin 5x5 mm 0.60 thickness QFN package and diagram,

CY8C21434-24LKXI. Update thermal resistance data. Add 56-Pin SSOP on-chip debug non-production part, CY8C21001-24PVXI. Update typical and recommended Storage Temperature per industrial specs. Update copyright and trademarks.

See ECN Add CapSense SNR requirement reference. Add new Dev. Tool section. Add

CY8C20x34 to PSoC Device Characteristics table. Add Low Power

Comparator (LPC) AC/DC electrical spec. tables. Update rev. of 32-Lead (5x5 mm 0.60 MAX) QFN package diagram.

02/27/08 Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering information.

04/01/08 Added 32 pin thin sawn package diagram.

*O

*P

2684145

2693024

SNV /

AESA

12/09/08 Added Note in Ordering Information section.

Changed title from PSoC Mixed-Signal Array to PSoC

Programmable System-on-Chip

04/06/2009 Updated 32-Pin Sawn QFN package dimension for CY8C21434-24LTXIT

Updated Getting Started, Development Tools, and Designing with PSoC

Designer Sections

04/16/2009 Updated 32-Pin Sawn QFN package diagram

*Q 2720594

DPT /

PYRS

BRW 06/22/09 Corrected ohm symbol and parenthesis in figure caption (Fig.25)

Removed references to mixed-sginal array from the text.

Updated Development Tools Selection section.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234


(continued)


®



Rev.

*R

ECN

2762499

Orig. of

Change

JVY

Submission

Date


*S 2900687 MAXK /

NJF

09/11/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows:

Modified F

IMO6

Replaced T specification.

and T

WRITE

specifications.

(time) specification with SR

Added note [11] to Flash Endurance specification.

Added I

T

OH

RAMP

, I

OL

, DC

PROGRAM_COLD

ILO

, F

32K_U

, T

specifications.

POWERUP

, T

POWER_UP

ERASEALL

(slew rate)

, T

PROGRAM_HOT

, and

03/30/2010 Updated

The Analog Multiplexer System

.

Updated Cypress website links.

Added T

BAKETEMP and T

BAKETIME parameters in

Absolute Maximum Ratings

.

Updated

5-V and 3.3-V AC Chip-Level Specifications .

Removed AC Low Power Comparator and AC Analog Mux Bus sections.

Updated note in Packaging Information

and package diagrams.

Added 56 SSOP values for

Thermal Impedances , Solder Reflow Specifications .

Removed Third Party Tools and Build a PSoC Emulator into your Board.

Updated

Ordering Code Definitions .

Removed inactive parts from Ordering Information

Removed obsolete package spec 001-06392.

Updated links in

Sales, Solutions, and Legal Information

.

*T 2937578 VMAD

*U 3005573 NJF

05/26/2010 Updated content to match current style guide and datasheet template.

No technical updates.

09/02/10 Added PSoC Device Characteristics table .

Added DC I

2

C Specifications table.

Added F

32K_U

max limit.

Added Tjit_IMO specification, removed existing jitter specifications.

I

Updated Units of Measure, Acronyms, Glossary, and References sections.

Updated solder reflow specifications.

No specific changes were made to AC Digital Block Specifications table and

C Timing Diagram. They were updated for clearer understanding.

Template and styles update.

*V 3068269 ARVM

*W

*X

*Y

3281271

3383568

3659297

VMAD

GIR

YLIU

10/21/2010 Removed pruned parts CY8C21434-24LKXI and CY8C21434-24LKXIT from

Ordering Information .

08/23/2011 Under

Table 20 on page 27 “Notes” section, the text “2.4 V < V

CC

< 3.0 V” is changed to “2.4 V < V

DD

< 3.0 V”.

Updated

Solder Reflow Specifications

.

Changed package diagram from 51-85188 *D to 001-30999 *C for QFN32 package.

10/05/2011 The text “Pin must be left floating” is included under Description of NC pin in

Pin Definitions on page 13

.

Changed spec 001-30999 from 32-Pin (5 × 5 mm 0.93 Max) Sawn QFN to

32-Pin (5 × 5 mm 1.0 Max) Sawn QFN

Removed pruned parts CY8C21434-24LCXI and CY8C21434-24LCXIT from the

Ordering Information

table.

07/26/2012 Updated

Packaging Information (Removed spec 001-44368).


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234


(continued)


®



Rev.

*Z

ECN

3902039

Orig. of

Change

VNJ

Submission

Date


02/12/2013 Updated

Electrical Specifications (Updated

AC Electrical Characteristics

(Updated AC Chip-Level Specifications (Updated Table 16 (Changed minimum

value of F of F

IMO6

IMO6

parameter from 5.5 MHz to 5.52 MHz, changed maximum value

parameter from 6.5 MHz to 6.48 MHz), updated Table 17

(Changed minimum value of F maximum value of F minimum value of F maximum value of F

IMO12

IMO12

IMO6

IMO6

parameter from 11.5 MHz to 11.04 MHz, changed



parameter from 6.5 MHz to 6.48 MHz)))).

AA

AB

3993249

4076892

SLAN

SLAN

Updated

Packaging Information :

spec 51-85068 – Changed revision from *D to *E.

spec 001-30999 – Changed revision from *C to *D.

spec 001-48913 – Changed revision from *B to *C.

spec 51-85062 – Changed revision from *E to *F.

05/07/2013 Added

Errata

.

07/25/2013 Added Errata footnotes (Notes 1, 2, 3, 4, 5, 8, 23, 28, 35).

Updated

Features

:

Added Note 1 and referred in “Internal ±2.5% 24- / 48-MHz main oscillator”.

Added Note 2 and referred in “I

2

C” under “Additional system resources”.

Updated

PSoC Functional Overview :

Updated

The PSoC Core :

Added Note 3 and referred in “24 MHz”.


2

C” under “System resources provide these additional capabilities”.

Updated

The Digital System :


2

C slave and multi-master”.

Updated

Additional System Resources :


2

C”.

Updated

Development Tools

:


interfaces”.

2

C” under “Built-in support for communication

Updated

Electrical Specifications :

Updated

AC Electrical Characteristics :

Updated

AC Chip-Level Specifications :

Added Note 23 and referred in “F

IMO24

” and “F

Added Note 28 and referred in “F

IMO12

” and “F

Updated

AC I2C [35] Specifications :

Added Note 35 and referred in the heading.

IMO6

IMO6

” parameters in

Table 16

.

” parameters in

Table 17

.

Updated in new template.

Completing Sunset Review.


CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .

Products

Automotive

Clocks & Buffers

Interface

Lighting & Power Control

Memory

PSoC

Touch Sensing

USB Controllers

Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless

PSoC

®

Solutions

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Community | Forums | Blogs | Video | Training

Technical Support

cypress.com/go/support

© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12025 Rev. AB Revised July 25, 2013 Page 53 of 53

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC

®

and CapSense

® are registered trademarks of Cypress Semiconductor Corporation.

Purchase of I 2 C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I that the system conforms to the I

2 C Patent Rights to use these components in an I 2 C system, provided

2 C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.

No results