Document Conventions. Cypress Semiconductor CY8C21234

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document Conventions

Units of Measure

Table 33

lists the units of measures.

Table 33. Units of Measure

Symbol kB dB

°C

µF fF pF kHz

MHz rt-Hz k 



µA mA nA pA mH

Unit of Measure

1024 bytes decibels degree Celsius microfarad femto farad picofarad kilohertz megahertz root hertz kilo ohm ohm microampere milliampere nano ampere pico ampere millihenry mVpp nV

V

µW

W mm ppm

%

Symbol

µH

µs ms ns ps

µV mV micro henry microsecond

Unit of Measure millisecond nanosecond picosecond microvolt millivolts millivolts peak-to-peak nano volt volt microwatt watt millimeter parts per million percent

Numeric Conventions

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).

Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.

Glossary

active high 1. A logic signal having its asserted state as the logic 1 state.

2. A logic signal having the logic 1 state as the higher voltage of the two states.

analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.

These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.

analog-to-digital

(ADC)

A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.

Application programming interface (API) asynchronous bandgap reference bandwidth

A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications.

A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.

A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.

1. The frequency range of a message or information processing system measured in hertz.

2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum.

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Glossary

(continued) bias block buffer bus clock

1. A systematic deviation of a value from a reference value.

2. The amount by which the average of a set of values departs from a reference value.

3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device.

1. A functional unit that performs a single function, such as an oscillator.

2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block.

1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written.

2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device.

3. An amplifier used to lower the output impedance of a system.

1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns.

2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0].

3. One or more conductors that serve as a common connection for a group of related devices.

The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks.

comparator compiler

An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements.

A program that translates a high level language, such as C, into machine language.

configuration space

In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.

crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components.

cyclic redundancy check (CRC)

A calculation used to detect errors in data communications, typically performed using a linear feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression.

data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.

debugger dead band

A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory.

A period of time when neither of two or more signals are in their active state or in transition.

digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI.

digital-to-analog

(DAC)

A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation.

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Glossary

(continued) duty cycle emulator

External Reset

(XRES)

Flash

Flash block

The relationship of a clock period high time to its low time, expressed as a percent.

Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system.

An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state.

An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is

OFF.

The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes.

The number of cycles or events per unit of time, for a periodic function.

frequency gain

I

2

C

The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB.

A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated

Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.

ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer).

input/output (I/O) A device that introduces data into or extracts data from a system.

interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed.

interrupt service routine (ISR)

A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution.

jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams.

2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.

low-voltage detect

(LVD)

A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.

M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space.

master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device.

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Glossary

(continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor.

mixed-signal The reference to a circuit containing both analog and digital techniques and components.

modulator noise

A device that imposes a signal on a carrier.

1. A disturbance that affects a signal and that may distort the information carried by the signal.

2. The random variations of one or more characteristics of any entity such as voltage, current, or data.

A circuit that may be crystal controlled and is used to generate a clock frequency.

oscillator parity

Phase-locked loop (PLL) pinouts

A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).

An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal.

The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names.

A group of pins, usually eight.

port

Power on reset

(POR)

A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset.

PSoC

®

Semiconductor’s of Cypress.

PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.

pulse width modulator (PWM)

An output in the form of duty cycle which varies as a function of the applied measurand

RAM register reset

ROM

An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in.

A storage device with a specific capacity, such as a bit or byte.

A means of bringing a system back to a know state. See hardware reset and software reset.

An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial settling time

1. Pertaining to a process in which all events occur one after the other.

2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel.

The time it takes for an output signal or value to stabilize after the input has changed from one value to another.

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Glossary

(continued) shift register slave device

SRAM

SROM stop bit synchronous tri-state

UART user modules

A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.

A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device.

An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device.

An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash.

A signal following a character or block that prepares the receiving device to receive the next character or block.

1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.

2. A system whose operation is synchronized by a clock signal.

A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net.

A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.

Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming

Interface) for the peripheral function.

user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program.

V

DD

A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.

V

SS

A name for a power net meaning "voltage source." The most negative power supply signal.

watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.

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