SuperH Family E10A-USB Emulator Supplementary Information on Using the SH7214 and SH7216 Additional Document for User's Manual

SuperH™ Family E10A-USB Emulator

Supplementary Information on Using the SH7214 and SH7216

Additional Document for User’s Manual

SuperH

™

Family / SH7216 Series

E10A-USB for SH7216 HS7216KCU01HE

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corporation without notice. Please review the latest information published by Renesas Electronics Corporation through various means, including the Renesas Electronics

Corporation website (http://www.renesas.com). www.renesas.com

Rev.3.00 Jun 2013

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of

Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas

Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas

Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas

Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.

Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use

Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas

Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

Regulatory Compliance Notices

European Union regulatory notices

This product complies with the following EU Directives. (These directives are only valid in the European Union.)

CE Certifications:

• Electromagnetic Compatibility (EMC) Directive 2004/108/EC

EN 55022 Class A

WARNING:

This is a Class A product. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.

EN 55024

• Information for traceability

• Authorised representative

Address: 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa, 211-8668, Japan

• Manufacturer

Name: Renesas Solutions Corp.

Address: Nippon Bldg., 2-6-2, Ote-machi, Chiyoda-ku, Tokyo 100-0004, Japan

• Person responsible for placing on the market

Name: Renesas Electronics Europe Limited

Address: Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Environmental Compliance and Certifications:

•

Waste Electrical and Electronic Equipment (WEEE) Directive 2002/96/EC

WEEE Marking Notice

(European Union Only)

Renesas development tools and products are directly covered by the European Union's Waste

Electrical and Electronic Equipment, (WEEE), Directive 2002/96/EC. As a result, this equipment, including all accessories, must not be disposed of as household waste but through your locally recognized recycling or disposal schemes. As part of our commitment to environmental responsibility Renesas also offers to take back the equipment and has implemented a Tools Product

Recycling Program for customers in Europe. This allows you to return equipment to Renesas for disposal through our approved Producer Compliance Scheme. To register for the program, click here “ http://www.renesas.com/weee ".

United States Regulatory notices on Electromagnetic compatibility

FCC Certifications (United States Only):

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part

15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.

CAUTION:

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

Table of Contents

Section 1 Connecting the Emulator with the User System .................................................................... 1

1.1

Components of the Emulator .................................................................................................................................... 1

1.2

Connecting the Emulator with the User System ....................................................................................................... 3

1.3

Installing the H-UDI Port Connector on the User System ........................................................................................ 4

1.4

Pin Assignments of the H-UDI Port Connector ........................................................................................................ 5

1.5

Recommended Circuit between the H-UDI Port Connector and the MCU .............................................................. 9

1.5.1

Recommended Circuit (36-Pin Type) ............................................................................................................ 9

1.5.2

Recommended Circuit (14-Pin Type) .......................................................................................................... 12

1.5.3

Recommended Circuit (38-Pin Type) .......................................................................................................... 14

Section 2 Software Specifications when Using the SH7214 and SH7216 Group ............................... 17

2.1

Differences between the MCU and the Emulator ................................................................................................... 17

2.2

Specific Functions for the Emulator when Using the SH7214 and SH7216 Group................................................ 25

2.2.1

Event Condition Functions ........................................................................................................................... 25

2.2.2

Trace Functions ............................................................................................................................................ 32

2.2.3

Note on Using the JTAG (H-UDI) Clock (TCK) ......................................................................................... 43

2.2.4

Notes on Setting the [Breakpoint] Dialog Box............................................................................................. 44

2.2.5

Notes on Setting the [Event Condition] Dialog Box and the BREAKCONDITION_ SET Command........ 45

2.2.6

Performance Measurement Function............................................................................................................ 45

SuperH

™

Family E10A-USB Emulator Section 1 Connecting the Emulator with the User System

Section 1 Connecting the Emulator with the User System

1.1

Components of the Emulator

The E10A-USB emulator supports the SH7214 and SH7216 group. Table 1.1 lists the components of the emulator.

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Family E10A-USB Emulator

User system interface cable

User system interface cable

Section 1 Connecting the Emulator with the User System

Table 1.1 Components of the Emulator

Classification Component

Hard- ware

Emulator box

Appearance

Quantity Remarks

1 HS0005KCU01H:

Depth: 65.0 mm, Width: 97.0 mm,

Height: 20.0 mm, Mass: 72.9 g or

HS0005KCU02H:

Depth: 65.0 mm, Width: 97.0 mm,

Height: 20.0 mm, Mass: 73.7 g

1

Length: 20 cm, Mass: 33.1 g


(only for HS0005KCU02H)


Soft- ware

E10A-USB emulator setup program,

SuperH

TM

Family E10A-

USB Emulator User’s

Manual,

Supplementary

Information on Using the

SH7214 and SH7216*, and

Test program manual for

HS0005KCU01H and

HS0005KCU02H

1 HS0005KCU01SR,

HS0005KCU01HJ,

HS0005KCU01HE,

HS7216KCU01HJ,

HS7216KCU01HE,

HS0005TM01HJ, and

HS0005TM01HE

(provided on a CD-R)

Note: Additional document for the MCUs supported by the emulator is included. Check the target

MCU and refer to its additional document.

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1.2

Connecting the Emulator with the User System

To connect the E10A-USB emulator (hereinafter referred to as the emulator), the H-UDI port connector must be installed on the user system to connect the user system interface cable. When designing the user system, refer to the recommended circuit between the H-UDI port connector and the MCU. In addition, read the E10A-USB emulator user's manual and hardware manual for the related device.

Table 1.2 shows the type number of the emulator, the corresponding connector type, and the use of

AUD function.

Table 1.2 Type Number, AUD Function, and Connector Type

Type Number Connector AUD Function

HS0005KCU01H, HS0005KCU02H 14-pin connector Not available

The H-UDI port connector has the 36-pin, 14-pin, and 38-pin types as described below. Use them according to the purpose of the usage.

1. 36-pin type (with AUD function)

The AUD trace function is supported. A large amount of trace information can be acquired in realtime. The window trace function is also supported for acquiring memory access in the specified range (memory access address or memory access data) by tracing.

2. 14-pin type (without AUD function)

The AUD trace function cannot be used because only the H-UDI function is supported. Since the 14-pin type connector is smaller than the 36-pin type (1/2.5), the size of the area where the connector is installed on the user system can be reduced.

3. 38-pin type (with AUD function)

The AUD trace function is supported. As well as the 36-pin type, a large amount of trace information can be acquired in realtime. Since the 38-pin type connector is smaller than the

36-pin type (1/2.5), the size of the area where the connector is installed on the user system can be reduced. To use the 38-pin type connector, however, an optional cable (HS0005ECK01H) is required.

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1.3

Installing the H-UDI Port Connector on the User System

Table 1.3 shows the recommended H-UDI port connectors for the emulator.

Table 1.3 Recommended H-UDI Port Connectors

36-pin connector

DX10M-36SE,

DX10G1M-36SE

14-pin connector 2514-6002

38-pin connector 2-5767004-2

Lock-pin type

3M Limited. 14-pin straight type

Tyco Electronics AMP K.K. 38-pin Mictor type

Note: When designing the 36-pin connector layout on the user board, do not connect any components under the H-UDI connector. When designing the 14-pin connector layout on the user board, do not place any components within 3 mm of the H-UDI port connector.

When designing the 38-pin connector layout on the user board, reduce cross-talk noise etc. by keeping other signal lines out of the region where the H-UDI port connector is situated.

As shown in figure 1.1, an upper limit (5 mm) applies to the heights of components mounted around the user system connector.

E10A-USB optional 38-pin user system interface cable

37

50 mm

1

2-5767004-2

5 mm

38 2

Tar g et system

: Area to be kept free of other components

H-UDI port connector (top view)

Figure 1.1 Restriction on Component Mounting

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1.4

Pin Assignments of the H-UDI Port Connector

Figures 1.2 through 1.4 show the pin assignments of the 36-pin, 14-pin, and 38-pin H-UDI port connectors, respectively.

Note: Note that the pin number assignments of the H-UDI port connector shown on the following pages differ from those of the connector manufacturer.

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5

6

7

8

1

2

3

4

9

Pin

No.

Signal

/

Output

SH7214, SH7216

Pin No.

LQFP

-176

LFBGA

-176

82

M12

AUDCK

GND

AUDATA0

Output

Output

GND

77

N11

78

R11

AUDATA1

GND

Output

AUDATA2

GND

Output

79

P11

AUDATA3

Output 80 M11

φ

2.8

14

15

16

17

18

10

11

12

GND

AUDSYNC#

*2

Output

GND

13

N.C.

GND

N.C.

GND

TCK

GND

Input

+0.1

0

2

4

81

127

R12

D13

Edge of the board

(connected to the connector)

φ

0.7

+0.1

0

Note

36

Pin

No.

32

33

34

35

36

Signal

GND

GND

*3

GND

N.C.

GND

Output

23

24

25

26

19

20

21

22

27

TMS

GND

TRST#

*2

Input

Input

28

29

30

31

TDI

GND

TDO

Input

Output

GND

ASEBRKAK#

Input/ output

GND

UVCC

Output

GND

RES#

*2

Output

Output

SH7214, SH7216

Pin No.

LQFP

-176

LFBGA

-176

128 D14

129

125

126

134

133

C12

D15

C15

C13

A15

Note

User reset


4.09

3

1

1.27

21.59

37.61

43.51

: Pattern inhibited area

H-UDIport connector (top view)

35

(Pin 1 mark)

H-UDI port connector (front view)

M2.6 x

0.45

Unit: mm

Notes:

1. Input to or output from the user system.

2. The symbol (_) means that the signal is active-low.

3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected.

4. When the user system interface cable is connected to this pin and the ASEMD0# pin is set to 0, do not connect to GND

but to the ASEMD0# pin directly.

Figure 1.2 Pin Assignments of the H-UDI Port Connector (36 Pins)

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Pin No.

1

2

3

4

5

6

7

8

9

11

10,12,13

14

Signal

TDI

RES#

N.C.

(GND)

UVCC

GND

GND

TCK

TRST#

*2

TDO

ASEBRKAK#

/ASEBRK#

*2

TMS

*2

*4

*3

Pin 1 mark

Input/

Output*1

Input

Input

Output

Input/

Output

Input

Input

Output

SH7216, SH7214

Pin No.

LQFP

-176

127

LFBGA

-176

D13

129

126

134

C12

C15

C13

128

125

133

D14

D15

A15

Note

User reset

Output

Output


25.0

23.0

6 x 2.54 = 15.24

(2.54)


Pin 8

Pin 1

Pin 14

Pin 7

0.45

Pin 1 mark

Unit: mm

Notes:




4. When the user system interface cable is connected to this pin and the ASEMD0# pin is set to 0, do not connect to GND

but to the ASEMD0# pin directly.


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16

17

18

19

12

13

14

15

Pin

No.

9

10

7

8

5

6

3

4

1

2

11

Signal

Input/

Output

*1

SH7216, SH7214

Pin No.

LQFP

-176

LFBGA

-176

N.C.

N.C.

*4

ASEMD#(GND)

N.C.

*3

UCON#(GND)

AUDCK Output

N.C.

ASEBRKAK#/

*2

ASEBRK#

RES#

*2

Input/

Output

Output

N.C.

TDO Output

82

134

133

126

M12

C13

A15

C15

Note

User reset

Output

UVCC_AUD

N.C.

UVCC

TCK

N.C.

TMS

N.C.

TDI

Output

Input

Input

Input

127

128

125

D13

D14

D15

Pin

No.

32

33

34

35

28

29

30

31

36

37

38

24

25

26

27

20

21

22

23

Signal

Input/

*1

Output

SH7216, SH7214

Pin No.

LQFP

-176

LFBGA

-176

N.C.

N.C.

N.C.

N.C.

N.C.

TRST#

*2

N.C.

N.C.

Input

AUDATA3

N.C.

Output

AUDATA2

N.C.

Output

AUDATA1

N.C.

AUDATA0

Output

Output

N.C.

AUDSYNC#

*2

Output

129

80

79

78

77

81

C12

M11

P11

R11

N11

R12

N.C.

N.C.

Note

37 1

6.91

38 2

25.4


Unit: mm

Notes:




4. When the user system interface cable is connected to this pin and the ASEMD0 pin is set to 0, do not connect to GND

but to the ASEMD0 pin directly.

5.The GND bus lead at the center of the H-UDI port connector must be grounded.


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1.5

Recommended Circuit between the H-UDI Port Connector and the

MCU

1.5.1

Recommended Circuit (36-Pin Type)

Figure 1.5 shows recommended circuits for connection between the H-UDI and AUD port connectors (36 pins) and the MCU when the emulator is in use.

Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector.

2. The ASEMD0# pin must be 0 when the emulator is connected and 1 when the emulator is not connected, respectively.

(1) When the emulator is used: ASEMD0# = 0

(2) When the emulator is not used: ASEMD0# = 1

Figure 1.5 shows examples of circuits that allow the _ASEMD pin to be GND (0) whenever the emulator is connected by using the user system interface cable.

When the ASEMD0# pin is changed by switches, etc., ground pin 22. Do not connect this pin to the ASEMD0# pin.

3. When a network resistance is used for pull-up, it may be affected by a noise. Separate

TCK from other resistances.

4. The pattern between the H-UDI port connector and the MCU must be as short as possible. Do not connect the signal lines to other components on the board.

5. The AUD signals (AUDCK, AUDATA3 to AUDATA0, and AUDSYNC#) operate in high speed. Isometric connection is needed if possible. Do not separate connection nor connect other signal lines adjacently.

6. Since the H-UDI and the AUD of the MCU operate with the VCCQ, supply only the

VCCQ to the UVCC pin. Make the emulator’s switch settings so that the user power will be supplied (SW2 = 1 and SW3 = 1).

7. The resistance value shown in figures 1.5 is for reference.

8. For the AUDCK pin, guard the pattern between the H-UDI port connector and the

MCU at GND level.

9. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related MCU.

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When the circuit is connected as shown in figure 1.5, the switches of the emulator are set as SW2

= 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH

TM

Family E10A-USB Emulator User’s Manual.

H-UDI port connector

( 3 6-pin type)

2

4

6

8

10

12

14

16

1 8

20

22

24

26

2 8

3 0

3 2

3 4

3 6

1

GND AUDCK

3

GND AUDATA0

5

GND AUDATA1

7

GND AUDATA2

9

GND AUDATA 3

11

GND

AUD S YNC

1 3

GND N.C.

GND

N.C.

15

17

GND

TCK

1 9

GND

TM S

21

(GND)

TR S T

GND TDI

25

GND TDO

GND

A S EBRKAK

GND

/A S EBRK

UVCC

27

2 9

3 1

GND RE S

2 3

33

GND GND

3 5

GND

N.C.

All p u lledu p a t 4.7 k

Ω

or more

VCCQ VCCQ VCCQ

1 k

Ω

VCCQ

VCCQ = I/O power su pply

S H7214,

TCK

TM S

TR S T

TDI

TDO

A S EBRKAK

/A S EBRK

*

RE

A S

S

EMD0

S

AUDCK

AUDATA0

AUDATA1

AUDATA2

AUDATA 3

AUD S YNC

H7216

Re s et s ign a l

U s er s y s tem

Figure 1.5 Recommended Circuit for Connection between the H-UDI Port Connector and

MCU when the Emulator is in Use (36-Pin Type)

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Note: The ASEBRKAK#/ASEBRK# pin (I/O pin) is multiplexed with the FWE pin (input pin) function. For pin processing when the emulator is in use and the user system is independently in operation, referring to the section of the MCU operating mode in the hardware manual of the MCU, pins must be pulled up by a 4.7- to 10-k

Ω

resistor or pulled down by a 100-k

Ω

resistor for the desired operating mode without being directly connected to VCC or GND.

When the pin function is set to high for independent operation of the user system:

Pins must be pulled up by a 4.7- to 10-k

Ω

resistor.

When the pin function is set to low for independent operation of the user system:

Pins must be pulled down by a 100-k

Ω

resistor.

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1.5.2


Figure 1.6 shows recommended circuits for connection between the H-UDI port connectors (14 pins) and the MCU when the emulator is in use.





Figure 1.6 shows examples of circuits that allow the ASEMD0# pin to be GND (0) whenever the emulator is connected by using the user system interface cable.





5. Since the H-UDI and the AUD of the MCU operate with the VCCQ, supply only the

VCCQ to the UVCC and UVCC_AUD pins. Make the emulator’s switch settings so that the user power will be supplied (SW2 = 1 and SW3 = 1).

6. The resistance value shown in figure 1.6 is for reference.

7.

For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related MCU.



TM


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(14-pin type)

1

TCK

9

10

12

1 3

(GND)

GND

TR S T

TDI

2

GND

TDO

GND

A S EBRKAK

/A S EBRK

TM S

3

4

5

6

14

GND RE S

7

N.C.

8

11

UVCC

VCCQ


Ω

or more

VCCQ VCCQ VCCQ

VCCQ


1 k

Ω

S H7214, S H7216

TCK

TR S T

TDO

A S EBRKAK/A S EBRK

*

TM S

TDI

RE S

Re s et s ign a l

A S EMD0

U s er s y s tem




Ω


Ω




Ω

resistor.



Ω

resistor.

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1.5.3


Figure 1.7 shows recommended circuits for connection between the H-UDI port connectors (38 pins) and the MCU when the emulator is in use.





Figure 1.7 shows examples of circuits that allow the ASEMD0# pin to be GND (0) whenever the emulator is connected by using the user system interface cable.





5.

Since the H-UDI and the AUD of the MCU operate with the VCCQ, supply only the

VCCQ to the UVCC and UVCC_AUD pins. Make the emulator’s switch settings so that the user power will be supplied (SW2 = 1 and SW3 = 1).

6.

The resistance value shown in figure 1.7 is for reference.

7.

For the AUDCK pin, guard the pattern between the H-UDI port connector and the

MCU at GND level.

8.

The GND bus lead at the center of the H-UDI port connector must be grounded.

9.

For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related MCU.



TM


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( 38 -pin type)

AUDCK

AUD S YNC

6

3 2

3 0

AUDATA0

AUDATA1

2 8

AUDATA2

26

AUDATA 3

24

VCCQ


Ω

or more

VCCQ VCCQ VCCQ


S H7214, S H7216

AUDCK

AUD S YNC

AUDATA0

AUDATA1

AUDATA2

AUDATA 3

TCK

TM S

TR S T

TDI

TDO

A S EBRKAK

/A S EBRK

RE S

A S EMD(GND)

UVCC

UVCC_AUD

UCON(GND)

9

3

14

12

5

15

17

21

1 9

11

8

1 k

Ω

Re s et s ign a l

TCK

TM S

TR S T

TDI

TDO

A S EBRKAK

/A S EBRK

*

RE S

A S EMD0

GND

GND bus le a d s

N.C.

1,2,4,7,

10,1 3 ,16,1 8 ,

20,22,2 3 ,25,27,2 9 ,

3 1, 33 , 3 4, 3 5, 3 6, 3 7, 38

U s er s y s tem



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Ω


Ω




Ω

resistor.



Ω

resistor.

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Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7214 and SH7216 Group

Section 2 Software Specifications when Using the SH7214 and SH7216 Group

2.1

Differences between the MCU and the Emulator

1. When the emulator system is initiated, it initializes the general registers and part of the control registers as shown in table 2.1. The initial values of the MCU are undefined. When the emulator is initiated from the workspace, a value to be entered is saved in a session.

Table 2.1 Register Initial Values at Emulator Link Up

Register

R0 to R14

R15 (SP)

PC

Emulator at Link Up

H'00000000

Value of the SP in the power-on reset vector table

Value of the PC in the power-on reset vector table

SR H'000000F0

GBR H'00000000

VBR H'00000000

TBR H'00000000

MACH H'00000000

MACL H'00000000

PR H'00000000

FPSCR* H'00040001

FPUL* H'00000000

FPR0-15* H'00000000

Note: This value is not displayed for MCUs which do not have floating point units (FPUs).

2. The emulator uses the H-UDI; do not access the H-UDI.

3. Low-Power States

⎯

When the emulator is used, the sleep state can be cleared with either the clearing function or with the [STOP] button, and a break will occur.

⎯

The memory must not be accessed or modified in software standby state.

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⎯

Do not stop inputting the clock to the H-UDI module by using the module standby function.

4. Reset Signals

The MCU reset signals are only valid during emulation started with clicking the GO or STEPtype button. If these signals are enabled on the user system in command input wait state, they are not sent to the MCU.

Note: Do not break the user program when the RES#, _BREQ#, or WAIT# signal is being low.

A TIMEOUT error will occur. If the BREQ# or WAIT# signal is fixed to low during break, a TIMEOUT error will occur at memory access.

5. Direct Memory Access Controller (DMAC)

The DMAC operates even when the emulator is used. When a data transfer request is generated, the DMAC executes DMA transfer.

6. Memory Access during User Program Execution

During execution of the user program, memory is accessed by the following two methods, as shown in table 2.2.

Table 2.2 Memory Access during User Program Execution

Method Description

H-UDI read/write The stopping time of the user program is short because memory is accessed by the dedicated bus master.

Short break The stopping time of the user program is long because the user program temporarily breaks.

The method for accessing memory during execution of the user program is specified by using the [Configuration] dialog box.

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Table 2.3 Stopping Time by Memory Access (Reference)

Method Condition

H-UDI read/write Reading of one longword for the internal RAM

Writing of one longword for the internal RAM

Reading: Maximum three bus clocks

(B

φ

)

Writing: Maximum two bus clocks

(B

φ

)

About 50 ms

Short break CPU clock: 160 MHz

JTAG clock: 20 MHz

Reading or writing of one longword for the external area

7. Memory Access to the External Flash Memory Area

The emulator can download the load module to the external flash memory area (for details, refer to section 6.22, Download Function to the Flash Memory Area, in the SuperH

TM

Family

E10A-USB Emulator User’s Manual). Other memory write operations are enabled for the

RAM area. Therefore, an operation such as memory write or BREAKPOINT should be set only for the RAM area.

8. ROM Cache

For ROM cache in the MCU, the emulator operates as shown in table 2.4.

Table 2.4 Operation for ROM Cache

Function Operation

Write and erase Writes or erases all contents of ROM cache.

Download

Memory read Accesses the disabled cache area to read the content of internal flash memory.

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9. Multiplexing the Emulator Pins

A part of the emulator pins is multiplexed as shown in table 2.5.

Table 2.5 Multiplexed Functions

MCU

SH7214 and

SH7216 group

Function 1 Function 2

FWE _ASEBRKAK/_ASEBRK

PD16/D16/IRQ0/POE0/UBCTRG AUDATA0

PD17/D17/IRQ1/POE4/ADTRG AUDATA1

PD18/D18/IRQ2/MDIO AUDATA2

PD19/D19/IRQ3/LNKSTA AUDATA3

PD21/D21/IRQ5/TEND1/EXOUT AUDCK

PD20/D20/IRQ4/AUDSYNC/MDC _AUDSYNC

Note: Function 1 can be used when the AUD pins of the device are not connected to the emulator.

The AUD pins are multiplexed with other pins. When the AUD function is used by the

SH7214 and SH7216 group E10A-USB emulator, AUD pins are used regardless of the settings of the pin function controller (PFC).

10. Using WDT

The WDT does not operate during break.

11. Loading Sessions

Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading sessions. Thus the TCK value will be as follows:

⎯

When HS0005KCU01H or HS0005KCU02H is used: TCK = 5 MHz

12. [IO] Window

⎯

Display and modification

⎯

For each watchdog timer register, there are two registers to be separately used for write and read operations.

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Table 2.6 Watchdog Timer Register

Register Name

WTCSR(W)

Usage

Write

Register

Watchdog timer control/status register

WTCSR(R) Read Watchdog timer control/status register

WRCSR(W)

WRCSR(R)

Write

Read

Watchdog reset control/status register

Watchdog reset control/status register

⎯

Customization of the I/O-register definition file

The internal I/O registers can be accessed from the [IO] window. After the I/O-register definition file is created, the MCU’s specifications may be changed. If each I/O register in the I/O-register definition file differs from addresses described in the hardware manual, change the I/O-register definition file according to the description in the hardware manual.

The I/O-register definition file can be customized depending on its format. However, the emulator does not support the bit-field function.

⎯

Verify

In the [IO] window, the verify function of the input value is disabled.

13. Illegal Instructions

Do not execute illegal instructions with STEP-type commands.

14. Reset Input

During execution of the user program, the emulator may not operate correctly if a contention occurs between the following operations for the emulator and the reset input to the target device:

⎯

Setting an Event Condition

⎯

Setting an internal trace

⎯

Displaying the content acquired by an internal trace

⎯

Reading or writing of a memory

Note that those operations should not contend with the reset input to the target device.

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15. Contention between the Change of the FRQCR Register and the Debugging Functions

The following notes are required for the user program for changing the division rate of the divider to change the frequency:

⎯

Avoid contention between the change of the FRQCR register in the user program and the memory access from the [Memory] window, etc.

⎯

When the automatic updating function is used in the [Monitor] window or [Watch] window, generate and set a break of Event Condition for an instruction immediately before changing the FRQCR register. Contention will be avoided by generating a break and executing the user program again.

⎯

While the SH7216G, SH7216H, SH7214G, or SH7214H is in use, 1/1 is not selectable as the division rate for I

φ

. Select 1/2, 1/4, or 1/8 instead.

For the change of the division rate of the divider and the FRQCR register, refer to the hardware manual for the MCU.

16. MCU Operating Mode

Note that the emulator does not support the boot mode and user boot mode.

17. Access to the Data Flash Memory (FLD)

(1) During execution of a program in the CS area, do not use emulator operations for access to the FLD. Otherwise, the FLD instruction fetch error bit in the flash access status register

(FASTAT) will be set to indicate an FLD instruction error.

(2) During execution of the user program, do not use emulator operations for access to a block of the data mat which is protected against reading.

18. Emulation of Programming and Erasure of the Internal Flash Memory

(1) The setting of the FWE pins is ignored while the emulator is connected. The flash write enable bit (FWE) of the flash pin monitor register (FPMON) becomes undefined. Note this point if the bit is referred to during execution of the user program.

(2) When the MCU is operating in mode 2 (MCU expansion mode) or in mode 3 (MCU single chip mode), writing and erasing of the internal flash memory by programs is possible.

Thus, if emulation is to include writing or erasure of the internal flash memory, the MCU operating mode must be mode 2 (MCU expansion mode) or mode 3 (MCU single chip mode). Do not select mode 6 (user program mode) or mode 7 (USB boot mode and user program mode) while the emulator is connected.

(3) Break processing is not possible during calls of the programs for writing and erasing the internal flash memory. Note that the following processing cannot be performed.

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⎯

STOP button

⎯

Automatic updating and tool chip watching for the watch function

⎯

Memory operations during emulation

⎯

Profiling function

⎯

Monitor function

⎯

AUD trace function (non-realtime trace mode)

(4) Do not set the breakpoint in a block of the internal flash memory that will be a target for writing or erasure.

(5) For emulating programming or erasure of the internal flash memory, select the [Flash memory to PC] or [PC to flash memory, Flash memory to PC] item from the [Flash memory synchronization] drop-down list box in the [Configuration] dialog box ->

[General] page; do not select the [Disable] or [PC to flash memory] items. Also, Select the

[Eeprom memory to PC] from the [Eeprom memory synchronization] drop-down list box.

Do not select the [Disable] item.

19. Selection of the Target Device

(1) The item to be selected in the [Select Emulator mode] dialog box are depends on the weekcode of the SH7216 emulator. When the chip in use has a week-code earlier than [0927], select the item below in the [Select Emulator mode] dialog box.

R5F72167AD (week-code is earlier than [0927]): R5F72167AD_Option

(2) While the SH7216G, SH7216H, SH7214G, or SH7214H is in use, select the corresponding device name given below in the [Select Emulator mode] dialog box.

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Actual MCU in Use Device Name in the [Select Emulator mode]

Dialog Box

R5F72145HD R5F72145BD

R5F72146HD R5F72146BD

R5F72147HD R5F72147BD

R5F72145GD R5F72145AD

R5F72146GD R5F72146AD

R5F72147GD R5F72147AD

R5F72165HD R5F72165BD

R5F72166HD R5F72166BD

R5F72167HD R5F72167BD

R5F72165GD R5F72165AD

R5F72166GD R5F72166AD

R5F72167GD R5F72167AD

(3) In the [Clock] dialog box, enter the frequency of the crystal oscillator connected to the

MCU or the external clock source being input. The value must be in the range from 10 to

12.5 MHz.

(4) If you select the [New ID Code] checkbox in the [ID Code] dialog box and click on [OK] during booting up of the emulator, all of the ROM and FLD areas will be erased.

20. Stepping around FPU Exceptions

When an FPU exception occurs during stepped execution, the message “The values of FPU registers being displayed are incorrect.” appears and the values of the FPU registers being displayed are undefined.

These values will return to normal as you continue stepped execution. To prevent this problem, execute [Go] instead of [Step] around FPU exceptions in the user program.

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2.2

Specific Functions for the Emulator when Using the SH7214 and

SH7216 Group

2.2.1

Event Condition Functions

The emulator is used to set event conditions for the following three functions:

•

Break of the user program

•

Internal trace

•

Start or end of performance measurement

Table 2.7 lists the types of Event Condition.

Table 2.7 Types of Event Condition

Event Condition Type

Address bus condition (Address)

Data bus condition (Data)

Bus state condition

(Bus State)

Count

Reset point

Description

Sets a condition when the address bus (data access) value or the program counter value (before or after execution of instructions) is matched.

Sets a condition when the data bus value is matched. Byte, word, or longword can be specified as the access data size.

There are two bus state condition settings:

Bus state condition: Sets a condition when the data bus value is matched.

Read/Write condition: Sets a condition when the read/write condition is matched.

Sets a condition when the specified other conditions are satisfied for the specified counts.

A reset point is set when the count and the sequential condition are specified.

Action Selects the operation when a condition (such as a break, a trace halt condition, or a trace acquisition condition) is matched.

Use the [Combination action(Sequential or PtoP)] dialog box to specify the sequential condition, the point-to-point operation of the internal trace, and the start or end of performance measurement.

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Table 2.8 lists the combinations of conditions that can be set under Ch1 to Ch11.

Table 2.8 Dialog Boxes for Setting Event Conditions

Dialog Box

[Event

Condition 1]

[Event

Condition 2]

[Event

Condition 3]

[Event

Condition 4]

Function

Address Bus

Condition

(Address)

Data Bus

Condition

(Data)

Bus State

Condition (Bus

Status)

Count

Condition

(Count) Action

(B, T1, and P)

(B, T1, and P)

(B and T2)

(B and T3)

[Event

Condition 5]

[Event

Condition 6]

[Event

Condition 7]

[Event

Condition 8]

[Event

Condition 9]

(B and T3)

(B and T2)

(B and T2)

(B and T2)

(B and T2)

[Event

Condition 10] (B and T2)

[Event

Condition 11]

Ch11 O

(reset point)

X X X X

Notes: 1. O: Can be set in the dialog box.

X: Cannot be set in the dialog box.

2. For the Action item,

B: Setting a break is enabled.

T1: Setting the trace halt and acquisition conditions are enabled for the internal trace.

T2: Setting the trace halt is enabled for the internal trace.

T3: Setting the trace halt and point-to-point is enabled for the internal trace.

P: Setting a performance-measurement start or end condition is enabled.

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The [Event Condition 11] dialog box is used to specify the count of [Event Condition 1] and becomes a reset point when the sequential condition is specified.

Sequential Setting:

Using the [Combination action (Sequential or PtoP)] dialog box specifies the sequential condition and the start or end of performance measurement.

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Table 2.9 Conditions to Be Set

Classification Item Description

[Ch1, 2, 3] list box Sets the sequential condition and the start or end of performance measurement using Event Conditions 1 to 3 and 11.

Don’t care Sets no sequential condition or the start or end of performance measurement.

Break: Ch3-2-1

Break: Ch3-2-1,

Reset point

Break: Ch2-1

Break: Ch2-1,

Reset point

Breaks when a condition is satisfied in the order of

Event Condition 3, 2, 1.


Event Condition 3, 2, 1.

Enables the reset point of Event Condition 11.


Event Condition 2, 1.


Event Condition 2, 1.

Enables the reset point.

I-Trace stop: Ch3-2-1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition

3, 2, 1.

I-Trace stop: Ch3-2-1,

Reset point

Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition

3, 2, 1.


I-Trace stop: Ch2-1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition

2, 1.

I-Trace stop: Ch2-1,

Reset point

Ch2 to Ch1 PA

Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition

2, 1.


Sets the performance measurement period during the time from the satisfaction of the condition set in

Event Condition 2 (start condition) to the satisfaction of the condition set in Event Condition

1 (end condition).

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Table 2.9 Conditions to Be Set (cont)

Classification Item

[Ch1, 2, 3] list box

(cont)

Ch1 to Ch2 PA

Description

Sets the performance measurement period during the time from the satisfaction of the condition set in

Event Condition 1 (start condition) to the satisfaction of the condition set in Event Condition

2 (end condition).

[Ch4, 5] list box Sets the point-to-point of the internal trace (the start or end condition of trace acquisition) using Event Conditions 4 and 5.

Don’t care Sets no start or end condition of trace acquisition.

I-Trace: Ch5 to Ch4

PtoP

Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition

5 (start condition) to the satisfaction of the condition set in Event Condition 4 (end condition).

I-Trace: Ch5 to Ch4

PtoP, power-on reset

Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition

5 (start condition) to the satisfaction of the condition set in Event Condition 4 (end condition) or the power-on reset.

Notes: 1. After the sequential condition and the count specification condition of Event Condition 1 have been set, break and trace acquisition will be halted if the sequential condition is satisfied for the specified count.

2. If a reset point is satisfied, the satisfaction of the condition set in Event Condition will be disabled. For example, if the condition is satisfied in the order of Event Condition 3, 2, reset point, 1, the break or trace acquisition will not be halted. If the condition is satisfied in the order of Event Condition 3, 2, reset point, 3, 2, 1, the break and trace acquisition will be halted.

3. If the start condition is satisfied after the end condition has been satisfied by measuring performance, performance measurement will be restarted. For the measurement result after a break, the measurement results during performance measurement are added.

4. If the start condition is satisfied after the end condition has been satisfied by the pointto-point of the internal trace, trace acquisition will be restarted.

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Usage Example of Sequential Break Extension Setting:

A tutorial program provided for the product is used as an example. For the tutorial program, refer to section 6, Tutorial, in the

SuperH

TM


The conditions of Event Condition are set as follows:

1. Ch3

Breaks address H’00001068 when the condition [Only program fetched address after] is satisfied.

2. Ch2

Breaks address H’0000107a when the condition [Only program fetched address after] is satisfied.

3. Ch1

Breaks address H’00001086 when the condition [Only program fetched address after] is satisfied.

Note: Do not set other channels.

4. Sets the content of the [Ch1,2,3] list box to [Break: Ch 3-2-1] in the [Combination action

(Sequential or PtoP)] dialog box.

5. Enables the condition of Event Condition 1 from the popup menu by clicking the right mouse button on the [Event Condition] sheet.

Then, set the program counter and stack pointer (PC = H’00000800, R15 = H’00010000) in the

[Registers] window and click the [Go] button. If this does not execute normally, issue a reset and execute the above procedures.

The program is executed up to the condition of Ch1 and halted. Here, the condition is satisfied in the order of Ch3 -> 2 -> 1.

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Figure 2.1 [Source] Window at Execution Halted (Sequential Break)

If the sequential condition, performance measurement start/end, or point-to-point for the internal trace is set, conditions of Event Condition to be used will be disabled. Such conditions must be enabled from the popup menu by clicking the right mouse button on the [Event Condition] sheet.

Notes: 1. If the Event condition is set for the slot in the delayed branch instruction by the program counter (after execution of the instruction), the condition is satisfied before executing the instruction in the branch destination (when a break has been set, it occurs before executing the instruction in the branch destination).

2. Do not set the Event condition for the SLEEP instruction by the program counter (after execution of the instruction).

3. When the Event condition is set for the 32-bit instruction by the program counter, set that condition in the upper 16 bits of the instruction.

4. If the power-on reset and the Event condition are matched simultaneously, no condition will be satisfied.

5. Do not set the Event condition for the DIVU or DIVS instruction by the program counter (after execution of the instruction).

6. If a condition of which intervals are satisfied closely is set, no sequential condition will be satisfied.

•

Set the Event conditions, which are satisfied closely, by the program counter with

intervals of two or more instructions.

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•

After the Event condition has been matched by accessing data, set the Event

condition by the program counter with intervals of 17 or more instructions.

7. If the settings of the Event condition or the sequential conditions are changed during execution of the program, execution will be suspended. (The number of clocks to be suspended during execution of the program is a maximum of about 102 bus clocks

(B

φ

). If the bus clock (B

φ

) is 20 MHz, the program will be suspended for 5.1

μ s.)

8. If the settings of Event conditions or the sequential conditions are changed during execution of the program, the emulator temporarily disables all Event conditions to change the settings. During this period, no Event condition will be satisfied.

9. If the break condition before executing an instruction is set to the instruction followed by DIVU and DIVS, the factor for halting a break will be incorrect under the following condition:

If a break occurs during execution of the above DIVU and DIVS instructions, the break condition before executing an instruction, which has been set to the next instruction, may be displayed as the factor for halting a break.

10. If the break conditions before and after executing instructions are set to the same address, the factor for halting a break will be incorrectly displayed. The factor for halting a break due to the break condition after executing an instruction will be displayed even if a break is halted by the break condition before executing an instruction.

11. Do not set the break condition after executing instructions and BREAKPOINT

(software break) to the same address.

12. When the emulator is being connected, the user break controller (UBC) function is not available.

2.2.2

Trace Functions

The emulator supports the trace functions listed in table 2.10.

Table 2.10 Trace Functions

Function

Branch trace

Internal Trace

Supported

Memory access trace Supported

Software trace

Not

AUD Trace

Supported

Supported

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Table 2.11 shows the type numbers that the AUD function can be used.

Table 2.11 Type Number and AUD Function

Type Number AUD Function

HS0005KCU02H Supported

The internal and AUD traces are set in the [Acquisition] dialog box of the [Trace] window.

Internal Trace Function:

When [I-Trace] is selected for [Trace type] on the [Trace Mode] page of the [Acquisition] dialog box, the internal trace can be used.

Figure 2.2 [Acquisition] Dialog Box – Internal Trace Function

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The following three items can be selected as the internal trace from [Type] of [I-Trace mode].

Table 2.12 Information on Acquiring the Internal Trace

[M-Bus & Branch]

[I-Bus]

[F-Bus]

[I-Bus, M-Bus & Branch]

[F-Bus, M-Bus & Branch]

[I-Bus, F-Bus]

Data and branch information on the M-bus.

•

Data access (read/write)

•

PC-relative access

•

Branch information

Data on the I-bus.

•

Data access (read/write)

•

Selection of the bus master on the I-bus (CPU/DMA/A-DMA)

•

Instruction fetching

Instruction-fetch information on the F-bus.

•

Instruction fetching

The contents of [M-Bus & Branch] and [I-Bus].

The contents of [M-Bus & Branch] and [F-Bus].

The contents of [I-Bus] and [F-Bus].

After selecting [Type] of [I-Trace mode], select the content to be acquired from [Acquisition].

Typical examples are described below (note that items disabled for [Acquisition] are not acquired).

•

Example of acquiring branch information only:

Select [M-Bus & Branch] from [Type] and enable [Branch] on [Acquisition].

•

Example of acquiring the read or write access (M-bus) only by a user program:

Select [M-Bus & Branch] from [Type] and enable [Read], [Write], and [Data access] on

[Acquisition].

•

Example of acquiring the read access only by DMA (I-bus):

Select [I-Bus] from [Type] and enable [Read], [DMA], and [Data access] on [Acquisition].

Using Event Condition restricts the condition; the following three items are set as the internal trace conditions.

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Table 2.13 Trace Conditions of the Internal Trace

Trace halt

Trace acquisition

Acquires the internal trace until the Event Condition is satisfied. (The trace content is displayed in the [Trace] window after a trace has been halted. No break occurs in the user program.)

Acquires only the data access where the Event Condition is satisfied.

Point-to-point Traces the period from the satisfaction of Event Condition 5 to the satisfaction of Event Condition 4.

To restrict trace acquisition to access for only a specific address or specific function of a program, an Event Condition can be used. Typical examples are described below.

•

Example of halting a trace with a write access (M-bus) to H’FFF80000 by the user program as a condition (trace halt):

Set the condition to be acquired on [I-Trace mode].

Set the following in the [Event Condition 1] or [Event Condition 2] dialog box:

Address condition: Set [Address] and H’FFF80000.

Bus state condition: Set [M-Bus] and [Write].

Action condition: Disable [Acquire Break] and set [Acquire Trace] for [Stop].

•

Example of acquiring the write access (M-bus) only to H’FFF80000 by the user program (trace acquisition condition):

Select [M-Bus & Branch] from [Type] and enable [Write] and [Data access] on [Acquisition].

Set the following in the [Event Condition 1] or [Event Condition 2] dialog box:

Address condition: Set [Address] and H’FFF80000.

Bus state condition: Set [M-Bus] and [Write].

Action condition: Disable [Acquire Break] and set [Acquire Trace] for [Condition].

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For the trace acquisition condition, the condition to be acquired by Event Condition should be acquired by [I-Trace mode].

•

Example of acquiring a trace for the period while the program passes H’1000 through H’2000

(point-to-point):

Set the condition to be acquired on [I-Trace mode].

Set the address condition as H’1000 in the [Event Condition 5] dialog box.

Set the address condition as H’2000 in the [Event Condition 4] dialog box.

Set [I-Trace] as [Ch5 to Ch4 PtoP] in the [Combination action (Sequential or PtoP)] dialog box.

When point-to-point and trace acquisition condition are set simultaneously, they are ANDed.

Notes on Internal Trace:

•

Timestamp

The timestamp is the clock counts of B

φ

(48-bit counter). Table 2.14 shows the timing for acquiring the timestamp.

Table 2.14 Timing for the Timestamp Acquisition

Item Acquisition Information Counter Value Stored in the Trace Memory

M-bus data access Counter value when data access (read or write) has been completed

Branch Counter value when the next bus cycle has been completed after a branch

I-bus Fetch

Data access

Counter value when a fetch has been completed

Counter value when data access has been completed

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•

Point-to-point

The trace-start condition is satisfied when the specified instruction has been fetched.

Accordingly, if the trace-start condition has been set for the overrun-fetched instruction (an instruction that is not executed although it has been fetched at a branch or transition to an interrupt), tracing is started during overrun-fetching of the instruction. However, when overrun-fetching is achieved (a branch is completed), tracing is automatically suspended.

If the start and end conditions are satisfied closely, trace information will not be acquired correctly.

The execution cycle of the instruction fetched before the start condition is satisfied may be traced.

When the I-bus is acquired, do not specify point-to-point.

•

Memory access may not be acquired by the internal trace if it occurs at several instructions immediately before satisfaction of the point-to-point end condition.

•

Halting a trace

Do not set the trace end condition for the sleep instruction and the branch instruction that the delay slot becomes the sleep instruction.

•

Trace acquisition condition

Do not set the trace end condition for the sleep instruction and the branch instruction according to which the delay slot becomes the sleep instruction.

When [I-Bus, M-Bus & Branch] is selected and the trace acquisition condition is set for the Mbus and I-bus with Event Condition, set the M-bus condition and the I-bus condition for [Event

Condition 1] and [Event Condition 2], respectively.

If the settings of [I-Trace mode] are changed during execution of the program, execution will be suspended. (The number of clocks to be suspended during execution of the program is 66 bus clocks (B

φ


φ

) is 20 MHz, the program will be suspended for 3.3

μ s.)

•

Displaying a trace

If a trace is displayed during execution of the program, execution will be suspended to acquire the trace information. (The number of clocks to be suspended during execution of the program is 24576 bus clocks (B

φ


φ

) is 20 MHz, the program will be suspended for

1228.8.

μ s.)

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•

Branch trace

If breaks occur immediately after executing non-delayed branch and TRAPA instructions and generating a branch due to exception or interrupt, a trace for one branch will not be acquired immediately before such breaks.

However, this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition.

•

Writing memory immediately before generating a break

If an instruction is executed to write memory immediately before generating a break, trace acquisition may not be performed.

AUD Trace Functions:

This function is operational when the AUD pin of the device is connected to the emulator. Table 2.15 shows the AUD trace acquisition mode that can be set in each trace function.

Table 2.15 AUD Trace Acquisition Mode

Type Mode Description

Continuous trace occurs

Realtime trace When the trace information is being generated intensely that the output from the AUD pin incapable of keeping up, the

CPU temporarily suspends the output of trace information.

Therefore, although the user program is run in real time, the acquisition of some trace information might not be possible.

Non realtime trace When trace information is being generated so intensely that the output from the AUD pin is incapable of keeping up, CPU operations are temporarily suspended and the output of trace information takes priority. In such cases, the realtime characteristics of the user program are lost.

Trace buffer full

Trace continue

Trace stop

This function overwrites the latest trace information to store the oldest trace information.

After the trace buffer becomes full, the trace information is no longer acquired. The user program is continuously executed.

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To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The AUD trace acquisition mode can be set in the [AUD mode1] or [AUD mode2] group box in the [Trace mode] page of the [Acquisition] dialog box.

Figure 2.3 [Trace mode] Page

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When the AUD trace function is used, select the [AUD function] radio button in the [Trace type] group box of the [Trace mode] page.

(a) Branch Trace Function

The branch source and destination addresses and their source lines are displayed.

Branch trace can be acquired by selecting the [Branch trace] check box in the [AUD function] group box of the [Trace mode] page.

The branch type can be selected in the [AUD Branch trace] page.

Figure 2.4 [AUD Branch trace] Page

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(b) Window Trace Function

Memory access in the specified range can be acquired by trace.

Two memory ranges can be specified for channels A and B. The read, write, or read/write cycle can be selected as the bus cycle for trace acquisition.

[Setting Method]

(i) Select the [Channel A] and [Channel B] check boxes in the [AUD function] group box of the [Trace mode] page. Each channel will become valid.

(ii) Open the [Window trace] page and specify the bus cycle, memory range, and bus type that are to be set for each channel.

Figure 2.5 [Window trace] Page

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Note: When [M-Bus] or [I-Bus] is selected, the following bus cycles will be traced.

•

M-Bus: A bus cycle generated by the CPU is acquired.

•

I-Bus: A bus cycle generated by the CPU or DMA is acquired.

(c) Software Trace Function

Note: This function can be supported with SHC/C++ compiler (manufactured by Renesas

Electronics Corp.; including OEM and bundle products) V7.0 or later.

When a specific instruction is executed, the PC value at execution and the contents of one general register are acquired by trace. Describe the Trace(x) function (x is a variable name) to be compiled and linked beforehand. For details, refer to the SHC manual.

When the load module is downloaded on the target system and is executed while a software trace function is valid, the PC value that has executed the Trace(x) function, the general register value for x, and the source lines are displayed.

To activate the software trace function, select the [Software trace] check box in the [AUD function] group box of the [Trace mode] page.

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Notes on AUD Trace:

1. When the trace display is performed during user program execution, the mnemonics, operands, or source is not displayed.

2. The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses. The window trace function outputs the differences between newly output addresses and previously output addresses. If the previous branch source address is the same as the upper 16 bits, the lower 16 bits are output. If it matches the upper 24 bits, the lower 8 bits are output. If it matches the upper 28 bits, the lower

4 bits are output.

The emulator regenerates the 32-bit address from these differences and displays it in the

[Trace] window. If the emulator cannot display the 32-bit address, it displays the difference from the previously displayed 32-bit address.

3. If the 32-bit address cannot be displayed, the source line is not displayed.

4. If a completion-type exception occurs during exception branch acquisition, the next address to the address in which an exception occurs is acquired.

5. The AUD trace is disabled while the profiling function is used.

6. Set the AUD clock (AUDCK) frequency to 40 MHz or lower. If the frequency is higher than

40 MHz, the emulator will not operate normally.

7. If breaks occur immediately after executing non-delayed branch and TRAPA instructions and generating a branch due to exception or interrupt, a trace for one branch will not be acquired immediately before such breaks. However, this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition.

2.2.3

Note on Using the JTAG (H-UDI) Clock (TCK)

1. Set the JTAG clock (TCK) frequency to lower than the frequency of the peripheral module clock (CKP) and to under 25 MHz.

2. The initial value for the JTAG clock (TCK) is 5 MHz.

3. A value to be set for the JTAG clock (TCK) is initialized after executing [Reset CPU] or

[Reset Go].

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2.2.4

Notes on Setting the [Breakpoint] Dialog Box

1. When an odd address is set, the next lowest even address is used.

2. A BREAKPOINT is accomplished by replacing instructions of the specified address.

It cannot be set to the following addresses:

−

An area other than CS and the internal RAM

−

An instruction in which Break Condition 2 is satisfied

−

A slot instruction of a delayed branch instruction

3. During step operation, specifying BREAKPOINTs and Event Condition breaks are disabled.

4. When execution resumes from the address where a BREAKPOINT is specified and a break occurs before Event Condition execution, single-step operation is performed at the address before execution resumes. Therefore, realtime operation cannot be performed.

5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot instruction of a delayed branch instruction.

6. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a mark z

will be displayed in the [BP] area of the address on the [Source] or [Disassembly] window by refreshing the [Memory] window, etc. after Go execution. However, no break will occur at this address. When the program halts with the event condition, the mark z disappears.

7. If you wish to use a BREAKPOINT (software break), specify the SH2A_SBSTK command to enable use of a user stack before setting a PC break. While enabled, extra four bytes of a user stack are used when a break occurs. The value of the stack pointer (R15) must be correctly set in advance because a user stack is to be used. By default, use of a user stack is disabled. For details on the command, refer to the help file.

•

Example

To enable use of a user stack:

>SH2A_SBSTK enable

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2.2.5

Notes on Setting the [Event Condition] Dialog Box and the BREAKCONDITION_

SET Command

1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Event

Condition 3 are disabled.

2. When an Event Condition is satisfied, emulation may stop after two or more instructions have been executed.

2.2.6

Performance Measurement Function

The emulator supports the performance measurement function.

1. Setting the performance measurement conditions

To set the performance measurement conditions, use the [Performance Analysis] dialog box and the PERFORMANCE_SET command. When any line in the [Performance Analysis] window is clicked with the right mouse button, a popup menu is displayed and the

[Performance Analysis] dialog box can be displayed by selecting [Setting].

Note: For the command line syntax, refer to the online help.

(a) Specifying the measurement start/end conditions

The measurement start/end conditions are specified by using Event Condition 1,2. The

[Ch1,2,3] list box of the [Combination action (Sequential or PtoP)] dialog box can be used.

Table 2.16 Measurement Period

Classification Item

Selection in the [Ch1, 2, 3] list box

Ch2 to Ch1

PA

Ch1 to Ch2

PA

Description

The period from the satisfaction of the condition set in Event

Condition 2 (start condition) to the satisfaction of the condition set in Event Condition 1 (end condition) is set as the performance measurement period.

The period from the satisfaction of the condition set in Event

Condition 1 (start condition) to the satisfaction of the condition set in Event Condition 2 (end condition) is set as the performance measurement period. above occurrence of a break is measured.

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Figure 2.6 [Performance Analysis] Dialog Box

For measurement tolerance,

•

The measured value includes tolerance.

•

Tolerance will be generated before or after a break.

Note: When [Ch2 to Ch1 PA] or [Ch1 to Ch2 PA] is selected, to execute the user program, specify conditions set in Event Condition 2 and Event Condition 1 and one or more items for performance measurement.

(b) Measurement item

Items are measured with [Channel 1 to 4] in the [Performance Analysis] dialog box.

Maximum four conditions can be specified at the same time.

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Table 2.17 Measurement Item

Selected Name Option

Disabled None

Elapsed time AC (the number of execution cycles (I

φ

))

Branch instruction counts

Number of execution instructions

Number of execution 32bit-instructions

Exception/interrupt counts

Interrupt counts

BT

I

I32

EA

INT

Data cache-miss counts

Instruction cache-miss counts

All area access counts

All area instruction access counts

All area data access counts

Cacheable area access counts

Cacheable area instruction access counts

DC

IC

ARN

ARIN

ARND

CDN (data access)

CIN

Non cacheable area data access counts

URAM area access counts

URAM area instruction access counts

URAM area data access counts

Internal I/O area data access counts

Internal ROM area access counts

Internal ROM area instruction access counts

Internal ROM area data access counts

NCN

UN

UIN

UDN

IODN

RN

RIN

RDN

All area access cycle

All area instruction access cycle

All area data access cycle

All area access stall

ARC

ARIC

ARDC

ARS

All area instruction access stall ARIS

All area data access stall ARDS

Note: Selected names are displayed for CONDITION in the [Performance Analysis] window.

Options are parameters for <mode> of the PERFORMANCE_SET command.

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Notes: 1. In the non-realtime trace mode of the AUD trace, normal counting cannot be performed because the generation state of the stall or the execution cycle is changed.

2. For SH7214 and SH7216 group, do not set measurement items for the cache-miss counts, cacheable area, or non-cacheable area.

2. Displaying the measured result

The measured result is displayed in the [Performance Analysis] window or the

PERFORMANCE_ANALYSIS command with hexadecimal (32 bits).

Note: If a performance counter overflows as a result of measurement, “********” will be displayed.

3. Initializing the measured result

To initialize the measured result, select [Initialize] from the popup menu in the [Performance

Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command.

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Supplementary Information on Using the SH7214 and

SH7216

Publication Date: Rev.1.00, Jan 13, 2010

Rev.3.00, Jun 04, 2013

Published by: Renesas Electronics Corporation

SALES OFFICES

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada

Tel: +1-905-898-5441, Fax: +1-905-898-3220

Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-651-700, Fax: +44-1628-651-804

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-65030, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China

Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898

Renesas Electronics Hong Kong Limited

Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2886-9318, Fax: +852 2886-9022/9044

Renesas Electronics Taiwan Co., Ltd.

13F, No. 363, Fu Shing North Road, Taipei, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics Korea Co., Ltd.

11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com

Colophon 1.3



Supplementary Information on Using the SH7214 and SH7216

R20UT2160EJ0300

SuperH Family E10A-USB Emulator Supplementary Information on Using the SH7214 and SH7216 Additional Document for User's Manual

SuperH™ Family E10A-USB Emulator

Supplementary Information on Using the SH7214 and SH7216

Additional Document for User’s Manual

SuperH

Family / SH7216 Series

E10A-USB for SH7216 HS7216KCU01HE

Regulatory Compliance Notices

Table of Contents

Section 1 Connecting the Emulator with the User System

1.1

Components of the Emulator

1.2

Connecting the Emulator with the User System

1.3

Installing the H-UDI Port Connector on the User System

1.4

Pin Assignments of the H-UDI Port Connector

1.5

Recommended Circuit between the H-UDI Port Connector and the

MCU

Section 2 Software Specifications when Using the SH7214 and SH7216 Group

2.1

Differences between the MCU and the Emulator

2.2

Specific Functions for the Emulator when Using the SH7214 and

SH7216 Group