Cypress Semiconductor | CY8C21x34 | User manual | PSoC® Mixed-Signal Array Final Data Sheet CY8C21234

PSoC® Mixed-Signal Array

CY8C21234, CY8C21334,

CY8C21434, CY8C21534, and CY8C21634

Final Data Sheet

Features

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz

❐ Low Power at High Speed

❐ 2.4V to 5.25V Operating Voltage

❐ Operating Voltages Down to 1.0V Using

On-Chip Switch Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC Blocks)

❐ 4 Analog Type “E” PSoC Blocks Provide:

- 2 Comparators with DAC Refs

- Single or Dual 8-Bit 28 Channel ADC

❐ 4 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Full-Duplex UART, SPI

™ Master or Slave

- Connectable to All GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Flexible On-Chip Memory

❐ 8K Flash Program Storage 50,000 Erase/Write

Cycles

❐ 512 Bytes SRAM Data Storage

❐ In-System Serial Programming (ISSP™)

❐ Partial Flash Updates

❐ Flexible Protection Modes

❐ EEPROM Emulation in Flash

■ Complete Development Tools

❐ Free Development Software

(PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

❐ 128K Trace Memory

■ Precision, Programmable Clocking

❐ Internal ±2.5% 24/48 MHz Oscillator

❐ Internal Oscillator for Watchdog and Sleep

■ Programmable Pin Configurations

❐ 25 mA Drive on All GPIO

❐ Pull Up, Pull Down, High Z, Strong, or Open

Drain Drive Modes on All GPIO

❐ Up to 8 Analog Inputs on GPIO

❐ Configurable Interrupt on All GPIO

■ Versatile Analog Mux

❐ Common Internal Analog Bus

❐ Simultaneous Connection of IO Combinations

❐ Capacitive Sensing Application Capability

■ Additional System Resources

❐ I 2

C™ Master, Slave and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers

❐ User-Configurable Low Voltage Detection

❐ Integrated Supervisory Circuit

❐ On-Chip Precision Voltage Reference

PSoC® Functional Overview

The PSoC® family consists of many Mixed-Signal Array with

On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A

PSoC device includes configurable blocks of analog and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts.

The PSoC architecture, as illustrated on the left, is comprised of four main areas: the Core, the System Resources, the Digital

System, and the Analog System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects.

The PSoC Core

The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The

January 12, 2007 © Cypress Semiconductor Corp. 2004-2007 — Document No. 38-12025 Rev. *K 1

CY8C21x34 Final Data Sheet PSoC® Overview

CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor.

System Resources provide additional capability, such as digital clocks to increase the flexibility of the PSoC mixed-signal arrays, I2C functionality for implementing an I2C master, slave,

MultiMaster, an internal voltage reference that provides an absolute value of 1.3V to a number of PSoC subsystems, a switch mode pump (SMP) that generates normal operating voltages off a single battery cell, and various system resets supported by the M8C.

The Digital System is composed of an array of digital PSoC blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global buses that can route any signal to any pin. Freeing designs from the constraints of a fixed peripheral controller.

The Analog System is composed of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to

8 bits in precision.

The Digital System

■

■

■

■

■

■

■

■

■

■

The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.

PWMs (8 to 32 bit)

PWMs with Dead band (8 to 32 bit)

Counters (8 to 32 bit)

Timers (8 to 32 bit)

UART 8 bit with selectable parity

SPI master and slave

I2C slave and multi-master

Cyclical Redundancy Checker/Generator (8 to 32 bit)

IrDA

Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled “PSoC Device Characteristics” on page 3 .

8

8

Digital System Block Diagram

Port 3 Port 1

Port 2 Port 0

Digital Clocks

From Core

To System Bus To Analog

System

GIE[7:0]

GIO[7:0]

DIGITAL SYSTEM

Digital PSoC Block Array

Row 0 4

DBB00 DBB01 DCB02 DCB03

4

Global Digital

Interconnect

GOE[7:0]

GOO[7:0]

8

8

The Analog System

The Analog System is composed of 4 configurable blocks, allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are listed below.

■

■

■ Analog-to-digital converters (single or dual, with 8-bit resolution)

Pin-to-pin comparator

Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference

■ 1.3V reference (as a System Resource)

In most PSoC devices, analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC

(Switched Capacitor) blocks. The CY8C21x34 devices provide limited functionality Type “E” analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Mixed-Signal Array Technical Reference Manual for detailed information on the CY8C21x34’s Type E analog blocks.

January 12, 2007 Document No. 38-12025 Rev. *K 2


Array Input

Configuration

X

X

X

X

All IO

X

Analog System Block Diagram

ACI0[1:0]

ACOL1MUX

Analog Mux Bus

ACE00

Array

ACE01

ASE10

ACI1[1:0]

ASE11

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that allows analog input from any IO pin.

■ Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the signal-to-noise system level requirement found in Application

Note AN2403 at http://www.cypress.com/design/AN2403 on the

Cypress web site.

Additional System Resources

System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.

■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■ The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR

(Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter.

■ Versatile analog multiplexer system.

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below.

PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C27x43

CY8C24x94

CY8C24x23A

CY8C21x34 up to

64 up to

44

56 up to

24 up to

28

16

4

2

1

1

1

16

8

4

4

4

12

28

CY8C21x23 1 4 8

CY8C20x34 up to

28

0 0 28 a.

Limited analog functionality

.

b. Two analog blocks and one CapSense.

12

48

12

4

4

2

2

0

0

0

2

2

0

4

4

2

2

12

6

6

12

4 a

4 a

3 b

2K 32K

256

Bytes

1K

256

Bytes

512

Bytes

256

Bytes

512

Bytes

16K

16K

4K

8K

4K

8K



Getting Started

The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated

Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the

PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc.

For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com.

Development Kits

Development Kits are available from the following distributors:

Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for

PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Program-

mable System-on-Chip) to view a current list of available items.

Technical Training Modules

Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http:// www.cypress.com/techtrain .

Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to http://www.cypress.com, click on Design

Support located on the left side of the web page, and select

CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm

.

Application Notes

A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com

web site and select Application

Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default.

Development Tools

PSoC Designer is a Microsoft ® Windows-based, integrated development environment for the Programmable System-on-

Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium

(Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the

PSoC, and debug the application. This system provides design database management by project, an integrated debugger with

In-Circuit Emulator, in-system programming support, and the

CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

PSoC Designer Subsystems



PSoC Designer Software Subsystems

Device Editor

The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs,

DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It’s also possible to change the selected components and regenerate the framework.

Design Browser

The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design.

Examples provided in the tools include a 300-baud modem, LIN

Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit your C language and

Assembly language source code. You can also assemble, compile, link, and build.

Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24

MHz) operation.



Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.

Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User

Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC

Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.

User Module and Source Code Development Flows

User

Module

Selection

Device Editor

Placement and

Parameter

-ization

Source

Code

Generator

Project

Manager

Generate

Application

Application Editor

Source

Code

Editor

Build

Manager

Build

All

Debugger

Interface to ICE

Storage

Inspector

Event &

Breakpoint

Manager

The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.

The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.



Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

POR

PPOR

PSoC®

PWM

SC

SLIMO

SMP

SRAM

IMO

IO

IPOR

LSb

LVD

MSb

PC

PLL

Acronym

AC

ADC

API

CPU

CT

DAC

DC

ECO

EEPROM

FSR

GPIO

GUI

HBM

ICE

ILO

Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset

Programmable System-on-Chip™ pulse width modulator switched capacitor slow IMO switch mode pump static random access memory

Units of Measure

A units of measure table is located in the Electrical Specifica-

tions section. Table 3-1 on page 17

lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).

Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

6.

7.

Table of Contents

For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Refer-

ence Manual on http://www.cypress.com

. This document is organized into the following chapters and sections.

1.

2.

3.

4.

5.

Pin Information ........................................................................................ 8

1.1

Pinouts ........................................................................................... 8

1.1.1

16-Pin Part Pinout .......................................................... 8

1.1.2

1.1.3

20-Pin Part Pinout .......................................................... 9

28-Pin Part Pinout ........................................................ 10

1.1.4

1.1.5

32-Pin Part Pinout ........................................................ 11

56-Pin Part Pinout ......................................................... 12

Register Reference ................................................................................ 14

2.1

Register Conventions ................................................................... 14

2.2

Register Mapping Tables ............................................................. 14

Electrical Specifications ....................................................................... 17

3.1

Absolute Maximum Ratings ......................................................... 18

3.2

Operating Temperature ................................................................ 18

3.3

DC Electrical Characteristics ........................................................ 18

3.3.1

3.3.2

3.3.3

3.3.4

DC Chip-Level Specifications ........................................ 18

DC General Purpose IO Specifications ......................... 19

DC Operational Amplifier Specifications ....................... 20

DC Low Power Comparator Specifications ................... 20

3.3.5

3.3.6

3.3.7

3.3.8

DC Switch Mode Pump Specifications .......................... 21

DC Analog Mux Bus Specifications ............................... 22

DC POR and LVD Specifications .................................. 22

DC Programming Specifications ................................... 23

3.4

AC Electrical Characteristics ........................................................ 24

3.4.1

AC Chip-Level Specifications ........................................ 24

3.4.2

3.4.3

AC General Purpose IO Specifications ......................... 26

AC Operational Amplifier Specifications ........................ 27

3.4.4

3.4.5

3.4.6

3.4.7

3.4.8

3.4.9

AC Low Power Comparator Specifications ................... 27

AC Analog Mux Bus Specifications ............................... 27

AC Digital Block Specifications ..................................... 27

AC External Clock Specifications .................................. 29

AC Programming Specifications .................................... 30

AC I2C Specifications .................................................... 31

Packaging Information .......................................................................... 32

4.1

Packaging Dimensions ................................................................. 32

4.2

Thermal Impedances .................................................................. 36

4.3

Solder Reflow Peak Temperature ................................................ 36

Development Tool Selection ................................................................ 37

5.1

Software ....................................................................................... 37

5.1.1

5.1.2

PSoC Designer............................................................... 37

PSoC Express‰ ........................................................... 37

5.1.3

5.1.4

PSoC Programmer ........................................................ 37

CY3202-C iMAGEcraft C Compiler ............................... 37

5.2

Development Kits ......................................................................... 37

5.2.1

CY3215-DK Basic Development Kit .............................. 37

5.2.2

CY3210-ExpressDK Development Kit ........................... 38

5.3

Evaluation Tools ........................................................................... 38

5.3.1

5.3.2

CY3210-MiniProg1 ........................................................ 38

CY3210-PSoCEval1 ...................................................... 38

5.3.3

CY3214-PSoCEvalUSB ................................................ 38

5.4

Device Programmers ................................................................... 38

5.4.1

5.4.2

CY3216 Modular Programmer ...................................... 38

CY3207ISSP In-System Programmer ........................... 38

5.5

Accessories (Emulation and Programming) ................................. 39

5.6

3rd-Party Tools ............................................................................. 39

5.7

Build a PSoC Emulator into Your Board ...................................... 39

Ordering Information ............................................................................ 40

6.1

Ordering Code Definitions ............................................................ 40

Sales and Service Information ............................................................. 41

7.1

Revision History ........................................................................... 41

7.2

Copyrights and Code Protection .................................................. 42


1.

Pin Information

This chapter describes, lists, and illustrates the CY8C21x34 PSoC device pins and pinout configurations.

1.1

Pinouts

The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

1.1.1

16-Pin Part Pinout

Table 1-1. 16-Pin Part Pinout (SOIC)

Pin

No.

1

2

3

4

5

Type

Digital Analog

IO I, M

IO

IO

IO

Power

I, M

I, M

I, M

Name Description

P0[7] Analog column mux input.


P0[3] Analog column mux input, integrating input.

P0[1] Analog column mux input, integrating input.

SMP Switch Mode Pump (SMP) connection to required external components.

8

9

6

7 IO

Power

Power

M

M

M

M

I, M

I, M

I, M

I, M

Vss Ground connection.

P1[1] I2C Serial Clock (SCL), ISSP-SCLK*.

Vss Ground connection.

P1[0] I2C Serial Data (SDA), ISSP-SDATA*.

10

11

12

13

14

15

IO

IO

IO

IO

IO

IO

IO

P1[2]

P1[4] Optional External Clock Input (EXTCLK).

P0[0]

P0[2]

Analog column mux input.




16 Power Vdd Supply voltage.

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

* These are the ISSP pins, which are not High Z at POR (Power On Reset).

See the PSoC Mixed-Signal Array Technical Reference Manual for details.

CY8C21234 16-Pin PSoC Device

A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

SMP

Vss

M, I2C SCL, P1[1]

Vss

1

2

3

4

5

6

7

8

SOIC

16

15

14

13

12

11

10

9

Vdd

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

P1[4], EXTCLK, M

P1[2], M

P1[0], I2C SDA, M


CY8C21x34 Final Data Sheet

1.1.2

20-Pin Part Pinout

Table 1-2. 20-Pin Part Pinout (SSOP)

8

9

10

11

5

6

7

12

13

Pin

No.

1

2

3

4

14

15

16

17

18

19

Type

Digital Analog

IO I, M

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

Power

Power

Input

I, M

I, M

I, M

M

M

M

M

M

M

M

M

I, M

I, M

I, M

I, M

Name

P0[7]

P0[5]

P0[3]

P0[1]

Vss

P1[7]

P1[5]

P1[3]

P1[1]

Vss

P1[0]

P0[0]

P0[2]

P0[4]

P0[6]

Description



Analog column mux input, integrating input.


Ground connection.

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

I2C Serial Clock (SCL), ISSP-SCLK*.

Ground connection.

I2C Serial Data (SDA), ISSP-SDATA*.

P1[2]

P1[4] Optional External Clock Input (EXT-

CLK).

P1[6]

XRES Active high external reset with internal pull down.









1. Pin Information


A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

Vss

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

Vss

1

2

3

6

7

4

5

8

9

10

SSOP

20

19

15

14

13

12

18

17

16

11

Vdd

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

XRES

P1[6], M

P1[4], EXTCLK, M

P1[2], M

P1[0], I2C SDA, M



1.1.3

28-Pin Part Pinout


Pin

No.

1

2

3

4

IO

IO

IO

IO

Type

Digital Analog

I, M

I, M

I, M

I, M

Name

P0[7]

P0[5]

P0[3]

P0[1]

Description


Analog column mux input and column output.

Analog column mux input and column output, integrating input.


12

13

14

15

16

17

8

9

10

11

5

6

7

18

19

24

25

26

27

20

21

22

23

IO

IO

IO

M

M

I, M

IO

Power

I, M

IO

IO

M

M

IO

IO

M

M

Power

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

Input

M

M

M

M

I, M

I, M

M

M

I, M

I, M

I, M

I, M

P2[7]

P2[5]

P2[3]

P2[1]

Vss

P1[7]

P1[5]

P1[3]

P1[1]

Vss

P1[0]

P1[2]

P1[4]

Direct switched capacitor block input.


Ground connection.



P1[6]


P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]


Ground connection.


Optional External Clock Input (EXT-

CLK).





Analog column mux input



LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.





A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

Vss

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

Vss

10

11

7

8

9

12

13

14

1

4

5

6

2

3

SSOP

22

21

20

19

18

17

16

15

25

24

23

28

27

26

Vdd

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

P2[6], M

P2[4], M

P2[2], M

P2[0], M

XRES

P1[6], M

P1[4], EXTCLK, M

P1[2], M

P1[0], I2C SDA, M



1.1.4

32-Pin Part Pinout

10

11

12

13

8

9

7

7

14

15

16

4

5

2

3

6

6

Table 1-4. 32-Pin Part Pinout (QFN**)

Pin

No.

1

Type

Digital Analog

IO I, M

Name

P0[1]

Description


IO

IO

IO

IO

IO

Power

M

M

M

M

M

P2[7]

P2[5]

P2[3]

P2[1]

P3[3]

SMP

IO

IO

IO

IO

IO

Power

M

IO

IO

IO

IO

M

M

M

M

Power

M

M

M

M

P3[1]

Vss

P1[7]

P1[5]

P1[3]

P1[1]

Vss

P1[0]

P1[2]

P1[4]

P1[6]

In CY8C21434 part.

Switch Mode Pump (SMP) connection to required external components in

CY8C21634 part.

In CY8C21434 part.

Ground connection in CY8C21634 part.




Ground connection.


Optional External Clock Input (EXTCLK).

17 Input XRES Active high external reset with internal pull down.

26

27

28

29

30

31

22

23

24

25

18

19

20

21

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

I, M

I, M

IO

Power

I, M

IO

IO

M

M

I, M

I, M

M

M

M

M

I, M

I, M

P3[0]

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

P0[7]

P0[5]

P0[3]





Supply voltage.




32 Power Vss Ground connection.




** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.





CY8C21x34 Final Data Sheet 1. Pin Information

1.1.5

56-Pin Part Pinout

The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.


17

18

19

20

21

22

23

24

25

26

27

32

37

38

39

40

41

33

34

35

36

45

46

47

42

43

44

28

29

30

31

Pin

No.

12

13

14

15

16

8

9

10

11

6

7

4

5

1

2

3

Type

Digital Analog

Power

IO

IO

IO

IO

I

I

I

I

IO

IO

IO

IO

I

I

OCD

OCD

Power

IO

IO

Power

Power

IO

IO

IO

IO

IO

IO

IO

IO

OCD

OCD

IO

IO

Power

Input

Pin

Name

Description

Vss

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

Ground connection.





P2[3]

P2[1]

NC

NC



No connection.

No connection..

NC

NC

OCDE OCD even data IO.

OCDO OCD odd data output.

SMP

No connection.

No connection..

Vss

Switch Mode Pump (SMP) connection to required external components.

Ground connection.

Ground connection.

Vss

P3[3]

P3[1]

NC No connection.

NC

P1[7]

P1[5]

No connection..



NC

P1[3]

P1[1]

No connection.

I

FMTEST

.

Crystal Input (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK*.

Ground connection.

Vss

NC

NC

P1[0]

No connection.

No connection..

P1[2]

Crystal Output (XTALout), I2C Serial Data

(SDA), ISSP-SDATA*.

V

FMTEST

.

Optional External Clock Input (EXTCLK).

P1[4]

P1[6]

NC

NC

NC

NC

NC

NC

No connection..

No connection.

No connection..

No connection.

No connection..

No connection..


HCLK OCD high-speed clock output.

OCD CPU clock output.

CCLK

P3[0]

P3[2]

NC

NC

No connection.

No connection..


P3[3]

P3[1]

NC

NC

I2C SCL, P1[7]

I2C SDA, P1[5]

NC

P1[3]

SCLK, I2C SCL, P1[1]

Vss

NC

NC

NC

OCDE

OCDO

SMP

Vss

Vss

Vss

AI, P0[7]

AI, P0[5]

AI, P0[3]

AI, P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

NC

14

15

16

17

11

12

13

7

8

9

10

5

6

3

4

1

2

18

19

20

21

22

23

24

25

26

27

28

SSOP 43

42

41

40

39

38

37

36

35

34

33

32

31

30

50

49

48

47

46

45

44

29

56

55

54

53

52

51

Not for Production

Vdd

P0[6], AI

P0[4], AI

P0[2], AI

P0[0], AI

P2[6]

P2[4]

P2[2]

P2[0]

NC

NC

P3[2]

P3[0]

CCLK

HCLK

XRES

NC

NC

NC

NC

NC

NC

P1[6]

P1[4], EXTCLK

P1[2]

P1[0], I2C SDA, SDATA

NC

NC


CY8C21x34 Final Data Sheet 1. Pin Information


51

52

53

54

48

49

50

55

56

IO

IO

IO

IO

IO

IO

IO

IO

Power

I

I

I

I

I

I

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd





Supply voltage.

LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.

* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.


2.

Register Reference

This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, reference the

PSoC Mixed-Signal Array Technical Reference Manual.

2.1

Register Conventions

The register conventions specific to this section are listed in the following table.

L

C

R

W

#

Convention Description

Read register or bit(s)

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

2.2

Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are

Reserved and should not be accessed.



Register Map 0 Table: User Space

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

10

11

12

13

0C

0D

0E

0F

08

09

0A

0B

04

05

06

07

18

19

1A

1B

1C

14

15

16

17

00

01

02

03

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

29

2A

2B

2C

25

26

27

28

21

22

23

24

1D

1E

1F

20

31

32

33

34

35

2D

2E

2F

30

#

W

RW

#

#

W

RW

#

#

W

RW

#

#

W

RW

#

AMX_IN

AMUXCFG

PWM_CR

CMP_CR0

CMP_CR1

ADC0_CR

ADC1_CR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACE00CR1

ACE00CR2

69

6A

6B

6C

65

66

67

68

61

62

63

64

5D

5E

5F

60

71

72

73

74

75

6D

6E

6F

70

RW

RW

RW

#

RW

#

#

RW

RW

RW

RW

RW

RW

3A

3B

3C

3D

36

37

38

39

ACE01CR1

ACE01CR2

3E

3F

7E

7F

Blank fields are Reserved and should not be accessed.

7A

7B

7C

7D

76

77

78

79

RW

RW

50

51

52

53

4C

4D

4E

4F

48

49

4A

4B

44

45

46

47

58

59

5A

5B

5C

54

55

56

57

40

41

42

43

ASE10CR0

ASE11CR0

RW

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

A9

AA

AB

AC

A5

A6

A7

A8

A1

A2

A3

A4

9D

9E

9F

A0

B1

B2

B3

B4

B5

AD

AE

AF

B0

RDI0RO1

BA

BB

BC

BD

B6

B7

B8

B9

BE

BF

# Access is bit specific.

RW

RW

RW

RW

RW

RW

RW

90

91

92

93

8C

8D

8E

8F

88

89

8A

8B

84

85

86

87

98

99

9A

9B

9C

94

95

96

97

80

81

82

83

CUR_PP

STK_PP

IDX_PP

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

INT_CLR3

INT_MSK3

INT_MSK0

INT_MSK1

INT_VC

RES_WDT

DEC_CR0

DEC_CR1

CPU_F

DAC_D

CPU_SCR1

CPU_SCR0

E9

EA

EB

EC

E5

E6

E7

E8

E1

E2

E3

E4

DD

DE

DF

E0

F1

F2

F3

F4

F5

ED

EE

EF

F0

FA

FB

FC

FD

F6

F7

F8

F9

FE

FF

D0

D1

D2

D3

CC

CD

CE

CF

C8

C9

CA

CB

C4

C5

C6

C7

D8

D9

DA

DB

DC

D4

D5

D6

D7

C0

C1

C2

C3

RW

RW

RW

RW

RW

RW

#

RW

#

RW

RW

RW

RW

RW

RW

RC

W

RW

RW

RL

RW

#

#

January 12, 2007 Document No. 38-12025 Rev. *K

2. Register Reference

15


Register Map 1 Table: Configuration Space

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

DBB00FN

DBB00IN

DBB00OU

DBB01FN

DBB01IN

DBB01OU

DCB02FN

DCB02IN

DCB02OU

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

1F

20

21

22

1B

1C

1D

1E

17

18

19

1A

13

14

15

16

27

28

29

2A

2B

23

24

25

26

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

5F

60

61

62

63

CMP_GO_EN 64

AMD_CR1

ALT_CR0

65

66

67

68

5B

5C

5D

5E

CLK_CR3

57

58

59

5A

53

54

55

56

69

6A

6B

4C

4D

4E

4F

48

49

4A

4B

44

45

46

47

40

41

42

43

50

51

52

RW

RW

RW

RW

RW

RW

RW

DCB03FN

DCB03IN

DCB03OU

38

39

3A

3B

34

35

36

37

30

31

32

33

2C

2D

2E

2F

RW

RW

RW

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACE00CR1

ACE00CR2

ACE01CR1

ACE01CR2

3C

3D

3E

3F

7C

7D

7E

7F

Blank fields are Reserved and should not be accessed.

70

71

72

73

6C

6D

6E

6F

78

79

7A

7B

74

75

76

77

RW

RW

RW

RW

RW

RW

RW

RW

RW

ASE10CR0

ASE11CR0

RW

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

B8

B9

BA

BB

B4

B5

B6

B7

B0

B1

B2

B3

AC

AD

AE

AF

BC

BD

BE

BF

# Access is bit specific.

RW

RW

RW

RW

RW

RW

RW

9F

A0

A1

A2

9B

9C

9D

9E

97

98

99

9A

93

94

95

96

A7

A8

A9

AA

AB

A3

A4

A5

A6

8C

8D

8E

8F

88

89

8A

8B

84

85

86

87

80

81

82

83

90

91

92

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3 DB

DC

OSC_GO_EN DD

OSC_CR4 DE

D7

D8

D9

DA

D3

D4

D5

D6

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

VLT_CMP

ADC0_TR

ADC1_TR

E3

E4

E5

E6

DF

E0

E1

E2

IMO_TR

ILO_TR

BDG_TR

ECO_TR

E7

E8

E9

EA

EB

CPU_F

FLS_PR1

DAC_CR

CPU_SCR1

CPU_SCR0

CC

CD

CE

CF

C8

C9

CA

CB

C4

C5

C6

C7

C0

C1

C2

C3

D0

D1

D2

F8

F9

FA

FB

F4

F5

F6

F7

FC

FD

FE

FF

F0

F1

F2

F3

EC

ED

EE

EF

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

R

RW

RW

W

W

RW

W

RL

RW

RW

#

#

January 12, 2007 Document No. 38-12025 Rev. *K

2. Register Reference

16

3.

Electrical Specifications

This chapter presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40 o C

≤ T

A

≤ 85 o C and T

J

≤ 100 o C as specified, except where noted.

Refer to Table 3-15 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options

5.25

5.25

SLIMO

Mode=1

SLIMO

Mode=0

4.75

O

R eg pe io n

V ra tin ali g d

4.75

3.00

2.40

3.60

3.00

2.40

SLIMO

Mode=1

SLIMO

Mode=1

SLIMO

Mode=1

SLIMO

Mode=0

93 kHz 3 MHz 12 MHz

CPU Frequency

24 MHz 93 kHz 6 MHz 12 MHz

IM O Frequency

24 MHz

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol o C dB fF

Hz

KB

Kbit kHz k

Ω

MHz

M

Ω

µA

µF

µH

µs

µV

µVrms

Unit of Measure degree Celsius decibels femto farad hertz

1024 bytes

1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square pA pF pp ppm ps sps

σ

V

Symbol

µW mA ms mV nA ns nV

Ω

Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts


CY8C21x34 Final Data Sheet 3. Electrical Specifications

T

A

Vdd

V

IO

V

IOZ

I

MIO

ESD

LU

3.1

Absolute Maximum Ratings

Table 3-2. Absolute Maximum Ratings

Symbol

T

STG

Storage Temperature

Description

-55

Min

Ambient Temperature with Power Applied

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

DC Voltage Applied to Tri-state

Maximum Current into any Port Pin

Electro Static Discharge Voltage

Latch-up Current

-40

-0.5

Vss - 0.5

–

Vss - 0.5

–

–

–

-25

2000

–

–

–

–

25

Typ Max

+100

+85

+6.0

Vdd + 0.5 V

Vdd + 0.5 V o C

V

+50

–

200 mA

V mA o C

Units Notes

Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25 o C ± 25 o C. Extended duration storage temperatures above 65 o C will degrade reliability.

Human Body Model ESD.

3.2

Operating Temperature

Table 3-3. Operating Temperature

Symbol

T

A

T

J

Ambient Temperature

Junction Temperature

Description

-40

Min

-40

–

–

Typ Max

+85

+100 o C

Units o C

Notes

The temperature rise from ambient to junction is package specific. See

“Thermal Impedances” on page 36

. The user must limit the power consumption to comply with this requirement.

3.3

DC Electrical Characteristics

3.3.1

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A

≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-4. DC Chip-Level Specifications

Symbol

Vdd Supply Voltage

Description Min

2.40

–

Typ Max

5.25

I

DD

I

DD3

I

DD27

I

SB27

I

SB

V

REF

Supply Current, IMO = 24 MHz

Supply Current, IMO = 6 MHz using SLIMO mode.

Supply Current, IMO = 6 MHz using SLIMO mode.

–

–

–

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active.

Reference Voltage (Bandgap)

–

–

1.28

3

1.2

1.1

2.6

2.8

1.30

4

2

1.5

4.

5

1.32

µA

µA

V

V

Units mA mA mA

Notes

See table titled “DC POR and LVD Specifications” on page 22

.

Conditions are Vdd = 5.0V, T

A

= 25 o C, CPU = 3

MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 =

93.75 kHz, VC3 = 0.366 kHz.


A

= 25 o C, CPU = 3

MHz, clock doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz.


A

= 25 o C, CPU = 3

MHz, clock doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz.

Vdd = 2.55V, 0 o C

≤ T

A

≤ 40 o C.

Vdd = 3.3V, -40 o C

≤ T

A

≤ 85 o C.

Trimmed for appropriate Vdd. Vdd = 3.0V to

5.25V.



Table 3-4. DC Chip-Level Specifications (continued)

Symbol

V

REF27

Description

Reference Voltage (Bandgap)

AGND Analog Ground

Min

1.16

V

REF

- 0.003

Typ

1.30

V

REF

Max

1.33

V

REF

+ 0.003

V

Units Notes

Trimmed for appropriate Vdd. Vdd = 2.4V to

3.0V.

V

3.3.2

DC General Purpose IO Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A

≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 3-5. 5V and 3.3V DC GPIO Specifications

Symbol

R

PU

R

PD

V

OH

Pull-up Resistor

Pull-down Resistor

High Output Level

Description

V

OL

V

IL

V

IH

V

H

I

IL

C

IN

C

OUT

Low Output Level

Input Low Level

Input High Level

Input Hysteresis

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

–

–

–

–

2.1

–

4

4

Min

5.6

5.6

Vdd - 1.0

–

Typ

–

–

–

60

1

3.5

3.5

–

–

10

10

8

8

–

Max

0.75

0.8

V

V mV nA pF pF

Units k

Ω k

Ω

V

V

Notes

IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

Vdd = 3.0 to 5.25.

Vdd = 3.0 to 5.25.

Gross tested to 1

µA.

Package and pin dependent. Temp = 25 o C.


Table 3-6. 2.7V DC GPIO Specifications

Symbol

R

PU

R

PD

V

OH

Pull-up Resistor

Pull-down Resistor

High Output Level

Description

V

OL

V

IL

V

IH

V

H

I

IL

C

IN

C

OUT

Low Output Level

Input Low Level

Input High Level

Input Hysteresis

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

–

–

–

–

2.0

–

4

4

Min

5.6

5.6

Vdd - 0.4

–

Typ

8

8

–

Max

–

–

–

90

1

3.5

3.5

0.75

0.75

–

–

–

10

10

V

V mV nA pF pF

Units k

Ω k

Ω

V

V

Notes

IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget).

IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget).

Vdd = 2.4 to 3.0.

Vdd = 2.4 to 3.0.

Gross tested to 1

µA.

Package and pin dependent. Temp = 25 o

Package and pin dependent. Temp = 25 o

C.

C.



3.3.3

DC Operational Amplifier Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-7. 5V DC Operational Amplifier Specifications

Symbol

V

OSOA

TCV

OSOA

I

EBOAa

C

INOA

V

CMOA

Description

Input Offset Voltage (absolute value)

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

–

–

–

–

0.0

Min Typ

2.5

10

200

4.5

–

–

–

15

Max

9.5

Vdd - 1 pA pF

V

Units mV

µV/ o C

Notes

Gross tested to 1

µA.


G

OLOA

I

SOA

Open Loop Gain

Amplifier Supply Current

–

–

80

10

–

30 dB

µA a. Atypical behavior: I

EBOA

of Port 0 Pin 0 is below 1 nA at 25 ° C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

Table 3-8. 3.3V DC Operational Amplifier Specifications

Symbol

V

OSOA

TCV

OSOA

I

EBOAa

C

INOA

V

CMOA

G

OLOA

I

SOA

Description






Open Loop Gain


–

–

–

0

–

–

–

Min Typ

2.5

10

200

4.5

–

80

10

15

–

Max

–

9.5

pF

Vdd - 1 V

–

30 dB

µA

Units mV

µV/ o C pA

Notes

Gross tested to 1

µA.


a. Atypical behavior: I

EBOA


Table 3-9. 2.7V DC Operational Amplifier Specifications

Symbol

V

OSOA

TCV

OSOA

I

EBOAa

C

INOA

V

CMOA

G

OLOA

I

SOA

Description






Open Loop Gain


–

–

–

0

–

–

–

Min Typ

2.5

10

200

4.5

–

80

10

15

–

Max

–

9.5

pF

Vdd - 1 V

–

30 dB

µA

Units mV

µV/ o C pA

Notes

Gross tested to 1

µA.


a. Atypical behavior: I

EBOA


3.3.4

DC Low Power Comparator Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A

≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-10. DC Low Power Comparator Specifications

Symbol

V

REFLPC

I

SLPC

V

OSLPC

Description

Low power comparator (LPC) reference voltage range

LPC supply current

LPC voltage offset

–

–

0.2

Min

–

10

2.5

Typ Max

Vdd - 1

40

30

V

µA

Units mV

Notes



3.3.5

DC Switch Mode Pump Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-11. DC Switch Mode Pump (SMP) Specifications

Symbol

V

PUMP5V

Description

5V Output Voltage from Pump

Min

4.75

5.0

Typ Max

5.25

V

PUMP3V

V

PUMP2V

I

PUMP

V

BAT5V

V

BAT3V

V

BAT2V

V

BATSTART

∆V

PUMP_Line

∆V

PUMP_Load

3.3V Output Voltage from Pump

2.6V Output Voltage from Pump

Available Output Current

V

BAT

= 1.8V, V

PUMP

= 5.0V

V

BAT

= 1.5V, V

PUMP

= 3.25V

V

BAT

= 1.3V, V

PUMP

= 2.55V

Input Voltage Range from Battery



Minimum Input Voltage from Battery to Start Pump

Line Regulation (over Vi range)

Load Regulation

∆V

PUMP_Ripple

E

3

Output Voltage Ripple (depends on cap/load)

Efficiency

E

2

Efficiency

3.00

2.45

5

8

8

1.8

1.0

1.0

1.2

–

–

–

35

35

3.25

2.55

F

PUMP

DC

PUMP

Switching Frequency

Switching Duty Cycle

–

– a. L

1

= 2 µH inductor, C

1

= 10 µF capacitor, D

1

= Schottky diode. See Figure 3-2.

1.3

50

–

–

–

–

–

–

–

5

5

100

50

80

3.60

2.80

–

–

–

5.0

3.3

2.8

–

–

–

–

–

–

–

– mA mA mA

V

V

Units

V

V

V

V

V

%V

%V mVpp

%

%

O

O

Notes

Configuration of footnote.

a Average, neglecting ripple. SMP trip voltage is set to 5.0V.






a

SMP trip voltage is set to 5.0V.




a SMP trip voltage is set to 5.0V.






a 0 o C

≤ T

A

≤ 100.

1.25V at T

A

= -40 o C.


a V

O

is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting

in the DC POR and LVD Specification, Table 3-

13 on page 22

.


a V

O

is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting

in the DC POR and LVD Specification, Table 3-

13 on page 22

.


a Load is 5 mA.


a Load is 5 mA. SMP trip voltage is set to 3.25V.

For I load = 1mA, V

PUMP

= 2.55V, V

BAT

= 1.3V,

10 uH inductor, 1 uF capacitor, and Schottky diode.

MHz

%

Figure 3-2. Basic Switch Mode Pump Circuit

D1

Vdd V

PUMP

L

1

V

BAT

+

Battery

SMP

PSoC

Vss

C1



3.3.6

DC Analog Mux Bus Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-12. DC Analog Mux Bus Specifications

Symbol

R

SW

Description

Switch Resistance to Common Analog Bus

R

VDD

Resistance of Initialization Switch to Vdd

–

Min

–

–

Typ

–

Max

400

800

800

Ω

Ω

Ω

Units

Vdd

≥ 2.7V

2.4V

≤ Vdd ≤ 2.7V

Notes

3.3.7

DC POR and LVD Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-13. DC POR and LVD Specifications

V

LVD0

V

LVD1

V

LVD2

V

LVD3

V

LVD4

V

LVD5

V

LVD6

V

LVD7

Symbol

V

PPOR0

V

PPOR1

V

PPOR2

V

PUMP0

V

PUMP1

V

PUMP2

V

PUMP3

V

PUMP4

V

PUMP5

V

PUMP6

V

PUMP7

Description

Vdd Value for PPOR Trip

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

Vdd Value for PUMP Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

– a. Always greater than 50 mV above V

PPOR

(PORLEV = 00) for falling supply.

b. Always greater than 50 mV above V

PPOR

(PORLEV = 01) for falling supply.

c. Always greater than 50 mV above

V

LVD0

.

d. Always greater than 50 mV above

V

LVD3

.

Min

2.45

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

Typ

2.36

2.82

4.55

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.55

3.02

3.10

3.25

4.64

4.73

4.82

5.00

Max

2.40

2.95

4.70

2.62

c

3.09

3.16

3.32

d

4.74

4.83

4.92

5.12

2.51

a

2.99

b

3.09

3.20

4.55

4.75

4.83

4.95

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Units Notes

Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.



3.3.8

DC Programming Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-14. DC Programming Specifications

Symbol

Vdd

IWRITE

I

DDP

V

ILP

V

IHP

I

ILP

I

IHP

V

OLV

V

OHV

Flash

ENPB

Flash

ENT

Flash

DR

Description

Supply Voltage for Flash Write Operations

Supply Current During Programming or Verify

Input Low Voltage During Programming or Verify

Input High Voltage During Programming or Verify

Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify

Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify

Output Low Voltage During Programming or Verify

Output High Voltage During Programming or Verify

Flash Endurance (per block)

Flash Endurance (total) a

Flash Data Retention

–

–

2.70

Min

2.2

–

– –

– –

Vdd - 1.0

–

50,000 –

1,800,000 –

10 –

–

–

–

5

–

Typ

–

25

0.8

–

0.2

Max

1.5

V

V

V mA

Units mA mA

–

–

–

Vss + 0.75 V

Vdd V

–

–

Years

Notes

Driving internal pull-down resistor.

Driving internal pull-down resistor.

Erase/write cycles per block.

Erase/write cycles.

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than

50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.



3.4

AC Electrical Characteristics

3.4.1

AC Chip-Level Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-15. 5V and 3.3V AC Chip-Level Specifications

Symbol

F

IMO24

F

IMO6

Description

Internal Main Oscillator Frequency for 24 MHz


Min

23.4

5.75

24

Typ

6

Max Units

24.6

a,b,c MHz

6.35

a,b,c MHz

Notes

Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 17 . SLIMO mode = 0.

Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 17 . SLIMO mode = 1.

24 MHz only for SLIMO mode = 0.

F

CPU1

F

CPU2

F

BLK5

CPU Frequency (5V Nominal)

CPU Frequency (3.3V Nominal)

Digital PSoC Block Frequency 0 (5V Nominal)

0.93

0.93

0

24

12

48

24.6

a,b

12.3

b,c

49.2

a,b,d

MHz

MHz

MHz Refer to the AC Digital Block Specifications below.

F

BLK33

F

32K1

Jitter32k

Jitter32k

T

XRST

DC24M

Step24M

Fout48M

Jitter24M1

F

MAX

T

RAMP

Digital PSoC Block Frequency (3.3V Nominal)

Internal Low Speed Oscillator Frequency

32 kHz RMS Period Jitter

32 kHz Peak-to-Peak Period Jitter

External Reset Pulse Width

24 MHz Duty Cycle

24 MHz Trim Step Size

48 MHz Output Frequency

24 MHz Peak-to-Peak Period Jitter (IMO)

Maximum frequency of signal on row input or row output.

Supply Ramp Time

0

15

–

–

0

–

–

10

40

–

46.8

24

32

100

1400

–

50

50

48.0

600

–

–

24.6

b,d

64

200

–

–

60

–

49.2

a,c

12.3

–

MHz kHz ns

µs

% kHz

MHz ps

MHz

µs

Trimmed. Utilizing factory trim values.

a. 4.75V < Vdd < 5.25V.

b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

d. See the individual user module data sheets for information on maximum frequencies for user modules.

Table 3-16. 2.7V AC Chip-Level Specifications

Symbol

F

IMO12

F

IMO6

F

CPU1

F

BLK27

Description



CPU Frequency (2.7V Nominal)

Digital PSoC Block Frequency (2.7V Nominal)

Min

11.5

5.75

0.093

0

12 0

Typ

6

3

12

Max Units

12.7

a,b,c MHz

6.35

a,b,c

3.15

a,b

12.5

a,b,c

MHz

MHz

MHz

Notes

Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 17 .

SLIMO mode = 1.

Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 17 .

SLIMO mode = 1.

24 MHz only for SLIMO mode = 0.

Refer to the AC Digital Block Specifications below.

F

32K1

Jitter32k

Jitter32k

T

XRST

F

MAX

T

RAMP

Internal Low Speed Oscillator Frequency

32 kHz RMS Period Jitter

32 kHz Peak-to-Peak Period Jitter

External Reset Pulse Width

Maximum frequency of signal on row input or row output.

Supply Ramp Time

8

–

0

–

–

10

32

–

–

150

1400

–

96

200

–

–

12.3

– kHz ns

µs

MHz

µs a. 2.4V < Vdd < 3.0V.

b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.



Figure 3-3. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F

24M

Figure 3-4. 32 kHz Period Jitter (ILO) Timing Diagram

Jitter32k

F

32K1

3. Electrical Specifications



3.4.2

AC General Purpose IO Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-17. 5V and 3.3V AC GPIO Specifications

Symbol

F

GPIO

TRiseF

TFallF

TRiseS

TFallS

Description

GPIO Operating Frequency

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

0

3

2

7

7

Min

–

–

–

27

22

Typ

–

–

12

18

18

Max Units

MHz ns ns ns ns

Notes

Normal Strong Mode

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

Table 3-18. 2.7V AC GPIO Specifications

Symbol

F

GPIO

TRiseF

TFallF

TRiseS

TFallS

Description

GPIO Operating Frequency

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

Figure 3-5. GPIO Timing Diagram

90%

GPIO

Pin

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

0

6

6

18

18

Min

–

–

–

40

40

Typ

3

50

50

Max

120

120

Units

MHz ns ns ns ns

Notes

Normal Strong Mode

Vdd = 2.4 to 3.0V, 10% - 90%

Vdd = 2.4 to 3.0V, 10% - 90%

Vdd = 2.4 to 3.0V, 10% - 90%

Vdd = 2.4 to 3.0V, 10% - 90%



3.4.3

AC Operational Amplifier Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-19. AC Operational Amplifier Specifications

Symbol

T

COMP

Description

Comparator Mode Response Time, 50 mV Overdrive

Min Typ Max

100

200 ns ns

Units

Vdd

≥ 3.0V.

2.4V < Vcc <

3.0V.

Notes

3.4.4

AC Low Power Comparator Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A

≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-20. AC Low Power Comparator Specifications

Symbol

T

RLPC

LPC response time

Description

–

Min

–

Typ

50

Max

µs

Units Notes

≥ 50 mV overdrive comparator reference set within V

REFLPC

.

3.4.5

AC Analog Mux Bus Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-21. AC Analog Mux Bus Specifications

Symbol

F

SW

Switch Rate

Description

–

Min

–

Typ Max

3.17

Units

MHz

Notes

3.4.6

AC Digital Block Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-22. 5V and 3.3V AC Digital Block Specifications

Function

All

Functions

Timer

Counter

Description

Maximum Block Clocking Frequency (> 4.75V)

Maximum Block Clocking Frequency (< 4.75V)

Capture Pulse Width

Maximum Frequency, No Capture

Maximum Frequency, With or Without Capture

Enable Pulse Width

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

CRCPRS

(PRS Mode)

Synchronous Restart Mode

Disable Mode

Maximum Frequency

Maximum Input Clock Frequency

20

50

50

–

–

50

–

–

50 a

–

–

Min

–

–

–

–

–

–

–

–

–

–

–

Typ

–

–

–

49.2

49.2

Max

49.2

24.6

–

49.2

24.6

–

49.2

24.6

ns ns ns

MHz

MHz

Units

MHz

MHz ns

MHz

MHz ns

MHz

MHz

4.75V < Vdd < 5.25V.

Notes

3.0V < Vdd < 4.75V.

4.75V < Vdd < 5.25V.

4.75V < Vdd < 5.25V.

4.75V < Vdd < 5.25V.

4.75V < Vdd < 5.25V.



Table 3-22. 5V and 3.3V AC Digital Block Specifications (continued)

CRCPRS

(CRC Mode)

SPIM



–

–

–

–

24.6

8.2

MHz

MHz

SPIS Maximum Input Clock Frequency

Width of SS_ Negated Between Transmissions

Transmitter Maximum Input Clock Frequency

Maximum Input Clock Frequency with Vdd

≥ 4.75V, 2

Stop Bits

Receiver Maximum Input Clock Frequency

Maximum Input Clock Frequency with Vdd

≥ 4.75V, 2

Stop Bits

–

–

–

50

–

–

–

–

–

–

–

–

4.1

–

24.6

49.2

24.6

49.2

MHz ns

MHz

MHz

MHz

MHz a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Maximum data rate at 4.1 MHz due to 2 x over clocking.

Maximum data rate

at 3.08 MHz due to 8 x over clocking.

Maximum data rate


Maximum data rate


Maximum data rate


Table 3-23. 2.7V AC Digital Block Specifications

Function

All

Functions

Timer

Description

Maximum Block Clocking Frequency

Capture Pulse Width

Counter

Maximum Frequency, With or Without Capture

Enable Pulse Width

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

Synchronous Restart Mode

Disable Mode

Maximum Frequency

Maximum Input Clock Frequency CRCPRS

(PRS Mode)

CRCPRS

(CRC Mode)

SPIM



SPIS Maximum Input Clock Frequency

Width of SS_ Negated Between Transmissions

Transmitter Maximum Input Clock Frequency

Receiver Maximum Input Clock Frequency

–

–

20

100

100

–

–

–

100

–

–

Min

–

–

100 a

–

100

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Typ

–

–

–

12.7

12.7

12.7

6.35

4.1

–

12.7

12.7

Max

12.7

–

12.7

–

12.7

12.7

Units

MHz 2.4V < Vdd < 3.0V.

Notes ns

MHz ns

MHz

MHz ns ns ns

MHz

MHz

MHz

MHz

MHz ns

MHz

MHz a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).






3.4.7

AC External Clock Specifications


and -40°C

≤ T

A

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T

A


Table 3-24. 5V AC External Clock Specifications

–

–

Symbol

F

OSCEXT

–

Description

Frequency

High Period

Low Period

Power Up IMO to Switch

Min

0.093

20.6

20.6

150

–

–

–

–

Typ Max

24.6

5300

–

–

Units

MHz ns ns

µs

Notes

F

OSCEXT

Frequency with CPU Clock divide by 2 or greater

–

–

–

Table 3-25. 3.3V AC External Clock Specifications

Symbol

F

OSCEXT

Description

Frequency with CPU Clock divide by 1

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1


Min

0.093

–

Typ

0.186

41.7

41.7

150

–

–

–

–

Max

12.3

24.6

5300

–

– ns ns

µs

Units

MHz

MHz

Notes

Maximum CPU frequency is 12 MHz at 3.3V.

With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.

F

OSCEXT

–

–

–

Table 3-26. 2.7V AC External Clock Specifications

Symbol

F

OSCEXT

Description

Frequency with CPU Clock divide by 1

Frequency with CPU Clock divide by 2 or greater

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1


Min

0.093

–

Typ

0.186

160

160

150

–

–

–

–

Max

3.08

0

6.35

5300

–

– ns ns

µs

Units

MHz

MHz

Notes

Maximum CPU frequency is 3 MHz at 2.7V.

With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.



3.4.8

AC Programming Specifications


and -40°C

≤ T

A

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T

A


Table 3-27. AC Programming Specifications

Symbol

T

RSCLK

T

FSCLK

T

SSCLK

T

HSCLK

Rise Time of SCLK

Fall Time of SCLK

Description

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

F

SCLK

T

ERASEB

Frequency of SCLK

Flash Erase Time (Block)

T

WRITE

T

DSCLK

Flash Block Write Time

Data Out Delay from Falling Edge of SCLK

T

DSCLK3


T

DSCLK2


–

–

–

–

0

–

1

1

40

40

Min

–

–

30

–

–

–

–

–

–

15

Typ

–

45

50

70

–

8

–

20

Max

20

– ms ns ns ns ns

Units ns ns ns

MHz ms

3.6

< Vdd

3.0

≤ Vdd ≤ 3.6

2.4

≤ Vdd ≤ 3.0

Notes



3.4.9

AC I 2 C Specifications


and -40°C

≤ T

A

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A


Table 3-28. AC Characteristics of the I 2 C SDA and SCL Pins for Vdd

≥

3.0V

Symbol

F

SCLI2C

T

HDSTAI2C

T

LOWI2C

T

HIGHI2C

T

SUSTAI2C

T

HDDATI2C

T

SUDATI2C

T

SUSTOI2C

T

BUFI2C

T

SPI2C

Description

SCL Clock Frequency

Hold Time (repeated) START Condition. After this period, the first clock pulse is generated.

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

Set-up Time for a Repeated START Condition

Data Hold Time

Data Set-up Time

4.7

4.0

4.7

0

250

Set-up Time for STOP Condition 4.0

Bus Free Time Between a STOP and START Condition 4.7

Pulse Width of spikes are suppressed by the input filter.

–

0

Standard Mode

Min Max

100

4.0

–

–

–

–

–

–

–

–

–

0

0.6

Fast Mode

Min Max

400

–

1.3

0.6

0.6

0

100 a

0.6

1.3

0

–

–

–

–

50

–

–

– ns

µs

µs

µs

µs

µs

µs ns

Units kHz

µs

Notes a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

SU;DAT

≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t rmax

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

Table 3-29. 2.7V AC Characteristics of the I 2 C SDA and SCL Pins (Fast Mode not Supported)

F

Symbol

SCLI2C

Description

SCL Clock Frequency

T

HDSTAI2C

Hold Time (repeated) START Condition. After this period, the first clock pulse is generated.

T

LOWI2C

T

HIGHI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

T

SUSTAI2C

Set-up Time for a Repeated START Condition

0

4.0

4.7

4.0

4.7

T

HDDATI2C

Data Hold Time

T

SUDATI2C

Data Set-up Time

Set-up Time for STOP Condition T

SUSTOI2C

T

BUFI2C

T

SPI2C

Pulse Width of spikes are suppressed by the input filter.

0

250

4.0

Bus Free Time Between a STOP and START Condition 4.7

–

Standard Mode

Min Max

100

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Fast Mode

Min Max

–

–

–

–

–

–

–

–

–

– ns

µs

µs

µs

µs

µs

µs ns

Units kHz

µs

Figure 3-6. Definition for Timing for Fast/Standard Mode on the I 2 C Bus

Notes

SDA

T

LOWI2C T

SUDATI2C

SCL

S T

HDSTAI2C

T

HDDATI2C

T

HIGHI2C

T

SUSTAI2C Sr

T

HDSTAI2C

T

SPI2C

T

SUSTOI2C

P

T

BUFI2C

S


4.

Packaging Information

This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161 .

4.1

Packaging Dimensions

Figure 4-1. 16-Lead (150-Mil) SOIC

51-85068 *B


CY8C21x34 Final Data Sheet 4. Packaging Information

Figure 4-2. 20-Lead (210-MIL) SSOP

51-85077 *C

January 12, 2007

Figure 4-3. 28-Lead (210-Mil) SSOP

51-85079 *C

Document No. 38-12025 Rev. *K 33


E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)

Figure 4-4. 32-Lead (5x5 mm 0.93 MAX) QFN

51-85188 *A

January 12, 2007

E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)

Figure 4-5. 32-Lead (5x5 mm 0.60 MAX) QFN

Document No. 38-12025 Rev. *K

001-06392 *A

34


Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf

.

Figure 4-6. 56-Lead (300-Mil) SSOP

51-85062 *C



4.2

Thermal Impedances

Table 4-1. Thermal Impedances per Package

Package

16 SOIC

20 SSOP

28 SSOP

32 QFN** 5x5 mm 0.60 MAX

Typical

θ

JA

*

123 o

C/W

117 o

C/W

96 o

C/W

27 o

C/W

22 o

C/W

Typical

θ

JC

55 o

C/W

41 o

C/W

39 o

C/W

15 o

C/W

12 o

C/W

32 QFN** 5x5 mm 0.93 MAX

* T

J

= T

A

+ Power x

θ

JA

** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the

PCB ground plane.

4.3

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-2. Solder Reflow Peak Temperature

Package

16 SOIC

Minimum Peak Temperature*

240 o

C

Maximum Peak Temperature

260 o

C

20 SSOP

28 SSOP

240 o

C

240 o

C

260 o

C

260 o

C

32 QFN

240 o

C 260 o

C

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 o

C with Sn-Pb or 245 ± 5 o

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

4. Packaging Information


5.

Development Tool Selection

This chapter presents the development tools available for all current PSoC device families including the CY8C21x34 family.

5.1

Software

5.1.1

PSoC Designer ™

At the core of the PSoC development software suite is PSoC

Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http:// www.cypress.com

under DESIGN RESOURCES >> Software and Drivers.

5.1.2

PSoC Express ™

As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress .

5.1.3

PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-

Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer.

5.1.4

CY3202-C iMAGEcraft C Compiler

CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the

Cypress Online Store. At http://www.cypress.com

, click the

Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items..

5.2

Development Kits

All development kits can be purchased from the Cypress Online

Store.

5.2.1

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

■

■

■

■

■

■

■

■

■

■

PSoC Designer Software CD

ICE-Cube In-Circuit Emulator

ICE Flex-Pod for CY8C29x66 Family

Cat-5 Adapter

Mini-Eval Programming Board

110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required)

ISSP Cable

USB 2.0 Cable and Blue Cat-5 Cable

2 CY8C29466-24PXI 28-PDIP Chip Samples


CY8C21x34 Final Data Sheet 5. Development Tool Selection

5.2.2

CY3210-ExpressDK PSoC Express

Development Kit

The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I

2

C buses, voltage reference, switches, upgradeable modules and more. The kit includes:

■

■

■

■

■

■

■

■

■

■

■

■

■

PSoC Express Software CD

Express Development Board

4 Fan Modules

2 Proto Modules

MiniProg In-System Serial Programmer

MiniEval PCB Evaluation Board

Jumper Wire Kit

USB 2.0 Cable

Serial Cable (DB9)

110 ~ 240V Power Supply, Euro-Plug Adapter

2 CY8C24423A-24PXI 28-PDIP Chip Samples



5.3

Evaluation Tools

All evaluation tools can be purchased from the Cypress Online

Store.

5.3.1

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■

■

■

■

■

■

■

MiniProg Programming Unit

MiniEval Socket Programming and Evaluation Board

28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

28-Pin CY8C27443-24PXI PDIP PSoC Device Sample


Getting Started Guide

USB 2.0 Cable

5.3.2

CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■

■

■

■

■

■

Evaluation Board with LCD Module


28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)



USB 2.0 Cable

5.3.3

CY3214-PSoCEvalUSB

■

■

■

■

■

■

■

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

PSoCEvalUSB Board

LCD Module

MIniProg Programming Unit

Mini USB Cable

PSoC Designer and Example Projects CD


Wire Pack

5.4

Device Programmers

All device programmers can be purchased from the Cypress

Online Store.

5.4.1

CY3216 Modular Programmer

■

■

■

■

■

■

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

Modular Programmer Base

3 Programming Module Cards




USB 2.0 Cable

5.4.2

CY3207ISSP In-System Serial

Programmer (ISSP)

■

■

■

■

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment.

Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

CY3207 Programmer Unit

PSoC ISSP Software CD

110 ~ 240V Power Supply, Euro-Plug Adapter

USB 2.0 Cable



5.5

Accessories (Emulation and

Programming)

Table 5-1. Emulation and Programming Accessories

Part #

CY8C21234

-24S

CY8C21334

-24PVXI

CY8C21434

-24LFXI

CY8C21534

-24PVXI

CY8C21634

-24LFXI

Pin

Package

16 SOIC

20 SSOP

32 QFN

28 SSOP

32 QFN

Flex-Pod Kit a

Foot Kit b

Adapter c

CY3250-21X34 CY3250-

16SOIC-FK

CY3250-21X34 CY3250-

20SSOP-FK

CY3250-

21X34QFN

CY3250-

32QFN-FK

CY3250-21X34 CY3250-

28SSOP-FK

CY3250-

21X34QFN

CY3250-

32QFN-FK

See note c. below

See note c. below

See note c. below

See note c. below

See note c. below a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

b. Foot kit includes surface mount feet that can be soldered to the target PCB.

c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com

.

5.6

3rd-Party Tools

Several tools have been specially designed by the following

3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com

under DESIGN

RESOURCES >> Evaluation Boards.

5.7

Build a PSoC Emulator into

Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production

PSoC device, see Application Note “Debugging - Build a PSoC

Emulator into Your Board - AN2323” at http://www.cypress.com/ an2323 .

5. Development Tool Selection


6.

Ordering Information

.

CY8C21x34 PSoC Device Key Features and Ordering Information

16 Pin (150-Mil) SOIC

16 Pin (150-Mil) SOIC

(Tape and Reel)

20 Pin (210-Mil) SSOP


(Tape and Reel)



(Tape and Reel)

32 Pin (5x5 mm 0.93 MAX) QFN b

32 Pin (5x5 mm 0.93 MAX) QFN b

(Tape and Reel)

32 Pin (5x5 mm 0.60 MAX) QFN b

32 Pin (5x5 mm 0.06 MAX) QFN b

(Tape and Reel)

32 Pin (5x5 mm 0.93 MAX) QFN b

32 Pin (5x5 mm 0.93 MAX) QFN b

(Tape and Reel)

56 Pin OCD SSOP

CY8C21234-24SXI

CY8C21234-24SXIT

CY8C21334-24PVXI

CY8C21334-24PVXIT

CY8C21534-24PVXI

CY8C21534-24PVXIT

CY8C21434-24LFXI

CY8C21434-24LFXIT

CY8C21434-24LKXI

CY8C21434-24LKXIT

CY8C21634-24LFXI

CY8C21634-24LFXIT

CY8C21001-24PVXI a. All Digital IO Pins also connect to the common analog mux.

b. Refer to the “32-Pin Part Pinout” on page 11 for pin differences.

8K

8K

8K

8K

8K

8K

8K

8K

8K

8K

8K

8K

8K

512

512

512

512

512

512

512

512

512

512

Yes -40 ° C to +85 ° C

Yes -40 ° C to +85 ° C

No -40 ° C to +85 ° C

No -40 ° C to +85 ° C

No -40 ° C to +85 ° C

No -40 ° C to +85 ° C

No -40 ° C to +85 ° C

No

No

No

-40

-40

-40

°

°

°

C to +85

C to +85

C to +85

°

°

°

C

C

C

512 Yes -40 ° C to +85 ° C

512 Yes -40 ° C to +85 ° C

512 Yes -40 ° C to +85 ° C

4

4

4

4

4

4

4

4

4

4

4

4

4

6.1

Ordering Code Definitions

CY 8 C 21 xxx-24xx

Package Type:

PX = PDIP Pb-Free

SX = SOIC Pb-Free

PVX = SSOP Pb-Free

LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free

Thermal Rating:

C = Commercial

I = Industrial

E = Extended

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

4

4

4

4

4

4

4

4

4

4

4

4

4

28

28

28

12

12

16

16

24

24

28

26

26

26

28 a

28 a

26 a

24 a

24 a

28 a

12 a

12 a

16 a

16 a

28 a

26 a

26 a

Yes

Yes

Yes

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

0

0

0

0

0

0

0

0

0

0

0

0

0


7.

Sales and Service Information

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134

408.943.2600

Web Sites: Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

7.1

Revision History

Document Title: CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 PSoC Mixed-Signal Array Final Data Sheet

Document Number: 38-12025

Revision ECN # Issue Date

Origin of

Change

Description of Change

** 227340 5/19/2004 HMT New silicon and document (Revision **).

*A

*B

*C

*D

*E

*F

*G

*H

*I

*J

*K

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248572

277832

285293

301739

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677717

See ECN

See ECN

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See ECN

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Distribution: External/Public

SFV

SFV

HMT

HMT

HMT

HMT

HMT

HMT

HMT

HMT

HMT

Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part.

Revised the register mapping tables. Added a SSOP 28-pin part.

Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534.

Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634.

Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs.

Update PSoC Characteristics table. Update diagrams and specs. Final.

Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.

DC Chip-Level Specification changes. Update links to new CY.com Portal.

Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature. Update Electrical

Specifications. Update Reflow Peak Temp. table. Add 32 MLF E-PAD dimensions. Add ThetaJC to

Thermal Impedance table. Fix 20-pin package order number. Add CY logo. Update CY copyright.

Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update

Transmitter and Receiver AC Digital Block Electrical Specifications.

Clarify MLF thermal pad connection info. Replace 16-pin 300-MIL SOIC with correct 150-MIL.

Update 32-pin QFN E-Pad dimensions and rev. *A. Update CY branding and QFN convention.

Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram, CY8C21434-24LKXI. Update thermal resistance data. Add 56-pin SSOP on-chip debug non-production part, CY8C21001-

24PVXI. Update typical and recommended Storage Temperature per industrial specs. Update copyright and trademarks.

Add CapSense SNR requirement reference. Add new Dev. Tool section. Add CY8C20x34 to

PSoC Device Characteristics table. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Update rev. of 32-Lead (5x5 mm 0.60 MAX) QFN package diagram.

Posting: None

January 12, 2007 © Cypress Semiconductor Corp. 2004-2007 — Document No. 38-12025 Rev. *K 41

CY8C21x34 Final Data Sheet 7. Sales and Service Information

7.2

Copyrights and Code Protection

Copyrights

© Cypress Semiconductor Corp. 2004-2007. All rights reserved. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies

Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor.

Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.

Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress

Semiconductor are committed to continuously improving the code protection features of our products.


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