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S3F80JB
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.
This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.
"Typical" parameters can and do vary in different applications. All operating parameters, including
"Typicals" must be validated for each customer application by the customer's technical experts.
Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the
Samsung product could create a situation where personal injury or death may occur.
Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or manufacture of said product.
S3F80JB 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.1
Publication Number: 21.1-S3F-80JB-032006
© 2006 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and
objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu,
Yongin-City, Gyunggi-Do, Korea
C.P.O. Box #37, Korea 446-711
TEL: (82)-(31)-209-5238
FAX: (82)-(31)-209-6494
Home-Page URL: Http://www.samsungsemi.com
Printed in the Republic of Korea
Preface
The S3F80JB Microcontroller User's Manual is designed for application designers and programmers who are using S3F80JB microcontroller for application development. It is organized in two main parts:
Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters:
Chapter 1
Chapter 2
Chapter 3
Product Overview
Address Spaces
Addressing Modes
Chapter 4
Chapter 5
Chapter 6
Control Registers
Interrupt Structure
Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to S3F80JB with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3C8-series CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, "Interrupt Structure," describes the S3F80JB interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3F8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3F8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.
Part II "hardware Descriptions," has detailed information about specific hardware components of the S3F80JB microcontroller. Also included in Part II are electrical, mechanical, MTP, and development tools data. It has 14 chapters:
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Clock Circuits
RESET
I/O Ports
Basic Timer and Timer 0
Timer 1
Counter A
Timer 2
Comparator
Chapter 15
Chapter 16
Chapter 17
Chapter 18
Embedded Flash Memory Interface
Low Voltage Detector
Electrical Data-4MHz
Electrical Data-8MHz
Chapter 19 Mechanical Data
Chapter 20 Development Tools Data
Two order forms are included at the back of this manual to facilitate customer order for S3F80JB microcontrollers: the Flash Factor Writing Order Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
S3F80JB MICROCONTROLLER iii
Table of Contents
Part I — Programming Model
Chapter 1 Product Overview
S3C8/S3F8-Series Microcontrollers ........................................................................................................... 1-1
S3F80JB Microcontroller ............................................................................................................................ 1-1
Features ..................................................................................................................................................... 1-2
Block Diagram (32-pin package) ................................................................................................................ 1-3
Block Diagram (44-pin package) ................................................................................................................ 1-4
Pin Assignments......................................................................................................................................... 1-5
Pin Circuits ................................................................................................................................................. 1-10
Chapter 2 Address Spaces
Overview .................................................................................................................................................... 2-1
Program Memory........................................................................................................................................ 2-2
Register Architecture .................................................................................................................................. 2-5
Register Page Pointer (PP)................................................................................................................ 2-7
Register Set1 ..................................................................................................................................... 2-8
Register Set 2 .................................................................................................................................... 2-8
Prime Register Space ........................................................................................................................ 2-9
Working Registers.............................................................................................................................. 2-10
Using the Register Pointers ............................................................................................................... 2-11
Register Addressing ................................................................................................................................... 2-13
Common Working Register Area (C0H–CFH).................................................................................... 2-15
4-Bit Working Register Addressing .................................................................................................... 2-16
8-Bit Working Register Addressing .................................................................................................... 2-18
System and User Stacks ............................................................................................................................ 2-20
Chapter 3 Addressing Modes
Overview .................................................................................................................................................... 3-1
Register Addressing Mode (R)........................................................................................................... 3-2
Indirect Register Addressing Mode (IR) ............................................................................................. 3-3
Indexed Addressing Mode (X)............................................................................................................ 3-7
Direct Address Mode (DA) ................................................................................................................. 3-10
Indirect Address Mode (IA) ................................................................................................................ 3-12
Relative Address Mode (RA).............................................................................................................. 3-13
Immediate Mode (IM)......................................................................................................................... 3-14
Chapter 4 Control Registers
Overview .................................................................................................................................................... 4-1
S3F80JB MICROCONTROLLER v
Table of Contents
(Continued)
Chapter 5 Interrupt Structure
Overview ....................................................................................................................................................5-1
Interrupt Types ...................................................................................................................................5-2
Interrupt Vector Addresses.................................................................................................................5-5
Enable/Disable Interrupt Instructions (EI, DI) .....................................................................................5-7
System-Level Interrupt Control Registers...........................................................................................5-7
Interrupt Processing Control Points....................................................................................................5-8
Peripheral Interrupt Control Registers ................................................................................................5-9
System Mode Register (SYM)............................................................................................................5-10
Interrupt Mask Register (IMR) ............................................................................................................5-11
Interrupt Priority Register (IPR) ..........................................................................................................5-12
Interrupt Request Register (IRQ) .......................................................................................................5-14
Interrupt Pending Function Types ......................................................................................................5-15
Interrupt Source Polling Sequence.....................................................................................................5-16
Interrupt Service Routines..................................................................................................................5-16
Generating interrupt Vector Addresses ..............................................................................................5-17
Nesting of Vectored Interrupts............................................................................................................5-17
Instruction Pointer (IP) .......................................................................................................................5-17
Fast Interrupt Processing ...................................................................................................................5-17
Chapter 6 Instruction Set
Overview ....................................................................................................................................................6-1
Flags Register (FLAGS) .....................................................................................................................6-6
Flag Descriptions ...............................................................................................................................6-7
Instruction Set Notation ......................................................................................................................6-8
Condition Codes.................................................................................................................................6-12
Instruction Descriptions ......................................................................................................................6-13
Chapter 7 Clock Circuit
Overview ....................................................................................................................................................7-1
System Clock Circuit ..........................................................................................................................7-1
Clock Status During Power-Down Modes ..........................................................................................7-2
System Clock Control Register (CLKCON) ........................................................................................7-3
Table of Contents
(Continued)
Chapter 8 RESET
Overview .................................................................................................................................................... 8-1
Reset Sources ................................................................................................................................... 8-1
Reset Mechanism .............................................................................................................................. 8-4
External Reset Pin ............................................................................................................................. 8-4
Watch Dog Timer Reset..................................................................................................................... 8-4
LVD Reset ......................................................................................................................................... 8-4
Internal Power-On Reset ................................................................................................................... 8-5
External Interrupt Reset ..................................................................................................................... 8-7
Stop Error Detection & Recovery ....................................................................................................... 8-8
Power-Down Modes ................................................................................................................................... 8-9
Idle Mode ........................................................................................................................................... 8-9
Back-up mode.................................................................................................................................... 8-10
Stop Mode ......................................................................................................................................... 8-11
Sources to Release Stop Mode ......................................................................................................... 8-12
System Reset Operation .................................................................................................................... 8-14
Hardware Reset Values ..................................................................................................................... 8-15
Recommendation for Unusued Pins .................................................................................................. 8-19
Summary Table of Back-Up Mode, Stop Mode, and Reset Status..................................................... 8-20
Overview .................................................................................................................................................... 9-1
Port Data Registers............................................................................................................................ 9-4
Pull-Up Resistor Enable Registers ..................................................................................................... 9-5
S3F80JB MICROCONTROLLER vii
Table of Contents
(Continued)
Chapter 10 Basic Timer and Timer 0
Overview ....................................................................................................................................................10-1
Basic Timer (BT) ................................................................................................................................10-1
Timer 0...............................................................................................................................................10-1
Basic Timer Control Register (BTCON)..............................................................................................10-2
Basic Timer Function Description.......................................................................................................10-3
Timer 0 Control Register (T0CON).....................................................................................................10-4
Timer 0 Function Description .............................................................................................................10-6
Chapter 11 Timer 1
Overview ....................................................................................................................................................11-1
Timer 1 Overflow interrupt..................................................................................................................11-2
Timer 1 Capture interrupt ...................................................................................................................11-2
Timer 1 Match interrupt ......................................................................................................................11-3
Timer 1 Control Register (T1CON).....................................................................................................11-5
Chapter 12 Counter A
Overview ....................................................................................................................................................12-1
Counter A Control Register (CACON) ................................................................................................12-3
Counter A Pulse Width Calculations...................................................................................................12-4
Chapter 13 Timer 2
Overview ....................................................................................................................................................13-1
Timer 2 Overflow Interrupt..................................................................................................................13-2
Timer 2 Capture Interrupt ...................................................................................................................13-2
Timer 2 Match Interrupt ......................................................................................................................13-3
Timer 2 Control Register (T2CON).....................................................................................................13-5
Chapter 14 Comparator
Overview ....................................................................................................................................................14-1
Comparator Operation .......................................................................................................................14-3
Table of Contents
(Continued)
Chapter 15 Embedded Flash Memory Interface
Overview .................................................................................................................................................... 15-1
ISP TM (On-Board Programming) Sector ..................................................................................................... 15-3
ISP Reset Vector and ISP Sector Size............................................................................................... 15-5
Flash Memory Control Registers (User Program Mode) .............................................................................15-6
Flash Memory Control Register (FMCON) ......................................................................................... 15-6
Flash Memory User Programming Enable Register (FMUSR) ........................................................... 15-6
Flash Memory Sector Address Registers........................................................................................... 15-7
Sector Erase .............................................................................................................................................. 15-8
Programming.............................................................................................................................................. 15-12
Reading...................................................................................................................................................... 15-17
Hard Lock Protection .................................................................................................................................. 15-18
Chapter 16 Low Voltage Detector
Overview .................................................................................................................................................... 16-1
LVD.................................................................................................................................................... 16-1
LVD Flag............................................................................................................................................ 16-1
Low Voltage Detector Control Register (LVDCON) ............................................................................ 16-3
Chapter 17 Electrical Data – 4MHz
Overview .................................................................................................................................................... 17-1
Chapter 18 Electrical Data – 8MHz
Overview .................................................................................................................................................... 18-1
Chapter 19 Mechanical Data
Overview······················································································································································ 19-1
Chapter 20 Development Tools Data
Overview······················································································································································ 20-1
Target Boards................................................................................................................................... 20-1
Programming Socket Adapter........................................................................................................... 20-1
TB80JB Target Board....................................................................................................................... 20-2
OTP/MTP Programmer (Writer)........................................................................................................ 20-7
S3F80JB MICROCONTROLLER ix
List of Figures
Number Number
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
Block Diagram (32-pin) .............................................................................................1-3
Block Diagram (44-pin) .............................................................................................1-4
Pin Assignment Diagram (32-Pin SOP Package) .....................................................1-5
Pin Assignment Diagram (44-Pin QFP Package)......................................................1-6
Pin Circuit Type 1 (Port 0 and Port2) ........................................................................1-10
Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)......................................................1-11
Pin Circuit Type 3 (P3.0)...........................................................................................1-12
Pin Circuit Type 4 (P3.1)...........................................................................................1-13
Pin Circuit Type 5 (P3.2 and P3.3) ...........................................................................1-13
1-10 Pin Circuit Type 6 (nRESET) ....................................................................................1-14
2-1
2-2
2-3
2-4
2-5
2-6
2-7
Program Memory Address Space.............................................................................2-2
Smart Option ............................................................................................................2-3
Internal Register File Organization ...........................................................................2-6
Register Page Pointer (PP) ......................................................................................2-7
Set 1, Set 2, and Prime Area Register Map ..............................................................2-9
8-Byte Working Register Areas (Slices)....................................................................2-10
Contiguous 16-Byte Working Register Block ............................................................2-11
2-8
2-9
2-10
2-11
Non-Contiguous 16-Byte Working Register Block.....................................................2-12
16-Bit Register Pair ..................................................................................................2-13
Register File Addressing...........................................................................................2-14
Common Working Register Area ..............................................................................2-15
4-Bit Working Register Addressing ...........................................................................2-17 2-12
2-13
2-14
4-Bit Working Register Addressing Example ............................................................2-17
8-Bit Working Register Addressing ...........................................................................2-18
2-15 8-Bit Working Register Addressing Example ............................................................2-19
Operations ......................................................................................................2-20
Register Addressing .................................................................................................3-2
Working Register Addressing ...................................................................................3-2
Indirect Register Addressing to Register File............................................................3-3
Indirect Register Addressing to Program Memory ....................................................3-4
Indirect Working Register Addressing to Register File..............................................3-5
Indirect Working Register Addressing to Program or Data Memory..........................3-6
Indexed Addressing to Register File .........................................................................3-7
Indexed Addressing to Program or Data Memory with Short Offset..........................3-8
Indexed Addressing to Program or Data Memory .....................................................3-9
Register Description Format .....................................................................................4-4
Direct Addressing for Load Instructions ....................................................................3-10
Direct Addressing for Call and Jump Instructions .....................................................3-11
Indirect Addressing...................................................................................................3-12
Relative Addressing..................................................................................................3-13
Immediate Addressing ..............................................................................................3-14
Number
8-8
9-1
9-2
10-1
10-2
10-3
10-4
10-5
10-6
10-7
11-1
11-2
11-3
11-4
11-5
5-8
5-9
6-1
7-1
7-2
7-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
7-4
8-1
8-2
8-3
8-4
8-5
8-6
8-7
List of Figures
(Continued)
Number
S3C8/S3F8-Series Interrupt Types........................................................................... 5-2
S3F80JB Interrupt Structure..................................................................................... 5-4
ROM Vector Address Area ....................................................................................... 5-5
Interrupt Function Diagram....................................................................................... 5-8
System Mode Register (SYM) .................................................................................. 5-10
Interrupt Mask Register (IMR) .................................................................................. 5-11
Interrupt Request Priority Groups ............................................................................. 5-12
Interrupt Priority Register (IPR) ................................................................................ 5-13
Interrupt Request Register (IRQ).............................................................................. 5-14
System Flags Register (FLAGS) .............................................................................. 6-6
Main Oscillator Circuit (External Crystal or Ceramic Resonator) ............................ 7-1
External Clock Circuit ............................................................................................... 7-1
System Clock Circuit Diagram.................................................................................. 7-2
System Clock Control Register (CLKCON)............................................................... 7-3
RESET Sources of The S3F80JB............................................................................. 8-2
RESET Block Diagram of The S3F80JB .................................................................. 8-3
RESET Block Diagram by LVD for The S3F80JB IN STOP MODE .......................... 8-4
Internal Power-On Reset Circuit ............................................................................... 8-5
Timing Diagram for Internal Power-On Reset Circuit................................................ 8-6
Reset Timing Diagram for The S3F80JB in STOP mode by IPOR ........................... 8-7
Block Diagram for Back-up Mode ............................................................................. 8-10
Timing Diagram for Back-up Mode Input and Released by LVD............................... 8-10
S3F80JB I/O Port Data Register Format .................................................................. 9-5
Pull-up Resistor Enable Registers (Port 0 and Port 2 only) ...................................... 9-6
Basic Timer Control Register (BTCON) .................................................................... 10-2
Timer 0 Control Register (T0CON) ........................................................................... 10-5
Timer 0 DATA Register (T0DATA) ........................................................................... 10-5
Simplified Timer 0 Function Diagram: Interval Timer Mode ...................................... 10-6
Simplified Timer 0 Function Diagram: PWM Mode ................................................... 10-7
Simplified Timer 0 Function Diagram: Capture Mode ............................................... 10-8
Basic Timer and Timer 0 Block Diagram .................................................................. 10-9
Simplified Timer 1 Function Diagram: Capture Mode ............................................... 11-2
Simplified Timer 1 Function Diagram: Interval Timer Mode ...................................... 11-3
Timer 1 Block Diagram ............................................................................................. 11-4
Timer 1 Control Register (T1CON) ........................................................................... 11-5
Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL)................................. 11-6
S3F80JB MICROCONTROLLER xi
Number
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
12-1
12-2
12-3
12-4
13-1
13-2
13-3
13-4
13-5
14-1
14-2
14-3
14-4
14-5
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
16-1
16-2
17-1
17-2
17-3
List of Figures
(Continued)
Number
Counter A Block Diagram .........................................................................................12-2
Counter A Control Register (CACON) ......................................................................12-3
Counter A Registers .................................................................................................12-3
Counter A Output Flip-Flop Waveforms in Repeat Mode ..........................................12-5
Simplified Timer 2 Function Diagram: Capture Mode ...............................................13-2
Simplified Timer 2 Function Diagram: Interval Timer Mode ......................................13-3
Timer 2 Block Diagram .............................................................................................13-4
Timer 2 Control Register (T2CON) ...........................................................................13-5
Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6
Comparator Block Diagram for The S3F80JB...........................................................14-2
Conversion Characteristics.......................................................................................14-3
Comparator Mode Register (CMOD) ........................................................................14-4
Comparator Input Selection Register (CMPSEL) ......................................................14-4
Comparator Result Register (CMPREG) ..................................................................14-5
Program Memory Address Space.............................................................................15-3
Smart Option ............................................................................................................15-4
Flash Memory Control Register (FMCON)................................................................15-6
Flash Memory User Programming Enable Register (FMUSR) ..................................15-6
Flash Memory Sector Address Register (FMSECH) .................................................15-7
Flash Memory Sector Address Register (FMSECL)..................................................15-7
Sector Configurations in User Program Mode ..........................................................15-8
Sector Erase Flowchart in User Program Mode........................................................15-9
Byte Program Flowchart in a User Program Mode....................................................15-13
Program Flowchart in a User Program Mode............................................................15-14
Low Voltage Detect (LVD) Block Diagram ································································16-2
Low Voltage Detect Control Register (LVDCON)······················································16-3
Typical Low-Side Driver (Sink) Characteristics (P3.1 only) ·······································17-5
Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) ·························17-5
Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································17-6
Typical High-Side Driver (Source) Characteristics (P3.1 only) ··································17-6
Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3) ····················17-7
Typical High-Side Driver (Source) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································17-7
Stop Mode Release Timing When Initiated by an External Interrupt ·························17-8
Stop Mode Release Timing When Initiated by a Reset·············································17-8
Stop Mode Release Timing When Initiated by a LVD ···············································17-9
Input Timing for External Interrupts (Port 0 and Port 2) ············································17-10
Input Timing for Reset (nRESET Pin) ·······································································17-10
Operating Voltage Range of S3F80J9 ······································································17-13
Number
18-9
18-10
18-11
18-12
19-1
19-2
20-1
20-2
20-3
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
List of Figures
(Continued)
Number
Typical Low-Side Driver (Sink) Characteristics (P3.1 only)······································· 18-5
Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) ························· 18-5
Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ·························································· 18-6
Typical High-Side Driver (Source) Characteristics (P3.1 only)·································· 18-6
Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)···················· 18-7
Typical High-Side Driver (Source) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ·························································· 18-7
Stop Mode Release Timing When Initiated by an External Interrupt························· 18-8
Stop Mode Release Timing When Initiated by a Reset············································· 18-8
Stop Mode Release Timing When Initiated by a LVD ··············································· 18-9
Input Timing for External Interrupts (Port 0 and Port 2) ············································ 18-10
Input Timing for Reset (nRESET Pin)······································································· 18-10
Operating Voltage Range of S3F80JB ····································································· 18-13
32-Pin SOP Package Dimension.............................................................................. 19-1
44-Pin QFP Package Dimension .............................................................................. 19-2
TB80JB Target Board Configuration········································································· 20-2
50-Pin Connector Pin Assignment for TB80JB ························································· 20-5
TB80JB Adapter Cable for 44-QFP Package ··························································· 20-5
S3F80JB MICROCONTROLLER xiii
Number
1-1
1-2
2-1
4-1
4-2
4-3
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-3
9-4
List of Tables
Number
Pin Descriptions of 32-SOP...................................................................................... 1-7
Pin Descriptions of 44-QFP ...................................................................................... 1-8
S3F80JB Register Type Summary ........................................................................... 2-5
Mapped Registers (Bank0, Set1) ............................................................................. 4-2
Mapped Registers (Bank1, Set1) ............................................................................. 4-3
Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package ... 4-32
S3F80JB Interrupt Vectors ....................................................................................... 5-6
Interrupt Control Register Overview ......................................................................... 5-7
Vectored Interrupt Source Control and Data Registers............................................. 5-9
Instruction Group Summary...................................................................................... 6-2
Flag Notation Conventions ....................................................................................... 6-8
Instruction Set Symbols............................................................................................ 6-8
Instruction Notation Conventions.............................................................................. 6-9
Opcode Quick Reference ......................................................................................... 6-10
Condition Codes....................................................................................................... 6-12
Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1”
(always LVD-On) ...................................................................................................... 8-8
Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0” ....................... 8-8
Set 1, Bank 0 Register Values After Reset ............................................................... 8-15
Set 1, Bank 1 Register Values After Reset ............................................................... 8-17
Reset Generation According to the Condition of Smart Option................................. 8-18
Guideline for Unused Pins to Reduced Power Consumption.................................... 8-19
Summary of Each Mode ........................................................................................... 8-20
S3F80JB Port Configuration Overview (44-QFP) ..................................................... 9-2
S3F80JB Port Configuration Overview (32-SOP) ..................................................... 9-3
Port Data Register Summary.................................................................................... 9-4
S3F80JB MICROCONTROLLER xv
List of Tables
(Continued)
Number Number
15-1
15-2
15-3
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
20-1
20-2
Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode ..............15-2
ISP Sector Size ........................................................................................................15-5
Reset Vector Address...............................................................................................15-5
Absolute Maximum Ratings ......................................................................................17-2
D.C. Electrical Characteristics ..................................................................................17-2
Characteristics of Low Voltage Detect Circuit ...........................................................17-4
Data Retention Supply Voltage in Stop Mode...........................................................17-4
Input/Output Capacitance .........................................................................................17-9
Absolute Maximum Ratings ······················································································18-2
D.C. Electrical Characteristics ··················································································18-2
Characteristics of Low Voltage Detect Circuit ···························································18-4
Data Retention Supply Voltage in Stop Mode···························································18-4
Input/Output Capacitance ·························································································18-9
A.C. Electrical Characteristics ··················································································18-9
Comparator Electrical Characteristics·······································································18-11
Oscillation Characteristics ························································································18-11
Oscillation Stabilization Time ····················································································18-12
AC Electrical Characteristics for Internal Flash ROM··············································18-13
Components Consisting of S3F80JB Target Board ··················································20-3
Default Setting of the Jumper in S3F80JB Target Board ··········································20-4
A.C. Electrical Characteristics ..................................................................................17-9
Comparator Electrical Characteristics.......................................................................17-11
Oscillation Characteristics ........................................................................................17-11
Oscillation Stabilization Time ....................................................................................17-12
AC Electrical Characteristics for Internal Flash ROM................................................17-13
List of Programming Tips
Description Page
Number
Chapter 2 Address Spaces
Setting the Register Pointers ...................................................................................................................... 2-11
Using the RPs to Calculate the Sum of a Series of Registers..................................................................... 2-12
Addressing the Common Working Register Area ....................................................................................... 2-16
Standard Stack Operations Using PUSH and POP .................................................................................... 2-21
Chapter 8 Reset
To Enter STOP Mode ................................................................................................................................. 8-10
Chapter 10 Basic Timer and Timer 0
Configuring the Basic Timer ....................................................................................................................... 10-11
Programming Timer 0................................................................................................................................. 10-12
Chapter 12 Counter A
To Generate 38 kHz, 1/3duty Signal Through P3.1 .................................................................................... 12-6
To Generate a one Pulse Signal Through P3.1 .......................................................................................... 12-7
Chapter 15 Embedded Flash Memory Interface
Sector Erase .............................................................................................................................................. 15-10
Programming.............................................................................................................................................. 15-15
Reading...................................................................................................................................................... 15-17
Hard Lock Protection .................................................................................................................................. 15-18
S3F80JB MICROCONTROLLER xvii
List of Register Descriptions
Register Full Page
Identifier Number
BTCON
CACON
CLKCON
Basic Timer Control Register.................................................................................... 4-5
Counter A Control Register ...................................................................................... 4-6
System Clock Control Register................................................................................. 4-7
CMPSEL
EMT
FMCON
FMSECH
FMSECL
FMUSR
IMR
IPH
IPL
IPR
LVDCON
P0CONL
P0INT
P0PND
P0PUR
P1CONH
P1CONL
P2CONH
P2CONL
P2INT
P2PND
P3CON
P345CON
P4CON
P4CONH
P4CONL
PP
RP0
RP1
SPL
Comparator Input Selection Register........................................................................ 4-9
External Memory Timing Register ............................................................................ 4-10
Flash Memory Control Register ................................................................................ 4-12
Flash Memory Sector Address Register (High Byte) ................................................ 4-13
Flash Memory Sector Address Register (Low Byte) ................................................. 4-13
Flash Memory User Programming Enable Register.................................................. 4-13
Interrupt Mask Register ............................................................................................ 4-14
Instruction Pointer (High Byte).................................................................................. 4-15
Instruction Pointer (Low Byte) .................................................................................. 4-15
Interrupt Priority Register.......................................................................................... 4-16
LVD Control Register ............................................................................................. 4-18
Port 0 Control Register (Low Byte) ........................................................................... 4-20
Port 0 External Interrupt Enable Register ................................................................. 4-21
Port 0 External Interrupt Pending Register ............................................................... 4-22
Port 0 Pull-up Resistor Enable Register ................................................................... 4-23
Port 1 Control Register (High Byte) .......................................................................... 4-24
Port 1 Control Register (Low Byte) ........................................................................... 4-25
Port 2 Control Register (High Byte) .......................................................................... 4-26
Port 2 Control Register (Low Byte) ........................................................................... 4-27
Port 2 External Interrupt Enable Register ................................................................. 4-28
Port 2 External Interrupt Pending Register ............................................................... 4-29
Port 3 Control Register ............................................................................................. 4-31
Port3[4:5] Control Register ....................................................................................... 4-33
Port 4 Control Register ............................................................................................. 4-34
Port 4 Control Register (High Byte) .......................................................................... 4-35
Port 4 Control Register (Low Byte) ........................................................................... 4-36
Register Page Pointer .............................................................................................. 4-37
Register Pointer 0..................................................................................................... 4-38
Register Pointer 1..................................................................................................... 4-38
Stack Pointer (Low Byte) .......................................................................................... 4-39
T1CON
T2CON
Timer 1 Control Register .......................................................................................... 4-42
Timer 2 Control Register .......................................................................................... 4-43
S3F80JB MICROCONTROLLER xix
List of Instruction Descriptions
Mnemonic
Page
Number
ADD Add........................................................................................................................... 6-15
BTJRF
BTJRT
Bit Test, Jump Relative on False .............................................................................. 6-23
Bit Test, Jump Relative on True ............................................................................... 6-24
CLR Clear ........................................................................................................................ 6-28
COM Complement ............................................................................................................. 6-29
CP Compare .................................................................................................................. 6-30
CPIJE Compare, Increment, and Jump on Equal ................................................................ 6-31
CPIJNE Compare, Increment, and Jump on Non-Equal ........................................................ 6-32
DEC Decrement................................................................................................................ 6-35
DJNZ Decrement and Jump if Non-Zero ............................................................................ 6-39
ENTER Enter ........................................................................................................................ 6-41
EXIT Exit ........................................................................................................................... 6-42
INC Increment ................................................................................................................. 6-44
JP Jump ........................................................................................................................6-47
LD Load ......................................................................................................................... 6-49
LD Load ......................................................................................................................... 6-50
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
Load Memory and Decrement .................................................................................. 6-54
Load Memory and Increment.................................................................................... 6-55
Load Memory with Pre-Decrement ........................................................................... 6-56
Load Memory with Pre-Increment............................................................................. 6-57
S3F80JB MICROCONTROLLER xxi
List of Instruction Descriptions
(Continued)
Instruction
Mnemonic
Full Register Name Page
Number
NEXT Next ..........................................................................................................................6-60
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
Pop From Stack........................................................................................................6-63
Pop User Stack (Decrementing) ...............................................................................6-64
Pop User Stack (Incrementing).................................................................................6-65
Push To Stack ..........................................................................................................6-66
Push User Stack (Decrementing) .............................................................................6-67
Push User Stack (Incrementing) ...............................................................................6-68
RET Return.......................................................................................................................6-70
RLC
RRC
Rotate Left Through Carry ........................................................................................6-72
Rotate Right Through Carry......................................................................................6-74
SUB Subtract ....................................................................................................................6-82
TCM
TM
WFI
Test Complement Under Mask .................................................................................6-84
Test Under Mask ......................................................................................................6-85
Wait For Interrupt......................................................................................................6-86
S3F80JB PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8/S3F8-SERIES MICROCONTROLLERS
Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include:
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupts
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum four CPU clocks) can be assigned to specific interrupt levels.
S3F80JB MICROCONTROLLER
The S3F80JB single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture.
The S3F80JB is the microcontroller which has 64-Kbyte Flash Memory ROM.
Using a proven modular design approach, Samsung engineers developed S3F80JB by integrating the following peripheral modules with the powerful SAM8 RC core:
— Internal LVD circuit and 16 bit-programmable pins for external interrupts.
— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
— One 8-bit Timer/counter with three operating modes.
— Two 16-bit timer/counters with selectable operating modes.
— 4-bit analog voltage comparator with four/three channels (internal/external reference).
— One 8-bit counter with auto-reload function and one-shot or repeat control.
The S3F80JB is a versatile general-purpose microcontroller, which is especially suitable for use as remote transmitter controller. It is currently available in a 32-pin SOP and 44-pin QFP package.
1-1
PRODUCT OVERVIEW S3F80JB
FEATURES
CPU
• SAM8 RC CPU core
Memory
• Program memory:
- 64-Kbyte Internal Flash Memory
- Sector size: 128Bytes
- 10years data retention
- Fast Programming Time : Sector Erase: 10ms
Byte Program: 32us
- Byte Programmable
- User programmable by ‘LDC’ instruction
- Sector (128-bytes) Erase available
- External serial programming support
- Endurance: 10,000 Erase/Program cycles
- Expandable OBPTM (On Board Program)
• Data memory : 272-byte general purpose RAM
Instruction Set
•
•
78 instructions
IDLE and STOP instructions added for powerdown modes
Instruction Execution Time
• 500 ns at 8-MHz f
OSC
(minimum)
Interrupts
• 24 interrupt sources with 18 vectors and 8 levels.
I/O Ports
• Four 8-bit I/O ports (P0–P2 , P4) and 6-bit port
(P3) for a total of 38 bit-programmable pins.
(44-QFP)
• Four 8-bit I/O ports (P0–P2 , P4) and 4-bit port
(P3) for a total of 36 bit-programmable pins.
(42-SDIP)
• Three 8-bit I/O ports (P0–P2) and one 2-bit I/O port (P3) for a total of 26-bit programmable pins.
(32-SOP)
Carrier Frequency Generator
• One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A)
Basic Timer and Timer/Counters
• One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer
(software reset) function
• One 8-bit timer/counter (Timer 0) with three operating modes: Interval mode, Capture and
PWM mode.
• One 16-bit timer/counter (Timer1) with two operating modes: Interval and Capture mode.
• One 16-bit timer/counter (Timer2) with two operating modes: Interval and Capture mode.
Back-up Mode
• When V
DD
is lower than V
LVD
, the chip enters
Back-up mode to block oscillation and reduce the current consumption.
In S3F80JB, this function is disabled when operating state is “STOP mode”.
• When reset pin is lower than Input Low Voltage
(V
IL
), the chip enters Back-up mode to block oscillation and reduce the current consumption.
Analog Voltage Comparator
• 4-bit resolution: 16-step variable reference voltage, 150mV Input Voltage Accuracy (worst case)
• 4-channel mode: CIN0-3, Internal reference voltage generator
• 3-channel mode: CIN0-2, External reference voltage source (CIN3) supply
Low Voltage Detect Circuit
• Low voltage detect to get into Back-up mode and
Reset
2.15V (Typ)
± 200mV at 8MHz
1.90V (Typ)
± 200mV at 4MHz
• Low voltage detect to control LVD_Flag bit
2.30V (Typ)
± 200mV at 8MHz
2.15V (Typ)
± 200mV at 4MHz
Operating Temperature Range
• –25
°
C to + 85
°
C
Operating Voltage Range
• 1.95V to 3.6V at 8MHz
Package Types
•
•
32-pin SOP
44-pin QFP
1-2
S3F80JB
BLOCK DIAGRAM (32-PIN PACKAGE)
PRODUCT OVERVIEW
P0.0-0.3 (INT0-INT3)
P0.4-P0.7(INT4) P1.0-1.7
Port0 Port1
V
DD
X
IN
X
OUT
LVD
IPOR(note)
Main
OSC
8-Bit
Basic
Timer
8-Bit
Timer0
/Counter
16-Bit
Timer1
/Counter
16-Bit
Timer2
/Counter
I/O Port and Interrupt
Control
SAM8RC CPU
64K-byte
FLASH
Memory
272-byte
Register File
TEST nRESET
Port2
P2.0-2.3
(INT5-INT8)
P2.4-2.7
(INT9)
(CIN0-CIN3)
Port3
P3.0/T0PWM/T0CAP/
SDAT/T1CAP/T2CAP
P3.1/REM/T0CK/SCLK
Comparator
Carrier Generator
(Counter A)
Figure 1-1. Block Diagram (32-pin)
NOTE
IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)
1-3
PRODUCT OVERVIEW
BLOCK DIAGRAM (44-PIN PACKAGE)
S3F80JB
V
DD
X
IN
X
OUT
LVD
IPOR(note)
Main
OSC
8-Bit
Basic
Timer
8-Bit
Timer0
/Counter
16-Bit
Timer1
/Counter
16-Bit
Timer2
/Counter
P0.0-0.3 (INT0-INT3)
P0.4-P0.7(INT4)
P1.0-1.7
Port0 Port1
I/O Port and Interrupt
Control
SAM8RC CPU
64K-byte
FLASH
Memory
272-byte
Register File
TEST nRESET
Port2
Port3
P2.0-2.3
(INT5-INT8)
P2.4-2.7
(INT9)
(CIN0-CIN3)
P3.0/T0PWM/T0CAP/SDAT
P3.1/REM/SCLK
P3.2/T0CK
P3.3/T1CAP/T2CAP
P3.4-P3.5
Comparator
Carrier Generator
(Counter A)
Port4
P4.0-P4.7
Figure 1-2. Block Diagram (44-pin)
NOTE
IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)
1-4
S3F80JB
PIN ASSIGNMENTS
PRODUCT OVERVIEW
VSS
XOUT
XIN
TEST
P2.5/INT9/CIN1
P2.6/INT9/CIN2 nRESET
P2.7/INT9/CIN3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
13
14
15
16
8
9
10
11
12
6
7
4
5
1
2
3
S3F80JB
(Top View)
32-SOP
20
19
18
17
25
24
23
22
21
32
31
30
29
28
27
26
VDD
P3.1/REM/T0CK/SCLK
P3.0/T0PWM/T0CAP/T1CAP/T2CAP/SDAT
P2.4/INT9/CIN0
P2.3/INT8
P2.2/INT7
P2.1/INT6
P2.0/INT5
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package)
1-5
PRODUCT OVERVIEW
PIN ASSIGNMENTS (Continued)
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4
P4.3
P4.2
P4.1
P4.0
P2.0/INT5
P2.1/INT6
P2.2/INT7
38
39
40
41
42
43
44
34
35
36
37
S3F80JB
(Top View)
(44-QFP)
18
17
16
15
14
13
12
22
21
20
19
P1.3
P1.2
P1.1
P4.7
P3.3/T1CAP/T2CAP
P3.2/T0CK
P1.0
P2.7/INT9/CIN3
P3.5
P3.4
nRESET
S3F80JB
Figure 1-4. Pin Assignment Diagram (44-Pin QFP Package)
1-6
S3F80JB PRODUCT OVERVIEW
Table 1-1. Pin Descriptions of 32-SOP
Pin
Names
Pin
Type
Pin Description
P0.0–P0.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED&R (note) circuit built in P0 for STOP releasing.
P1.0–P1.7 I/O I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type.
P2.0–P2.3
P2.4–P2.7
P3.0
I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. SED & R (note) circuit built in P2-P2.7 for STOP releasing. Also P2.4-
P2.7 can be assigned individually as analog input pins for Comparator.
I/O I/O port with bit-programmable pin. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software.
This port 3 pin has high current drive capability.
Also P3.0 can be assigned individually as an output pin for T0PWM or input pin for T0CAP.
In the tool mode, P3.0 is assigned as serial MTP interface pin; SDAT
P3.1
X OUT, X IN
I/O I/O port with bit-programmable pin. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software.
This port 3 pin has high current drive capability.
Also P3.1 can be assigned individually as an output pin for REM.
In the tool mode, P3.1 is assigned as serial MTP interface pin; SCLK
– System clock input and output pins nRESET
TEST
V
V
DD
SS
I System reset signal input pin and back-up mode input.
I Test signal input pin
(for factory use only; must be connected to V
SS
).
– Power supply input pin
– Ground pin
Circuit
Type
2 9–16
1
4 31
–
6
32 Pin
No.
25–28
29,5,6,8
2,3
(INT0–INT3)
– 4
(INT4)
–
Ext. INT
(INT5–INT8)
(INT9)
(CIN0-CIN3)
(SDAT)
–
7 –
– 32
– 1
Shared
Functions
REM
(SCLK)
–
–
–
1-7
PRODUCT OVERVIEW S3F80JB
Pin
Names
P0.0–P0.7
P1.0–P1.7
P2.0–P2.3
P2.4–P2.7
P3.0
Table 1-2. Pin Descriptions of 44-QFP
Pin
Type
Pin Description
I/O I/O port with bit-programmable pins.
Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control.
SED & R(note)circuit built in P0 for STOP releasing.
I/O I/O port with bit-programmable pins.
Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type.
I/O I/O port with bit-programmable pins.
Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control.
SED & R(note) circuit built in P2.4-P2.7 for STOP releasing. Also P2.4-P2.7 can be assigned individually as analog input pins for Comparator.
I/O I/O port with bit-programmable pin.
Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software.
This port 3pin has high current drive capability. Also P3.0 can be assigned individually as an output pin for T0PWM or input pin for T0CAP.
In the tool mode, P3.0 is assigned as serial MTP interface pin; SDAT
Circuit
Type
44 Pin
No.
Shared
Functions
1 30–37 Ext.
(INT0–INT3)
(INT4)
2 16
1
20–26
42–44
1, 2,
10,11,
15
–
Ext. INT
(INT5–INT8)
(INT9)
(CIN0-CIN3)
3 3 T0PWM/T0CAP
(SDAT)
NOTE: SED & R means “STOP Error Detect & Recovery”. The Stop Error Detect & Recovery Circuit is used to release stop mode and prevent abnormal-stop mode. Refer to page 8-11.
1-8
S3F80JB PRODUCT OVERVIEW
Pin
Names
P3.1
P3.2–P3.3
P3.4–P3.5
P4.0–P4.7
X
OUT
TEST
V
V
DD
SS
, X
IN nRESET
Table 1-2. Pin Descriptions of 44-QFP (Continued)
Pin
Type
Pin Description
I/O I/O port with bit-programmable pin. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software.
This port 3pin has high current drive capability.
Also P3.1 can be assigned individually as an output pin for REM.
In the tool mode, P3.1 is assigned as serial MTP interface pin; SCLK
I C-MOS Input port with a pull-up resistor
Circuit
Type
44 Pin
No.
4 4 REM
(SCLK)
Shared
Functions
5 17
18
(T0CK)
(T1CAP/T2CAP)
I/O I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. Pullup resistors can be assigned by software.
2 13–14 –
I/O I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type.
– System clock input and output pins
2 38–41
27–29
19
– 7,8
–
–
I
I
–
System reset signal input pin and back-up mode input.
Test signal input pin
(for factory use only; must be connected to V
SS
.)
Power supply input pin
6 12 –
_ 9
– 5
– 6
_
–
–
1-9
PRODUCT OVERVIEW
PIN CIRCUITS
V DD
Pull-Up
Resistor
(55k
Ω- typ)
Pull-up
Enable
V DD
Data
INPUT/OUTPUT
Output Disable
P2.4-P2.7 Only
P2CONx.x
CMPSEL.0-.3
External REF (P2.7 only)
Comparator
+
-
V SS
MUX
REF
External
Interrupt
Noise
Filter
Stop
Stop
Release
Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)
S3F80JB
1-10
S3F80JB
PIN CIRCUITS (Continued)
PRODUCT OVERVIEW
Pull-up
Enable
Data
Open-Drain
Output Disable
V DD
V DD
Pull-up
Resistor
(55k
Ω-Typ)
INPUT/OUTPUT
V SS
Normal
Input
Noise
Filter
Figure 1-6. Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)
1-11
PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
Pull-up
Enable
Port 3.0 Data
T0_PWM
Open-Drain
Output Disable
P3CON.2
M
U
X
Data
P3.0 Input
T0CAP/(T1CAP/T2CAP)
P3CON.2,6,7
M
U
X
Noise filter
V
DD
V DD
Pull-up
Resistor
(55k
Ω-Typ)
V SS
P3.0/T0PWM T0CAP/
(T1CAP/T2CAP)
Figure 1-7. Pin Circuit Type 3 (P3.0)
S3F80JB
1-12
S3F80JB
PIN CIRCUITS (Continued)
PRODUCT OVERVIEW
Pull-up
Enable
Port 3.1 Data
Carrier On/Off (P3.7)
CACON.2
P3CON.5
M
U
X
Data
V DD
Open-Drain
Output
Disable
V SS
P3.1 Input
T0CK
P3CON.5,6,7
M
U
X
Noise filter
Figure 1-8. Pin Circuit Type 4 (P3.1)
V DD
Pull-up
Resistor
(55k
Ω-Typ)
P3.1/REM
/(T0CK)
Input
T0CK : P3.2
T1CAP/T2CAP: P3.3
P3CON.2,6,7
M
U
X
Figure 1-9. Pin Circuit Type 5 (P3.2 and P3.3)
V DD
Pull-up
Resistor
(55k
Ω-Typ)
INPUT
1-13
PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
V DD
Pull-up
Resistor
(500k
Ω-Typ)
nRESET
Figure 1-10. Pin Circuit Type 6 (nRESET)
S3F80JB
1-14
2
ADDRESS SPACE
OVERVIEW
The S3F80JB microcontroller has two types of address space:
— Internal program memory (Flash memory)
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.
The S3F80JB has a programmable internal 64-Kbytes Flash ROM. An external memory interface is not implemented.
There are 333 mapped registers in the internal register file. Of these, 272 are for general-purpose use. ( This number includes a 16-byte working register common area that is used as a “scratch area” for data operations, a
192-byte prime register area, and a 64-byte area (Set 2) that is also used for stack operations). Twenty-two 8-bit registers are used for CPU and system control and 39 registers are mapped peripheral control and data registers.
2-1
S3F80JB ADDRESS SPACES
PROGRAM MEMORY
Program memory (Flash memory) stores program code or table data. The S3F80JB has 64-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–FFFFH of Flash memory
(See Figure 2-1).
The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (0000H – 00FFH except 03CH, 03DH, 03EH and 03FH) in this address range can be used as normal program memory. The location 03CH, 03DH, 03EH and 03FH is used as smart option ROM cell. If you use the vector address area to store program code, be careful to avoid overwriting vector addresses stored in these locations.
The program memory address at which program execution starts after reset is 0100H(default). If you use ISP TM sectors as the ISP TM software storage, the reset vector address can be changed by setting the Smart Option.
(Refer to Figure 2-2).
(Decimal)
65,536
(HEX)
FFFFH
384(256+128)byte
Internal RAM
FE80H
Internal
Program
Memory
(Flash)
S3F80JB(64Kbyte)
Note 1
255
0
ISP Sector
Interrupt Vector Area
Smart Option Rom Cell
01FFH, 02FFH, 04FFH or 08FFH
0FFH
03FH
03CH
00H
Figure 2-1. Program Memory Address Space
NOTES:
1. The size of ISP
TM sector can be varied by Smart Option. (Refer to Figure 2-2). According to the smart option setting related to the ISP, ISP reset vector address can be changed one of addresses to be select (200H, 300H, 500H or
900H).
2. ISP
TM sector can store On Board Program Software (Refer to chapter 15. Embedded Flash Memory Interface).
2-2
S3F80JB ADDRESS SPACES
SMART OPTION
Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is
0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable).
Before execution the program memory code, user can set the smart option bits according to the hardware option for user to want to select.
MSB .7
.6
.5
ROM Address: 003CH
.4
.3
Not used
.2
.1
.0
LSB
MSB .7
.6
.5
ROM Address: 003DH
.4
.3
Not used
.2
.1
.0
LSB
MSB .7
.6
.5
ROM Address: 003EH
.4
.3
.2
.1
.0
LSB
ISP Reset Vector Change Selection Bit: (1)
0 = OBP Reset vector address
1 = Normal vector (address 100H)
Not used
ISP Reset Vector Address Selection Bits: (2)
00 = 200H (ISP Area size: 256 bytes)
01 = 300H (ISP Area size: 512 bytes)
10 = 500H (ISP Area size: 1024 bytes)
11 = 900H (ISP Area size: 2048 bytes)
ISP Protection Size
Selection Bits: (4)
00 = 256 bytes
01 = 512 bytes
10 = 1024 bytes
11 = 2048 bytes
ISP Protection Enable/Disable Bit: (3)
0 = Enable (Not erasable)
1 = Disable (Erasable)
MSB .7
.6
.5
ROM Address: 003FH
.4
.3
.2
.1
.0
LSB
IPOR / LVD Control Bit
0 = IPOR enable
LVD disable in the stop mode (5)
1 = IPOR disable
LVD enable in the stop mode (6)
Frequency Selection Bits (7) :
Operating Frequency Range
111110 = 1MHz ~ 4MHz
11111 = 1MHz ~ 8MHz
Not used
Figure 2-2. Smart Option
2-3
S3F80JB ADDRESS SPACES
NOTES
1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area.
If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless.
2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).
If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).
If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H to 08FFH (2048bytes).
3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by 3EH.1 and 3EH.0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit
(3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.
5. If IPOR / LVD Control Bit (3FH.7) is '0', IPOR is enabled regardless of operating mode and LVD block is disabled in the STOP mode. So, the current consumption in the stop mode can be decreased by setting IPOR / LVD Control Bit (3FH.7) to ‘0’. Although LVD block is disabled, IPOR can make power on reset on the behalf of LVD. When CPU wakes up by any interrupts or reset sources, CPU comes back normal operating mode and LVD block is re-enabled automatically. But, user can’t disable LVD in the normal operating mode.
6. If IPOR / LVD Control Bit (3FH.7) is '1', LVD block will not be disabled in the STOP mode. In this case, LVD can make power on reset and IPOR is disabled in the normal operating and STOP mode.
7. If Frequency Selection Bits (3FH.6-2) are '11110', operating max frequency is from 1MHz to 4MHz, and operating voltage range is from 1.7V to 3.6V. If Frequency Selection Bits (3FH.6-2) are ‘11111’, operating max frequency is from 1MHz to 8MHz, and operating voltage range is from 1.95V to 3.6V.
2-4
S3F80JB ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3F80JB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set
1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area.
In case of S3F80JB the total number of addressable 8-bit registers is 333. Of these 333 registers, 22 bytes are for
CPU and system control registers, 39 bytes are for peripheral control and data registers, 16 bytes are used as shared working registers, and 272 registers are for general-purpose use.
The extension of register space into separately addressable areas (sets, banks) is supported by various addressing mode restrictions: the select bank instructions, SB0 and SB1.
Specific register types and the area occupied in the S3F80JB internal register space are summarized in Table 2-
1.
Table 2-1. The Summary of S3F80JB Register Type
Register Type
General-purpose registers (including the 16-byte common working register area, the 64-byte set 2 area and 192-byte prime register area of page 0)
CPU and system control registers
Mapped clock, peripheral, and I/O control and data registers
(bank 0: 27 registers, bank 1: 12 registers)
Total Addressable Bytes
Number of Bytes
272
22
39
333
2-5
S3F80JB ADDRESS SPACES
FFH
64
Bytes
E0H
DFH
D0H
CFH
Set 1
Bank1
Bank 0
System and
Peripheral
Control Register
(Register Addressing
Mode)
System Register
(Register Addressing
Mode)
Working Register
(Working Register
Addressing only)
C0H
E0H
32
Bytes
32
Bytes
Set 2
Page 0
General Purpose
Data Register
(Indirect Register or
Indexed Addressing
Modes or
Stack Operations)
Page 0
FFH
C0H
BFH
256
Bytes
192
Bytes
Prime
Data Register
(All Addressing
Mode)
00H
Figure 2-3. Internal Register File Organization
2-6
S3F80JB ADDRESS SPACES
REGISTER PAGE POINTER (PP)
The S3C8/S3F8-series architecture supports the logical expansion of the physical 333-byte internal register files
(using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer PP (DFH, Set 1, Bank0). In the S3F80JB microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to “page 0”.
Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always
'0000'automatically. Therefore, S3F80JB is always selected page 0 as the source and destination page for register addressing. These page pointer (PP) register settings, as shown in Figure 2-4, should not be modified during normal operation.
MSB .7
.6
Register Page Pointer (PP)
DFH ,Set 1, Bank0, R/W
.5
.4
.3
.2
.1
.0
LSB
Destination Register Page Seleciton Bits:
0 0 0 0 Destination: page 0
Source Register Page Selection Bits:
0 0 0 0 Source: page 0
NOTE: A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should not be modified to address other pages.
Figure 2-4. Register Page Pointer (PP)
2-7
S3F80JB ADDRESS SPACES
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3F80JB microcontroller, bank 1 is implemented. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing.
The upper two 32-byte area of set 1, bank 0, (E0H–FFH) contains 31mapped system and peripheral control registers. Also, the upper 32-byte area of set1, bank1 (E0H–FFH) contains 16 mapped peripheral control register.
The lower 32-byte area contains 15 system registers (D0H–DFH) and a 16-byte common working register area
(C0H–CFH). You can use the common working register area as a “scratch” area for data operations being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte working register area can only be accessed using working register addressing. (For more information about working register addressing, please refer to Chapter 3, “Addressing Modes,”)
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. The set 2 locations (C0H–FFH) is accessible on page 0 in the S3F80JB register space.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only
Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
2-8
S3F80JB ADDRESS SPACES
PRIME REGISTER SPACE
The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.).
The prime register area on page 0 is immediately addressable following a reset.
FFH
FCH
E0H
D0H
C0H
Bank 0
Set 1
Bank 1
FFH
Page 0
Set 2
C0H
BFH
Page 0
CPU and system control
General-purpose
Peripheral and IO
Prime
Register
Area
00H
Figure 2-5. Set 1, Set 2, and Prime Area Register Map
2-9
S3F80JB ADDRESS SPACES
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces:
All of the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
1 1 1 1 1 X X X
RP1 (Registers R8-R15)
Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block.
0 0 0 0 0 X X X
RP0 (Registers R0-R7)
~
Slice 32
Slice 1
FFH
F8H
F7H
F0H
Set 1
Only
CFH
C0H
~
10H
0FH
08H
07H
00H
Figure 2-6. 8-Byte Working Register Areas (Slices)
2-10
S3F80JB ADDRESS SPACES
USING THE REGISTER POINTERS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see
Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see
Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can define the working register area very flexibly to support program requirements.
PROGRAMMING TIP — Setting the Register Pointers
SRP #70H
RP0
← A0H, RP1 ← no change
← 00H, RP1 ← no change
LD RP1,#0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
RP1
0 0 0 0 0 X X X
RP0
8-Byte Slice
8-Byte Slice
0FH (R15)
08H
07H
00H (R0)
16-byte contiguous working register block
Figure 2-7. Contiguous 16-Byte Working Register Block
2-11
S3F80JB ADDRESS SPACES
8-Byte Slice
F7H (R7)
F0H (R0)
Register File
Contains 32
8-Byte Slices
07H (R15)
00H (R0)
16-byte non-contiguous working register block
1 1 1 1 0 X X X
RP0
0 0 0 0 0 X X X
RP1
8-Byte Slice
Figure 2-8. Non-Contiguous 16-Byte Working Register Block
PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0 #80H ;
;
R0
← R0 + R4 + C
ADC R0,R5
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used:
ADD 80H,81H
ADC 80H,82H
80H
← (80H) + (82H) + C
80H
← (80H) + (84H) + C
ADC 80H,85H
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.
2-12
S3F80JB ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.
Working register addressing differs from Register addressing because it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
Rn+1 n = Even address
Figure 2-9. 16-Bit Register Pair
2-13
S3F80JB ADDRESS SPACES
E0H
D0H
C0H
BFH
FFH
Special-Purpose Registers
Bank 1 Bank 0
Control
Registers
System
Registers
CFH
RP1
RP0
Register
Pointers
Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set
2). After a reset, RP0 points to locations C0H-C7H and
RP1 to locations C8H-CFH (that is, to the common working register area).
NOTE: In the S3F80JB microcontroller,only page0 is implemented.Page0 containsall of the addressable registers in the internal register file.
General-Purpose Registers
Prime
FFH
C0H
Registers
Set 2
00H
Register Addressing Only
Can be Pointed by Register Pointer
Page 0
All
Addressing
Modes
Page 0
Indirect
Register,
Indexed
Addressing
Modes
Figure 2-10. Register File Addressing
2-14
S3F80JB ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:
RP0
→ C0H–C7H
RP1
→ C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations.
Set 1
FFH
F0H
E0H
D0H
C0H
Following a hareware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH.
FFH
Page 0
Set 2
C0H
BFH
Page 0
~
Prime
Area
~
RP0 =
1 1 0 0 0 0 0 0
RP1 = 1 1 0 0 1 0 0 0
00H
Figure 2-11. Common Working Register Area
2-15
S3F80JB ADDRESS SPACES
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.
Example 1:
LD 0C2H,40H
Use working register addressing instead:
SRP #0C0H
LD R2,40H ; R2 (C2H)
← the value in location 40H
Example 2:
ADD 0C3H,#45H
Use working register addressing instead:
SRP #0C0H
ADD R3,#45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);
— The five high-order bits in the register pointer select an 8-byte slice of the register space;
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
2-16
S3F80JB ADDRESS SPACES
Selects
RP0 or RP1
Address OPCODE
RP0
RP1
Register pointer provides five high-order bits
4-bit address procides three low-order bits
Together they create an
8-bit register address
Figure 2-12. 4-Bit Working Register Addressing
0 1 1 1
RP0
0
0 1 1 1 0
0 0 0
1 1 0
Selects RP0
RP1
0 1 1 1 1 0 0 0
Register address
(76H)
R6
0 1 1 0
OPCODE
1 1 1 0
Instruction:
'INC R6'
Figure 2-13. 4-Bit Working Register Addressing Example
2-17
S3F80JB ADDRESS SPACES
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address. The three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five-address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
These address bits indicate
8-bit working register addressing
RP0
RP1
Selects
RP0 or RP1
1 1 0 0
Address
8-bit logical address
Three loworder bits
Register pointer provides five high-order bits
8-bit physical address
Figure 2-14. 8-Bit Working Register Addressing
2-18
S3F80JB ADDRESS SPACES
0 1 1 1 0
RP0
0 0 0
Selects RP1
1 1 0 0 1
R11
0 1 1
1 0
8-bit address from instruction
'LD R11, R2'
RP1
1 0 1 0 0 0
Specifies working register addressing
Register address (0ABH) 1 0 1 0 1 0 1 1
Figure 2-15. 8-Bit Working Register Addressing Example
2-19
S3F80JB ADDRESS SPACES
SYSTEM AND USER STACKS
S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3F80JB architecture supports stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS registers are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15.
High Address
PCL
PCL
PCH
Top of stack
PCH
Stack contents after a call instruction
Top of stack
Flags
Stack contents after an interrupt
Low Address
Figure 2-16. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL)
Register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in The S3F80JB, the SPL must be initialized to an 8-bit value in the range 00–FFH.
2-20
S3F80JB ADDRESS SPACES
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD SPL,#0FFH
; (Normally, the SPL is set to 0FFH by the initialization
•
•
•
PUSH PP
PUSH RP0 address address
← PP
← RP0
0FCH
← R3
•
•
•
POP R3 R3
← Stack address 0FCH
← Stack address 0FDH
POP PP
2-21
S3F80JB ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8/S3F8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction:
— Indirect Register (IR)
— Direct Address (DA)
— Relative Address (RA)
3-1
ADDRESSING MODES S3F80JB
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).
Working register addressing differs from Register addressing because it uses a register pointer to specify an 8byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory Register File
8-bit register file address
One-Operand
Instruction
(Example) dst
OPCODE
Points to one register in register file
Value used in instruction execution
OPERAND
Sample Instruction:
DEC CNTR ; Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
MSB Points to
RP0 ot RP1
Register File
RP0 or RP1
4-bit
Working Register
Two-Operand
Instruction
(Example)
Program Memory dst src
OPCODE
3 LSBs
Points to the woking register
(1 of 8)
Sample Instruction:
ADD R1, R2
OPERAND
Selected RP points to start of working register block
; Where R1 and R2 are registers in the curruntly
selected working register area.
Figure 3-2. Working Register Addressing
3-2
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be accessed using Indirect Register addressing mode.
8-bit register file address
One-Operand
Instruction
(Example)
Program Memory dst
OPCODE
Points to one register in register file
Address of operand used by instruction
Register File
ADDRESS
OPERAND
Value used in instruction execution
Sample Instruction:
RL @SHIFT ; Where SHIFT is the label of an 8-bit register address.
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Example
Instruction
References
Program
Memory
Program Memory dst
OPCODE
Points to
Register Pair
Sample Instructions:
CALL
JP
@RR2
@RR2
Register
Pair
Value used in instruction
Program Memory
OPERAND
16-Bit
Address
Points to
Program
Memory
Figure 3-4. Indirect Register Addressing to Program Memory
S3F80JB
3-4
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
4-bit
Working
Register
Address
Program Memory dst src
OPCODE
~
3 LSBs
Point to the
Woking Register
(1 of 8)
~
ADDRESS
~
~
Sample Instruction:
OR R3, @R6
Value used in instruction
OPERAND
Selected
RP points to start of woking register block
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
S3F80JB
MSB Points to
RP0 or RP1
Register File
RP0 or RP1
4-bit Working
Register Address
Example Instruction
References either
Program Memory or
Data Memory
Program Memory dst src
OPCODE
Next 2-bit Point
to Working
Register Pair
(1 of 4)
LSB Selects
Register
Pair
Program Memory or
Data Memory
Value used in
Instruction
OPERAND
16-Bit address points to program memory or data memory
Sample Instructions:
LCD
LDE
LDE
R5,@RR6
R3,@RR14
@RR4, R8
; Program memory access
; External data memory access
; External data memory access
NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB.
Selected
RP points to start of working register block
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented). You cannot, however, access locations C0H–FFH in set 1 using indexed addressing.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3–8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3–9).
The only instruction that supports indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory (if implemented).
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
Value used in
Instruction
~
OPERAND
~
Selected RP points to start of working register block
Two-Operand
Instruction
Example
+
Program Memory
Base Address dst/src x
OPCODE
3 LSBs
Points to one of the
Woking Registers
(1 of 8)
~
INDEX
~
Sample Instruction:
LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value.
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
INDEXED ADDRESSING MODE (Continued)
S3F80JB
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
Program Memory
OFFSET dst/src x
OPCODE
~ ~
Selected
RP points to start of working register block
4-bit Working
Register Address
NEXT 2 BITS
Point to Working
Register Pair
(1 of 4)
Register
Pair
16-Bit address added to offset
LSB Selects
8-Bit
+
16-Bit
Program Memory or
Data Memory
16-Bit
OPERAND
Value used in
Instruction
Sample Instructions:
LDC
LDE
R4, #04H[RR2]
R4,#04H[RR2]
; The values in the program address (RR2 + 04H)
are loaded into register R4.
; Identical operation to LDC example, except that
external data memory is accessed.
NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
INDEXED ADDRESSING MODE (Continued)
4-bit Working
Register Address
Program Memory
OFFSET
OFFSET dst/src x
OPCODE
MSB Points to
RP0 or RP1
NEXT 2 BITS
Point to Working
Register Pair
LSB Selects
16-Bit
+
16-Bit
~
Register File
RP0 or RP1
~
Selected
RP points to start of working register block
Register
Pair
Program Memory or
Data Memory
16-Bit address added to offset
16-Bit
OPERAND
Value used in
Instruction
Sample Instructions:
LDC
LDE
R4, #1000H[RR2]
R4,#1000H[RR2]
; The values in the program address (RR2 + 1000H)
are loaded into register R4.
; Identical operation to LDC example, except that
external data memory is accessed.
NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB.
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES S3F80JB
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Program Memory
Upper Address Byte
Lower Address Byte dst/src "0" or "1"
OPCODE
Memory
Address
Used
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Sample Instructions:
LDC
LDE
R5,1234H
R5,1234H
; The values in the program address (1234H)
are loaded into register R5.
; Identical operation to LDC example, except
that external data memory is accessed.
NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB.
Figure 3-10. Direct Addressing for Load Instructions
3-10
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Program
Memory
Address
Used
Lower Address Byte
Upper Address Byte
OPCODE
Sample Instructions:
JP
CALL
C,JOB1
DISPLAY
; Where JOB1 is a 16-bit immediate address
; Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES S3F80JB
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.
Program Memory
Current
Instruction dst
OPCODE
Next Instruction
LSB Must be Zero
Lower Address Byte
Upper Address Byte
Program Memory
Locations 0-255
Sample Instruction:
CALL #40H ; The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
3-12
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current Instruction
Displacement
OPCODE
Current
PC Value
Signed
Displacement Value
+
Sample Instructions:
JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
Figure 3-13. Relative Addressing
3-13
ADDRESSING MODES S3F80JB
IMMEDIATE MODE (IM)
In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.
The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The operand value is in the instruction)
Sample Instruction:
LD R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
4
CONTROL REGISTERS
OVERVIEW
In this section, detailed descriptions of the S3F80JB control registers are presented in an easy-to-read format.
You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order ( A~Z ) according to the register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual.
Data and counter registers are not described in detail in this reference section. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual.
41
CONTROL REGISTERS
Table 4-1. Mapped Registers (Bank0, Set1)
Register Name
Timer 0 Counter
Timer 0 Data Register
Timer 0 Control Register
Basic Timer Control Register
Clock Control Register
System Flags Register
Register Pointer 0
Register Pointer 1
Stack Pointer (Low Byte)
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request Register
Interrupt Mask Register
System Mode Register
Register Page Pointer
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 2 Interrupt Enable Register
Port 2 Interrupt Pending Register
Port 0 Pull-up Resistor Enable Register
Port 0 Control Register (High Byte)
Port 0 Control Register (Low Byte)
Port 1 Control Register (High Byte)
Port 1 Control Register (Low Byte)
Port 2 Control Register (High Byte)
Port 2 Control Register (Low Byte)
Port 2 Pull-up Enable Register
Port 3 Control Register
Port 4 Control Register
Port 0 Interrupt Enable Register
Port 0 Interrupt Pending Register
Mnemonic
T0CNT
T0DATA
T0CON
Decimal
208
209
210
BTCON
CLKCON
FLAGS
RP0
211
212
213
214
RP1 215
Location D8H is not mapped.
SPL 217
IPH
IPL
IRQ
IMR
SYM
PP
218
219
220
221
222
223
P1
P2
P3
P4
P2INT
P2PND
P0PUR
P0CONH
P0CONL
P1CONH
P1CONL
P2CONH
P2CONL
P2PUR
P3CON
P4CON
P0INT
P0PND
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
D9H
DAH
DBH
DCH
DDH
DEH
DFH
Hex
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
S3F80JB
R/W
R (NOTE)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R (NOTE)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4-2
S3F80JB CONTROL REGISTERS
Basic Timer Counter
External Memory Timing Register
Interrupt Priority Register
Table 4-1. Mapped Registers (Continued)
Register Name
Counter A Control Register
Counter A Data Register (High Byte)
Counter A Data Register (Low Byte)
Timer 1 Counter Register (High Byte)
Timer 1 Counter Register (Low Byte)
Timer 1 Data Register (High Byte)
Timer 1 Data Register (Low Byte)
Timer 1 Control Register
STOP Control Register
Mnemonic
CACON
CADATAH
CADATAL
T1CNTH
T1CNTL
Decimal
T1DATAH
T1DATAL
248
249
T1CON
STOPCON
250
251
Location FCH is not mapped.
BTCNT 253
EMT
IPR
243
244
245
246
247
254
255
FDH
FEH
FFH
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
Hex
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
Table 4-2. Mapped Registers (Bank1, Set1)
Register Name
LVD Control Register
Port 3 [4:5] Control Register
Port 4 Control Register (High Byte)
Port 4 Control Register (Low Byte)
Timer 2 Counter Register (High Byte)
Timer 2 Counter Register (Low Byte)
Mnemonic Decimal
LVDCON 224
P345CON
P4CONH
225
226
P4CONL
T2CNTH
T2CNTL
227
228
229
Timer 2 Data Register (High Byte)
Timer 2 Data Register (Low Byte)
Timer 2 Control Register
Comparator Mode Register
Comparison Result Register
Comparator Input Selection Register
T2DATAH
T2DATAL
T2CON
CMOD
CMPREG
CMPSEL
Flash Memory Sector Address Register (High Byte)
Flash Memory Sector Address Register (Low Byte)
Flash Memory User Programming Enable Register
Flash Memory Control Register
FMSECH
FMSECL
FMUSR
FMCON
Not mapped in address F0H to 0FFH.
236
237
238
239
230
231
232
233
234
235
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
Hex
E0
E1
E2
E3
E4
E5
R/W
R/W
R/W
R/W
R/W
R (NOTE)
R (NOTE)
R/W
R/W
R/W
R/W
R (NOTE)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R (NOTE)
R (NOTE)
R/W
R/W
R/W
W
R (NOTE)
R/W
R/W
4-3
CONTROL REGISTERS S3F80JB
Bit number(s) that is/are appended to the register name for bit addressing
Register mnemonic Full register name
Name of individual bit or bit function
Register address
(Hexadecimal)
Register address
(Set )
Register address
(Bank )
FLAGS
- System Flags Register
Bit Identifier
Reset Value
Read/Write
.7
x
R/W
.6
x
R/W
.5
x
R/W
.4
x
R/W
.3
x
R/W
D5H Set1 Bank0
.2
x
R/W
.1
0
R/W
.0
0
R/W
.7
.6
.5
Carry Flag Bit (C)
0
1
Operation dose not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit7
Zero Flag Bit (Z)
0 Operation result is a non-zero value
1 Operation result is zero
Sign Flag Bit (S)
0 Operation generates positive number (MSB = "0")
1 Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
' - ' = Not used
Addressing mode or modes you can use to modify register values
Description of the effect of specific bit settings
RESET value notation:
'-' = Not used
'x' = Undetermind value
'0' = Logic zero
'1' = Logic one
Bit number:
MSB = Bit 7
LSB = Bit 0
Figure 4-1. Register Description Format
4-4
S3F80JB CONTROL REGISTERS
BTCON
— Basic Timer Control Register D3H Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
.0
.1
.7 – .4
.3 and .2
Watchdog Timer Function Enable Bits (for System Reset)
1 0 1 0
Any other value
Disable watchdog timer function
Enable watchdog timer function
Basic Timer Input Clock Selection Bits f
OSC f
OSC f
OSC
1 1
/4096
/1024
/128
Not used for S3F80JB.
Basic Timer Counter Clear Bit
1
(1)
Clear the basic timer counter value
Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 (2)
1 Clear both block frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to ‘00H’. Immediately following the write operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".
4-5
CONTROL REGISTERS S3F80JB
CACON
— Counter A Control Register
Reset Value
Read/Write
Addressing Mode
.7 and .6
.2
.3
.5 and .4
.1
.0
Counter A Input Clock Selection Bits f
OSC f
OSC
/2 f
OSC
/4 f
OSC
/8
Counter A Interrupt Timing Selection Bits
0 0 Elapsed time for Low data value
0 1 Elapsed time for High data value
1 0 Elapsed time for combined Low and High data values used S3F80JB.
Counter A Interrupt Enable Bit
Counter A Start Bit
Counter A Mode Selection Bit
Counter A Output Flip-Flop Control Bit
0 Flip-Flop Low level (T-FF = Low)
1 Flip-flop High level (T-FF = High)
Bank0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
4-6
S3F80JB CONTROL REGISTERS
CLKCON
— System Clock Control Register D4H Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 – .5
.4 and .3
.2 – .0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Not used for S3F80JB
CPU Clock (System Clock) Selection Bits f f f f
OSC
OSC
OSC
OSC
/16
/8
/2
(non-divided)
(1)
Subsystem Clock Selection Bits (2)
1 0 1 Not used for S3F80JB.
Other value Select main system clock (MCLK)
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The
S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
4-7
CONTROL REGISTERS S3F80JB
CMOD
— Comparator Mode Register E9H Set1 Bank1
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Comparator Enable Bit
0 Comparator operation disable
1 Comparator operation enable
Conversion Timer Control Bit
0 8
× 2 7 / f
OSC
, 256 at 8 MHz
1 8
× 2 4 / f
OSC
, 32 at 8 MHz
.4
0 Internal reference, CIN0-3: Analog input
1 External reference, CIN0-2: Analog input, CIN3: Reference input
Not used for S3F80JB.
.3 – .0 Reference Voltage Selection Bits
Selected V
REF
= V
DD
× (N + 0.5)/16, N = 0 to 15
NOTE: You can select the number of analog input pin for your purpose by setting the CMPSEL.
4-8
S3F80JB CONTROL REGISTERS
CMPSEL
— Comparator Input Selection Register EBH Bank1
.0
.1
.2
Reset Value
Read/Write
Addressing Mode
.7– .4
.3
.7 .6 .5 .4 .3 .2 .1 .0
– – – – 0 0 0 0
Register addressing mode only
Not used for S3F80JB.
P2.7 Function Selection Bit
0 Normal I/O selection
1 Alternative function enable: CIN3
P2.6 Function Selection Bit
0 Normal I/O selection
1 Alternative function enable: CIN2
P2.5 Function Selection Bit
0 Normal I/O selection
1 Alternative function enable: CIN1
P2.4 Function Selection Bit
0 Normal I/O selection
1 Alternative function enable: CIN0
NOTE: If a bit of CMPSEL is set to “1”(Comparator input is selected), the port pin is operated as comparator input regardless of the P2CONH settings.
4-9
CONTROL REGISTERS S3F80JB
EMT
— External Memory Timing Register
(NOTE)
FEH Set1 Bank0
.6
Reset Value
Read/Write
Addressing Mode
.7
.5 and .4
.3 and .2
.7 .6 .5 .4 .3 .2 .1 .0
0 1 1 1 1 1 0 –
R/W R/W R/W R/W R/W R/W R/W –
Register addressing mode only
External WAIT Input Function Enable Bit
0 Disable WAIT input function for external device
1 Enable WAIT input function for external device
Slow Memory Timing Enable Bit
0 Disable slow memory timing
1 Enable slow memory timing
Program Memory Automatic Wait Control Bits
Data Memory Automatic Wait Control Bits
.0
0
1
Select internal register file area
Select external data memory area
Not used for S3F80JB
NOTE: The EMT register is not used for S3F80JB, because an external peripheral interface is not implemented in the
S3F80JB. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of
EMT values during normal operation may cause a system malfunction.
4-10
S3F80JB CONTROL REGISTERS
FLAGS
—
.1
.2
.3
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
Bank0
.7 .6 .5 .4 .3 .2 .1 .0 x x x x x x 0 0
R/W R/W R/W R/W R/W R/W R R/W
Register addressing mode only
Carry Flag Bit (C)
0 Operation does not generate a carry or borrow condition
1 Operation generates a carry-out or borrow into high-order bit 7
Zero Flag Bit (Z)
0 Operation result is a non-zero value
1 Operation result is zero
Sign Flag Bit (S)
0 Operation generates a positive number (MSB = "0")
1 Operation generates a negative number (MSB = "1")
Overflow Flag Bit (V)
0 Operation result is
≤ +127 or ≥ –128
1 Operation result is > +127 or < –128
Decimal Adjust Flag Bit (D)
0 Add operation completed
1 Subtraction operation completed
Half-Carry Flag Bit (H)
0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
Fast Interrupt Status Flag Bit (FIS)
0 Interrupt return (IRET) in progress (when read)
1 Fast interrupt service routine in progress (when read)
0 Bank 0 is selected
1 Bank 1 is selected
4-11
CONTROL REGISTERS S3F80JB
FMCON
— Flash Memory Control Register EFH Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 – .4
.3 – .1
.0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 – – – 0
R/W R/W R/W R/W –
Register addressing mode only
Flash Memory Mode Selection Bits
0110 Hard Lock mode (NOTE)
Others Not used for S3F80JB
Not used for S3F80JB
– – R/W
Flash Operation Start Bit (available for Erase and Hard Lock mode only)
0 Operation stop
1 Operation start (auto clear bit)
NOTE: Hard Lock mode is one of the flash protection modes. Refer to page 15-18.
4-12
S3F80JB CONTROL REGISTERS
FMSECH
— Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 – .0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Flash Memory Sector Address (High Byte)
Note: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.
FMSECL
— Flash Memory Sector Address Register(Low Byte) EDH Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 – .0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Flash Memory Sector Address (Low Byte)
Note: The low-byte flash memory sector address pointer value is the lower eight bits of the 16-bit pointer address.
FMUSR
— Flash Memory User Programming Enable Register EEH Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7—.0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Flash Memory User Programming Enable Bits
Other values Disable user programming mode
NOTES:
1. To enable flash memory user programming, write 10100101B to FMUSR.
2. To disable flash memory operation, write other value except 10100101B into FMUSR.
4-13
CONTROL REGISTERS S3F80JB
IMR
— Interrupt Mask Register DDH Set1 Bank0
.0
.1
.4
.3
.2
.5
Reset Value
Read/Write
Addressing Mode
.7
.6
.7 .6 .5 .4 .3 .2 .1 .0 x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
0 Disable (mask)
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0 Disable (mask)
Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.7–P2.4
0 Disable (mask)
Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.3–P2.0
0 Disable (mask)
Interrupt Level 3 (IRQ3) Enable Bit; Timer 2 Match or Overflow
0 Disable (mask)
Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt
0 Disable (mask)
Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0 Disable (mask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0 Disable (mask)
4-14
S3F80JB CONTROL REGISTERS
IPH
— Instruction Pointer (High Byte) DAH Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 – .1
Register addressing mode only
Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).
IPL
— Instruction Pointer (Low Byte) DBH Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 – .0
.7 .6 .5 .4 .3 .2 .1 .0 x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH register (DAH).
4-15
CONTROL REGISTERS S3F80JB
IPR
—
Reset Value
Read/Write
Addressing Mode
.7, .4, and .1
Priority Control Bits for Interrupt Groups A, B, and C
Bank0
.7 .6 .5 .4 .3 .2 .1 .0 x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 1 B > C > A
0 1 0 A > B > C
0 1 1 B > A > C
1 0 0 C > A > B
1 0 1 C > B > A
1 1 0 A > C > B
.3
.5
.2
.6
.0
Interrupt Subgroup C Priority Control Bit
0
1
0
1
1
IRQ6 > IRQ7
IRQ7 > IRQ6
Interrupt Group C Priority Control Bit
IRQ5 > (IRQ6, IRQ7)
(IRQ6, IRQ7) > IRQ5
Interrupt Subgroup B Priority Control Bit
0 IRQ3>IRQ4
1 IRQ4>IRQ3
Interrupt Group B Priority Control Bit
(IRQ3, IRQ4) > IRQ2
Interrupt Group A Priority Control Bit
0 IRQ0 > IRQ1
1 IRQ1 > IRQ0
NOTE: The S3F80JB interrupt structure uses eight levels: IRQ0-IRQ7.
(See Note)
(See Note)
4-16
S3F80JB CONTROL REGISTERS
IRQ
—
.1
.2
.3
.0
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
Bank0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R R R R R R R R
Register addressing mode only
Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4
1 Pending
Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0
1 Pending
Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4
1 Pending
Level 4 (IRQ4) Request Pending Bit; External Interrupts P2.3–P2.0
1 Pending
Level 3 (IRQ3) Request Pending Bit; Timer 2 Match/Capture or Overflow
1 Pending
Level 2 (IRQ2) Request Pending Bit; Counter A Interrupt
1 Pending
Level 1 (IRQ1) Request Pending Bit; Timer 1 Match/Capture or Overflow
1 Pending
Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow
1 Pending
4-17
CONTROL REGISTERS S3F80JB
LVDCON
— LVD Control Register E0H Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 – .1
.0
.7 .6 .5 .4 .3 .2 .1 .0
– – – – – – – 0
Register addressing mode only
Not used for S3F80JB.
LVD Flag (2.3V) Indicator Bit
0 V
DD
≥
LVD_FLAG Level (2.3V)
1 V
DD
< LVD_FLAG Level (2.3V)
NOTE: When LVD detects LVD_FLAG level (2.3V), LVDCON.0 flag bit is set automatically. When VDD is upper 2.3V,
LVDCON.0 flag bit is cleared automatically.
4-18
S3F80JB CONTROL REGISTERS
P0CONH
— Port 0 Control Register (High Byte) E8H Set1 Bank0
.1 and .0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P0.7/INT4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P0.6/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
P0.5/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
P0.4/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector address
(E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
(P0PUR.7 – P0PUR.4)
4-19
CONTROL REGISTERS S3F80JB
P0CONL
— Port 0 Control Register (Low Byte) E9H Set1 Bank0
.1 and .0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P0.3/INT3 Mode Selection Bits
0
1
P0.2/INT2 Mode Selection Bits
0
1
P0.1/INT1 Mode Selection Bits
0
1
P0.0/INT0 Mode Selection Bits
0
1
1
1
1
1
1
1
C-MOS input mode; interrupt on rising and falling edges
C-MOS input mode; interrupt on rising edges
C-MOS input mode; interrupt on rising and falling edges
C-MOS input mode; interrupt on rising edges
C-MOS input mode; interrupt on rising and falling edges
C-MOS input mode; interrupt on rising edges
C-MOS input mode; interrupt on rising and falling edges
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector address.
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
(P0PUR.3 – P0PUR.0)
4-20
S3F80JB CONTROL REGISTERS
P0INT
— Port 0 External Interrupt Enable Register F1H Set1 Bank0
.1
.2
.3
.0
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P0.7 External Interrupt (INT4) Enable Bit
P0.6 External Interrupt (INT4) Enable Bit
P0.5 External Interrupt (INT4) Enable Bit
P0.4 External Interrupt (INT4) Enable Bit
P0.3 External Interrupt (INT3) Enable Bit
P0.2 External Interrupt (INT2) Enable Bit
P0.1 External Interrupt (INT1) Enable Bit
P0.0 External Interrupt (INT0) Enable Bit
4-21
CONTROL REGISTERS S3F80JB
P0PND
— Port 0 External Interrupt Pending Register F2H Set1 Bank0
.0
.1
.2
.3
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P0.7 External Interrupt (INT4) Pending Flag Bit (see Note)
0 No P0.7 external interrupt pending (when read)
1 P0.7 external interrupt is pending (when read)
P0.6 External Interrupt (INT4) Pending Flag Bit
0 No P0.6 external interrupt pending (when read)
1 P0.6 external interrupt is pending (when read)
P0.5 External Interrupt (INT4) Pending Flag Bit
0 No P0.5 external interrupt pending (when read)
1 P0.5 external interrupt is pending (when read)
P0.4 External Interrupt (INT4) Pending Flag Bit
0 No P0.4 external interrupt pending (when read)
1 P0.4 external interrupt is pending (when read)
P0.3 External Interrupt (INT3) Pending Flag Bit
0 No P0.3 external interrupt pending (when read)
1 P0.3 external interrupt is pending (when read)
P0.2 External Interrupt (INT2) Pending Flag Bit
0 No P0.2 external interrupt pending (when read)
1 P0.2 external interrupt is pending (when read)
P0.1 External Interrupt (INT1) Pending Flag Bit
0 No P0.1 external interrupt pending (when read)
1 P0.1 external interrupt is pending (when read)
P0.0 External Interrupt (INT0) Pending Flag Bit
0 No P0.0 external interrupt pending (when read)
1 P0.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt pending flag (P0PND.7–0) has no effect.
4-22
S3F80JB CONTROL REGISTERS
P0PUR
— Port 0 Pull-up Resistor Enable Register E7H Set1 Bank0
.1
.2
.3
.0
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P0.7 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.6 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.5 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.4 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.3 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.2 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.1 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
P0.0 Pull-up Resistor Enable Bit
0 Disable pull-up resistor
4-23
CONTROL REGISTERS S3F80JB
P1CONH
— Port 1 Control Register (High Byte) EAH Set1 Bank0
.1 and .0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.7 .6 .5 .4 .3 .2 .1 .0
1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P1.7 Mode Selection Bits
1 1 C-MOS input with pull up mode
P1.6 Mode Selection Bits
1 1 C-MOS input with pull up mode
P1.5 Mode Selection Bits
1 1 C-MOS input with pull up mode
P1.4 Mode Selection Bits
1 1 C-MOS input with pull up mode
4-24
S3F80JB CONTROL REGISTERS
P1CONL
— Port 1 Control Register (Low Byte) EBH Set1 Bank0
.1 and .0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P1.3 Mode Selection Bits
0 0 C-MOS input mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
P1.2 Mode Selection Bits
0 0 C-MOS input mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
P1.1 Mode Selection Bits
0 0 C-MOS input mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
P1.0 Mode Selection Bits
0 0 C-MOS input mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
4-25
CONTROL REGISTERS S3F80JB
P2CONH — Port 2 Control Register (High Byte) ECH Set1 Bank0
.1 and .0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P2.7/INT9 Mode Selection Bits
0
1
P2.6/INT9 Mode Selection Bits
0
1
P2.5/INT9 Mode Selection Bits
0
1
P2.4/INT9 Mode Selection Bits
0
1
1
1
1
1
1
1
C-MOS input mode; interrupt on rising and falling edges
C-MOS input mode; interrupt on rising edges
C-MOS input mode; interrupt on rising and falling edges
C-MOS input mode; interrupt on rising edges
C-MOS input mode; interrupt on rising and falling edges
C-MOS input mode; interrupt on rising edges
C-MOS input mode; interrupt on rising and falling edges
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. Pull-up resistors can be assigned to individual port2 pins by making the appropriate settings to the P2PUR control register, location EEH, set 1, bank0.
2. Analog comparator inputs (CIN0-CIN3) for P2.4-P2.7 can be assigned to individual port 2 pins by making the appropriate settings to the CMPSEL register, location EBH, set 1, bank1. If an analog comparator input is selected by the CMPSEL register, normal I/O inputs for P2.4-P2.7 are disconnected regardless of P2CONH register’s setting value.
4-26
S3F80JB CONTROL REGISTERS
P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.1 and .0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P2.3/INT8 Mode Selection Bits
0
0
1
1
1
1
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
0
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising edges and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.2/INT7 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising edges and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.1/INT6 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising edges and falling edges
1
1
0
1
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.0/INT5 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising edges and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control register, location EEH, set 1,bank0.
4-27
CONTROL REGISTERS S3F80JB
P2INT
— Port 2 External Interrupt Enable Register E5H Set1 Bank0
.1
.2
.3
.0
.4
5.
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P2.7 External Interrupt (INT9) Enable Bit
P2.6 External Interrupt (INT9) Enable Bit
P2.5 External Interrupt (INT9) Enable Bit
P2.4 External Interrupt (INT9) Enable Bit
P2.3 External Interrupt (INT8) Enable Bit
P2.2 External Interrupt (INT7) Enable Bit
P2.1 External Interrupt (INT6) Enable Bit
P2.0 External Interrupt (INT5) Enable Bit
4-28
S3F80JB CONTROL REGISTERS
P2PND
— Port 2 External Interrupt Pending Register E6H Set1 Bank0
Reset Value
Read/Write
.0
.2
.3
.1
.5
.4
.6
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P2.7 External Interrupt (INT9) Pending Flag Bit (see Note)
0
1
0
1
No P2.7 external interrupt pending (when read)
P2.7 external interrupt is pending (when read)
P2.6 External Interrupt (INT9) Pending Flag Bit
0
1
P2.5 External Interrupt (INT9) Pending Flag Bit
0
1
No P2.5 external interrupt pending (when read)
P2.5 external interrupt is pending (when read)
P2.4 External Interrupt (INT9) Pending Flag Bit
0
1
P2.3 External Interrupt (INT8) Pending Flag Bit
0
1
No P2.6 external interrupt pending (when read)
P2.6 external interrupt is pending (when read)
No P2.4 external interrupt pending (when read)
P2.4 external interrupt is pending (when read)
No P2.3 external interrupt pending (when read)
P2.3 external interrupt is pending (when read)
P2.2 External Interrupt (INT7) Pending Flag Bit
No P2.2 external interrupt pending (when read)
P2.2 external interrupt is pending (when read)
P2.1 External Interrupt (INT6) Pending Flag Bit
0
1
No P2.1 external interrupt pending (when read)
P2.1 external interrupt is pending (when read)
P2.0 External Interrupt (INT5) Pending Flag Bit
0 No P2.0 external interrupt pending (when read)
1 P2.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt rending flag (P2PND.0–7) has no effect.
4-29
CONTROL REGISTERS S3F80JB
P2PUR
— Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0
.1
.2
.3
.0
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P2.7 Pull-up Resistor Enable Bit
P2.6 Pull-up Resistor Enable Bit
P2.5 Pull-up Resistor Enable Bit
P2.4 Pull-up Resistor Enable Bit
P2.3 Pull-up Resistor Enable Bit
P2.2 Pull-up Resistor Enable Bit
P2.1 Pull-up Resistor Enable Bit
P2.0 Pull-up Resistor Enable Bit
4-30
S3F80JB CONTROL REGISTERS
.5
.4 and .3
P3CON
— Port 3 Control Register EFH Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Package Selection and Alternative Function Select Bits
0 0 32 pin package
P3.0: T0PWM/T0CAP/T1CAP/T2CAP, P3.1: REM/T0CK
Others 42/44 pin package
P3.0: T0PWM/T0CAP, P3.3: T1CAP/T2CAP
P3.1: REM, P3.2: T0CK
P3.1 Function Selection Bit
0 Normal I/O selection
1 Alternative function enable (REM/T0CK)
P3.1 Mode Selection Bits
0 0 Schmitt trigger input mode
1 0 Push pull output mode
1 1 Schmitt trigger input with pull up resistor.
.1 and .0
0 Normal I/O selection
1 Alternative function enable (P3.0: T0PWM/T0CAP, P3.3: T1CAP/T2CAP)
P3.0 Mode Selection Bits
0 0 Schmitt trigger input mode
1 0 Push pull output mode
1 1 Schmitt trigger input with pull up resistor.
4-31
CONTROL REGISTERS S3F80JB
NOTES:
1. The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following
Port 3 pin functions (bit 6 is not used for the S3F80JB: a. Port3, bit 7: carrier signal on (“1”) or off (“0”). b. Port3, bit 1,0: P3.1/REM/T0CK pin, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin.
c. Port3, bit 3,2: P3.3, P3.2 are selected only to input pin with pull up resistor automatically.
d. Port3, bit 5,4: P3.5, P3.4 are selected into digital I/O by setting P345CON register at E1H, Set1, Bank1.
2. The alternative function enable/disable are enabled in accordance with function selection bit (bit5 and bit2).
3. In case of 42/44pin package, the pin assign for alternative functions can be selectable relating to mode selection bit (bit0,
1, 2, 3, 4 and 5)
4. Following Table is the specific example about the alternative function and pin assignment according to the each bit control of P3CON in 42/44pin package.
Table 4-3. Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package
P3CON
B5 B4 B3
Each Function Description and Assignment to P3.0–P3.3
P3.0 P3.1 P3.2 P3.3
0
0
1
1
1
0
0
0 x x x x x
0
1
0 x x x x x
0
1
1
0
1
1
1
1
0
0
0 x
0
1
0
1 x x x x
0
1
1
0 x x x
Normal I/O
T0_CAP
T0_CAP
T0PWM
T0PWM
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal Input
Normal Input
REM
Normal Input
Normal Input
Normal Input
Normal Input
Normal Input
T0CK
T0CK
T0CK
Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
Normal Input
Normal Input
Normal Input
1 1 0 0 x x Normal I/O REM T0CK Normal Input
1 0 0 1 0 0 T0_CAP Normal T0CK/Normal T1CAP/Normal
1 1 1 1 1 1 T0_CAP Normal T0CK/Normal T1CAP/Normal
1 0 1 1 0 1 T0PWM
1 1 0 1 1 0 T0PWM
REM
REM T0CK/Normal Input
1 0 0 1 0 1 T0PWM Normal T0CK/Normal T1CAP/Normal
1 1 1 1 1 0 T0PWM Normal T0CK/Normal T1CAP/Normal
1 0 1 1 0 0 T0_CAP
1 1 0 1 1 1 T0_CAP
REM
REM
T0CK/Normal
T0CK/Normal
Input
Input
4-32
S3F80JB CONTROL REGISTERS
P345CON
— Port3[4:5] Control Register E1H Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .1
.0
.7 .6 .5 .4 .3 .2 .1 .0
0 1 0 1 – – – 0
R/W R/W R/W R/W – – – R/W
Register addressing mode only
P3.5 Mode Selection Bits
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
P3.4 Mode Selection Bits
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
Not used for S3F80JB.
Port 4 Control Register Selection Bit
1 P4CONH/P4CONL Register selection
NOTE: After CPU reset, P3.4 and P3.5 will be Open-drain output mode by the reset value of P345CON register at E1H,
Set1, Bank1. P345CON will be initialized as “50h” to set P3.4 into the open-drain output mode after reset operation.
Port4 control register P4CON will be selected by the reset value of P345CON.0 bit. If you use the Port4 input and output mode, set P345CON.0 to “1”.
4-33
CONTROL REGISTERS S3F80JB
P4CON
— Port 4 Control Register F0H Set1 Bank0
.1
.2
.3
.0
.4
.5
.6
Reset Value
Read/Write
Addressing Mode
.7
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P4.7 Mode Selection Bit
P4.6 Mode Selection Bit
P4.5 Mode Selection Bit
P4.4 Mode Selection Bit
P4.3 Mode Selection Bit
P4.2 Mode Selection Bit
P4.1 Mode Selection Bit
P4.0 Mode Selection Bit
4-34
S3F80JB CONTROL REGISTERS
P4CONH
— Port 4 Control Register (High Byte) E2H Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.1 and .0
.7 .6 .5 .4 .3 .2 .1 .0
1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P4.7 Mode Selection Bits
0
1
1
0
0
1
C-MOS input mode
Push-pull output mode
C-MOS input with pull up mode
P4.6 Mode Selection Bits
0
1
1
0
0
1
C-MOS input mode
Push-pull output mode
C-MOS input with pull up mode
P4.5 Mode Selection Bits
0
1
1
0
0
1
C-MOS input mode
Push-pull output mode
C-MOS input with pull up mode
P4.4 Mode Selection Bits
0 0 C-MOS input mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
NOTE: After CPU reset, P4.7- P4.4 will be C-MOS input with pull up mode by the reset value of P4CONH register.
4-35
CONTROL REGISTERS S3F80JB
P4CONL
— Port 4 Control Register (Low Byte) E3H Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.1 and .0
.7 .6 .5 .4 .3 .2 .1 .0
1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P4.3 Mode Selection Bits
1 1 C-MOS input with pull up mode
P4.2 Mode Selection Bits
1 1 C-MOS input with pull up mode
P4.1 Mode Selection Bits
1 1 C-MOS input with pull up mode
P4.0 Mode Selection Bits
1 1 C-MOS input with pull up mode
NOTE: After CPU reset, P4.3 – P4.0 will be C-MOS input with pull up mode by the reset value of P4CONL register.
4-36
S3F80JB CONTROL REGISTERS
PP
— Register Page Pointer DFH Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 – .4
.3 – .0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Destination Register Page Selection Bits
Destination: page 0
(See Note)
Source Register Page Selection Bits
Source: page 0 (See Note)
NOTE: In the S3F80JB microcontroller, a paged expansion of the internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to ‘0000B’ following a hardware reset. These values should not be changed curing normal
operation.
4-37
CONTROL REGISTERS S3F80JB
RP0
—
Reset Value
Read/Write
Addressing Mode
.7 – .3
Bank0
.7 .6 .5 .4 .3 .2 .1 .0
1 1 0 0 0 – – –
R/W R/W R/W R/W R/W – – –
Register addressing mode only
Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 248-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1,bank0, selecting the 8-byte working register slice C0H–C7H.
Not used for S3F80JB. .2 – .0
RP1
—
Reset Value
Read/Write
Addressing Mode
.7 – .3
.2 – .0
Bank0
.7 .6 .5 .4 .3 .2 .1 .0
1 1 0 0 1 – – –
R/W R/W R/W R/W R/W – – –
Register addressing mode only
Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 248-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, bank0, selecting the 8-byte working register slice C8H–CFH.
Not used for S3F80JB.
4-38
S3F80JB CONTROL REGISTERS
SPL
— Stack Pointer (Low Byte) D9H Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 – .0
.7 .6 .5 .4 .3 .2 .1 .0 x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only.
Stack Pointer Address (Low Byte)
The SP value is undefined following a reset.
STOPCON
— Stop Control Register FBH Set1 Bank0
Reset Value
Read/Write
Addressing Mode
.7—.0
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
W W W W W W W W
Register addressing mode only
Stop Control Register Enable Bits
Other value Disable STOP Mode
NOTES:
1. To get into STOP mode, stop control register must be enabled just before STOP instruction.
2. When STOP mode is released, stop control register (STOPCON) value is cleared automatically.
3. It is prohibited to write another value into STOPCON.
4-39
CONTROL REGISTERS S3F80JB
SYM
— System Mode Register DEH Set1 Bank0
.0
.1
Reset Value
Read/Write
Addressing Mode
.7
.6 and .5
.4 – .2
0
1
.7 .6 .5 .4 .3 .2 .1 .0
0 – – x x x 0 0
Register addressing mode only
Tri-State External Interface Control Bit
Fast Interrupt Enable Bit
0
1
(4)
Disable fast interrupt processing
Enable fast interrupt processing
(1)
Normal operation (disable tri-state operation)
Set external interface lines to high impedance (enable tri-state operation)
Not used for S3F80JB (2)
Fast Interrupt Level Selection Bits (3)
Global Interrupt Enable Bit (5)
0 Disable global interrupt processing
1 Enable global interrupt processing
NOTES:
1. Because an external interface is not implemented for the S3F80JB, SYM.7 must always be "0".
2. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a “1” to this bit during normal operation, a system malfunction may occur.
3. You can select only one interrupt level at a time for fast interrupt processing.
4. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
5. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"
4-40
S3F80JB CONTROL REGISTERS
T0CON
— Timer 0 Control Register D2H Set 1 Bank0
Reset Value
Read/Write
Addressing Mode
.7 – .6
.2
.3
.5 and .4
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Timer 0 Input Clock Selection Bits f
OSC
/4096 f
OSC
/256 f
OSC
/8
1 1 External clock input (at the T0CK pin, P3.1 or P3.2)
Timer 0 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Capture mode (rising edges, counter running, OVF interrupt can occur)
1 0 Capture mode (falling edges, counter running, OVF interrupt can occur)
1 1 PWM mode (Match and OVF interrupt can occur)
Timer 0 Counter Clear Bit
0 No effect (when write)
1 Clear T0 counter, T0CNT (when write)
Timer 0 Overflow Interrupt Enable Bit (note)
0 Disable T0 overflow interrupt
0 Disable T0 match/capture interrupt
1 Enable T0 match/capture interrupt
0 No T0 match/capture interrupt pending (when read)
0 Clear T0 match/capture interrupt pending condition (when write)
1 T0 match/capture interrupt is pending (when read)
1 No effect (when write)
NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0 match/capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine (S/W).
4-41
CONTROL REGISTERS S3F80JB
T1CON
— Timer 1 Control Register FAH Bank0
Reset Value
Read/Write
Addressing Mode
.7 and .6
.0
.1
.2
.3
.5 and .4
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Timer 1 Input Clock Selection Bits f
OSC f
OSC f
OSC
0
1
1
1
1
0
/4
/8
/16
1 1 Internal clock (counter A flip-flop, T-FF)
Timer 1 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
Capture mode (rising edges, counter running, OVF can occur)
Capture mode (falling edges, counter running, OVF can occur)
Timer 1 Counter Clear Bit
Clear T1 counter, T1CNT (when write)
Timer 1 Overflow Interrupt Enable Bit (note)
Enable T1 overflow interrupt
Timer 1 Match/Capture Interrupt Enable Bit
Timer 1 Match/Capture Interrupt Pending Flag Bit
0
0
1
No T1 match/capture interrupt pending (when read)
Clear T1 match/capture interrupt pending condition (when write)
T1 match/capture interrupt is pending (when read)
NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/ capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine (S/W).
4-42
S3F80JB CONTROL REGISTERS
T2CON
— Timer 2 Control Register E8H Set1 Bank1
Reset Value
Read/Write
Addressing Mode
.7 and .6
.3
.5 and .4
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Timer 2 Input Clock Selection Bits f
OSC
/4 f
OSC
/8 f
OSC
/16
1 1 Internal clock (counter A flip-flop, T-FF)
Timer 2 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Capture mode (rising edges, counter running, OVF can occur)
1 1 Capture mode (rising and falling edges, counter running, OVF can occur)
Timer 2 Counter Clear Bit
0 No effect (when write)
1 Clear T2 counter, T2CNT (when write)
0
1
Disable T2 overflow interrupt
Enable T2 overflow interrupt
0
1
Disable T2 match/capture interrupt
Enable T2 match/capture interrupt
0 No T2 match/capture interrupt pending (when read)
0 Clear T2 match/capture interrupt pending condition (when write)
1 T2 match/capture interrupt is pending (when read)
1 No effect (when write)
NOTE: A timer 2 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 2 match/ capture interrupt, IRQ3, vector F2H, must be cleared by the interrupt service routine (S/W).
4-43
S3F80JB INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The
SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0–IRQ7, also called level 0 – level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3F80JB interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are simply identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR register settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors used for S3C8/S3F8-series devices is always much smaller.) If an interrupt level has more than one vector address, the vector priorities are set in hardware. The S3F80JB uses eighteen vectors. Two vector addresses are shared by four interrupt sources.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for example. Each vector can have several interrupt sources. In the S3F80JB interrupt structure, there are 24 possible interrupt sources.
When a service routine starts, the respective pending bit is either cleared automatically by hardware or is must be cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method is used to clear its respective pending bit.
5-1
INTERRUPT STRUCTURE S3F80JB
INTERRUPT TYPES
The three components of the S3C8/S3F8-series interrupt structure described above — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (See
Figure 5-1):
Type 1: One level (IRQn) + one vector (V
1
) + one source (S
1
)
Type 2: One level (IRQn) + one vector (V
1
) + multiple sources (S
1
– S n
)
Type 3: One level (IRQn) + multiple vectors (V
1
– V n
) + multiple sources (S
1
– S n
, S n+1
– S n+m
)
In the S3F80JBmicrocontroller, all three interrupt types are implemented.
Type 1:
Type 2:
Type 3:
Levels
IRQn
IRQn
IRQn
Vectors
V
V
V
V
V
V
1
1
1
2
3 n
NOTE: The number of S n and V n value is expandable.
Sources
S 1
S 2
S 3
S n
S n + 1
S
1
S
1
S 2
S 3
S n
S n + 2
S n + m
Figure 5-1. S3C8/S3F8-Series Interrupt Types
5-2
S3F80JB INTERRUPT STRUCTURE
The S3F80JB microcontroller supports twenty-four interrupt sources. Sixteen of the interrupt sources have a corresponding interrupt vector address; the remaining eight interrupt sources share by two vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts: All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.
5-3
INTERRUPT STRUCTURE
Levels(8)
RESET
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Vectors(18)
100H
FCH
FAH
F6H
F4H
ECH
F2H
F0H
1
0
1
0
1
0
D6H
D4H
D2H
D0H
1
0
3
2
D8H
E6H
E4H
E2H
E0H
E8H
3
2
1
0
Sources(24)
Basic timer overflow
Timer 0 match/capture
Timer 0 overflow
Timer 1 match/capture
Timer 1 overflow
Counter A
Timer 2 match/capture
Timer 2 overflow
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
Figure 5-2. S3F80JB Interrupt Structure
NOTE: Reset interrupt vector address (Basic timer overflow) can be varied by smart option.
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Reset/Clear
H/W
S/W
H/W
S/W
H/W
H/W
S/W
H/W
S3F80JB
5-4
S3F80JB INTERRUPT STRUCTURE
INTERRUPT VECTOR ADDRESSES
All interrupt vector addresses for the S3F80JB interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH (See Figure 5-3).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
The program reset address in the ROM is 0100H. Reset address can be changed by smart option (Refer to Table
15-3 or Figure 2-2).
(Decimal)
65,536
64-Kbyte
Internal Program Memory
(Flash Memory)
(HEX)
FFFFH
01FFH, 02FFH, 04FFH or 08FFH
255
ISP Sector
Interrupt Vector Area
Smart Option Rom Cell
0
00FFH
003FH
003CH
0000H
Figure 5-3. ROM Vector Address Area
5-5
INTERRUPT STRUCTURE S3F80JB
232
230
228
226
224
216
216
216
216
214
212
210
208
Vector Address
Decimal
Value
Hex
Value
256
252
100H
FCH
250
246
244
236
FAH
F6H
F4H
ECH
246
244
232
232
232
F2H
F0H
E8H
E8H
E8H
E8H
E6H
E4H
E2H
E0H
D8H
D8H
D8H
D8H
D6H
D4H
D2H
D0H
Table 5-1. S3F80JB Interrupt Vectors
Interrupt Source
Basic timer overflow/POR
Timer 0 match/capture
Timer 0 overflow
Timer 1 match/capture
Timer 1 overflow
Counter A
Timer 2 match/capture
Timer 2 overflow
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
Level
RESET
IRQ0
IRQ1
IRQ2
IRQ3
IRQ7
IRQ6
IRQ5
IRQ4
Request
0
–
–
–
–
3
2
1
–
3
2
1
0
Level
–
1
0
1
0
–
1
0
–
–
–
Reset/Clear
H/W
√
√
√
√
√
S/W
NOTES:
1. Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on.
2. If two or more interrupts within the same level content, the interrupt with the lowest vector address usually
has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.
3. Reset (Basic timer overflow or POR) interrupt vector address can be changed by smart option
(Refer to Table 15-3 or Figure 2-2).
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
5-6
S3F80JB INTERRUPT STRUCTURE
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur, and according to the established priorities.
NOTE:
The system initialization routine that is executed following a reset must always contain an EI instruction to globally enable the interrupt structure.
During normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can manipulate SYM.0 directly to enable or disable interrupts, we recommend that you use the EI and DI instructions instead.
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing:
— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source).
— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented).
Control Register
Interrupt Mask Register
Interrupt Priority Register
Interrupt Request Register
System Mode Register
Table 5-2. Interrupt Control Register Overview
ID R/W Function Description
IMR R/W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0–IRQ7.
IPR R/W Controls the relative processing priorities of the interrupt levels.
The eight levels of the S3F80JB are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is
IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
IRQ R This register contains a request pending bit for each interrupt level.
SYM R/W A dynamic global interrupt processing enables/disables, fast interrupt processing, and external interface control (an external memory interface is not implemented in the S3F80JB microcontroller).
5-7
INTERRUPT STRUCTURE S3F80JB
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by a specific interrupt level and source.
The system-level control points in the interrupt structure are, therefore:
— Global interrupt enable and disable (by EI and DI instructions or by a direct manipulation of SYM.0)
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing the part of your application program that handles the interrupt processing, be sure to include the necessary register file address (register pointer) information.
EI nRESET
IRQ0-IRQ7
Interrupts
S
R
Q
Interrupt Priority
Register
Interrupt Request Register
(Read-only)
Interrupt Mask
Register
Polling
Cycle
Global Interrupt Control
(EI, DI or SYM.0 manipulation)
Vector
Interrupt
Cycle
Figure 5-4. Interrupt Function Diagram
5-8
S3F80JB INTERRUPT STRUCTURE
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3).
Timer 2 overflow
Table 5-3. Vectored Interrupt Source Control and Data Registers
Interrupt Source
Timer 0 match/capture or
Timer 0 overflow
Timer 1 match/capture or
Timer 1 overflow
Counter A
Timer 2 match/capture or
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
Interrupt Level
IRQ0
IRQ1
IRQ2
Register(s)
T0CON (see Note)
T0DATA
T1CON (see Note)
T1DATAH, T1DATAL
CACON
CADATAH, CADATAL
IRQ3 T2CON (see Note)
T2DATAH, T2DATAL
IRQ7 P0CONH
P0INT
P0PND
IRQ6 P0CONL
P0INT
P0PND
IRQ5 P2CONH
P2INT
P2PND
IRQ4 P2CONL
P2INT
P2PND
Location(s) in Set 1
D2H
D1H
FAH
F8H, F9H
F3H
F4H, F5H
E8H
E6H, E7H
E8H
F1H
F2H
E9H
F1H
F2H
ECH
E5H
E6H
EDH
E5H
E6H
Bank
Bank0
Bank0
Bank0
Bank1
Bank0
Bank0
Bank0
Bank0
NOTES:
1. Because the timer 0,timer1 and timer 2 overflow interrupts are cleared by hardware, the T0CON, T1CON and
T2CON registers control only the enable/disable functions. The T0CON, T1CON and T2CON registers contain enable/disable and pending bits for the timer 0, timer1 and timer2 match/capture interrupts, respectively.
2. If a interrupt is un-mask(Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt should be written after a DI instruction is executed.
5-9
INTERRUPT STRUCTURE S3F80JB
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable and disable interrupt processing and to control fast interrupt processing (See Figure 5-5).
A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value, SYM.4–SYM.2, is for fast interrupt level selection and undetermined values after reset. SYM.6 and SYM5 are not used.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this purpose.
MSB .7
-
System Mode Register (SYM)
DEH, Set 1, Bank 0, R/W
.4
.3
.2
.1
.0
LSB
External Interface Tri-state Enable Bit:
0 = Normal operation
(Tri-state disabled) Not used
1 = High impedance
(Tri-state enabled)
Fast Interrupt Level
Selection Bits:
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Global Interrupt Enable
Bit:
0 = Disable all
1 = Enable all
Fast Interrupt Enable Bit:
0 = Disable fast
1 = Enable fast
NOTE: In case of S3F80JB, an external memory interface is not implemented.
Figure 5-5. System Mode Register (SYM)
5-10
S3F80JB INTERRUPT STRUCTURE
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (DDH, Set 1, Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1and Bank0. Bit values can be read and written by instructions using the register addressing mode.
MSB .7
.6
Interrupt Mask Register (IMR)
DDH, Set 1, Bank 0, R/W
.5
.4
.3
.2
.1
.0
LSB
IRQ7
IRQ6
IRQ5
IRQ4
IRQ1
IRQ0
IRQ3
IRQ2
Interrupt Level Enable Bits (7-0):
0 = Disable (mask) interrupt
1 = Enable (un-mask) interrupt
NOTE: Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.
Figure 5-6. Interrupt Mask Register (IMR)
5-11
INTERRUPT STRUCTURE S3F80JB
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set the relative priorities of the interrupt levels used in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
When more than one interrupt source is active, the source with the highest priority level is serviced first. If both sources belong to the same interrupt level, the source with the lowest vector address usually has priority (This priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5–7):
Group A IRQ0, IRQ1
Group B IRQ2, IRQ3, IRQ4
Group C IRQ5, IRQ6, IRQ7
IPR
Group A
IPR
Group B
IPR
Group C
A1
IRQ0
A2
IRQ1
B1
IRQ2
B21
IRQ3
B2
B22
IRQ4
C1
IRQ5
C21
IRQ6
C2
C22
IRQ7
Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting '001B' for these bits would select the group relationship B > C > A; the setting '101B' would select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
— IPR.5 controls the relative priorities of group C interrupts.
— Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2, 3, and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B.
— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
5-12
S3F80JB INTERRUPT STRUCTURE
MSB .7
Group Priority:
D7 D4 D1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
= Undefined
= B > C > A
= A > B > C
= B > A > C
= C > A > B
= C > B > A
= A > C > B
= Undefined
.6
Interrupt Priority Register (IPR)
FEH, Set 1, Bank 0 , R/W
.5
.4
.3
.2
.1
.0
LSB
Group A
0 = IRQ0 > IRQ1
1 = IRQ0 < IRQ1
Group B
0 = IRQ2 > (IRQ3,IRQ4)
1 = IRQ2 < (IRQ3,IRQ4)
Subgroup B (see note)
0 = IRQ3>IRQ4
1 = IRQ3<IRQ4
Group C
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
Subgroup C
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
Figure 5-8. Interrupt Priority Register (IPR)
5-13
INTERRUPT STRUCTURE S3F80JB
INTERRUPT REQUEST REGISTER (IRQ)
You can poll bit values in the interrupt request register, IRQ (DCH, Set 1, Bank0), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level; a "1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the
IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled.
MSB .7
.6
Interrupt Request Register (IRQ)
DCH, Set 1, Bank 0 , Read-only
.5
.4
.3
.2
.1
.0
LSB
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
Interrupt Level Request Enable Bits:
0 = Interrupt level is not pending
1 = Interrupt level is pending
Figure 5-9. Interrupt Request Register (IRQ)
5-14
S3F80JB INTERRUPT STRUCTURE
INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software.
In the S3F80JB interrupt structure, the timer 0 overflow interrupt (IRQ0), the timer 1 overflow interrupt (IRQ1), the timer 2 overflow interrupt (IRQ3), and the counter A interrupt (IRQ2) belong to this category of interrupts whose pending condition is cleared automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit must be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source’s mode or control register.
In the S3F80JB interrupt structure, pending conditions for all interrupt sources except the timer 0 overflow interrupt, the timer 1 overflow interrupt, the timer 2 overflow interrupt and the counter A borrow interrupt, must be cleared by the interrupt service routine.
5-15
INTERRUPT STRUCTURE S3F80JB
INTERRUPT SOURCE POLLING SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to "1".
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the interrupt level of source.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).
7. The CPU continues polling for interrupt requests.
INTERRUPT SERVICE ROUTINES
Before an interrupt request can be serviced, the following conditions must be met:
— Interrupt processing must be globally enabled (EI, SYM.0 = "1")
— The interrupt level must be enabled (IMR register - unmask)
— The interrupt level must have the highest priority if more than one level is currently requesting service
— The interrupt must be enabled at the interrupt's source (peripheral control register)
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The
CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request.
5-16
S3F80JB INTERRUPT STRUCTURE
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure.
Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE
A 16-bit vector address always begins at an even-numbered ROM address within the range 00H–FFH.
NESTING OF VECTORED INTERRUPTS
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs).
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the above procedure to some extent.
INSTRUCTION POINTER (IP)
The instruction pointer (IP) is used by all S3C8/S3F8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts. The IP consists of register pair IPH(DAH Set1 Bank0) and
IPL(DBH Set1 Bank0). The IP register names are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).
FAST INTERRUPT PROCESSING
The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 22 clock cycles. To select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt processing for the selected level, you set SYM.1 to “1”.
5-17
INTERRUPT STRUCTURE S3F80JB
FAST INTERRUPT PROCESSING (Continued)
Two other system registers support fast interrupt processing:
— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and
— When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”).
NOTE
For the S3F80JB microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing.
Procedure for Initiating Fast Interrupt
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)
3. Write a "1" to the fast interrupt enable bit in the SYM register.
Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back.
6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends.
5-18
S3F80JB INSTRUCTION SET
6
INSTRUCTION SET
OVERVIEW
The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include:
— A full complement of 8-bit arithmetic and logic operations, including multiply and divide
— No special I/O instructions (I/O control/data registers are mapped directly into the register file)
— Decimal adjustment included in binary-coded decimal (BCD) operations
— 16-bit (word) data can be incremented and decremented
— Flexible instructions for bit addressing, rotate, and shift operations
Data Types
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit.
Register Addressing
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."
Addressing Modes
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative
(RA), Immediate (IM) and Indirect (IA). For detailed descriptions of these addressing modes, please refer to
Section 3, "Addressing Modes."
6-1
INSTRUCTION SET
Table 6-1. Instruction Group Summary
Mnemonic Operands Instruction
Load Instructions
CLR dst Clear
LDB
LDE
LDC
LDED
LDCD
LDEI
LDCI
LDEPD
LDCPD dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src
Load bit
Load external data memory
Load program memory
Load external data memory and decrement
Load program memory and decrement
Load external data memory and increment
Load program memory and increment
Load external data memory with pre-decrement
Load program memory with pre-decrement
LDEPI
LDCPI
LDW
POP
POPUD dst, src dst, src dst, src dst dst, src
Load external data memory with pre-increment
Load program memory with pre-increment
Load word
Pop from stack
Pop user stack (decrementing)
POPUI dst, src Pop user stack (incrementing)
PUSH Src stack
PUSHUD
PUSHUI dst, src dst, src
Push user stack (decrementing)
Push user stack (incrementing)
S3F80JB
6-2
S3F80JB INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Mnemonic Operands Instruction
Arithmetic Instructions
ADC dst,src Add with carry
DEC dst Decrement
DECW dst Decrement
INC dst Increment
INCW dst Increment
MULT dst,src Multiply
SBC dst,src Subtract with carry
Logic Instructions
COM dst Complement
XOR dst,src Logical exclusive OR
6-3
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Mnemonic Operands Instruction
Program Control Instructions
BTJRF
BTJRT
CALL dst Call
CPIJE dst,src Compare, increment and jump on equal
CPIJNE
DJNZ
ENTER dst,src dst,src dst,src r,dst
Bit test and jump relative on false
Bit test and jump relative on true
Compare, increment and jump on non-equal
Decrement register and jump on non-zero
Enter
EXIT
IRET
JP cc,dst
Exit
Interrupt return
Jump on condition code
JR
NEXT cc,dst
RET
WFI
Bit Manipulation Instructions
Jump relative on condition code
Next
Return
Wait for interrupt
S3F80JB
BITC dst Bit
BITR dst Bit
TCM dst,src Test complement under mask
6-4
S3F80JB INSTRUCTION SET
Table 6-1. Instruction Group Summary (Concluded)
Mnemonic Operands Instruction
Rotate and Shift Instructions
RLC dst Rotate left through carry
CCF
DI
EI
IDLE
NOP
RCF
SB0
SB1
SCF
SRP
SRP0
SRP1
STOP
RRC dst Rotate right through carry
SRA dst Shift right arithmetic
SWAP dst Swap
CPU Control Instructions src src src
Complement carry flag
Disable interrupts
Enable interrupts
Enter Idle mode
No operation
Reset carry flag
Set bank 0
Set bank 1
Set carry flag
Set register pointers
Set register pointer 0
Set register pointer 1
Enter Stop mode
6-5
INSTRUCTION SET S3F80JB
FLAGS REGISTER (FLAGS)
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and
FLAGS.2 are used for BCD arithmetic.
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.
MSB
Carry flag (C)
Zero flag (Z)
.7
.6
System Flags Register (FLAGS)
D5H, Set 1, Bank0 , R/W
.5
.4
.3
.2
.1
Sign flag (S)
.0
LSB
Bank address status flag (BA)
First interrupt status flag (FIS)
Half-carry flag (H)
Overflow (V) Decimal adjust flag (D)
Figure 6-1. System Flags Register (FLAGS)
6-6
S3F80JB INSTRUCTION SET
FLAG DESCRIPTIONS
C
Carry Flag (FLAGS.7)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.
Z
Zero Flag (FLAGS.6)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.
S
Sign Flag (FLAGS.5)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number.
V
Overflow Flag (FLAGS.4)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than
– 128. It is also cleared to "0" following logic operations.
D
Decimal Adjust Flag (FLAGS.3)
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition.
H
Half-Carry Flag (FLAGS.2)
The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program.
FIS
Fast Interrupt Status Flag (FLAGS.1)
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed.
BA
Bank Address Flag (FLAGS.0)
The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.
6-7
INSTRUCTION SET
INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag Description
S3F80JB
0
1
*
Cleared to logic zero
Set to logic one
Set or cleared according to operation
Table 6-3. Instruction Set Symbols
Symbol Description
@ Indirect register address prefix
FLAGS Flags register (D5H)
#
H
D
Immediate operand or register address prefix
Hexadecimal number suffix
Decimal number suffix
B Binary suffix opc Opcode
6-8
S3F80JB INSTRUCTION SET
Table 6-4. Instruction Notation Conventions
Notation Description cc Condition code
Actual Operand Range
See list of condition codes in Table 6-6. r rb r0
Working register only
Bit (b) of working register
Bit 0 (LSB) of working register
Rn (n = 0–15)
Rn.b (n = 0–15, b = 0–7)
Rn (n = 0–15) rr
R
Rb
RR
IA
Ir
IR
Irr
IRR
Working register pair
Register or working register
RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0–255, n = 0–15)
Bit 'b' of register or working register
Register pair or working register pair reg.b (reg = 0–255, b = 0–7) reg or RRp (reg = 0–254, even number only, where p = 0, 2, ..., 14) addr (addr = 0–254, even number only) Indirect addressing mode
Indirect working register only @Rn (n = 0–15)
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)
Indirect working register pair only @RRp (p = 0, 2, ..., 14)
X
XS xl da ra im iml
Indirect register pair or indirect working register pair
Indexed addressing mode
Indexed (short offset) addressing mode
Indexed (long offset) addressing mode
Direct addressing mode
Relative addressing mode
Immediate addressing mode
Immediate (long) addressing mode
@RRp or @reg (reg = 0–254, even only, where p = 0, 2, ..., 14)
#reg [Rn] (reg = 0–255, n = 0–15)
#addr [RRp] (addr = range –128 to +127, where p = 0, 2, ..., 14)
#addr [RRp] (addr = range 0–65535, where p = 0, 2, ..., 14) addr (addr = range 0–65535) addr (addr = number in the range +127 to –128 that is an offset relative to the address of the next instruction)
#data (data = 0–255)
#data (data = range 0–65535)
6-9
INSTRUCTION SET S3F80JB
B
L
E
N
I
B
P
E
R
U
P
E
X
H
Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
– 0 1 2 3 4 5 6 7
0
1
2
DEC
R1
RLC
R1
INC
R1
DEC
IR1
RLC
IR1
INC
IR1
ADD r1,r2
ADC r1,r2
SUB r1,r2
ADD r1,Ir2
ADC r1,Ir2
SUB r1,Ir2
ADD
R2,R1
ADC
R2,R1
SUB
R2,R1
ADD
IR2,R1
ADC
IR2,R1
SUB
IR2,R1
ADD
R1,IM
ADC
R1,IM
SUB
R1,IM
BOR r0–Rb
BCP r1.b, R2
BXOR r0–Rb
3
4
5
6
7
8
JP
IRR1
DA
R1
POP
R1
COM
R1
PUSH
R2
DECW
RR1
SRP/0/1
IM
DA
IR1
POP
IR1
COM
IR1
PUSH
IR2
DECW
IR1
SBC r1,r2
OR r1,r2
AND r1,r2
TCM r1,r2
TM r1,r2
PUSHUD
IR1,R2
SBC r1,Ir2
OR r1,Ir2
AND r1,Ir2
TCM r1,Ir2
TM r1,Ir2
PUSHUI
IR1,R2
SBC
R2,R1
OR
R2,R1
AND
R2,R1
TCM
R2,R1
TM
R2,R1
MULT
R2,RR1
SBC
IR2,R1
OR
IR2,R1
AND
IR2,R1
TCM
IR2,R1
TM
IR2,R1
MULT
IR2,RR1
SBC
R1,IM
OR
R1,IM
AND
R1,IM
TCM
R1,IM
TM
R1,IM
MULT
IM,RR1
BTJR r2.b, RA
LDB r0–Rb
BITC r1.b
BAND r0–Rb
BIT r1.b
LD r1, x, r2
9
A
B
C
D
E
F
RL
R1
INCW
RR1
CLR
R1
RRC
R1
SRA
R1
RR
R1
SWAP
R1
RL
IR1
INCW
IR1
CLR
IR1
RRC
IR1
SRA
IR1
RR
IR1
SWAP
IR1
POPUD
IR2,R1
CP r1,r2
XOR r1,r2
CPIJE
Ir,r2,RA
CPIJNE
Irr,r2,RA
LDCD r1,Irr2
LDCPD r2,Irr1
POPUI
IR2,R1
CP r1,Ir2
XOR r1,Ir2
LDC r1,Irr2
LDC r2,Irr1
LDCI r1,Irr2
LDCPI r2,Irr1
DIV
R2,RR1
CP
R2,R1
XOR
R2,R1
LDW
RR2,RR1
CALL
IA1
LD
R2,R1
CALL
IRR1
DIV
IR2,RR1
CP
IR2,R1
XOR
IR2,R1
LDW
IR2,RR1
LD
R2,IR1
LD
IR2,R1
DIV
IM,RR1
CP
R1,IM
XOR
R1,IM
LDW
RR1,IML
IR1,IM
LD
R1,IM
CALL
DA1
LD r2, x, r1
LDC r1, Irr2, xL
LDC r2, Irr2, xL
LD r1, Ir2
Ir1, r2
LDC r1, Irr2, xs
LDC r2, Irr1, xs
6-10
S3F80JB INSTRUCTION SET
H
L
E
E
X
N
E
R
I
B
B
U
P
P
Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
– 8 9 A B C D E F
NEXT 0 LD LD r1,R2 r2,R1
1
↓ ↓
DJNZ r1,RA
↓
JR cc,RA
↓
LD r1,IM
↓
JP cc,DA
↓
INC r1
↓
2
ENTER
EXIT
3
4
5
6
7
8
9
A
B
C
D
↓
↓
↓
↓
E
F LD LD r1,R2 r2,R1
↓
↓
DJNZ r1,RA
↓
↓
JR cc,RA
↓
↓
LD r1,IM
↓
↓
JP cc,DA
↓
↓
INC r1
IDLE
STOP
DI
EI
WFI
SB0
SB1
RET
IRET
RCF
SCF
CCF
NOP
6-11
INSTRUCTION SET S3F80JB
CONDITION CODES
The op-code of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions.
Binary Mnemonic
0000 F Always
1000 T Always
0111 (note)
1111
(note)
C
NC
Carry
No carry
0110 (note)
1110 (note)
Z Zero
NZ Not zero
1101 PL Plus
0101 MI Minus
0100 OV Overflow
1100 NOV No overflow
0110 (note)
1110 (note)
EQ Equal
NE Not equal
1001
0001
GE
LT
Greater than or equal
Less than
1010
0010
1111 (note)
0111 (note)
1011
0011
GT
LE
UGE
ULT
UGT
ULE
Table 6-6. Condition Codes
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
–
–
C = 1
C = 0
Z = 0
V = 0
Z = 0
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
C = 1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
NOTES:
1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6-12
S3F80JB INSTRUCTION SET
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description:
— Instruction name (mnemonic)
— Source/destination format of the instruction operand
— Shorthand notation of the instruction's operation
— Textual description of the instruction's effect
— Specific flag settings affected by the instruction
— Detailed description of the instruction's format, execution time, and addressing mode(s)
— Programming example(s) explaining how to use the instruction
6-13
INSTRUCTION SET S3F80JB
ADC
— Add with carry
ADC dst,src
Operation: dst
← dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise.
Format: opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH:
ADC R1,R2
ADC R1,@R2
→
→
ADC 01H,02H
→
ADC 01H,@02H
→
ADC 01H,#11H
→
R1 = 14H, R2 = 03H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds
03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6-14
S3F80JB INSTRUCTION SET
ADD
— Add
ADD dst,src
Operation: dst
← dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD R1,R2
→
ADD R1,@R2
→
ADD 01H,02H
→
ADD 01H,@02H
→
ADD 01H,#25H
→
R1 = 15H, R2 = 03H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register
R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.
6-15
INSTRUCTION SET S3F80JB
AND
— Logical AND
AND dst,src
Operation: dst
← dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND R1,R2
→
AND R1,@R2
→
AND 01H,02H
→
AND 01H,@02H
→
AND 01H,#25H
→
R1 = 02H, R2 = 03H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
6-16
S3F80JB INSTRUCTION SET
BAND
— Bit AND
BAND dst,src.b
BAND dst.b,src
Format: or
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected. opc opc dst | b | 0 src | b | 1 src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src dst
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples: Given: R1 = 07H and register 01H = 05H:
BAND R1,01H.1
BAND 01H.1,R1
→
→
R1 = 06H, register 01H = 05H
Register 01H = 05H, R1 = 07H
In the first example, source register 01H contains the value 05H (00000101B) and destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value
06H (00000110B) in register R1.
6-17
INSTRUCTION SET S3F80JB
BCP
— Bit Compare
BCP dst,src.b
Operation: dst(0) – src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.
Format:
Z: Set if the two bits are the same; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Bytes Cycles Opcode
(Hex)
Addr Mode dst src opc dst | b | 0 src
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Example: Given: R1 = 07H and register 01H = 01H:
BCP R1,01H.1
→
R1 = 07H, register 01H = 01H
If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
6-18
INSTRUCTION SET S3F80JB
BITC
— Bit Complement
BITC dst.b
Format:
This instruction complements the specified bit within the destination without affecting any other bits in the destination.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 57 rb opc dst | b | 0
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Example: Given: R1 = 07H
BITC R1.1
→
R1 = 05H
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared.
6-19
INSTRUCTION SET S3F80JB
BITR
— Bit Reset
BITR dst.b
The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination.
No flags are affected. Flags:
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 77 rb opc dst | b | 0
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Example: Given: R1 = 07H:
BITR R1.1
→
R1 = 05H
If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B).
6-20
S3F80JB INSTRUCTION SET
BITS
— Bit Set
BITS dst.b
Flags:
Format:
The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination.
No flags are affected.
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 77 rb opc dst | b | 1
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Example: Given: R1 = 07H:
BITS R1.3
→
R1 = 0FH
If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B).
6-21
INSTRUCTION SET S3F80JB
BOR
— Bit OR
BOR
BOR dst,src.b dst.b,src
Format: or
The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.
Z: Set if the result is "0"; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Bytes Cycles Opcode
(Hex)
Addr Mode dst src opc opc dst | b | 0 src | b | 1 src dst
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit.
Examples: Given: R1 = 07H and register 01H = 03H:
BOR R1,
→
BOR 01H.2,
→
R1 = 07H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 contains the value 07H (00000111B) and source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value
(07H) in working register R1.
In the second example, destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H.
6-22
S3F80JB INSTRUCTION SET
BTJRF
— Bit Test, Jump Relative on False
BTJRF
Operation: dst,src.b
If src(b) is a "0", then PC
← PC + dst
The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed.
No flags are affected. Flags:
Format: opc
(Note 1) src | b | 0
Bytes Cycles Opcode
(Hex)
Addr Mode dst src dst
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Example: Given: R1 = 07H:
BTJRF SKIP,R1.3
→
PC jumps to SKIP location
If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-23
INSTRUCTION SET S3F80JB
BTJRT
— Bit Test, Jump Relative on True
BTJRT dst,src.b
Operation: If src(b) is a "1", then PC
← PC + dst
The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed.
No flags are affected. Flags:
Format: opc
(Note 1) src | b | 1 dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Example: Given: R1 = 07H:
BTJRT SKIP,R1.1
If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-24
S3F80JB INSTRUCTION SET
BXOR
— Bit XOR
BXOR
BXOR dst,src.b dst.b,src
Format: or
The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Bytes Cycles Opcode
(Hex)
Addr Mode dst src opc opc dst | b | 0 src | b | 1 src dst
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples: Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):
BXOR R1,01H.1
BXOR 01H.2,R1
→
→
R1 = 06H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 has the value 07H (00000111B) and source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected.
6-25
INSTRUCTION SET S3F80JB
CALL
— Call Procedure
CALL dst
Operation: SP
←
SP – 1
← PCL
← SP
@SP
← dst
The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter.
Flags: No flags are affected.
Format: opc dst opc dst opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
3 14 F6 DA
2 12 F4 IRR
2 14 D4 IA
Examples: Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:
CALL #40H
→
SP = 0000H
(Memory locations 0000H = 1AH, 0001H = 4AH, where
4AH is the address that follows the instruction.)
SP = 0000H (0000H = 1AH, 0001H = 49H)
SP = 0000H (0000H = 1AH, 0001H = 49H)
In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H contains 35H and program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example.
6-26
S3F80JB INSTRUCTION SET
CCF
— Complement Carry Flag
CCF
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
No other flags are affected.
Format:
Example: opc
Bytes Cycles Opcode
(Hex)
1 4 EF
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.
6-27
INSTRUCTION SET S3F80JB
CLR
— Clear
CLR dst
Flags:
Format:
The destination location is cleared to "0".
No flags are affected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 B0
4 B1
R
IR
Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR 00H
→
Register 00H = 00H
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.
6-28
S3F80JB INSTRUCTION SET
COM
— Complement
COM dst
The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 60 R
4 61 IR
Given: R1 = 07H and register 07H = 0F1H:
COM R1
→
COM @R1
→
R1 = 0F8H
R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6-29
INSTRUCTION SET S3F80JB
CP
— Compare
CP dst,src
Operation: dst – src
The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: 1. Given: R1 = 02H and R2 = 03H:
CP R1,R2
→
Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are
"1".
2. Given: R1 = 05H and R2 = 0AH:
CP R1,R2
SKIP
In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.
6-30
S3F80JB INSTRUCTION SET
CPIJE
— Compare, Increment, and Jump on Equal
CPIJE dst,src,RA
Operation: If dst – src = "0", PC
← PC + RA
The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed.
No flags are affected. Flags:
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example: Given: R1 = 02H, R2 = 03H, and register 03H = 02H:
CPIJE R1,@R2,SKIP
→
R2 = 04H, PC jumps to SKIP location
In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-31
INSTRUCTION SET S3F80JB
CPIJNE
— Compare, Increment, and Jump on Non-Equal
CPIJNE dst,src,RA
Operation: If dst – src "0", PC
← PC + RA
The source operand is compared to (subtracted from) the destination operand. If the result is not
"0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction.
No flags are affected. Flags:
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example: Given: R1 = 02H, R2 = 03H, and register 03H = 04H:
CPIJNE R1,@R2,SKIP
→
R2 = 04H, PC jumps to SKIP location
Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-32
S3F80JB
DA
— Decimal Adjust
DA dst
INSTRUCTION SET
Format:
The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits):
Instruction Carry
Before DA
Bits 4–7
Value (Hex)
H Flag
Before DA
Bits 0–3
Value (Hex)
Number Added to Byte
Carry
After DA
0 0–9 0 0–9 00 0
0 0–8 0 A–F 06 0
0 0–9 1 0–3 06 0
ADD 0 A–F 0 0–9 60 1
ADC 0 9–F 0 A–F 66 1
0 A–F 1 0–3 66 1
1 0–2 0 0–9 60 1
1 0–2 0 A–F 66 1
1 0–3 1 0–3 66 1
0 0–9 0 0–9 00 = – 00 0
SUB
SBC
0
1
1
0–8
7–F
6–F
1
0
1
6–F
0–9
6–F
FA = – 06
A0 = – 60
9A = – 66
0
1
1
Z: Set if result is "0"; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 40 R
4 41 IR
6-33
INSTRUCTION SET S3F80JB
DA
— Decimal Adjust
DA (Continued)
Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains
27 (BCD), and address 27H contains 46 (BCD):
DA R1 ; R1
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic:
0 0 0 1 0 1 0 1 15
+ 0 0 1 0 0 1 1 1 27
0 0 1 1 1 1 0 0 = 3CH
The DA instruction adjusts this result so that the correct BCD representation is obtained:
0 0 1 1 1 1 0 0
+ 0 0 0 0 0 1 1 0
0 1 0 0 0 0 1 0 = 42
Assuming the same values given above, the statements
SUB 27H,R0
← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = 1
DA @R1
← 31–0 leave the value 31 (BCD) in address 27H (@R1).
6-34
S3F80JB INSTRUCTION SET
DEC
— Decrement
DEC dst
The contents of the destination operand are decremented by one.
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
2 4 00
Addr Mode dst
4 01
R
IR
Given: R1 = 03H and register 03H = 10H:
DEC R1
→
DEC @R1
→
R1 = 02H
Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.
6-35
INSTRUCTION SET S3F80JB
DECW
— Decrement Word
DECW dst
The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 8 80 RR
8 81 IR
Examples: Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW RR0
→
DECW @R2
→
R0 = 12H, R1 = 33H
Register 30H = 0FH, register 31H = 20H
NOTE:
In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H.
A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example:
LOOP: DECW RR0
LD R2,R1
OR R2,R0
JR NZ,LOOP
6-36
S3F80JB INSTRUCTION SET
DI
— Disable Interrupts
DI
Operation: SYM
← 0
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
No flags are affected. Flags:
Format: opc
Bytes Cycles Opcode
(Hex)
1 4 8F
Example: Given: SYM = 01H:
DI
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.
6-37
INSTRUCTION SET S3F80JB
DIV
— Divide (Unsigned)
DIV dst,src
Operation: dst ÷ src dst (UPPER)
← REMAINDER dst (LOWER)
← QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is
≥ 2 8
, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers.
Set if the V flag is set and quotient is between 2 8 and 2 9 –1; cleared otherwise.
Z: Set if divisor or quotient = "0"; cleared otherwise.
S: Set if MSB of quotient = "1"; cleared otherwise.
V: Set if quotient is
≥ 2 8 or if divisor = "0"; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format: opc src dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
26/10
26/10
95
96
RR
RR
IR
IM
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.
Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:
DIV RR0,R2
→
DIV RR0,@R2
→
DIV RR0,#20H
→
R0 = 03H, R1 = 40H
R0 = 03H, R1 = 20H
R0 = 03H, R1 = 80H
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1).
6-38
S3F80JB INSTRUCTION SET
DJNZ
— Decrement and Jump if Non-Zero
DJNZ r,dst
If r
≠ 0, PC ← PC + dst
The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to –128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement.
Flags:
Format:
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.
No flags are affected. r | opc dst
Bytes Cycles Opcode
(Hex) dst
2 8 (jump taken)
8 (no jump) rA r = 0 to F
RA
Example: Given: R1 = 02H and LOOP is the label of a relative address:
SRP #0C0H
DJNZ R1,LOOP
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.
The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label.
6-39
INSTRUCTION SET S3F80JB
EI
— Enable Interrupts
EI
Operation: SYM
← 1
An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
No flags are affected. Flags:
Format: opc
Bytes Cycles Opcode
(Hex)
1 4 9F
Example: Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.)
6-40
S3F80JB
ENTER
— Enter
ENTER
Operation: SP 2
INSTRUCTION SET
Flags:
Format:
Example:
This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two.
No flags are affected. opc
Bytes Cycles Opcode
(Hex)
1 14 1F
The diagram below shows one example of how to use an ENTER statement.
Address
IP 0050
Data
PC
SP
0040
0022
Before
Address
40
41
42
43
Enter
Address H
Address L
Address H
Data
1F
01
10
22 Data
Stack
Memory
Address
IP 0043
Data
After
PC
SP
0110
0020
Address
40
41
42
43
Enter
Address H
Address L
Address H
Data
1F
01
10
20
21
22
IPH
IPL
Data
Stack
00
50
110 Routine
Memory
6-41
INSTRUCTION SET
EXIT
— Exit
EXIT
Operation: IP
← @SP
S3F80JB
Flags:
Format:
Example:
This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.
No flags are affected. opc
Bytes Cycles Opcode
(internal 2F
16 (internal stack)
The diagram below shows one example of how to use an EXIT statement.
Before
Address
IP 0050
Data
Address
PC 0040
Data
50
51
PCL old
PCH
60
00
SP 0022
140 Exit 2F
20
21
22
IPH
IPL
Data
Stack
00
50
Memory
Address
IP 0052
Data
After
Address
PC 0060
60 Main
SP 0022
22 Data
Stack
Memory
Data
6-42
S3F80JB INSTRUCTION SET
IDLE
— Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
No flags are affected. Flags:
Format: opc
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Example: The instruction
IDLE stops the CPU clock but not the system clock.
6-43
INSTRUCTION SET S3F80JB
INC
— Increment
INC dst
The contents of the destination operand are incremented by one.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected. dst | opc opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
1 4 rE r r = 0 to F
2 4 20 R
4 21 IR
Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC R0
→
INC 00H
→
R0 = 1CH
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC
R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.
6-44
S3F80JB INSTRUCTION SET
INCW
— Increment Word
INCW dst
The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.
Format:
Examples:
NOTE:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 8 A0 RR
8 A1 IR
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:
INCW RR0
→
INCW @R1
→
R0 = 1AH, R1 = 03H
Register 02H = 10H, register 03H = 00H
In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.
A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example:
LOOP: INCW RR0
OR R2,R0
JR NZ,LOOP
6-45
INSTRUCTION SET
IRET
— Interrupt Return
IRET IRET (Normal) IRET (Fast)
PC
↔ IP
FLAGS
← FLAGS'
FIS
← 0
S3F80JB
Flags:
Format:
Example:
NOTE:
This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
IRET
(Normal) opc
IRET
(Fast) opc
Bytes Cycles Opcode
1 10 (internal stack) BF
12 (internal stack)
Bytes Cycles Opcode
1 6 BF
In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address.
The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H.
0H
FFH
100H
IRET
Interrupt
Service
Routine
JP to FFH
FFFFH
In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the IPR register).
6-46
S3F80JB INSTRUCTION SET
JP
— Jump
JP cc,dst (Conditional)
JP dst (Unconditional)
Operation: If cc is true, PC
← dst
The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the
PC.
No flags are affected. Flags:
Format: (1)
Bytes Cycles Opcode Addr Mode
(Hex) dst (2) cc | opc opc dst cc = 0 to F
2 8 30 IRR
NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.
Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
JP
C,LABEL_W
→ LABEL_W = 1000H, PC = 1000H
@00H
→ PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-47
INSTRUCTION SET S3F80JB
JR
— Jump Relative
JR cc,dst
Operation: If cc is true, PC
← PC + dst
If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes).
The range of the relative address is +127, –128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement.
No flags are affected. Flags:
Format:
(1) cc | opc
Bytes Cycles Opcode
(Hex)
Addr Mode dst dst 2 6 ccB RA cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each
Example: Given: The carry flag = "1" and LABEL_X = 1FF7H:
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.
6-48
S3F80JB INSTRUCTION SET
LD
— Load
LD dst,src
The contents of the source are loaded into the destination. The source's contents are unaffected.
No flags are affected. Flags:
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode dst src dst | opc src | opc opc src dst dst | src opc src dst opc dst src r = 0 to F opc src dst opc opc dst | src src | dst x x 3 6 97 r
6-49
INSTRUCTION SET S3F80JB
LD
— Load
LD (Continued)
Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
LD R0,#10H
→
LD R0,01H
→
LD 01H,R0
→
LD R1,@R0
→
LD @R0,R1
→
LD 00H,01H
→
LD 02H,@00H
→
LD 00H,#0AH
→
LD @00H,02H
→
LD R0,#LOOP[R1]
R0 = 10H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
R0 = 01H, R1 = 0AH, register 01H = 0AH
Register 00H = 20H, register 01H = 20H
Register 02H = 20H, register 00H = 01H
Register 00H = 0AH
Register 00H = 01H, register 01H = 10H
Register 00H = 01H, register 01H = 02, register 02H = 02H
R0 = 0FFH, R1 = 0AH
Register 31H = 0AH, R0 = 01H, R1 = 0AH
6-50
S3F80JB INSTRUCTION SET
LDB
— Load Bit
LDB dst,src.b
LDB dst.b,src or
The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.
No flags are affected. Flags:
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode dst src opc opc dst | b | 0 src | b | 1 src dst
NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples: Given: R0 = 06H and general register 00H = 05H:
R0 = 07H, register 00H = 05H
R0 = 06H, register 00H = 04H
In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.
In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general register 00H.
6-51
INSTRUCTION SET S3F80JB
LDC/LDE
— Load Memory
LDC/LDE dst,src
This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.
No flags are affected. Flags:
Format:
1. opc
6. opc dst | src
2. opc src | dst
3. opc dst | src
4. opc src | dst
5. opc dst | src src | dst
7. opc dst | 0000 DA
L
8. opc src | 0000 DA
L
9. opc dst | 0001 DA
L
10. opc src | 0001 DA
L
XS
XS
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
XL
L
XL
L
XL
XL
H
H
DA
H
DA
DA
DA
H
H
H
NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one
byte.
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two
bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
6-52
S3F80JB INSTRUCTION SET
LDC/LDE
— Load Memory
LDC/LDE (Continued)
Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:
LDC R0,@RR2 ;
← contents of program memory location 0104H
; R0 = 1AH, R2 = 01H, R3 = 04H
LDE R0,@RR2 ;
← contents of external data memory location 0104H
; R0 = 2AH, R2 = 01H, R3 = 04H
LDC (note) @RR2,R0 ; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3
→ no change
LDE @RR2,R0 ; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3
→ no change
;
← contents of program memory location 0105H
; R0 = 6DH, R2 = 01H, R3 = 04H
;
← contents of external data memory location 0105H
; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H
LDC (note) #01H[RR2],R0 ; 11H (contents of R0) is loaded into program memory location
; 0105H (01H + 0104H)
LDE #01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory
; location 0105H (01H + 0104H)
;
← contents of program memory location 1104H
; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
;
← contents of external data memory location 1104H
; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC R0,1104H ;
← contents of program memory location 1104H, R0 = 88H
LDE R0,1104H ;
← contents of external data memory location 1104H,
; R0 = 98H
LDC (note) 1105H,R0 ; 11H (contents of R0) is loaded into program memory location
; 1105H, (1105H)
← 11H
LDE 1105H,R0 ; 11H (contents of R0) is loaded into external data memory
; location 1105H, (1105H)
← 11H
NOTE: These instructions are not supported by masked ROM type devices.
6-53
INSTRUCTION SET
LDCD/LDED
— Load Memory and Decrement
LDCD/LDED dst,src
S3F80JB
These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory.
No flags are affected. Flags:
Format: opc dst | src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH:
LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is decremented by one
; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6
← RR6 – 1)
LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is decremented by one (RR6
← RR6 – 1)
; R8 = 0DDH, R6 = 10H, R7 = 32H
6-54
S3F80JB
LDCI/LDEI
— Load Memory and Increment
LDCI/LDEI dst,src
INSTRUCTION SET
Flags:
Format:
Examples:
These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes
'Irr' even for program memory and odd for data memory.
No flags are affected. opc dst | src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6
← RR6 + 1)
; R8 = 0CDH, R6 = 10H, R7 = 34H
LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6
← RR6 + 1)
; R8 = 0DDH, R6 = 10H, R7 = 34H
6-55
INSTRUCTION SET
LDCPD/LDEPD
— Load Memory with Pre-Decrement
LDCPD/
LDEPD dst,src
S3F80JB
These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location.
The contents of the source are unaffected.
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory.
No flags are affected. Flags:
Format: opc src | dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H:
LDCPD @RR6,R0
; 77H (contents of R0) is loaded into program memory location
; 2FFFH (3000H – 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH
LDEPD @RR6,R0
; 77H (contents of R0) is loaded into external data memory
; location 2FFFH (3000H – 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH
6-56
S3F80JB
LDCPI/LDEPI
— Load Memory with Pre-Increment
LDCPI/
LDEPI dst,src
INSTRUCTION SET
These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory.
No flags are affected. Flags:
Format: opc src | dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:
LDCPI @RR6,R0
; 7FH (contents of R0) is loaded into program memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H
LDEPI @RR6,R0
; 7FH (contents of R0) is loaded into external data memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H
6-57
INSTRUCTION SET S3F80JB
LDW
— Load Word
LDW dst,src
The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected.
No flags are affected. Flags:
Format: opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH:
LDW RR6,RR4
→
LDW 00H,02H
→
R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH
Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH
LDW RR2,@R7
→
LDW 04H,@01H
→
LDW RR6,#1234H
→
LDW 02H,#0FEDH
→
R2 = 03H, R3 = 0FH,
Register 04H = 03H, register 05H = 0FH
R6 = 12H, R7 = 34H
Register 02H = 0FH, register 03H = 0EDH
In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H.
The other examples show how to use the LDW instruction with various addressing modes and formats.
6-58
S3F80JB INSTRUCTION SET
MULT
— Multiply (Unsigned)
MULT dst,src
The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers.
Flags: C:
> 255; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if MSB of the result is a "1"; cleared otherwise.
V: Cleared.
D: Unaffected.
H: Unaffected.
Format: opc src dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:
MULT 00H,
→
Register 00H = 01H, register 01H = 20H, register 02H = 09H
@01H Register 00H = 00H, register 01H = 0C0H
MULT 00H,
→
Register 00H = 06H, register 01H = 00H
In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.
6-59
INSTRUCTION SET
NEXT
— Next
NEXT
S3F80JB
Flags:
Format:
Example:
The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.
No flags are affected. opc
Bytes Cycles Opcode
(Hex)
1 10 0F
The following diagram shows one example of how to use the NEXT instruction.
Address
IP 0043
Data
PC 0120
Before
Address
43
44
45
Address H
Address L
Address H
01
10
Address
IP 0045
Data
After
PC 0130
Address
43
44
45
Address H
Address L
Address H
Data
120 Next
Memory
130 Routine
Memory
6-60
S3F80JB INSTRUCTION SET
NOP
— No Operation
NOP
Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.
Flags: No flags are affected.
Format: opc
Bytes Cycles Opcode
(Hex)
1 4 FF
Example: When the instruction
NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
6-61
INSTRUCTION SET S3F80JB
OR
— Logical OR
OR dst,src
The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode Addr Mode
(Hex) dst src
Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH:
OR R0,R1
→
R0 = 3FH, R1 = 2AH
R0 = 37H, R2 = 01H, register 01H = 37H
Register 00H = 3FH, register 01H = 37H
Register 00H = 08H, register 01H = 0BFH
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result
(3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing modes and formats.
6-62
S3F80JB
POP
— Pop From Stack
POP dst
INSTRUCTION SET
Flags:
Format:
Examples:
The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
No flags affected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode
2 8 50
8 51 dst
R
IR
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H:
POP 00H
→
POP @00H
→
Register 00H = 55H, SP = 00FCH
Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location
00FCH.
6-63
INSTRUCTION SET
POPUD
— Pop User Stack (Decrementing)
POPUD dst,src
S3F80JB
Flags:
Format:
Example:
This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.
No flags are affected. opc src dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H:
Register 00H = 41H, register 02H = 6FH, register 42H = 6FH
If general register 00H contains the value 42H and register 42H the value 6FH, the statement
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H.
6-64
S3F80JB
POPUI
— Pop User Stack (Incrementing)
POPUI dst,src
INSTRUCTION SET
Flags:
Format:
Example:
The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
No flags are affected. opc src dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: Register 00H = 01H and register 01H = 70H:
Register 00H = 02H, register 01H = 70H, register 02H = 70H
If general register 00H contains the value 01H and register 01H the value 70H, the statement
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.
6-65
INSTRUCTION SET
PUSH
— Push To Stack
PUSH src
S3F80JB
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
No flags are affected. Flags:
Format: opc src
Bytes Cycles Opcode
(Hex) dst
2 8 (internal clock) 70 R
8 (external clock)
8 (internal clock)
8 (external clock) 71 IR
Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:
PUSH 40H
→
PUSH @40H
→
Register 40H = 4FH, stack register 0FFH = 4FH,
SPH = 0FFH, SPL = 0FFH
Register 40H = 4FH, register 4FH = 0AAH, stack register
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
In the first example, if the stack pointer contains the value 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack.
6-66
S3F80JB
PUSHUD
— Push User Stack (Decrementing)
PUSHUD dst,src
INSTRUCTION SET
Flags:
Format:
Example:
This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.
No flags are affected. opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:
PUSHUD @00H,01H
→
Register 00H = 02H, register 01H = 05H, register 02H = 05H
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer.
6-67
INSTRUCTION SET
PUSHUI
— Push User Stack (Incrementing)
PUSHUI dst,src
S3F80JB
Flags:
Format:
Example:
This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.
No flags are affected. opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:
PUSHUI @00H,01H
→
Register 00H = 04H, register 01H = 05H, register 04H = 05H
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer.
6-68
S3F80JB
RCF
— Reset Carry Flag
RCF RCF
The carry flag is cleared to logic zero, regardless of its previous value.
INSTRUCTION SET
Format:
Example:
No other flags are affected. opc
Bytes Cycles Opcode
(Hex)
1 4 CF
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
6-69
INSTRUCTION SET
RET
— Return
RET
S3F80JB
Flags:
Format:
Example:
The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value.
No flags are affected. opc
Bytes Cycles Opcode
1 8 (internal stack)
10 (internal stack)
AF
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:
RET
→
PC = 101AH, SP = 00FEH
The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH.
6-70
S3F80JB
RL
— Rotate Left
RL dst
INSTRUCTION SET dst (n + 1)
← dst (n), n = 0–6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
7 0
C
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 90
4 91
R
IR
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL 00H
→
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.
6-71
INSTRUCTION SET
RLC
— Rotate Left Through Carry
RLC dst
S3F80JB dst (n + 1)
← dst (n), n = 0–6
The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7 0
C
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 10 R
4 11 IR
Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC 00H
→
RLC @01H
→
Register 00H = 54H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement
"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-72
S3F80JB
RR
— Rotate Right
RR dst
INSTRUCTION SET
The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7 0
C
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 E0 R
4 E1 IR
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR 00H
→
RR @01H
→
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
6-73
INSTRUCTION SET
RRC
— Rotate Right Through Carry
RRC dst
Operation: dst
← C
S3F80JB
The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7
(MSB).
7 0
C
Format:
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 C0 R
4 C1 IR
Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC 00H
→
RRC @01H
→
Register 00H = 2AH, C = "1"
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
6-74
S3F80JB INSTRUCTION SET
SB0
— Select Bank 0
SB0
Flags:
Format:
The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.
No flags are affected. opc
Bytes Cycles Opcode
(Hex)
1 4 4F
SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing.
6-75
INSTRUCTION SET S3F80JB
SB1
— Select Bank 1
SB1
Flags:
Format:
Example:
The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some KS88-series microcontrollers.)
No flags are affected. opc
Bytes Cycles Opcode
(Hex)
1 4 5F
The statement
SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.
6-76
S3F80JB INSTRUCTION SET
SBC
— Subtract With Carry
SBC dst,src
The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.
Flags: C:
> dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow".
Format: opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
SBC R1,R2
→
R1 = 0CH, R2 = 03H
R1 = 05H, R2 = 03H, register 03H = 0AH
Register 01H = 1CH, register 02H = 03H
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.
6-77
INSTRUCTION SET
SCF
— Set Carry Flag
SCF
The carry flag (C) is set to logic one, regardless of its previous value.
Format:
Example:
No other flags are affected. opc
The statement
SCF sets the carry flag to logic one.
Bytes Cycles Opcode
(Hex)
1 4 DF
S3F80JB
6-78
S3F80JB
SRA
— Shift Right Arithmetic
SRA dst
Operation: dst
← dst (7)
INSTRUCTION SET
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.
7 6 0
C
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode dst
2 4 D0 R
4 D1 IR
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA 00H
→
SRA @02H
→
Register 00H = 0CD, C = "0"
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.
6-79
INSTRUCTION SET S3F80JB
SRP/SRP0/SRP1
— Set Register Pointer
SRP src
SRP0
SRP1
Operation: src src
If src (1) = 1 and src (0) = 0 then: RP0 (3–7)
← src
If src (1) = 0 and src (0) = 1 then: RP1 (3–7)
← src
If src (1) = 0 and src (0) = 0 then: RP0 (4–7)
← src
The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
No flags are affected. Flags:
Format: opc src
Bytes Cycles Opcode
(Hex)
Addr Mode src
2 4 31 IM
Examples: The statement
SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to
68H.
6-80
S3F80JB INSTRUCTION SET
STOP
— Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.
No flags are affected. Flags:
Format: opc
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Example: The statement
STOP halts all microcontroller operations.
6-81
INSTRUCTION SET S3F80JB
SUB
— Subtract
SUB dst,src
The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow".
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode dst src opc dst | src opc src dst opc dst src
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB R1,R2
→
R1 = 0FH, R2 = 03H
R1 = 08H, R2 = 03H
Register 01H = 1EH, register 02H = 03H
Register 01H = 17H, register 02H = 03H
Register 01H = 91H; C, S, and V = "1"
Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.
6-82
S3F80JB INSTRUCTION SET
SWAP
— Swap Nibbles
SWAP dst
Operation: dst (0 – 3)
↔ dst (4 – 7)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
7 4 3 0
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected. opc dst
Bytes Cycles Opcode
(Hex)
Addr Mode
2 4 F0
4 F1 dst
R
IR
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:
SWAP 00H
→
SWAP @02H
→
Register 00H = 0E3H
Register 02H = 03H, register 03H = 4AH
In the first example, if general register 00H contains the value 3EH (00111110B), the statement
"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value
0E3H (11100011B).
6-83
INSTRUCTION SET S3F80JB
TCM
— Test Complement Under Mask
TCM dst,src
Operation: (NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.
Format:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:
TCM R0,R1
→
R0 = 0C7H, R1 = 02H, Z = "1"
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1"
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.
6-84
S3F80JB INSTRUCTION SET
TM
— Test Under Mask
TM dst,src
Operation: dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:
TM R0,R1
→
R0 = 0C7H, R1 = 02H, Z = "0"
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.
6-85
INSTRUCTION SET S3F80JB
WFI
— Wait For Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .
No flags are affected. Flags:
Format: opc
Bytes Cycles Opcode
(Hex)
1 4n 3F
( n = 1, 2, 3, … )
Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement:
.
.
.
Main program
EI
WFI
.
.
.
(Next instruction)
Interrupt occurs
.
.
.
Interrupt service routine
Clear interrupt flag
IRET
(Enable global interrupt)
(Wait for interrupt)
Service routine completed
6-86
S3F80JB INSTRUCTION SET
XOR
— Logical Exclusive OR
XOR dst,src
The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Format:
Examples:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected. opc dst | src opc src dst opc dst src
Bytes Cycles Opcode
(Hex)
Addr Mode dst src
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:
XOR R0,R1
→
R0 = 0C5H, R1 = 02H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H, register 02H = 23H
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.
6-87
7
CLOCK CIRCUITS
OVERVIEW
The clock frequency for the S3F80JB can be generated by an external crystal or supplied by an external clock source. The clock frequency for the S3F80JB can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON register, is 8 MHz. The X
IN
and X
OUT
pins connect the external oscillator or clock source to the on-chip clock circuit.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— External crystal or ceramic resonator oscillation source (or an external clock)
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (f
OSC
divided by 1, 2, 8, or 16)
— Clock circuit control register, CLKCON
C1 X IN
C2 X OUT
Figure 7-1. Main Oscillator Circuit
(External Crystal or Ceramic Resonator)
External
Clock
X
IN
Open Pin
X OUT
Figure 7-2. External Clock Circuit
7-1
CLOCK CIRCUITS S3F80JB
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. When stop mode is released, the oscillator starts by a reset operation or by an external interrupt. To enter the stop mode, STOPCON (STOP Control Register) has to be loaded with value, #0A5H before STOP instruction execution. After recovering from the stop mode by a reset or an external interrupt, STOPCON register is automatically cleared.
— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer 0, timer 1, counter A and so on. Idle mode is released by a reset or by an interrupt
(external or internally generated).
STOPCON
STOP
Instruction
CLKCON.3, .4
Oscillator
Stop
Main
OSC
Oscillator
Wake-up
Noise
Filter
1/2
1/8
1/16
M
U
X
CPU CLOCK
INT Pin (1)
NOTES:
1.
An external interrupt with an RC-delay noise filter (for the S3F80JB INT0-9) is fixed to release stop mode and "wake up" the main oscillator.
2.
Because the S3F80JB has no subsystem clock, the 3-bit CLKCON signature code (CLKCON.2-CLKCON.0) is no meaning.
Figure 7-3. System Clock Circuit Diagram
7-2
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable and has the following functions:
— Oscillator frequency divide-by value
The CLKCON.7 - .5 and CLKCON.2- .0 Bit are not used in S3F80JB. After a reset, the main oscillator is activated, and the f
OSC/16
(the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the
CPU clock speed to f
OSC
, f
OSC/2
, f
OSC/8 or f
OSC/16
.
MSB .7
System Clock Control Register (CLKCON)
D4H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Not used
Divide-by selection bits for
CPU clock frequency
00 = fosc/16
01 = fosc/8
10 = fosc/2
11 = fosc (non-divided)
Figure 7-4. System Clock Control Register (CLKCON)
7-3
S3F80JB RESET
8
RESET
OVERVIEW
Resetting the MCU is the function to start processing by generating reset signal using several reset schemes.
During reset, most control and status are forced to initial values and the program counter is loaded from the reset vector. In case of S3F80JB, reset vector can be changed by smart option. (Refer to the page 2-3 or 15-5).
RESET SOURCES
The S3F80JB has six-different system reset sources as following
– The External Reset Pin (nRESET): When the nRESET pin transiting from VIL (low input level of reset pin) to VIH (high input level of reset pin), the reset pulse is generated on the condition of “VDD
≥
VLVD“ in any operation mode.
– Watch Dog Timer (WTD): When watchdog timer enables in normal operating, a reset is generated whenever the basic timer overflow occurs.
– Low Voltage Detect (LVD): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, and
VDD is changed in condition for LVD operation regardless of operation mode, reset occurs. Although
IPOR/LVD Control Bit (smart option bit [7] @03FH) is set to ‘0’, if the operation mode is not in STOP mode, reset signal is generated by LVD.
– Internal Power-ON Reset (IPOR): When IPOR/LVD Control Bit (smart option bit[7] @ 03FH) is set to ‘0’, and VDD is changed in condition for IPOR operation in STOP Mode, a reset is generated.
– External Interrupt (INT0-INT9): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and chip is in stop mode, if external interrupt is enabled, external interrupts by P0 and P2 generate the reset signal.
– STOP Error Detection & Recovery (SED&R): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and chip is in stop or abnormal state, the falling edge input of P0 or P2.4-P2.7 generates the reset signal regardless of external interrupt enable/disable.
8-1
STOP
IPOR / LVD Contorl Bit '1'
(smart option bit[7] @03FH)
LVD
IPOR / LVD Contorl Bit '1'
(smart option bit[7] @03FH)
STOP
IPOR
Watchdog Timer nRESET
1
2
3
4
5
6
RESET
P0&P2
(INT0-INT9)
(EI)external interrupt enable
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
STOP
P0 & P2.4-2.7
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
STOP
Figure 8-1. RESET Sources of The S3F80JB
1. When IPOR/LVD Control Bit of smart option is set to ‘1’, the rising edge detection of LVD circuit while rising of
VDD passes the level of VLVD.
2. When IPOR/LVD Control Bit of smart option is set to ‘0’ and mode is in STOP Mode, reset is generated by
internal power-on reset.
3. Basic Timer over-flow for watchdog timer. See the chapter 11. Basic Timer and Timer 0 for more understanding.
4. The reset pulse generation by transiting of reset pin (nRESET) from low level to high level on the condition that VDD is higher level state than VLVD (Low level Detect Voltage).
5. When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and chip is in stop mode, external interrupt input by P0 and P2 regardless of external interrupt enable/disable generates the reset signal.
8-2
S3F80JB RESET
IPOR / LVD Control Bit '1' smart option bit[7] @03FH
STOP
STOPCON
P0&P2
(INT0~INT9)
Enable/
Disable
Disable
/Enable
LVD
IPOR fosc
BT
(WDT) nRESET
Noise
Filter
Reset Pulse
Generator
IPOR / LVD Control Bit '1' smart option bit[7] @03FH
STOP
STOPCON
P0& P2 External Interrupt
Control Block
Enabled
INT0~INT9
Noise
Filter
P0& P2.4-P2.7
SED&R
Circuit
Falling Edgd
STOPCON
STOP
IPOR / LVD Control Bit '1' smart option bit[7] @03FH
Falling Edge
Detector
Rising Edge
Detector
Back-up Mode
Figure 8-2. RESET Block Diagram of The S3F80JB
RESET
8-3
RESET MECHANISM
The interlocking work of reset pin and LVD circuit supplies two operating modes: back-up mode input, and system reset input. Back-up mode input automatically creates a chip stop state when the reset pin is set to low level or the voltage at V
DD
is lower than V
LVD
. When the reset pin is at a high state and the LVD circuit detects rising edge of V
DD
on the point V
LVD
, the reset pulse generator makes a reset pulse, and system reset occurs. When the operating mode is in STOP mode and IPOR / LVD control bit of smart option is ‘0’, the LVD circuit is disabled to reduce the current consumption under 6uA instead of 20uA (at V
DD
= 3.6 V). Therefore, although the voltage at
V
DD
is lower than V
LVD
, the chip doesn’t go into back-up mode when the operating state is in stop mode and reset pin is High level (Vreset > V
IH
).
EXTERNAL RESET PIN
When the nRESET pin transiting from V
IL
(low input level of reset pin) to V
IH
(high input level of reset pin), the reset pulse is generated on the condition of “V
DD
≥ V
LVD
“.
WATCH DOG TIMER RESET
The watchdog timer that can recover to normal operation from abnormal function is built in S3F80JB. Watchdog timer generates a system reset signal, if Basic Timer Counter (BTCNT) isn’t cleared within a specific time by program. For more understanding of the watchdog timer function, please see the chapter 11, Basic Timer and
Timer0.
LVD RESET
The Low Voltage Detect Circuit (LVD) is built on the S3F80JB product to generate a system reset when
IPOR/LVD Control Bit of smart option is set to ‘1’ regardless of operation mode. So if IPOR / LVD Control Bit of smart option is set to ‘1’ and the operating status is stop mode, LVD can make a system reset. When the voltage at V
DD
is falling down and passing V
LVD
, the chip go into back-up mode at the moment “V
DD
= V
LVD
”. And the voltage at V
DD
is rising up, the reset pulse is occurred at the moment “V
DD
≥ V
LVD
“.
IPOR / LVD Control Bit: smart option bit[7] @03FH ( note 1 )
LVD
( note3 )
( note4 )
IPOR
STOPCON (note 2)
STOP Instruction
Figure 8-3. RESET Block Diagram by LVD for The S3F80JB in Stop Mode
Reset
8-4
S3F80JB RESET
NOTES
1. IPOR / LVD Control Bit is one of smart option bits assigned address 03FH. User can enable / disable
LVD in the stop mode by manipulating this bit. When the value is ‘1’, LVD always operate in the normal and stop mode. When the value is ‘0’, LVD is disabled in the stop mode. But, LVD is enabled in the normal operating mode.
2. CPU can enter stop mode by setting STOPCON (Stop Control Register) into 0A5H before execution
STOP instruction.
3. This signal is output of IPOR/LVD Control Bit setting. So that is one of two cases; one is LVD enable in STOP mode, the other is LVD disable in STOP mode.
4. This signal is output relating to STOP mode. If STOPCON has 0A5H, and STOP instruction is executed, that output signal makes S3F80JB enter STOP mode. So that is one of two statuses; one is
STOP mode, the other is not STOP mode.
5. In S3F80JB, one between LVD and IPOR is selected as reset source by IPOR / LVD Control Bit setting value of smart option in the stop mode. If the setting value is ‘0’, LVD can be disabled by
STOP instruction. Instead of LVD, IPOR is enabled. If the setting value is ‘1’, LVD is enabled regardless of executing STOP instruction and IPOR is disabled.
INTERNAL POWER-ON RESET
The power-on reset circuit is built on the S3F80JB product. During a power-on reset, the voltage at V
DD
goes to high level and the schmitt-trigger input of POR circuit is forced to low level and then to high level. The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the schmitt- trigger input senses the low level. This on-chip POR circuit consists of an internal resistor, an internal capacitor, and a schmitt- trigger input transistor. IPOR can be enabled by setting IPOR / LVD control bit of smart option to ‘0’.
V
DD
System Reset
C
Schmitt Trigger Inverter
V SS
R: 3000k
Ω On-Chip Internal Resistor
C: 340pF On-Chip Internal Capacitor
Figure 8-4. Internal Power-On Reset Circuit
8-5
Voltage [V]
V DD
T
VDD
= 1ms
(V DD Rising Time)
Reset Pulse Width
V IH = 0.85 V DD
Va
V IL = 0.4 V DD
V DD
Reset pulse
Time
Figure 8-5. Timing Diagram for Internal Power-On Reset Circuit
NOTE
The system reset operation depends on the interlocking work of the reset pin, LVD circuit and Internal
POR. The LVD circuit can be disabled and enabled in the stop mode by smart option. If 3FH.7 is ‘1’, LVD circuit is always enabled. In this case the system reset by LVD circuit occurs in stop mode. But, if 3FH.7 is
‘0’, the system reset by LVD circuit doesn’t occur in stop mode.
Refer to page 2-3 relating to the smart option. The rising time of VDD must be less than 1ms. If not, IPOR can’t detect power on reset.
8-6
S3F80JB RESET
If "Vreset > VIH", the operating status is in STOP mode and IPOR / LVD control bit of smart option is '0', LVD circuit is disabled in the S3F80JB.
V DD a 0.85V
DD
V LVD b
Va b
0.4V
DD
Reset Pulse Width
NOTE: Va is a schmitt trigger input signal of internal power-on reset (IPOR).
a. System reset is not occurred.
b. System reset is occurred by internal POR circuit.
Figure 8-6. Reset Timing Diagram for The S3F80JB in STOP mode by IPOR
EXTERNAL INTERRUPT RESET
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop mode, if external interrupt is occurred by among the enabled external interrupt sources, from INT0 to INT9, reset signal is generated.
8-7
STOP ERROR DETECTION & RECOVERY
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop or abnormal state, the falling edge input of P0 and P2.4-P2.7 generates the reset signal.
Refer to following table and figure for more information.
V
(V
DD
Table 8-1. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1” (always LVD-On)
Slope of V
DD
Rising up from
DD
< V
LVD
Standstill
≥ V
LVD
)
Condition
V
DD
V
DD
≥ V
LVD
The voltage level of reset pin
(Vreset)
≥ V
IH
V
DD
≥ V
LVD
Vreset < V
IH
V
DD
< V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
V
DD
≥ V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
Reset
Source
LVD circuit
–
Reset pin
System Reset
System reset occurs
No system reset
– No reset
System reset occurs
V
Slope of V
V
LVD
DD
< 0.4V
DD
Standstill
(V
DD
≥ V
LVD
)
Table 8-2. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0”
DD
Rising up from
0.4 V
DD
< V
DD
<
Rising up from
V
DD
V
Condition
DD
≥ V
LVD
The voltage level of reset pin
(Vreset)
≥ V
IH
V
DD
> V
LVD
Vreset
IH
V
DD
< V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
V
DD
≥ V
LVD
≥ V
IH
V
DD
> V
LVD
Vreset
IH
V
DD
< V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
V
DD
≥ V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
Reset
Source
–
–
–
Internal POR
–
–
Reset pin
System Reset
No system reset
No system reset
No system reset
System reset occurs
No system reset
No system reset
System reset occurs
NOTE: IPOR / LVD control bit is included in smart option at address 003FH. (3FH.7)
8-8
S3F80JB
POWER-DOWN MODES
The power down mode of S3F80JB are described following that:
— Idle mode
— Back- up mode
RESET
IDLE MODE
Idle mode is invoked by the instruction IDLE (op-code 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active:
— Comparator
I/O port pins retain the state (input or output) they had at the time Idle mode was entered.
IDLE Mode Release
You can release Idle mode in one of two ways:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware reset value for the CLKCON register. If all interrupts are masked in the IMR register, a reset is the only way you can release Idle mode.
2. Activate any enabled interrupt; internal or external. When you use an interrupt to release Idle mode, the 2-bit
CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately following the one which initiated Idle mode is executed.
NOTE
Only external interrupts built in to the pin circuit can be used to release stop mode. To release Idle mode, you can use either an external interrupt or an internally-generated interrupt.
8-9
BACK-UP MODE
For reducing current consumption, S3F80JB goes into Back-up mode. If external reset pin is low state or a falling level of V
DD
is detected by LVD circuit on the point of V
LVD
, chip goes into the back-up mode. Because CPU and peripheral operation were stopped due to oscillation stop, the supply current is reduced. In back-up mode, chip cannot be released from stop state by any interrupt. The only way to release back-up mode is the system-reset operation by interactive work of reset pin and LVD circuit. The system reset of watchdog timer is not occurred in back up mode.
LVD
Rising Edge
Detector
Falling Edge
Detector nRESET
Noise
Filter
V
V
D D
< = V reset
LVD
< = V
IL
Figure 8-7. Block Diagram for Back-up Mode
Back-Up Mode
Voltage [V]
V
DD
Slope of nRESET & V
DD
Pin
Rising edge detected
(V
DD
>= V
LVD
)
V
LVD
Low level detect voltage
Falling edge detected, oscillation stop.
(V
DD
< V
LVD
)
Normal Operation Back up Mode
Reset Pulse generated, oscillation starts
Normal Operation
NOTES:
1, When the rising edge is detected by LVD circuit, Back-up mode is relesased. (V
LVD
= V
DD
)
2. When the falling edge is detected by LVD circuit, Back-up mode is activated (V
LVD
> V
DD
)
Figure 8-8. Timing Diagram for Back-up Mode Input and Released by LVD
8-10
S3F80JB RESET
STOP MODE
STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In
STOP mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current consumption can be reduced. All system functions stop when the clock "freezes," but data stored in the internal register file is retained. STOP mode can be released in one of two ways: by a system reset or by an external interrupt. After releasing from STOP mode, the value of stop control register (STOPCON) is cleared automatically.
PROGRAMMING TIP – To Enter STOP Mode
This example shows how to enter the stop mode.
ORG 0000H Reset address
•
•
•
JP T,
ENTER_STOP:
LD STOPCON,
STOP
NOP
NOP
NOP
RET
ORG
JP T,
ORG 0100H
START: LD
; Reset address
BTCON, #03 ; Clear basic timer counter.
•
•
•
MAIN: NOP
•
•
•
CALL ENTER_STOP ; Enter the STOP mode
•
•
•
•
•
•
LD
JP
BTCON,#02H ; Clear basic timer counter.
T,MAIN
8-11
SOURCES TO RELEASE STOP MODE
Stop mode is released when following sources go active:
— System Reset by external reset pin (nRESET)
— System Reset by Internal Power-On Reset (IPOR)
— Low Voltage Detector (LVD)
— External Interrupt (INT0-INT9)
— SED & R circuit
Using nRESET Pin to Release STOP Mode
Stop mode is released when the system reset signal goes active by nRESET Pin: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained.
When the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in reset address.
Using IPOR to Release STOP Mode
Stop mode is released when the system reset signal goes active by internal power-on reset (IPOR). IPOR is enabled when IPOR/LVD Control Bit is set to ‘0’, and chip status is in stop mode by executing ‘STOP’ instruction. :
All system and peripheral control registers are reset to their default hardware values and contents of all data registers are unknown states. When the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in reset address.
Using LVD to Release STOP Mode
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, and VDD is changed in condition for LVD operation in stop mode, stop mode is released and reset occurs.
Using an External Interrupt to Release STOP Mode
External interrupts can be used to release stop mode. When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and external interrupt is enabled, S3F80JB is released stop mode and generated reset signal. On the other hand, when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode and isn’t generated reset signal. To wake-up from stop mode by external interrupt from INT0 to INT9, external interrupt should be enabled by setting corresponding control registers or instructions.
Please note the following conditions for Stop mode release:
— If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged.
— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering
Stop mode.
— If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains unchanged and the currently selected clock value is used.
8-12
S3F80JB RESET
SED&R (Stop Error Detect and Recovery)
The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2.4-P2.7.
One is releasing from stop status by switching the level of input port (P0 or P2.4-P2.7) and the other is keeping the chip from the stop mode when the chip is in abnormal status.
— Releasing from stop mode
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’, if falling edge input signal enters in through Port0 or P2.4-P2.7, S3F80JB is released stop mode and generate reset signal. On the other hand, when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode.
Reset doesn’t occur. When the falling edge of a pin on Port0 and P2.4-P2.7 is entered, the chip is released from stop mode even though external interrupt is disabled.
— Keeping the chip from entering abnormal - stop mode
This circuit detects the abnormal status by checking the port (P0 and P2.4-P2.7) status. If the chip is in abnormal status it keeps from entering stop mode.
NOTE
In case of P2.0-2.3, SED&R circuit isn’t implemented. So although 4pins, P2.0-2.3, have the falling edge input signal in stop mode, if external interrupt is disabled, the stop state of S3F80JB is unchanged. Do not use stop mode if you are using an external clock source because Xin input must be cleared internally to VSS to reduce current leakage.
8-13
SYSTEM RESET OPERATION
System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal
CPU and peripheral modules. This procedure brings the S3F80JB into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance. The minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are then reset to their default hardware values (See Tables 8-3).
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watch-dog function (Basic Timer) is enabled.
— Port 0,2 and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.
— Peripheral control and data register settings are disabled and reset to their default hardware values.
(See Table 8-3.)
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in reset address is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON. But we recommend you should use it to prevent the chip malfunction.
8-14
S3F80JB RESET
HARDWARE RESET VALUES
Tables 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An 'x' means that the bit value is undefined after a reset.
— A dash ('–') means that the bit is either not used or not mapped (but a 0 is read from the bit position)
Table 8-3. Set 1, Bank 0 Register Values After Reset
Register Name Mnemonic Address Bit Values After Reset
Dec Hex 7 6 5 4 3 2 1 0
T0CNT 208 D0H 0 0 0 0 0 0 0 0
T0DATA 209 D1H 1 1 1 1 1 1 1 1
T0CON 210 D2H 0 0 0 0 0 0 0 0
BTCON 211 D3H 0 0 0 0 0 0 0 0
CLKCON 212 D4H 0 0 0 0 0 0 0 0
FLAGS 213 D5H x x x x x x 0 0
RP0 214 D6H 1 1 0 0 0
− − −
RP1 215 D7H 1 1 0 0 1
− − −
Location D8H (SPH) is not mapped.
SPL 217 D9H x x x x x x x x
IPH 218 DAH x x x x x x x x
IPL 219 DBH x x x x x x x x
IRQ 220 DCH 0 0 0 0 0 0 0 0 Interrupt Request Register (Read-
Only)
IMR 221 DDH x x x x x x x x
SYM 222 DEH 0 – – x x x 0 0
PP 223 DFH 0 0 0 0 0 0 0 0
P0 224 E0H 0 0 0 0 0 0 0 0
P1 225 E1H 0 0 0 0 0 0 0 0
P2 226 E2H 0 0 0 0 0 0 0 0
P3 227 E3H 0 – 0 0 1 1 0 0
P4 228 E4H 0 0 0 0 0 0 0 0
P2INT 229 E5H 0 0 0 0 0 0 0 0
P2PND 230 E6H 0 0 0 0 0 0 0 0
P0PUR 231 E7H 0 0 0 0 0 0 0 0
(High P0CONH 232 E8H 0 0 0 0 0 0 0 0
(Low P0CONL 233 E9H 0 0 0 0 0 0 0 0
8-15
Table 8-3. Set 1, Bank 0 Register Values After Reset (Continued)
Register Name Mnemonic Address Bit Values After Reset
Dec Hex 7 6 5 4 3 2 1 0
(High P1CONH 234 EAH 1 1 1 1 1 1 1 1
Port 1 Control Register (Low Byte) P1CONL 235 EBH 0 0 0 0 0 0 0 0
(High P2CONH 236 ECH 0 0 0 0 0 0 0 0
Port 2 Control Register (Low Byte) P2CONL 237 EDH 0 0 0 0 0 0 0 0
P2PUR 238 EEH 0 0 0 0 0 0 0 0
P3CON 239 EFH 0 0 0 0 0 0 0 0
P4CON 240 F0H 0 0 0 0 0 0 0 0
P0INT 241 F1H 0 0 0 0 0 0 0 0
P0PND 242 F2H 0 0 0 0 0 0 0 0
CACON 243 F3H 0 0 0 0 0 0 0 0
Timer 1 Counter Register (High Byte) T1CNTH 246 F6H 0 0 0 0 0 0 0 0
(High T1DATAH 248 F8H 1 1 1 1 1 1 1 1
(Low T1DATAL 249 F9H 1 1 1 1 1 1 1 1
T1CON 250 FAH 0 0 0 0 0 0 0 0
STOPCON 251 FBH 0 0 0 0 0 0 0 0
Locations FCH is not mapped. ( For factory test )
Timing
BTCNT 253 FDH 0 0 0 0 0 0 0 0
EMT 254 FEH 0 1 1 1 1 1 0 –
IPR 255 FFH x x x x x x x x
NOTES:
1. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a 1 to this bit during normal operation, a system malfunction may occur.
2. Except for T0CNTH, T0CNTL, IRQ, T1CNTH, T1CNTL, T2CNTH, T2CNTL, and BTCNT, which are read-only, all registers in set 1 are read/write addressable.
3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.
8-16
S3F80JB RESET
Table 8-4. Set 1, Bank 1 Register Values After Reset
Register Name Mnemonic Address Bit Values After Reset
Dec Hex 7 6 5 4 3 2 1 0
LVDCON 224 E0H – – – – – – – 0
P345CON 225 E1H 0 1 0 1 0 0 0 0
(High P4CONH 226 E2H 1 1 1 1 1 1 1 1
(Low P4CONL 227 E3H 1 1 1 1 1 1 1 1
(High E4H 0 0 0 0 0 0 0 0
(Low E5H 0 0 0 0 0 0 0 0
(High T2DATAH 230 E6H 1 1 1 1 1 1 1 1
T2DATAL 231 E7H 1 1 1 1 1 1 1 1
T2CON 232 E8H 0 0 0 0 0 0 0 0
CMOD 233 E9H 0 0 0 0 0 0 0 0
CMPREG 234 EAH 0 0 0 0 0 0 0 0
Selection EBH – – – – 0 0 0 0
Flash Memory Sector Address FMSECH 236 ECH 0 0 0 0 0 0 0 0
Register (High Byte)
Flash Memory Sector Address
Register (Low byte)
Flash Memory User Programming
Enable Register
FMSECL 237 EDH 0 0 0 0 0 0 0 0
FMUSR 238 EEH 0 0 0 0 0 0 0 0
FMCON 239 EFH 0 0 0 0 – – – 0
NOTES:
1. P345CON will be initialized as “50H” to set P3.4 and P3.5 into open drain output mode after reset operation.
2. S3F80JB has P4CONH, P4CONL and P4CON as port4 control registers. P4CONH and P4CONL will be initialized as the C-MOS input with pull up mode after reset. On the other hand, P4CON will be initialized as open-drain output mode. After reset, status of port4 is decided by P345CON.0 bit. So port4 reset status will be initialized as open-drain output mode.
8-17
Normal
Operating
Stop
Mode
Table 8-5. Reset Generation According to the Condition of Smart Option
Reset Pin
Watch Dog Timer Enable
O Reset
O Reset
Smart option7th bit @3FH
1 0
O Reset
O Reset
LVD O Reset
External Interrupt (EI) P0 and P2 X External ISR X External ISR
External Interrupt (DI) P0 and
P2
X Continue X Continue
Reset Pin
Watch Dog Timer Enable
IPOR
O Reset
X STOP
X STOP
O Reset
X STOP
O STOP Release and
Reset
X STOP LVD O STOP Release and
Reset
External Interrupt (EI-Enable) P0 and P2
SED&R P0 & P2.4-2.7
X
X
STOP Release and
External ISR
STOP Release and
Continue
O
O
STOP Release and
Reset
STOP Release and
Reset
NOTES
1. ’X’ means that a corresponding reset source don’t generate reset signal. ‘O’ means that a corresponding reset source generates reset signal.
2. ’Reset’ means that reset signal is generated and chip reset occurs,
3. ’Continue’ means that it executes the next instruction continuously without ISR execution.
4. ’External ISR’ means that chip executes the interrupt service routine of generated external interrupt source.
5. ’STOP ‘ means that the chip is in stop state.
6. ‘STOP Release and External ISR’ means that chip executes the external interrupt service routine of generated external interrupt source after STOP released.
7. ‘STOP Release and Continue’ means that executes the next instruction continuously after STOP released.
8-18
S3F80JB RESET
RECOMMENDATION FOR UNUSUED PINS
To reduce overall power consumption, please configure unused pins according to the guideline description Table
8-6.
Pin Name
Port 0
Port 1
Port 2
P3.0–3.1
P3.2– P3.3
P3.4–P3.5
Port 4
TEST
Table 8-6. Guideline for Unused Pins to Reduced Power Consumption
• Set Input mode
• Enable Pull-up Resister
• No Connection for Pins
• Set Open-Drain Output mode
• Set P1 Data Register to #00H.
• Disable Pull-up Resister
• No Connection for Pins
• Set Push-pull Output mode
• Set P2 Data Register to #00H.
• Disable Pull-up resister
• No Connection for Pins
• Set Push-pull Output mode
• Set P3 Data Register to #00H.
• No Connection for Pins
–
• Set Push-pull Output mode
• Set P3.4 and P3.5 Data Register to #00H.
• No Connection for Pins
• Set Push-pull Output mode
• Set P4 Data Register to #00H.
• No Connection for Pins
•
Recommend
Connect to V
SS
.
Example
• P0CONH
← # 00H or 0FFH
• P0CONL
← # 00H or 0FFH
• P0PUR
← # 0FFH
• P1CONH
← # 55H
• P1CONL
← # 55H
• P1
← # 00H
•
•
•
•
•
•
•
• P345CON
← # A0H
• P3
← # 00H
•
P2CONH
← # 0AAH
P2CONL
← # 0AAH
P2
← # 00H
P2PUR
← # 00H
P3CON
← # 11010010B
P3
← # 00H
No connection
P4CONH
← # 0AAH
• P4CONL
← # 0AAH
• P4
← # 00H
–
8-19
SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS
For more understanding, please see the below description Table 8-7.
Table 8-7. Summary of Each Mode
Item/Mode Back-up
Approach
Condition
Port status
Control
Register
• External nRESET pin is low
level state or V
DD
is lower
than V
LVD
• External nRESET pin is on rising edge.
• The rising edge at VDD is
detected by LVD circuit.
(When VDD
≥ V
LVD
)
• Watch-dog timer overflow signal is activated.
• All I/O port is floating status
except for P3.2 and P3.3
• All port becomes input mode
but is blocked.
• Disable all pull-up resister
except for P3.2 and P3.3
• All control register and
system register are
initialized as list of Table 8-3.
• All I/O port is floating status except P3.2 and P3.3.
• Disable all pull-up resister except P3.2 and P3.3.
•
Reset Status
All control register and system register are initialized as list of Table 8-3.
Releasing
Condition
Others
• External nRESET pin is high
(rising edge).
• The rising edge of LVD
circuit is generated.
• There is no current
consumption in chip.
• After passing an oscillation
warm-up time
• There can be input leakage
current in chip.
Stop
• STOPCON
← # A5H
STOP
( LD STOPCON,#0A5H )
( STOP)
• All port is keep the previous
status.
• Output port data is not
changed.
–
• External interrupt, or reset
• SED & R Circuit.
• It depends on control
program
8-20
9
I/O PORTS
OVERVIEW
The S3F80JB microcontroller has two kinds of package and different I/O number relating to the package type:
44-QFP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports and P3 is a 6-bit port. This gives a total of 38 I/O pins.
32-SOP package has four bit-programmable I/O ports, P0–P3. Three ports, P0–P2, are 8-bit ports and P3 is a 2bit port. This gives a total of 26 I/O pins.
Each port is bit-programmable and can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.
For IR applications, port0, port1, and port2 are usually configured to the keyboard matrix and port 3 is used to IR drive pins.
Table 9-1, 9-2 and 9-3 give you a general overview of S3F80JB I/O port functions.
9-1
I/O PORTS S3F80JB
Table 9-1. S3F80JB Port Configuration Overview (44-QFP)
Port 0
Port 1
8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable register (P0INT) and pending control register (P0PND); Pull-up resistors can be assigned to individual P0 pins using P0PUR register settings. This port is dedicated for key input in IR controller application.
8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
This port is dedicated for key output in IR controller application.
Port 2 8-bit general-purpose I/O port; Input or push-pull output. The P2 pins, P2.0–P2.7, can be used as external interrupt inputs and have noise filters. The P2INT register is used to enable/disable interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up resistors can be assigned to individual P2 pins using P2PUR register settings. Also P2.4-P2.7 can be assigned individually as analog input pin for comparator.
P3.0–P3.1 P3.0 is configured input functions (Input mode, with or without pull-up, for normal input or T0CAP) or output functions (push-pull or open-drain output mode, for normal output or T0PWM). P3.1 is configured input functions (Input mode, with or without pull-up, for normal input) or output functions (push-pull or open-drain output mode, for normal output or REM function). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED drive.
P3.2–P3.3 P3.2 is configured only input pin with pull-up resistor (for normal input or T0CK function). P3.3 is configured only input pin with pull-up resistor (for normal input, T1CAP function, or T2CAP function). P3.3 can be used for IR signal capture pin with T1CAP function or T2CAP function.
P3.4–P3.5 2-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
P3.7
Port 4
P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.
8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
This port is dedicated for key output in IR controller application.
9-2
Table 9-3. S3F80JB Port Configuration Overview (32-SOP)
Port 0
Port 1
P3.7
8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable register (P0INT) and pending control register (P0PND); Pull-up resistors can be assigned to individual P0 pins using P0PUR register settings. This port is dedicated for key input in IR controller application.
8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
This port is dedicated for key output in IR controller application.
Port 2 8-bit general-purpose I/O port; Input or push-pull output. The P2 pins, P2.0–P2.7, can be used as external interrupt inputs and have noise filters. The P2INT register is used to enable/disable interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up resistors can be assigned to individual P2 pins using P2PUR register settings. Also P2.4-P2.7 can be assigned individually as analog input pin for comparator.
P3.0–P3.1 2-bit I/O port; P3.0 and P3.1 are configured input functions (Input mode, with or without pull-up, for
T0CK, T0CAP or T1CAP) or output functions (push-pull or open-drain output mode, or for REM and T0PWM). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED drive.
P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.
9-3
I/O PORTS S3F80JB
PORT DATA REGISTERS
Table 9-4 gives you an overview of the register locations of all four S3F80JB I/O port data registers. Data registers for ports 0,1,2 and 4 have the general format shown in Figure 9-1.
NOTE
The data register for port 3, P3, contains 6-bits for P3.0–P3.5, and an additional status bit (P3.7) for carrier signal on/off.
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Table 9-4. Port Data Register Summary
Mnemonic
P0
P1
P2
P3
P4
224
225
226
227
228
E0H
E1H
E2H
E3H
E4H
Set 1, Bank 0
Set 1, Bank 0
Set 1, Bank 0
Set 1, Bank 0
Set 1, Bank 0
R/W
R/W
R/W
R/W
R/W
Because port 3 is a 6–bit I/O port, the port 3 data register only contains values for P3.0 – P3.5. The P3 register also contains a special carrier on/off bit (P3.7). See the port3 description for details. All other I/O ports are 8–bit.
MSB .7
.6
.5
.4
.3
.2
.1
.0
LSB
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Pn.1
Pn.0
NOTE: Because port 3 is a 6-bit I/O port, the port 3 data register only
contains values for P3.0-P3.5.
The P3 register also contains a special carrier on/off bit (P3.7).
See the port 3 description for details.
All other S3F80JB I/O ports are 8-bit.
Figure 9-1. S3F80JB I/O Port Data Register Format
9-4
PULL-UP RESISTOR ENABLE REGISTERS
You can assign pull-up resistors to the pin circuits of individual pins in port0 and port2. To do this, you make the appropriate settings to the corresponding pull-up resistor enable registers; P0PUR and P2PUR. These registers are located in set 1, bank 0 at locations E7H and EEH, respectively, and are read/write accessible using Register addressing mode.
You can assign a pull-up resistor to the port 1 and port 4 pins, using basic port configuration setting in the
P1CONH, P1CONL, P4CONH, and P4CONL.
You can assign a pull-up resistor to the port 3 pins, P3.0, P3.1, P3.4, and P3.5 in the input mode using basic port configuration setting in the P3CON and P345CON registers.
P3.2–P3.3 are configured only input pins with pull-up resistor.
MSB
Pull-up Register Enable Registers (PnPUR, where n = 0/2)
Set 1 , E7H/ EEH , Bank0 , R/W
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Pn.7
Pn.6
Pn.1
Pn.0
Pn.2
Pn.3
Pn.5
Pn.4
Pull-up Resistor Enable Bit:
0 = Disable pull-up resistor
1 = Enable pull-up resistor
NOTES:
1. Pull-up resistors can be assigned to the port 3 pins, P3.0 and P3.1,
by making the appropriate setting the port 3 control register P3CON.
2. Pull-up resistors can be assigned to the port 3 pins , P3.4 and P3.5
by making the appropriate setting the port 3[4:5] and port3[6:7]
control register P345CON.
3. Pull-up resistors can be assigned to the P1 and P4 pins, by making the
appropriate setting the port 1 control register P1CONL, P1CONH and
the port 4 control register P4CONL, P4CONH respectively.
Figure 9-2. Pull-up Resistor Enable Registers (Port 0 and Port 2 only)
9-5
S3F80JB BASIC TIMER and TIMER 0
10
BASIC TIMER and TIMER 0
OVERVIEW
The S3F80JB has two default timers: the 8-bit basic timer and the 8-bit general-purpose timer/counter.
The 8-bit timer/counter is called timer 0.
BASIC TIMER (BT)
You can use the basic timer (BT) in two different ways:
— As a watch-dog timer to provide an automatic reset mechanism in the event of a system malfunction
— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (f
OSC
divided by 4096, 1024 or 128) with multiplexer
— 8-bit basic timer counter, BTCNT (FDH, Set 1, Bank0, Read-only)
— Basic timer control register, BTCON (D3H, Set 1, Bank0, R/W)
TIMER 0
Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting:
— Interval timer mode
— Capture input mode with a rising or falling edge trigger at the P3.0 pin
Timer 0 has the following functional components:
— Clock frequency divider (f
OSC
divided by 4096, 256 or 8) with multiplexer
— External clock input pin (T0CK)
— 8-bit timer 0 counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
— I/O pins for capture input (T0CAP) or match output
— Timer 0 overflow interrupt (IRQ0, vector FAH) and match/capture interrupt (IRQ0, vector FCH) generation
— Timer 0 control register, T0CON (D2H, Set 1, Bank0, R/W)
NOTE
The CPU clock should be faster than basic timer clock and timer 0 clock.
10-1
BASIC TIMER and TIMER 0 S3F80JB
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watch-dog timer function. It is located in Set 1 and
Bank0, address D3H, and is read/write addressable using register addressing mode.
A reset clears BTCON to '00H'. This enables the watch-dog function and selects a basic timer clock frequency of fOSC/4096. To disable the watch-dog function, you must write the signature code '1010B' to the basic timer register control bits BTCON.7–BTCON.4. For improved reliability, using the watch-dog timer function is recommended in remote controllers and hand-held product applications.
MSB .7
Basic Timer Control Register (BTCON)
D3H, Set 1, Bank 0 , R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Watch-dog Timer Enable Bits:
1010B = Disable watch-dog function
Others = Enable watch-dog function
Divider Clear Bit for BT and T0:
0 = No effect
1 = Clear both dividers
Basic Timer Counter Clear Bits:
0 = No effect
1 = Clear BTCNT
Basic Timer Input Clock Selection Bits:
00 = f OSC /4096
01 = f OSC /1024
10 = f OSC /128
11 = Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
S3F80JB BASIC TIMER and TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watch-dog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears BTCON to '00H', automatically enabling the watch-dog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.
A reset is generated whenever the basic timer overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
Stop mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of f
OSC
/4096. If an external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
10-3
BASIC TIMER and TIMER 0 S3F80JB
TIMER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt
— Clear timer0 match/capture interrupt pending conditions
T0CON is located in Set 1, Bank0, at address D2H, and is read/write addressable using register addressing mode.
A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency of fOSC/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.3.
The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address FAH. When a timer0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.
To enable the timer 0 mach/capture interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls T0CON.0. When a “1” is detected, a timer0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a “0” to the timer0 interrupt pending bit, T0CON.0.
10-4
S3F80JB BASIC TIMER and TIMER 0
MSB .7
.6
Timer 0 Control Register (T0CON)
D2H, Set 1, Bank0 , R/W
.5
.4
.3
.2
.1
.0
LSB
Timer 0 Input Clock Selection Bits:
00 = f
01 = f
OSC
OSC
/4096
/256
10 = f OSC /8
11 = External clock (NOTE)
Timer 0 Interrupt Pending Bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 0 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 0 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Timer 0 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge, counter running, OVF can occur)
10 = Capture mode (capture on falling edge, counter running, OVF can occur)
11 = PWM mode (OVF interrupt can occur)
NOTE: The external clock source of timer 0 is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 44-pin package.
Figure 10-2. Timer 0 Control Register (T0CON)
MSB .7
.6
Timer 0 Data Register (T0DATA)
D1H, Set1, Bank 0 , R/W
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 10-3. Timer 0 DATA Register (T0DATA)
10-5
BASIC TIMER and TIMER 0 S3F80JB
TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)
The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture interrupt (T0INT). T0OVF is interrupt with level IRQ0 and vector FAH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, FCH.
A timer 0 overflow interrupt (T0OVF) pending condition is automatically cleared by hardware when it has been serviced. The T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a “1” to the T0CON.0 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH) and clears the counter.
If, for example, you write the value ‘10H’ to T0DATA, ‘0BH’ to T0CON, the counter will increment until it reaches
‘10H’. At this point, the T0 interrupt request is generated. And after the counter value is reset, counting resumes.
With each match, the level of the signal at the timer 0 output pin is inverted (See Figure 10-4).
IRQ0(T0INT)
Pending (T0CON.0)
Interrupt
Enable/Disable
(T0CON.1)
CLK
8-Bit Counter
(T0CNT)
8-Bit Comparator
R (Clear)
Match
Buffer Register
T0CON.3
CTL
T0CON.5
T0CON.4
P3.0/T0CAP
Match Signal
T0CON.3
Timer0 Data Register
(T0DATA)
Figure 10-4. Simplified Timer 0 Function Diagram: Interval Timer Mode
10-6
S3F80JB BASIC TIMER and TIMER 0
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at ‘FFH’, and then continues incrementing from ‘00H’.
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0PWM pin is held to low level as long as the reference data value is less than or equal to (
≤ ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t
CLK
× 256 (See Figure 10-5).
CLK
IRQ0
(T0INT)
(T0PNT.0) Pending
Interrupt Enable/Disable
(T0CON.1)
8-bit Counter
(T0CNT)
8-bit Comparator
Buffer Register
Timer0 Data Register
(T0DATA) overflow clear
Match
Interrupt Enable/Disable
(T0CON.2)
Pending
(T0PNT.0)
IRQ0 (T0OVF)
CTL
T0CON.5
T0CON.4
Match Signal
T0CON.3
T0OVF
P3.0/T0PWM
High level when data > counter
Low level when data < counter
Figure 10-5. Simplified Timer 0 Function Diagram: PWM Mode
10-7
BASIC TIMER and TIMER 0 S3F80JB
Capture Mode
In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value into the T0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by setting the value of the timer 0 capture input selection bit in the port 3 control register, P3CON.2, (set 1, bank 0,
EFH). When P3CON.2 is “1”, the T0CAP input is selected. When P3CON.2 is set to “0”, normal I/O port (P3.0) is selected.
Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the T0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (See Figure 10-6).
P3.0/T0CAP
Interrupt
Enable/Disable
(T0CON.2)
CLK
8-bit Counter
(T0CNT)
Pending
T0CON.5
T0CON.4
Timer 0 Data Register
(T0DATA)
Pending
Interrupt
Enable/Disable
(T0CON.1)
IRQ0 (T0OVF)
IRQ0 (T0INT)
Figure 10-6. Simplified Timer 0 Function Diagram: Capture Mode
10-8
S3F80JB BASIC TIMER and TIMER 0
X IN
X IN
P3.1/T0CK or
P3.2/T0CK
(note 3)
P3.0/T0CAP
Bit 1
RESET or STOP
Bits 3, 2
Clear
Data Bus
Basic Timer Control Register
(Write '1010xxxxB' to disable.)
DIV
R
Bit 0
1/4096
1/1024
1/128
R
DIV
1/4096
1/256
1/8
Bits 5, 4
GND
MUX
Bits 7, 6
MUX
8-Bit Up Counter
(BTCNT, Read-Only)
OVF
When BTCNT.4 is set after releasing from
RESET or STOP mode, CPU clock starts.
Bit 2
Data Bus
OVF
RESET
IRQ0
(Timer 0 Overflow)
8-Bit Up-Counter
(T0CNT)
R Clear
Match (2)
Bit 3
Bit 1
8-Bit Compatator
Bit 0
IRQ0
(Timer 0 Match)
T0PWM
Timer 0 Buffer
Register
Bits 5, 4
Match Signal
T0CON.3
T0OVF
Timer 0 Data Register
(T0DATA)
Data Bus
Basic Timer Control Register
Timer 0 Control Register
NOTES:
1.
During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
2.
It is available only in using internal mode.
3.
The external clock source is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 42/44-pin package.
Figure 10-7. Basic Timer and Timer 0 Block Diagram
10-9
BASIC TIMER and TIMER 0
PROGRAMMING TIP — Configuring the Basic Timer
This example shows how to configure the basic timer to sample specifications:
ORG
LD BTCON,#0AAH ; Disable the watchdog timer
LD CLKCON,#18H
CLR
CLR
SYM
SPL
; Disable global and fast interrupts
; Stack pointer low byte
→ "0"
; Stack area starts at 0FFH
•
•
•
SRP #0C0H ;
EI ; interrupts
•
•
•
MAIN LD BTCON,#52H ; Enable the watchdog timer
;
OSC
/4096
;
NOP
NOP
•
•
•
JP
•
•
•
T,MAIN
S3F80JB
10-10
S3F80JB BASIC TIMER and TIMER 0
PROGRAMMING TIP — Programming Timer 0
This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:
— Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds
— General register 60H (page 0)
→ 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0 interrupt
VECTOR 00FAH,T0OVER ; Timer 0 overflow interrupt
VECTOR 00FCH ,T0INT ; Timer 0 match/capture interrupt
ORG
LD BTCON,#0AAH ;
LD CLKCON,#18H ;
CLR SYM
CLR SPL
; and
; Stack pointer low byte
→ "0"
; Stack area starts at 0FFH
•
•
•
LD T0CON,#4BH ;
; /256
;
; the interrupt
;
LD T0DATA,#5DH ; the interrupt
;
SRP #0C0H ;
EI
•
•
•
T0INT: PUSH RP0
SRP0
INC R0
; Save RP0 to stack
;
;
← 60H
← R0 + 1
ADD R2,R0 ;
ADC R3,R2 ;
ADC R4,R0 ;
(Continued
10-11
BASIC TIMER and TIMER 0
PROGRAMMING TIP — Programming Timer 0 (Continued)
CP R0,#32H ;
× 4 = 200 ms
JR ULT,NO_200MS_SET
BITS R1.2 ; Bit setting (61.2H)
NO_200MS_SET:
LD T0CON,#42H ;
POP RP0 ; Restore register pointer 0 value
T0OVER IRET ; Return from interrupt service routine
S3F80JB
10-12
S3F80JB TIMER 1
11
TIMER 1
OVERVIEW
The S3F80JB microcontroller has a 16-bit timer/counter called Timer 1 (T1). For universal remote controller applications, Timer 1 can be used to generate the envelope pattern for the remote controller signal. Timer 1 has the following components:
— One control register, T1CON (FAH, Set 1, Bank0, R/W)
— Two 8-bit counter registers, T1CNTH and T1CNTL (F6H and F7H, Set 1, Bank0, Read-only)
— Two 8-bit reference data registers, T1DATAH and T1DATAL (F8H and F9H, Set 1, Bank0, R/W)
You can select one of the following clock sources as the Timer 1 clock:
(f
OSC
) divided by 4, 8, or 16
— Internal clock input from the counter A module (counter A flip/flop output)
You can use Timer 1 in three ways:
— As a normal free run counter, generating a Timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time intervals.
— To generate a Timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit Timer 1 count value matches the
16-bit value written to the reference data registers.
— To generate a Timer 1 capture interrupt (IRQ1, vector F6H) when a triggering condition exists at the P3.2 pin for 44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as the trigger).
In the S3F80JB interrupt structure, the Timer 1 overflow interrupt has higher priority than the Timer 1 match or capture interrupt.
NOTE
The CPU clock should be faster than timer 1 clock.
11-1
TIMER 1 S3F80JB
TIMER 1 OVERFLOW INTERRUPT
Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the
16-bit up counter. When you set the Timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.3, you can clear/reset the 16-bit counter value at any time during program operation.
TIMER 1 CAPTURE INTERRUPT
Timer 1 can be used to generate a capture interrupt (IRQ1, vector F6H) whenever a triggering condition is detected at the P3.0 pin for 32 pin package and P3.3 pin for 44 pin package. The T1CON.5 and T1CON.4 bit-pair setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both signal edges.
In capture mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect when a Timer 1 capture interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a “0” to T1CON.0.
P3.0 or P3.3
(note)
CLK
T1CON.5
T1CON.4
T1CON.2
16-Bit Up Counter
Timer 1 Data
Pending
(T1CON.0)
Interrupt
Enable/Disable
(T1CON.1)
NOTE: P3.0 is assigned as T1CAP function for 32 pin package and P3.3 is assigned as T1CAP function for 44 pin package.
IRQ1 (T1OVF)
IRQ1
(T1INT)
Figure 11-1. Simplified Timer 1 Function Diagram: Capture Mode
11-2
S3F80JB TIMER 1
TIMER 1 MATCH INTERRUPT
Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.
In match mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect when a Timer 1 match interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a “0” to T1CON.0.
CLK
IRQ1 (T1INT)
Pending
(T1CON.0)
Interrupt
Enable/Disable
(T1CON.1)
16-Bit Up Counter
R (Clear)
16-Bit Comparator
Match
Timer 1 High/Low
Buffer Register
CTL
T1CON.5
T1CON.4
Match Signal
T1CON.3
Timer 1 Data High/Low
Buffer Register
P3.0 or P3.3
Figure 11-2. Simplified Timer 1 Function Diagram: Interval Timer Mode
11-3
TIMER 1 S3F80JB
CAOF (T-F/F) f OSC /4 f OSC /8 f
OSC
/16
T1CON. 7-.6
MUX
16-Bit Up-Counter
(Read-Only)
R
16-Bit Compatator
T1CON.2
OVF
Clear T1CON.3
Match (note)
T1CON.1
MUX
Timer 1 High/Low
Buffer Register
T1CON.5-.4
IRQ1
T1CON.0
IRQ1
T1CON.3
Match Signal
T1OVF
Timer 1 Data
High/Low Register
Data Bus
NOTE: Match signal is occurrd only in interval mode.
Figure 11-3. Timer 1 Block Diagram
11-4
S3F80JB TIMER 1
TIMER 1 CONTROL REGISTER (T1CON)
The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write addressable. T1CON contains control settings for the following T1 functions:
— Timer 1 input clock selection
— Timer 1 operating mode selection
— Timer 1 16-bit down counter clear
— Timer 1 overflow interrupt enable/disable
— Timer 1 match or capture interrupt enable/disable
— Timer 1 interrupt pending control (read for status, write to clear)
A reset operation clears T1CON to ‘00H’, selecting fosc divided by 4 as the T1 clock, configuring Timer 1 as a normal interval Timer, and disabling the Timer 1 interrupts.
MSB .7
.6
Timer 1 Control Register (T1CON)
FAH, Set 1, Bank 0 , R/W
.5
.4
.3
.2
.1
.0
LSB
Timer 1 Input Clock Selection Bits:
00 = f OSC /4
01 = f OSC /8
10 = f OSC /16
11 = Internal clock (T-F/F)
Timer 1 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = Capture mode (capture on rising and
falling edge, counter running, OVF can occur)
Timer 1 Interrupt Pending Bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 1 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 1 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Figure 11-4. Timer 1 Control Register (T1CON)
11-5
TIMER 1
MSB .7
Timer1 Counter High-byte Register (T1CNTH)
F6H, Set 1, Bank 0, R
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
MSB .7
Timer 1 Counter Low-byte Register (T1CNTL)
F7H, Set 1, Bank 0, R
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
MSB .7
Timer 1 Data High-byte Register (T1DATAH)
F8H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
MSB .7
Timer 1 Data Low-byte Register (T1DATAL)
F9H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 11-5. Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL)
S3F80JB
11-6
12
COUNTER A
OVERVIEW
The S3F80JB microcontroller has one 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (See Figure 12-1):
— Counter A control register, CACON
— 8-bit down counter with auto-reload function
— Two 8-bit reference data registers, CADATAH and CADATAL
Counter A has two functions:
— As a normal interval timer, generating a counter A interrupt (IRQ2, vector ECH) at programmed time intervals.
— To supply a clock source to the 16-bit timer/counter module, Timer 1, for generating the Timer 1 overflow interrupt.
NOTE
The CPU clock should be faster than count A clock.
12-1
COUNTER A S3F80JB
CACON.6-.7
DIV 1
DIV 2
DIV 4
DIV 8
MUX
CLK
16-Bit Down Counter
CACON.0
(CAOF)
To Other Block
(P3.1/REM)
Repeat
Control
Interrupt
Control
MUX CACON.3
INT. GEN.
f OSC
CACON.2
CACON.4-.5
Counter A Data
Low Byte Register
Counter A Data
High Byte Register
Data Bus
NOTE: The value of the CADATAL register is loaded into the 8-bit counter when the operation of the counter A stars. If a borrow occurs, the value of the
CADATAH register is loaded into the 8-bit counter. However, if the next borrow occurs, the value of the CADATAL register is loaded into the 8-bit counter.
IRQ2
(CAINT)
Figure 12-1. Counter A Block Diagram
12-2
COUNTER A CONTROL REGISTER (CACON)
The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON contains control settings for the following functions (See Figure 12-2):
— Counter A clock source selection
— Counter A interrupt enable/disable
— Counter A interrupt pending control (read for status, write to clear)
— Counter A interrupt time selection
MSB .7
Counter A Control Register (CACON)
F3H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Counter A Input Clock Selection Bits:
00 = f OSC
01 = f OSC /2
10 = f OSC /4
11 = f OSC /8
Counter A Output Flip-Flop Control Bit(CAOF):
0 = T-F/F is low
1 = T-F/F is high
Counter A Interrupt Time Selection Bits:
00 = Elapsed time for low data value
01 = Elapsed time for high data value
10 = Elapsed time for low and high data values
11 = Invalid setting
Counter A Mode Selection Bit:
0 = One shot mode
1 = Repeating mode
Counter A Start/Stop Bit:
0 = Stop counter A
1 = Start counter A
Counter A Interrupt Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Figure 12-2. Counter A Control Register (CACON)
MSB .7
Counter A Data High-Byte Register (CADATAH)
F4H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Counter A Data Low-Byte Register (CADATAL)
F5H, Set 1, Bank 0, R/W
MSB .7
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 12-3. Counter A Registers
12-3
COUNTER A S3F80JB
COUNTER A PULSE WIDTH CALCULATIONS t LOW t HIGH t LOW
To generate the above repeated waveform consisted of low period time, t
LOW
, and high period time, t
HIGH.
When CAOF = 0,
t
LOW
= (CADATAL + 2)
× 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock.
t
HIGH
= (CADATAH + 2)
× 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock.
When CAOF = 1,
t
LOW
= (CADATAH + 2)
× 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock.
t
HIGH
= (CADATAL + 2)
× 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock.
To make t
LOW
= 24 us and t
HIGH
= 15 us. f
OSC
= 4 MHz, FX = 4 MHz/4 = 1 MHz
[Method 1] When CAOF = 0,
t
LOW
= 24 us = (CADATAL + 2) / FX = (CADATAL + 2) x 1us, CADATAL = 22.
t
HIGH
= 15 us = (CADATAH + 2) / FX = (CADATAH + 2) x 1us, CADATAH = 13.
[Method 2] When CAOF = 1,
t
HIGH
= 15 us = (CADATAL + 2) / FX = (CADATAL + 2) x 1us, CADATAL = 13.
t
LOW
= 24 us = (CADATAH + 2) / FX = (CADATAH + 2) x 1us, CADATAH = 22.
12-4
Counter A Clock
0H
CAOF = '0'
CADATAL = 01-FFH
CADATAH = 00H
CAOF = '0'
CADATAL = 00H
CADATAH = 01-FFH
High
Low
CAOF = '0'
CADATAL = 00H
CADATAH = 00H
CAOF = '1'
CADATAL = 00H
CADATAH = 00H
Low
High
100H 200H
0H 100H 200H
Counter A Clock
CAOF = '1'
CADATAL = DEH
CADATAH = 1EH
CAOF = '0'
CADATAL = DEH
CADATAH = 1EH
CAOF = '1'
CADATAL = 7EH
CADATAH = 7EH
CAOF = '0'
CADATAL = 7EH
CADATAH = 7EH
E0H
E0H
80H
80H
20H
20H
80H
80H
Figure 12-4. Counter A Output Flip-Flop Waveforms in Repeat Mode
12-5
COUNTER A S3F80JB
PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1
This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:
8.795 us
17.59 us
37.9 kHz 1/3 duty
— Counter A is used in repeat mode
— Oscillation frequency is 4 MHz (0.25
µs)
— CADATAH = 8.795
µs / 0.25 µs = 35.18, CADATAL = 17.59 µs / 0.25 µs = 70.36
— Set P3.1 C-MOS push-pull output and CAOF mode.
— 44 pin package
ORG
START: DI
•
•
•
LD
LD
LD P3CON,#11110010B
;
; Set P3 to C-MOS push-pull output.
;
;
LD
;
; mode
;
;
;
LD
;
A high. pulse
•
•
•
;
12-6
PROGRAMMING TIP — To generate a one-pulse signal through P3.1
This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40
µs width pulse. The program parameters are:
40 us
— Counter A is used in one-shot mode
— Oscillation frequency is 4 MHz ( 1 clock = 0.25
µs)
=
µs / 0.25 µs = 160, CADATAL = 1
— Set P3.1 C-MOS push-pull output and CAOF mode.
ORG
START: DI
•
•
LD
LD
LD
CADATAH,# (160-2)
CADATAL,# 1
P3CON,#11110010B
; Set 40 ms
; Set any value except 00H
;
; Set P3 to C-MOS push-pull output.
;
LD CACON,#00000001B
;
; Clock Source
→ Fosc
;
;
;
;
LD P3,#80H
A Flip-Flop
; Set P3.7(Carrier On/Off) to high.
•
•
•
Pulse_out: LD CACON,#00000101B ; Start Counter A operation
; pulse point.
• ;
• ; falling edge of the pulse starts.
•
12-7
S3F80JB TIMER 2
13
TIMER 2
OVERVIEW
The S3F80JB microcontroller has a 16-bit timer/counter called Timer 2 (T2). For universal remote controller applications, timer 2 can be used to generate the envelope pattern for the remote controller signal. Timer 2 has the following components:
— One control register, T2CON (E8H, Set 1, Bank1, R/W)
— Two 8-bit counter registers, T2CNTH and T2CNTL (E4H and E5H, Set1, Bank1, Read only)
— Two 8-bit reference data registers, T2DATAH and T2DATAL (E6H and E7H, Set 1, Bank1, R/W)
You can select one of the following clock sources as the timer 2 clock:
(f
OSC
) divided by 4, 8, or 16
— Internal clock input from the counter A module (counter A flip/flop output)
You can use Timer 2 in three ways:
— As a normal free run counter, generating a timer 2 overflow interrupt (IRQ3, vector F0H) at programmed time intervals.
— To generate a timer 2 match interrupt (IRQ3, vector F2H) when the 16-bit timer 2 count value matches the
16-bit value written to the reference data registers.
— To generate a timer 2 capture interrupt (IRQ3, vector F2H) when a triggering condition exists at the P3.2 pin for 44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as the trigger).
In the S3F80JB interrupt structure, the timer 2 overflow interrupt has higher priority than the timer 2 match or capture interrupt.
NOTE
The CPU clock should be faster than timer 2 clock.
13-1
TIMER 2 S3F80JB
TIMER 2 OVERFLOW INTERRUPT
Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow occurs in the
16-bit up counter. When you set the timer 2 overflow interrupt enable bit, T2CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T2CON.3, you can clear/reset the 16-bit counter value at any time during program operation.
TIMER 2 CAPTURE INTERRUPT
Timer 2 can be used to generate a capture interrupt (IRQ3, vector F2H) whenever a triggering condition is detected at the P3.0 pin for 32 pin package and P3.3 pin for 44 pin package. The T2CON.5 and T2CON.4 bit-pair setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both signal edges.
In capture mode, program software can poll the timer 2 match/capture interrupt pending bit, T2CON.0, to detect when a timer 2 capture interrupt pending condition exists (T2CON.0 = “1”). When the interrupt request is acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a “0” to T2CON.0.
P3.0 or P3.3
(note)
CLK
16-Bit Up Counter
T2CON.2
Pending
(T2CON.0)
Interrupt
Enable/Disable
(T2CON.1)
IRQ3 (T2OVF)
IRQ3 (T2INT)
T2CON.5
T2CON.4
Timer 2 Data
NOTE: P3.0 is assigned as T2CAP function for 32 pin package and P3.3 is assigned
as T2CAP function for 42/44 pin package.
Figure 13-1. Simplified Timer 2 Function Diagram: Capture Mode
13-2
S3F80JB TIMER 2
TIMER 2 MATCH INTERRUPT
Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit counter value matches the value that is written to the timer 2 reference data registers, T2DATAH and T2DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.
In match mode, program software can poll the timer 2 match/capture interrupt pending bit, T2CON.0, to detect when a timer 2 match interrupt pending condition exists (T2CON.0 = “1”). When the interrupt request is acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a “0” to T2CON.0.
CLK
IRQ3 (T2INT)
Pending
(T2CON.0)
Interrupt
Enable/Disable
(T2CON.1)
16-Bit Up Counter
R (Clear)
16-Bit Comparator
Match
Timer 2 High/Low
Buffer Register
CTL
T2CON.5
T2CON.4
Match Signal
T2CON.3
Timer 2 Data High/Low
Buffer Register
P3.0 or P3.3
Figure 13-2. Simplified Timer 2 Function Diagram: Interval Timer Mode
13-3
TIMER 2 S3F80JB
CAOF (T-F/F) f OSC /4 f OSC /8 f OSC /16
T2CON. 7-.6
MUX
16-Bit Up-Counter
(Read-Only)
R
16-Bit Compatator
T2CON.2
OVF
Clear T2CON.3
Match (note)
T2CON.1
MUX
Timer 2 High/Low
Buffer Register
T2CON.5-.4
IRQ3
T1CON.0
IRQ3
T1CON.3
Match Signal
T2OVF
Timer 2 Data
High/Low Register
Data Bus
NOTE: Match signal is occurrd only in interval mode.
Figure 13-3. Timer 2 Block Diagram
13-4
S3F80JB TIMER 2
TIMER 2 CONTROL REGISTER (T2CON)
The timer 2 control register, T2CON, is located in address E8H, Bank1, Set 1 and is read/write addressable.
T2CON contains control settings for the following T2 functions:
— Timer 2 input clock selection
— Timer 2 operating mode selection
— Timer 2 16-bit down counter clear
— Timer 2 overflow interrupt enable/disable
— Timer 2 match or capture interrupt enable/disable
— Timer 2 interrupt pending control (read for status, write to clear)
A reset operation clears T2CON to ‘00H’, selecting fosc divided by 4 as the T2 clock, configuring timer 2 as a normal interval timer, and disabling the timer 2 interrupts.
MSB .7
.6
Timer 2 Control Register (T2CON)
E8H, Set 1, Bank 1, R/W
.5
.4
.3
.2
.1
.0
LSB
Timer 2 Input Clock Selection Bits:
00 = f OSC /4
01 = f OSC /8
10 = f OSC /16
11 = Internal clock (T-F/F)
Timer 2 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = Capture mode (capture on rising and
falling edge, counter running, OVF can occur)
Timer 2 Interrupt Pending Bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 2 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 2 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 2 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Figure 13-4. Timer 2 Control Register (T2CON)
13-5
TIMER 2
MSB .7
Timer2 Counter High-Byte Register (T2CNTH)
E4H , Set 1, Bank 1, Read-only
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
MSB .7
Timer 2 Counter Low-Byte Register (T2CNTL)
E5H , Set 1, Bank 1, Read-only
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
MSB .7
Timer 2 Data High-Byte Register (T2DATAH)
E6H , Set 1, Bank 1, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
MSB .7
Timer 2 Data Low-Byte Register (T2DATAL)
E7H , Set 1, Bank 1, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 13-5. Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
S3F80JB
13-6
S3F80JB COMPARATOR
14
COMPARATOR
OVERVIEW
P2.4, P2.5, P2.6 and P2.7 can be used as analog input pins for a comparator. The reference voltage for the 4channel comparator can be supplied either internally or externally at P2.7. When an internal reference voltage is used, four channels (P2.4–P2.7) are used for analog inputs and the internal reference voltage is varied in 16 levels. If an external reference voltage is input at P2.7, the other P2.4, P2.5 and 2.6 pins are used for analog inputs.
When a conversion is completed, the result is saved in the comparison result register CMPREG (EAH, Set1,
Bank1, Read-only). The initial values of the CMPREG are undefined and the comparator operation is disabled by a reset. The comparator module has the following components:
— Comparator
— Internal reference voltage generator (4-bit resolution)
— External reference voltage source at P2.7
— Comparator mode register (CMOD)
— Comparison result register (CMPREG)
— Comparison input selection register (CMPSEL)
14-1
COMPARATOR S3F80JB
SCAN signal
P2.4/CIN0
P2.5/CIN1
P2.6/CIN2
P2.7/CIN3
CMPSEL_0
CMPSEL_1
CMPSEL_2
CMPSEL_3
V DD
MUX
Ref
(External)
Ref (Internal)
MUX
MUX
+
-
Comparison
Result Register
(CMPREG)
4
Internal BUS
CMOD.7
CMOD.6
CMOD.5
Not used
CMOD.3
CMOD.2
CMOD.1
CMOD.0
8
1/2R
R
R
1/2R
MUX
NOTES:
1. INT occurs only for digital input selecting. If an analog input, any INT doesn't occur.
2. The comparison results of CIN0,CIN1,CIN2 and CIN3 are respectively stored in
CMPREG0,CMPREG1,CMPREG2 and CMPREG3.
Figure 14-1. Comparator Block Diagram for The S3F80JB
14-2
S3F80JB COMPARATOR
COMPARATOR OPERATION
The comparator compares input analog voltage at CIN0–CIN3 with an external or internal reference voltage
(V
REF
) that is selected by the CMOD register. The result is written to the comparison result register CMPREG at address EAH, Set1, Bank1. The comparison result at internal reference is calculated as follows:
If "1" Analog input voltage
≥ V
REF
+ 150 mV
If "0" Analog input voltage
≤ V
REF
– 150 mV
To obtain a comparison result, the data must be read out from the CMPREG register after V
REF
is updated by changing the CMOD value after a conversion time has elapsed.
Analog Input Voltage (CIN0-3)
Reference Voltage (V REF )
Comparision Time
(CMPCLK x8)
Comparator Clock
(fosc/16, fosc/128)
Comparision Result
(CMPREG)
Comparision
Start
Unknown
Comparision
End
1 1 Unknown 0
Figure 14-2. Conversion Characteristics
14-3
COMPARATOR
MSB .7
Comparator Mode Register (CMOD)
E9H, Set1, Bank 1, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for S3F80JB.
Reference Voltage Selection Bits
Selected Vref=Vdd x (N + 0.5)/16, n=0 to 15
External /Internal Reference Selection Bit
0: Internal reference, CIN0-3:analog input
1: External reference,CIN0-2: analog input, CIN3:reference input
Conversion Timer Control Bit
0: 8x2 7 /fosc,256us at 8MHz
1: 8x2 4 /fosc,32us at 8MHz
Comparator Enale/Disable Bit
0:Comparator operation disable
1:Comparator operation enable
Figure 14-3. Comparator Mode Register (CMOD)
MSB
Comparator Input Selection Register (CMPSEL)
EBH, Set1, Bank 1, R/W
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for S3F80JB.
P2.4 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN0
P2.5 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN1
P2.6 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN2
P2.7 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN3
Figure 14-4. Comparator Input Selection Register (CMPSEL)
S3F80JB
14-4
S3F80JB
Comparator Result Register (CMPREG)
EBH, Set1, Bank 1, R
MSB .7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for S3F80JB Comparator Result Data
Figure 14-5. Comparator Result Register (CMPREG)
COMPARATOR
14-5
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
15
EMBEDDED FLASH MEMORY INTERFACE
OVERVIEW
The S3F80JB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash memory area any time you want. The S3F80JB ‘s embedded 64K-byte memory has two operating features as below:
— User Program Mode
— Tool Program Mode
Flash ROM Configuration
The S3F80JB flash memory consists of 512sectors. Each sector consists of 128bytes. So, the total size of flash memory is 512x128 bytes (64KB). User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time.
— 64Kbyte Internal flash memory
— Sector size: 128-Bytes
— Fast programming Time:
Sector Erase: 10ms (min)
Byte Program: 32us (min)
— User programmable by ‘LDC’ instruction
— Sector (128-Bytes) erase available
— External serial programming support
— Endurance: 10,000 Erase/Program cycles (min)
— Expandable OBPTM (On Board Program)
15-1
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
User Program Mode
This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection).
The S3F80JB has the internal pumping circuit to generate high voltage. Therefore, 12.5V into Vpp (TEST) pin is not needed. To program a flash memory in this mode several control registers will be used.
There are four kind functions in user program mode – programming, reading, sector erase, and one protection mode (Hard lock protection).
Tool Program Mode
This mode is for erasing and programming full area of flash memory by external programming tools. The 6 pins of
S3F80JB are connected to a programming tool and then internal flash memory of S3F80JB can be programmed by Serial OTP/MTP Tools, SPW2 plus single programmer or GW-PRO2 gang programmer and so on. The other modules except flash memory module are at a reset state. This mode doesn’t support the sector erase but chip erase (all flash memory erased at a time) and two protection modes (Hard lock protection/ Read protection). The read protection mode is available only in tool program mode. So in order to make a chip into read protection, you need to select a read protection option when you write a program code to a chip in tool program mode by using a programming tool. After read protect, all data of flash memory read “00”. This protection is released by chip erase execution in the tool program mode.
Table 15-1. Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode
Normal Chip
Pin Name Pin Name
P3.0 SDAT
P3.1
TEST
SCLK
TEST
Pin No.
3[30]
4[31]
9[4]
During Programming
I/O
I/O Serial data pin. Output port when reading and input port when writing. SDAT (P3.0) can be assigned as an input or push-pull output port.
I
I
Function
Serial clock pin. Input only pin.
Tool mode selection when TEST pin sets Logic value ‘1’. If user uses the flash writer tool mode
(ex.spw2+ etc.), user should connect TEST pin to
V
DD
. (S3F80JB supplies high voltage 12.5V by internal high voltage generation circuit.) nRESET nRESET
V
DD
,
V
SS
V
V
DD
,
SS
12[7]
5[32],
6[1]
– Power supply pin for logic circuit.
V
DD should be tied to +3.3 V during programming.
NOTE: [ ] means 32SOP package.
15-2
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
ISP
TM
(ON-BOARD PROGRAMMING) SECTOR
ISP TM sectors located in program memory area can store On Board Program Software (Boot program code for upgrading application code by interfacing with I/O port pin). The ISP TM sectors can’t be erased or programmed by
‘LDC’ instruction for the safety of On Board Program Software.
The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart
Option. If you don’t like to use ISP sector, this area can be used as a normal program memory (can be erased or programmed by ‘LDC’ instruction) by setting ISP disable bit (“1”) at the Smart Option. Even if ISP sector is selected, ISP sector can be erased or programmed in the tool program mode by serial programming tools.
The size of ISP sector can be varied by settings of smart option (Refer to Figure 2-2 and Table 15-2). You can choose appropriate ISP sector size according to the size of On Board Program Software.
(Decimal)
65,536
(HEX)
FFFFH
384(256+128)byte
Internal RAM
FE80H
255
0
Internal
Program
Memory
(Flash)
ISP Sector
Interrupt Vector Area
Smart Option ROM Cell
01FFH, 02FFH, 04FFH or 08FFH
0FFH
03FH
03CH
00H
Figure 15-1. Program Memory Address Space
15-3
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
SMART OPTION
Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable).
Before execution the program memory code, user can set the smart option bits according to the hardware option for user to want to select.
MSB .7
.6
.5
ROM Address: 003CH
.4
.3
Not used
.2
.1
.0
LSB
MSB .7
.6
.5
ROM Address: 003DH
.4
.3
Not used
.2
.1
.0
LSB
MSB .7
.6
.5
ROM Address: 003EH
.4
.3
.2
.1
.0
LSB
ISP Reset Vector Change Selection Bit: (Note1)
0 = OBP Reset vector address
1 = Normal vector (address 100H)
Not used
ISP Reset Vector Address Selection Bits: (Note2)
00 = 200H (ISP Area size: 256 bytes)
01 = 300H (ISP Area size: 512 bytes)
10 = 500H (ISP Area size: 1024 bytes)
11 = 900H (ISP Area size: 2048 bytes)
ISP Protection Size Selection Bits:
00 = 256 bytes
01 = 512 bytes
10 = 1024 bytes
11 = 2048 bytes
ISP Protection Enable/Disable Bit:
0 = Enable (Not erasable)
1 = Disable (Erasable)
(Note3)
(Note4)
MSB .7
.6
.5
ROM Address: 003FH
.4
.3
.2
.1
.0
LSB
Not used
Reserved
IPOR / LVD Control Bit
0 = IPOR enable
LVD disable in the stop mode
1 = IPOR disable
LVD enable in the stop mode
Figure 15-2. Smart Option
15-4
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
NOTES
1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area.
If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless.
2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or
0900H).
If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).
If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can be from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be from 0100H to 08FFH
(2048bytes).
3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by
3EH.1 and 3EH.0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit
(3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.
Table 15-2. ISP Sector Size
Smart Option (003EH) ISP Size Selection Bit
Bit 2 Bit 1 Bit 0
Area of ISP Sector
1 x x
0 0 0
0
100H – 1FFH (256 Bytes)
0
0
0
1
1
0
100H – 2FFH (512 Bytes)
100H – 4FFH (1024 Bytes)
0 1 1 100H – 8FFH (2048 Bytes)
ISP Sector Size
0
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
NOTE: The area of the ISP sector selected by smart option bit (3EH.2 – 3EH.0) can’t be erased and programmed by ‘LDC’ instruction in user program mode.
ISP RESET VECTOR AND ISP SECTOR SIZE
If you use ISP sectors by setting the ISP enable/disable bit to “0” and the reset vector selection bit to “0” at the smart option, you can choose the reset vector address of CPU as shown in Table 15-3 by setting the ISP reset vector address selection bits. (Refer to Figure 2-2 Smart Option).
Table 15-3. Reset Vector Address
Smart Option (003EH)
ISP Reset Vector Address Selection Bit
Reset Vector
Address after POR
Usable Area for
ISP Sector
ISP Sector Size
Bit 7 Bit 6 Bit 5
1 x x 0100H 0 0
0
0
0
0
0
1
0200H
0300H
100H – 1FFH
100H – 2FFH
256 Bytes
512 Bytes
0
0
1
1
0
1
0500H
0900H
100H – 4FFH
100H – 8FFH
1024 Bytes
2048 Bytes
NOTE: The selection of the ISP reset vector address by Smart Option (003EH.7 – 003EH.5) is not dependent of the selection of ISP sector size by Smart Option (003EH.2 – 003EH.0).
15-5
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)
FLASH MEMORY CONTROL REGISTER (FMCON)
FMCON register is available only in user program mode to select the flash memory operation mode; sector erase, byte programming, and to make the flash memory into a hard lock protection.
MSB .7
Flash Memory Control Register (FMCON)
EFH , Set1 , Bank1 , R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Flash Memory Mode Selection Bits
0101: Programming mode
1010: Erase mode
0110: Hard lock mode others: Not used for S3F80JB
Not used for S3F80JB.
Flash (Erase or Hard Lock Protection)
Operation Start Bit
0 = Operation stop
1 = Operation start
(This bit will be cleared automatically just after erase operation.)
Figure 15-3. Flash Memory Control Register (FMCON)
The bit 0 of FMCON register (FMCON.0) is a bit for the operation start of Erase and Hard Lock Protection.
Therefore, operation of Erase and Hard Lock Protection is activated when you set FMCON.0 to “1”. If you write
FMCON.0 to 1 for erasing, CPU is stopped automatically for erasing time (min.10ms). After erasing time, CPU is restarted automatically. When you read or program a byte data from or into flash memory, this bit is not needed to manipulate.
FLASH MEMORY USER PROGRAMMING ENABLE REGISTER (FMUSR)
The FMUSR register is used for a safe operation of the flash memory. This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming mode is disabled, because the value of FMUSR is “00000000B” by reset operation. If necessary to operate the flash memory, you can use the user programming mode by setting the value of FMUSR to “10100101B”. The other value of “10100101B”, user program mode is disabled.
Flash Memory User Programming Enable Register (FMUSR)
EEH, Set1, Bank 1, R/W
MSB .7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash Memory User Programming Enable Bits
10100101: Enable user programming mode
Other values: Disable user programming mode
Figure 15-4. Flash Memory User Programming Enable Register (FMUSR)
15-6
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
FLASH MEMORY SECTOR ADDRESS REGISTERS
There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory
Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory
Address Sector Register High Byte) indicates the high byte of sector address. The FMSECH is needed for
S3F80JB because it has 512 sectors.
One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of sector is XX00H or XX80H. So bit .6-.0 of FMSECL don’t mean whether the value is ‘1’ or ‘0’. We recommend that it is the simplest way to load the sector base address into FMSECH and FMSECL register. When programming the flash memory, user should program after loading a sector base address, which is located in the destination address to write data into FMSECH and FMSECL register. If the next operation is also to write one byte data, user should check whether next destination address is located in the same sector or not. In case of other sectors, user should load sector address to FMSECH and FMSECL Register according to the sector. (Refer to page 15-16
PROGRAMMING TIP — Programming)
MSB
Flash Memory Sector Address Register (FMSECH)
ECH, Set1, Bank 1, R/W
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash Memory Sector Address(High Byte)
NOTE: The High- Byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.
Figure 15-5. Flash Memory Sector Address Register (FMSECH)
MSB
Flash Memory Sector Address Register (FMSECL)
EDH, Set1, Bank 1, R/W
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Don't Care
Flash Memory Sector Address(Low Byte)
NOTE: The Low- Byte flash memory sector address pointer value is the lower eight bits of the 16-bit pointer address.
Figure 15-6. Flash Memory Sector Address Register (FMSECL)
15-7
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
SECTOR ERASE
User can erase a flash memory partially by using sector erase function only in user program mode. The only unit of flash memory to be erased in the user program mode is a sector.
The program memory of S3F80JB, 64Kbytes flash memory, is divided into 512 sectors. Every sector has all 128byte sizes. So the sector to be located destination address should be erased first to program a new data (one byte) into flash memory. Minimum 10ms’ delay time for the erase is required after setting sector address and triggering erase start bit (FMCON.0). Sector erase is not supported in tool program modes (MDS mode tool or programming tool).
Sector 511
(128 byte)
Sector 510
(128 byte)
Sector 127
(128 byte)
Sector 11
(128 byte)
Sector 10
(128 byte)
Sector 0-9
(128 byte x 10)
05FFH
057FH
0500H
04FFH
0000H
FFFFH
FF7FH
FEFFH
3FFFH
3F7FH
Figure 15-7. Sector Configurations in User Program Mode
15-8
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
The Sector Erase Procedure in User Program Mode
1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.
2. Set Flash Memory Sector Address Register (FMSECH and FMSECL).
3. Set Flash Memory Control Register (FMCON) to “10100001B”.
4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
Start
SB1
FMUSR #0A5H
FMSECH High Address of Sector
FMSECL Low Address of Sector
FMCON #10100001B
FMUSR #00H
SB0
Finish One Sector Erase
; Select Bank1
; User Programimg Mode Enable
; Set Sector Base Address
; Mode Select & Start Erase
; User Prgramming Mode Disable
; Select Bank0
Figure 15-8. Sector Erase Flowchart in User Program Mode
NOTES
1. If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL,
FMUSR should be enabled just before starting sector erase operation. And to erase a sector, Flash
Operation Start Bit of FMCON register is written from operation stop ‘0’ to operation start ‘1’. That bit will be cleared automatically just after the corresponding operation completed. In other words, when
S3F80JB is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase, it will get the result of erasing selected sector as user’s a purpose and
Flash Operation Start Bit of FMCON register is also clear automatically.
2. If user executes sector erase operation with FMUSR disabled, FMCON.0 bit, Flash Operation Start
Bit, remains 'high', which means start operation, and is not cleared even though next instruction is executed. So user should be careful to set FMUSR when executing sector erase, for no effect on other flash sectors.
15-9
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
PROGRAMMING TIP — Sector Erase
Case1. Erase one sector
•
•
ERASE_ONESECTOR:
SB1
LD FMUSR,#0A5H ; User program mode enable
LD FMSECH,#40H ; Set sector address 4000H,sector 128,
LD
LD
FMSECL,#00H ; among sector 0~511
FMCON,#10100001B ; Select erase mode enable & Start sector erase
ERASE_STOP: LD
SB0
FMUSR,#00H ; User program mode disable
Case2.Erase flash memory space from Sector (n) to Sector (n + m)
•
•
;;Pre-define the number of sector to erase
LD SecNumH,#00H
LD SecNumL,#128
LD R6,#01H
LD R7,#7DH
LD R2,SecNumH
LD R3,SecNumL
ERASE_LOOP: CALL SECTOR_ERASE
XOR P4,#11111111B
INCW RR2
LD SecNumH,R2
LD SecNumL,R3
DECW RR6
LD R8,R6
OR R8,R7
CP R8,#00H
JP NZ,ERASE_LOOP
•
•
; Set sector number
; Selection the sector128 ( base address 4000H )
; Set the sector range (m) to erase
; into High-byte(R6) and Low-byte(R7)
; Display ERASE_LOOP cycle
15-10
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
SECTOR_ERASE:
LD R12,SecNumH
LD R14,SecNumL
MULT RR12,#80H
MULT RR14,#80H
ADD R13,R14
NOCARRY:
ERASE_START:
LD R10,R13
LD R11,R15
SB1
LD FMUSR,#0A5H
LD FMSECH,R10
; Calculation the base address of a target sector
; The size of one sector is 128-bytes
; BTJRF FLAGS.7,NOCARRY
; INC R12
; User program mode enable
; Set sector address
LD
LD
FMSECL,R11
FMCON,#10100001B ; Select erase mode enable & Start sector erase
ERASE_STOP:
LD FMUSR,#00H ; User program mode disable
SB0
RET
15-11
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
PROGRAMMING
A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by
‘LDC’ instruction.
The program procedure in user program mode
1. Must erase target sectors before programming.
2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.
3. Set Flash Memory Control Register (FMCON) to “0101000XB”.
4. Set Flash Memory Sector Address Register (FMSECH and FMSECL) to the sector base address of destination address to write data.
5. Load a transmission data into a working register.
6. Load a flash memory upper address into upper register of pair working register.
7. Load a flash memory lower address into lower register of pair working register.
8. Load transmission data to flash memory location area on ‘LDC’ instruction by indirectly addressing mode
9. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
NOTE
In programming mode, it doesn’t care whether FMCON.0’s value is “0” or “1”.
15-12
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
Start
SB1
FMSECH High Address of Sector
FMSECL Low Address of Sector
R(n) High Address to Write
R(n+1) Low Address to Write
R(data) 8-bit Data
FMUSR #0A5H
FMCON #01010000B
LDC @RR(n),R(data)
FMUSR #00H
SB0
Finish 1-BYTE Writing
; Select Bank1
; Set Secotr Base Address
; Set Address and Data
; User Program Mode Enable
; Mode Select
; Write data at flash
; User Program Mode Disable
; Select Bank0
Figure 15-9. Byte Program Flowchart in a User Program Mode
15-13
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
Start
SB1
FMSECH
FMSECL
High Address of Sector
Low Address of Sector
R(n) High Address to Write
R(n+1) Low Address to Write
R(data) 8-bit Data
FMUSR #0A5H
FMCON #01010000B
LDC @RR(n),R(data)
NO
NO
Same Sector?
YES
Continuous address?
YES
Write again?
NO
FMUSR #00H
SB0
Finish Writing
; Select Bank0
YES
INC R(n+1)
YES
Different Data?
R(data) New 8-bit Data
NO
;; Update Data to Write
Figure 15-10. Program Flowchart in a User Program Mode
; Select Bank1
; Set Secotr Base Address
; Set Address and Data
; User Program Mode Enable
; Mode Select
; Write data at flash
; User Program Mode Disable
; User Program Mode Disable
;; Check Sector
;; Check Address
;; Increse Address
15-14
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
PROGRAMMING TIP — Programming
Case1. 1-Byte Programming
•
•
WR_BYTE: ; Write data “AAH” to destination address 4010H
SB1
LD
LD
LD
LD
LD
LD
FMUSR,#0A5H ; User program mode enable
FMCON,#01010000B ; Selection programming mode
FMSECH, #40H ; Set the base address of sector (4000H)
FMSECL, #00H
R9,#0AAH ; Load data “AA” to write
R10,#40H ; Load flash memory upper address into upper register of pair working
R11,#10H
; register
; Load flash memory lower address into lower register of pair working
@RR10,R9
; register
; Write data 'AAH' at flash memory location (4010H)
LD
LDC
LD
SB0
FMUSR,#00H ; User program mode disable
Case2. Programming in the same sector
•
•
WR_INSECTOR: ; RR10-->Address copy (R10 –high address,R11-low address)
LD R0,#40H
SB1
LD
LD
LD
LD
FMUSR,#0A5H ; User program mode enable
FMCON,#01010000B ; Selection programming mode and Start programming
FMSECH,#40H ; Set the base address of sector located in target address to write data
FMSECL,#00H ; The sector 128’s base address is 4000H.
LD
LD
LD
WR_BYTE:
LDC
INC
LD
SB0
R9,#33H ; Load data “33H” to write
R10,#40H ; Load flash memory upper address into upper register of pair working
R11,#40H
; register
; Load flash memory lower address into lower register of pair working
; register
@RR10,R9
R11
DJNZ R0,WR_BYTE
; Write data '33H' at flash memory location
; Reset address in the same sector by INC instruction
; Check whether the end address for programming reach 407FH or not.
FMUSR,#00H ; User Program mode disable
15-15
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
Case3. Programming to the flash memory space located in other sectors
•
•
WR_INSECTOR2:
LD
LD
SB1
R0,#40H
R1,#40H
LD FMUSR,#0A5H ; User program mode enable
LD FMCON,#01010000B ; Selection programming mode and Start programming
LD FMSECH,#01H ; Set the base address of sector located in target address to write data
LD FMSECL,#00H ; The sector 2’s base address is 100H
LD
LD
LD
R9,#0CCH ; Load data “CCH” to write
R10,#01H
R11,#40H
; Load flash memory upper address into upper register of pair working
; register
; Load flash memory lower address into lower register of pair working
; register
LD R0,#40H
WR_INSECTOR50:
LD
LD
FMSECH,#19H
FMSECL,#00H
; Set the base address of sector located in target address to write data
; The sector 50’s base address is 1900H
LD
LD
LD
R9,# 55H
R10,#19H
R11,#40H
; Load data “55H” to write
; Load flash memory upper address into upper register of pair working
; register
; Load flash memory lower address into lower register of pair working
; register
WR_INSECTOR128:
LD
LD
FMSECH,#40H
FMSECL,#00H
; Set the base address of sector located in target address to write data
; The sector 128’s base address is 4000H
LD
LD
LD
R9,#0A3H
R10,#40H
R11,#40H
; Load data “A3H” to write
; Load flash memory upper address into upper register of pair working
; register
; Load flash memory lower address into lower register of pair working
; register
WR_BYTE1:
LDC
INC
LD
SB0
@RR10,R9
R11
DJNZ R1,WR_BYTE1
; Write data 'A3H' at flash memory location
FMUSR,#00H ; User Program mode disable
•
•
WR_BYTE:
LDC @RR10,R9 ; Write data written by R9 at flash memory location
INC R11
DJNZ R0,WR_BYTE
RET
15-16
S3F80JB EMBEDDED FLASH MEMORY INTERFACE
READING
The read operation starts by ‘LDC’ instruction.
The program procedure in user program mode
1. Load a flash memory upper address into upper register of pair working register.
2. Load a flash memory lower address into lower register of pair working register.
3. Load receive data from flash memory location area on ‘LDC’ instruction by indirectly addressing mode
PROGRAMMING TIP — Reading
LOOP:
•
•
•
•
•
•
LD
LD
LDC
INC
CP
R2,#03H
R3,#00H
; Load flash memory’s upper address
; to upper register of pair working register
; Load flash memory’s lower address
; to lower register of pair working register
R0,@RR2 ; Read data from flash memory location
; (Between 300H and 3FFH)
R3
R3,#0FFH
15-17
EMBEDDED FLASH MEMORY INTERFACE S3F80JB
HARD LOCK PROTECTION
User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area.
This protection can be released by the chip erase execution in the tool program mode. In terms of user program mode, the procedure of setting Hard Lock Protection is following that. In tool mode, the manufacturer of serial tool writer could support Hardware Protection. Please refer to the manual of serial program writer tool provided by the manufacturer.
The program procedure in user program mode
1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.
2. Set Flash Memory Control Register (FMCON) to “01100001B”.
3. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
PROGRAMMING TIP — Hard Lock Protection
•
•
SB1
LD
•
•
LD
LD
SB0
FMUSR,#0A5H ; User program mode enable
FMCON,#01100001B ; Select Hard Lock Mode and Start protection
FMUSR,#00H ; User program mode disable
15-18
S3F80JB LOW VOLTAGE DETECTOR
16
LOW VOLTAGE DETECTOR
OVERVIEW
The S3F80JB micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and
LVD_FLAG detection of power voltage. The S3F80JB has two options in LVD and LVD_FLAG voltage level according to the operating frequency to be set by smart option (Refer to the page 2-4).
Operating Frequency 4MHz:
•
Low voltage detect level for Backup Mode and Reset (LVD): 1.9V (Typ)
± 200mV
•
Low voltage detect level for Flash Flag Bit (LVD_FLAG): 2.15V (Typ)
± 200mV
Operating Frequency 8MHz:
•
Low voltage detect level for Backup Mode and Reset (LVD): 2.15V (Typ)
± 200mV
•
Low voltage detect level for Flash Flag Bit (LVD_FLAG): 2.3V (Typ)
± 200mV
After power-on, LVD block is always enabled. LVD block is only disable when executed STOP instruction with a smart option setting. The LVD block of S3F80JB consists of two comparators and a resistor string. One of comparators is for LVD detection, and the other is for LVD_FLAG detection.
LVD
LVD circuit supplies two operating modes by one comparator: back-up mode input and system reset input. The
S3F80JB can enter the back-up mode and generate the reset signal by the LVD level (note1) detection using
LVD circuit. When LVD circuit detects the LVD level (note1) in falling power, S3F80JB enters the Back-up mode.
Back-up mode input automatically creates a chip stop state. When LVD circuit detects the LVD level (note1) in rising power, the system reset occurs. When the reset pin is at a high state and the LVD circuit detects rising edge of V
DD
on the point V
LVD
, the reset pulse generator makes a reset pulse, and system reset occurs. This reset by LVD circuit is one of the S3F80JB reset sources. (Refer to the page 8-3 for more.)
LVD FLAG
The other comparator’s output makes LVD indicator flag bit ‘1’ or ‘0’. That is used to indicate low voltage level
(note2). When the power voltage is below the LVD_FLAG level, the bit 0 of LVDCON register is set ‘1’. When the power voltage is above the LVD_FLAG level, the bit 0 of LVDCON register is set ‘0’ automatically. LVDCON.0 can be used flag bit to indicate low battery in IR application or others.
16-1
16-2
LOW VOLTAGE DETECTOR S3F80JB
NOTES
1. When smart option bit is set “1”, operating frequency is selected 8MHz and LVD voltage level is 2.3V.
On the other hand, when smart option bit is set “0”, operating frequency is selected 4MHz and LVD voltage level is 2.15V.
2. When smart option bit is set “1”, operating frequency is selected 8MHz and LVD_FLAG voltage level is 2.15V. On the other hand, when smart option bit is set “0”, operating frequency is selected 4MHz and LVD_FLAG voltage level is 1.9V.
3. A term of LVD is a symbol of parameter that means ‘Low Level Detect Voltage for Back-Up Mode’.
4. A term of LVD_FLAG is a symbol of parameter that means ‘Low Level Detect Voltage for Flag
Indicator’.
5. In case of 8MHz operating frequency, the voltage gap between LVD and LVD_FLAG is 150mV. In case of 4MHz operating frequency, the voltage gap between LVD and LVD_ FLAG is 250mV.
IPOR/LVD Control Bit
(smart option[7]@03FH)
STOP
Resistor String
Comparator
Bias
V DIV
V DIV_Flag
V IN
Comparator
V REF
Bias
BANDGAP
LVD
(BackupMode
/Reset)
LVDCON.0
(LVD Flag Bit)
Figure 16-1. Low Voltage Detect (LVD) Block Diagram
S3F80JB LOW VOLTAGE DETECTOR
LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON)
LVDCON.0 is used flag bit to indicate low battery in IR application or others. When LVD circuit detects
LVD_FLAG, LVDCON.0 flag bit is set automatically. The reset value of LVDCON is #00H.
MSB .7
Low Voltage Detect Control Register (LVDCON)
E0H, Set1, Bank 1, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for S3F80J9/S3F80J5
LVD Indicator Flag Bit:
0 = V
DD
1 = V
DD
> LVD_Flag Voltage
< LVD_Flag Voltage
NOTE: LVD_Flag Voltage is 2.3V at 8MHz and 2.15V at 4MHz.
Figure 16-2. Low Voltage Detect Control Register (LVDCON)
16-3
S3F80JB ELECTRICAL DATA (4MHz)
17
ELECTRICAL DATA – 4MHz
OVERVIEW
In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged in the following order:
— Absolute Maximum Ratings
— Characteristics of Low Voltage Detect Circuit
— Data Retention Supply Voltage in Stop Mode
— Stop Mode Release Timing When Initiated by an External Interrupt
— Stop Mode Release Timing When Initiated by a Reset
— Stop Mode Release Timing When Initiated by a LVD
— A.C. Electrical Characteristics
— Input Timing for External Interrupts
— Input Timing for Reset
— Oscillation Stabilization Time
— Operating Voltage Range
— A.C. Electrical Characteristics for Internal Flash ROM
17-1
ELECTRICAL DATA (4MHz) S3F80JB
Table 17-1. Absolute Maximum Ratings
(T
A
= 25
°C)
Parameter Symbol
Supply Voltage V
DD
Input Voltage
Output Voltage
Output Current High
V
IN
V
O
I
OH
Conditions
All output pins
One I/O pin active
–
–
Output Current Low I
OL
All I/O pins active
One I/O pin active
All I/O pins active
Operating
Temperature
Storage
Temperature
Electrostatic
Discharge
T
V
T
A
STG
ESD
–
–
Rating Unit
– 0.3 to + 3.8
– 0.3 to V
– 0.3 to V
DD
+ 0.3
DD
+ 0.3
– 18
– 60
+ 30
+ 150
– 25 to + 85
– 65 to + 150
V
V
V mA mA
°C
°C
MM 200
Table 17-2. D.C. Electrical Characteristics
(T
A
= – 25 °C to + 85 °C, V
DD
= 1.7 V to 3.6 V)
Parameter Symbol
Operating Voltage V
DD
F
OSC
= 4 MHz
Input High Voltage
Input Low Voltage
V
IH1
V
IH2
V
IH3
All input pins except V nRESET
X
IN
IH2
and V
IH3
All input pins except V
IL2 and V
IL3
V
IL1
V
IL2
V
IL3
Output High
Voltage
V
OH1
X
IN
V
DD
= 2.1 V, I
OH
= – 6mA
Port 3.1 only
V
OH2
V
OH3
V
DD
= 2.1 V, I
OH
= – 2.2mA
P3.0 and P2.0-2.3
V
DD
= 2.35 V, I
OH
= – 1mA
Port0, Port1, P2.4-2.7, P3.4-3.5 and Port4
Typ Unit
1.7 – 3.6 V
0.8 V
DD
0.85 V
DD
V
DD
– 0.3
– V
V
V
DD
DD
DD
0.2 V
DD
V
V
V
DD
– 1.0
V
DD –
1.0
V
DD
–
1.0
0.3
V
– –
17-2
S3F80JB ELECTRICAL DATA (4MHz)
Table 17-2. D.C. Electrical Characteristics (Continued)
(T
A
= – 25 °C to + 85 °C, V
DD
= 1.7 V to 3.6 V)
Parameter Symbol
Output Low
Voltage
V
OL1
V
DD
= 2.1 V, I
OL
Port 3.1 only
= 12mA
V
OL2
Input High
Leakage Current
V
I
OL3
LIH1
V
DD
= 2.1 V, I
OL
= 5mA
P3.0 and P2.0-2.3
V
DD
= 2.35 V, I
OH
= – 1mA
Port0, Port1, P2.4-2.7, P3.4-3.5 and
Port4
V
IN
= V
DD
All input pins except I
LIH2 and X
OUT
Input Low
Leakage Current
I
LIH2
I
LIL1
V
IN
= V
DD ,
X
IN
V
IN
= 0 V
All input pins except I
LIL2 and X
OUT
Output High
Leakage Current
Output Low
Leakage Current
Pull-Up
Resistors
Feed Back
Resistor
I
LIL2
I
LOH
I
LOL
R
R
R
L1
L2
FD
V
IN
= 0 V, X
IN
V
OUT
= V
DD
All output pins
V
OUT
= 0 V
All output pins
V
IN
= 0 V, V
DD
= 2.1 V
T
A
= 25
°
C, Ports 0–4
V
IN
= 0 V, V
DD
= 2.1 V
T
A
= 25
°
C, nRESET
V
IN
T
A
= V
DD
= 25
°
, V
DD
= 2.1 V
C, X
IN
– 0.4 0.5 V
– – 1
µA
20
20
– – 1
µA
40 90 150 k
200 700 1200 k
500 900 1500 k
Ω
Ω
Ω
17-3
ELECTRICAL DATA (4MHz) S3F80JB
Table 17-2. D.C. Electrical Characteristics (Continued)
(T
A
= – 25 °C to + 85 °C, V
DD
= 1.7 V to 3.6 V)
Parameter Symbol
Supply Current
(note)
I
DD1
Operating Mode
V
DD
= 3.6 V
4 MHz crystal
I
DD2
Idle Mode
V
DD
=3.6 V
4 MHz crystal
I
DD3
LVD OFF, V
DD
= 3.6 V
Stop Mode
LVD ON, V
DD
= 3.6 V
–
–
–
–
5
1.0
9
2.5 mA
10 20
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
(T
A
= – 25 °C to + 85 °C)
Table 17-3. Characteristics of Low Voltage Detect Circuit
Hysteresys voltage of LVD
(Slew Rate of LVD)
Low level detect voltage for back-up mode
Low level detect voltage for flag indicator
∆V
LVD_FLAG –
NOTE: The voltage gap between LVD and LVD FLAG is 250mV.
1.95 2.15 2.35 V
(T
A
= – 25
°C to + 85 °C)
Table 17-4. Data Retention Supply Voltage in Stop Mode
–
Data retention supply voltage
Data retention supply current
V
DDDR
I
DDDR
V
DDDR
= 1.5 V
Stop Mode
1.5 – 3.6 V
– – 1 µA
17-4
S3F80JB ELECTRICAL DATA (4MHz)
TYPICAL VOL vs IOL(VDD=3.3V) TYPICAL VOL VS VDD(IOL=12mA)
1.00
0.80
0.60
0.40
0.20
0.00
0
85°C
25°C
−25°C
300
250
200
150
100
50
10 20 30 40 50 60
IOL(mA)
70 80
0
1.800V
2.400V
3.000V
VDD(V)
Figure 17-1. Typical Low-Side Driver (Sink) Characteristics (P3.1 only)
85°C
25°C
−25°C
3.600V
TYPICAL VOL vs IOL(VDD=3.3V) TYPICAL VOL VS VDD(IOL=5mA)
1.00
250
0.80
85°C
25°C
−25°C 200
0.60
150
0.40
100
0.20
50
0.00
0 10 20
IOL(mA)
30 40
0
1.800V
2.400V
3.000V
VDD(V)
Figure 17-2. Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)
3.600V
85°C
25°C
−25°C
NOTE: Figure 17-1 and 17-2 are characterized and not tested on each device.
17-5
ELECTRICAL DATA (4MHz) S3F80JB
TYPICAL VOL vs IOL(VDD=3.3V) TYPICAL VOL VS VDD(IOL=2mA)
1.00
0.80
85°C
25°C
−25°C
160
140
85°C
25°C
−25°C
0.60
0.40
120
100
80
60
40
0.20
20
0.00
0 5
IOL(mA)
10 15
0
1.800V
2.400V
3.000V
VDD(V)
3.600V
Figure 17-3. Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
TYPICAL VDD-VOH(VDD=3.3V) TYPICAL VDD-VOH VS VDD(IOH=
−6mA)
85°C
25°C
−25°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8V
5 10
IOH(mA)
15 20 25 2.3
2.8
VDD(V)
3.3
Figure 17-4. Typical High-Side Driver (Source) Characteristics (P3.1 only)
85°C
25°C
−25°C
3.8V
NOTE: Figure 17-3 and 17-4 are characterized and not tested on each device.
17-6
S3F80JB ELECTRICAL DATA (4MHz)
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
TYPICAL VDD-VOH(VDD=3.3V)
85°C
25°C
−25°C
2 4 6
IOH(mA)
8 10 12
TYPICAL VDD-VOH VS VDD(IOH=
−2.2mA)
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8V
2.3
2.8
VDD(V)
3.3
85°C
25°C
−25°C
3.8
Figure 17-5. Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)
TYPICAL VDD-VOH(VDD=3.3V)
TYPICAL VDD-VOH VS VDD(IOH=
−1mA)
1.20
1.00
85°C
25°C
−25°C
0.45
0.4
0.35
0.3
85°C
25°C
−25°C
0.80
0.60
0.40
0.20
0.25
0.2
0.15
0.1
0.05
0
1.8V
0.00
0 1 2 3
IOH(mA)
4 5 6 2.3
2.8
VDD(V)
3.3
3.8
Figure 17-6. Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
NOTE: Figure 17-5 and 17-6 are characterized and not tested on each device.
17-7
ELECTRICAL DATA (4MHz) S3F80JB
V DD
EXT INT
Stop Mode
Data Retention Mode
V DDDR
Idle Mode
(Basic Timer Active)
~ ~
~ ~
Execution of
STOP Instrction
Normal Operating Mode
0.2V
DD
0.8V
DD t
WAIT
Figure 17-7. Stop Mode Release Timing When Initiated by an External Interrupt
V DD
~ ~
~ ~ Stop Mode
Execution of
STOP Instrction
Reset
Occur
Oscillation Stabilization Time
Normal
Operating
Mode nRESET
0.2V
DD
0.85V
DD t WAIT
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
Figure 17-8. Stop Mode Release Timing When Initiated by a Reset
17-8
S3F80JB ELECTRICAL DATA (4MHz)
Stop Mode
Reset
Occur
Oscillation Stabilization Time
Normal Operating Mode
Back-up Mode
V DD
V
LVD
~ ~
~ ~
Execution of
STOP Instrction
V
DDDR
Data Retention Time t WAIT
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
Figure 17-9. Stop Mode Release Timing When Initiated by a LVD
Table 17-5. Input/Output Capacitance
(T
A
= – 25
°C to + 85 °C)
Parameter Symbol
Input
Capacitance
Output
Capacitance
C
IN
C
OUT f = 1 MHz
V
DD
= 0 V, unmeasured pins are connected to V
SS
I/O Capacitance C
IO
Table 17-6. A.C. Electrical Characteristics
(T
A
= – 25
°C to + 85 °C)
Parameter Symbol
Interrupt Input
High, Low Width nRESET Input
Low Width t
INTH
, t
INTL t
RSL
P0.0–P0.7, P2.0–P2.7
V
DD
= 3.6 V
Input
V
DD = 3.6 V
200 300 – ns
1000 – –
17-9
ELECTRICAL DATA (4MHz) S3F80JB
0.2 V DD t
INTL t
INTH
0.8 V DD
0.2 V DD
0.8 V DD
NOTE: The unit t CPU means one CPU clock period.
Figure 17-10. Input Timing for External Interrupts (Port 0 and Port 2)
V DD nRESET
Normal Operating Mode
Reset
Occur
Back-up Mode
(Stop Mode)
Oscillation Stabilization Time
Normal
Operating
Mode t WAIT
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
Figure 17-11. Input Timing for Reset (nRESET Pin)
17-10
S3F80JB
Table 17-7. Oscillation Characteristics
(T
A
= – 25
°C to + 85 °C)
Crystal
X
IN
CPU clock oscillation frequency
C1
X
OUT
C2
Ceramic
X
IN
CPU clock oscillation frequency
C1
X
OUT
C2
External Clock
External
Clock
X IN
Open Pin
X OUT
X
IN
input frequency
ELECTRICAL DATA (4MHz)
17-11
ELECTRICAL DATA (4MHz) S3F80JB
Table 17-8. Oscillation Stabilization Time
(T
A
= – 25
°C to + 85 °C, V
DD
= 3.6 V)
Main crystal f
OSC
> 400 kHz
Main ceramic Oscillation stabilization occurs when V
DD is equal to the minimum oscillator voltage range.
External clock
(main system)
X
IN
input High and Low width (t
XH
, t
XL
)
Oscillator stabilization wait time t
WAIT
when released by a reset
(1) t
WAIT
when released by an interrupt (2)
– 2
16
/f
OSC
– ms
NOTES:
1. f
OSC
is the oscillator frequency.
2. The duration of the oscillation stabilization time (t
WAIT
) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.
17-12
S3F80JB ELECTRICAL DATA (4MHz)
Minimun Instruction
Clock
2 MHz
1.5MHz
1MHz
500 kHz
250 kHz
1kHz f OSC
(Main Oscillator Frequency)
A
1 2 3 4
Supply Voltage (V)
5 6
8 MHz
6 MHz
4 MHz
2 MHz
7
1 MHz
400 kHz
Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16)
A: 1.7 V, 4 MHz
Figure 17-12. Operating Voltage Range of S3F80J9
Table 17-9. AC Electrical Characteristics for Internal Flash ROM
(T
A
= – 25
°C to + 85 °C)
Flash Write/Erase Voltage
Flash Read Voltage
Programming Time (1)
Sector Erasing Time (2)
Chip Erasing Time (3)
Data Access Time
Number of Writing/Erasing
Data Retention
Fwe
Frv
Ftp2
Ft
RS
FNwe
Ftdr
V
DD
= 2.0 V
–
–
1.95
1.7
–
–
3.6 V
3.6 V
– 250 – nS
10,000
10
–
–
NOTES:
1. The programming time is the time during which one byte (8-bit) is programmed.
2. The Sector erasing time is the time during which all 128-bytes of one sector block is erased.
3. In the case of S3F80J9, the chip erasing is available in Tool Program Mode only.
–
–
Times
Years
17-13
S3F80JB ELECTRICAL DATA (8MHz)
18
ELECTRICAL DATA – 8MHZ
OVERVIEW
In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged in the following order:
— Absolute Maximum Ratings
— Characteristics of Low Voltage Detect Circuit
— Data Retention Supply Voltage in Stop Mode
— Typical Low-Side Driver (Sink) Characteristics
— Typical High-Side Driver (Source) Characteristics
— Stop Mode Release Timing When Initiated by an External Interrupt
— Stop Mode Release Timing When Initiated by a Reset
— Stop Mode Release Timing When Initiated by a LVD
— A.C. Electrical Characteristics
— Input Timing for External Interrupts
— Input Timing for Reset
— Comparator Electrical Characteristics
— Oscillation Stabilization Time
— Operating Voltage Range
— A.C. Electrical Characteristics for Internal Flash ROM
18-1
ELECTRICAL DATA (8MHz) S3F80JB
Table 18-1. Absolute Maximum Ratings
(T
A
= 25
°C)
Parameter Symbol
Supply Voltage V
DD
Input Voltage
Output Voltage
Output Current High
V
IN
V
O
I
OH
Conditions
All output pins
One I/O pin active
–
–
Output Current Low I
OL
All I/O pins active
One I/O pin active
All I/O pins active
Operating
Temperature
Storage
Temperature
Electrostatic discharge
T
V
T
A
STG
ESD
–
–
Rating Unit
– 0.3 to + 3.8
– 0.3 to V
– 0.3 to V
DD
+ 0.3
DD
+ 0.3
– 18
– 60
+ 30
+ 150
– 25 to + 85
– 65 to + 150
V
V
V mA mA
°C
°C
MM 200
Table 18-2. D.C. Electrical Characteristics
(T
A
= – 25 °C to + 85 °C, V
DD
= 1.95 V to 3.6 V)
Parameter Symbol
Operating Voltage V
DD
F
OSC
= 8 MHz
Input High Voltage
Input Low Voltage
V
IH1
V
IH2
V
IH3
All input pins except V nRESET
X
IN
IH2
and V
IH3
All input pins except V
IL2 and V
IL3
V
IL1
V
IL2
V
IL3
Output High
Voltage
V
OH1
X
IN
V
DD
= 2.35 V, I
OH
= – 6mA
Port 3.1 only
V
OH2
V
OH3
V
DD
= 2.35 V, I
OH
= – 2.2mA
P3.0 and P2.0-2.3
V
DD
= 2.35 V, I
OH
= – 1mA
Port0, Port1, P2.4-2.7, P3.4-3.5 and Port4
Typ Unit
1.95 – 3.6 V
0.8 V
DD
0.85 V
DD
V
DD
– 0.3
– V
V
V
DD
DD
DD
0.2 V
DD
V
V
V
DD
– 0.7
V
DD –
0.7
V
DD
–
1.0
0.3
V
– –
18-2
S3F80JB ELECTRICAL DATA (8MHz)
Table 18-2. D.C. Electrical Characteristics (Continued)
(T
A
= – 25 °C to + 85 °C, V
DD
= 1.95
V to 3.6 V)
Parameter Symbol
Output Low
Voltage
V
OL1
V
DD
= 2.35 V, I
OL
Port 3.1 only
= 12mA
V
OL2
V
OL3
V
DD
= 2.35 V, I
OL
= 5mA
P3.0 and P2.0-2.3
V
DD
= 2.35 V, I
OL
= 2mA
Port0, Port1, P2.4-2.7, P3.4-3.5 and Port4
Input High
Leakage Current
I
LIH1
Input Low
Leakage Current
Output High
Leakage Current
Output Low
Leakage Current
I
I
LOH
I
I
I
LIH2
LIL1
LIL2
LOL
V
IN
= V
DD
All input pins except I
LIH2 and
X
OUT
V
IN
= V
DD ,
X
IN
V
IN
= 0 V
All input pins except I
LIL2 and
X
OUT
V
IN
= 0 V, X
IN
V
OUT
= V
DD
All output pins
V
OUT
= 0 V
All output pins
Pull-Up Resistors
Feedback
Resistor
R
L1
R
R
L2 fd
V
IN
= 0 V, V
DD
= 2.35 V
T
A
= 25
°
C, Ports 0–4
V
IN
= 0 V, V
DD
= 2.35 V
T
A
= 25
°
C, nRESET
V
IN
= V
DD
, V
DD
=2.35V
T
A
= 25
°
C, X
IN
– 0.4 0.5 V
0.4 0.5
– – 1
µA
20
20
– – 1
µA
44 70 95 k
200 500 1000 k
300 700 1500 k
Ω
Ω
Ω
18-3
ELECTRICAL DATA (8MHz) S3F80JB
Table 18-2. D.C. Electrical Characteristics (Continued)
(T
A
= – 25 °C to + 85 °C, V
DD
= 1.95 V to 3.6 V)
Parameter Symbol
Supply Current
(note)
I
DD1
Operating Mode
V
DD
= 3.6 V
8 MHz crystal
I
DD2
Idle Mode
V
DD
=3.6 V
8 MHz crystal
I
DD3
LVD OFF, V
DD
= 3.6 V
Stop Mode
LVD ON, V
DD
= 3.6 V
–
–
–
–
5
1.0
9
2.5 mA
1 6
10 20 uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
(T
A
= – 25 °C to + 85 °C)
Table 18-3. Characteristics of Low Voltage Detect Circuit
Hysteresis Voltage of LVD
(Slew Rate of LVD)
Low Level Detect Voltage
For Back-Up Mode
Low Level Detect Voltage
For Flag Indicator
∆V
NOTE: The voltage gap between LVD and LVD FLAG is 150mV.
100 mV
2.1 V
(T
A
= – 25
°C to + 85 °C)
Table 18-4. Data Retention Supply Voltage in Stop Mode
Data Retention Supply
Voltage
Data Retention Supply
Current
V
I
DDDR
DDDR
–
V
DDDR
= 1.5 V
Stop Mode
1.5 – 3.6 V
18-4
S3F80JB ELECTRICAL DATA (8MHz)
1.00
0.80
0.60
0.40
0.20
0.00
0
TYPICAL VOL vs IOL(VDD=3.3V) TYPICAL VOL VS VDD(IOL=12mA)
85°C
25°C
−25°C
300
250
200
150
100
50
0
1.800V
10 20 30 40
IOL(mA)
50 60 70 80
2.400V
3.000V
VDD(V)
Figure 18-1. Typical Low-Side Driver (Sink) Characteristics (P3.1 only)
3.600V
85°C
25°C
−25°C
TYPICAL VOL vs IOL(VDD=3.3V)
TYPICAL VOL VS VDD(IOL=5mA)
1.00
250
0.80
0.60
0.40
0.20
85°C
25°C
−25°C
200
150
100
50
0.00
0 10 20
IOL(mA)
30 40
0
1.800V
2.400V
3.000V
VDD(V)
Figure 18-2. Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)
3.600V
85°C
25°C
−25°C
NOTE: Figure 18-1 and 18-2 are characterized and not tested on each device.
18-5
ELECTRICAL DATA (8MHz) S3F80JB
TYPICAL VOL vs IOL(VDD=3.3V) TYPICAL VOL VS VDD(IOL=12mA)
1.00
0.80
85°C
25°C
−25°C
300
250
85°C
25°C
−25°C
0.60
200
150
0.40
100
0.20
50
0.00
0 10 20 30 40
IOL(mA)
50 60 70 80
0
1.800V
2.400V
3.000V
VDD(V)
3.600V
Figure 18-3. Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
TYPICAL VDD-VOH(VDD=3.3V) TYPICAL VDD-VOH VS VDD(IOH=
−6mA)
85°C
25°C
−25°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5 10 15
IOH(mA)
20 25
0
1.8V
2.3
2.8
VDD(V)
3.3
Figure 18-4. Typical High-Side Driver (Source) Characteristics (P3.1 only)
85°C
25°C
−25°C
3.8V
NOTE: Figure 18-3 and 18-4 are characterized and not tested on each device.
18-6
S3F80JB ELECTRICAL DATA (8MHz)
TYPICAL VDD-VOH(VDD=3.3V)
1.20
25 °C
-25 °C
1.00
85°C
25°C
−25°C
0.80
0.6
0.5
0.4
TYPICAL VDD-VOH VS VDD(IOH=
−2.2mA)
0.60
0.40
0.20
0.00
0
0.3
0.2
0.1
2 4 6
IOH(mA)
8 10 12
0
1.8V
2.3
2.8
VDD(V)
3.3
Figure 18-5. Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)
85°C
25°C
−25°C
3.8
TYPICAL VDD-VOH(VDD=3.3V) TYPICAL VDD-VOH VS VDD(IOH=
−1mA)
1.20
1.00
85°C
25°C
−25°C
0.45
0.4
85°C
25°C
−25°C
0.80
0.60
0.35
0.3
0.25
0.2
0.40
0.20
0.15
0.1
0.05
0.00
0 1 2 3
IOH(mA)
4 5 6
0
1.8V
2.3
2.8
VDD(V)
3.3
3.8
Figure 18-6. Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
NOTE: Figure 18-5 and 18-6 are characterized and not tested on each device.
18-7
ELECTRICAL DATA (8MHz) S3F80JB
V DD
EXT INT
Stop Mode
Data Retention Mode
V DDDR
Idle Mode
(Basic Timer Active)
~ ~
~ ~
Execution of
STOP Instrction
Normal Operating Mode
0.2V
DD
0.8V
DD t
WAIT
Figure 18-7. Stop Mode Release Timing When Initiated by an External Interrupt
V DD
~ ~
~ ~ Stop Mode
Execution of
STOP Instrction
Reset
Occur
Oscillation Stabilization Time
Normal
Operating
Mode nRESET
0.2V
DD
0.85V
DD t WAIT
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
Figure 18-8. Stop Mode Release Timing When Initiated by a Reset
18-8
S3F80JB ELECTRICAL DATA (8MHz)
Stop Mode
Reset
Occur
Oscillation Stabilization Time
Normal Operating Mode
Back-up Mode
V DD
V
LVD
~ ~
~ ~
Execution of
STOP Instrction
V
DDDR
Data Retention Time t WAIT
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
Figure 18-9. Stop Mode Release Timing When Initiated by a LVD
Table 18-5. Input/Output Capacitance
(T
A
= – 25
°C to + 85 °C)
Parameter Symbol
Input
Capacitance
Output
Capacitance
C
IN
C
OUT f = 1 MHz
V
DD
= 0 V, unmeasured pins are connected to V
SS
I/O Capacitance C
IO
Table 18-6. A.C. Electrical Characteristics
(T
A
= – 25
°C to + 85 °C)
Parameter Symbol
Interrupt Input
High, Low Width nRESET Input
Low Width t
INTH
, t
INTL t
RSL
P0.0–P0.7, P2.0–P2.7
V
DD
= 3.6 V
Input
V
DD = 3.6 V
200 300 – ns
1000 – –
18-9
ELECTRICAL DATA (8MHz) S3F80JB
0.2 V DD t
INTL t
INTH
0.8 V DD
0.2 V DD
0.8 V DD
NOTE: The unit t CPU means one CPU clock period.
Figure 18-10. Input Timing for External Interrupts (Port 0 and Port 2)
V DD nRESET
Normal Operating Mode
Reset
Occur
Back-up Mode
(Stop Mode)
Oscillation Stabilization Time
Normal
Operating
Mode t WAIT
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
Figure 18-11. Input Timing for Reset (nRESET Pin)
18-10
S3F80JB ELECTRICAL DATA (8MHz)
Table 18-7. Comparator Electrical Characteristics
(T
A
= –25
°
C to + 85
°
C, V
DD
= 1.95 V to 3.6 V, V
SS
= 0 V)
– 0 Input voltage range –
Reference voltage range
Input leakage current
V
REF
Input voltage Internal V
CIN1
Accuracy External
CIN2
I
CIN
, I
REF
–
Table 18-8. Oscillation Characteristics
(T
A
= –25
°C to + 85 °C)
Crystal
X
IN
CPU clock oscillation frequency
C1
X
OUT
C2
Ceramic
X
IN
CPU clock oscillation frequency
C1
X
OUT
C2
External Clock
External
Clock
X IN
Open Pin
X OUT
X
IN
input frequency
V
DD
V
V mV mV
18-11
ELECTRICAL DATA (8MHz) S3F80JB
Table 18-9. Oscillation Stabilization Time
(T
A
= –25
°C to + 85 °C, V
DD
= 3.6 V)
Main crystal f
OSC
> 400 kHz
Main ceramic Oscillation stabilization occurs when V
DD is equal to the minimum oscillator voltage range.
External clock
(main system)
X
IN
input High and Low width (t
XH
, t
XL
)
Oscillator stabilization wait time t
WAIT
when released by a reset
(1) t
WAIT
when released by an interrupt (2)
– 2
16
/f
OSC
– ms
NOTES:
1. f
OSC
is the oscillator frequency.
2. The duration of the oscillation stabilization time (t
WAIT
) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.
18-12
S3F80JB ELECTRICAL DATA (8MHz)
Minimun Instruction
Clock
2 MHz
1.5MHz
1MHz
500 kHz
250 kHz
1kHz f OSC
(Main Oscillator Frequency)
A
1 2 3 4
Supply Voltage (V)
5 6
8 MHz
6 MHz
4 MHz
2 MHz
7
1 MHz
400 kHz
Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16)
A: 1.95 V, 8 MHz
Figure 18-12. Operating Voltage Range of S3F80JB
Table 18-10. AC Electrical Characteristics for Internal Flash ROM
(T
A
= –25
°C to + 85 °C)
Flash Erase/Write/Read Voltage Fewrv
Programming Time
(1)
Sector Erasing Time (2)
Chip Erasing Time
(3)
Data Access Time
Number of Writing/Erasing
Data Retention
Ftp2
Ft
RS
FNwe
Ftdr
V
DD
V
DD
= 2.0 V
–
–
1.95 3.3 3.6 V
– 250 – nS
10,000
10
–
–
1. The programming time is the time during which one byte (8-bit) is programmed.
2. The Sector erasing time is the time during which all 128-bytes of one sector block is erased.
3. In the case of S3F80JB, the chip erasing is available in Tool Program Mode only.
–
–
Times
Years
18-13
ELECTRICAL DATA (8MHz)
NOTES
S3F80JB
18-14
19
MECHANICAL DATA
OVERVIEW
The S3F80JB microcontroller is currently available in a 32-pin SOP and 44-pin QFP package.
0-8
#32 #17
32-SOP-450A
#16
0.25
+ 0.10
- 0.05
#1
20.30 MAX
19.90 ± 0.20
0.10 MAX
(0.43) 0.40
± 0.10
1.27
NOTE: Dimensions are in millimeters.
Figure 19-1. 32-Pin SOP Package Dimension
19-1
MECHANICAL DATA
13.20
± 0.30
10.00 ± 0.20
0-8
0.15
+ 0.10
- 0.05
44-QFP-1010B
0.10 MAX
#44
0.80
#1
0.35
+ 0.10
- 0.05
0.15 MAX
(1.00)
NOTE: Dimensions are in millimeters.
Figure 19-2. 44-Pin QFP Package Dimension
0.05 MIN
2.05 ± 0.10
2.30 MAX
S3F80JB
19-2
S3F80JB DEVELOPMENT TOOLS DATA
20
DEVELOPMENT TOOLS DATA
OVERVIEW
Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator,
OPENice-i500, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options.
TARGET BOARDS
Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables and adapters are included on the device-specific target board. TB80JB is a specific target board for the S3F80JB development.
PROGRAMMING SOCKET ADAPTER
When you program S3F80JB’s flash memory by using an emulator or OTP/MTP writer, you need a specific writer socket adapter for S3F80JB. In case of S3F80JB, there are SA-44QFP and SA-32SOP socket adapters for it’s
44-QFP and 32-SOP packages respectively. (Refer to Flash Application Notes)
20-1
DEVELOPMENT TOOLS DATA S3F80JB
TB80JB TARGET BOARD
The TB80JB target board is used for the S3F80JB microcontrollers. It is supported by OPENice-i500 (In-Circuit
Emulator).
CABLEs For CONNECTION
To Open-ice500
TB80JB Rev1
S1
To User_Vcc
Off On
U2
RESET
JP10
74HC11 nRESET
IDLE STOP
+ + +
Y1
25
BOARD_CLK
MDS_CLK 4
VDDMCU
VDD_3.3
VDD_REG
JP8
JP5
JP11
JP6
JP1
+5V
+3V
TA-SAM 8
CABLE To Connect
Between Target Board And
Open-ice Connect Board
J1A
USER_MODE
JP2
TEST_MODE
1
U1
144 QFP
S3E80JB
EVA Chip
SMDS2
JP3
SMDS2+
JP1
MAIN_MODE
1
J2
50
EVA_MODE
J3
1
1
25 26
Figure 20-1. TB80JB Target Board Configuration
NOTE
1. S3E80JB should be supplied 3.3V. So jumpers and switches in both OPENice-i500 connect board and target board of S3E80JB (TB80JB) should be set as like this description. In that case, regulator in TB80JB is not used.
20-2
S3F80JB DEVELOPMENT TOOLS DATA
Table 20-1. Components Consisting of S3F80JB Target Board
Block Symbols
OPEN-i500 Connector J1A Connection debugging signals between emulator and 80JB
EVA target board.
TEST Board Connector
RESET Block
POWER Block
J2
RESET Push Switch Generation low active reset signal of 80JB EVA-chip
VCC, GND, S, nRESET LED
Connection between target board and remocon application board.
Generation 3.3V with 5V power inserted from external power source or open –ice (recommend).
STOP/IDLE Display
FLASH Serial Writing
IDLE, STOP LED
J3
Indicate the status of STOP or IDLE
Signal for writing flash ROM in tool mode. Don’t use these in user mode.
MODE Selection JP1, JP2 Selection of Flash tool/user mode and Eva/Main-chip mode
20-3
DEVELOPMENT TOOLS DATA S3F80JB
Table 20-2. Default Setting of the Jumper in S3F80JB Target Board
S1
JP1
JP2
JP3
JP6
JP8
Target board power source Open-ice power
Target board mode selection H: Main-Mode
Operation Mode H: User Mode
MDS version SMDS2
L: EVA-Mode
L: Test-Mode
SMDS2+
Board peripheral power connection connection
When supplied 5V in target board, generation of 3.3V using regulator.
In case of selection 3.3V between open-ice powers, connect core without a step of regulation.
80JB V
DD
power connection 80JB V
DD
power connection
In case of selection 5V between open-ice powers, connect regulator to generate 3.3V
Join 1-2
Join 2-3
Join 1-2
Join 2-3
Connect
Join 2-3
Connect
JP10 Clock source selection connection
When using the internal clock source which is generated from OPENice-i500, join connector 2-3 and 4-5 pin. If user wants to use the external clock source like a crystal, user should change the jumper setting from 1-2 to 5-6 and connect Y1 to an external clock source.
Connection between regulator out voltage and 80JB’s
Power V
DD
when using the regulator. When debugging with Openice-i500, JP11 don’t need to be connect.
SW2 Smart option at address 3EH Dip switch for smart option. These 1byte are mapped address 3EH for special function. Refer to the page 2-3.
SW3 Smart option at address 3FH Dip switch for smart option. These 1byte are mapped address 3FH for special function. Refer to the page 2-3.
Y1
J3
To
User_Vcc
External clock source
Header for flash serial programming signals
Target System is supplied
V
DD
Connecting point for external clock source like a crystal.
To program an internal flash, connect the signals with flash writer tool.
Target Board is not supplied
V
DD
to Target System.
Target Board is supplied
V
DD
to Target System.
J3
Join 2-3
NOTE: S3F80JB Target board consists of 74HC11N, regulator and other components. In case of 74HC11N, typical operating voltage is 5V. So 80jb target board includes a regulator for 3.3V generation. As you know, S3F80JB typical operating voltage is 3.3V. Although open-i500 supports 3.3 V for target board ‘s power source, we recommend that you connect jumper of open-i500 power source to 5V. Check the interface board’s jumper status between emulator and target board.
This LED is OFF when the Reset switch is ON.
This is LED is ON when the evaluation chip (S3E80JB) is in idle mode.
This LED is ON when the evalution chip (S3E80JB) is in stop mode.
20-4
S3F80JB DEVELOPMENT TOOLS DATA
P2.3/INT8
P2.4/INT9/CIN0
P3.0/T0PWM/T0CAP/SDAT
P3.1/REM/SCLK
V DD
V SS
X OUT
X
IN
TEST
P2.5/INT9/CIN1
P2.6/INT9/CIN2
RESET
P3.4
P3.5
P2.7/INT9/CIN3
P1.0
P3.2/T0CK
P3.3/T1CAP/T2CAP
P4.7
P1.1
P1.2
P1.3
N.C
N.C
N.C
J2 (for 44-QFP)
13
14
15
16
9
10
11
12
6
7
4
5
8
1
2
3
17
18
19
20
21
22
32
31
30
29
36
35
34
33
44
43
42
41
40
39
38
37
28
27
26
25
24
23
P4.5
P4.6
P1.7
P1.6
P1.5
P1.4
N.C
N.C
N.C
P2.2/INT7
P2.1/INT6
P2.0/INT5
P4.0
P4.1
P4.2
P4.3
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
P4.4
NOTE: N.C means No Connection.
Figure 20-2. 50-Pin Connector Pin Assignment for TB80JB
Target Board
J2
1 50
Target System
1 50
25 26
Target Cable for 50-Pin Connector
25 26
Figure 20-3. TB80JB Adapter Cable for 44-QFP Package
20-5
DEVELOPMENT TOOLS DATA S3F80JB
SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG Incircuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer.
Series In-Circuit Emulator
— OPENice-i500
— SMART
OTP/MTP Programmer
— BlueChips-Combi
— GW-PRO2
Development Tools Suppliers
Please contact our local sales offices on how to get MDS tools. Or contact the 3rd party tool suppliers directly as shown below.
8-bit In-Circuit Emulator
OPENice - i500
SMART Kit
AIJI System
•
TEL: 82-31-223-6611
•
FAX: 82-331-223-6613
• E-mail : [email protected]
• URL : http://www.aijisystem.com
C & A Technology
•
TEL: 82-2-2612-9027
•
FAX: 82-2-2612-9044
•
E-mail: [email protected]
•
URL: http://www.cnatech.com
20-6
S3F80JB DEVELOPMENT TOOLS DATA
OTP/MTP PROGRAMMER (WRITER)
SPW2+
Single PROM OTP/ FLASH MTO Programmer
• Download/Upload and data edit function
• PC-based operation with RS232C port
• Full function regarding OTP programmer
(Read, Program, Verify, Blank, Protection..)
• Fast programming speed (1Kbyte/sec)
• Support all of SAMSUNG OTP devices
•
•
Low-cost
Download the files from the 3rd party link shown
below.
C & A Technology
•
TEL: 82-2-2612-9027
•
FAX: 82-2-2612-9044.
•
E-mail: [email protected]
•
URL:
http://www.cnatech.com
International Sale
BlueChips-Combi
BlueChips-combi is a programmer for all Samsung
MCU. It can program not only all Samsung
OTP/MTP (Flash) MCU but also the popular
E(E)PROMs. New devices will be supported just by adding device files or upgrading the software. It is connected to host PC’s serial port and controlled by the software.
SEMINIX
•
TEL: 82-2-539-7891
•
FAX: 82-2-539-7819.
•
E-mail:
•
URL:
http://www.seminix.com
AIJI System
• TEL: 82-31-223-6611
• FAX: 82-31-223-6613
• E-mail :
• URL :
http://www.aijisystem.com
GW-PRO2
Gang Programmer for One-time PROM device
• 8 devices programming at one time
• Fast programming speed (1.2Kbyte/sec)
•
•
PC-based control operation mode
Full Function regarding OTP program
(Read,Program,Vertify,Protection,blank..)
•
Data back-up even at power break
After setup in Desgin Lab,it can be moved to the
factory site.
•
Key Lock protecting operator's mistake
•
Good/Fail quantity displayed and memorized
•
Buzzer sounds after programming
•
User friendly single-menu operation (PC)
•
Operation mode displayed in LCD pannel
(Stand-alone mode)
C & A Technology
•
TEL: 82-2-2612-9027
•
FAX: 82-2-2612-9044.
•
E-mail: [email protected]
•
URL:
http://www.cnatech.com
International Sale
SEMINIX
•
TEL: 82-2-539-7891
•
FAX: 82-2-539-7819.
•
E-mail:
•
URL:
http://www.seminix.com
20-7
S3C8 SERIES MASK ROM ORDER FORM
Product description:
Device Number: S3C80JB S3F80JB
S3C8__________- ___________(write down the ROM code number)
Product Order Form: Package Pellet Wafer Package Type: __________
Package Marking (Check One):
Standard Custom A
(Max 10 chars)
Custom B
(Max 10 chars each line)
SEC
@ YWW
Device Name
@ YWW
Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities:
ROM code
Customer sample
Risk order
–
Quantity
Not applicable
Comments
See ROM Selection Form
See Risk Order Sheet
Please answer the following questions:
)
For what kind of product will you be using this order?
New product Upgrade of an existing product
Replacement of an existing product Other
If you are replacing an existing product, please indicate the former product name
( )
)
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price Product quality Features and functions
Development system Technical support Delivery on time
Used same micom before Quality of documentation Samsung reputation
Mask Charge (US$ / Won): ____________________________
Customer Information:
Company Name: ___________________ Telephone number _________________________
Signatures: ________________________ __________________________________
(Person placing the order) (Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3F8 SERIES REQUEST
FOR PRODUCTION AT CUSTOMER RISK
Customer Information:
Company Name: ________________________________________________________________
Department: ________________________________________________________________
Telephone Number: __________________________ Fax: _____________________________
Date: __________________________
Risk Order Information:
Device Number: S3F8__________- ___________(write down the ROM code number)
Package:
_____________________
Number of Pins: ____________ Package Type:
Intended Application: ________________________________________________________________
Product Model Number: ________________________________________________________________
Customer Risk Order Agreement:
We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule:
Risk Order Quantity: _____________________ PCS
Delivery Schedule:
Delivery Date (s) Quantity Comments
Signatures: _______________________________ _______________________________________
(Person Placing the Risk Order) (SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
FLASH APPLICATION NOTES
S3F80JB Programming By Tool
TOOL PROGRAMMING OF S3F80JB
To read/write/erase by OTP/MTP writer, the following six pins are used.
S3F80JB
Table 1. Descriptions of Pins Used to Read/Write/Erase the Flash in Tool Program Mode
Normal Chip
Pin Name
P3.0
Pin Name Pin No. I/O
SDAT 3[30] I/O
During Programming
Function
Serial data pin. Output port when reading and input port when writing. SDAT (P3.0) can be assigned as an input or push-pull output port.
P3.1 SCLK 4[31] I Serial clock pin. Input only pin.
9[4] Tool mode selection when TEST pin sets Logic value ‘1’. If user uses the flash writer tool mode (ex.spw2+ etc.), user should connect TEST pin to V
DD.
(S3F80JB supplies high voltage 12.5V by internal high voltage generation circuit.)
V
DD
,
V
SS
V
V
DD
SS
, 5[32],
6[1]
– Power supply pin for logic circuit.
V
DD should be tied to +3.3 V during programming.
When writing or erasing using OTP/MTP writer, user must check the following:
T he maximum operating voltage of S3F80JB is 3.6V. (Refer to the electrical data of S3F80JB manual.) The selection flag of Vdd must be set to 3.3V as like a figure on next page.
— Test Pin Voltage
The TEST pin on socket board for OTP/MTP writer must be connected to Vdd (3.3V). The TEST pin on socket board must not be connected Vpp(12.5V) which is generated from OTP/MTP Writer.
So the specific socket board for S3F80JB must be used, when writing or erasing using OTP/MTP writer.
1
S3F80JB
This is only an example for setting Vdd. This is SPW2+ which is one of OPT/MTP Writers.
2
Important Note
Subject :
Toggling phenomenon when serial writing programming on the S3F80JB.
Important Note
1. ANALYSIS RESULT
When serial writing programming on S3F80JB, only port1.4,1.5,1.6,1.7 are affected by SDAT signal. This phenomenon is only port1.4,1.5,1.6,1.7 issues and in normal operating mode it never be occurred.
2.
ANALYSIS OF PHENOMENON
2.1 FOR SERIAL PROGRAMMING MODE
The S3F80JB/9 is needed to nRESET pin = “0(GND)” & TEST pin = “1(VDD)”
S3F80JB
P1.4~1.7
When nRESET pin = “0(GND)” & TEST pin = “1(VDD)”
In the Figure 1, “SDAT” signal effects to “outdis” and “data” signal ( See 1 )
But, because MUX level is “unknown” ( See 2 ), “outdis” and “data” is toggling.
This toggling phenomenon is only occurred to port1.4,1.5,1.6,1.7 on S3F80JB
1
2.2 FOR NORMAL OPERATING MODE
The S3F80JB/9 is needed to nRESET pin = “1(VDD)” & TEST pin = “0(GND)”
P1.4~1.7
When nRESET pin = “1(VDD)” & TEST pin = “0(GND)”
In the Figure 2, because TEST signal is low(Logic level 0), “outdis” and “data” signal is same to MUX “0” signal.
So, in normal operation, port1.7 doesn’t occurred to toggling phenomenon because of SDAT changing
Timing Diagram of Figure1, Figure2
2
Important Note S3F80JB
3. DIFFERENCE S3F80JB AND S3F80J9
3.1 WHEN TEST PIN = “1(VDD)”
This is Fabrication Test mode (For Design team & PE ) : Design team & PE team tested S3F80JB by using
ADVAN equipment When testing S3F80JB, port1.0~1.7 is set to address port and data port for chip test.
So, output disable signal of Port1.0~1.7 is toggling to Input/Output mode.
¾ When S3F80JB
Port1.0~1.7 is used to address & data port between Advan equipment and S3F80JB. When Advan equipment sends data to S3F80JB, port1.0~1.7 is input mode. And when Advan equipment receives next address to
S3F80JB, port1.0~1.7 is output mode. I.e, port1.0~1.7 is toggling to Input/Output mode during chip test.
3
¾ When S3F80J9
On S3F80J9, address & data port is different from S3F80JB. Because the 28-SOP type doesn’t have port1.4~1.7, port1.0~1.3 and port2.4~2.7 are used to address & data port. (S3F80J9 is supported to 32-SOP and 28-SOP type.)
4. NOTICE
When serial writing programming on S3F80JB, port1.4,1.5,1.6,1.7 should be floating node or not connected to any device effected to damage by toggling.
-
4
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Table of contents
- 65 S3C8/S3F8-Series Microcontrollers
- 65 S3F80JB Microcontroller
- 65 Features
- 65 Block Diagram (32-pin package)
- 65 Block Diagram (44-pin package)
- 65 Pin Assignments
- 66 Overview
- 66 Program Memory
- 66 Register Architecture
- 66 Register Page Pointer (PP)
- 66 Register Set
- 66 Prime Register Space
- 66 Working Registers
- 66 Using the Register Pointers
- 66 Register Addressing
- 66 Common Working Register Area (C0H–CFH)
- 66 4-Bit Working Register Addressing
- 66 8-Bit Working Register Addressing
- 67 Overview
- 67 Register Addressing Mode (R)
- 67 Indirect Register Addressing Mode (IR)
- 67 Indexed Addressing Mode (X)
- 67 Direct Address Mode (DA)
- 67 Indirect Address Mode (IA)
- 67 Relative Address Mode (RA)
- 68 Overview
- 127 Overview
- 127 Interrupt Types
- 127 Interrupt Vector Addresses
- 127 Enable/Disable Interrupt Instructions (EI, DI)
- 127 System-Level Interrupt Control Registers
- 127 Interrupt Processing Control Points
- 127 Peripheral Interrupt Control Registers
- 127 System Mode Register (SYM)
- 127 Interrupt Mask Register (IMR)
- 127 Interrupt Priority Register (IPR)
- 127 Interrupt Request Register (IRQ)
- 127 Interrupt Pending Function Types
- 127 Interrupt Source Polling Sequence
- 127 Interrupt Service Routines
- 127 Generating interrupt Vector Addresses
- 127 Nesting of Vectored Interrupts
- 127 Instruction Pointer (IP)
- 128 Overview
- 128 Flags Register (FLAGS)
- 128 Flag Descriptions
- 128 Instruction Set Notation
- 128 Condition Codes
- 129 Overview
- 129 System Clock Circuit
- 129 Clock Status During Power-Down Modes
- 129 System Clock Control Register (CLKCON)
- 222 Overview
- 222 Reset Sources
- 222 Reset Mechanism
- 222 External Reset Pin
- 222 Watch Dog Timer Reset
- 222 LVD Reset
- 222 Internal Power-On Reset
- 222 External Interrupt Reset
- 222 Stop Error Detection & Recovery
- 222 Power-Down Modes
- 222 Idle Mode
- 222 Back-up mode
- 222 Stop Mode
- 222 Sources to Release Stop Mode
- 222 System Reset Operation
- 222 Hardware Reset Values
- 222 Recommendation for Unusued Pins
- 223 Overview
- 223 Port Data Registers
- 223 Pull-Up Resistor Enable Registers
- 244 Overview
- 244 Basic Timer (BT)
- 244 Timer
- 244 Basic Timer Control Register (BTCON)
- 244 Basic Timer Function Description
- 244 Timer 0 Control Register (T0CON)
- 244 Timer 0 Function Description
- 245 Overview
- 245 Timer 1 Overflow interrupt
- 245 Timer 1 Capture interrupt
- 245 Timer 1 Match interrupt
- 325 Overview
- 325 (On-Board Programming) Sector
- 325 ISP Reset Vector and ISP Sector Size
- 325 Flash Memory Control Registers (User Program Mode)
- 325 Flash Memory Control Register (FMCON)
- 325 Flash Memory User Programming Enable Register (FMUSR)
- 325 Flash Memory Sector Address Registers
- 325 Sector Erase
- 325 Programming
- 325 Reading
- 326 Overview
- 326 LVD Flag
- 326 Low Voltage Detector Control Register (LVDCON)
- 330 Overview
- 330 Target Boards
- 330 Programming Socket Adapter
- 330 TB80JB Target Board
- 330 OTP/MTP Programmer (Writer)