143078-001

iSBC™ 208 FILEXIBLE DISK DRI"E

CO'NTROLLER

Hj~RDWARE

REFERIENCE MANUAL

Order Number: 143078-001

Copyright © 1981 Intel Corporation

J

Intel Corporation, 3065 B,)wers Avenue, Santa Clara, California 95051 r

ii

Additional copies of this manual or other Intel literature may be obtained from:

Literature Department

Intel Corporation

3065 Bowers Avenue

Santa Clara, CA 95051

The information in this document is subject to change without notice.

Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that may appear in this document. Intel Corporation makes no commitment to update nor to keep current the information contained in this document.

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.

Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR

7-104.9(a)(9).

No part of this document may be copied or reproduced in any form or by any mmns without the prior written consent of Intel Corporation.

The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products:

BXP

CREDIT i

ICE

.

'

1m lnsite

Inlel in tel lntelevision

Intellec iRMX iSBC iSBX

Library Manager

MCS

Megachassis

Micromainframe

Micromap

Multibus

Multimodule

Plug· A-Bubble

PROMPT

RMX/SO

SYSlem2000

UPI

[A475/1081/

6[fu[1

REV.

-001 Original issue.

REVISION HISTORY DATE

10/81 iii

PREFACE

I

This manual is the hardware referl~nce for the iSBC 208 Flexible Disk Controller.

The manual is divided into five chapters that describe general information, preparation for use, programmingnformation, principles of operation, and service information. Three appendices, describing sample 110 drivers, the iSBX

Multimodule interface, and drive interfaces are also included. Supplemental information can be found in the following Intel publications:

• Intel Multibus Specification, order number 9800683

• iSBX Bus Specification, order number 142686

• iSBC Applications Manual, oreler number 142687

• Intel Component Data Catalog

• MCS-80/85 Family User's Manual, order number 121506

• The 8086 Family User's Manual, order number 9800722

• 8080/8085 Assembly Language Programming Manual, order number 9800940

• MCS-86 Macro Assembly Language Reference Manual order number 9800640 v

CONTENTS

I

CHAPTER 1

GENERAL INFORMATION

PAGE

Introduction ...................... " .......... . 1-1

Specifications 1-2

CHAPTER 2

PREPARATION FOR USE

Introduction ................................. .

Unpacking and Inspection .................. .

Installation Considerations .................... .

Powt:r Requirements ........................ .

Cooling Requirements ...................... .

Bus Interface .................................

Multibus Interface AC Characteristics ......... .

Multibus Interface DC Characteristics ......... .

Auxiliary Connl~ctor ........................ .

Board Location Considerations ................. .

Controller Board Configuration ................ .

Host Processor Configuration ................ .

Drive Configuration ........................ .

Auxiliary Port Configuration .......... " ..... .

Drive Interfacing ............................. .

Controller Interface Signals .................. .

Drive Interface AC Characteristics ............ .

Drive Interface DC Characteristics ............ .

Drive Cabling ................................ .

2-8

2-8

2-9

2-11

2-11

2-1

2-1

2-1

2-7

2-7

2-11

2-11

2-11

2-17

2-1

2-1

2-1

2-1

2-1

Drive Modifications .......................... .

Ready Logic ............................... .

Motor-On Control ......................... .

Radial Head Load .......................... .

Drive Termination .......................... .

Drive Numbering ........................... .

Multiple Drive Pin Assignments .............. .

Stepper Motor Power ....................... .

2-18

2-18

2-18

2-18

2-18

2-18

2-18

2-18

CHAPTER 3

PROGRAMMING INFORMATION

Introduction ................................. .

UO Port Commands ...........................

3-1

3-1

Read/Write DMAC Address Registers... .... ... 3-1

Read/Write DMAC Word Count Registers ...... 3-3

Write DMAC Command Register .............. 3-3

Read DMAC Status Register Command ........ 3-3

Write DMAC Request Register ................. 3-4

Set/Reset DMAC Mask Register ............... 3-4

Write DMAC Mode Register .................. 3-4

Clear DMAC First/Last Flip-Flop ............. 3-5

DMAC Master Clear ......................... 3-5

Write DMAC Mask Register .................. 3-5

Read FDC Status Register ..................... 3-6

Read/Write FDC Data Register ................ 3-6

Write Controller Auxiliary Port ...... ,........ 3-6

Poll Interrupt Status ................ '........ 3-7

PAGE

Controller Reset ........................... .

Write Controller Low- And High-Byte Segment

3-7

Address Registers ...................... .

Diskette Organization ......................... .

3-8

3-8

FDC Commands ............................ ". 3-12

Specify Command .......................... . 3-16

Seek Command ............................. 3-17

Read Data ................................ .

Read Deleted Data ..........................

3-17

3-19

Read ID ................................... 3-20

Read Track ................................ .

Write Data ................................ .

Write Deleted Data ..... .

....................

3-20

3-21

3-21

Format Track .............................. .

Recalibrate

3-21

Sense Drive Status .......................... .

Sense Interrupt Status ....................... .

3-23

3-24

3-24

Invalid Commands ......................... .

Software .....................................

3-24

3-24

Initialization .............................. .

Programming the DMAC .................... .

3-25

3-25

Programming the FDC ...................... .

Interrupt Processing ....................... .

3-25

3-28

CHAPTER 4

PRINCIPLES OF OPERATION

Introduction

Schematic Interpretation ...................... .

Functional Description ........................ .

Clock and Timing Circuitry .................. .

Multibus Interface .......................... .

DMA Controller (DMAC) ................... .

DMA Addressing .......................... .

Floppy Disk Controller ...................... .

FDD Interface ............................. .

Drive and Head Selection .................. .

Write Precompensation ................... .

Data Separator ... , ...................... .

4-1

4-1

4-1

4-1

4-2

4-3

4-3

4-4

4-5

4-5

4-5

4-5

CHAPTER 5

SERVICE INFORMATION

Introduction 5-1

Service and Repair Assistance ................... 5-1

Replaceable Parts ............................. 5-1

Adjustments .................................. 5-1

Service Diagrams .............................. 5-1

APPENDIX A

SAMPLE DRIVERS

Introduction .................................. A-I

PUM 86 Driver ............................... A-I

Assembly Language Driver ..................... A-15 vii

CONTENTS (Cont'd.)

APPENDIXB iSBX MUL TIMODULE BOARD

INTERFACE

PAGE

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-1

Installation ................................... B-1

Configuration ................................ B-1

DMA Channels ............................. B-1

Interrupts .................................. B-2

Programming Information ..................... B-2

PAGE

Port Assignments ........................... B-2

Programming the DMAC .................... B-2

APPENDIXC

DRIVE INTERFACES

Introduction .................................. C-I

U sing the Tables .............................. C-I

TABLES

TABLE

2-8

2-9

2-10

2-11

2-12

2-13

3-1

3-2

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

TITLE PAGE

Specifications ......................... 1-2

Multibus Interface Pin Assignments ...... 2-2

Multibus Interface Signal Definitions ..... 2-3 iSBC 208 Board DC Characteristics ...... 2-6

P2 Bus Connector ..................... 2-7

110 Base Address Selection ............. 2-9

Drive Configuration Jumper Links ....... 2-9

Auxiliary Port Jumper Matrix ........... 2-11

12 Interface Connector Pin Assignments .. 2-13

Jl Interface Connector Pin Assignments .. 2-13

Interface Connector Signal Functions .... 2-14

Drive Interface AC Timing Characteristics 2-16

Drive Interface DC Characteristics ....... 2-16

Mating Connectors .................... 2-17

I/O Port Controller Commands ......... 3-2

Track Format ......................... 3-10

3-11

3-12

4-1

4-2

4-3

4-4

5-1

5-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

TABLE TITLE PAGE

Recording Capacities .................. 3-12

FDC Commands ...................... 3-12

Result Phase Status Registers ............ 3-13

Command Mnemonics ................. 3-15

HUT Values .......................... 3-16

SRT Values .......................... 3-17

HLT Values .......................... 3-17

Command Byte Values ................. 3-18

Result Phase 10 Information ............ 3-19

Formatting Table ..................... 3-23

IC U71 Output ........................ 4-2

Write Clock Frequency ................. 4-2

Chip Select Coding .................... 4-2

On Time Clock Versus Data Rate ........ 4-6

Replaceable Parts ..................... 5-2

Manufacturer's Codes ................. 5-4 viii

ILLUSTRATIONS

2-5

2-6

2-7

2-8

3-1

3-2

3-3

3-4

FIGURE

1-1

2-1

2-2

2-3

2-4

TITLE PAGE iSBC 208 Flexible Disk Drive Controller

Bus Acquisition and Memory

1-1

Transfer Timing .................... 2-4

I/O Transfer Timing ................... 2-5

Serial Priority Resolution ............... 2-8

Typical Four-Drive System (Standard-Sized

Drives) ............................. 2-12

Seek Timing .......................... 2-15

Head Load Timing .................... 2-15

Write Data Timing .................... 2-15

Flat-Ribbon I/O Interface Cable ......... 2-17

Main Status Register Timing ............ 3-7

20-Bit Addressing ..................... 3-8

Track Format ......................... 3-9

Sector Interleaving .................... 3-22

3-5

3-6

3-7

3-8

3-9

3-10

4-1

4-2

4-3

4-4

5-1

5-2

FIGURE

TITLE PAGE

I/O Parameter Block .................. 3-25

Initialization Flow Chart ............... 3-26

FOC Command Phase Flow Chart ....... 3-26

Serial/Parallel Command Phase

Flow Chart ......................... 3-27

Result Phase Flow Chart ............... 3-28

Interrupt Processing Flow Chart ......... 3-29

Logic Conventions .................... 4-1

DMA Transfer Timing ................. 4-4

Data Recovery Timing ................. 4-6

Block Diagram of Controller ............ 4-7 iSBC 208 Parts Location Diagram ........ 5-5 iSBC 208 Board Schematic Drawing

(7 sheets) ........................... 5-7

IX

l

CHAPTER

11

GENERAL INFORMATION

,----~-

1-1. INTRODUCTION

The iSBC 208 Flexible Disk Controller is one product within a complete line of Intel iSBC single board computer expansion modules. The iSBC 208 controller is designed to interface up to four single- or double-sided, standard 8-inch floppy disk drives or four single- or double-sided 5 'i4 -inch mini-floppy drives. The controller permits both single- and double-sided drives of the same size to be interfaced, and both single-delilsity (FM) and double-density

(MFM) recording formats to be used concurrently.

The controller supports a soft-sector format with sector sizes ranging from 128 bytes to 409~ bytes in the

IBM 3740-compatible single-density format and ranging from 256 bytes to 8192 bytes in the IBM system 34-compatible double-density format.

The iSBC 208 controller is designed expressly for

Intel Multibus interface compatibility and can be inserted directly into a standard iSBC 604/614 cardcage as found in the iSBC System 80 series mainframe or into any of the Intel microcomputer development systems. All circuitry is contained on a single printed circuit board and operates from a single +5 volt source. A majority of the controller's logic is LSI (large scale integration) and includes both an Intel 8237 DMA Controller (DMAC) and an Intel

8272 Floppy Disk Controller (FDC). Additionally, data separation logic is included on the board to eliminate the necessity of this logic within the drive or off-board. The controller interfaces directly with any multibus-compatible single board computer. This computer, referred to in the remainder of this manual as the "host processor," provides all information required to perform a disk operation. Once all of the information is received, further host processor involvement is unnecessary, and the controller takes control of the bus for the duration of the data transfer. When the transfer is complete, the controller interrupts the host processor. When interrupted, the host processor examines the controller's status register to determine the outcome of the operation.

In addition to programmable sector sizes and recording density, the head load time, head unload time and track-to-track access time (step rate) operating characteristics also can be program specified. Additionally, a number of jumper-selectable options are provided to support various drive features and drive interface pin assignments. As shown in figure 1-1, the controller has two drive-interface connectors, -a 50pin connector for interfacing standard 8-inch drives and a 34-pin connector for interfacing 5 'i4 -inch mini drives. A 36-pin connector is incorporated on the controller board for the installation of either a singleor double-wide iSBX Multimodule board. The controller extends M ultibus capability to the

Multimodule board and also provides up to two

MINI-DRIVE

INTERFACE

STANDARD-DRIVE

INTERFACE

J2 iSBX T• MULTIMODULP"

INTERFACE

J3

Pl

MlILTlBUS·MINTERFACE

P2

AUXILIARY INTERFACE

Figure 1-1. iSBcr M 208 Flexible Disk Drive Controller

143078-1

1-1

General Information iSBC 208

DMA channels for use by the iSBX board. The P2 auxiliary edge connector includes four address lines that extend the controller's memory addressing capability to 16 megabytes (24-bit address bus).

1·2. SPECIFICATIONS

Table 1-1 lists the physical and performance characteristics of the iSBC 208 controller.

Table 1-1. Specifications

Compatibility

Host Processor

Diskette Drive

Drive Interface

Any Intel mainframe, microcomputer development system or Multibus-compatible

CPU. The controller supports either 16-,20- or 24-bit addresses and an 8-bit data bus width.

Single- or double-sided, standard 8-inch or 5%-inch mini drives. Up to four drives of one size can be interfaced; single- and double-density, and single- and doublesided drives can be mixed.

Compatible with Shugart SA850 (standard 8-inch) and Shugart SA450 (5%-inch mini) or any other drive with a similar interface.

Typical Drive Characteristics

Transfer Rate

Standard 8-inch Drive

250 kilobits per second, single density (FM)

500 kilobits per second, double density (MFM)

5%-inch Mini Drive

125 kilobits per second, single density (FM)

250 kilobits per second, double density (MFM)

Disk Speed

360 rpm (standard 8-inch)

300 rpm (5%-inch mini)

Track-to Track Access Time (Step Rate)

Programmable from 1 to 16 ms in 1 ms steps (standard) or from 2 to 32 ms in 2 ms steps (mini).

Head Load Time

Programmable from 2 to 254 ms in 2 ms increments (standard) or from 4 to 508 ms in 4 ms increments (mini).

Head Unload Time

Programmable from 16 to 240 ms in 16 ms increments (standard) or from 32 to 480 ms in 32 ms increments (mini); jumper selectable for 1 second.

Physical

Dimensions

Length: 30.48 cm (12.0 inches)

Width: 17.15 cm (6.75 inches)

Height: 1.27 cm (0.5 inches)

Shipping Weight

0.82 kg (1.8 pounds)

Power Requirements

5.0 volts (±5%), 3 amperes (maximum)

Environmental

Temperature: O°C to +55°C, operating (+32°F to +131 OF)

-55°C to +85°C, non-operating (-67°F to +185°F)

Humidity: Up to 90% relative humidity without condEmsation.

1-2

iSBC 208

Table 1-1. Specifications (Cont'd.)

Data Organization and Capacity (Standard 8-inch drives')

Single Density

Bytes per Sector

Sectors per Track

Tracks per Side

Bytes per Side

Double Density

Bytes per Sector

Sectors pHr Track

Tracks per Side

Bytes per Side

IBM Format

128 256 512

26

77

15

77

8

77

256,256 (128-byte sector)



IBM Format

256 512 1024

26 15 8

77 77 77



630,784 (1 024-byte sector)

'Consult manufacturer's data for mini-floppy drive organization and capacity.

General Information

N,on-IBM Format

1024 2048 4096

4 2 1

2Ei6 Addressable

315,392 (77 tracks)

Non-IBM Format

2048 4096 8192

4 2

2~i6 Addressable

1

630,784 (77 tracks)

1-3

CHAPTER 2

PREPARATION FOR USE

2-1.

INTRODUCTION

This chapter presents information on the preparation and installation of the iSBC 208 Controller. Included within this chapter are instructions describing the unpacking and inspection, installation, board configuration, host processor bus interface and drive cabling for the controller.

2-2.

UNPACKING AND INSPECTION

On receipt of the controller from the carrier, immediately inspect the shipping carton for evidence of mishandling in transit. If the shipping carton is damaged or waterstained, request that the carrier's agent be present when the carton is opened. If the carrier's agent is not present when the carton is opened and if the contents of the carton are damaged, keep the carton and packing materials intact for the agent's inspection.

For repairs or replacement of an Intel product damaged in shipment, contact the Intel Technical

Support Center (see Chapter 5) to obtain a Return

Authorization Number and further instructions. A copy of the purchase order should be submitted to the carrier with the claim.

Carefully unpack the shipping carton and verify that the following items are included. Compare the packaging slip with your purchase order to verify that the order is complete. The carton and packing materials should be saved in case it becomes necessary to reship the controller at a later date.

Item 1: iSBC 208 Interface Printed Circuit

Assembly.

Item 2: Schematic Diagram.

2-3.

INSTALLATION

CONSIDERATIONS

The controller is designed expressly for installation into the Intel iSBC 604/614 modular backplane and card cage as found in the Series 80 single board computer mainframes. The controller can also be installed into any odd-numbered slot in an Inteillec Model 800 or in any slot in an Intellec microcomputer development system. The controller additionally can be installed into a user's Multibus-compatible backplane assembly that meets the controller's mating connector dimensional requirements.

2-4. POWER REQUIREMENTS

The controller operates from a single +5 volt (±5 070) source and requires a maximum of 3.0 amperes.

When installing the interface in an iSBC 80 Series, microcomputer development, or custom system, ensure that the system"s power supply can meet the additional current requirements of the controller.

2-5. COOLING REQUIREMENTS

The iSBC 80 Series and Intellec microcomputer development systems use forced-air cooling that generally is adequate to maintain an internal operating temperature below 55°C. When installing the controller in a high-temperature environment or in any other system enclosure, ensure that the internal operating temperature is not permitted to exceed the 55°C maximum.

2-6.

BUS INTERFACE

The controller communicates with the host processor

(and memory) via the Mulilibus interface. Tables 2-1 and 2-2 define the Multibus interface pin assignments and corresponding signal definitions. The controller connects to the Multibus interface through connector

PI, an 86-pin, double-sided printed circuit edge connector with 3.96mm (0.156 inch) contact centers.

2-7. MUL TIBUS INTERFACE

AC CHARACTERISTICS

Figures 2-1 and 2-2 show the Multibus interface ac timing characteristics when the controller is operating as a "bus mastl~r" (Bus Acquisition and

Memory Transfer Timing) and as a "bus slave" (110

Transfer Timing).

2.8 MUL TIBUS INTERFACE

DC CHARACTERISTICS

The controller's dc signal characteristics for the

Multibus interface are given in table 2-3.

2-1

Preparation for Use iSBC 208

Table 2-1. Multibus Interface Pin Assignments

Pin"

21

22

23

24

25

17

18

19

20

9

10

11

12

13

14

15

16

5

6

7

8

1

2

3

4

34

35

36

37

38

39

40

41

42

43

30

31

32

33

26

27

28

29

Signal

GND

GND

+5VDC

+5VDC

+5VDC

+5VDC

+12VDC

+12VDC

GND

GND

BCLK!

INIT!

BPRN!

BPRO!

BUSY!

BREQ!

MRDC!

MWTC!

10RC!

10WC!

XACK!

}

Ground

ADR10!

CBRQ!

ADR11!

CCLK!

ADR12!

ADR13!

INT6!

INH!

INT4!

INT5!

INT2!

INT3!

INTO!

INT1!

ADRE!

'Unassigned Pins are reserved.

}

Function

Power Inputs

}

Ground

Bus Clock

Initialization

Bus Priority In

Bus Priority Out

Bus Busy

Bus Request

Memory Read Command

Memory Write Command

110 Read Command

I!O Write Command

Transfer Acknowledge

Address Bus

Common Bus Request

Address Bus

Constant Clock

Address Bus

Address Bus

Interrupt Request 6

Interrupt Request 7

Interrupt Request 4

Interrupt Request 5

Interrupt Request 2

Interrupt Request 3

Interrupt Request 0

Interrupt Request 1

Address Bus

Pin"

62

63

64

65

58

59

60

61

51

52

53

54

55

56

57

44

45

46

47

48

49

50

77

78

79

80

81

72

73

74

75

76

82

83

84

85

86

66

67

68

69

70

71

Signal Function

ADRF! ....

ADRC!

ADRD!

ADRAI

ADRB

ADR8!

ADR9!

ADR6!

ADR7!

ADR4!

ADR5!

ADR2!

ADR3!

ADRO!

ADR1!

J

~ Address Bus

DAT6! ...

DAH!

DAT4!

DAT5!

DAT2!

DAT3!

DATO!

DAT1!

J

>

Data Bus

GND }

GND

Ground

-12VDC

-12VDC

+5VDC

+5VDC

+5VDC

+5VDC

GND

GND

}

Power Inputs

}

Ground

2-2

iSBC 208

Signal

ADRO/-ADRFI

ADR10/-ADR131

BCLKI

BPRNI

BPROI

BREQI

BUSYI

CBRQI

CCLKI

DATO/-DAT71

INITI

INTO/-INT71

10RCI

10WCI

MRDCI

MWTCI

XACKI

Preparation for Use

Table 2-2. Multibus Interface Signal Definitions

Function

Address. These ·,6 bidirectional lines specify the address of the memory location or

110 port to be accessed. ADRF I is the most significant bit.

Extended Address. These four output lines extend the controller's memory addressing to 1 megabyte. ADR131 is the most significant bit.

Bus Clock. This input signal is used to synchronize the controller's bus control logic.

Bus Priority In. This input signal level indicates that no higher-priority master board has requested control of the bus.

Bus Priority Out. This output signal level is used with serial priority resolution schemes and indicates to the next lower-priority master board that either the controller or another higher-priority master board has requested control of the bus.

Bus Request. Thils output signal is used with parallel priority resolution schemes and indicates that the controller is requesting control of the bus.

Bus Busy. This bidirectional signal indicates that either the controller or another master board is currently in control of the bus and consequently prevents any other master board from gaining access to the bus.

Common Bus Request. This output signal indicates that the controller requires access to the bus while the bus is in the use by another bus master.

Constant Clock. A clock signal routed through the controller to the iSBX multimodule.

Data. These eight bidirectional lines transfer data either to or from the memory location or 110 port addressed. DA T71 is the most significant bit.

Initialization. This input signal generally originates from a power-up reset circuit or a contact closure to ground (Le., a front panel reset switch) and resets all devices on the bus to an initialized state.

Interrupt. A set of eight, mUlti-level interrupt request lines for use with parallel interrupt resolution logic. The selected (jumper determined) output interrupt signal is used to indicate a controller-initiated interrupt request.

110 Read Command. This input signal instructs the controller to place the data associated with the addressed input port onto the data lines.

110 Write Command. This input signal instructs the controller to accept the data associated with the addressed output port that is present on the data lines.

Memory Read Command. This output signal indicates that the address of a memory location is on the address lines and that the contents of that location are to be placed on the data lines for acceptance by the controller.

Memory Write Command. This output signal indicates that the address of a memory location is on the address lines and that the data presented by the controller on the data lines is to be written into that location.

Transfer Acknowledge. This signal originates from the controller during 110 port transfers and indicates that the controller has accepted or is presentinrl the associated data of' the data lines. During memory transfers, this Signal originates from the random access memory board and indicates that the data on the data lines either has been written into the addressed memory location or that the data is present and is to be accepted by the controller.

2-3

Preparation for Use iSBC208

2-4

Parameter tCBRO tBCY tBW tBREO tBPRNS tBPRO tBPRNO tBUSY tASR tAH tDXl tXCR tDHR tASW tDS txcw tDHW tlNIT

BCLKI

BREOI

~

-...j

~tBPRO

<I ~tBUSY

"BPROI - - -

"BUSYI \

_

_ _ , . ' - t CBRO

\ CBROI

ADROI - ADR131 _ _ _ _ _ _ _ _ _

~~

BREO

---t

j...-tBPRO

' ' ' ' ' - - - - - - . . ; . I - I - - - tB-US-Y-

1

-I

!;::tCBRO

1

MRDCI OR 10RCI

DATOI-DATlI

MWTCI OR 10WCI

I

1;::::= tDXL

-I.. tXCR:::::! tDHR

---------------""'x:

STABLE READ DATA

~tASW9

DATOI - DATl I - - - - - - - - - - - - -

:::::I

!-==tDSW

I

l---tXCW~

*' ------

1-------

~lf

---STABLE WRITE DATA---....

I-'DHW

.x."-------

XACKI

'---~/

• ASSUMES BPRNI ACTIVE

Minimum

67 ns

100 ns

35 ns

22 ns

286 ns

147 ns

-250 ns

567ns

-80 ns

786 ns

80 ns

567ns

65ns

4 ns

Maximum

35 ns

40 ns

30 ns

55ns

1327 ns

1257 ns

Description

BClKI to CBROI Delay

Bus Clock Period

Bus Clock Pulse Width

BClK/ to BREO/ Delay

BPRN / to BClKI Setup Time

BClK/ to BPRO/ Delay

BPRN/ to BPRO/ Delay

BClK/ to BUSY/low Delay

Address Setup Time (Read)

Address Hold Time

Data Setup to Acknowledge Time (Read)

Acknowledge to Command High (Read)

Data Hold Time (Read)

Address Setup Time (Write)

Data Setup to Command Time (Write)

Acknowledge to Command High-(Write)

Data Hold Time (Write)

Reset Pulse Width

Figure 2-1. Bus Acquisition and Memory Transfer Timing 121746-2


ADDRESS/

WRITE DATAl

READ DATA/

ADDRESS STABLE

~------3 r-''"~

J - t

DATA STABLE

+-3

¥

DATASTAB~E

r-''"1

I

COMMAND/

(IORC/ OR IOWC/)

XACK/

~

'XACK r'""-1

\

~ ~'''"!

Parameter tAS tAH tXACK

,tXACK tDXL tDHR tXAH tDS tOH

Minimum

-384 ns

50 ns

906 ns

4400 ns

2 ns

20 ns

61 ns

-189 ns

35 ns

'Software RESET command only.

Maximum

1100 ns

5100 ns

Description

Address Setup Time

Address Hold Time

Command to Acknowledge

Read Data Setup Time

Read Data Hold Time

Acknowledge Hold Time

Write Data Setup Time

Write Data Hold Time

Figure 2-2. 110 Transfer Timing

143078-2

2-5

Preparation for Use

Signals

XACKI

ADRO/-

ADRFI

BCLK/,

BPRNI

ADR10/-

ADR131

ADR14/-

ADR17I

(on P2)

BPROI

VOL

VOH

VIL

VIH

IlL

IIH

'CL

VOL

VOH

VIL

VIH

IlL

·6

H

L

VIL

VIH

IlL

·6

H

L

VOL

VOH

V

LL

ILH

'CL

Symbol

Table 2-3. iSBC 208 Board DC Characteristics

Parameter

Description

Output Low Voltage

Output High Voltage

Input Low Voltage

Input High Voltage

Input Current at Low V

Input Current at High V

Capacitive Load

Output Low Voltage

Output High Voltage

Input Low Voltage

Input High Voltage



Capacitive Load

Input Low Voltage

Input High Voltage



Capacitive Load

Output Low Voltage

Output High Voltage

Output Leakage Low

Output Leakage High

Capacitive Load

Test

Conditions

IOL =32 rnA

IOH=-5.2 rnA

VIN =0.4V

VIN=2.4V

IOL =32 rnA

IOH=-5 rnA

VIN =-0.45 V

VIN =5.25V

VIN =0.45V

Vln =5.25V

IOL =24 rnA

IOH=-15 rnA

Min

2.0

2.0

2.4

2.0

2.0

2.4

BREQI

BUSYI

(Open

Collector)

DATO/-

DAT71

CBRQI

(Open

Collector)

IORC/,

IOWC/,

INIT/,

CCLKI

VOl.

VOH

'CL

VOL

VOH

'CL

-

VOl.

VIL

VIH

VIL

·6

H

L

VOL

VOH

V1L

V"H

IlL

·6

H

L

-

V,x

'C

IL

VIL

VIH

IlL

.~I

L

Output Low Voltage

Output High Voltage

Capacitive Load

Output Low Voltage

Output High Voltage

Capacitive Load

Output Low Voltage

Input Low Voltage

Input High Voltage



Capacitive Load

Output Low Voltage

Output High Voltage

Input Low Voltage

Input High Voltage


Output Leakage High

Capacitive Load

Output Low Voltage

Capacitive Load

Input Low Voltage

Input High Voltage



Capacitive Load

IOL =3.2 rnA

IOH=-0.4 rnA

IOL =20 rnA

IOH=-0.4 rnA

IOL=20 rnA

VIN =0.45V

VIN =5.25V

IOL=32 rnA

IOH=-5 rnA

VIN =0.45V

Vo=5.25V

10L =60 rnA

VIN =O.4V

VIN =2.4V

2.4

2.4

2.0

2.4

2.0

2.0

0.45

0.8

-0.5

100

20

0.45

0.80

-'0.20

100

18

0.8

15

0.45

15

0.45

10

0.8

-1.2

40

18

Max

0.8

-0.2

50

18

0.8

-0.5

100

15

0.4

20

20

15

.04

0.8

-1.2

40

15

0.45 iSBC 208

V

V

V rnA

IJA pF

V

V

V

V rnA

IJA pF

V pF

V

V pF

V

V pF

V

V rnA flA pF

Units

V

V

V

V rnA

IJA pF

V

V

V

V rnA

IJA pF

V

V rnA

IJA pF

V

V

IJA

IJA pF

2-6

iSBC 208 Preparation for Use

Signals Symbol

Table 2-3. iSBC™ 208 Board DC Characteristics (Cont'd.)

Parameter

Description

INTO/-

INT71

VOL

VOH

ILH

.~L

L

Output Load Voltage

Output High Voltage

Output Leakage High

Output Leakage Low

Capacitive Load

MRDC/,

MWTCI

VOL

VOH

VIL

VIH

10

Output Low Voltage

Output High Voltage

Input Low Voltage

Input High Voltage

Output Leakage Current

·CL Capacitive Load

·Capacitive load values are approximations ..

Test

Conditions

IOL=60 mA

Open Collector

Vo=5.25V

Vo=0.45V

IOL=32 mA

IOH=-2 mA

VIN =0.45V

VIN =5.25

Min

2.4

2.0

Max

0.45

250

-500

15

0.45

0.8

-100

100

25

2-9. AUXILIARY CONNECTOR

The auxiliary connector (P2) provides the four 1megabyte paging bits to effectively allow the controller to address up to 16 megabytes. The bits are set in the controller's auxiliary port and are routed to the

P2 connector as noted in table 2-4. illustration (figure 2-3), a wire-wrap jumper must be installed from terminal post B (BPRN/) to logic ground at terminal post N (604) or terminal post L

(614).

2-10. BOARD LOCATION

56

55

58

57

CONSIDERATIONS

Since the controller functions as a bus master during

DMA transfers, when installing the controller in a serial priority environment (e.g., within any of the

Intel Series 80 mainframes), the controller should occupy the highest priority slot (top physical slot) in the 604/614 backplane and card cage assembly, with any other bus masters and the host processor board located below. The backplane providl~s bus priority in and out s~nal continuity among adjacent bus masters. The BPRNI (Bus Priority In) input to the top slot (12) of either the single (604) or expansion

(614) backplane must be connt~cted to logic ground.

Both backplanes provide the BPRNI input on a wirewrap terminal post. As shown in the following

Pin Signal

ADR171

ADR161

ADR151

ADR141

Always remove system power prior to installing or removing a board in the backplane. Failure to observe this precaution can result in circuit damage.

Note that if a bus slave (e.g., a memory board) is installed between two bus masters (or if a vacant slot exists between two bus masters), the serial priority input-output chain must be physically jumpered on the backplane to maintain signal continuity. Figure

2-3 shows the installation of a jumper between terminal posts C and E that would provide the required BPROI-BPRNI continuity around a

"slave" installed in the second slot (13).

When installing the controller in a parallel priority resolution environment, the controller should be given the highest bus priority .. In an Intellec Model

Table 2-4. P2 Bus Connector

Function

DC Characteristics (each signal)

Current Drive

Low (I OL) High (loHI

Current Load

Low (IlL) High (IIHI

High-Order Page Address Bit

24mA -15mA 0 0

Low-Order Page Address Bit

Units

V flA flA pF

V

V

V

V flA flA pF

2-7


HIGHEST PRIORITY

LOWEST PRIORITY

J2

J3 J4 J5

15

1

0

BPRNI

BPROI

16

1 1

0

1 1

0 1 1

0

1

15

15 N.C.

BPRNI 15 N.C.

N.C.

16

BPROI

16

N.C.

~"~J

1

0 J 1

0 J 1

0 J 1

0 J iSBC CPU iSBC 208

CONTROLLER iSBC 1/0

BOARD iSBC RAM

BOARD BOARD

(TYPICAL) (TYPICAL) (TYPICAL)

Jl-16 (614)

INSTALL

JUMPER

C

INSTALL

JUMPER

-

-

-

-

TERMINAL POST DESIGNATIONS IN PARENTHESES

CORRESPOND TO 614 EXPANSION BACKPLANE

E l

L(M)

-

-

H

K(N~

-

-

Figure 2-3. Serial Priority Resolution

143078-3

800 development system, the controller must be installed in an odd-numbered (bus master) slot and ideally should be installed in slot 17 (highest bus priority). In an Intellec Series II or Series III development system, the controller should be installed in the bottom (highest bus priority) slot.

2-11. CONTROLLER BOARD

CONFIGURATION

The controller board includes alterable jumpers that are used to configure the controller to its intended system environment. The jumpers can be divided into three major groups: host processor configuration, drive configuration, and auxiliary port configuration. The locations of the jumpers are shown in figure 5-1. Note that the controller jumpers associated with the iSBX Multimodule interface are described in Appendix B.

2-12. HOST PROCESSOR

CONFIGURATION

The jumpers associated with the host processor interface are used to specify the 110 address bit length, the 110 base address of the controller, parallel or serial bus priority resolution, and Multibus interface interrupt level selection.

The 110 address bit length (8 or 16 bits) is determined by the jumper link at E41-E45-E49. When shipped from the factory, a push-on shorting plug is installed between E45 and E49 to select 8-bit 110 address decoding. To implement 16-bit 110 address decoding, remove the shorting plug connecting E45 and E49 and install the plug between E41 and E45.

The controller's 110 base address is specified by a set of jumpers that provides either a high (" 1") or low

("0") input to the 110 address decode comparators.

2-8


Depending on the 110 address bit length selected (8 or 16 bits), either three (8-bit addressing) or all eleven

(l6-bit addressing) jumpers must be configured.

When shipped from the factory, all of the 1/0 base address shorting plugs are in the "0" position (corresponding to a 16-bit I/O base address of OOOOH). To relocate the 110 base address, reposition the shorting plugs according to table 2-5. As an example, to select an 110 base address of F800H, address bits F, E, D,

C, and B would be jumpered to the "I" position, and the remaining address bits would be jumpered to the "0" position. 8-bit addressing allows base addresses from OOH to EOOH, while 16- bit addressing gives addresses from OOOOH to FFEOH.

Table 2-5. I/O Base Address Selection

Address Bit

5

6

7

8*

9*

A*

S*

C*

0*

E*

F*

Shorting - Plug Position

"1" "0"

E42-E46

E43-E4i'

E44-E48

E53-E61

E54-E6'!

E55-E63

E56-E64

E57-E6Ei

E58-E6Ei

E59-E6i'

E60-E68

E46-E50

E47-E51

E48-E52

E61-E69

E62-E70

E63-E71

E64-E72

E65-E73

E66-E74

E67-E75

E68-E76

*Only required for 16-bit 1/0 addressing.

Parallel/serial bus priority resolution is determined by jumper E77-E78. The controller is configured at the factor for serial bus priority resolution (jumper installed between E77 and E78) as found in the Intel

System 80 mainframes. To select parallel bus priority resolution (e.g., when installing the controller in an

Intellec microcomputer development system), remove the jumper between E77 and E78.

The controller's Multibus interface interrupt level is selected by installing a jumper from E79 to one of the eight Multibus interface lines on E82 through E89.

The following list defines the interrupt/jumper correspondence.

Jumpers

E79-E89

E79-E88

E79-E87

E79-E86

E79-E85

E79-E84

E79-E83

E79-E82

Interrupt Level

INTOI

INT11

INT21

INT31

INT41

INT51

INT61

INT71

Note that an interrupt level jumper is not installed at the factory and that the interrupt level selected must

not have been previously assigned to another bus master.

2-13. DRIVE CONFIGURATION

The jumpers associated with drive configuration are used to define both the controller pin assignments on the drive interface connectors and the type of drive being interfaced (mini or standard) as well as to support optional features within the drive. Table 2-6 defines the usual functions of the drive configuration jumper links; any unused jumper associated with the interface connectors can be used to implement other functions within the d~ive or to reassign pin assignments for radial signals when interfacing multiple drives.

Function

FAULT RESET I

LOW CURRENTI

Table 2-6. Drive Configuration Jumper Links

Jumper

Posts

E27,E28

E25,E26

Factory

Configuration

Removed

Installed

Description

When this jumper link is installed, the controller provides a FAULT RESETI output on J2-50 during read Iwrite operations. This output is used to reset optional fault detection circuitry within a drive.

With this jumper link installed, the controller provides a LOW

CURRENTI output on J2-2 during read/write operations whenever the track address is 43 or greater (to reduce write current on the inner tracks). If the drive interfaced does not support low write current compensation, remove the jumper link between E25 and E26.

2-9

Preparation for Use

Function

READY I

TWO SIDED I

FAULTI

Mini/Standard

HEAD LOADI iSBC 2(}8

Table 2-6. Drive Configuration Jumper Links (Cont'd.)

Jumper

Posts

E17,E18,E19

E21,E22

E23,E24

E4,E5

E29 thru E40

Factory

Configuration

E18-E19

Installed

Removed

Removed

E31-E32,

E38-E39

Description

A jumper link is installed between E18 and E19 (factory configuration) when the drive interfaced provides a

READY I signal to the controller on

J2-22 or J1-6. When a drive does not provide a READY I signal (most minisized drives do not provide this signal), remove the jumper link between E18 and E19 and install a jumper link between E17 and E19.

With this jumper installed, the TWO

SIDEDI status signal from a drive is available to the controller on J2-10 or

J1-34. When all of the drives interfaced are single-sided, this jumper link can be omitted.

When this jumper link is installed, the optional FAULTI status signal from a drive is available to the controller on J2-48.

This jumper link identifies the type of drive (mini or standard) interfaced to the controller. With the jumper link removed, the controller is configured for standard 8-inch drives. When interfacing mini-sized drives, install the jumper link between E4 and E5.

In the factory configuration (jumper links E31-E32 and E38-E39 installed), a common HEAD LOADI signal is output (on J2-18) to all drives interfaced. The head load and head unload time intervals associated with the HEAD LOADI signal are user programmable.

Individual (radial) HEAD LOADI signals for each drive can be made available at the J2 connector by removing the jumper link between

E38 and E39 and installing the following jumper links:

E37to E38

E39 to E40

E29 to E30

E35 to E36

E33 to E34

In this configuration, the programmed head load interval remains unchanged, but the programmed head unload interval is increased by 1 second (fixed) to decrease wear on the head load mechanism during heavy usage.

The HEAD LOADI jumper link matrix also allows a common HEAD LOADI signal (on J2-18) with the additional 1 second head unload delay. This configuration is implemented by installing the following jumper links:

E37to E38

E39 to E40

E34 to E36

E36to E30

E30 to E32

E32 to E31

2-10

iSBC208

Function

Mini Drive Select

Preparation for Use

Table 2-6. Drive Configuration Jumper Links (Cont'd.)

Jumper

Posts

E20

Factory

Configuration

Removed

Description

When shipped from the factory, the controller does not provide a DRIVE

SELECT 31 signal on mini-drive interface connector J1. To interface four mini drives, the DRIVE SELECT 31 signal on jumper post E20 must be connected to one of the jumper posts corresponding to an unused pin on the J1 connector. Depending on the functions supported by the mini drive, the following jumper posts may be available:

E18 (READYI input from drive on

J1-6)

E21 (TWO SIDEDI input from drive on J1-34)

Also, any unassigned J1 connector pin in the auxiliary port matrix can be used (see Section 2-14).

2-14. AUXILIARY PORT

CONFIGURA TION

The auxiliary port jumper linlks form a matrix that includes four jumper posts on !the low··order four bits of the controller's auxiliary I/O port and three jumper posts on specific pins of drive interface connectors J2 and J 1. By interconnecting auxiliary port and connector pin jumper posts, special drive functions and signals can be defined through the auxiliary port. The primary function of the port is to provide

MOTOR ONI signals to mini-sized drives. Table 2-7 defines the jumper posts in the auxiliary port matrix. interface connectors, a 50-pin connector (J2) for interfacing standard-sized drives and a 34-pin connector (Jl) for interfacing mini-sized drives. Figure

2-4 depicts a typical four-drive system.

~16. CONTROLLER INTERFACE

SIGNALS

The individual pin assignments for the J2 and J 1 drive interface connectors are given in tables 2-8 and

2-9, respectively. Table 2-10 describes the individual signal functions.

Table 2-7. Auxiliary Port Jumper Matrix

Jumper Auxiliary Port Jumper Interface Connector

Post Assignment Post Pin Assignment

E11

E9

E7

E2

Bit 0

Bit 1

Bit 2

Bit3

E10

E8

E6

J1-2, J2-8

J1-4, J2-12

J1-16*, J2-16

*J1-16 is defined as the MOTOR ON 1 signal pin on the Shugart drive interface.

2-17. DRIVE INTERFACE AC

CHARACTERISTICS

The drive interface ac timing characteristics are shown in the following timine> diagrams (figures 2-5 through 2-7); the individual timing values are given in table 2-11.

2-15. DRIVE INTERFACING

The iSBC 208 controller can interface up to four single- or double-sided, standard 8-inch or 5 V4-inch mini-sized drives. The controller includes two drive

2-18. DRIVE INTERFACE DC

CHARACTERISTICS

The drive interface de signal characteristics are given in table 2-12. Note that all controller output signals are open collector and that all input signals are terminated on the controller with 220/330 ohm resistor networks.

2-11


2-12

Figure 2-4. Typical Four-Drive System (Standard-Sized Drives)

143078-4


Table 2-8. 12 Interface Connector Pin Assignments

Pin

Assignment

18

20

22

24

26

2

4

6

8

10

12

14

16

Signal

LOW CURRENT I

HEAD LOAD 21

HEAD LOAD31

Spare

TWOSIDEDI

Spare

SIDE SELECT I

Spare

HEAD LOAD 01

INDEXI

READY I

HEAD LOAD11

DRIVE SELECT 01

Pin

Assignment

36

38

40

42

28

30

32

34

44

46

48

50

Note that all odd-numbered pins are connected to logic ground.

Signal

DRIVE SELECT 11

DRIVE SELECT 21

DRIVE SELECT 31

DIRECTION I

STEPI

WRITE DATAl

WRITEGATEI

TRACK 01

WRITE PROTECT I

READ DATAl

FAULTI

FAULTRESETI

Table 2-9. 11 Interface Connector Pin Assignments

Pin

Assignment

8

10

12

14

2

4

6

16

18

Signal

Spare

Spare

READY I

INDEXI

DRIVE SELECT 01

DRIVE SELECT 11

DRIVE SELECT 21

Spare

DIRECTION I

Pin

Assignment

Note that all odd-numbered pins are connected to.iogic ground.

20

22

24

26

28

30

32

34

Signal

STEPI

WRITE DATAl

WRITEGATEI

TRACKOI

WRITE PROTECT I

READ DATAl

SIDE SELECT I

TWOSIDEDI

2-13


Signal

LOW CURRENT/

HEAD LOAD2/

HEAD LOAD3/

TWO SIDED/

SIDE SELECT /

HEAD LOADO/

INDEX/

READY/

HEAD LOAD 1/

DRIVE SELECT 0/

DRIVE SELECT 1/

DRIVE SELECT 2/

DRIVE SELECT 3/

DIRECTION/

STEP/

WRITE DATA/

WRITE GATE/

TRACK 0/

WRITE PROTECT /

READ DATA/

FAULT/

FAULT RESET/

Table 2-10. Interface Connector Signal Functions

Function

A low-state active output signal used to select low write current compensation circuitry available in some drives. This signal is enabled during read/write operations and is active (low) when the track address is 43 or greater. Note that a factory-installed jumper link is used to route this signal to pin 2 of connector J2.

An optional (jumper selectable) low-state active output signal used to load the read/write head in drive 2. When the head is initially loaded, the controller provides a programmed delay (head load time) prior to initiating any read/write operation. Following a read/write operation, the controller delays inactivating the HEAD LOAD 2/ signal until the programmed head unload time and the one-second fixed delay intElrvals time out. Note that a jumper link must be installed to route the HEAD LOAD 2/ signal to theJ2 interface connector.

An optional low-state active output signal that is functionally identical to HEAD LOAD 2/ except routed to drive 3.

A low-state active status input signal that indicates the installation of a double-sided diskette within the drive. Note that a factory-installed jumper link is used to route this signal into the controller from drive interface connectors J2 and J1, and that this signal is only examined during the Sense Drive Status command.

An output control signal that selects one side of a double-sided drive. When SIDE SELECT is low, read/write qperations are performed on side 1 of the drive.

A low-state active output signal used to load the read/write head in drive O. When configured at the factory, this signal is the only HEAD LOAD/ signal available on interface connector J2

(common HEAD LOAD/ signal for all drives interfaced), and the additional one-second head unload delay is not used.

A low-state active input pulse that is coincident with the detection of the index hole in the diskette (indicates the logical beginning of a track).

A low-state active input signal indicating that the drive is ready to perform an operation. The qualifications for READY/are drive dependent and usually include diskette in place, door closed and diskette rpm at specified speed. The controller uses a common READY / input and requires that the drives interfaced provide a gated READY / output when individually selected.

An optional low-state active output Signal that is functionally identical to HEAD LOAD 2/ except routed to drive 1.

Individual low-state active output signals for selecting the individual drives interfaced. Note that a DRIVE SELECT 3/ signal is not included on the J1 interface connector and that when interfacing four mini drives, this signal must be connected to one of the jumper posts associated with an unassigned pin of connector J1.

An output control signal that specifies the direction in which the drive's read/write head is stepped. This signal is only enablod during seek operations and when at a logic low level, causes the head to be stepped toward the spindle (step in).

A low-state active output pulse that causes the drive to move (step) the read/write head one track position. The direction that the head is stepped is determined by the state of the

DIRECTION/ output Signal. Like thl~ DIRECTION/ signal, STEP/ is only enabled during seek operations.

The serial data/clock composite write signal to the drive. The high-to-Iow-going transition of this signal indicates a bit to be written on the diskette.

A low-state active control signal that is used to enable the drive's write electronics (allowing data to be written on the diskette). When this signal is in its inactive state, the write electronics are disabled, and the drive reads data from the diskette.

A low-state active input status signal that indicates the drive's read/write head currently is positioned over track O. Note that this signal is only examined during a seek or recalibrate operation.

A low-state active input status signal that indicates the installation of a write-protected diskette in the drive. Note that this signal is only examined during a write or format operation.

The composite (unseparated) data and clock input signal generated by the drive during a diskette read operation. A high-to-Iow-going transition indicates a clock or data "one" bit.

An optional low-state active input signal that indicates a write fault condition within the drive.

This signal is only examined durin!l read/write operations and requires the installation of a jumper link to route the signal into the controller from the J2 interface connector.

A low-state active output control Signal that is used to reset fault detection logic optional in some drives. This signal is automatically generated at the beginning of every read/write operation and requires the installation of a jumper link to route the Signal to the J2 interface connector.

2-14


DRIVE SELECT /

DIRECTION/

STEP/

143078-5

Figure 2-5. Seek Timing

HEAD LOAD/

\

FIRST OPPORTUNITY

TOREjDATA s s

LAST BYTE

READ OR WRITTEN

~ r t H l l l F - t H L D - - - 1

WRITE DATA/

Figure 2-6. Head Load Timing

143078-6

CLOCK CLOCK

+ +

~-''''~

"'W

~

Figure 2-7. Write Data Timing

143078-7

2-15


Symbol Parameter

Table 2-11. Drive Interface AC Timing Characteristics

Standard 8-inch Drive

Minimum Typical

51!4-inch Mini Drive

Maximum Minimum Typical Maximum

Seek Timing tDSD tSDS tDS tSD tSCY tspw

DRIVE SELECT I to

DIRECTIONI Setup

Time

DRIVE SELECTI Hold

Time from STEPI

DIRECTION I to STEP I

Setup Time

DIRECTION I Hold

Time from STEPI

STEP I Cycle Time

STEPI Pulse Width

Head Load Timing tHLD tHUL tHUT

Head Load Time

Head Unload Time

Head Unload

Time-Out (Optional)

Write Data Timing tHBC tFBC tDPW

Half Bit Cell

Full Bit Cell

Data Pulse Width

*FM Mode Values.

19

5

1

24

1

5

2

16

200

1

1 or 2*

2 or 4*

250

16

254

240

38

10

2

48

2

10

4

32

200

1

2 or 4*

4 or 8*

250

32

508

480

Units

IlS ms ms s

IlS

Ils ns

Ils

Ils

IlS ms

Ils

Signal

All Output Signals*

READY/, INDEXI, READ DATAl

WRITE PROTECT I, TWO SIDED/,

FAULT I, TRACK 01

Table 2-12. Drive Interface DC Characteristics

Current Drive

IOL IOH

48mA

-

-

- 25OIlA

-

-

Current

Loa~

IlL

-

-O.8mA

-O.2mA

IIH

-

40llA

20llA

* Auxiliary port output signals have an additional 10k ohm pullup resistor to V cc.

2-16


2-19. DRIVE CABLING

The controller uses two drive interface connectors, a

34-pin connector for interfacing mini-sized drives

(J 1) and a 50-pin connector for interfacing standardsized drives (2). Each interface connector can interface up to four drives using a daisy-chain technique.

Since most drives compatible with the controller follow the Shugart flexible disk drive interface requirements, flat ribbon cable and mass-termination type connectors are recommended for cable fabrication. (A number of the individual drive interface signal pin assignments can be altered or defined by jumpers on the controller board.) To fabricate the

I/O interface cable, the cable ends are fitted with the appropriate mating connectors, and when interfacing multiple drives, additional drive mating connectors are inserted directly into the cable to form a daisychain cable. The recommended maximum cable length between the controller and the (last) drive is 10 feet (3 meters); consult the drive manufacturer's specifications for additional limitations. Figure 2-8 illustrates a typical daisy-chain flat ribbon cable designed to interface two standard-sized drives.

Table 2-13 lists compatible controller mating connectors and cable. Refer to the drive manufacturer's documentation for the required drive mating connectors.

Controller

Connector

J1

J2

Table 2-13. Mating Connectors

Mating

Connector

3M 3414-7034 or

T&BI Ansley 609-3401 M

3M 3425-7050 or

T&BI Ansley 609-5001 M

Cable

3M ]365/34

T&BI Ansley 171-34

Spectra-Strip (twisted pair)

455-248-34

3M 3365/50

T&B/Ansley 171-50

Spectra-Strip (twisted pair)

455-248-50

,

[CONTROLLER MATING CONNECTOR

3M 3425-7050 OR EQUIVALENT

F= ff r-I!!!!!!!!!!!!!==I~

--=--.-... -. ~~I

===

====

~

==

II

-T

DRIVE MATING CONNECTORS-J

(SEE DRIVE MANUFACTURER'S

DOCUMENTATION)

Figure 2-8. Flat-Ribbon I/O Interface Cable

143078-8

2-17

Preparation for Use iSBC20B

2-20.

DRIVE MODIFICATIONS

The following subsections define the general drive modifications that may be necessary to ensure proper interface with the controller. Detailed information is included in the drive manufacturer's documentation.

HEAD LOADI (common only)

LOW CURRENT I (if used)

FAULT RESET I (if used)

MOTOR ONI (if used; common only)

2-21. READY LOGIC

Most standard-sized drives compatible with the controller provide a ready indication to the controller only when the drive is selected. If the drive provides an ungated READY I output (generally referred to as radial ready), the drive must be modified to condition the drive's READY I output with DRIVE

SELECT I. Most mini-sized drives do not provide a ready indication. Accordingly, when interfacing drives that do not provide a READY I output, make sure that the controller's READY I input is permanently enabled with the installation of a jumper link between jumper posts E17 and E19 as described in table 2-6.

2-24. DRIVE TERMINATION

When two or more drives are interfaced (daisychained) to the controller, the termination resistors/networks on the following common drive input signal lines must be removed from all but the last physical drive on the cable:

DIRECTION I

STEPI

WRITE DATAl

WRITEGATEI

2-25. DRIVE NUMBERING

When interfacing multiple drives, each drive must be assigned a unique drive unit number. Depending on the manufacturer, internal drive unit assignment may be determined by wire jumper, shorting plug, or individual switch contacts. Generally, drives are shipped by their manufacturer configured for singledrive systems (i.e., the drive is assigned unit 0 with drives numbered 0 through 3 or unit 1 with drives numbered 1 through 4).

2-22. MOTOR-ON CONTROL

The MOTOR ONI control output for mini-sized drives must be enabled prior to drive selection to allow time for the drive to reach operating speed before an operation is initiated. Accordingly, the

MOTOR ONI input to the drive must not be gated with DRIVE SELECT I. Note that this restriction applies when using either a common MOTOR ONI signal or a radial MOTOR ONI signal in multipledrive configurations.

2-23. RADIAL HEAD LOAD

As an option, the controller can be configured to provide individual (radial) HEAD LOADI outputs.

When this option is used, the individual HEAD

LOADI signals must not Qe gated with their associated DRIVE SELECT I signal within the drive.

2-26. MULTIPLE DRIVE

PIN ASSIGNMENTS

When interfacing more than one drive, unique pin assignments for the individual DRIVE SELECT/,

MOTOR ONI (when used in radial configuration), and radial HEAD LOADI (optional) signal lines associated with each drive must be provided. The actual pin assigned will depend on pin availability based on drive features supported and interface signal requirements. Note that it may be necessary to cut traces within the drive in order to reroute the input signal within the drive. It also may be necessary to cut traces to omit non-critical drive status signals

(e.g., TWO-SIDEDI or IN USE) in order to provide additional pin assignments on the interface. Appe:ndix C lists the pin assignments for a number of the standard- and mini-sized drives compatible with the controller.

2-27. STEPPER MOTOR POWER

Many drives compatible with the controller support a power-down feature that allows power to the stepper motor to be enabled only when the drive is selected.

Since the controller automatically polls all four possible drives for a change in drive-ready status by cycling through the DRIVE SELECT I lines, the power down feature cannot be supported directly

(i.e., power to the stepper motor must not be dependent on drive selection). Note that in addition to the above restriction, the interval between drive selection and the generation of the first STEP I pulse is too short to allow the stepper motor to be enabled by the

DRIVE SELECT I lines. When the stepper motor power-down featue is to be used, the host processor must enable and disable the stepper motor through the controller's auxiliary port.

2-18

CHAPTER 3



This chapter describes the 110 port commands that are executed by the host processor to convey information to and from the controller's programmable flexible disk controller (FDC) and DMA controller

(DMAC) circuits and the individual FDC commands that control all disk operations and the transfer of data to and from the drive. Additionally, this chapter contains a description of the diskette formats supported and individual flow charts depicting the various diskette operations.

All disk operations are defined and initiated by the host processor through the execution of a series of

110 port commands while the controller is functioning as a bus slave. Once all information required to define the operation has been received, the controller functions as a bus master; the controller accesses and maintains control of the system bus and completes the specified operation without further intervention from the host processor. When the operation is complete, the controller reverts to a bus slave; the host processor must interrogate the controller to determine the outcome of the operation.

To initiate a disk operation, a series of 110 port commands is executed by the host processor. This series of commands defines the FDC operation to be performed, provides all supplemental information

(parameters) required to perform the operation, and, if a data transfer to or from the diskette is indicated, defines the direction of the data transfer, the starting memory address of the first data byte to be transferred and the I,lUmber of bytes to be transferred.

3-2. 1/0

PORT COMMANDS

Host processor communication with the controller is accomplished through an 110 port address block as defined by the least-significant bits of the 110 address. The location of this block (the 110 base address) in host processor memory must be on a

32-bit boundary (64-bit boundary with iSBX

Multimoduk board installed) and is defined by the user through a set of jumpers on the controller.

These jumpers correspond to the three mostsignificant bits of an 8-bit 110 address or the eleven most-significant bits of a 16-bit 110 address (8- or 16bit I/O addressing is user-selectable by an additional jumper on the controller).

The host processor executes an 110 port read or write instruction at one of the locations within the 110 port address block to transfer information either to (110 write) or from (110 read) the controller. Table 3-1 defines the controller's I/O port command set. Note that a number of the ports can be both read and written while other ports are either read-only or writeonly. Each port command transfers one byte of data; a number of the 110 port commands require two data bytes (i.e., the port command must be issued twice to transfer all data associated with the 110 port command).

3-3. READ/WRITE DMAC ADDRESS

REGISTERS

The controller's DMAC circuit has four DMA channels of which three channels are available. Each channel has an identical pair of 16-bit address registers, a "current-address" register, and a "baseaddress" register (each channel also has an identical pair of 16-bit word-count registers). Channel 0 is used by the controller for all diskette data transfers,

Channel 1 is not used, and Channels 2 and 3 are available for use by an iSBX Multimodule board installed on the controller.

The Write DMAC Address Register command is used to simultaneously load a channel's current-address register and base-address register with the memory address of the first byte to be transferred. (The

Channel 0 current/base address register must be loaded prior to initiating a diskette read or write operation.) Since each channel's address registers are

16 bits in length (64K address range), two "write address register" commands must be executed in order to load the complete current/base address registers for any channel. The register byte loaded

(high- or low-order) is determined by the state of the

DMAC's first/last flip-flop. (When the flip-flop is reset, the associated data byte is written into the Ioworder eight bits of the register; the flip-flop is toggled with each command so that a second address register command accesses the "other" byte.) The currentaddress register is incremented with each byte transferred; the base-address register maintains its initial value until it is reloaded by a subsequent Write

Address Register command (or until the DMAC or controller is reset).

The Read DMAC Address Register command reads the low- or high-order byte of a channel's currentaddress register (a channel's base-address register

3-1

Port

Address

0

1

2,3

4

5

6

7

8

12

13

14

15

16-1F

20-2F

OE

OF

10

11

9

OA

OB

OC

00

Programming Information iSBC 208

Table 3-1. I/O Port Controller Commands

Mode

Write

Read

Write

Read

-

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Write

Write

Write

Write

-

Write

Read

Write

Read

Write

Read

Write

Write

Write

-

-

Command Function

Load OMAC Channel 0 Base and Current Address Regsiters

Read OMAC Channel 0 Current Address Register

Load OMAC Channel 0 Base and Current Word Count Registers

Read OMAC Channel 0 Current Word Count Register

Reserved

Load OMAC Channel 2 Base and Current Address Registers




Load OMAC Channel 3 Base and Current Jlddress Registers




Load OMAC Command Register

Read OMAC Status Register

Load OMAC Request Register

Set/Reset OMAC Mask Register

Load OMAC Mode Register

Clear OMAC First/Last Flip-Flop

OMAC Master Clear

Reserved

Load OMAC Mask Register

Read FOC Status Register

Load FOC Data Register

Read FOC Data Register

Load Controller Auxiliary Port

Poll Interrupt Status

Controller Reset

Load Controller Low-Byte Segment Address Register

Load Controller High-Byte Segment Address Regist.er

Not Used

Reserved for iSBX Multimodule Board (see Appendix B)

3-2

iSBC 208 Programming Information cannot be read). The current-address register byte' accessed is determined by the state of the DMAC's first/last flip-flop as previously described. are applicable to the controller; the remaining bits select functions that are not supported and, accordingly, must always be set to zero.

3-4. READ/WRITE DMAC WORD

COUNT REGISTERS

Like the DMAC address registers, each DMA channel also has an identical pair of 16-bit word-count registers, a "current word-count register" and a

"base word-count register." The channel 0 wordcount registers are used to specify the number of bytes to be transferred during a diskette read or write operation. The channel 1 word-count registers are not used, and the word-count registers for channels 2 and 3 are dedicated to DMA functions associated with a Multimodule board.

The Write DMAC Word Count Register command is used to simultaneously load a channel's current and base word-count registers with the number of bytes to be transferred during a subsequent DMA operation. Since the word-count registers are 16-bits in length, two commands must be executed to load both halves of the registers. As described in section 3-3, the register half loaded (low- or high-order) is determined by the state of the DMAC's first/last flip-flop.

The actual count loaded is a binary value that is one less than the number of bytes to be transferred (i.e., the register value 01 FFH transfers 512 bytes). During the subsequent DMA transfer, the current wordcount register is decremented with each byte transferred; the base word-count register maintains its initially-loaded value until it is reloaded by a subsequent Write Word Count Register command or until either the DMAC or controller is reset. When the word count decrements to zero, the DMA transfer is stopped and the corresponding TC (terminal count) bit in the DMAC status register is set.

The Read DMAC Word Count Register command reads the low- or high-order byte of a channel's current word-count register (a channel's base wordcount register cannot be read). The current wordcount register byte accessed is determined by the state of the DMAC's first/last flip-flop.

MEMORY·TO·MEMORY DISABLE

GHANNEL 0 ADDRESS HOLD DISABLE

L-------l 0 CONTROLLER ENABLE

'1 CONTROLLER DISABLE

' - - - - - NORMAL TIMING

FIXED PRIORITY

~-----

~------

~-------

11

ROTATING PRIORITY

I.ATE WRITE SELECTION

[)REQ SENSE ACTIVE HIGH

[)ACK SENSE ACTIVE LOW

Bit 2: Controller Enable/Disable. This bit, when set to one, prevents all DMA channels from responding to data transfer requests. Normally, this bit is always set to zero to enable the DMAC. When multiple DMA channels are used and a non-essential DMA request from the iSBX Multimodule board could interrupt the programming of channel 0, the

DMAC could be disabled while it is being programmed and then enabled by a subsequent Write DMAC Command Register command after it has been programmed.

Bit 4: Fixed/Rotating Priority. This bit, when set to zero, selects fixed priority (channel 0 has the highest priority, channel 3 has the lowest priority) and when set to one, selects rotating priority (each channel is granted highest priority on a rotational scheme).

Note that when programming the command register, an aU-zero byte enables the DMAC and gives the disk controller (channel 0) the highest priority. The command register is cleared by a DMAC master clear or controller reset.

3-6. READ DMAC STATUS REGISTER

COMMAND

The Read DMAC Status Register command accesses an 8-bit status byte that identifies the DMA channels that have reached terminal count or that have a pending DMA request.

3-5. WRITE DMAC COMMAND

REGISTER

The Write DMAC Command Register command loads an 8-bit byte into the DMAC's command register to define the operating characteristics of the

DMAC. The functions of the individual bits in the command register are defined in the following diagram. Note that only two bits within the register

CftANNELOTC

CHANNEL1 TC

' - - - - CflANNEL2TC

' - - - - - CflANNEL3 TC

' - - - - - - CHANNEL 0 DMA REQUEST

' - - - - - - - CHANNEL1 DMA REQUEST

' - - - - - - - - CflANNEL2 DMA REQUEST

CflANNEL3 DMA REQUEST

3-3

3-4 iSBC208 Programming Information

Bits 0 through 3 are set when their corresponding channel has reached terminal count (i.e., when the channel's current word count register decrements to zero). Since DMA channell is not used, bit 1 always is zero. Bits 2 and 3 are associated with an iSBX

Multimodule board and indicate a terminal count condition on channels 2 and 3. Note that if external

EOP (End of Process) logic is implemented on the iSBX Multimodule board, the generation of an external EOP signal sets the active channel's TC bit irrespective of the current word count.

Bits 4 through 7 are set when their corresponding channel requests DMA service (DMAC's DREQ input activated or corresponding bit in the request register set). Again, since DMA channell is not used, bit 5 always is zero, and bits 6 and 7 indicate DMA requests originating from an iSBX Multimodule board.

The TC bits in the status register are cleared whenever the register is read by a DMAC master clear or by a controller reset.

3-8. SET IRESET DMAC MASK

REGISTER

The Set/Reset DMAC Mask Register command is used to reset (or set) individual bits within the

DMAC's internal 4-bit mask register. Each DMAC channel has an associated mask bit within the register that, when reset, enables the channel's DREQ (DMA

Request) input and, when set, disables (masks) the

DREQ input.

7 6 5 4 3 2 1 0

DON'T CARE

L{

00 SELECT CHANNEL 0

01SELECTCHANNEL1

10 SELECT CHANNEL 2

11 SELECTCHANNEL3

' - - _ - { 0 RESET MASK BIT

1 SET MASK BIT

Prior to a DREQ-initiated DMA transfer, the channel's mask bit must be reset to enable recognition of the DREQ input. When the transfer is complete (terminal count reached or external EOP applied) and the channel is not programmed to autoinitialize, the channel's mask bit is automatically set (disabling

DREQ) and must be reset prior to a subsequent

DMA transfer. All four bits of the mask register are set (disabling the DREQ inputs) by a DMAC master clear or controller reset. Additionally, all four bits can be set/reset by a single Write DMAC Mask

Register command (see section 3-12).

3-7. WRITE DMAC REQUEST REGISTER

The Write DMAC Request Register command is used with DMAC channels 2 and 3 (the iSBX Multimodule board channels) to allow DMA requests to be initiated by the host processor. The command only can be used when the selected channel is operated in the

"block transfer mode" (see section 3-9); the controller's DMA channel (channel 0) operates in either the "single transfer mode" or the "demand transfer mode" and does not use the Write DMAC Request

Register command.

The data byte associated with the Write DMAC

Request Register command sets or resets a channel's associated request bit within the DMAC's internal 4bit request register.

DON'T CARE

L{

00 SELECT CHANNEL 0

01 SELECT CHANNEL 1

. 10 SELECT CHANNEL 2

11 SELECT CHANNEL3

' - - _ - { 0 RESET REQUEST BIT

1 SET REQUEST BIT

The individual channel request bits are non-maskable and are subject to channel prioritization (fixed or rotating). Each request bit is individually set or reset according to the state of bit 2 and, when onc.e set within the register, is cleared when the corresponding channel reaches terminal count or when an external

EOP signal is applied. The entire request register is cleared by a DMAC master clear or controller reset.

3-9. WRITE DMAC MODE REGISTER

The Write DMAC Mode Register command is used to define the operating mode characteristics for each

DMA channel. Each channel has an internal 6-bit mode register; the high-order six bits of the associated data byte are written int'o the mode register addressed by the two low-order bits.

7 6 5 4 3 2 1 0 r

9°OCHANNECO""CT

MCHANNEL1SELECT

10 CHANNEL 2 SELECT

1'1 CHANNEL 3 SELECT 1

00 VERIFY TRANSFER

01 WRITE TRANSFER

10 READ TRANSFER

11 (ILLEGAL)

1 AUTOINITIALIZE ENABLE

1 ADDRESS DECREMENT

00 DEMAND MODE

10 BLOCK MODE

11 (Illegal)

iSBC 208 Programming Information

Verify Transfer. The verify transfer mode is not used by the controller; this mode may be used by an iSBX Multimodule board.

Write Transfer. The write transfer mode programs the selected DMA channel to transfer data from the

110 device to host memory. This mode must be selected to read data from the diskette (i.e., the data read from the diskette is written into host memory).

Read Transfer. The read transfer mode programs the selected DMA channel to transfer data from host memory to the 110 device. This mode must be selected to write data on the diskette (i.e., the data read from host memory is written onto the diskette).

Autoinitialize. The autoinitialize enable/disable bit is used to control a channel's autoinitialization function. When this bit is set (1), the autoinitialize mode is enabled, and the current word-count and current address register values are automatically restored from the corresponding base registers when the DMA transfer is complete (terminal count or EOP). The mask bit is not set when the autoinitialize mode is enabled, and the channel is prepared to perform a subsequent DMA transfer without reprogramming the DMAC. Note that for most controller applications, the autoinitalize mode is not used.

Address Increment/Decrement. The address increment/decrement bit determines the sequence in which memory addresses are generated. When this bit is reset (0), the memory address in the current address register is incremented with each byte transferred. Conversely, when the address increment/decrement bit is set (I), the memory address in the current address register is decremented with each byte transferred. Note that for most controller applications, the address increment mode is used.

Demand Mode. In the demand transfer mode the channel data transfer is initiated by DREQ. The channel continues to transfer data until DREQ goes inactive or until either a terminal count condition is reached or an external EOP is received. If DREQ is held active throughout the entire transfer, the channel maintains bus access until the transfer is complete. The controller (DMAC channel 0) can use the demand transfer mode; however, since the DREQ input from the FDC goes inactive following each byte transferred, the channel releases the bus after each byte transferred.

Single Transfer Mode. In single transfer mode, the channel performs a sequence of single byte transfers

(the channel releases the bus after each byte transferred) until the transfer is complete (terminal count reached or external EOP applied). DREQ must be held active by the 110 device until DACK is received.

Unlike the demand mode, if DREQ is held active throughout the entire transfer, the bus is released with each byte transferred. The controller normally uses the single transfer mode for all DMA data transfers.

NOTE

Since both the demand and single transfer modes used by the controller release the bus with each byte transferred, the controller should be given "high bus priority" to prevent interruptions in the DMA transfer.

Block Mode. In block transfer mode the channel data transfer again is initiated by DREQ. The transfers continue, irrespective of the state of DREQ, until terminal count is reached or an external EOP is applied. (DREQ must be held active until DACK is received.) The controller does not support operation in the block transfer mode; this mode may be used by an iSBX Multimodule board.

3-10. CLEAR DMAC FIRST/LAST

FLIP-FLOP

The Clear DMAC First/Last Flip-Flop command initializes the DMAC's int'ernal first/last flip-flop so that the next byte written to or read from the 16-bit address or word-count registers is the low-order byte.

The flip-flop is toggled with each register access so that a second register read or write command accesses the high-order byte. The first/last flip-flop also is initialized (to access the low-order register byte) by a DMAC master clear or controller reset.

Note that the Clear DMAC First/Last Flip-Flop command does not require a specific bit pattern in the associated command data byte.

3-11. DMACMASTERCLEAR

The DMAC Master Clear command clears the

DMAC's command, status, request, and temporary registers to zero, initializf!s the first/last flip-flop, and sets the four channel mask bits in ·the mask register to disable all DMA requests «(.e., the DMAC is placed in an idle state). Note that the DMAC

Master Clear command dOf!S not require a specific bit pattern in the associated command data byte.

3-12. WRITE DMAC MASK REGISTER

The Write DMAC Mask Register command allows all four bits of the DMAC's mask register to be written with a single command.

3-5


7 6 5 4 3 2 1 0 o

CLEAR CHANNEL 0 MASK BIT

1 SET CHANNEL 0 MASK BIT o

CLEAR CHANNELl MASK BIT

1 SET CHANNEL 1 MASK BIT o CLEAR CHAIIINEL2 MASK BIT

1 SET CHANNEl 2 MASK BIT

L - -_ _ _

0 CLEAR CHANNEL3 MASK BIT

1 SETCHANNEL3MASK BIT

Like the Set/Reset OMAC Mask Register command, clearing a channel's mask bit enables recognition of the associated OREQ input, and setting a channel's mask bit disables (masks) the associated OREQ input. Again, a OMAC master clear or controller reset sets all four mask register bits (disabling the

OREQ inputs).

3-13. READ FDC STATUS REGISTER

The Read FOC Status Register command accesses the

FOC's main status register. The individual status register bits are as follows:

7 6 5 4 3 2 1 0

NON-DMA MODE. This bit only is applicable in systems that do not support OMA tranfers and is irrelevant to the controller.

DATA INPUT/OUTPUT. The data input/output

(DIO) bit indicates the direction of the transfer between the FOC's data register and the host processor. When this bit is set, the direction of the transfer is from the FOC to the host processor, and when this bit is reset, the direction of the transfer is from the host processor to the FOC.

REQUEST FOR MASTER. The request for master

(RQM) bit, when set, indicates that the FOC's data register is ready to presell1t a byte to or accept a byte from the host processor.

The host processor can read the main status register at any time and should use the 010 and RQM status bits to perform a "handshaking" function with the

FOC when transferring data to or from the FOC's data register. Figure 3-\ shows the status register timing.

Note that like any microprocessor, the FOC requires a finite amount of time to update its RQM status bit between byte transfers to or from the data register.

The sample PL/M and assembly language drivers in

Appendix A illustrate typical wait subroutines that must be inserted between successive byte transfers to or from the FOC's data register.

FDDOBUSY

FDD 1 BUSY

FDD 2 BUSY

' - - - - - - FDC BUSY

' - - - - - - - - - - REQUEST FOR MASTER

FDD 0 BUSY. This bit, when set (1), indicates that drive 0 is in the process of performing a seek operation.

FDD 1 BUSY. This bit, when set, indicates that drive 1 is in the process of performing a seek operation.



FDC BUSY. This bit, when set, indicates that the

FOC is in the command execution phase (i.e., the

FOC is in the process Of performing a diskette read or write operation).

3-14. READ/WRITE FDC DATA

REGISTER

The Read and Write FOC Oata Register commands are used to write command and parameter bytes to the FOC in order to specify the operation to be performed (referred to as the "command phase") and to read status bytes from the FOC following the operation (referred to as the "result phase"). Ouring the command and result phases, the 8-bit data register is actually a series of 8-bit registers in a stack. Each register is accessed in sequence;. the number of registers accessed and th(! individual register contents are defined by the specific disk command (refer to the FOC command descriptions in sections 3-20 through 3-32).

3-15. WRITE CONTROLLER AUXILIARY

PORT

The Write Controller Auxiliary Port command is used to set or clear individual bits within the controller's auxiliary port. The four low-order port bits are dedicated to auxiliary drive control functions

3-6

iSBC208 Programming Information

DATA IN-OUT

(010)

REOUEST

FOR MASTER

(ROM)

WR

RD

OUT OF FDC AND INTO PROCESSOR

OUT OF PROCESSOR AND INTO FDC

READY

I

I I in

I

LJ

I

I

I u

I

I

I I

I I I I I II u

I

A

I I I I I

I

B

I

IY II

I

A

I

B

I

A

I

C

I

0

I

C

I

0

I

B

I

A

I

NOTES: A DATA REGISTER READY TO BE WRITTEN INTO BY HOST PROCESSOR

B DATA REGISTER NOT READY TO BE WRITTEN INTO BY HOST

PROCESSOR

C DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ BY THE

HOST PROCESSOR o -

DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ BY

THE HOST PROCESSOR

Figure 3-1. Main Status Register Timing

143078-9

(jumper links are required to connect the desired port bit to an available pin on the drive interface connectors; see section 2-14). The most common application for these bits is the "Motor-On" control function for mini-sized drives.

The four high-order bits of the auxiliary port are the

AORI4 through AOR17 address bits that are used to extend the OMA addressing capability of the controller to 16 megabytes (24-bit addressing). These bits are set prior to initiating a diskette read or write operation to define the specific I-megabyte page of memory to be accessed. when interrupts are disabled to poll the controller

(and iSBX Multimodule board) in order to determine when an operation has been completed. A bit set in the status byte returned indicates a pending interrupt.

7 6 5 4 3 2 1 0

GONTROLLER INTERRUPT

MUL TIMODULE BOARD

INTERRUPTO

INTERRUPT 1

3-16. POLL INTERRUPT STATUS

The Poll Interrupt Status command presents the interrupt status of the controller and the two interrupt status lines dedicated to the iSBX Multimodule board. This command is used by the host processor

3-17. CONTROLLER RESET

The Controller Reset command is the software reset for the controller. This command clears the controller's auxiliary port and segment address register, provides a reset signal to the iSBX Multimodule board and initializes the bus controller (releases the bus), the OMAC (clears the internal registers and masks the OREQ inputs), and the FOC (places the

FOC in an idle state and disables the output control lines to the diskette drive). Following reset, the controller is in an idle stat~:. Note that the Controller

Reset command does not require a specific bit pattern in the associated command data byte.

3-7


3-18. WRITE CONTROLLER LOW- AND

HIGH-BYTE SEGMENT ADDRESS

REGISTERS

The Write Controller Low- and High-Byte Address

Registers commands are required when the controller uses 20-bit addressing (memory address range from 0 to OFFFFFH). These commands are issued prior to initiating a diskette read or write operation to specify the 16-bit segment address. The data byte loaded into the low-order half of the register is the A4 through

All address bits, and the data byte loaded into the high-order half of the register is the A12 through A19 address bits.

7 6 5 4 3 2 1 0

IA111A101 A91 Asl A71 A61 Asl A41

LOW-ORDER SEGMENT ADDRESS

7 6 S 4 3 2 1 0

I A191 A1SIA17IA161 A1SlA141A131A121

HIGH-ORDER SEGMENT ADDRESS

During the subsequent DMA transfer, the segment address is combined with the DMAC's current address to form a 20-bit "effective" address. As shown in figure 3-2, the segment address value is offset by four bit positions and added to the current address value.

The segment address register is reset (to zero) by the

Reset Controller command.

3-19.

DISKETTE ORGANIZATION

The controller is compatible with two physical sizes of diskettes: a single- or double-sided, standard 8inch diskette that typically consists of 77 tracks and a single- or double-sided 5 Y4 -inch mini diskette that typically consists of 35 tracks. Note that the term

"cylinder" is used with double-sided drives to indicate the set of two tracks at a given head position.

The tracks are numbered sequentially (beginning at the outermost track) from 0 to 76 (standard size) or from 0 to 34 (mini size). Each track, in turn, is divided into sections or "sectors." The number of sectors on each track and the number of bytes per sector are program-determined ("soft sectoring") and are established when the track is formatted. The controller is programmed to operate in either the single-density (FM) format or the double-density

(MFM) format. Figure 3-3 and table 3-2 describe the track and sector formats for both single- and doubledensity recording, and table 3-3 defines the recording capacities for both the standard 8-inch and 5 Y4 -inch mini drives.

3-8

15 o

Figure 3-2. 20-Bit Addressing 143078-10

w

\0

J

I_

1-

I~

1 TRACK

1 SECTOR

- ,

-I-

NEXT SECTOR-j r

LAST SECTORl

fL

GAP3i GAP4B

Figure 3-3. Track Format

143078-11 o

~

~ i3 i3

S·

OQ

-

:l

... i3 o·

:l

o

1il

O;j

(j

~

00

Programming Information iSBC208

Designation

GAP4A

SYNC4

INOEXAM

GAP1

SYNC1 lOAM

10 FIELO

10CRC

GAP2

Description

Preamble gap; written by the FOC when the track is formatted.

A sequence of all-zero bytes used to synchronize the controller's data separa" tion logic prior to reading the index address mark; written by the FOC when the track is formatted.

Index address mark. Unique data pattern that identifies the logical beginning of a track; written by the FOC when the track is formatted.

Post index gap; written by the FOC when the track is formatted.

A sequence of all-zero bytes used to synchronize the controller's data separation logic prior to reading an

10 field address mark; written by the FOC when the track is formatted.

10 field address mark.

Unique data pattern that identifies the beginning of a sector 10 field; written by the FOC when the track is formatted.

Four bytes used to uniquely identify each sector on a diskette by track address, side, sector number and sector size; these bytes are supplied to the FOC by the program (format table) and written in the 10 field when the track is formatted.

A 16-bit cyclic redundancy check character derived by the FCO from the 10 address mark and the four 10 field bytes and written immediately following the 10 field when the track is formatted.

Post 10 field gap; written by the FOC when the track is formatted. Ouring sector write operations, the controller switches the drive electronics from read to write during the post 10 field gap interval.

Table 3-2. Track Format

Number of Bytes

40

FM Format

Pattern

(Hexadecimal)

FF

6

26

6

4

2

11

00

Oata=FC

Clock=07

FF

00

Oata=FE

Clock=C7

FF

Number of Bytes

80

MFM Format

Pattern

(Hexadecimal)

4E

12

4

50

12

4

4

2

00

3 Bytes C2,

1 Byte FC

4E

00

3 Bytes A1,

1 Byte FE

22 4E

3-10

iSBC208

Programming Information

Designation

SYNC 2

DATA AM

DATA FIELD

DATACRC

GAP3

GAP4B

Description

Table 3-2. Track Format (Cont'd.)

Number of Bytes

6

FM Format

Pattern

(Hexadecimal)

00 A sequence of all-zero bytes used to synchronize the controller's data separation logic prior to reading a data field address mark.

These sync bytes are rewritten by the FDC during every sector write operation.

Data field address mark.

Unique data pattern that identifies the beginning of a sector's data field; the data field address mark is written by the FDC each time the sector is written. Note that data pattern F8 (deleted data mark) is used in place of FB to identify a deleted sector.

The sector's data field. The length of the data field

(number of bytes) is programmable: 128 (singledensity only), 256, 512, 1024,

2048,4096, and 8192 (doubledensity only).

A 16-bit cyclic redundancy check character derived by the FDC from the data field address mark and the data field bytes and written immediately following the data field during sector write operations. During subsequent sector read operations, a second CRC character is calculated from the data read and compared with the CRC character previously written to verify data integrity.

Post data field gap. A prog ram-selectable gap length that separates the previous sector's data field from the next sector's ID field. The gap length specified is dependent on the recording format and sector length (see table

3-10). Note that the gap length specified differs for a format command and read Iwrite commands.

Postamble gap. A variablelength gap that follows the last sector on a track. This gap is written by the FDC when the track is formatted and extends from the end of gap 3 to the index pUlse'.

2

FB

FF

FF

MFM Format

Number of Bytes

12

Pattern

(Hexadecimal)

00

4 3 Bytes A1,

1 Byte FB

2

4E

4E

3-11


Drive

Size

Standard

8-inch

51f4-inch mini

Sectors

Per

Track

18

16

8

4

2

1

26

15

8

4

2

1 iSBC208

Table

3-3.

Recording Capacities

Bytes Per Sector

Single Density

(FM)

Double Density

(MFM)

128

256

512

1024

2048

4096

128

128

256

512

1024

2048

256

512

1024

2048

4096

8192

256

256

512

1024

2048

4096

Bytes Per Track (Formatted)

Single Density

(FM)

Double Density

(MFM)

3328

3840

4096

4096

4096

4096

2304

2048

2048

2048

2048

2048

6656

7680

8192

8192

8192

8192

4608

4096

4096

4096

4096

4096

3-20. FDC COMMANDS

The FDC is capable of executing 12 unique commands. Of these 12 commands, all but one (the Sense

Interrupt Status command) require a multibyte transfer from the host processor to initiate command execution. Following the execution of most commands, the host processor must initiate a multibyte transfer from the FDC to determine the outcome of the operation and to terminate the command. Table

3-4 lists the FDC commands and the number of bytes required to initiate and to terminate the command.

Table

3-4.

FOC Commands

Command

Specify

Seek

Read Data

Read Deleted Data

Read ID

Read Track

Write Data

Write Deleted Data

Format Track

Recalibrate

Sense Drive Status

Sense Interrupt Status

Command

Bytes

6

2

2

1

2

9

9

9

3

3

9

9

Result

Bytes

0

1

2

7

7

7

7

7

7

0

0

7

FDC command processing consists of three phases that are entered in the following sequence:

1. Command Phase. The host processor initiates command processing by writing one or more bytes to the FDC's data register. Depending on the command to be executed, up to nine bytes may be required before the execution phase.can be entered.

2. Execution Phase. The operation specified during the command phase is performed. The execution phase is entered automatically when the last command byte is received. Since the controller uses

DMA for all data transfers to and from the diskette, no host IProcessor intervention is required during the execution phase.

3. Result Phase. Following command execution, the FDC enters the result phase. With most commands, the FDC generates an interrupt to inform the host processor of the completion of the execution phase. To complete the result phase the host processor must read a series of bytes from the FDC's data register.

During the command and result phases, the main status register must be read by the host processor to determine when the FDC is ready to provide or accept the next command or result byte to be written or read from the data register as described in section

3-13. Note that during multibyte transfers to or from the FDC's data register, a delay interval must be inserted between each byte read or written to allow time for the FDC to upda.te the main status register

(see "wait" routines in the sample drivers in

Appendix A).

During the execution phase of commands that transfer data to or from the diskette, the FDC generates a DMA request for each byte transferred.

The DMAC responds to the DMA request with a

DMA acknowledge to reset the DMA request. When the transfer is complete (terminal count received from the DMAC), the FDIC generates an interrupt to indicate the beginning of the result phase. When the host processor reads the first byte from the FDC's data register (status byte STO), the FDC automatically clears the interrupt. The host processor must read all of the result bytes to complete the command; the FDC will not accept a new command until the current command is completed.

3-12


The FDC contains five status registers. The main status register, as previously mentioned, is read by the host processor during the command and result phases. The other four status registers (STO, STl,

ST2 and ST3) are read directly from the FDC's data register during the result phase. The status registers presented are determined by the FDC command executed. Table 3-5 defines the contents of the four result status registers.

The writing and reading of the command and result bytes to and from the FDC's data register must be performed in the order shown by the command format tables given in the individual FDC command descriptions. After the last command byte is written to the FDC, the execution phase starts automatically.

During the execution phas1e of commands that write data to or read data from the diskette, the number of bytes transferred is determined by the word-count value loaded into the DMAC. The DMAC signals the

FDC when the programmed number of bytes have been transferred; the FDC then stops the transfer, interrupts the host processor, and enters the result phase. When the host processor reads the last result byte from the FDC's data register, the command is completed and the FDC is prepared to accept a new command.

Table 3-6 defines the mnemonics used in the command format tables for the individual commands.

Bit(s)

07,06

05

04

03

02

01,00

Name

Interrupt Code

Seek End

Equipment Check

Not Ready

Head Address

Unit Select

Table 3-5. Result Phase Status Registers

Symbol

IC

SE

Status Register 0 (STO)

Description

07=0 and 06=0

Normal Termination of Command. Command execution was completed successfully.

07=0 and 06=1

Abnormal Termination of Command. Command execution was initiated, but was not completed successfully.

07=1 and 06=0

Invalid Command Issued. Command execution was not initiated.

07=1 and 06=1

Ready Change. During command execution the drive went Not

Ready.

Set (05=1) when the FOC completes execution of a Seek command.

Note that there is no result byte associatHd with a Seek command; the host processor must issue a Sense Interrupt Status command to access the STO status byte. When parallel (overlapped) seeks are performed on multiple drives, this bit is set by the first drive to complete its seek (the drive completing its seek is identified by unit select bits DO and 01). When performing overlapped seeks, the main status register must be examined to determine when the other drives have completed their seeks.

EC

NR

HO

US

Set when the addressed drive activates its FAULT 1 signal to the controller or when during execution of a Recalibrate command, a

TRACK 01 signal is not received from the addressed drive after 77

STEPI pulses have been issued. Note tilat if a FAULT 1 signal is received during command execution, the operation is terminated immediately.

Set when a command that accesses the drive is issued and the drive is in a not-ready state or when a diskette read or write command, which specifies side 1 of a single-sided drive, is issued. The command issued is not executed.

Indicates the state of the head (side selected) when the interrupt was generated (0 = side 0, 1 = side 1).

Indicates the drive unit number of the drive addressed when the interrupt was generated.

01 =0,00=0 = DRIVE UNIT 0

01=0,00=1 = DRIVE UNIT1

01=1,00=0 = DRIVE UNIT 2

01=1,00=1 = DRIVE UNIT 3

3-13


06

05

04

Bit(s)

07

03

02

01

DO

07

06

05

04

03,02

01

DO

Name

End of Cylinder

Not Used

Data Error

Overrun

Not Used

No Data

Not Writable

Missing Address

Mark

Not Used

Control Mark

Data Error in

Data Field

Wrong Cylinder

Reserved

Bad Cylinder

Missing

Address Mark in

Data Field

Table 3-5. Result Phase Status Registers (Cont'd.)

Symbol

EN

DE

Status Register 1 (ST1)

Description

Set (07=1) during a multisector transfer when the starting sector number and the number of bytes to be transferred exceeds the last logical sector on the track or cylind~r (multitrack transfers). The data transfer is terminated by the FOG when the data from the last logical sector on the track or cylinder is transferred.

This bit is always 0 (reset).

Set when the FDC detects a CRC error in either the field.

10 field or data

OR

NO

Set when the OMAC did not respond to a data request within the allotted time interval to prevent loss of data. When an overrun condition occurs, the operation is terminated immediately.


Set during execution of diskette read/write commands when the currently-addressed sector cannot be located within one full revolution of the diskette (Le., two index pulses encountered). This bit usually indicates an improperly formatted diskette or, when the WC bit in status register 2 also is set, indicates that the head ia positioned over the wrong track. During execution of a Read Track command, the NO bit is set when the FDC cannot locate the 10 field of the first sector following the index mark.

NW

MA

CM

DO

Set during execution of a Write Data, Write Deleted Data or Format

Track command if the WRITE PROTECT signal from the drive is active. The Write operation is immediately aborted, and no data is written on the diskette.

Set during execution of diskette read/write operations if an 10 address mark cannot be found within one revolution of the diskette

(usually indicates that an unformatted diskette has been installed in the drive). This bit also is set during diskette read operations if the addressed sector's data address mark (or deleted data address mark) is not encountered (the MD bit in status register 2 also will be set).



Set during execution of a Read Data command when a deleted data address mark is encountered or set during execution of a Read

Deleted Data command when a (normal) data address mark is encountered.

Set during diskette read operations when a CRC error is detected in the data field. Note that since this bit is only set afJer the sector is read, the data transferred must be considered invalid.

WC

BC

MD

Set when the cylinder (track) address specified does not match the cylinder address byte read from a sector's 10 field. Note that the NO bit in status register 1 also will be set.

These bits are 0 (reset).

Set when. a diskette read/write 0pElration is attempted on a defective "bad" track (bad tracks are designated by writing a byte of FFH in the cylinder address byte of each 10 field on the defective track using the format track command). Note that the WC bit and the

NO bit in status register 1 also will be set.

Set during diskette read operations when the addressed sector's data address mark (or deleted data address mark) is not encountered before the next sector's ID address mark is read. Note that the MA bit in status register 1 also will be set.

3-14


05

04

03

Bit(s)

07

06

02

01,00

Symbol

C

0

07-00

DSO,OS1

DTL

EOT

GPL

H

HDS

HLT

HUT

MFM

MT

Name

Fault

Write Protected

Ready

Track 0

Two Sided

Head Address

Unit Select

T

bl

-

R esu t Phase

~~

Symbol

FT

WP


Description

Set when the FAULT I signal from the addressed drive is active.

Set when the WRITE PROTECT I signal from the addressed drive is active.

ROY

TO

TS

HO

Set when the READY I signal from the addressed drive is active.

Set when the TRACKO/ signal from the addressed drive is active.

Set when the TWO SIDED/ signal from the addressed drive is active.

Indicates the state of the SIDE SELECT I signal to the drive (0 = side

0,1=side1).

US Indicates the drive unit number of the drive addressed by the Sense

Drive Status command:

01=0,00=0 = DRIVE UNITO

01=0,00=1 = DRIVE UNIT 1

01=1,00=0 = DRIVE UNIT 2

01=1,00=1 = DRIVE UNIT 3

Name

Cylinder Number

Data

Data Bus

Drive Select

Data Length

End of Track

Gap Length

Head Address

Head Select

Head Load Time

Head Unload Time

Mode Select

Multitrack

Table 3-6. Command Mnemonics

Description

The cylinder (track) number. In the result phase, C defines the current location

(track address) of the drive's read/write head(s).

The data pattern (filler byte) to be written into each sElctor's data field when the track is formatted.

The a-bit data bus to/from the FDC's data register. Bit DO is the least-significant bit.

The drive unit addressed by the command:

DS1 =0, DSO=O = DRIVE UNIT 0

DS1 =0, DSO=1 = DRIVE UNIT 1

DS1 =1, OSO=O = DRIVE UNIT 2

DS1 =1, DSO=1 = DRIVE UNIT 3

Specifies non-standard data transfer length for diagnostic use only. For normal diskette transfer operations, the DTL value specified must be FFH.

The sector number of the last logical sector on a track.

The number of bytes to be writteninto Gap 3 (see table 3-10).

The head (side) selected (0 = side 0,1 = side 1). In the command phase, Hand

HDS are the same value; in the result phase, H reflects the state of the side select signal on interrupt.

The read/write head addressed by the command (0 = head 0, 1 = head 1).

The head load time interval in the Specify command. The HL T value specified corresponds to the drive's head load time specification (see table 3-9).

The head unload time interval in the Specify command. The HUT value specifies the time interval that the head remains loaded following a read or write operation (see table 3-7).

The recording mode selected (0 = FM mode, 1 = MFM mode).

When set (MT=1), permits multisector read/write operations on the two tracks at the same cylinder address (Le., an operatron that begins on a track on side 0 can be continued on the same track on side 1).

3-15


iSBC208

R/W

SC

SK

SRT

STO

ST1

ST2

ST3

SYMbol

N

NCN

PCN

R

Nlme

Number

New Cylinder

Number

Present Cylinder

Number

Record

Read/Write

Sector Count

Skip

Step Rate Time

Status Register 0

Status Register 1

Status Register 2

Status Register 3

Table 3-6. Command Mnemonics (Cont'd.)

Description

A number (N) that represents the length of a sector; the sector length (number of data bytes) is equal to 128 x 2N.

The cylinder address value specified during the command phase of a Seek command.

The current position (cylinder address) of the read lwrite head(s).

The record (sector) number. During the command phase, R specifies the (first) sector to be accessed; during the result phase, R indicates the number of the next logical sector number to be accessed.

The direction of the I/O transfer between the host processor and" the FDC's data register.

The number of sectors to be formatted on a track.

When set (SK=1) during a Read Data command, causes the FDC to "skip over" any sectors with a deleted data address mark (when SK=O, the deleted sector is transferred and the command is terminated).

When set during a Read Deleted Data command, causes the FDC to "skip over" any sectors with a (normal) data address mark (when SK=O, the "n6ndeleted" sector is transferred and the command is terminated).

The step rate time interval in the Specify command. The SRT value specified corresponds to the drive's step rate specification (see table 3-8).

One of the four status registers that are read by the host processor during the result phase to determine the outcome of command execution. The status registers can only be read after a command has been executed (Le., after an interrupt) and contain information relevant only to the command executed.

3-21. SPECIFY COMMAND

The specify command requires three bytes to load the command and command data. Since this command only loads information into the FOC for future commands, there is no execution or result phase.

DATA BUS

PHASE R/W 0 7 0 6 05 D. 0 3 O2 0,

Command

Remarks

Do

1 W 0 0 0 0 0 0

W - S R T - " ' - H U T ..

0

W HLT

1 Command Codes

The specify command sets the initial values for the three internal timers that define the drive's head load time and step rate characteristics to the FOC and the

FOC's head unload time interval. Accordingly, a

Specify command must be executed prior to executing any command that accesses the drive. The

Head Unload Time (HUT) value defines the time from the end of the execution phase of a read/write command to the head unload state. This timer is 'programmable from 16 to 240 ms in 16 ms increments as shown in table 3-7. The Step Rate Time (SRT) value defines the time interval between step pulses sent to

D3

0

0

0

1

0

0

0

0

1

1

1

1

1

1

1 the drive from the FOC. This timer is programmable from 1 to 16 ms in 1 ms iincrements as shown in table

3-8. The SRT value must be set to 1 ms greater than the minimum desired step rate interval. The Head

Load Time (HL T) value defines the time between activation of the HEAO LOAO signal and the initiation of a read or write operation. This timer is programmable from 2 to 254 ms in increments of

2 ms as shown in table 3-9.

D2

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

Table

3-7.

HUT Values

D1

1

0

0

1

1

0

0

1

1

0

1

1

0

0

1

Do

0

1

0

1

1

0

1

1

0

1

0

1

0

0

1

HEX

7

8

9

A

8

C

D

E

F

1

2

3

4

5

6

HUT TIME

16 ms

32 ms

48ms

64 ms

80ms

96ms

112 ms

128 ms

144 ms

160 ms

176ms

192 ms

208 ms

224 ms

240 ms

3-16


The time intervals mentioned in the previous paragraph are a direct function of the clock frequency. The times indicated are for an 8 MHz clock; if the clock frequency is reduced to 4 MHz (minifloppy applications), .all time intervals are increased by a factor of two.

Table 3-8. SRT Values

0

7

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

6

0

0

0

0

1

1

1

0

0

0

1

1

1

1

1

0

0

5

1

0

0

0

0

1

1

1

0

0

1

1

1

1

0

0

0

4

1

0

1

0

1

0

0

1

0

1

0

1

0

1

0

1

HEX

F

E

0

C

B

A

9

8

7

6

5

4

3

2

1

0

'The SRT must be set to 1 ms greater than the minimum desired step interval time.

'SRTTIME

9ms

10 ms

11 ms

12 ms

13 ms

14 ms

15 ms

16 ms

1 ms

2ms

3ms

4ms

5ms

6ms

7ms

8ms

DATA BUS

PHASE R/W D7 D8 Ds D4 D3 D2

Dl Do

Command W 0 0 0 0 1 1 1 1

Remarks

Command Codes

W 0 0 0 0 0 HDS OS1 OSO

W NCN

Execution Head is positioned over proper Cylinder on

Diskette

During execution of a Seek command, the read/write head(s) in the addressed drive (DS1, DSO) are moved

(stepped) from cylinder to cylinder by the FDe. The

FDC compares the Present Cylinder Number (PCN), which is the current head position, with the New

Cylinder Number (NCN) specified in the command and performs the following operation when there is a difference:

• When NCN is less than PCN, the FDC sets the

DIRECTION signal to a "1" (step out toward track 0) and issues STEP pulses to the drive.

• When NCN is greater than PCN, the FDC sets the DIRECTION signal to a "0" (step in toward spindle) and issues STEP pulses to the drive.

Table 3-9. HLT Values t8

0

7

0

6

0

5

0

4

0

3

O

2

°

1

Do HEX

0 0 0 0 0 0 1 0 02

0 0 0 0 0 1 0 0 04

0 0 0 0 0 1 1 0 06

0 0 0 0 1 0 0 0 08

1 1 1 0 1 0 0 0 E8

1 1 1 0 1 0 1 0 EA

1 1 1 0 1 1 0 0 EC

1 1 1 0 1 1 1 0 EE

1 1 1 1 0 0 0 0 FO

1 1 1 1 0 0 1 0 F2

1 1 1 1 0 1 0 0 F4

1 1 1 1 0 1 1 0 F6

1 1 1 1 1 0 0 0 F8

1 1 1 1 1 0 1 0 FA.

1 1 1 1 1 1 0 0 FC

1 1 1 1 1 1 1 0 FE

HLTTIME

2ms

4ms

6ms

8ms

232 ms

234 ms

236 ms

238ms

240 ms

242 ms

244ms

246ms

248ms

250ms

252 ms

254 ms

~R

The step rate is determined by the SRT value in the

Specify command. After each STEP pulse is issued,

NCN is compared with PCN. When NCN equals

PCN, the SE flag is set in status register 0 and tI:te command is terminated. At the termination of the

Seek command, the interrupt line to the host processor is activated; the host processor must perform a

Sense Interrupt Status command to determine if the seek was successful.

During the command phase, the FDC is in the busy state, but during the execution phase, the FDC is in its non-busy state. When the FDC is not busy, a Seek command may be issued to another drive. In this manner, parallel (overlapped) seek operations may be performed on up to four drives.

If the drive's READY signal is not active at the beginning of the command execution phase or if it goes inactive during the seek operation, the NR bit in

Status Register 0 is set and the command is terminated.

3-22. SEEK COMMAND

The Seek command requires three bytes to load the command and command data.

A Seek command must be executed prior to the execution of any command that acc~sses data on a track other than the track currently positioned under the read/write head(s).

3-23. READ DATA

The Read Data command requires nine bytes to load the command and command data. Following command execution, the host processor must read seven bytes from the FDC to complete the result phase.

3-17


DATA BUS

PHASE R/W 0 7 0 6 05 0 4 0 3 O2 0, Do

Command W MT MFM SK 0 0 1 1

Remarks

0 Command Codes

Execution

Result R

R

R

R

R

R

R

W

W

W

W

W

W

W

W 0 0 0 0 0 HDS DSl DSO

C

H

R

N

EOT

GPL

DTL

Sector 10 informatibn prior to

Command execution

STO

ST1

ST 2

C

H

R

N

Data transfer from diskette to host memory

Status information after Command execution

Sector ID informaticn after Command execution

After the last command byte is received, the FOC loads the read/write heads (if they are not loaded) at the current cylinder location, waits the specified head-settling time and then begins reading sector

10 fields to locate the addressed sector (the sector number specified in byte 5 of the command). When the addressed sector is located, the FOC remains in the read mode to locate the data address mark at the beginning of the data field. After reading the data address mark, the FOC assembles the serial data from the data field into 8-bit bytes that are transferred, under direction of the OMAC, from the FOC's data register to host memory.

The number of bytes transfl:!rred is dependent on the word count value loaded into the OMAC. If the word count specified is less than a full sector, only the number of bytes specified are transferred; the FOC always reads a complete sector (to access the data field CRC bytes) in order to verify the data transfer. Conversely, if the word count value specified is greater than a sector, the FOC internally increments the sector number (R +

1) and begins reading from the next logical sector on the track. The FOC will continue to read sectors until the word count is satisfied (terminal count reached) or until the last logical sector on the track is reached. If the MT (Multitrack) bit is set in the command byte, a transf,er beginning on side 0 of a double-sided drive can extend to the last sector on side 1 (of the same cylinder). Table 3-10 outlines the EOT and GPL command byte values for the various sector sizes in both the FM and MFM recording modes.

When the transfer is complete (or if the transfer cannot be completed), the FOC interrupts the host processor, initiates the head-unload timeout, and enters the result phase. The host processor must then read the seven result bytes from the FOC's data register. The first three bytes read are the STO, STl, and ST2 status register bytes that indicate the outcome of the operation. The last four bytes reflect the updated values for C, H, R, and N (result phase ID information) when the FDC completes command execution. Table 3-11 specifies the ID information for normal (no error detected) command termination.

During normal read operations (SK bit in command byte not set), if a deleted data address mark is encountered at the beginning of a sector's data field, the data from the deleted sector is transferred to host memory and the read operation is terminated

(irrespective of the word count specified). The CM

Table 3-10. Command Byte Values

Mode

Single

Density.

(MFM=O)

Double

Density

(MFM=1)

Bytes

Per

Sector

(deCimal)

256

256

512

1024

2048

4096

8192

128

128

256

512

1024

2048

4096

01

01

02

03

04

05

06

Sector

Size

(N)

Sectors

Per

Track

(decimal)

Standard a-inch Drives

Last

Sector

(EOT)

Gap3 Length (GPL)

R/W Format

Sectors

Per

Track

(decimal)

51/4-inch Mini Drives

Last

Sector

(EOT)

Gap3 Length (GPL)

R/W Format

00

00

01

02

03

04

05

26

--

15

8

-

26

15

8

4

2

1

4

2

1

1A

-

OF

1A

-

OF

08

04

02

01

08

04

02

01

-

07

OE

18

47

C8

C8

OE

-

18

35

99

C8

C8

1B

-

2A

3A

8A

FF

FF

-

36

54

74

FF

FF

FF

18

16

8

4

2

-

1

18

16

8

4

2

-

1

12

10

08

04

02

01

-

12

10

08

04

02

01

-

OA

20

2A

80

C8

C8

-

07

10

18

46

C8

C8

-

OC

32

50

FO

FF

FF

-

09

19

30

87

FF

FF

-

Unless otherwise specified, all values are in hexadecimal.

3-18

MT EOT

0

1

*NC = no change

1A

OF

08

04

02

01

1A

OF

08

04

02

01

1A

OF

08

04

02

1A

OF

08

04

02

01

1A

OF

08

04

02 iSBC208


(Control Mark) bit in Status Register 2 will be set, and the R (sector number) result byte will contain the number of the deleted sector. During read operations with the SK bit set (SK=I), if a deleted data address mark is encountered, the FDC skips over the deleted sector and reads the next logical (non-deleted) sector.

When the operation is complete (i.e., when terminal count is reached), the CM bit will be set to indicate that a deleted sector was encountered during the transfer, and the R result byte will be incremented to the next sequential sector number.

When a Read Data command cannot be completed due to an error condition, the FDC sets the Interrupt

Code (IC) bits in Status Register 0 to indicate abnormal termination of the command (07 = 0,

06 = I) and sets specific bits in Status Registers 1 and 2 to indicate the nature of the error.

During DMA transfers between the controller and host memory, the FDC must be serviced within 27 us in the FM mode or within 13 us in the MFM mode to prevent data from being overwritten. If the FDC is not serviced within the above time limits (usually caused by a bus contention problem), the FDC terminates the transfer (abnormal termination) and sets the OR (Overrun) bit in Status Register I.

3-24. READ DELETED DATA

The Read Deleted Data command, like the Read

Data command, requires nine bytes to load the command and command data. Following command execution, the host processor must read seven bytes from the FDC to complete the result phase.

Execution of a Read Deleted Data command is identical to the Read Data command description in the previous section except for the handling of data field address marks. During a read deleted data operation in the non-skip mode (SK bit = 0 in the command byte), if a (normal) data address mark is encountered at the beginning of the sector's data field, the data from the sector is transferred and the read operation is terminated (irrespective of the word count specified). The CM bit in Status Register 2 will be set, and the R result byte will contain the number of the

Table 3-11. Result Phase 10 Information

Result Phase 10 Information

Last Sector Transferred

C H R

Sector 1 thru 25 (Side 0 or 1)




Sector 1 (Side 0 or 1)

NC* NC R+1



Sector 8(SideOor1)









Sector 26 on Side 0

Sector 15 on Side 0

Sector 8 on Side 0

Sector 4 on Side 0

Sector 2 on Side 0

Sector 1 on Side 0

Sector 26 on Side 1

Sector 15 on Side 1

Sector 8 on Side 1

Sector 4 on Side1

Sector 2 on Side 1

Sector 1 on Side 1

C+1

NC

NC

C+1

NC

NC

H=01

H=OO

R=01

R+1

R=01

R=01

N

NC

NC

NC

NC

NC

3-19


DATA BUS

PHASE R/W 0 7 0 6 Os 0 4 0 3 O

2

0 1 Do

Command W MT MFM SK 0 1 1 0 0

Remarks

Command Codes

0 0 W

W

W

W

W

W

W

W

0 0 0 HOS DS1 DSO

C

H

R

N

EOT

GPL

DTL

Sector 10 information prior to

Command execution

Execution Data transfer from diskette to host memory

Result R

R

R

R

R

R

R

STO

ST1

ST2

C

H

R

N


Sector 10 information after Command execution

When the first valid ID field is read, the FOe interrupts the host processor, initiates the head-unload timeout, and enters the result phase. The host processor must read the seven result bytes to complete the command; the e, H, R, and N result bytes contain the corresponding ID field byte values read from, the ID field (Le., the value returned in the e result byte indicates the current track address).

During the command execution phase, if an ID field address mark cannot be found within one full revolution of the diskette (e.g., if the track is not formatted), the FOe sets the MA (missing address mark) bit in Status Register 1 and sets the interrupt code bits in Status Register 0 to indi<;ate abnormal termination. non-deleted sector_During execution of a Read

Deleted Data command with the SI( bit set in the command byte, if a (normal) data address mark is encountered, the FOe skips over the "non-deleted" sector and reads the next logical deleted sector. When the operation is complete (Le., when terminal count is reached), the eM bit will be set to indicate that a non-deleted sector was encountered during the transfer and the R result byte will be incremerited to the next sequential sector number.

3-25. READ ID

The READ ID command requires two bytes to load the command and command data. Following command execution, the host processor must read seven bytes from the FOe to complete the result phase.

DATA BUS

PHASE R/W 0 7 0 6 Os 0 4 0 3 O

2

Command W 0 MFM 0 0 1 0

0

1

1

Do

Remarks

0 Command Codes

W 0 0 0 0 0 HDS DS1 DSO

Execution

Result R

R

R

R

R

R

R

SlO

ST1

ST 2

C

H

R

N

The first correct 10 information on the Irack is stored in Data Register


Sector 10 informaticn during Execution

Phase

3-26. READ TRACK

The Read Track command requires nine bytes to load the command and command, data. Following command execution, the host processor must read seven bytes from the FOe to complete the result phase.

DATA BUS

PHASE R/W 0 7 0 6 Os 0 4 0"

Command W 0 MFM 0 0 0

°2 0 1 Do Remarks

1 0 0 Command Codes

W

W

W

W

W

W

W

W

0 0 0 0 0 HDS DS1 DSO

C

H

R

N

EOT

GPL

DTL

Sector 10 information prior to

Command execution

Execution

Result R

R

R

R

R

R

R

STI)

ST'I

ST2

C

H

R

N

Data transfer from diskette to host memory, FDC transfers all sectors wi h first sector following index


Sector 10 information after Execution Phase for this command.

The Read 10 command allows the host processor to verify the current position of the drive's read/write heads without initiating a data transfer. During-command execution, the FOe loads the h.eads and waits the specified head-settling time (if the heads are unloaded) and begins searching for a sector II) field.'

The Read Track command operates similar to the

Read Data command except that all sector data fields on the addressed track are read, beginning with the first sector following index, in their order of physical appearance on the track. During the transfer the

FOe ignores 10 and data field eRe errors and deleted data address marks (Le., sectors with errors and deleted sectors are transferred)_ Note that multitrack and skip operations are not permitted with the Read Track command.

3-20


3-27. WRITE DATA

The Write Data command requires nine bytes to load the command and command data. Following command execution, the host processor must read seven bytes from the FDC to complete the result phase.

DATA BUS

PHASE R/W 0 7 06 0

5 D.

0

3

.02 0, DO

Command W MT MFM 0 0 0 1 0 1

Remarks

Command Codes

W 0 0 0 0 0 HOS DS, DSO

W

W

W

W

W

W

W

C

H

R

N

GPL

EOT

DTL

Sector ID information prior to

Command execution

Execution

Result R

R

R

R

R

R

R

STO

STI

ST2

C

H

R

N

Data transfer from host memory to diskette


Sector ID information after Command execution

The command data bytes for the Write Data command are identical to the command data bytes for the

Read Data command (see section 3-23). After the last command byte is received, the FDC loads the read/write heads, waits the specified head-settling time, and then begins reading sector ID fields to locate the addressed sector (the sector number

~pecified in byte 5). After the addressed sector is located, the FDC switches the drive to the write mode during the post ID field gap and updates (writes) the sector's sync field and data field address mark.

Immediately after writing the address mark, the FDC begins writing the data bytes received at its data register onto the diskette as a serial bit stream.

The number of bytes written is dependent on the word count value loaded into the DMAC. If the word count specified is less than a full sector, only the number of bytes specified are transferred to the

FDC; the FDC fills the remainder of the data field with zeros. After the last data field bit is written, the

FDC writes the 16-bit data field CRC character. If the word count specified is greater than a sector, the

FDC internally increments the sector number and, after locating (reading) the next sector's ID field, begins writing the sector data field. The FDC will continue to write sectors until the word count is satisfied (terminal count reached) or until the last logical sector on the track is written. If the

Multitrack bit is set in the command byte, a write operation beginning on side 0 of a double-side drive can extend to the last sector on side 1 (of the same cylinder).

When the transfer is complete (or if the transfer cannot be completed), the FDC interrupts the host processor, initiates the head-unload timeout, and enters the result phase. The host processor must then read the seven result bytes from the FDC's data register. As described under the Read Data command, the first three bytes indicate the outcome of the operation, and the last four bytes reflect the updated values for C, H, R, and N.

During DMA transfers between the controller and host memory, the FDC must receive the data byte to be written within 31 us in the FM mode or within 15 us in the MFM mode to prevent data from being underwritten. If the FDC is not serviced within the above time limits (usually caused by a bus contention problem), the FDC terminates the operation

(abnormal termination) and sets the OR (Overrun) bit in Status Register 1.

3-28. WRITE DELETED DATA

The Write Deleted Data command is identical to the

W rite Data command previously described except that a deleted data address mark is written at the beginning of the sector's data field in place of a data address mark.

DATA BUS

PHASE R/W 0 7 06 0

5 D.

0

3 O2

0, DO

Command W MT MFM 0 0 1 0 0

Remarks

1 Command Codes

W

W

W

W

W

W

W

W

0 0 0 0 0 HDS DSI DSO

C

H

R

N

GPL

EOT

DTL

Sector ID information prior to

Command execution

Execution Data transfer from host memory to diskette

Result R

R

R

R

R

R

R

STO

STI

ST2

C

H

R

N


Sector ID information after Command execution

3-29. FORMAT TRACK

The Format Track command requires six bytes to load the command and command data. Following command execution, the host processor must read seven bytes from the FDC to complete the result phase.

3-21


PHASE R/W 0 7 0 6 0 5 0 4 0 3 O

2

Command W 0 MFM 0 0 1 1

W

0 1

DO Remarks

0 1 Command Codes

0 0 0 0 0

HOS OSl OSO

W

W

W

W

DATA BUS

N

SC

GPL

0

Byles/Sector

Sectors/Track

GapS

Filler Byte

Execution FOC formats an entire track

Result R

R

R

R

R

R

R

STO

STI

ST2

C

H

R

N


In this case, the

10 information has no meaning

The Format Track command formats or "initializes" a track by writing the ID field, gaps, sync bytes, and address marks for each sector. The track to be formatted is determined by the position of the read/write heads on the diskette. Prior to command execution, a table in memory containing the ID field values (track address, head address, sector number and sector size) for each sector on the track must be prepared. (During command execution, the FDC uses the values from the table to write the individual

ID fields.) Referring to the track format illustration

(figure 3-3), address marks are written automatically by the FDC. The track (C) and head (H) addresses, sector number (R) and sector size (N) byte values to be written into the ID field are taken, in order, from the table. The ID field CRC character is derived from the ID address mark and ID field data, and is written immediately following the ID field" Gaps and sync fields are written automatically by the FDC; the length of the post data field gap (gap 3) is determined by the GPL command data byte value. The number of data bytes per sector and the number of sectors per track are determined by the Nand SC command data byte values; the data pattern written into each byte of each sector's data field is determined by the D command data byte value. The data field CRC character is derived from the data address mark and the data written in the sector's data field.

Since the sector number is taken directly from the formatting table, tracks can be formatted either sequentially (the first sector following the index mark is assigned sector number 1, the next adjacent sector is assigned sector number 2, and so on) or sector numbers can be "interleaved" on a track.

The sequential sector format optimizes sector access times during multisector transfers by permitting a number of sectors (up to an entire track) to be transferred within a single revolution of the diskette.

Sector interleaving is used when a number of logically-consecutive sectors are to be transferred individually and the processing time between adjacent sectors is greater than the time required to access the next sector.

As an example of sector interleaving, assume that a number of consecutive sectors are to be transferred individually on both a sequentially formatted track and on a track that utiliz.es sector interleaving. On a sequentially formatted track, assuming that the amount of processing time required between sectors is greater than the time required to access the next sector, the diskette must rotate nearly a full revolution to access the next sector to be transferred. Since one diskette revolution requires approximately 167 milliseconds, to transfer an entire track of 15 sectors,

15 revolutions, or 2.5 s(!conds, are required. Conversely, if sector numbers are assigned with an interleaving factor of three (see figure 3-4), the processing time between logically-adjacent sectors is increased substantially and, if sufficient, allows the complete track to be transferred in three revolutions of the diskette (500 milliseconds).

The following table (table 3-12) describes the organization of the formatting table that would be used to format the diskette shown in figure 3-4.

The order of sector number assignment on the track is taken directly from the formatting table in memory. Four entries are required for each sector: a track address, a head address, the sector number and a sector size. Note that the order of sector number entries in the table is the sequence in which sector numbers appear on the track when it is formatted.

The number of 4-byte entries in the table must equal the number of sectors on the track. Caution must be exercised when creating the formatting table since entries are not verified by the FDC and it is possible to fo~mat a track with an il1egal, redundant, or missing sector number.

INDEX MARK . -

Figure 3-4. Sector Interleaving 143078-12

3-22


5

6

7

1

2

3

4

8

9

10

11

12

Byte

Table 3-12. Formatting Table

Function

Track Address (C)

Head Address (H)

Sector Number 1 (R)

Sector Size (N)

Track Address

Head Address

Sector Number 6

Sector Size

Track Address

Head Address

Sector Number 11

Sector Size

Data

Contents

(Hexadecimal)

06

OX

XX

OX

08

OX

XX

OX

01

OX

XX

OX

3-30. RECALIBRATE

The Recalibrate command requires two bytes to load the command and command data.

DATA BUS

PHASE

Command

R/W 0 1 0 6 05 D. 0 3 O2 0, Do

W 0 0 0 0 0 1 1

Remarks

1 Command Codes

W 0 0 0 0 0 0 DS1 DSO

Execution Head retracted to Track 0

57

58

59

60

53

54

55

56

Track Address

Head Address

Sector Number 10

Sector Size

Track Address

Head Address

Sector Number 15

Sector Size

XX

OX

OA

OX

XX

OX

OF

OX

Following the command phase, the FDC loads the read/write heads at the current cylinder location, waits the specified head-settling time and monitors the INDEX signal from the drive. When the INDEX signal goes active (index hole detected), the FDC begins formatting the track according to figure 3-3.

After writing the ID address mark for the first sector, the FDC writes the first four bytes from the format table into the ID field (the FDC initiates a DMA transfer and receives the requested bytes at its data register). The FDC writes the remainder of the sector based on the command data received during the command phase. After writing the first sector's post-data field gap, the FDC writes the sync field and ID address mark for the next sector and writes the next four bytes from the format table into the second sector's ID field. This formatting operation continues until the FDC writes the number of sectors specified by the SC command data byte. When the index mark is encountered, the FD~ interrupts the host processor, initiates the head-unload timeout, and enters the result phase. The host processor must read the seven result bytes to complete the command. Note that the C, H, R, and N result bytes are irrelevant with the Format Track command.

Prior to formatting a track, the DMAC's base and current address registers (and, if required, the controller's segment address registers) must point to the first byte of the format table in memory. The DMAC word count specified must be equal to (or greater than) the number of byte entries in the format table

(i.e., to format a track with 26 sectors, 104 bytes must be transferred).

The Recalibrate command pOSitIOns the drive's read/write heads at a known track position and is used following power-up or a seek error (e.g., WC bit set in Status Register 2). During command execution, the FDC sets the PCN (present cylinder number) counter to zero and monitors the TRACKO/ signal from the drive. As long as the TRACKO/ signal remains inactive, the FDC holds the DIRECTION/ signal high (l) and issues up to 77 STEP/signals to the drive (to step the read/write heads toward track

O). When the TRACKO/ signal goes active, the FDC interrupts the host processor and sets the SE (seek end) bit in status register O. Since the Recalibrate command does not have a result phase, the host processor must issue a Seek Interrupt Status command to properly terminate the Recalibrate command and to clear the interrupt.

During the command phase, the FDC is in a busy state, but during the execution phase, the FDC is in a non-busy state. When the FDC is not busy, a recalibrate (or seek) command can be issued to another drive. In this manner, parallel (overlapped) recalibrate operations can be performed on up to four drives concurrently.

During the execution phase, if the TRACKO/ signal does not go active following 77 STEP/pulses, the

FDC sets both the EC (equipment check) and the SE bits in Status Register processor.

0 and interrupts the host

NOTE

When executing a Recalibrate command on a drive with more than 77 tracks, if the drive's read/write head is positioned on track 77 or greater when the command is executed, an abnormal termination will result (EC bit set in status register O). A second Recalibrate command must be issued to complete the recalibrate operation and to position the read/write head over track O.

3-23


3-31. SENSE DRIVE STATUS

The Sense Drive Status command requires two bytes to load the command and command data. Note that there is no execution phase associated with the command, and no interrupt is generated. After the command is loaded, the host processor must read one result byte to complete the result phase.

DATA BUS

PHASE R/W D7 D. D5 Dc D3 D2 D, Do

Command W 0 0 0 0 0 I 0 0

Remarks

Command Codes

W 0 0 0 0 0 HOS. OSI OSO

Result R ST3 Status information regarding selected drive

The Sense Drive Status command is used to interrogate the FDC regarding the status of the drive selected during the command phase. The result byte read (Status Register 3) contains the drive status information (see section 3-5).

3-32. SENSE INTERRUPT STATUS

The Sense Interrupt Status command requires one byte to load the command. Note that there is no execution phase associated with the command. After the command is loaded, the host processor must read two result bytes to complete the result phase.

DATA BUS

PHASE R/W D7 D6 D5 0 4 D3 D2 0, Do

Command W 0 0 0 0 I 0 0 0

Remarks

Command Codes

Result R

R

STO

PCN

Status information following a seek or reealibrate operation

The host processor issues a Sense Interrupt Status command to effectively terminate a See1c or

Recalibrate command (the PCN result byte defines the current position of the read/write head) or whenever an unexpected interrupt is received from the FDC (the Sense Interrupt Status command clears the interrupt sig~al). The" host processor, by reading bits 5, 6, and 7 of Status Register 0, can readily identify the cause of the interrupt as follows:

Interrupt

Code

Bit7 Bit 6

Seek End

BitS

1 1 0

0

0

0

1

1

1

Cause

READYI signal from drive changed state.

Normal Termination of Seek or

Recalibrate command.

Abnormal Termination of Seek or Recalibrate command.

3-33. INVALID COMMANDS

If the host processor issues either a Sense Interrupt

Status command when no interrupts are pending or a command code not recognized by the FDC, the FDC immediately terminates the command phase and enters the result phase without generating an interrupt (i.e., the FDC enters a stand-by state or simply "goes to sleep"). To wake the FDC and to complete the result phase, the host processor must read a result byte from the FDC's data register; the

STO result byte read will indicate that an invalid command was issued (bit 7=1, bit 6=0).

The ability of the FDC to recognize a Sense Interrupt

Status command as an invalid command when no interrupt is pending allows the host processor to locate or "flush out" possible "hidden interrupts."

(A hidden interrupt occurs during overlapped seek or recalibrate operations when a second drive completes its seek or recalibrate and the interrupt from the first drive is still pending or when more than one drive ready status change occurs before the first interrupt is cleared.) By continuing to issue Sense Interrupt

Status commands until invalid command status is received, the host processor can be assured that all interrupts have been acknowledged.

Note that while in the stand-by state, the FDC cannot generate an interrupt. This fact provides a mechanism by which the host processor essentially can shut out the controller when a critical task is being performed and an interrupt from the controller cannot be tolerated.

3-34.

SOFTWARE

The host software requirements for the controller consist of a set of InpuUOutput driver routines to perform the following tasks:

• Initialize the controller, including the FDC and

DMAC, following power-up.

• Issue commands to the FDC and pass command data to the FDC and DMAC.

• Respond to completion interrupts and interpret results from the FDC.

• Handle errors.

Appendix A provides two example drivers for the iSBC 208 board. A PLlM-86 driver is given for 16bit systems and an assembly language driver is given for 8080/8085 (8-bit) systems.

3-24


In the example I/O drivers in Appendix A, subroutines are written to perform disk I/O transfers. These subroutines:

• Are user-callable

• Pass command data via an I/O parameter block

• Wait if the FDC is busy

As decribed previously in this chapter, all FDC commands that transfer data to or from the diskette require multiple bytes of information from the host processor before the command can be executed. In addition to the information passed to the FDC, the

DMAC requires information as to the number of bytes to be transferred, the starting location in memory for' the transfer, and the direction of the transfer. Also, if memory addresses greater than 64K are required, the controller's segment address register must be programmed. The I/O driver routines communicate all of this information to the controller through a user-programmed I/O parameter block

(lOPB). Figure 3-5 shows· the 10PB used by the

PLlM-86 sample driver in Appendix A.

Some bytes of the IOPB are dynamic (e.g., the track and sector numbers) and must be written into the

10PB by the calling program prior to the call. Other bytes remain fixed during program operation (e.g., bytes per sector, sectors per track) and can be declared when the driver is compiled. Some commands do not use all the parameter bytes. The 10PB may be located anywhere in host memory convenient to the user program.

The IOPB used by the Assembly Language sample driver is structured the same way as shown under each of the FDC command descriptions with the addition of a NSEC parameter used by some commands to specify the number of sectors to be transferred. 4-n example using the assembly language driver is shown in Appendix A.

3-35. INITIALIZATION

Figure 3-6 depicts a typical initialization sequence.

Initialization requires applying power to the controller and drives, resetting the controller (resets the

FDC and DMAC), programming the operating mode of the DMAC, specifying the drive parameters to the

FDC, and, once the drive parameters are specified, positioning the drive's read/write heads to a known position.

3-36. PROGRAMMING THE DMAC

Once the DMAC has been initialized, programming the DMAC for a subsequent diskette data transfer includes loading the startiing (offset) memory address

(DMAC Address Register), the number of bytes to be transferred (DMAC Word-Count Register), the direction of the transfer (DMAC Mode Register), and clearing the channel 0 mask bit. Also, if memory addresses greater than 64K are to be used, the controller's segment address registers must be loaded.

Note that since FDC command execution begins automatically after the last command data byte is received, the DMAC must' be completely programmed before the last command byte is output to the FDC.

3-37. PROGRAMMING THE FDC

Figure 3-7 shows a generalized program flow chart for the FDC's command phase. The twelve commands are broken down into Specify, Sense Drive

Status, Seek, Recalibrate, and the six data transfer commands. The remaining comand, Sense Interrupt

Status, only is issued in response to an interrupt.

1S 8 7

TRACK ADDRESS

SECTOR NUMBER

INSTRUCTION NUMBER

HEAD AND DRIVE ADDRESSES

SECTORS PER TRACK MT IMFM/SK BYTE

BYTES PER SECTOR GAP3 LENGTH

NUMBER OF BYTES TO ItE TRANSFERRED

SEGMENT ADDRESS

OFFSET ADDRESS

WORD 1

WORD2

WORD3

WORD4

WORDS

WORD6

WORD7

Figure 3-5. I/O Parameter Block

143078-13

3-25


RESET

CONTROLLER

SETUPDMAC

(WRITEDMAC

COMMAND,

REQUEST,

AND MASK

REGISTERS

SETUP FDC

DRIVE

PARAMTERS

(SPECIFY

COMMAND)

RECALIBRATE

DRIVES

(RECALIBRATE

COMMAND)

CHECK STATUS

(SENSE

INTERRUPT

STATUS

COMMAND)

Figure 3-6. Initialization Flow Chart

143078-14

Figure 3-8 shows the detailed steps of the command phase. The "serial" commands (e.g., Read Data) require the exclusive use of the FDC and must wait for the FDC to be idle. A "parallel" command (e.g.,

Seek) may start while another "parallel" command is being executed, but must wait for the FDC to become idle. The two entry points "Command FDC Serial" and "Command FDC Parallel" are used in the flowchart in figure 3-8.

The Specify command establishes the timing intervals for the FDC's three internal timers and typically is issued only during initialization. The Specify command has neither an eXI!cution phase nor a result phase and does not generate a completion interrupt.

The Sense Drive Status command is issued between other commands to obtain the status of any particular drive. The status of a drive is available immediately; the Sense Drive Status command does not have an execution phase and does not generate a completion interrupt.

The Seek command is used to position the addressed drive's read/write heads over the desired track location prior to issuing a subsequent data transfer command; the Recalibrate command is used to position a drive's read/write heads over a known track position

(track 0) and is issued following system initialization or a seek error. During the execution phase of these commands, the FDC enters a non-busy state, and concurrent seek or recalibrate operations can be initiated on the other drives. Following command execution, the FDC generates a completion interrupt; a Sense Interrupt Status command must be issued in response to the interrupt to complete a Seek or

Recalibrate command.

3-26

NOTE: NO EXECUTION

PHASE

NO RESULT

PHASE

NOTE: NO EXECUTION

PHASE

NOTE: FDC AUTOMATIC-

ALLY ENTERS

EXECUTION PHASE

ON COMPLETION

NOTE: FDC AUTOMATIC-

ALLY ENTERS

EXECUTION PHASE

ON COMPLETION OF

OF COMMAND

PHASE

COMMAND PHASE.

RECEIPT OF DMA

REQUEST INDICATES

BEGINNING OF

EXECUTION PHASE

Figure 3-7. FDC Command Phase Flow Chart

143078-15

iSBC 208 Programming Information

DISABLE

INTERRUPTS

DELAY

~~--I~(

ERROR)

ENABLE

INTERRUPTS

( RETURN)

Figure 3-8. Serial/Parallel Command Phase Flow Chart

143078-16

3-27


The seven data transfer commands (Read Data, Read

Deleted Data, Write Data, Write Deleted Data, Read

Track, Read ID, and Format Track) all have an execution phase and a result phase, and all generate a completion interrupt.

Figure 3-9 shows the detailed steps necessary to complete a command's result phase. When a data transfer command terminates, the FDC generates an interrupt and begins the result phase. The host processor must read a series of result bytes from the

FDC's data register to complete the result phase; the interrupt is cleared automatically when the last result byte is read. As shown in figure 3-9, the host processor does not need to count the number of result bytes read; the host processor can determine when the result phase is complete by checking the FDC

Busy bit in the main status register. (When the Busy bit goes inactive, all result bytes have been read and the FDC is ready for a new command.)

3-38. INTERRUPT PROCESSING

When a data transfer command is completed, the

FDC interrupts the host processor and enters the result phase. The host processor must then read a series of result bytes from the FDC's data register to complete the command; the interrupt is cleared automatically by the FDC when the last result byte is read.

When an interrupt results from the completion of a

Seek or Recalibrate command, the host processor must issue a Sense Interrupt Status command to

DELAY

~-=-----..,

.. ( RETURN)

>--_(

ERROR)

Figure 3-9. Result Phase Flow Chart· 143078-17

3-28

iSBC 208 Programming Information properly terminate the command (Seek and

Recalibrate commands do not have a result phase and rely on the result phase of the Sense Interrupt

Status command to complete the operation).

Unexpected interrupts (i.e., interrupts that result from a change in a drive's ready status) also are cleared by a Sense Interrupt Status command. Note that if a Sense Interrupt Status command is issued when no interrupts are pending, Status Register 0 will indicate that an invalid command was issued. Accordingly, when servicing an unexpected interrupt or an interrupt resulting from the execution of a Seek or

Recalibrate command, the host processor should continue to issue Sense Interrupt Status commands until an Invalid Command status is received to ensure that all "hidden" interrupts are serviced. (Hidden interrupts occur when a second interrupt is received before the first interrupt is cleared.)

Figure 3-10 illustrates the processing of FOC interrupts.

YES NO

YES

DATA TRANSFER

COMPLETE

RESULT PHASE

INITIATED

NO

RETURN

SEEK/RECALIBRATE

RESULT PHASE

OR READY CHANGE

OR ABNORMAL

INTERRUPT

CHECK FOR

HIDDEN

INTERRUPTS

YES

YES

NO

ABNORMAL

TERMINATION

YES

Figure 3-10. Interrupt Processing Flow Chart

1430711-18

3-29

CHAPTER 4

PRINCIPLES OF OPERATION


This chapter explains the circuit operation of the iSBC 208 controller board. The level of the following discussion assumes that the reader has a working knowledge of digital electronics and has access to the individual component descriptions of all integrated circuits employed on the board. As a prerequisite, the reader should be familiar with the programming conventions outlined in Chapter 3 of this manual and the functional operation of both the host processor and the Multibus interface. Familiarity with the diskette drive interface specifications and operation also will prove beneficial in the comprehension of controller operation.

The gate configuration on the left (positive NAND), in figure 4-1, indicates that the required low-level output results from a logic high level at both inputs

(AND function), and the gate configuration on the right (negative OR) indicates that the required highlevel output results from a logic low level at either (or both) input (OR function).

In addition to the inversion symbol convention, signal nomenclature also follows an active state convention. When a signal (or level) is active in its logic low state, the signal mnemonic is followed by a slash

(e.g., RST/). Conversely, when a signal is active in its high state, the slash is omitted from the signal mnemonic (e.g., RST).

4-2. SCHEMATIC INTERPRETATION

The controller PC board schematic consists of seven individual sheets that are labeled Sheet 1 of 7, Sheet 2 of 7, etc. These drawings (figure 5-2) and the PC board assembly drawing (figure 5-1) are located in

Chapter 5.

Schematic logic symbols follow active-state conventions in the positioning of the inversion symbol. A gate with an inversion symbol at its output is active in its low state, and a gate without an inversion symbol is active in its high state. Logic gating symbols are drawn according to their circuit function rather than by manufacturer's definition. For example, the gate shown in figure 4-1, depending on its application, would be drawn in either of the two configurations shown.

A

L

B

L

Y

H

H

L

L

H

H H

H

H

L

Figure 4-1. logic Conventions

143078-19

4-3. FUNCTIONAL DESCRIPTION

The following subsections describe the operation of the individual circuit modules or blocks that compose the iSBC 208 controller. Figure 4-4, located at the conclusion of this chapter, is the functional block diagram of the controller and shows the interrelationship of the various blocks.

4-4. CLOCK AND TIMING CIRCUITRY

All timing and clock signals generated by the controller originate from 8-MHz crystal oscillator G 1

(6ZD7). The buffered output of G 1 ctrives timing generator U50 (3ZD6), provides a comparator frequency to the VCO frequency indicator on sheet 2, supplies the 8-MHz clock for the FDC, and drives flip-flop U67 (6ZD7). Flip-flop U67 is used as a frequency divider to provide the 4-MHz clock signal.

This signal also drives write shift register U3 (7ZB5) and binary counter U69 (6ZD6). U69 produces frequencies of 2 MHz (U69-11), 1 MHz (U69-1O), 0.5

MHz (U69-9), and 0.25 MHz (U69-8). Three of these frequencies (1, 0.5, and 0.25 MHz) are input to data selectors U70 (6ZD4) and U71 (6ZD3). The data selectors provide the correct clocks to the various circuits as determined by the MFM signal from the

FD(: and the MINI! signal from the jumper matrix.

(The MINI!signal is low for 5 Y4 -inch drives and is high for 8-inch drives; the MFM signal is low for single-density operation and is high for doubledensity operation.) Table 4-1 shows the resultant output from U71 for the different states of the MINI! and MFM signals.

4-1

Principles of Operation iSBC208

MINI/Low

MFM Low

1Y = 2200 ns pulse

2Y =0.25 MHz

4Y =0.25 MHz

Table 4-1. IC U71 Output

MINI/High

MFM High

1Y = 550 ns pulse

2Y = 1 MHz

4Y=1 MHz

MINI/Low

MFM High

1Y = 1100 ns pulse

2Y = 0.5 MHz

4Y = 0.5 MHz

MINI/High

MFM Low

1Y = 1100 ns pulse

2Y = 0.5 MHz

4Y =0.5 MHz

The output from U71-12 clocks flip-flop US4 at the selected frequency. The flip-flop is cleared by the

2-MHz input at US4-1 to create a 2S0 ns write clock pulse at the selected frequency. Table 4-2 lists the various write clock frequencies. The outputs from

U71-4 and U71-7 are used in the data separator circuits (see paragraph 4-12).

Table 4-2. Write Clock Frequency

Mode

Single density

Double density

8inch

Drive Size

5Y4-inch

0.5 MHz

1.0 MHz

0.25 MHz

0.5 MHz

4-5. MUL TIBUS INTERFACE

The bidirectional Multibus interface data lines are buffered by U64 (lZC6). This circuit is enabled for both I/O and DMA type operations by U14 (IZB6).

The BDSELI signal enables the data driver for I/O transfers, and the DMACI signal enables the drivers for DMA transfers. The 10RI signal controls the direction of the data buffer. When the IORI signal is active (low), U64 is in the output mode (I/O READ or DMA WRITE operations) and when the 10RI signal is inactive (high), U64 is in the input mode

(I/O WRITE or DMA READ operations).

Bidirectional address buffering for ADROI - ADRF I is provided by U62 and U63 (SZC2). These buffers are always enabled. Normally, the ADEN (SZA 7) signal is low to allow the address to enter the board

(I/O transfers). When ADEN is high, the address buffers place the address on the Multibus interface

(DMA operations only). Address lines ADRlOl -

ADR 131 are buffered by U S7 (SZB2) and are used only for DMA operations.

The iSBC 208 controller I/O address decode circuitry decodes either 8- or 16-bit I/O addresses and occupies either 22 or 38 ports. This complex I/O mapping is performed by the Intel 362S PROM at

U16 (2ZC4). The PROM provides a board enable signal (SEll) and an encoded number (0-7) for I/O circuit selection. The encoded number is decoded into eight individual chip select signals by U27

(2ZC2). Table 4-3 lists the base addresses and shows the resulting chip select signal.

A comparison between the I/O address and the base address jumpers is performed by comparators U28,

U41, and U40 (2ZC6, 2ZB6). Since the A = B output from U28 is true for both 8- and 16-bit I/O addresses, this output is used to enable the PROM's

CS2 input (the CSI input is permanently enabled by a resistor to ground). For 8- or 16-bit address decode selection, the PROM ignores the A = B output

(U40-6) when the PROM's A9 input is high (l6-bit mode). When the PROM's A9 input is low (8-bit mode), a high output from comparator U40-6 is required in order to generate the SELl signal. When the MPST I signal is high (no Multimodule installed), the PROM only generates a

SEll signal when inputs

AS and A6 match and produces the 22 ports that reside on 32-port boundaries. With an iSBX multimodule installed, MPST I is held low to cause the

PROM to ignore its A6 input and to produce the 38 ports on 64-port boundaries.

Bus control signals 10RCI and IOWCI are inverted by US8 (3ZC7) and then ORed together by U26

(3ZD6) to generate a common command signal. This signal removes the clear input to shift registers U49

(3ZDS) and USO (3ZD6). After 16 clock pulses (eight at 8 MHz and eight at 2 MHz), both registers are filled with "ones." The resistor outputs provide three delays that are used during I/O accesses. The first delay of SOO /-Is at U SO-1O(3ZD6) delays the I/O commands to allow time for the I/O address signals to propagate through the decode circuitry and additional time to meet the DMA controller's recovery

Table 4-3. Chip Select Coding

I/O Base Address

(Hex)

00 thru OF

10,11

12

13

14

15

20 thru 27

28 thru 2F

U27

Output

CSOI

CS11 eS21 eS31 eS41

CS51

MeSOI

MCS11

DMAC

FDC

Circuit

Enabled

Auxiliary Port

Software Reset

Low byte of Seg. Reg.

High byteofSeg. Reg. iSBX (when installed)

4-2

iSBC208 Principles of Operation time between active read/write pulses. This delayed signal, together with the common command and

SEll signals, enables four three-state gates (U56) that in turn, pass 10RI or lOW 1 to the selected circuitry. Dual buffering is used on lOWland 10RI for loading purposes. The second delay (U50-13) provides the acknowledge timing for all I/O accesses except the software reset. A third delay of approximately 4 /ls is provided to meet the reset timing requirements of the S272 FDC. The proper XACKI timing is determined by the level of CS31 through gates U47 and U65 (3ZD4).

4-6. DMA CONTROLLER (DMAC)

OMA controller UlS (4ZC6) mediates the flow of data between both the disk drive (through the FDD interface and the FDC) or the iSBX module (if installed) and the Multibus interface memory.

The following DMA controller modes of operation are not supported and cannot be used on the iSBC

20S controller:

• Cascade Mode

• Memory to Memory transfers

• Compressed Timing

A one-byte transfer from memory to the FDC will be used to describe a DMA operation. Since the timing for all DMA operations is basically the same, only differences from the one byte transfer will be described where appropriate.

Assuming the host processor has set up the OMAC and the FDC, the DMA process starts when the

DMAC receives a request (DREQO) from the FDC.

The DMAC resolves priority among simultaneous requests and activates its HRQ output pin (U IS-IO) to inform the S21S bus controller (U39) to acquire the system bus. The bus controller then activates BREQI and deactivates BPROI and then waits for BUSY 1 to go inactive. When BUSY 1 goes inactive, and if

BPRNI is active, the bus controller takes control of the system bus by 'activating BUSY I. The bus controller then notifies the DMAC to continue the transfer by activating the ADEN I signal which, through inverter U15 (4ZA5), activates the HLDA input at UlS-7.

The ADENI signal also inhibits the 1/0 address decoder via U2S-3 (2ZC6) to prevent the generation of false chip-select signals caused by a match between a memory address and the 1/0 base address jumpers.

The ADEN signal conditions the bidireCtional system bus drivers (U62, U63) on sheet 5 to place the addre~s on the Multibus interface.

After receiving HLDA, the DMAC proceeds with the actual data transfer by activating the following signals in the order listed: l. DAEN (UlS-9) is ANDed with ADEN at U66

(SZBS) to enable three-state address buffers U46

(SZC3), US7 (SZB2), and U61 (SZB3).

2. The high-order memory address byte is output on the on-board data bus as DO-D7 (U IS), buffered by U33 (IZBS) and latched into register

U31 (SZC6) by the address strobe (ASTB) signal.

At the same time, the low-order memory address byte is output as AO-A3 and DA4-DA7 (UIS).

3. DACKOI

(4ZD6).

(UlS-2S) is sent to enable the FOC

4. MEMR (UlS-3) is sent to the bus controller

(U39) which, in turn, activates MROC (U39-12) to produce a memory read command on the system bus. System memory now responds with a byte of data that passes through data buffer U64

(lZC6) that has been enabled by the OMACI signal from the bus controller.

S. The 10WCI signal from the Multibus interface is now sent to the FOC (U 17-3 on sheet 7) to enable the FOC to accept the data byte.

Acknowledgment from the system memory (XACK/) is synchronized with DCLK at latch U22 (3ZD2). The

REDY signal from U22 is passed to the DMAC

(UlS-6) to allow the DMAC to complete the transfer cycle. Completion of the transfer cycle takes place in the reverse order (see figure 4-2 for DMA transfer timing).

An end of process (EOP) signal is generated by the

DMAC (UlS-36) when its word count register reaches zero. The EOP signal is ANDed with DACKO and sent as a terminal count (TC) signal (EO POI) to inform the FOC that the last transfer has occurred.

4-7. DMA ADDRESSING

When the iSBC 20S controller is operating as a bus master and performing DMA transfers, it has the capability of addressing up to 16 megabytes (24 address bits) of system memory. The controller can address the full I-megabytc! address space as specified by the Multibus interface by using the 20 address lines provided on Multibus connector PI and, in addition,can generate four additional address lines to select between sixteen unique I-megabyte pages.

The four additional address lines, AOR14 through

ADRI7, are routed onto the P2 conn·ector. Since the

DMA chip only generates a 16~bit address, circuits on the board are used to latch additional address bit~ and then to add these bits to the DMA address when a DMA transfer occurs. The 16-bit address from the

4-3


DREOOI

HRy

BREOI

BUSYI

ADEN I

AEN

ASTB

DBO-DB7

- - - - - - - 1 - - - {

AO-A7 - - - - - - - - \ - {

DACKOI

MRDCI

IOWI

XACKI

Figure 4-2. DMA Transfer Timing

DMA chip (offset address) is added to a 16-bit segment address from the Multibus to form a 20-bit memory address. The 20-bit memory' address is appended to the four high-order paging bits.

Prior to the start of a DMA transfer, segment registers U30 (5ZB6) and U32 (5ZC6) must be loaded, the starting (offset) address and word count must be loaded into the DMA chip, and then the four high-order paging bits of the memory address must be loaded into the AUX port. The low-order byte of the segment register is loaded into U32 and latched when the CS41 (5ZC8) and IOWBI (5ZC8) signals are active. The high-order byte of the segment register is loaded into U30 and latched when the

CS51 (5ZB8) and IOWBI (5ZC8) signals are active.

The DMA chip, in turn, loads the upper half of the offset address in offset register U31 (5ZC6) when

ASTB (5ZB8) is active_ The high-order paging bits

(ADR 14 - ADR 17) are loaded into the AUX port

(3ZB5) when CS2/ (3ZB8) and IOWBI (3ZB6) are active. The outputs from the segment registers, the offset register, and bits DA4 through DA7 of the offset address from the DMAC are input to a set of, four adders, U42 through U45 (5ZD-B4). The sum of these inputs plus offset address bits AO-A3 from the

DMAC and the four high-order bits from the AUX port form the 24-bit memory address.

4-8. FLOPPY DISK CONTROLLER

143078-20

Central to all disk operations is the floppy disk controller (FDC), an Intel 8272_ The FDC interprets all read, write, and seek instructions and, via the floppy disk drive interface, commands the selected FDD to

4-4

iSBC208 Principles of Operation perform the requested operation. The FDC operates in either single-density (FM) or double-density

(MFM) mode and supports an IBM sector format in both modes. Additionally, the FDC is compatible with both single-sided and double-sided media; the controller includes the circuitry for interfacing up to four drives and is capable of performing concurrent seek or recalibrate operations on four drives.

The FDC performs parallel-to-serial and serialto-parallel data conversions; the FDC passes reassembled parallel data to the DMA contro.ller during diskette read operations and provides serial data from the DMA controller to the selected drive during write operations. TheFDC also generates an interrupt to signal the host processor that a requested operation has been completed; the FDC's status registers provide the host processor with both normal- and failure-mode status information.

4-9. FDD INTERFACE

The FDD interface consists principally of buffers, head-load and drive-select decoders, head load timers, special-function latches, and data-clock and data separation circuitry.

4-10. DRIVE AND HEAD SELECTION. Drive select decoding is performed by half of U24 (12BS); the other half of U24 provides radial head-load signals by decoding the drive select signal from the

FDC (12C6). The radial head-load signals drive timers Ul3 (7ZC3) and U23 (7ZC3) which, in turn, provide extended HEAD LOAD signals to the drives.

The timers are wired as one shots with retriggerable operation provided by transistors Ql through Q4.

Each timer produces. a head-load signal for approximately one second after the FDC inactivates its HDL signal.

Half of U21 (7ZDS) provides demultiplexing for the

FAULT RESET/, STEP/, LOW CURRENT/, and

DIRECTION 1 signals, and the other half of U21

(7ZB7) multiplexes the signals WRITE PROTECT I,

TWO SIDED/, FAULT/, and TRACK 01 signals, all under control of the RW /Seek signal from the

FDC.

4-11. WRITE PRECOMPENSATION. U3

(7ZBS) is connected as a shift register and is clocked with a 4-MHz signaL This signal timing causes write data from the FDC to arrive at th_e shift register outputs in increments of 250 ns. Compared to the data at

U3-tO, the data at U3-7 is 250 ns early and the data at

U3-1S is 250 ns late. The normal, early, or late data is selected by U4 (7ZB3) to provide write precompensation under control of the FDC. AND gates U 14-3 and U 14-6 gate the pre-shift control signals

(PSO,PSl) to allow precompensation only on the inner tracks (tracks 43-77) as determined by the low current signal from U8-2 (7ZD4).

4-12. DATA SEPARATOR. The purpose of the data separ(!tor circuit is to generate a data window signal (RDWN) that enables the FDC to separate the data bits from the clock bits in the serial data stream received from the drive. The actual determination of a data" 1" bit is performed by the FDC.

The data and clock pulses must be kept in their respective windows in the presence of data clock pulse jitter and frequency variations. Pulse jitter is overcome by a window-extender feature, while frequency variation is minimized by the use of a phaselock-loop circuit. Figure 4-3 is a timing diagram of the data seperator circuit. While this circuit is designed to run at three data rates, only one rate, double density on an 8-inch drive, is used in the following description (a comparison between the three data rates is shown in table 4-4).

At the double-density, 8-inch data rate, clock and data pulses can be 2, 3, or 4 microseconds apart. This timing separation requires a I-microsecond, on-time clock for the comparison. The on-time clock signal originates from the VCO and is generated by divider

U69-S (6ZC4) and selected by data selector U71-7

(6ZD3). Flip-flop U67-S stays set since its K input is held low and allows the undivided on-time clock to be fed directly into U69-1. An on-time clock of

1 MHz is selected by U71.

The data from the drive (READ DATAl) is delayed and shaped by one-shot U3S-7 (6ZC7) into a series of

SSO ns-wide pulses and fed to the 4B in-put of U70

(6ZD4). Since the MINI! signal is inactive, the 550 ns pulses are multiplexed to U71; the resultant output at

U71-4 is input to the clock inputs of US3-9 (6ZA5),

US4-9 (6ZBS), and U37-S (6ZB5). The digital phase comparator consisting of U37 (6ZAS) is prevented from making false comparisons by flip-flop U53-9.

The leading edge of each delayed data pulse from

U71-4 clocks US3-9 to enable U37 to make a comparison between the trailing edge of the delayed data pulse at U37-3 and the rising edge of the on-time clock at U37-11.

The phase comparator controls transistors Q5 and

Q6 (6ZA3) that form a current pumping circuit to increase or decrease the charge across C46. The resultant voltage on C46 controls the operating frequency of VCO U38 (6ZA2); an increase in voltage causes a corresponding increase in VCO output frequency.

4-5


DATA o o o o

DATA CELL

EARLY-LATE

DRIVE DA TA t--t---t---t---t---t---=----+--=--+--=--+--=---+--=--+--=---+--=---+--=-+--=--+--=--+-.....::....-+-.....::....-+-....:::..-I-

L..:...L..:...L..:...tT-.L:....L..:...L..:....L..:....L..:....L..:...;;~...L:....L:....L:....L:.r1r...L:....L:....L:....L..f~...L:....L:....L:.~4-!;..L.!:...l..!;..L.!:...l..!:..+;~:....L;~:....L;~

DELAYED en~

------.Ur--------.Ur------,Ur----'U.-------.LJr------.Ur-----

VCO

OUJ;~_~ nruw ttttttttt

ON TIMECLK

U71-7

WINDOW

US3-S

RDWINDOW

--~

RDWN LOCKED L ____ r--- ... .,

.J ......... L ___ r----..,

...J tttttt r----, ttttttt ttttttt ttttttt ttttttt

__ n

n n

r I

n

n

..=,. ___ ~---..,

...J r---..,

L;:..::,_...J L ____ r----.

...J L ____ r----..,

.J r---

L ____ -' n n n n n n n n

_ _ _ n n r I n

n

L-. _ _ _

Figure 4-3. Data Recovery Timing 143078-21

When flip-flop U37-3 (6ZB5) is clocked set by the delayed data pulse before flip-flop U37-9 is clocked set by the on-time clock, Q5 conducts (increasing the charge on C46 and increasing the VCO output frequency) until U37-9 is set. When U37-9 sets, both flip-flops are cleared immediately through U52-3 and

U53-9_ This action creates a pump up (or pump down) time proportional to the phase difference between the delayed data pulse and the on-time clock. (A pump-down condition occurs when the ontime clock signal arrives ahead of the delayed data pulse.)

The phase comparator is enabled by the VCO signal from the FDC when reading data from the diskette.

When the VCO signal is inactive, both comparator flip-flops are held set, a-nd both pumping transistors

(Q5 and Q6) conduct to cause the control voltage to return to its nominal value of 3 volts. When the control voltage is at its nominal value, the VCO (U38) output frequency is adjusted for 8 MHz by potentiometer Rl until VCO frequency indicator DSI is at its brightest level.

Flip-flops U54-9 (6ZB5), and U73-5 (6ZB5), and

U73-9 (6ZB4) form a shift register that synchronizes the delayed data to the VCO clock and that provides a 125 ns read data (RDAT) pulse for each delayed data pulse and a read window extension signal. The basic read window signal (RDWN) is generated by flip-flop U53-5 (6ZC3) on the falling edge of every other on-time clock pulse. The outputs from U53 drive slave flip-flop U55-3 and U55-11 (6ZC2). This flip-flop follows U 53 unless it is inhibited by one of the shift register outputs at OR-gate U52-8 (6ZB3).

The output from U52-8 is active whenever there is a pulse in the first cell (U74-9) of the shift register or whenever a data pulse occurs near the end of the normal window (i.e., whenever U73-7 is active).

Data Rate

(k Bits/s)

500

250

250

125

Table 4-4. On Time Clock Versus Data Rate

Drive Size

8-inch

8-inch

51f4-inch

51f4-inch

Encoding Mode

MFM

FM

MFM

FM

Bit-to-Bit

Spacing ("s)

2,3,4

2,4

4,6,8

4,8

On-Time Clock

(MHz)

1.0

0.5

0.5

0.25

4-6

iSBC208 Principles of Operation

MULTIBUS

INTERFACE

1'1 r----

10RC lowe

I~

BUS CONTROL LINES

DATO-DA-T1

AORO·ADR13

M·At'

AQ·AF

BUS

CONTROLLER

14

DMAC

11.0-11.3 ~

ADDRESS

REGISTER!

DRllfERS

1\10-A13

K'·/',;!";!;{L';IV;';;',

,.

M·AF

[5

i' l

MEMfl

MEMW

HRQ

ADEN

Y

SIOIREC·

TIONAl rt BUS

DRIVERS

1

OREQ3

CSO

2MHZ

DMA

CONTROLLER

XACK

B00-807 •

·;:Jr~."';''!l

: lOR

Y ~ f4

DACK3

MOROT

MDACK

~3

I - -

£JACKO

IliREQ

EOI' i ie,

' -

i

rr

DRllfE CONTROLS

WR!TEOATA

EOPO INDEX

CS1 EINT flOPPY

!)lSK !AEN 00-1:>1 ..

CONTROLLER

"/l

•

r -

-

17

ROAT

TIMING

AND

PHASE

LOCK lOOP

EOP1

rs

-

READ DATA

!I-iNCH

ORWES

-J2

MIl'll

00-07 lowe

.. 1'300·807

OMA

ADDRESS lOGIC

15

T DM.DA7

IAEN

CS4

CS5

; lei

'.

I

I

; -

00-03

I

I i - -

BDO-BD~

",' f - -

~

AUX

PORT

~ DRIVE

OPTION r-+

JUMPERS

13

ADR14

AOR15

ADR16

ADRi7 i3

" i . . -

MOROT

MDACK

MPST

MINI

DRIVES

-

J1

"

" " -

~

" " -

J3

MDO-MDlr-

EXTENDED

ADDRESSING

BASE

ADDRESS

SELECTION

JUMPERS f2

~

11

BASE

ADDRESS

A6-AF

DECODE

IT

AO-A5 liD

ADDRESS

DECODE

J1

U,

SEt.:

L.-

CHIP

SELECT

12

CSO

C$1

CS2

ess

Cf>4

CSS

Meso

MCS1

11.0-11.2

IOWRT lORD

Meso

MCS1 iSBX

MUL TlMOOULE

CONNECTOR

EINT

MINTR1

MINTRll

INTRO-INTR7 INTERRUPT

MATRIX f4

MINTR1

MINTRO i . . - -

XACK

110

COMMAND

ACKNOWLEDGE

13

SEl

IORC lowe

CS3

MWAIT

OACK3

EOI'

DREQ3

ISaX

OMAOPTION

JUMPERS

14

OPTO opn

MWAIT -

ONE WAY BUS

BIOIRECTIONAl 8US

14307t!-22

Figure4-4. Block Diagram of Controller

4-7/4-8

CHAPTER

51

SERVICE INFORMATION


This chapter provides the service information required for the iSBC 208 Floppy Disk Controller

Board and includes a list of replaceable parts, the service diagrams, and service and repair assistance instructions.

5-2. SERVICE AND REPAIR

ASSISTANCE

United States customers can obtain service and repair assistance by contacting the Intel Product Service

Hotline in Phoenix, Arizona. Customers outside the

United States should contact their sales source (Intel

Sales Office or authorized distributor) for service information and repair assistance.

Before calling the Product Service Hotline, you should have the following information available: a. Date you received the product. b. Complete part number of the product (including dash number). On boards, this number is usually silk-screened onto the board. On other MCSD products, it is usually stamped on a label. c. Serial number of product. On boards, this number is usually stamped on the board. On other MCSD products, the serial number is usually stamped on a label. d. Shipping and billing addresses. e. Purchase order number for billing purposes if your Intel product warranty has expired. f. Extended warranty agreement information, if applicable.

Use the following numbers for contacting the Intel

Product Service Hotline:

Telephone:

From Alaska, Arizona, or Hawaii call-

(602) 869-4600

From all other U.S. locations call toll free-

(800) 528-0595

TWX: 910-951-1330

Always contact the Product Service Hotline bi~fore returning a product to Intel for repair. You wiill be given a repair authorization number, shipping instructions, and other important information that will help Intel provide you with fast, efficient service.

If you are returning the product because of damage sustained during shipment or if the product is out of warranty, a purchase order is required before Intel can initiate the repair.

In preparing the product for shipment to the repair center, use the original factory packing material, if possible. If this material is' not available, wrap the product in a cushioning material such as Air Cap

TH-240, manufactured by the Sealed Air Corporation, Hawthorne, N.J. Then enclose the product in a reinforced corrugated shipping carton and label

"FRAGILE" to ensure careful handling. Ship only to the address specified by Product Service Hotline personnel.

~3. REPLACEABLE PARTS

Table 5-1 provides a list of replaceable parts for the iSBC 208 controller. Table 5-2 identifies the manufacturers specified in the MFR CODE column in table 5-1. Intel parts that are available on the open market are listed in the MFR CODE column as

"COML"; every effort should be made to procure these parts from a local (commercial) distributor.

5-4. ADJUSTMENTS

The controller includes only one adjustable component, a potentiometer that sets the center frequency of the voltage-controlled oscillator (VCO). The adjustment is performed at the factory'and normally is valid for the life of the controller. However, if a component is replaced within the phase-lock-loop circuit, it may be necessary to readjust the center frequency of the VCO. To perform this adjustment, insert the controller into the system, apply power, and allow the controller to "'idle." While observing

LED indicator DSI (located on the front edge of the pc board towards the left), adjust potentiometer RI

(adjacent to DSI) until the LED is at its maximum brightness.

5-5. SERVICE DIAGRAMS

The parts location diagram and schematic diagram for the iSBC 208 controller are provided in figures

5-1 and 5-2, respectively. Thc~ parts location diagram is useful in locating the parts listed in table 5-1.

5-1

Service Information iSBC208

The schematic diagram (figure 5-2) consists of seven sheets of logic drawings that were current when the manual was printed. Minor revisions and changes may have occurred since the manual was printed. If a discrepancy exists between the schematic in the manual and the schematic shipped with the controller, the schematic shipped with the controller always supersedes the schematic in the manual.

A signal on the schematic diagram that traverses from one sheet of the drawing to another is labeled with the same boxed letter reference (e.g., A) on each sheet to simplify signal tracing. The signal mnemonic and the source/destination sheet number are shown adjacent to the boxed letter reference.

Generally, signal mnemonics listed on the left side of a sheet are entering the diagram, and signal mnemonics listed on the right side of a sheet are leaving the diagram. On the schematic diagram, a signal mnemonic that ends with a slash (e:.g., ALE/) is active low. Conversely, a signal mnemonic without a slash (e.g., ALE) is active high.

Reference

U1

U2,U19,

U51,U61

U3

U4

U5,U6,U9,

U10,U12

U7,U34,

U8,U11,U58

U13,U23

U14

U15,U48

U16

U17

U18

U20

U21,U57,U72

U22,U37,U54

U24

U25

U26

U27

U28,U40,U41

U29,U30,U~2

U31

U33,U46

U35,U36

U38

U39

U42,U43

U44,U45

U47

U49,U50

U52,U55

U53,U67,U73

U56

U59

U60

U62,U63,U64

U65,U66

U69

U70,U71

Table 5-1. Replaceable Parts

Description

IC, Quad 2-input positive-NOR gate

IC, Quad bus buffer gates

Mfr.

Part No.

7402

74125

IC, Quad D-type flip-flops

IC, DuaI4-to-1 data selector/mux

IC, Quad 2-input positive-NAND buffer

Not Used

IC, Hex Schmidt trigger inverters

IC, Dual timer

IC, Quad 2-input positive-AND gate

IC, Hex inverters

IC, PROM, 1024x4

IC, Floppy disk controller

IC, Programmable DMA controller

IC, Quad 2-input positive-NOR gate

IC, Octal 3-state buffers

IC, Dual D-type flip-flop

IC, DuaI2-to-4 decoder/multiplexer

IC, Quad 2-input positive-OR gate

IC, Quad 2-input positive-OR gate

IC, 3-to-8 tine decoder/mux

IC, 4-bit magnitude comparator

IC, Octal D-type flip-flops

IC, Octal D-type latches

IC, Octal bufferltine driver/receiver

IC, Dual retriggerable multivibrator

IC, Dual voltag.e controller oscillator

IC, Bus controller

IC, 4-bit binary full adder

74175

74153

7438

7414

NE556

7408

7404

3625

8272

8237A

74S02

74LS240

74S74

74LS139

7432

74S32

3205

74LS85

74LS273

74LS373

74LS244

9602

74124

8218

74LS283

IC, Triple 3-input positive-NAND gates

IC, Serial shift register

IC, Quad 2-input positive-NAND gate

Ic, Dual J/K flip-flops

IC, Hex bus drivers

IC, Quad bus buffer gates

IC, Quad 2-input positive-NA~D gate

IC, Octal bus transceiver

74S10

74LS164

7400

74S112

74368

74LS125

74S38

8287

IC, Dual4-bit binary counter

IC, Quad 2-to-1 data selector/mux

74LS393

74157

1

1

3

1

2

4

3

1

1

2

3

2

1

2

1

1

1

1

3

3

1

3

3

1

2

1

1

1

2

1

1

4

Qty.

1

4

1

1

5

TI

TI

TI

TI

TI

TI

TI

Intel

TI

TI

TI

SIG

TI

TI

Intel

Intel

Intel

TI

TI

TI

TI

TI

TI

Intel

TI

TI

TI

TI

SIG

TI

Intel

TI

TI

TI

Mfr.

Code

TI

TI

TI

5-2

iSBC 208

Service Information

Reference

RP1

RP2,RP3

RP4

R1

C66

C1,C3,C5,C7,C10,

C12,C16,C17,C1S,

C19,C21,C23,C25,

C27,C2S,C29,C30,

C32,C34,C39,C43,

C44,C47,C4S,C50,

C52,C54,C56,C59,

C60,C62,C64,C65,

C71,C73,C74,C76,

C79,CSO,CS2,CS4

C2,C4,C6,CS,

C9,C11,C13,C20,

C26,C31,C33,C35,

C36,C37,C3S,C47,

C49,C51,C53,C55,

C57,C5S,C61,C63,

C67,C70,C72,C75,

C78,CS1,CS3

C14,C15,C22,C24

C34

C40,C41,C42

C45,

C46

C6S,C77

C69

L1

01,02,03,04,05

06

R2,R3,R6,R7,

R12,R15,R1S,

R20,R29,R30,

R39,R40

R4,R3S

R5

RS

R9,R10,R16,R17

R11,R25,R26,

R27,R2S

R13,R14

R19,R34,R41

R21

R22

R23

R24

R31

R32,R35,R36

R33

R37

R42

R43,R44,R45,

R46,R47

Resistor, 4.7k ohm, 1/4W, 5-

Resistor, 330 ohm, 1/4W, 5%



Resistor, 1M ohm, 1/4W. 5%


Resistor, 33k ohm, 1/4W, 5%

Resistor, 1.5k ohm, 1/4W, 5%

Resistor, 4.99k ohm, 1/SW, 1%

Resistor, carbon, S.2k, 1/4W, 5%

Resistor, 10k ohm, 1/SW, 1%

Resistor, 20k ohm, 1/SW, 1%

Resistor, 2.2k ohm, 1/4W, 5%

Resistor, 1 k ohm, 1/4W, 5%

Resistor, 750 ohm, 1/4W. 5%

Resistor, 1.3k ohm, 1/4'11',5%

Resistor, 470 ohm, 1/4W. 5%

Resistor, 10k ohm, 1/4W, 5%

Resistor pack,

Resistor pack, 10k ohm, DIP

Resistor pack, 5.6k ohm, DIP

Resistor, variable, 1 k, O.!iW

Thermistor, Sk, 10%

Capacitor, 0.1IlF, 50V, +SIJ-20%

Not Used

Table 5-1. Replaceable Parts (Cont'd.)

Description

220/330 ollm, SIP

Capacitor, 11lF, 20V, 10%

Capacitor, 1000pF, 15V, 5'Yo

Capacitor, 270pF, 100V, 5%

Capacitor, 50pF, 100V, 5°;',

Capacitor, 0.01IlF, 50V, 20%

Capacitor, 221lF, 15V, 10%

Capacitor, 390pF, 100V, 5%

Inductor, 100IlH, 10%

Transistor, PNP, 2N2907P

Transistor, NPN, 2N2222t.

Mfr.

Part No.

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

9230-S

2N290j'A

2N2222~A

Mfr.

Code

COML

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

OBO

430SR·103-

331/221

4114R·002-103

4114R··002-562S

6SXR1K

IMSOOH

OBO

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

COML

BOUR

BOUR

BOUR

BECK

WEST

COML

COML

COML

COML

COML

COML

COML

COML

JWM

FAIR

FAIR

1

5

1

1

1

1

4

1

1

1

Qty.

12

1

2

1

1

1

41

3

1

1

1

5

1

1

1

3

2

3

1

2

1

1

3

5

5-3

Service Information

Reference

XU17,XU18

G1

DS1

E1 through

E89, TP1 , TP2

J1

J2

J3

Table 5-1. Reptiaable Parts (Cont'd.)

Description

Socket, IC, 40-pin

Crystal, clock oscillator, 8MHz

Light emitting diode, red

Wirewrap posts, interconnect

Mfr.

Part No.

540-AG110

208-CB

HLMP-0301

87623-1

Connector, header, 34-pin

Connector, header, 50-pin

Connector, Multimodule, 18/36-pin

Connector, HSG, receptacle, 2-pin

3433-1302

3431-1302.

000291-001

530153-2 iSBC208

Mfr.

Code

AUG

WAK

HEW

AMP

MMM

MMM

VIK

AMP

1

1

1

12

Qty.

2

1

1

91

Mfr. Code

AMP

AUG

BECK

BOUR

FAIR

HEW

Intel

JWM

MMM

SIG

TI

VIK

WAK

WEST

COML

Table 5-2. Manufacturer's Codes

Manufacturer

AMP, Inc.

Augat, Inc.

Beckman Instruments, Inc.

Bourns, Inc.

Fairchild Semiconductor

Hewlett Packard

Intel

J. W. Miller Division Bell

Minnesota Mining Manufacturing

Signetics Semiconductor

Texas Instruments

Viking Connector, Inc.

Wakefield Engineering, Inc.

Western Thermistor Corp.

Any commercial source;

Order By Description (OBD)

Address

Harrisburg, PA

Attelboro, MA

Cedar Grove, NJ

Riverside, CA

Santa Clara, CA

Cupertino, CA

Santa Clara, CA

Compton, CA

Minneapolis, MN

Santa Clara, CA

Dallas, TX

San Diego, CA

Wakefield, MA

Oceanside, CA

5-4

iSBC208

D

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143Z75

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C EC.O 40 -21002

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AND U22 - \3.

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Figure 5-1. is BerM 208 Parts Location Diagram

5-5/5-6

iSBC208 Service Information

7 6 s

,

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P I - I a - - -

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PI- 71

PI-72.

PI -~

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13 B6 UC4 A6t-:7--::D:..: - I I -__ .f-__

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NOTES: UNLESS OTHEP..WI5E SPECIFIED

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MVLTIMODULE OPTIONS.

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7 14

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3 z.

16

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Figure 5-2. iSBC

M

208 Board Schematic Drawing (Sheet 1 of 7)

5-7/5-8

Service Information

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5-9/5-10

iSBC 208 Service Information

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APPENDIX A

SAMPLE DRIVERS

A-1. INTRODUCTION

This appendix provides two sample drivers fc r the iSBC 208 Controller. Section A-2 describes a

PLlM-86 driver for I6-bit systems. Section A-3 provides an assembly language listing for 8-bit systems.

A-2. PL/M-86 DRIVER

This is an instruction decode and driver for the iSBC 208 Disk

Controller. The procedure is called from the main routine with no parameters. All of the instructions and necessary parameters are passed in an lOPB as defined below in the structure declarations. There are 12 possibie instructions for the controller.

Some of the instructions require programming of the DMA controller chip on the board •. The driver determines this need and either programs the chip or skips the section altogether.

The lOPE is filled with the required information for a particular instruction by the calling program. Only those locations needed for the instruction are filled, the other locations are don't ~ares. The lOPB is structured as follows:

\ bytes/sector \gap-3 length

~----------------------

____ _

\ number of bytes to be transferred

I

I

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I segment - memory location

------------------_._--------------------------------------

offset - memory location

Word

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

Since the lOPE is a public data structure, the addreSs need not be passed by the calling routine.

The driver makes some assucptions and performs no error checking on the data in the lOPB. Care must be taken by the calling routine to ensure correct data for the instruction being requested.

A-I

Sample Drivers iSBC 208

The instructions available and their instruction numbers are as follows:

I NST RU CTlON II INSTRUCTION

1

2

3

4

5

6

7 o

9

10

11

12

13

14

15

Read Data

Write Data

Write Deleted Data

Read Deleted Data

Read a Track

--NOT USED··.

--NOT USEDitit.

·-NOT USED···

Format a Track

Read ID

Recalibrate

Sense Interrupt Status

Specify

Sense Drive Status

Seek

For any instruction, the calling program is responsible for plaCing the correct values necessary for the instruction in the lOPB.

Status is returned to the calling procedure via a STATUS structure that also is declared public. The status is pulled directly from the FDC on completion of the instruction and is only reported; no action is taken on the status values. The PASS_FAIL byte is set to pass if status is received properly.

The STATUS structure is as follows:

15

I-------------------------------~----------------------------1 status byte 0

8 7

1

0

1 ____________________________

2

I status byte 2

I track number

I head address

I sector number

1_------------------------______

1 ______ -----------.---________

....! pass-fail byte

I N byte

1

Word

Word 2

Word 3

Word 4

A-2

iSBC208

Sample Drivers

execute$module:

DO;

1* This structure is used as an IOPB device to pass information throughout the software regarding the current instruction to be executed.

The structure is filled with information by the calling program and is taken apart by the 8272 drivers. It is declared public. *1

DECLARE iopb STRUCTURE(instruction track$no head$drive sector$no mt$mf$sk sectors$per n gap$3 byte$cnt buffer

BYTE,

BYTE,

BYTE,

BYTE,

BYTE,

BYTE,

BYTE,

BYTE,

WORD,

POINTER) PUBLIC;

1* This structure is used to return status information from the 5272 drivers to the calling program. It also is declared public. *;

DECLARE status STRUCTURE(zero one two track$no head$addr sector$no pass$fail n

BYTE,

BYTE,

Byn:,

BYTE,

BYTE,

BYTE,

BYTE,

BYTE) PUBLIC;

1* The following are variables and literals used by the program *1

DECLARE base$addr WORD PUBLIC; ;* Base address of iSBC 208 *1

DELCARE (temp',temp2,temp3) BYTE; 1* Temporary byte variables *1

DELCARE (segval,offsetval) WORD PUBLIC; 1* Used to split pOinters *1

DELCARE port LiTERALLY 'base$addr + 11'; 1* data 1/0 port on the iSBC 20b*;

1* literal declarations *;

DELCARE fail LITERALLY 'Offh';

DELCARB pass LITERALLY '0';

DELCARE failure LITERALLY 'status.pass$fail=fail; return ';

IV

external and public procedure declarations *1

DELCARE (retry,retry$number) BYTE; 1* used for soft error retrys·*1

1* SPLIT is used to get around a limitation of PLM/86. The routi~~ ~s called with a pOinter parameter and returns two words in the variables

SEGVAL and OFFSETVAL which are the segment and offset derived from the pOinter. The routine can be found right after this listing. *1 split:

PROCEDURE (buff$ptr) EXTERNAL;

DECLARE buff$ptr POiNTER;

END split;

A-3

Sample Drivers

Ie The following two routines are used to delay the programming of the

FDC between bytes to prevent overrunning the part. This delay is required by the 8272. Wait$H272 is used tor writing out to the FOC and WAIT1$H272 is used to read status from the FOC, as they use different bit sequences. *1 wait$1:l272:

PROCEDURE PUBLIC;

DECLARE (pp,i) BYTE;

1* i initialize counters *1

=

O;pp

=

0;

1* no delay. The FDC insists on this delay before reading busy bits *1

DO WHILE pp<20; pp = pp+ 1; END;

1* we have delayed enough, now loop on the busy status bits *1

DO wHILE «INPUT(base$addr+10) AND OcOh <> 80h);

Ie we do not want to hang up, so only attempt this 100 times *1 i = i+1; IF i = 100 THhN RETURN;

END;

RETURN;

END wait$8272; wait1$H272:

PROCEDURE PUBLIC;

DECLARE (pp,i) BYTE; i

1* initialize counters *1

= 0; pp = 0;

1*

DO set up a delay *1

WHILE pp<20; pp

= pp+1; END;

1* now set up a loop to read the busy status *1

DO wHILE «INPUT(base$addr+10) AND OcOh) <> OcOh); i = i+1; IF i = 100 THEN RhTURN;

END;

RETURN;

Ef'jD wait1$o272; iSBC 208

A-4

iSBC 208

Sample Drivers read$data:

This module contains the code to program the 8272 for a read data instruction. It accepts one parameter which determines if the instuction is for read data or read deleted data •

••••• * ••• * ••• * •••••••••••••••••••

fi • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

1 read~data:

PROCEDURE(del) PUBLICj

DECLARE del BYTEj

I · determine the type of read and set up the parameters . /

IF del=O THEN temp2=06hj ELSE IF del=1 THEN temfl2=Ochj ELSE temp2=02hj

I · byte 1 litl

OUTPUT(port)=shl(iopb.mt$mf$sk,5) OR temp2;

CALL wait$8272j

I· byte 2 .1 temp1=(shr«iopb.head$drive AND 'Oh,2) + (iopb.head$drive AND 03h»j

CALL wait$8272j

OUTPUT(port)=temp1j llit byte 3 ·1

CALL wait$b272j

OUTPUT(port)=iopb.track$noj llit byte 4 .1

CALL wait$8272 j

OUTPUT(port)=shr«iopb.head$drive AND 10h),4)j

I· byte 5 *1

CALL wait$8272j

OuTPUT(port)=iopb.sector$noj

I· byte 6 ·1

CALL wait$8272 j

OUTPUT(port)=iopb.nj lilt byte 7 *1

CALL wait$b272j

OUTPUT(port)=iopb.sectors$perj lilt byte 8 .1

CALL wait$8272j

OUTPUT(port)=iopb.gap$3i

I · byte 9 *1

CALL wait$8272j

OUTPUT(port)=Offhj

RETURNj

END read$dataj

A-5


I •••• ~ •••

**** ••• *.** •••••••••• *.** •••• ** ••••

* •••••••••• ••••••••••••••••••

WRITE$DATA:

This module contains the code to program the 8272 for a write data instruction. It accepts one parameter which determines if the instuction is for write data or write deleted data •

••• * ••••••• * ••••••••• * •••••••••••••••••••••••••••••••

*

···················*1

write$data:

PROCEDURE(del) PUBLIC;

DECLARE del BYTE;

I· determine if write data or deleted data ·1

IF del=O THEN temp2=05h; ELSE temp2=09h;

I·byte 1 .1

CALL wait$o272;

OUTPUT(port)=shl(iopb.mt$mf$sk,5) OR temp2;

CALL wait$f:l272;

I*byte 2 ·1 temp1=(shr«iopb.head$drive AND 10h),2) + (iopb.head$drive AND 03h»);

CALL wait$e272;

OUTPUT(port)=temp1;

I·

byte 3

·1

CALL wait$b272;

OUTPUT(port)=iopb.track$no;

I·byte 4 ·1

CALL wait$8272;

OUTPUT(port)=shr«iopb.head$drive AND 10h),4);

I· byte 5 ·1

CALL wait$b272;

OUTPUT(port)=iopb.sector$no;

I·byte 6 ·1

CALL wait$e272;

OUTPUT(port)=iopb.n;

I·byte '7 ·1

CALL wait$f:l272;

OUTPUT(port)=io~.sectors$per;

I.

byte b

·1

CALL wait$tiC72;

OUTPUT(port)=iopb.gap$3;

I·oyte 9 ·1

CALL wait$b272;

OUTPUT(port)=Offh;

RETURN;

END write$ da ta;

A-6

iSBC 208 Sample Drivers

/

......................................••••••.................•......••.•.

FORMAT$COMMAND:

This module contains the code to program the 8272 for a format track instruction •

•••••••••••••••••••••••••••••••••••••••••••••••••••••• """"""""""1

format$command:

PROCEDURE PUBLICj temp1=iopb.mt$mf$sk AND 02h;

I'byte 1 '1

CALL wai t$ci27 2 j

OUTPUT(port)=(shl(temp1,5) OR Odh)j

CALL wait$i3272j

I'byte 2 ' i temp2=(shr{(iopb.head$drive AND 10h),2) + (iopb.head$drive AND 03h»;

OUTfUT(port)=temp2;

I'byte 3 '1

CALL wait$tl272;

OUTPUT(port)=iopb.n;

I'byte 4 . /

CALL wa1t$t)272;

OUTPUTlport)=iopb.sectors$per;

I'byte 5 '1

CALL wa1t$tl272;

OUTPUT(port)=iopb.gap$3;

I'byte 6 ' i

CALL wait$tl272;

OUTPUT(port)=4eh;

RETURN;

END format.command;

A-7


, ........................................................................ .

READ$lD:

This module contains the code to program the ti272 for a read id instruction •

.......................................................................... ,

read$id:

PROCEDURE PUBLIC;

'·byte 1 . , temp1=shl(iopb.mt$mf$sk AND 02h,5); temp2=temp1 OR Oah;

CALL wait$1:l212;

OUTPUT(port)=temp2;

'.byte 2 . , temp1=(shr«iopb.head$drive AND 10h),2)

+

(iopb.head$drive AND 03h»;

CALL wait$8212;

OUTPUT(port)=temp1;

RETURN;

END read$id;

A-8

iSBC208 Sample Drivers

/

....................................................................... .

S"PECIFY:

This module contains the code to set up the iSBC 208 to the desired disk controller parameters. The parameters to be INPUT to the FDC are: Head Unload Time, the time to wait before removing the read/write head from the diskj Step Rate, the time to wait between step pulses on seeksj and Head Load Time, the time to wait before loading the read/write head onto the disk. The module will program the e272 with the correct values. This module features full error checking for INPUT boundaries •

• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • */ specify:

PROCEDURE PUBLICj

DECLARE lbyte$2,byte$3) BYTEj

DECLARE (step$rate,hd$unld$tm,stp$rate,hd$ld$tm) BYTEj

/* reset the iSBC 20e before beginning the SPECIFY command . /

OUl'PUT( base$addr + 13h) =Offhj /. board reset . /

/. set the head unload time to 10 . / hd$unld:ptm=10j

/. set the step rate to 3 . / step$rate=3j

/* set the head load time to 70 . / hd$ld$tm=70j

/* this section puts the info in the form that the FDC wants . / byte$2=hd$unld$tm

+ shl«(step$rate 1) XOR Offh),4)j stp$rate;(step$rate 1) XOR Offhj

/. set up the byte for the FDC . / byte$3=shl(hd$ld$tm,1) AND Ofehj

/* now start spitting the bytes to the FDC as needed *1

CALL wait$d272j

OUTPUT(port)=03hj /. specify command . /

CALL wait$b272j

OUTPUT(port)=byte$2j /. head unload time and step rate . /

CALL wait$8272j

OUTPUT(port)=byte$3j /* Head load time . /

/- ok we are done, now return . /

R El'U RN j

EN]) specifYj

A-9


1 this is the main driver routine *1 execute$instruction:

PROCEDURE PUBLIC;

1* first set the retry counter to 0 *1 retry$number=O;

1* now enter the section to take the IOPB apart *1 skip: retry=O; 1* reset retrys *1

IF iopb.instruction<= 9/~ for all instructions less than 9, DMA is needed *1

THE;N DO:

1* DMA is required *1

CALL split (iopb.buffer); 1* split pOinter into 2 words *1

OUTPUT(base$addr + 14h)=LOW(seg$val); 1* low byte of segment register *1

OUTPUT(base$addr +

15h)=HIGH(seg~val); 1* programming segment reg on 208 *1

OUTPUT(base$addr + Och)=O; 1* clear first/last flip-flip *1

OUTPUT(base$addr

+

Odh)=O; 1* master clear the DMA chip *1

OUTPUT(base$addr + Obh)=OOh; 1* mode reg for channel 0 *1

OUTPUT(base$addr + Obh)=Olh; 1* mode reg for channell *1

OUTPUT(base$addr + Obh)=02h; 1* mode reg for channel 2 *1

OUTPUT(base$addr + Obh)=03h; 1* mode reg for channel 3

*'

OUTPUT(base$addr + Och)=O; 1* first/last flop *1 iopb.byte$cnt=iopb.byte$cnt-l;

1* PROGRAM CHANNEL 0 OF 8237 *1

OUTPUT(base$addr)=LOW(offset$val); 1* base address of memory buffer *1

OUTPUT(base$addr)=HIGH(offset$val);

OUTPUT(base$addr + Och)=O; 1* clear first/last flip-flop *1

I"

CHANNEL 0 *1

OUTPuT(base$addr + 01h)=LOW(iopb.byte$cnt); 1* number of bytes to move *1

OUTPUT(base$addr + 01h)=HIGH(iopb.byte$cnt);

OUTPUT(base$addr

+

06h)=0; /* DMA chip command *1

1* determine if read or write memory DMA direction */

IF (iopb.instruction=l) or (iopb. instruction=4)

OR (iopb.instruction=5)

THEN temp3=44h; 1* disk to memory transfer *1

ELSE temp3=46h; /* memory to disk transfer */

OUTPUT(base$addr + Obh)=temp3; /* DMA mode register *1

OUTPUT(base$addr-+ Ofh)=Ofah; /- DMA mask register *1

END; 1* end of DMA section *1$

A-lO

Sample Drivers iSBC208

'* now we program the 8272 chip for the operation selected. To do this, we use a case statement to either call the correct procedure or execute the proper statements.

*'

DO CASE iopb.instruction

,* case 0 case 1

,* case 2 case 3

,* case 4 case 5 ,*

,* case 6 case 7 case 8 case 9

*'

-

1 ;

*' CALL write$data( 1);

CALL read$data(1);

*'

*'

*'

CALL read$data(O);

CALL write$dat.a(O) ;

CALL read$data(2);

RETURN;

RETU RN;

RETURN;

,* not used til not used not used

CALL read$id;

,* between 0 and 14 *'

CALL format$command;

*'

'ti case 10

*'

DO; CALL wait$8272;

OUTPUT(port)=07h;

CALL wait$8272;

OUTPUT(port)=iopb.head$drive AND 03h;

END;

/*

/* case 11 */ DO; CALL wait$8272;

OUTPUT(port)=08h;

END; case 12

*'

CALL specify;

/* case 13 */ DO; CALL wait$d272;

OUTPUT(port)=04h; temp1=(shr«iopb.head$drive AND 10h),2)

+ (iopb.head$drive AND 03h»;

CALL wai.t$tl272;

OUTPUT(port)=temp1;

END;

/* case 14 */ DO; CALL wait$8272;

OUTPUT(port)=Ofh; temp1=(shr«iopb.head$drive AND 10h),2)

+

(iopb.head$drive AND 03h»;

CALL wait$8272;

OUTPUT(port)=temp1;

CALL wait$8272;

OUTPUT(port)=iopb.track$no;

END;

END; /* end of do case block */

A-ll


IF iopb.instruction=15 THEN RETURN; 1* return now if seek *1

IF (iopb.instruction=13) OR (iopb.instruction=11) THEN RETURN;

IF (iopb.instruction=14) THEN GOTO over;

1* loop on FINT bit from 0272 to detect DONE interrupt *1 temp1=Ofeh;

DO WHILE (INPUT(base$addr

+

12h) OR temp1) = temp1;

END;

I · Now get the status from the 8272 and fill the STATUS block. ~he number of status bytes to be read is determined by the instruction. Most instructions require 9 bytes be read, but some only need 1 or 2. *1 over: status.pass$fail=pass; 1* we made it to here ok *1

IF iopb.instruction<=10

THEN DO;

CALL wait1$t)272; status.zero=INPUT(port);

CALL wait1$8272; status.one=INPUT(port);

CALL wait1$tl272; status.two=INPUT(port);

CALL wait1$ti272; status.n=INPUT(port);

CALL wait 1 $8272; status.head$addr=INPUT(port);

CALL wait1$ti272; status.sector$no=INPUl(port);

CALL wait1$82'72; status.n=INPUT(port);

A-12

iSBC 208

/ see if a retry is needed */

IF (status.zero AND OcOh)=O THEN retry=O;

ELSE DO; retry$number=retry$number+1;

IF retry$number>3 THEN retry=O;

ELSE retry=1;

END;

IF retry=1 THEN GOTO skip;

RETURN;

END;

IF liopb.instruction=141

THEN DO; CALL wait1$H272; status.zero=INPUT(port);

RETURN

END;

IF iopb.instruction=12

THEN DO; CALL wait1$H272; status.zero=INPUT(port);

CALL wait1$d2'(2; status.track$no=INPUT(port);

RETURN;

END;

IF iopb.instruction>=16 THEN RETURN; status.pass$fail=fail;

RETURN;

END execute$instruction;

END execute$mode; /*jbe*/

Sample Drivers

A-13


*********************************************************.**************

SPLIT:

ACCEPTS: ONE POINTER IN THE STACK POINTED TO BY THE BP REG

DESTROYS: SI,DI

USES: TWO MEMORY LOCATIONS TO PLACE THE SEGMENT AND OFFSET INTO

WHICH ARE DECLARED PUBLIC IN STRUCT.

FUNCTION: TO SPLIT THE POINTER INTO TWO WORDS, A SEGMENT AND AN OFFSET,

SO THAT PLM/86 CAN PROGRAM THEM INTO THE 208 BOARD. THE TWO

NAME

WORDS ARE RETURNED IN THE LOCATIONS SEG_VAL AND OFFSET_VAL.

,

,

POINTER_SPLITTER

PUBLIC SPLIT

DGROUP GROUP DATA

CGROUP GROUP CODE

ASSUME CS:CODE,DS:DATA

DATA SEGMENT WORD PUBLIC 'DATA'

EATRN SEGVAL:WORD,OFFSETVAL:WORD

DATA ENDS

CODE

SPLlT

SEGNENT WORD

PROC fAR

PUBLIC 'CODE'

;FAR CALL TO AID IN THE LINK

SPLIT

COOE

PUSH

MOV

MOV

MOV

MOV

~jOV

POP

RET

ENDP

ENDS

BP

BP , SP

DI,[BP+d] ;GET THE SEGMENT OUT OF THE STACK

SI,[BP+6] ;GET THE OFFSET OUT Of THE STACK

SEGVAL,DI ;PUT THE SEGMENT INTO MEMORY

OFFSETVAL,SI jPUT THE OFFSET INTO MEMORY

BP

4 jRETURN TO CALLER

A-14

iSBC 208

A-3. ASSEMBLY LANGUAGE DRIVER

A!:,;M80 DR208. SOR

Sample Drivers

ISIS-I I 8080/8085 MACRO ASSEMBLER, V~:. 0

LOC OB ....

I

0010

MODULE PAGE

LINE !;OURCE !:;;TATEMENT

1

2

;*******************************************************

;*******************************************************

3 ; sec 208 FLEXIBLE DISK CONTROLLER liD SUBROUTINES

5

6

7

;*******************************************************

;*******************************************************

VER EQU 10H ; VERSION 1.0

8

9

10

;*******************************************************

THERE ARE TWO LEVELS OF SUBROUT I NE::;:; PRCrV I DED.

11 LEVEL 1 SUBROUTINES ARE THE PRIMITIVE SUBROUTINES.

12 WHEN USING THESE SUBROUTINES, IT IS POSSIBLE TO WRITE

13 SPECIAL USER ORIENTED SUBROUTINES TO PERFORM DISKETTE

14 1/0 OPERATIONS

17

18

19

20

21

16 THE LEVEL 1 SUBROUTINES:

ARE USER CALLABLE THRU THE JUMP TABLE

USE ALL 8085 REGISTERS

RETURN IMMEDIATELY IF FDC IS BUSY

FOLLOW PL/M CONVENTIONS FOR PARAMETER PASSING

22

23 LEVEL 2 SUBROUTINES PERFORM DISKETTE 110 BY CALLING

24 THE PROPER SUBROUTINE.

44

45

46

47

48

49

50

51

~52

29

30

31

32

3::::

34

26 THE LEVEL 2 SUBROUTINES:

27

28

ARE USER CALLABLE THRU THE JUMP TABLE

PASS PARAMETERS VIA lOPS (INPUT/OUTPUT

PARAMETER BLOCK)

- SAVE AND RESTORE ALL REGISTERS EXCEPT CARRY

CARRY=O FOR NORMAL RETURN

CARRY=1 INDICATE!::; THAT A COMMAND HAND

:39

40

41

42

4::;:

SHAKING ERROR HAS OCCURED (BITS

6 AND/OR 7 OF THE MAIN STATUS

REGISTER ARE IN THE WRONG STATE)

WAIT IF FDC IS BUSY

- FOLLOW PL/M CONVENTIONS FOR PARAMETER PASSING

AUTOMATICALLY SEEK TO CYLINDER NO. IN IOPB.

USE NSEC (NUMBER OF SECTORS) FOR MULTIPLE

SECTOR 1/0

WHEN RETURNING FROM THE

D 0 NORMAL

INTERRUPT SERVICE

ROUTINE, THE "D" REGU;:;TEI:;; INDICATE!::; THE TYPE

OF TERMINATION THAT WAS COMPLETED.

THE

D = 1 ABNORMAL. EXAMINE THE RESULT BYTES

FORMAT

TO DETERMINE WHY THE OPERATION WAS

NOT COMPLETED SUCCESSFULLY.

OF EACH IOPB IS SHOWN AT THE

BEGINNING OF EACH ROUTINE. NOTE THAT COMMAND

BITS ARE Nor REQUIRED IN THE FIRST PARAMETER

AS THEY ARE INSERTED BY THE SPECIFIC ROUTINE

CALLED.

5:::: EXTENSIVE ERROR MESSAGES ARE PROVIDED TO HELP

DURING PROGRAM DEBUGGING. rHE ROUTINES AND

A-IS


0000

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

OOOA

OOOB

OOOC

OOOD

OOOE

OOOF

0010

0011

0012

0013

0014

0015

0800

0800

0803

0806

C35~i08

C3D108

C31E:09

080';> C30::::0B

080C C30[-rOEl

080F C330013

ISIS-II 8080/8085 MACRO ASSEMBLER, V3.0

LOC OBJ

OODA

0020

0040

0080

0040

MODULE PAGE 2

LINE SOURCE STATEMENT

55

56

57

58 ,

SOURCE LINES USED TO PROVIDE THESE MESSAGES

ARE MARKED AT THE END OF THE LINE WITH A "#"

SIGN. THEY CAN BE DELETED TO SAVE MEMORY SPACE

WHEN DEBUGGING IS COMPLETE.

59 ;*******************************************************

60 ; 8259 EQUATES c,l ICCP

62 EOIC

EQU

EQU

ODAH

020H

; INTERRUPT CONTROLLER CMND PORT

;END OF INTERRUPT COMMAND WORD

63

64 DMAMD EQU

65

;*******************************************************

40H ;DMA (8237) MODE

; CHO, VERIFY, AUTO-DISABLED,

66 ADDRESS INC, SINGLE

67 RD

68

69

EG"~U 80H

WR EG!U 40H

; I/O PORT EQUATES

; 8237 READ BIT

; 8237 WR ITE BIT

PUBL I C BASE, DMARO, DMWCO, DMAR 1 , DMWC 1 , DMAR2, DMWC2, DMAR:::: 70

71 PUBLIC DMWC3,DMSR,DMRQ,DMI<SR,DMODE,DCLFL,DMCLR,DMTR

72 PUBLIC DMASK, FDCST, FDCDT, AUXP, SFTRS, SEGLO, S;EGHI, READ

73 PUBLIC RDDD,WRITE,WRTDD,RDTRK,RDID,FRMTK,AUXRST,AUXSET

74 PUBLIC AUXAbR,SCNEQ,SCNLE,SCNHE,RECAL,SEEK,SPCFY,SNSDS

75 PUBLIC SNSIS,INIT,INT20,PRSLT

76 BASE EQU OH ;BASE PORT ADDRESS FOR FDC BOARD

77 DMARO EQU

78 rlMWCO EQU

79 DMARI EQU

BASE+O ;DMAC CH.O ADDRESS REG

BASE+l; DMAC CH.O WORD COUNT REG

BASE+2 ;DMAC CH.l ADDRESS REG

BASE +3 ; DMAC CH. 1 WORD COUNT REG 80 DMWC 1 EG"~U

81 DMAR2 EQU

82 DMWC2

DMAR3

EQU

EQU

84

85

86

87

DMWC3

DMSR

DMRQ

DMI<SR

EQU

EQU

EQU

EQU

BASE+4

BASE+5

BASE+6

BASE+7

BASE+8

BASE+9

BASE+OAH

;DMAC CH.2 ADDRESS REG

;DMAC CH.2 WORD COUNT REG

;DMAC CH.3 ADDRESS REG

;DMAC CH.3 WORD COUNT REG

;DMAC STATUS REGISTER

;DMAC REQUEST REGISTER

; DMAC MASK SET/RESET REG

88

89

90

91

93

94

95

'?6

97

£1M ODE

DCLFL

DMCLR

DMTR

DMASI<

FDCST

FDCDT

AUXP

SFTRS

SEGLO

SEGHI

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EI:;lU

EG"IU

EQU

EQU

BASE +OBH

BASE+OCH

BASE +ODH

BASE +OEH

BASE +OFH

BASE+I0H

BASE+I1H

BASE+12H

BASE+13H

BASE+14H

BASE + 15H

; DMAC MODE REG.

;DMAC CLEAR 1ST/LAST F/F

; DMAC MASTER CLEAR

; DMAC READ TEMP. REG,

; DMAC WR I TE MASK REG,

;FDC MAIN STATUS REG,

; FDC DATA REGISTER

;AUXILIARY PORT

; SOFTWARE RESET

;LOWER BYTE SEGMENT REG,

; UPPER BYTE SEGMENT REG.

99

100 ; ENTRY PO I NT ,...lUMP TABLE

101 ORG

102

103

104

800H

JMP

JMP

.... IMP

INTI0

INT20

INIT

;SINGLE LEVEL INTERRUPT (NO 8259)

; INTERRUPT WITH 825';> SERV I CE

;INITIALIZE DMA CONTROLLER

105 ;*******************************************************

106 ; LEVEL 1 ROUTINES

107 .JMP CMNDS ;COMMAND SERIAL OPERATION

108

109

JMP

.JMP

CMNDP

RSULT

;COMMAND PARALLEL OPERATION

A-16


ISIS-II 8080/8085 MACRO ASSEMBLER. V3.0

LOC OB.J

0812 C3DFOA

0815 C3E40A

0818 C32A09

081B C33309

081E C33C09

0821 C34509

0824 C34E09

0827 C36509

082A C36E09

082D C38809

0830 C39109

0833 C39A09

0836 C3A309

0839 C3BA09

083C C3D309

083F C3EA09

0842,C3040A

0845 C3ACOA

0848 C3B90A

084B C3DI0A

7F80

7F30

084E 297F

0850 C34300

0853 20

0854 10

0855 1600

0857 DBI0

0859 47

085A E610

085C C2BI08


MODULE PAGE 3

136

137

138

139

140

141

142

129

130

131

132

133

134

135

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

119

12.0

121

122

123

124

125

126

127

128

110

111

112

113

114

115

116

117

118

; DMA READ. I/O I.J!R ITE

;DMA WRITE. I/O READ

;*******************************************************

REGF

CONO:

.JMP

.JMP rlMARD

DMAWR

;*******************************************************

; LEVEL 2 ROUTINES

... IMP READ ; READ

.JMP

.JMP

.JMP

.JMP

.JMP

.JMP

.JMP

.JMP

.JMP

.JMP

.JMP

... IMP

.JMP

.JMP

.JMP

.JMP

.JMP

USTACK EQU

EQU

ARSBF: DW

... IMP

DELAY: DB

VERSION: DB

; RESERVE 80 LOCATIONS

;*******************************************************

INTERRUPT SERVICE ROUTINE (NON-8259 SYSTEM)

CALLING SEQUENCE

CALL INTlO

REGS: AF. BC. D. HL

STK PRS: 4+CONO

INT10: MVI D.O

IN

MOV

ANI

RDDD

WRITE

WRTDD

RDTRK

RDID

FRMTK

SCNEQ

SCNLE

SCNHE

RECAL

SEEK

SPCFY

SNSDS

SNSIS

FDCST

B.A

10H

; READ DELETED D~HE

; WRITE

; WRITE DELETED DATA

;READ TRACK

;READ ID

;FORMAT TRACK

;SCAN EQUAL

;SCAN LOW OR EQUAL

;SCAN HIGH OR EQUAL

;RECALIBRATE

; SEEK

; SPECIFY

;SENSE DRIVE STATUS

;SENSE INTERRUPT STATUS

;*******************************************************

AUXILIARY PORT ROUTINES

AUXRST; RESET-A-BIT (DR'IVE CONTROL

; FUNCTIONS)

AUXSET ;SET-A-BIT (DRIVE CONTROL

; FUNCTIONS)

AUXADR;l MEGABYTE PAGE ADDRESS BITS

7F80H ;STACK POINTER

USTACK-50H

43H

; FOR THE STACK

REGF-7; RESERVE 7 LOCATIONS FOR RESULT

; BYTES

; CONSOLE OUTPUT

; PASS DATA BYTE IN C

#

20H

VER

; ASSUMES B. DE. HL PRESERVED

;DELAY FOR FDC STATUS ()100US)

;VERSION NUMBER

;CLEAR ABNORMAL TERMINATION FLAG

;A

=

FDC STATUS

;SAVE STATUS

;FDC BUSY?

... INZ ITOlO ; YES. IS A READ. RrIDD. WRITE.

WRTDD. RDTRK. RDID. FRMTK.

SCNEQ. SCNLE. OR SCNHE INT.

SEEK/RECALIBRATE·RESULT PHASE

OR ATTENTION. ABNORMAL. INTERRUPT

A-17


LOC OBJ

OS SF 21C30B

OS62 C0720B

0865 CDS BOB

OS6S OS

OS69 3EOS

086B 0311

0860 C0300B

0870 08

0871 COE108

0874 2A4E08

0877 7E

0878 47

0879 E6CO

087B FE80

0870 C8

087E B7

087F CA6508

0882 FECO

0884 CA9508

0887 1601

0889 21E50B

088C CD720B

088F COE108

0892 C3650S

0895 3E08

0897 AO

0898 C26508

089B 3E03

0890 AO

089E 47

089F C05BOB

08A2 08

08A3 3E07

08A5 0311

08A7 C05BOB

08AA D8

08AB 78

08AC D311

08AE C36508

OSBl 21070B

08B4 CD720B

08B7 C0300B

08BA DS

08BB COEI08

OSBE 2A4EOS

08Cl 7E

08C2 E6CO

OSC4 C8

OSC5 21F40B

08C8 C0720S

ISIS-II SOSO/SOS5 MACRO ASSEMBLER, V3.0 MODULE PAGE 4


165

166

LXI

CALL

167 IT002: CALL

168 RC

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

MVI

OUT

CALL

RC

CALL

LHLD

MOV

MOV

ANI

CPI

RZ

ORA

,..IZ

CPI

.JZ

MVI

LXI

CALL

H,MSG30 ; "FDC SEEKIATTN INT"

MESSG ;PRINT MESSAGE

RDYC ;FOC READY FOR COMMAND?

#

#

; NO"FDC ERR OIO HI IN CMO PHASE"

A,08H ; YES

FOCOT ;SENSE INTERRUPT STATUS

; (CLEARS INTERRUPT FROM 8272)

RSULT ;REAOFOC STATUS

; ERROR" D I 0 ERR LO IN RSL T PHASE'"

PRSLT ;PRINT RESULT BYTES

ARSBF

#

A,M

B,A

OCOH

SOH

;A = STATUS REGISTER 0

;SAVE STATUS

;EXAMINE UPPER TWO BITS

A

; INVALID COMMAND? (10)

; YES, RETURN

;NORMAL TERMINATION? (00)

IT002; YES, CHECK FOR HIDDEN INTERRUPTS

OCOH ; NO, ATTENTION INTERRUPT? (11)

IT008; YES

D,l ;SET ABNORMAL TERMINATION FLAG

H,MSG50 ;NO, ABNORMAL TERMINATION

MESSG ; "FDC SEEK ERR"

«)1)

188

189

CALL

JMP

PRSLT ;PRINT RESULT BYTES

IT002 ;CHECK FOR HIDDEN INTERRUPTS

190 ATTENTION INTERRUPT

191 IT008: MV I A, 08H ; A=FDD READY MASK FOR ::HO

#

#

#

200

201

202

20::::

204

205

206

192

193

196

197

198

199

ANA

JNZ

B ; IS THE FOO READY?

IT002 ;NO, CHECK FOR HIDDEN INTERRUPTS

194 ; RECALI BRATE FOR NEWL Y MOUNTED

[II

SK

195 MVI A,3H ;A=UNIT SELECT MASK

ANA

MOV

CALL

RC

B

B,A

RDYC

;A = US?

;SAVE UNIT SELECT

; ERROR "010 ERR"

MVI

OUT

CALL

RC

MOV

OUT

... IMP

A,07H

FDCDT; RECALIBRATE

RDYC

; ERROR "010 ERR"

A,B

FDCDT ;OUTPUT UNIT SELECT

I T002 ; CHECK FOR HIDDEN INTERRUPTS

207 ; 1/0 INTERRUPT

208 ITOlO: LXI

209

210

211

CALL

CALL

212

213

214

RC

CALL

LHLD

215

216

217

218

219

MOV

ANI

RZ

LXI

CALL

H,MSG40 ; "FDC

MESSG

ARSBF

A,M

OCOH

1/0 INT"

;PRINT MESSAGE

RSULT ;GET RESULT BYTES

; AND RESET 8272 INTERRUPT

; ERROR "010 ERR"

PRSLT ;PRINTRESULT BYTES

;A=STATUS REGISTER 0

;NORMAL TERMINATION?

;YES, "INTERRUPT CODE IS ZERO"

H,MSG60 ;NO, ERROR

MESSG ; "FDC I/O ERR"

#

#

#

#

#

A-I8


ISIS-II 8080/8085 MACRO ASSEMBLER. V3.0

LOC OB..J

08CB CDEI08

08CE 1601

08DO C9

08D1 CD190j~

08D4 3E20

08D6 D3DA

08D8 CD550~3

08DB F1

08DC C1

08DD D1

08DE E1

08DF FB

08EO C9

08El C5

08E2 41

08E3 2A4E08

08E6 OE20

08E8 CD5008

08EB 7E

08EC CD0409

08EF 7E

08FO CD0809

08F3 23

08F4 05

08F5 C2E608

08F8 OEOD

08FA CD5008

08FD OEOA

08FF CD5008

0902 C1

0903 C9

0904 OF

0905 OF

0906 OF

0907 OF


MODULE PAGE 5

220

221

222

CALL

MVI

RET

PRSLT

D.1

;PRINT RESULT BYTES

;SET ABNORMAL TERMINATION FLAG

#

223

;***************************************if***************

224 INTERRUPT SERVICE ROUTINE .(SYSTEMS WITH 8259)

225 SAVES ALL REGISTERS. PROCESSES INT FROM 8272

226 RESTORES ALL REGISTER. AND ·RETURNS

227

228 REGS: NONE

229 STK PRS: 9+CONO (NOTE: INTERRUPT USES l. PAIR)

230 INT20: CALL

231 MVI

232 OUT

SAVER ;SAVE REGISTERS

A.EOIC ;A=END OF INTERRUPT COMMAND

ICCP ;RESET INTERRUPT CONTROLLER

233 ; NOTE: 8259 MUST USE EDGE TRIGGER MODE

234 CALL INT10 ;PROCESS INTERRUPT

235

236

237

238

239

240

POP

POP

POP

POP

EI

RET

PSW

B

D

H

; RESTORE

ALL

REGISTERS

AND

ENABLE INTEHRUPTS

RETURN

241

;***************************************,****************

242 PRINT RESULT BYTES (THIS ROUTINE CAN BE ELIMINATED

266

267

268

269

270

271

272

273

274

253

254

255

256

257

258

259

260

261

262

263

264

265

243

244

245

246

247

248

249

250

251

252

REGS: AF, HL

STK PRS: 2+CONO

PRSLT: PUSH

MOV

LHLD

PROO5: MVI

CALL

B

B.C

;SAVE BC

;B=BYTE COUNT

ARSBF ;ADR OF RESULT

., .' ;PRINT

CONO ; SPACE

MOV

CALL

MOV

CALL

INX

DCR

..JNZ

MVI

CALL

MVI

CALL

A.M ;PRINT

PROlO ; MSN

A.M ;PRINT

PR020 ;LSN

H ;BUMP POINTER

B ; DONE?

PROOS ;NO

C,ODH ;YES, PRINT

CONO ;CR

C,OAH ;PRINT

CONO ; LF

,

.

C= # OF BYTES

CALL PRSLT

POP

RET

PRINT MOST SIGNIFICANT NIBBLE

PROlO: RRC

RRC

RRC

B

WHEN ERROR MESSAGES ARE NO LONGER

REQUIRED)

; RESTORE BC

; MOVE

LEFT

NIBBLE

RRC TO RIGHT

PRINT LEAST SIGNIFICANT NIBBLE

BUFFER

A-19



LOC OB.J

0908 EMF

090A D60A

090C OE3A

090E DA1309

0911 OE41

0913 81

0914 4F

0915 C35008

0918 F3

0919 CD190A

091C 3E40

091E D30B

0920 3C

0921 FE44

0923 C21E09

0926 FB

0927 C31EOA onA CDl90A

092D 21E649

0930 C32DOA

MODULE PAGE 6


298

299

300

301

302

30:3

304

305

306

307

:308

309

310

311

312

::;:13

314

:315

316

317

318

319

320

321

:322

275 PR020:

276

277

278

279

280 PR030:

281

282

ANI

SUI

MVI

,-IC

MVI

ADD

MOV

.JMP

OFH

OAH

C,3AH

PR030

C,41H

C

C,A

CONO

DMODE

A

DMAMD+4

INIO

; o TO 15

; -10 TO 5

;ASCII DISPLACEMENT FOR 0 TO 9

283 ;*******************************************************

284 I N I TI ALI Z E 8237 DMA CONTROLLER

285

286

287

288

289

290

291

REGS:: F (CARRY = 0)

STI< PRS: 4

INIT: DI

CALL

MVI

SAVER

A,DMAMD

;DISABLE INTERRUPTS WHILE

;INITIALIZING BOARD

;SELECT DMA MODE

292

293

294

295

296

297

INIO: OUT

INR

CPI

.JNZ

EI

.JMP RSTOR

;ASCII DISPLACEMENT FOR A TO F

;CONVERT BINARY TO ASCII

;PASS CHAR IN C

;PRINT CHA~

;SET 8237 MODE

;SELECT NEXT CHANNEL

;LAST CHANNEL

; NO, SET ALL CHI=INNELS

;RE-ENABLE INTERRUPTS

;RETURN TO USER, CARRY=O

323

326

:327

;**************************************~r****************

LEVEL 2 ROUTINES

USER CALLABLE

SAVE ALL REGISTERS EXCEPT CARRY

;*******************************************************

READ

CALLING SEQUENCE

BC=ADR(IOPB)

IOPB: MT.MF,SI(,X ;X=SPACE FOR COMMAND

HD,US lHEAD, UNIT r

H

R

N lCYLINDER lHEAD

; RECORD lSECTOR SIZE

EOT

GPL

DTL

NSEC

;END OF TRACK lGAF' LENGTH

;DATA LENGTH lNUMBER OF SECTORS

DE=ADR(DATA)

CALL READ

NORMAL RETURN, CARRY=O (NC)

ERROR RETURN, CARRY=1 (C)

REGS: CARRY

STI< PRS: 13+CONO

READ: CALL

LXI

.JMP


H, (WR+9) SHL 8 + OEOH + 06H lDMA WRITE,

1 9 BYTES, MTMFSK MASK, COMMAND

DTRN1 lDATA TRANSFER COMMAND

328 ;*******************************************************

329 ; READ DELETED DATA

A-20

iSBC208

Sample Drivers


LOC OB..J

0933 CD190A

0936 21EC49

0939 C32DOA

093C CD190A

093F 21C589

0942 C32DOA

MODULE PAGE 7


330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

CALLING SEQUENCE

BC=ADR(IOPB)

IOPB:

DF=ADR(DATA)

CALL WRITE

MT.MF.SK.X;X=SPACE FOR COMMAND

HD. US ; HEAD. UN IT SELECT

C

H

R

N

EOT

GPL

EOT

GPL

DTL

NSEC

; CYL I NDEJ;:

; HEAD

; RECORD

; SECTOR SIZE

; END OF TRACK

; GAP LENGTH

; DATA LENGTH

; NUMBER OF SECTORS

347

348

349

REGS: CARRY

STK PRS: 13+CONO

350

351

352

RDDD: CALL

LXI


H. (WR+9) SHL 8 + OEOH + OCH ;DMA WRITE.

;9 BYTES, MTMFSK MASK. COMMAND

353 ..JMP DTRN1

354

;***************************************~f***************

355 WRITE DATA

356

357

358

359

360

361

362

363

364

365

366

367

368

369

DE=ADR(DATA)

CALLING SEQUENCE

BC=ADR(IOPB)

10PB:

DTL

NSEC

CALL RDDD

NORMAL RETURN. CARRY=O (NC)

ERROR RETURN. CARRY=1 (C)

MT,MF,X

HD,US

C

H

R

N

;X=SPACE FOR COMMAND

; HEAD. UNIT SELECT

;CYLINDEH

; HEAD

; RECORD

;SECTOR SIZE

;END OF TRACK

;GAP LENGTH

;DATA LENGTH

;NUMBER OF SECTORS

370

371

372

373

374

375

376

377

378

379



REGS: CARRY

STK PRS: 13+CONO

WRITE: CALL

LXI

..JMP

SAVER

DTRN1

;SAVE REGISTERS

H.(RD+9) SHL 8 + OCOH + 05H ;DMA READ.

;9 BYTES, MTMFSI< MASK, COMMAND

380

382

;*******************************************************

381 WRITE DELETED DATA

383

384

CALLING SEQU~NCE

BC=ADR(IOPB)

A-21



LOC OB.J

0945 CD190A

0948 21C989

094B C32DOA

094E CD190A

0951 2162'~9

0954 OA

0955F5

0956 C5

0957 E5

0958 D5

0959 CDC609

095C DA380A

MODULE PAGE 8


396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

4-14

415

416

417

385

386

387

388

389

390

391

392

393

394

395

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

IOPB:

R

N

EOT

GPL

; RECORD

;SECTOR SIZE

;END OF TRACK

;GAP LENGTH

DTL

NSEC

;DATA-LENGTH

;NUMBER OF SECTORS

DE=ADR<DATA)

CALL WRTDD



REGS: CARRY

STK PRS: 13+CONO

WRTDD: CALL

LXI

...IMP

READ A TRACK

MT,MF,X

HD,US

C

H


;HEAD, UNIT SELECT

; CYLINDER

; HEAD


H,(RD+9) SHL 8 +OCOH +09H ;DMA READ

DTRN1

;9 BYTES, MTMFSK MASK, COMMAND

;**************************************~;****************

CALLING SEQUENCE

BC=ADR(IOPB)

IOPB: MF, SK, X

HD,US

C

H

R


;HEAD, UNIT SELECT

; CYLINDER

; HEAD

; RECORD

N

EOT

GPL

DTL

NSEC

;SECTOR SIZE

;END OF TRACK

;GAP LENGTH

;DATA LENGTH

;#

DE=ADR(DATA)

CALL RDTRI<



OF SECTORS (NOT lISED)

REGS: CARRY

STK PRS: 14+CONO

RDTRK: CALL SAVER ;SAVE USER REGISTERS

LXI

LDAX

PUSH

PUSH

PUSH

H, (WR+9) SHL 8 + 60H + 02H ;DMA WRITE,

;9 BYTES, MTMFSK MA3K, COMMAND

B

PSW

B

H

;SAVE

; MT,MF,SK

;SAVE ADDR(10PB)

; SAVE ADR <DATA)I

PUSH D ;SAVE PARAMETERS

SEEK

CALL

.JC

SKOl!)

DT005 ;.JUMP IF ERROR

FORCE DTRN ROUTINE TO USE EOT INSTEAD OF NSEC TO

A-22



LOC OSJ

095F 2103001

0962 C3440A

0965 CD190A

0968 214A02

096B C391 O~\

096E CD 1 90~~

0971 210300

0974 09

0975 6E

0976 2600

0978 29

0979 29

097A 2B

097S C5

097C 4D

097D 44

097E CDDFO~~

0981 Cl

0982 214D06

0985 C39l0A

MODULE PAGE 9


440

441

442

443

444

445

446

447

448

449

450

451

452

453

CALCULATE BYTE COUNT

LXI H,3

.... IMP DT015

;DISPLACEMENT FOR EOT

;PICI< UP IN MIDDLE OF DTRN

; ROUTINE

;*******************************************************

READ ID

NOTE: MUST BE PRECEDDED BY A SEH:

CALLI NG SEQUENCE

BC=ADR ( I OPB ) ....

1 lOPS: MF,X ;X=SPACE FOR COMMAND

HD, US ; HEAD, UN IT SELECT

CALL RDID


ERROR RETURN, CARRY=1

(C)

481

482

483

484

485

486

487

488

489

490

491

492

493

494

4~.3

464

465

466

467

468

469

470

471

472

473

474

475

476

454

455 REGS: CARRY

456 STI< PRS: 11+CONO

457 RDID: CALL

458 LXI

459

460 JMP

SAVER

H,2 SHL

DTRN2 lSAVE REGISTERS

8 + 040H + OAH ;NO. OF BYTES,

; MTMFSI< MASK, COI"IMAND

461 ;*******************************************************

462 FORMAT A TRACI<

NOTE: MUST BE PRECEEDED BY A SEE~:

CALLING SEQUENCE

SC=ADR(IOPB) lOPS: MF,X

HD,US

N


; HEAD, UNIT SELECT

; SECTOR S;I ZE

SC

GPL3

D

;SECTORS/TRACI< lGAP LENGTH lDATA

DE=ADR(DATA)

CALL FRMTI<


ERROR RETURN, CARRY=l (C)

477

478

479

480

REGS: CARRY

STI< PRS: 11+CONO

FRMTK: CALL SAVER

LXI H,3

;SAVE REGISTERS

;HL POINTS TO SC PARAMETER DAD

MOV

MVI

DAD

DAD

DCX

PUSH

MOV

MOV

CALL

POP

LXI

... IMP

B

L,M

H,C>

H

H

H

B

C,L

B,H

DMARD

B

H,6 SHL

DTRN2

;HL=SC

;DOUBLE COUNT

; GKIADRUPLE COUNT

;DECREMENT FOR 8237

;SAVE ADR(IOPB)

; BC=COUNT

;SET UP 8237

;RESTORE ADR(lOPE!)

8 + 04C>H + ODH ;NO. OF BYTES,

;MTMFSI< MASK, COMMAND

A-23

Sample Drivers

iSBC208


LOC OB..J

0988 CD190A

098B 21F189

098E C32DOA

0991 CD190A

0994 21F989

0997 C32DOA

MODULE PAGE 10


536

537

538

539

540

541

542

543

544

545

546

547

548

549

503

504

505

506

507

508

509

510

495

496

497

498

499

500

501

502

511

;*******************************************************

SCAN EQUAL

524

525

526

527

528

529

530

531

532

533

534

535

512

513

514

515

516

517

518

519

520

521

522

523

CALLI NG SEQUENCE

BC=ADR(IOPB)

IOPB: MR.MF.SK.X;X=SPACE FOR COMMAND

UD. US ; HEAD. UNIT SELECT

C ; CYLINDER

H

R

N

EOT

GPL

STP

NSEC

; HEAD

; RECORD

;SECTOR SIZE

; END OF TRACK

;GAP LENGTH

OR 2)

;NUMBER OF SECTORS

DE=ADR<DATA)

CALL SCNEQ


ERROR RETURN. CARRY=l (C)

REGS: CARRY

STK PRS: 13+CONO

SCNEQ: CALL SAVER ; REGISTERS

LXI H.(RD+9) SHL

;9

8 + OEOH + 11H ;DMA READ.

BYTES. MTMFSK MASK. COMMAND

JMP DTRNl

;*******************************************************

SCAN LOW OR EQUAL

CALLING SEQUENCE

BC=ADR(IOPB)

I OPEl: MT.MF.SK.X ;X==SPACE FOR COMMAND

HD.US ;HEAD, UNIT SELECT

C

H

; CYLINDER

; READ

R

N

EOT

; RECORD

;SECTOR SIZE

;END OF TRACK

GPL

STP

NSEC

;GAP LENGTH

;STEP (1 OR 2)

; NUMBER OF SECTORS

DE=ADRCDATA)

CALL SCNLE



REGS: CARRY

STK PRS: 13+CONO

SCNLE: CALL

LXI


H.(RD+9) SHL 8 + OEOH + 19H ;DMA READ.

;9 BYTES, MTMFSK MASK. COMMAND

JMP DTRN1

;*******************************************************

;SCAN HIGH OR EQUAL

A-24

iSBC 208

Sample Drivers


LOC OB,J

099A

cI.ll

90A

0990 21F089

09AO C3200A

09A3 C0190A

09A6 OA

09A7 F5

09A8 C5

09A9 3E07

09AB 02

09AC lE02

09AE COO BOB

09Bl OAA50A

09B4 C2AE09

09B7 C3A50A

MODULE PAGE .11


562

563

564

565

566

567

568

569

570

571

572

550

551

552

553

554

555

556

557

558

559

560

561

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

573

574

575

576

577

578

579

580

581

582

583

584

585

CALLING SEQUENCE

BC=AOR(IOPB)

IOPB: MT, MF, SK, X ; X=SI"'ACE FOR COMMAND

HD,US ;HEAD, UNIT SELECT

C ; CYLINDER

H

R

N

;HEAO

; RECORD

;SECTOR SIZE

EOT

GPL

STP

NSEC

;END OF TRACK

;GAP LENGTH

;STEP (lOR 2)

;NUMBER OF SECTORS

DE=ADR(DATA)

CALL SCNHE


ERROR RETURN, CARRY=l (C)

REGS: CARRY

STK PRS: 13+CONO

SCNHE: CALL

LXI


H, (RO+9) SHL 8 + OEOH + lDH ;DMA READ,

;9 BYTES, MTMFSK MASK, COMMAND

,JMP DTRNI

;*******************************************************

RECALIBRATE

CALLING SEQUENCE

BC=ADR(IOPB)

IOPB: X

O,US


;UNIT SELECT

CALL RECAL



(C)

REGS: CARRY

STK PRS: 11 +CONO

RECAL: CALL SAVER

LDAX

PUSH

PUSH

MVI

STAX

MVI

RE010: CALL

B

PSW

B

A,07H

B

E,2

CMNDP

,JC

,JNZ

... IMP

DT060

RE010

DT060

;SAVE REGISTERS

;MT,MF,SK

;SAVE MT,MF,SK

; SAVE ADR ( MR, MF , SIO

;A=CAMMAND

;STORE COMMAND IN IOPB

;B=NO. OF BYTES IN COMMAND

; RECALIBRATE

; QUIT IF ERROR

;WAIT IF FDC BUSY

;NORMAL RETURN

;*******************************************************

SEEK

CALLING SEQUENCE

BC=ADR(IOPB)

IOPB: X

HD,US

C

;S=SPACE FOR COMMAND

;HEAD, UNIT SELECT

; CYL. I NDER

A-25



LOC OB .

09BA CD 1 901~

09BD OA

09BE F5

09BF C5

09CO CDC609

09C3 C3A50,A

09C6 3EOF

09C8 02

09C9 lE03

09CB CDOBOB

09CE D8

09CF C2CB09

09D2 C9

09D3 CD190A

09D6 OA

09D7 F5

09D8 C5

09D9 lE03

09DB 3E03

09DD 02

09DE CD03C1B

09El DAA50A

09E4 C2DE09

09E7 C3A50A

MODULE PAGE 12


605

606

607

CALL SEEK

NORMAL RETURN, CARRY=O CNC)

ERROR RETURN, CARRY=l CC)

608

609

610

611

612

613

614

615

REGS: CARRY

STK PRS: 12+CONO

SEEK: CALL

LDAX

SAVER

B

PUSH

PUSH

CALL

JMP

PSW

B

SKO!O

DT060 616

617

618 REGS: ALL

619 STK PRS: 5+CONO

620 SKOI0: MVI A,OFH

621 STAX B

;SAVE REGISTERS

;MT,MF,SK

;SAVE MT,MF,SK

;SAVE ADRCMR.MF,SK)

; ISSUE SEEK

;SET SEEK COMMAND IN 10PB c.22 MVI

623 SK020: CALL

624

625

626

627

628

629

RC

JNZ

RET

E,3

CMNDP

SK020

;NO. OF BYTES IN COMMAND

; ISSUE SEEK COMMAND

;RETURN IF ERROR

; WAIT FOR FDC RE,ADY

;***************************************~***************

SPECIFY

630

631

632

633

634

635

636

637

638

639

640 c.41

642

643

644

645

646

647

648

649

650 c.5!

652

653

654

655

656

CALLING SEQUENCE

BC=ADRCIOPB)

CALL

REGS: CARRY

SPCFY:

10PB:

SPCFY

STK PRS: 11+CONO

;*******************************************************

SENSE DRIVE STATUS

X ;X=SPACE FOR COMMAND

SRT,HUT ;STEP

NORMAL RETURN, CARRY=O CNC)

ERROR RETURN, CARRY=! CC)

CALL

LDAX

PUSH

PUSH

MVI

MVI

STAX

SPCI0: CALL

JC

JNZ

JMP

SAVER

B

PSW

B

E,3

A,03H

B

CMNDS

DT060

SPCI0

DT060

;SAVE REGISTERS

;MT,MF,SK

;SAVE MT,MF,SK

;WAIT FOR FDC READY

;NORMAL RETURN

RATE, AND

;SAVE ADRCMT,MF,SI<)


;SET COMMAND WORD

;IN 10PB

; ISSUE COMMAND

; QUIT IF ERROR

HEAD

; UNLOAD TIME

HLT,ND ;HEAD LOAD TIME, AND

; NON-DMA MODE

657

658

6.59

CALLING SEQUENCE

BC=ADR C I OPB )

IOPE(: X ;X=SPACE FOR COMMAND

A-26


ISIS-II 8080/8085 MACRO ASSEMBLER. V3.0

LOC OB ... I

09EA CD1901~

09ED OA

09EE F5

09EF C5

09FO ::':E04

09F2 02

09F3 1E02

09F5 CDOBOB

09F8 DAA501~

09FB C2F509

09FE (:D::':OOB

OA01 C3A501~

OA04 CD1901~

OA07 011801~

OAOA lEOl

OAOC CD210B

OAOF DAIEOI~

OA12 (:D300B

OA15 C31EOI~

OA18 08

OAIA D5

OAIB C5

OAIC F5

OAID E9

MODULE PAGE


660

661 c.62

663

664

CALL SNSDS

665

666

667

668

669

670 c·71

672

673

674 SD010:

675

676

REGS: CARRY

STK PRS: 11+CONO

SNSDS: CALL SAVER

LDAX

PUSH

PUSH

MVI

STAX

MVI

B

PSW

B

A.04H

B

E.2

CALL

... IC

..JNZ

CMNDP

DT060

SD010

HD,US ;HEAD, UNIT SELECT

NORMAL RETURN, CARRY=O (NC).ST3 IN RESULT BUFFER

ERROR RETURN. CARRY=1 (C)

;SAVE REGISTERS

;MT.MF.Sr.::

;SAVE MT.MF,SK

;SAVE ADR(MT,MF.SK)

;A=COMMAND

;STORE COMMAND IN IOPB


; ISSUE COMMAND

;OUIT IF ERROR

;WAIT FOR FDC READY

677

678

679

680

CALL

... IMP

RSULT

DT060

; GET ::':T3

;RETURN TO CALLER

;*******************************************************

SENSE INTERRUPT STATUS

681

682

683

684

CALLING SEOUENCE

CALL SNSIS

NORMAL RETURN,CARRY=O (NC), STO

685

686

687

688 REGS: CARRY

689 STr.:: PRS: 9+CONO

BUFFER


690 SNSIS: CALL

691 LXI

692 MVI

693

694

695

CALL

..JC

CALL

696 ..JMP

697 SNSIC: DB

SAVER

B,SNSIC ;ADR(lOPB)

E,l

CMND

RSTOR

08H

;SAVE REGISTERS

;NO. OF BYTES

; ISSUE COMMAND

RSTOR ;OUIT IF ERROR

RSULT ;GET RESULTS

; RETURN

& PCN IN RESULT

698 ;*******************************************************

699 SAVE REGISTERS ON STACK

700

701 REGS: HL

702 STK PRS: :3

703 SAVER: XTHL

704

705

706

PUSH

PUSH

707

708

PUSH

PCHL

709

710

D

B

PSW

;SAVE HL ON STACK

; HL=ADR (CALLER)

;SAVE DE

;SAVE BC

;SAVE AF

;RETURN TO CALLER

;*******************************************************

RESTORE REGISTERS FROM STACK

711

712

713

714

NORMAL RETURN, CARRY=O

ERROR RETURN. CARRY=1

A-27

Sample Drivers


LOC OB,J

OAIE DA270A

OA21 Fl

OA22 37

OA23 3F

OA24 C3290A

OA27 Fl

OA28 37

OA29 Cl

OA2A Dl

OA2B El

OA2C C9

MODULE PAGE 14


715

716

717

718

719

720

721

722

REGS: CARRY

STK PRS: -4

RSTOR: ~IC

POP

STC

CMC

~IMP

RSTC: POP

STC

RSBDH: POP

POP

POP

RET

RSTC

PSW

RSBDH

PSW

B

D

H

; RESTORE WITH CARRY=1

;RESTORE WITH CARRY=O

;RESTORE B,D,H

OA2D OA

OA2E F5

OA2F C5

OA30 E5

OA31 D5

OA32 CDC609

OA35 D2410A

OA38 El

OA39 Dl

OA3A Cl

OA3B Fl

OA3C 02

OA3D 37

OA3E C31EOA iSBC208

CALLING SEQUENCE

CALL SAVER

BC=ADR(IOPB)

DE=ADR(DATA)

L=MMMCCCCC 735

736

737

738

7~:9

740

741

742

743

744

745

746

747

748

749

750

751

752

753

754

755

756

757

758

759

760

761

762

763

764

H=RWNNNNNN

,JMP

OR

~IMP

DTRNI

BC=ADR(IOPB)

L=MMMCCCCC

H=XXNNNNNN

DTRN2



765

761;.

767

768

769

REGS: ALL

STK PRS: 9+CONO

DTRN1: LDAX

PUSH

PUSH

PUSH

PUSH

B

PSW

B

H

D

SEEK

CALL

,JNC

DT005: POP

POP

POP

POP

SKOI0

DTOI0

H

D

B

PSW

STAX

STC

B

... IMP RSTOR

CALCULATE SECTOR SIZE

WHERE MMM=MTMFSK MASK

CCCCC=FDC COMMAND

WHERE R=82~:7

W=8237 WR BIT

NNNNNN=NO. OF BYTES IN COMMAND

WHERE MMM=MTMFSK MASK

CCCCC=NO. OF BYTES IN COMMAND

WHERE XX=DOWT CARE

NNNNNN= NO. OF BYTES IN COMMAND

;MT,MF,Sf<

RD BIT

;SAVE MT,MF,SK

;SAVE ADR(IOPB)

;SAVE PARAMETERS

;SAVE ADR(DATA)

; SEEK

;,JUMP IF OK

;ERRClR

;IN

SEEK

; RESTORE

;MT,MF,SK

;RETURN WITH CARRY=1

A-28

iSBC 208

Sample Drivers

LOC OBJ

OA41 210600

OA44 09

OA45 5E

OA46 210200

OA49 09

OA4A 7E

OA4B B7

OA4C C2550A

OA4F 21S000

OA52 C3600A

OA55 210001

OA58 30

OA59 CA600A

OA5C 29

OA50 C3580A

OA60 7B

OA61 54

OA62 50

OA63 30

OA64 CA6BOf~

OA67 19

OA6S C3630A

OA6B 2B

OA6C EB

OA60 F3

OA6E 030C

OA70 7B

OA71 0301

OA73 7A

OA74 0301

OA76 01

OA77 7B

OA78 0300

OA7A 7A

OA7B 0300

OA70 E1

OA7E 3ECO

OASO A4

OAS1 1F

OAS2 IF

OAS3 IF

OAS4 IF

OAS5 1640

OAS7 B2

OA88 030B

OASA AF

OASB 030A

OASO FB

OASE Cl

OA8F Fl

OA90 02

ISIS-II SOSO/SOS5 MACRO ASSEMBLER, V3.0 MODULE PAGE 15


802

803

804

805

806

807

808

809

810

778

779

7S0

7S1

7S2

783

7S4

785

786

787

788

789

790

791

792

793

794

795

796

797

798

799

800

801

811

812

813

814

815

816

817

818

819

820

821

822

823

824

770

771

772

773

774

775

776

777

OTOI0: LXI

OT015: OAO

MOV

LXI

OAO

MOV

ORA

JNZ

LXI

...IMP

OT020: LXI

OTO:30: OCR

. ...IZ

OAO

...IMP

H,6

B

E,M

H,2

B

A,M

A

OT020

H,80H

OT040

H,256

A

OT040

H

OT030

;AOR(NSEC)

;SAVE NSEC

;HL=ADR(N)

;A=N=(O TO 3)

;N=O?

;NO

;YES, SET sECTOR SIZE=128

;HL=BASE SECTOR SIZE

;OONE?

;YES, HL=SECTOR SIZE

;NO, OOUBLE THE VALUE

OT040: MOV

MOV

MOV

A,E

D,H

E,L

; MULTIPLY SECTOR SI ZE

OT042: OCR A

DAD

..JMP

DT045: DCX

; SET UP DMA

XCHG

DI

DT045

D

DT042

H

CONTROLLER

;RECALL NSEC

; SAVE

;SECTOR SIZE

BY NSEC

; DONE?

;YES

;NO, ADD ANOTHER SECTOR SIZE

;CHECK AGAIN

;HL=(SECTOR SIZE)

*

NSEC-l

;DE=8237 WORD COUNT


;PROGRAMMING 8237

;CLEAR F/L F/F OUT

MOV

OUT

MOV

OUT

POP

MOV

DCLFL

A,E

DMWCO

A,D

DMWCO o

A,E

;PROGRAM LSB OF COUNT

;PROGRAM MSB OF COUNT

;RESTORE ADR (DATA)

OUT

MOV

OUT

POP

MVI

ANA

RAR

RAR

RAR

RAR

MVI

ORA

OUT

XRA

OUT

EI

POP

POP

STAX

COMMAND FtlC

OMARO

A,D

DMARO

H

A,OCOH

H

O,OMAMD

D

DMOOE

A

OMKSR

B

PSW

B

;PROGRAM LSB OF ADDRESS

;PROGRAM MSB OF ADDRESS

;HL=PARAMETERS

;MASK FOR RD, WR BITS

; A=RD, WR BIT

; POSITION

; RD

WR

BIT

;DMA MODE WORD

; OR RO/WR BIT WITH MODE WORD

;SET MODE

;DMAC MASK VALUE

;ENABLE DMA TRANSFER ON CH.O

; RE-ENABLE INTERI::,{UPTS

;RESTORE ADR(IOPB)

; RESTORE

; MT, MF, 81<

A-29

Sample Drivers


LOC OBd

OA91 OA

OA92 FS

OA93 CS

OA94 F61F

OA96 AS

OA97 02

OA98 3E3F'

OA9A A4

OA9B SF

OA9C CD03:0B

OA9F DAA5iOA

OAA2 C29COA

OAAS C1

OAA6 D1

OAA7 7A

OAA8 02

OAA9 C31EOA


REGS: ALL

STK PRS: 7 + CONO

DTRN2: LDAX B

PUSH

PUSH

ORI

PSW

B lFH

L ANA

STAX

MVI

ANA

MOV

DTOSO: CALL

,JC

B

A.3FH

H

E.A

CMNDS

DT060

,...INZ

DT060: POP

DTOSO

B

POP

MOV

STAX

JMP

D

A.D

£I

RSTOR

MODULE PAGE 16

OAAC

OAAF

OAB2

OAB3

OAB4

OABS

OAB6

CD190A

CDC80A

2F

SF

OA

A3

C3C2'OA

OAB9 CD1S-0A

(IABC CDC:::OA

OABF SF

OACO OA

OACl B3 iSBC 208

847

848

849

850

851

852

853

CALL AUXRST

BC=ADR (CONTROL BYTE)

E=CONTROL BIT (0 ~O 3).REMAINING BITS (4 TO 7)

MUST =0

RETURN W/CARRY=O

854

855

856

857

S58

859

SbO

:361

S62

863

S64

865

REGS: F

STK PRS: 4

AUXRST: CALL

CALL

CMA

MOV

LDAX

ANA

... IMP

SAVER

SLECT

E.A

£I

E

EXRTN

;SAVE HEGISTEHS

;SELECT CONTROL LINE

; RESETS

; SELECTED

BIT

; RETURN

;*******************************************************

; AUXILIARY PORT SET-A-BIT SUBROUTINE

866

S67

8e.8

CALL AUXSET


E=CONTROL BIT (0 TO 3).REMAINING BITS (4 TO 7)

869

870

871 RETURN W/CARRY=O

872

873 REGS: F

MUST=O

874 STI< PRS: 4

875 AUXSET: CALL

876

877

CALL

MOV

878

879

LDAX

ORA

SAVER

SLECT

E.A

B

E

;SAVE REGISTERS

;SELECT CONTROL LINE

;SAVE MASK

;GET CONTROL BYTE

; SET SELECTED BIT

A-30

iSBC 208

Sample Drivers


LOC OB..J

OAC2 02

OAC3 D312

OAC5 C31EOA

OAC8 lC

OAC9 3E80

OACB 07

OACC ID

OACD C2CBOA

OADO C9

ClAD 1 CD190A

OAD4 7B

OAD5 E6FO

OAD7 5F

OAD8 OA

OAD9 E60F

OADB B3

OADC C3C20A

ClADF 3E80

OAEI C3E60A

OAE4 3E40

OAE6 F3

OAE7 05

OAE8 IF

OAE9 IF

OAEA IF

OAEB IF

OAEC lc.40

OAEE B2

OAEF D30B

MODULE PAGE 17


880 EXRTN:

881

882

883

884 SLECT:

:385

886 SLOI0:

887

888

889

STAX

OUT

.... IMP

INR

MVI

RLC

DCR

.... INZ

RET

B

AUXP

; UPDATE CONTROL BYTE

; SEND COMMAND

RSTOR ; RESTORE REGISTERS

E

A,80H

E

; 1 TO

; CORRECT UNIT?

SLOI0 INO

4

890 ;****************************************.~**************

891 ;AUXILIARY PORT ADDRESS BITS (14H TO 17H)

892

894

895


E=PAGE NO. IN HI NIBBLE (BITS 4 TO 7),

LO NIBBLE (BITS 0 TO 3) DON~T O~RE

896

897

898

899 ; REGS: F

RETURN W/CARRY=O

900 ;STI< PRS: 4

901 AUXADR: CALL

902

903

904

MOV

ANI

MOV

SAVER

A,E

OFOH

E,A

;SAVE REGISTERS

; CLEAR

; LO

905

906

907

908

LDAX

ANI

ORA

.... IMP

B

OFH

E

EXRTN

NIBBLE

;GET CONTROL BYTE

;MASI< PAGE BITS

;PUT PAGE INTO CONTROL BYTE

;RETURN

909 ;*******************************************************

910 LEVEL 1 ROUTINES

911

912

913

914

~15

926

USER CALLABLE THRU JUMP TABLE

USE ALL REGISTERS

916

917

918

DMA SET ROUTINE

BC=COUNT

DE=ADDRESS

CALL

919

920 REGS: AF,B

921 STK PRS: 0

DMARD OR DMAWR

922 DMARD:

923

924 DMAWR:

MVI

..JMP

MVI

925 DMAST: DI

A,RD

DMAST

A,WR

;TURN ON 8237 RD BIT

;TURN ON 8237 WR BIT


; PROGRAMM I NG THE E:237

927

928

929

PUSH

RAR

RAR

D ;SAVE ADDRESS

;POSITION

RD

930

931

932

9:33

';1::;:4

RAR

RAR

MVI

ORA

OUT

WR

BIT

D,DMAMD IDMA MODE WORD

D lOR RD/WR BIT WITH MODE WORD

DMODE ;SET MODE

A-31



LOC OB.J

OAFI 01

OAF2 79

OAF3 0301

OAF5 78

OAF6 0301

OAF8 7B

OAF9 0300

OAFB 7A

OAFC 0300

OAFE AF

OAFF D30A

OBOI FB

OB02 C9

0803 0810

0805 E61F

0807 CO

0808 C3210B

MODULE PAGE 18


951

952

953

954

955

956

957

958

959

960

961

962

963

935

936

937

938

939

940

941

942

943

944

945

946

947

948

949

950

POP

MOV

OUT

MOV

OUT

MOV

OUT

MOV

OUT

XRA

OUT

EI

RET

0

A.C

; RESTORE ADDRESS

DMWCO ; PROGRAM LSB OF COUNT

A.B

DMWCO ; PROGRAM MSB OF COUNT

A.E

DMARO ;PROqRAM LSB OF ADDRESS

A.D

DMARO ;PROGRAM MSB OF ADDRESS

A ;DMAC MASK VALUE

DMKSR ;ENABLE DMA TRANSFER

;RE-ENABLE INTERRUPTS

;*******************************************************

COMMAND PHASE ROUTINE

CALLING SEQUENCE

BC=ADR(IOPB)

E=# OF BYTES IN COMMAND

CALL

OR

CALL

OR

CALL

CMNDS

CMNDP

CMND

; COMMAND SERIAL OPERATION

; COMMAND PARALLEL OPERATION

;UNCHECKED COMMAND OUTPUT


BUSY RETURN. ZERO FLAG=O (NZ). CARRY=O (NC)

REGS BC. E PRESERVED FOR WAIT LOOPING

NORMAL RETURN. ZERO FLAG=1 (Z). CARRY=O (NC)

964

965

966

967

968

969

970

971

972

973

974

975

976

977

978

NOTE: THE 8272 FDC IS EITHER IN THE READ/WRITE MODE OR

THE SEEK MODE. AND THESE TWO MODES ARE MUTUALLY

EXCLUSIVE.

REGS: ALL

STK PRS: 4+CONO

COMMAND SERIAL OPERATIONS

I.E. COMMANDS THAT OPERATE IN THE READ/WRITE

MODE OF THE 8272 AND/OR COMMANDS THAT

E. G.

MUST CHECK FOR FDC BUSY AND FOR ANY FDD

SEEKING

READ DATA. REA[I DELETED DATA. WRITE

DATA. WRITE DELETED DATA. READ A TRACK.

SCAN EQUAL. SCAN LOW OR EQUAL. SCAN HIGH

979

980

981

982

983

984

985

986

987

988

989

CMNDS: IN

ANI

RNZ

... IMP

OR EQUAL. READ 10. FORMAT A TRACK. AND

SPECIFY

FDCST

IFH

CMND

;GET MAIN FDC STATUS

;FDC BUSY OR FDC IN SEEK MODE? eYES. RETURN W/ZERO FLAG=O. AND

; CARRY=O

;NO, START COMMAND OUTPUT

A-32

iSBC208

Sample Drivers

ISIS-II SOSOlSOS5 MACRO ASSEMBLER. V3.0

LaC 08J

080B DBI0

OBOD 6F

OBOE E610

OBI0 CO

0811 03

OB12 OA

OB13 OB

0814 E603

OB16 57

0817 f4

OBIS 3E80

081A 07

081B 15

081C C2IA08

OBIF AS

OB20 CO

0821 F3

0822 CD5BOB

0825 08

OB26 OA

0827 0311

OB29 03

082A ID

OB2B C2220B

082E FB

OB2F C9

MODULE PAGE 19


990 COMMAND PARALLEL OPERATIONS

991 I.E. COMMANDS THAT OPERATE IN THE SEEK MODE

992 OF THE 8272 ANDIOR COMMANDS THAT MUST

993

994

995 E.G.

CHECK FOR FDC BUSY AND FOR SPECIFIED

FDD SEEKING

SEEK. RECALIBRATE. SENSE DRIVE STATUS

996

997 CMNDP:

998

999

1000

IN

MOV

ANI

FDCST

L.A

10H

;GET MAIN F:DC STATUS

; SAVE FDC STATUS

;FDC BUSY? (I. E. IS FDC IN

; READ/WRITE MODE?)

1001

1002

1003

1008

1009

1010 CM01O:

1011

RNZ

DCR

JNZ

ANA

RNZ

B

B

B

03H

; YES.,

;

RETURN W/ZERO FLAG=O. AND

CARRY-O

;ADR (UNIT SELECT BYTE)

1004

1005

1006

1007

1012

1013

1014

1015

1016

INX

LDAX

DCX

ANI

MOV

INR

MVI

RLC

D.A

D

A.80H

;A-HD.US BYTE

; RESTORE POINTER

;A = US=O TO :3

;D=US

;D=1 TO 4

; SHIFT MASK TO NEXT HIGHER UNIT

D ; DONE?

CMOI0 ;NO. CONTINUE

L ; YES. IS FDD SEEKING?

;YES. RETURN W/ZERO FLAG=O.

; CARRY=O

;NO, START COMMAND OUTPUT

1017

1018 COMMANDS THAT DO NOT C~ECK FOR FDC BUSY OR ANY

AND

1019 FDD SEEKING

1020

1021

E.G.

1022 CMND:

1023

1024 CM020:

DI

1025

1026

1027

CALL

RC

LDAX

OUT

1028

1029

1030

1031

1032

1033

INX

DCR

. ...INZ

EI

RET

SENSE INTERRUPT STATUS

RDYC

B

FDCDT

B

E

CM020


; PROGRAMMING THE 8272

; IS FDC READY FOF1 COMMAND

;NO. ERROR. CARRY=1

;YES. A-BYTE FROM IOPB

;SEND BYTE TO FDC DATA PORT

;BUMP POINTER

; DONE?

;NO. CONTINUE

;YES. RE-ENABLE INTERRUPTS

;NORMAL RETURN, CARRY=O. AND

; ZERO FLAG=1

1034 ;***************************************************.***

1035 RESULT PHASE ROUTINE

1036

1037

1038

1039

CALLING SEQUENCE

CALL RSULT

1040

1041

1042

1043

104·4

NORMAL RETURN. CARRY=O

C=NO. OF BYTES FOUND

RESlLT BYTES STORED IN BUFFER


A-33

Sample Drivers

ISIS-II 8080/8085 MACRO ASSEMBLER. V3.0 MODULE PAGE 21

LOC OBJ

OB72 C5

OB73 7E

OB74 B7

OB75 CA800B

OB78 4F

OB79 CD50Ot8

OB7C 23

OB7D C3730B

OB80 Cl

OB81 C9

OB82 46444·320

OB86 4552~i22C

OB8A 20444~94F

OB8E 20484~920

OB92 494E2043

OB96 4D4E~~420

OB9A 153

OB9E 45

OB9F 00

OBAO OA

OBAl 00

OBA2 4644L~320

OBA6 4552~)22C

OBAA 2044L~94F

OBAE 204CL~F20

OBB2 494E2052

OBB6 5355 LK54

OBBA 2050L~841

OBBE 5345

OBCO 00

OBCl OA

OBC2 00

OBC3 4644'J320

OBC7 5345'~54B

OBCB 2F 41 ~5454

OBCF 4E20'~94E

OBD3 54

OBD4 00

OBD5 OA

OBD6 00

OBD7 4644.11-320

OBnB 492F'II-F20

OBnF 494E~54

OBE2 00

OBE3 OA

OBE4 00

OBE5 46444320

OBE9 5345454B

OBED 20455252

OBFl 00

OBF2 OA


1100

1101

1102

1103

1104

1105

1106

1107

1108

1109

1110

1111

1112

1113

1114

REGS: AF.HL

STK PRS: 2+CONO

MESSG: PUSH B

MSOI0: MOV

ORA

JZ

A,M

A

MS020

MOV

CALL

INX

JMP

MS020: POP

RET

C.A

CONO

H

MSOI0

B

MSGI0:

;SAVE BC

;END OF MESSAGE?

;YES

;NO, OUTPUT NEXT CHAR

;CONSOLE OUTPUT

; CONTINUE

;RESTORE BC

DB -'FDC ERR, 010 HI IN CMND PHASE-', ODH, OAH, 0

1115 MSG20:

1116 MSG30:

1117 MSG40:

1118 MSGSO:

DB -'FDC ERR, DIO LO IN RSULT

DB 'FDC 1/0 INT',O,OAH,O

DB 'FDC SEEK ERR"',O,OAH,O

PH~ISE-',O[lH,OAH,O

DB -'FDC SEEK/ATTN INT-', 0, OAH, 0 iSBC208

A-34

iSBC 208

Sample Drivers

ISIS-II 8080/8085 MACRO ASSEMBL.ER, V3.0

LOC OB..J

OB30 2A4E08

OB33 OEOO

OB35 3A5308

OB38 3D

OB39 C2380B

OB3C DBI0

OB3E 47

OB3F £610

OB41 C8

OB42 78

OB43 07

OB44 023COB

OB47 07

OB48 DA530B

OB48 21A20B

OB4E C0720B

0851 37

OB52 C9

0853 OBll

OB55 77

OB56 23

OB57 OC

0858 (::3350B

OB5B ~3A5308

085E 3D

OB5F C25EOB

OB62 OBI0

OB64 07

OB65 02620B

OB68 07

OB69 DO

OB6A 21820B

OB60 C0720B

OB70 '37

OB71 C9

MODULE PAGE 20


1045

1046

1047

1048

1049

1050

1051

1052

1053

1054

1055

1056

1057

1058

1059

1060

1061

REGS: AF,BC,HL

STt< PRS: 3+CONO

RSULl: LHLO

MVI

RSOI0: LOA

RS015: OCR

. ...INZ

RS017: IN

MOV

ANI

RZ

ARSBF

C,O

DELAY

A

RS015

FOCST

B,A

10H

1062

1063

1064

1065

1066 RS020:

1067

1068

1069

1070

MOV

RLC

. .JNC

RLC

. ...IC

LXI

CALL

STC

RET

IN

MOV

INX

INR

JMP

A,B

RS017

RS020

H,MSG20

MESSG

FDCDT

M,A

H

C

RSOI0

;HL=AOR (RESULT BUFFER)

;INITIALIZE BYTE COUNT

;ALLOW 8272 TIME

; TO CHANGE

FDC STATUS

; A=FDC STATU!::;

; SAVE FDC :;:;TATU:;:

;MORE RESULT-BYTES? STILL BUSY?

;NO, NORMAL RETURN

;NOTE: CARRY=O FROM "ANI"

;YES, RESTORE STATUS

;RQM (READY) HIGH?

;NO, t<EEP WAITING

;YES, DIO=OUTPUT?

;YES

;PRINT OUT "010 LO IN RESULT #

; PHASE" ERROR MESSAGE

;SET CARRY TO

#

; INDICATE ERROl':

;GET RESULT BYTE FROM FLOPPY

;STORE BYTE IN MEMORY

;BUMP POINTER

;BUMP COUNT

;GO BACt<

&

CHECK FOR MORE BYTES

1071

;*******************************************************

1072 READY FOR COMMAND SUBROUTINE

107'3

1084

1085

1086

1087

1088

1089

1090

1091

1092

1093

1094

1074 CALLING SEQUENCE

1075

1076

CALL RDYC

1077

1078

1079

NORMAL RETURN, CARRY=O

ERROR RETURN, CARRY=l

1080

1081

1082

1083 iREGS: AF, HL

STK PRS: 3+CONO

RDYC:

RYOIO:

RY020:

LDA

DCR

",INZ

IN

RLC

,-INC

RLC

RNC

LXI

CALL

STC

RET

DELAY

A

RYOIO

FDCST

RY020

H,MSGI0

MESSG

;ALLOW 8272 TIME

; TO CHANGE

FDC STATUS

; GET FDC STATlI!::;

;IS RQM (READY) HIGH?

;NO, WAIT UNTIL IT IS

;YES, DIO=INPUT?

;YES, FDC READY FOR COMMAND

;NO, ERROR

;"DIO HIGH"

;SET CARRY TO

; INDICATE ERROF(

1095

1096

1097

1098

1099

#

#

MESSAGE SUBROUTINE

(FROM THIS POINT TO THE END OF THE PROGRAM CAN

BE ELIMINATED WHEN ERROR MESSAGES ARE NO LONGER

REOUIRED)

HL=ADR (MESSAGE) ,NOTE: LAST BYTE MUST EQUAL ZEF(O

A-35


ISIS-II 8080/8085 MACRO ASSEMBLER. V3.0 MODULE

LOC OB..J LINE SOURCE STATEMENT

OBF3 00

OBF4 4644~~320 1119 MSG60: DB 'FDC I/O ERR-'. 0. OAH.

(J

OBF8 492F4F20

OBFC 4552~52

OBFF 00

OCOO OA

OCOl 00

1120 END

PAGE 22

PUBLIC SYMBOLS

AUXADR A OADI

DMARI A 0002

Dl'tRQ A 0009

FDCDT A 0011

RDID A 0965

SEEK A 09BA

WRITE A 093C

AUXP A 0012

DMAR2 A 0004

DMSR A 0008

FDCST A 0010

RDTRK A 094E

SEGHI A 0015

WRTDD A 0945

AUXRST A OAAC

DMAR3 A 0006

DMTR A OOOE

FRMTK A 096E

READ A 092A

SEGLO A 0014

AUXSET A OAB9

DMASK A OOOF

DMWCO A 0001

INIT A 0918

RECAL A 09A3

SFTRS A 0013

BASE A 0000

DMCLR A OOOD

DMWCI A 0003

INT20 A 08DI

SCNEQ A 0988

SNSDS A 09EA

DCLFL A OOOC

DMKSR A OOOA

DMWC2 A 0005

PRSLT A 08EI

SCNHE A 099A

SNSIS A OA04

DMARO A 0000

DMODE A OOOB

DMWC3 A 0007

A 0933 RDDD

SCNLE A 0991

SPCFY A 09D3

EXTERNAL SY~1BOLS

USER SYMBOLS

ARSBF A 084E

CI1NDP A OBOB

DI1Af1D A 0040

DrtAST A OAE6

DMTR A OOOE

DT015 A OA44

DT060 A OAA5

FRI1TK A 096E

IT008 A 0895

I1S050 A OBE5

PR030 A 0913

READ A 092A

RS017 A OB3C

SAVER A OAI9

SEOLO A 0014

SNSIC A OA18

WR A 0040

AUXADR A OADI

CMNDS A OB03

DMARO A 0000

DI1AWR A OAE4

DMWCO A 0001

DT020 A OA55

DTRNI A OA2D

ICCP A OODA

ITOIO A 08Bl

MSG60 A OBF4

PRSLT A 08EI

RECAL A 09A3

RS020 A OB53

SCNEQ A 0988

SFTRS A 0013

SNSIS A OA04

WRITE A 093C

AUXP ~I 0012

CMOIO ~I OBIA

DI1ARI ~I 0002

DMCLR ~I 0000

DMWCI ~I 0003

DT030 A OA58

DTRN2 A OA91

INIO A 091E

ME SSG A OB72

MSOIO A OB73

RD A 0080

REGF A 7F30

RSTC A OA27

SCNHE A 099A

SKOIO ~\ 09C6

SPCIO

1\

09DE

WRTDD ~\ 0945

AUXRST A OAAC

CM020 A OB22

DMAR2 A 0004

DMKSR A OOOA

DMWC2 A 0005

DT040 A OA60

EOIC A 0020

INIT A 0918

MSGIO A OB82

MS020 A 0880

RDDD A 0933

REOIO A 09AE

RSTOR A OAIE

SCNLE A 0991

SK020 A 09CB

SPCFY A 0903

AUXSET A OAB9

CONO A 0850

DMAR3 A 0006

DMODE A OOOB

DMWC3 A 0007

DT042 A OA63

EXRTN A OAC2

INTIO A 0855

MSG20 A OBA2

PR005 A 08E6

RDID A 0965

RS8DH A OA29

RSULT A OB30

SDOIO A 09F5

SLECT A OAC8

US TACK A 7F80

BASE A 0000

DCLFL A OOOC

DMARD A OADF

DMRQ A 0009

DT005 A OA38

DT045 A OAbB

FDCDT A 0011

INT20 A 08DI

MS030 A OBC3

PROIO A 0904

RDTRK A 094E

RSOIO A 0835

RYOIO A OB5E

SEEX A 09BA

SLOIO A (IACB

VER A 0010

CMND A OB21

DELAY A 0853

DMASK A OOOF

DMSR A 0008

DTOIO A OA41

DT050 A OA9C

FDCST A 0010

IT002 A 0865

MSG40 A OBD7

PR020 A 0908

RDYC A OB58

RSOl5 A OB38

RY020 A OB62

SEGHI A 0015

SNSDS A 09EA

VERSIO A 0854

ASSEMBLY COMPLETE. NO ERRORS

A-36

APPENDIX B iSBX™ MUL TIMODULE™

BOARD INTERFACE


The iSBC 208 Controller is designed to accept a single- or double-wide iSBX Multimodule board. The iSBX Multimodule board installed on the controller is accessed by the host processor directly through the

Multibus interface; the controller dedicates two of its

DMA channels (DMAC channels 2 and 3) to the iSBX board to provide direct memory access between the iSBX board and system memory. The physical interface between the parent iSBC 208 Controller and the installed iSBX Multimodule board is provided through a 36-pin connector. For specific information on an individual iSBX board, refer to the corresponding iSBX Multimodule board hardware reference manual.

8-2. INSTALLATION

Physical installation of the selected iSBX

Multimodule board on the controller is described in the corresponding iSBX Multimodule board hardware reference manual. Table B-1 defines the iSBX

Multimodule board signals on the controller's 13 connector.

8-3. CONFIGURATION

As noted in table B-1, the iSBC 208 Controller includes a number of jumpers that must be installed to enable the correspondiing signals on the controller's 13 connector. Note that none of the jumpers are installed at the factory. The following subsections define the jumper functions for the Multimodule board DMA channels and system interrupts.

B-4. DMA Channels

Channel 2 of the DMAC is reserved exclusively for the iSBX Multimodule board; the channel 2 DREQ

(DMA Request) and DACK (DMA Acknowledge) signals are permanently routed to the 13 connector, and no jumpers are required. If an end-of-process

(EOP) signal is required by the iSBX Multimodule board to indicate when the channel 2 DMA transfer is complete (i.e., DMAC channel 2 word count register decrements to zero), a jumper must be installed between jumper post E15 (OEOP) and either jumper post E16 (OPTO signal line on 13-30) or jumper post E14 (OPT! signal line on 13-28).

Channel 3 of the DMAC is available to the iSBX

Multimodule board; the channel 3 DACK and DREQ signals must be jumpered on the controller to route

Table B-1. 13 Connector Pin Assignments

Pin Signal Function

13

14

15

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

+12V

-12V

Gnd

+5V

MRESET

MCLK

MA2

MPSTI

MA1

Reserved

MAO

MINTR1'

10WRTI

MINTRO'

10RDI

MWAITI

Gnd

+5V

+12 volts

-12 volts

Logic Ground

+5 volts

Multimodule Reset

Multimodule Glock

Multimodule Address Bit 2

Multimodule Present



Multimodule Interrupt 1

I/O Write

Multimodule Interrupt 0

I/O Read

Multimodule Wait

Logic Ground

+5 volts

'Signal requires jumper connection on controller board.

Pin

25

26

27

28

29

30

31

32

33

34

35

36

19

20

21

22

23

24

Signal

MD7

MCS11

MD6

MCSOI

MD5

Reserved

MD4

TDMA'

MD3

OPT1'

MD2

OPTO'

MD1

MDACKI

MOO

MDRQT

Gnd

+5V

Function

Multimodule Data Bit 7

Multimodule Chip Select 1


Multimodule Chip Select 0



Terminate DMA


Optional Signal 1


Optional Signal 0


Multimodule DMA Ack.


Multimodule DMA Request

Logic Ground

+5volts

B-1

iSBX Multimodule Board Interface iSBC 208 the signals to the 13 connector. The DACK3 signal

(ODACK) appears on jumper post E13, and the

DREQ3 signal (ODREQ) appears on jumper post

E12. These two signals must be connected to jumper posts El6 (OPTO signal line on 13-30) and E14

(OPTl signal line on 13-2S).

NOTE

Since DMAC channel 3 requires the use of both the OPTO and OPTl optional signal lines, the EOP signal from the DMAC to the iSBX Multimodule board cannot be supported.

If the iSBX Multimodule board includes logic to externally terminate a DMA transfer, a jumper must be installed between jumper post El (TDMA signal on 13-26) to jumper post E3 (external EOP input to the DMAC).

B-5. INTERRUPTS

There are two interrupt signals available on iSBX

Multimodule board interface connector 13, MINTRO on 13-14 and MINTRI on 13-12. These signals are routed to the controller's interrupt jumper matrix

(jumper posts ESO and ES1, respectively) and must be connected to the desired Multibus interface interrupt level according to the following table.

Interrupt

Signal

MINTRO

Jumper

Post

E80

Jumper

Post

E89

E88

E87

E86

Interrupt

Level

INTOI

INT11

INT21

INT31

MINTR1 E81

E85

E84

E83

E82

INT41

INT51

INT61

INT71

Note that the interrupt level selected must not have been previously assigned to another bus. master .

I/O ports reference the same I/O base address as the controller and are numbered port addresses 20 through 2F (hexadecimal). To address the additional

1/0 ports, a 6-bit I/O port address is required (the controller only requires a 5-bit port address); the I/O base address must be located on a 64-port boundary, and I/O base address bit 5 is irrelevant.

B-7. PORT ASSIGNMENTS

The 16 1/0 ports assigned to the iSBX Multimodule board are divided into two groups of eight ports by the two Multimodule chip select signals (MCSOI and

MCSlI). The individual port addressed within the group is determined by Multimodule address bits 0 through 2 (MAO-MA2). Table B-2 defines the iSBX

Multimodule port assignments; refer to the corresponding iSBX Multimodule board hardware reference manual for the specific I/O port functions.

Table B-2.

110

Port Assignments iSBX Board Signal Levels

1/0 Port Address

(Hexadecimal) MCS11 MCSOI MA2 MA1 MAO

20

21

22

23

24

25

26

27

1 0

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

28

29

2A

2B

2C

2D

2E

2F

0 1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

B-6.


When an iSBX Multimodule board is installed on the controller, host processor communication is accomplished through a set of 16 I/O ports. These 16

B-8. PROGRAMMING THE DMAC

Programming the DMAC is described in sections 3-3 through 3-12 of this manual.

B-2

APPENDIX C

DRIVE INTERFACES

C1. INTRODUCTION

The following tables (tables C-I and C-2) define specific drive interfaces for a number of standardand mini-sized drives that are compatible with the iSBC 208 controller. In the tables, a drive interface pin number appearing in an individual drive column indicates that the signal function and pin assignment on the controller interface connector are the same on the drive interface connector.

C-2. USING THE TABLES

As an example of how the tables are used, assume that four Micropolis 1015 mini drives are to be interfaced to the controller. Referring to the Micropolis

1015 column in table C-2, note that a (common)

HEAD LOAD signal is required on pin 2, a MOTOR

ON signal is required on pin 16, the drive select signal for the fourth drive is required on pin 34, and that all of the remaining interface signals are directly pin-topin compatible.

Referring to the controller schematic in Chapter 5, to configure the controller to provide a HEAD LOAD signal on pin 2 of connector J I, the jumper between posts E31 and E32 (see sh~:et 7 of the schematic) is removed, and a jumper is installed between posts E32

(the source of the HEAD LOAD signal) and EIO (pin

2 of connector 11); see sheet 3 of the schematic.

Again referrring to sheet 3 of the schematic, to provide a MOTOR ON signal on pin 16, a jumper is installed between the selected auxiliary port bit (see section 2-14) on jumper post Ell, E9, E7, or E2, and jumper post E6 (pin 16 of connector 11). To provide a fourth drive select signal, the factory-installed jumper between posts E21 and E22 (TWO SIDED/) is removed, and a jumper is installed between post

E20 (the controller's DRIVE SELECT 3/ signal on sheet 7) and post E21 (pin 34 of connector 11).

C-l/C-2

iSBC208

I

:

Controller Interface Connector J2

Signal Name Pin

""LOW CURRENT I

"HEAD LOAD 21

"HEAD LOAD 31

"User Defined

6

8

2

4 i

"·TWOSIDEDI

"User Defined

SIDE SELECT I

"User Defined

""HEAD LOAD 01

INDEXI

""READYI

"HEAD LOAD 11

DRIVE SELECT 01

DRIVE SELECT I

DRIVE SELECT 21

DRIVE SELECT 31

DIRECTiON I

STEP I

WRITE DATAl

WRITEGATEI

TRACK 01

WRITE PROTECT I

READ DATAl 46

"FAULTI

"FAULTRESETI

42

44

46

48

30

32

34

36

38

40

18

20

22

24

26

28

10

12

14

16

50

Table

Col.

Standard 8-inch Drive Interface Pin Assignments

Shugart

SA800/8S0

Caleomp

143M

CDC

9406-3

Memorex

550/552

MFESeries

5001700 fersel

70

Persel

288

Pertee

650

Pertee

5x4

21

Unassigned

Unassigned

Unassigned

101

DISK

CHANGE

141

IN USE

18

20

22

SECTOR

26

28

30

32

34

42

44

46

36

38

40

SEPARATED

DATA

SEPARATED

CLOCK

HEAD

LOAD 2

HEAD

LOAD 3

HEAD

LOAD 4

TRK43

Unassigned Unassigned 2

Unassigned Unassigned Unassigned

Unassigned Unassigned POWER

SAVE

Unassigned Unassigned Unassigned

MOTOR ON

Unassigned

Unassigned

Unassigned

Unassigned

Unassigned

Unassigned Unassigned

10

DISK

CHANGE

HEAD

LOAD1

IN USE

10

DISK

CHANGE

14

102

DISK

CHANGE

142

103

DISK

CHANGE

143

SEEK

COMPLETE

RItSTORE

10

DISK

CHANGE

14

IN USE IN USE IN USE IN USE

18

20

22

SECTOR

34

36

38

26

28

30

32

40

42

44

46

SEPARATED

DATA

SEPARATED

CLOCK

18 18 18 18 18

20

22

20

22

20

22

20

22

20

22

SECTOR SECTOR SECTOR SECTOR SECTOR

26 26 26 26 26

28 28 28 28 28

30 30 30 30 30

32

34

32

34

32

34

32

34

32

34

36 36 36 36 36

38 38 38 38 38

40 40 40 40 40

42 42 42 42 42

44 44 44 44 44

46 46 46 46 46

SEPARATED SEPARATED SEPARATED SE~RATED SEPARATED

DATA DATA DATA ATA DATA

SEPARATED SEPARATED SEPARATED SEaARATED

CLOCK CLOCK CLOCK LOCK

SEPARATED

CLOCK

2

Unassigned

Unassigned

WRITE

BUSY

10

2

Unassigned

Unassigned

Unassigned

Unassigned

DISK

CHANGE

14

Unassigned

Unassigned

BUSY

CONTROL

Unassigned

18

20

22

SECTOR

26

18

20

22

SECTOR

28

26

28

30

32

30

32

34

36

36

34

36

38

40

42

44

40

42

44

46 46

SEPARATED SEPARATED

DATA DATA

SEPARATED SEPARATED

CLOCK CLOCK

Qume

Data Trak8

Remex

2000/4000

Siemens

FDD200-8

FDD 100-8

Unassigned

Unassigned

Unassigned

Unassigned

10

DISK

CHANGE

14

IN USE

2

Unassigned

Unassigned

Unassigned

10 4

DISK

CHANGE

144

IN USE

18

20

22

Unassigned

26

28

30

32

~

36

38

40

18

20

22

SECTOR

26

28

30

32

34

36

38

40

42

44

46

42

44

46

Unassigned SEPARATED

DATA

Unassigned SEPARATED

CLOCK

2

Unassigned

Unassigned

Unassigned

ILLEGAL5

PACK

Unassigned

145 iN USE

18

20

~2

SECTOR

26

28

30

40

42

44

32

34

36

38

46

SEPARATED

DATA

SEPARATED

CLOCK

"Requires jumper on controller

"" ' Jumper is installed on controller

1850 Only 25520niy 3700 Only 44000 Only

Drive Interfaces

C-3/C-4

iSBC208

Controller Interface Connector J1

Signal Name Pin

*UserDefined

*UserDefined

**READYI

INDEXI

DRIVE SELECT 01

DRIVE SELECT 11

DRIVE SELECT 21

*User Defined

DIRECTION I

STEPI

WRITE DATAl

WRITE ENABLEI

TRACK 0

WRITE PROTECT I

READ DATAl

SIDE SELECT I

**TWO SIDEDI

6

20

22

24

26

28

30

32

34

8

10

12

14

16

18

2

4

Shugart

SA400/450

Unassigned

IN USE1

Unassigned

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

321

Unassigned

*Requires jumper on controller

**Jumper is installed on controller

1450 Only

Shugart

SA410/460

Unassgined

IN USE

DRIVE

SELECT 4

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

32 2

DOOR

OPEN

2460 Only

Table C-2. Mini Drive Interface Pin Assignments

BASF

6106/6108

CDC

9409

Micr:POIiS

1 15

MPI

51/52

HEAD

LOAD

Unassigned

6

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

323

IN USE

Unassigned

Unassigned

DRIVE

SELECT 4

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

32

Unassigned

H~AD

L AD

Unassigned

6

8

10

12

14

MOTqlRON

28

30

32

18

20

22

:14

26

°1VE

SEL CT4

Unassigned

IN USE

DRIVE

SELECT 4

8

10

12

14

MOTOR ON.

18

20

22

24

26

28

30

32

Unassigned

36108 Only

Pertee

FD200

Unassigned

Unassigned

DRIVE

SELECT 3

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

Unassigned

Unassigned

Pertec

FD250

Unassigned

BUSY

CONTROL

DRIVE

SELECT 3

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

32

Unassigned

Siemens

FDD200-5N

FDD100-5B

Unassigned

IN USE4

DRIVE

SELECT 3

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

3~

Unassigned

4200-5N Only

Tandon

TM100

Unassigned

Unassigned

DRIVE

SELECT 3

8

10

12

14

MOTOR ON

18

20

22

24

26

28

30

32

Unassigned

Drive IntetfKCS

C-S/C-6

143078-001

iSBC™ 208 FILEXIBLE DISK DRI"E

CO'NTROLLER

Hj~RDWARE

REFERIENCE MANUAL

6[fu[1

PREFACE

CONTENTS

CHAPTER 1

GENERAL INFORMATION

PREPARATION FOR USE

CHAPTER 3

PROGRAMMING INFORMATION

PRINCIPLES OF OPERATION

CHAPTER 5

SERVICE INFORMATION

SAMPLE DRIVERS

CONTENTS (Cont'd.)

APPENDIXB iSBX MUL TIMODULE BOARD

INTERFACE

APPENDIXC

DRIVE INTERFACES

TABLES

ILLUSTRATIONS

3-5

CHAPTER

GENERAL INFORMATION

1-1. INTRODUCTION

1·2. SPECIFICATIONS

CHAPTER 2

PREPARATION FOR USE

INTRODUCTION

UNPACKING AND INSPECTION

INSTALLATION

CONSIDERATIONS

BUS INTERFACE

}

}

}

---t

---------------""'x:

l---tXCW~

*' ------

1-------

.x."-------

r-''"1

I

Table 2-3. iSBC 208 Board DC Characteristics

·6

2-10. BOARD LOCATION

CONSIDERATIONS

2-11. CONTROLLER BOARD

CONFIGURATION

Table 2-6. Drive Configuration Jumper Links (Cont'd.)

2-15. DRIVE INTERFACING

Table 2-10. Interface Connector Signal Functions

2-19. DRIVE CABLING

DRIVE MODIFICATIONS

CHAPTER 3

PROGRAMMING INFORMATION

3-1. INTRODUCTION

PORT COMMANDS

I

I

DISKETTE ORGANIZATION

fL

Table 3-2. Track Format

Table 3-2. Track Format (Cont'd.)

Table

Recording Capacities

3-20. FDC COMMANDS

Table

FOC Commands

Table 3-5. Result Phase Status Registers (Cont'd.)

bl

R esu t Phase

Table 3-6. Command Mnemonics

Programming Information

Table 3-6. Command Mnemonics (Cont'd.)

Table