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FPD-Link Evaluation Kit User’s Manual
FPD-Link Evaluation Kit
User’s Manual
NSID FLINK3V8BT-85
Rev 3.0
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 1 of 25
FPD-Link Evaluation Kit User’s Manual
Table of Contents
INTRODUCTION .............................................................................................................. 3
CONTENTS OF EVALUATION KIT................................................................................. 4
APPLICATIONS ............................................................................................................... 4
FEATURES AND EXPLANATIONS ..................................................................................
T
RANSMITTER
.................................................................................................................. 7
R
ECEIVER
..................................................................................................................... 12
HOW TO HOOK UP THE DEMO BOARDS (OVERVIEW) ............................................. 6
TRANSMITTER BOARD .................................................................................................. 7
S
ELECTABLE
J
UMPER
S
ETTINGS FOR THE
T
X
B
OARD
......................................................... 8
LVDS M
APPING BY
IDC C
ONNECTOR
............................................................................... 9
T
X
O
PTIONAL
: P
ARALLEL
T
ERMINATION FOR
T
X
IN .......................................................... 10
BOM (B
ILL OF
M
ATERIALS
) ............................................................................................ 11
RECEIVER BOARD ....................................................................................................... 12
S
ELECTABLE
J
UMPER
S
ETTINGS FOR THE
R
X
B
OARD
....................................................... 13
LVDS M
APPING BY
IDC C
ONNECTOR
............................................................................. 14
R
X
O
PTIONAL
: S
ERIES
T
ERMINATION FOR
R
X
O
UT
.......................................................... 15
BOM (B
ILL OF
M
ATERIALS
) ............................................................................................ 16
TYPICAL CONNECTION / TEST EQUIPMENT ............................................................ 17
T
YPICAL
W
AVESHAPES
.................................................................................................. 19
TROUBLESHOOTING ................................................................................................... 21
ADDITIONAL INFORMATION ....................................................................................... 22
A
PPLICATION
N
OTES
...................................................................................................... 22
APPENDIX...................................................................................................................... 23
T
RANSMITTER AND
R
ECEIVER
S
CHEMATICS
..................................................................... 24
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 2 of 25
FPD-Link Evaluation Kit User’s Manual
Introduction:
National Semiconductor - Interface Products Group FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the DS90C385A/DS90CF386 chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.
The Transmitter board accepts LVTTL/LVCMOS RGB signals from the graphics controller along with the clock signal. The LVDS Transmitter converts the
LVTTL/LVCMOS parallel lines into four serialized LVDS data pairs plus a LVDS clock. The serial data streams toggle at 3.5 times the clock rate.
The Receiver board accepts the LVDS serialized data streams plus clock and converts the data back into parallel LVTTL/LVCMOS RGB signals and clock for the panel timing controller.
The user needs to provide the proper RGB inputs and clock to the Transmitter and also provide a proper interface from the Receiver output to the panel timing controller or test equipment. A cable conversion board or harness scramble may be necessary depending on type of cable/connector interface used. A power down feature is also provided that reduces current draw when the link is not required.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 3 of 25
FPD-Link Evaluation Kit User’s Manual
Contents of the Evaluation Kit:
1) One Transmitter board with the DS90C385AMTD - 28 bit Transmitter
2) One Receiver board with the DS90CF386MTD - 28 bit Receiver
3) One 20-pin IDC Flat Ribbon Cable
4) One 60-pin IDC Flat Ribbon Cable
5) Evaluation Kit Documentation (this manual)
6) DS90C385A/DS90CF386 Datasheet
7) LVDS Owner’s Manual (2nd Edition)
FPD-Link Typical Application:
DATA (LVDS)
HOST GRAPHICS
CONTROLLER
LVCMOS/
LVTTL
LVCMOS/
LVTTL
LCD PANEL
CONTROLLER
CLOCK (LVDS)
FPSHIFT OUT (TxCLK IN) FPSHIFT OUT (RxCLK OUT)
DS90C385A DS90CF386
FPD-Link Application
LVCMOS/LVTTL
DS90C385A
28
FPD
Link
Tx
LVDS
5 Pairs
Cable
LVCMOS/LVTTL
DS90CF386
FPD
Link
Rx
28
Column Drivers
TFT-LCD
Display
CLK
Notebook Computer
Motherboard
GND
Notebook Computer Display
Notebook
Hinge
Typical FPD-Link Application (24-bit Color)
The diagrams above illustrate the use of the Chipset (Tx/Rx) in a Host to LCD Panel
Interface.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 4 of 25
FPD-Link Evaluation Kit User’s Manual
Chipsets support up to 18-bit or 24-bit AM-TFT LCD Panels for any VGA (640X480),
SVGA (800X600), XGA (1024X768), and Single/Dual Pixel SXGA (1280X1024) resolutions.
Because of the non-periodic nature of STN-DD SHFCLK, the Chipset may not work with all D-STN panels. The PLL CLK input of the Transmitter requires a free running periodic SHFCLK. Most Graphics Controller can provide a separate pin with a free running clock. In this case the STN-DD SHFCLK can be sent as Data while the free running clock can be used as SHFCLK for the PLL ref CLK. For example, C&T's
65550's WEC (Pin 102) can be programmed to provide a free running clock using the BMP (Bios Modification Program). Please refer to STN Application using (AN-
1056) for more information on STN support.
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board for more detailed information.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 5 of 25
FPD-Link Evaluation Kit User’s Manual
How to set up the Evaluation Kit:
The PCB routing for the Tx input pins (TxIN) have been laid out to accept incoming data from a 60-pin IDC connector. The TxOUT/RxIN interface uses a 20-pin IDC connector through a IDC ribbon cable. Please follow these steps to set up the evaluation kit for bench testing and performance measurements:
1) Connect one end of the 20-pin IDC cable to the transmitter board and the other end to the receiver board. Longer lengths can be used.
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be scrambled in the IDC cable in order to be compatible with this demo kit.
2) Jumpers have been configured at the factory, they should not require any changes for operation of the chipset. See text on Jumper settings for more details.
3) From the Graphics card, connect a flat (ribbon) cable to the transmitter board and connect the another flat cable from the receiver board to the panel (Note: Refer to AN-1127 for suggested mapping schemes). Note that pin 1 on the connector should be connected to pin 1 of the cable. A scramble cable may be required.
4) Power for the Tx and Rx boards must be supplied externally through TP1 (Vcc).
Grounds for both boards are connected through TP2 (GND) (see section below).
Power Connection:
The Transmitter and Receiver boards must be powered by supplying power externally through TP1 (Vcc) and TP2 (GND) on EACH board. The maximum voltage that should ever be applied to the FPD-Link Transmitter (385A) or Receiver
(386) Vcc terminal is +4V MAXIMUM.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 6 of 25
FPD-Link Evaluation Kit User’s Manual
FPD-Link Transmitter Board Description:
J1 (60 position) accepts 28 bit LVTTL/LVCMOS data along with the clock.
The FPD-Link Transmitter board is powered externally. For the transmitter to be operational, the Power Down pin must be set HIGH with a jumper. Rising or falling edge reference clock is selected by JP1 tied to Vcc (rising) or GND (falling).
The 20-pin IDC connector (J2) provides the interface for LVDS signals for the
Receiver board.
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be scrambled in the IDC cable in order to be compatible with this demo kit.
60-pin IDC Connector
1 2
GND
TXIN0
GND
TXIN1
GND
TXIN2
GND
TXIN3
GND
TXIN4
GND
TXIN5
GND
TXIN6
GND
TXIN7
GND
TXIN8
GND
TXIN9
GND
TXIN10
GND
TXIN11
GND
TXIN12
GND
TXIN13
GND
TXIN14
GND
TXIN15
GND
TXIN16
GND
TXIN17
GND
TXIN18
GND
TXIN19
GND
TXIN20
GND
TXIN21
GND
TXIN22
GND
TXIN23
GND
TXIN24
GND
TXIN25
GND
TXIN26
GND
TXIN27
GND
TXCLKIN
GND GND
59 60
J1
Vcc and Gnd MUST be applied externally here
R_FB /PD
TxOUT LVDS signals
20-pin IDC connector
1 2
GND
OUT0-
OUT0+
GND
GND
OUT1-
OUT1+
GND
GND
OUT2-
OUT2+
GND
GND
CLK+
CLK-
GND
GND
OUT3-
OUT3+
GND
19 20
J2
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be scrambled in the IDC cable in order to be compatible with this demo kit.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 7 of 25
FPD-Link Evaluation Kit User’s Manual
Jumper Settings for the Tx Board
Jumper Purpose
R_FB Rising or Falling
Settings
= Rising
Strobe
Vcc GND
= Falling
Vcc GND
Default setting is JP1 set LOW (to GND), falling edge strobe.
/PD PowerDown
(JP2)
Vcc GND Vcc GND
(ON: Tx is operational; OFF: Tx powers down)
Default setting is JP2 set HIGH (to Vcc), operational mode.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 8 of 25
FPD-Link Evaluation Kit User’s Manual
Tx LVDS Mapping by IDC Connector
The following two figures illustrate how the Tx inputs are mapped to the IDC connector (J1) (Note – labels are also printed on the demo boards). The 20-pin IDC
(J2) connector pinout is also shown.
(Transmitter Board)
60-pin IDC Connector TxOUT LVDS signals
20-pin IDC connector
Pin 1
GND
TXIN0
2
GND
TXIN1
GND
TXIN2
GND
TXIN3
GND
TXIN4
GND
TXIN5
GND
TXIN6
GND
TXIN7
GND
TXIN8
GND
TXIN9
GND
TXIN10
GND
TXIN11
TXOUT0
TXOUT0
TXOUT1
Pin 1
19
GND
OUT0-
OUT0+
GND
GND
OUT1-
OUT1+
GND
GND
OUT2-
OUT2+
GND
GND
CLK+
CLK-
GND
GND
OUT3-
OUT3+
GND
J2
2
20
GND
TXIN12
GND
TXIN13
GND
TXIN14
GND
TXIN15
GND
TXIN16
GND
TXIN17
GND
TXIN18
TXOUT1
TXOUT1
TXOUT3
GND
TXIN19
GND
TXIN20
GND
TXIN21
GND
TXIN22
TXOUT2
59
GND
TXIN23
GND
TXIN24
GND
TXIN25
GND
TXIN26
GND
TXIN27
GND
TXCLKIN
GND GND
60
TXOUT2
J1
TXCLKOUT
TXOUT3
Previous Cycle Next Cycle
TXIN23 TXIN17 TXIN16 TXIN11 TXIN10 TXIN5 TXIN27
TXOUT2 TXIN26 TXIN25 TXIN24 TXIN22 TXIN21 TXIN20 TXIN19
TXOUT1
TXOUT0
TXIN18 TXIN15 TXIN14 TXIN13 TXIN12 TXIN9 TXIN8
TXIN7 TXIN6 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0
Parallel LVTTL/LVCMOS Data Inputs Mapped to LVDS Outputs
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 9 of 25
FPD-Link Evaluation Kit User’s Manual
Tx Board Options: 50 Ohm Termination for TxIN
On the Tx demo board, the 29 inputs have an option for 50 Ohm terminations.
There are 0402 pads for this purpose. One side is connected to the signal line and the other side is tied to ground. These pads are unpopulated from the factory but are provided if the user needs to install a 50 Ohm termination. R1 TO R28 are associated with the Tx data input lines. R29 is associated with CLKIN. Some test equipment may require a 50 Ohm load.
Mapping of Transmitter Inputs for the Optional Termination Resistors is shown below:
Tx Pin
Names
Tx Pin
Number
Termination
Resistor
TX
TxIN0 51 R1
TxIN1 52 R2
TxIN2 54 R3
TxIN3 55 R4
TxIN4 56 R5
TxIN5 2 R6
TxIN6 3
TxIN7 4
R7
R8
TxIN8 6
TxIN9 7
TxIN10 8
TxIN11 10
TxIN12 11
TxIN13 12
TxIN14 14
TxIN15 15
R9
R10
R11
R12
R13
R14
R15
R16
TxIN16 16
TxIN17 18
TxIN18 19
TxIN19 20
TxIN20 22
TxIN21 23
TxIN22 24
TxIN23 25
TxIN24 27
TxIN25 28
TxIN26 30
TxIN27 50
TxCLKIN 31
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
50 Ohm Termination
(Optional)
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 10 of 25
FPD-Link Evaluation Kit User’s Manual
BOM (Bill of Materials) Transmitter PCB:
HSL Demo Board Schematic REV3
HSL8TXR3 Revision: 3 FPD-Link
Item Qty Reference Part
10
µF
CASE D
0.1
µF
22
µF
0.001
µF
0.01
µF
1206 (3216)
7343 (D)
0805 (2012)
0805 (2012)
IDC30X2 IDC60
IDC10X2 IDC20
0402
R15,R16,R17,R18,R19,R20,
R21,R22,R23,R24,R25,R26,
R27,R28,R29
R36,R37
N/A
0402
TP_.2"X.2"
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 11 of 25
FPD-Link Evaluation Kit User’s Manual
Rx FPD-Link Receiver Board:
J1 (60 position) provides access to the 28 bit LVTTL/LVCMOS and clock outputs.
The FPD-Link Receiver board is powered from the pads show below. For the receiver to be operational, the Power Down pin must be set HIGH with the jumper.
The 20-pin IDC connector (J2) provides the interface for LVDS signals for the
Receiver board.
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be scrambled in the IDC cable in order to be compatible with this demo kit.
60-pin IDC Connector
RxIN LVDS signals
20-pin IDC connector
1 2
GND
IN0-
IN0+
GND
IN1+
GND
IN1-
GND
GND
IN2+
GND
CLK+
IN2-
GND
CLK-
GND
IN3+
GND
IN3-
GND
19 20
J2
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be scrambled in the IDC cable in order to be compatible with this demo kit.
Vcc and Gnd MUST be applied externally here
/PD
60 59
RXOUT27
GND
RXOUT26
GND
RXOUT25
GND
RXOUT24
GND
RXOUT23
GND
RXOUT22
GND
RXOUT21
GND
RXOUT20
GND
RXOUT19
GND
RXOUT18
GND
RXOUT17
GND
RXOUT16
GND
RXOUT15
GND
RXOUT14
GND
RXOUT13
GND
RXOUT12
GND
RXOUT11
GND
RXOUT10
GND
RXOUT9
GND
RXOUT8
RXOUT7
RXOUT6
GND
GND
GND
RXOUT5
RXOUT4
GND
GND
GND
RXOUT3
RXOUT2
RXOUT1
RXOUT0
GND
GND
GND
GND
RXCLKOUT
GND
GND
2 1
J1
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 12 of 25
FPD-Link Evaluation Kit User’s Manual
Selectable Jumper Settings for the Rx Board
Jumper Purpose Settings
/PD PowerDown = ON
Vcc GND
(ON: Rx is operational;
Default setting is JP1 set HIGH (to Vcc), operational mode.
= OFF
Vcc GND
OFF: Rx powers down)
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 13 of 25
FPD-Link Evaluation Kit User’s Manual
RXIN3
LVDS Mapping by IDC Connector
The following two figures illustrate how the Rx outputs are mapped to the IDC connector (J1) (Note
– labels are also printed on the demo boards). The 20-pin IDC connector (J2) pinout is also shown.
(Receiver Board)
RXIN2
RXIN2
RXIN1
RXIN1
RXIN1
RXIN0
RXIN0
60
60-pin IDC Connector
2
RXOUT27
GND
RXOUT26
GND
RXOUT25
GND
RXOUT24
GND
RXOUT23
GND
RXOUT22
GND
RXOUT21
GND
RXOUT20
GND
RXOUT19
GND
RXOUT18
GND
RXOUT17
GND
RXOUT16
GND
RXOUT15
GND
RXOUT14
GND
RXOUT13
GND
RXOUT12
GND
RXOUT11
GND
RXOUT10
GND
RXOUT9
GND
RXOUT8
RXOUT7
RXOUT6
RXOUT5
RXOUT4
RXOUT3
RXOUT2
RXOUT1
RXOUT0
GND
GND
GND
GND
GND
GND
GND
GND
GND
RXCLKOUT
GND
GND
GND
J1
59
Pin 1
Pin 1
19
RxIN LVDS signals
20-pin IDC connector
GND
IN0+
GND
IN1+
GND
IN2+
GND
CLK+
GND
IN3+
J2
IN0-
GND
IN1-
GND
IN2-
GND
CLK-
GND
IN3-
GND
2
20
RXCLKIN
RXIN3
RXIN2
RXIN1
RXIN0
Previous Cycle Next Cycle
RXOUT23 RXOUT17 RXOUT16 RXOUT11 RXOUT10 RXOUT5 RXOUT27
RXOUT26 RXOUT25 RXOUT24 RXOUT22 RXOUT21 RXOUT20 RXOUT19
RXOUT18 RXOUT15 RXOUT14 RXOUT13 RXOUT12 RXOUT9 RXOUT8
RXOUT7 RXOUT6 RXOUT4 RXOUT3 RXOUT2 RXOUT1 RXOUT0
LVDS Data Inputs Mapped to LVTTL/LVCMOS Outputs
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 14 of 25
FPD-Link Evaluation Kit User’s Manual
Rx Optional: Series Termination for RxOut
On the Rx demo board, there are 29 outputs that have an 0402 pad in series (which are shorted out). These pads are unpopulated from the factory but are provided if the user needs to install a 450 Ohm series resistors. This is required if directly connecting to 50 Ohm inputs on a scope. To use this option the user must cut the signal line between the pads before installing the 450 Ohm series resistors. R1 to
R28 are associated with the DATA output lines. R29 is associated with CLKOUT.
The total load presented to the receiver output is 500 Ohms (450 + 50). The waveform on the scope is 1/10 of the signal due to the resulting voltage divider (50 /
(450 + 50)).
Optional Series Termination Resistor mapping is shown below:
Rx Pin Names Rx Pin
Number
Series
Termination
Resistor
RxOUT0 27 R28
RxOUT1 29 R27
RxOUT2 30 R26
RxOUT3 32 R25
RxOUT4 33 R24
RxOUT5 34 R23
RxOUT6 35 R22
RxOUT7 37 R21
RxOUT8 38 R20
RxOUT9 39 R19
RxOUT10 41 R18
RxOUT11 42 R17
RxOUT12 43 R16
RxOUT13 45 R15
RxOUT14 46 R14
RxOUT15 47 R13
RxOUT16 49 R12
RxOUT17 50 R11
RxOUT18 51 R10
RxOUT19 53 R9
RxOUT20 54 R8
RxOUT21 55 R7
RxOUT22 1
RxOUT23 2
R6
R5
RxOUT24 3
RxOUT25 5
RxOUT26 6
RxOUT27 7
RxCLKOUT 26
R4
R3
R2
R1
R29
RX
Series Termination
(Optional)
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 15 of 25
FPD-Link Evaluation Kit User’s Manual
BOM (Bill of Materials) Receiver PCB:
HSL Demo Board Schematic REV3
HSL8RXR3 Revision: 3 FPD-Link
Item Qty Reference Part
10
µF
CASE D
0.1
µF
22
µF
0.001
µF
0.01
µF
1206 (3216)
7343 (D)
0805 (2012)
0805 (2012)
R15,R16,R17,R18,R19,R20,
R21,R22,R23,R24,R25,R26,
R27,R28,R29
IDC30X2
IDC10X2
N/A
IDC60
IDC20
0402
0402
0402
TP_.2"X.2"
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 16 of 25
FPD-Link Evaluation Kit User’s Manual
Typical Connection / Test Equipment
The following is a list of typical test equipment that may be used to generate signals for the TX inputs:
1) Graphics card or GUI controller with digital RGB (LVTTL) output.
2) TEK HFS9009 - This pattern generator along with 9DG2 Cards may be used to generate input signals and also the clock signal.
3) TEK DG2020 - This generator may also be used to generate data and clock signals.
4) TEK MB100 BERT - This bit error rate tester may be used for both signal source and receiver.
5) Any other signal / pattern generator that generates the correct input levels as specified in the datasheet.
The following is a list of typically test equipment that may be used to monitor the output signals from the RX:
1) LCD Display Panel which supports digital RGB (LVTTL) inputs.
2) TEK MB100 BERT - Receiver.
3) Any SCOPE with 50 Ohm inputs or high impedance probes.
LVDS signals may be easily measured with high impedance / high bandwidth differential probes such as the TEK P6247 or P6248 differential probes.
The picture below shows a typical test set up using a Graphics Card and LCD Panel.
Transmitter
Board
Receiver
Board
LCD Panel
Digital RGB (TTL) from Graphic
Contoller
LVDS Interface
Cable
Digital RGB (TTL) to Panel
Contents of Demo Kit
Graphics
Card
AGP/PCI/ISA Bus
Typical FPD-Link Setup / PC Panel Application
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 17 of 25
FPD-Link Evaluation Kit User’s Manual
The picture below shows a typical test set up using a generator and scope.
Signal/Pattern Generator,
BERT Tester
50 ohm
Transmitter
Board
LVDS Interface
Cable
50 ohm
Optional
Termination
Receiver
Board
Optional
Termination
450 ohm
50 ohm
50 ohm
Oscilloscope,
BERT Tester
Typical Connection / Test Equipment Setup
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 18 of 25
FPD-Link Evaluation Kit User’s Manual
Typical Waveshapes
LVDS
The plot above shows both the LVDS Data channel with PRBS data and also the
LVDS Clock over laid. Note that the clock pattern is 4 bit times HIGH and 3 bit times
LOW. The differential signal should be typically +/-300mV. These waveforms were acquired using the TEK P6248 Probes. Clock rate is 85MHz.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 19 of 25
RxOUT
FPD-Link Evaluation Kit User’s Manual
The plot above shows both the recovered PRBS data and also the regenerated
Clock overlaid. Note that the clock transitions slightly before the data transition and strobes the data on the falling edge of the clock. The data and clock signals are low drive 3V CMOS outputs. The plot above is at 85MHz.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 20 of 25
FPD-Link Evaluation Kit User’s Manual
Troubleshooting
If the demo boards are not performing properly, use the following as a guide for quick solutions to potential problems.
QUICK CHECKS:
1. Check that Power and Ground are connected to both Tx AND Rx boards.
2. Check the supply voltage (typical 3.3V) and also current draw with both Tx and
Rx boards (should be about 200mA with clock and one data bit at 66MHz).
3. Verify input clock and input data signals meet requirements (VIL, VIH, tset, thold), Also verify that data is strobed on the selected rising/falling (R_FB pin) edge of the clock.
4. Check that the Jumpers are set correctly.
5. Check that the cable is properly connected.
TROUBLESHOOTING CHART
Problem…
Solution…
There is only the output clock.
There is no output data.
Make sure the data is applied to the correct input pin.
Make sure data is valid at the input.
No output data and clock.
Power, ground, input data and input clock are connected correctly, but no outputs.
Make sure Power is on. Input data and clock are active and connected correctly.
Make sure that the cable is secured to both demo boards.
Check the Power Down pins of both boards and make sure that the devices are enabled (/PD=Vcc) for operation.
The devices are pulling more than 1A of current.
After powering up the demo boards, the power supply reads less than 3V when it is set to 3.3V.
Check for shorts in the cables connecting the TX and
RX boards.
Use a larger power supply that will provide enough current for the demo boards, a 500mA power supply is recommended.
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 21 of 25
FPD-Link Evaluation Kit User’s Manual
Additional Information
For more information on FPD-Link Transmitters/Receivers, refer to the National’s
LVDS website at: www.national.com/appinfo/fpd
Application Notes
• AN-1032 An Introduction to FPD-Link
• AN-1056 STN Application using FPD-Link
• AN-1059 High Speed Transmission with LVDS Devices
• AN-1084
Application of Link Chips
• AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines
• AN-1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link
• AN-1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A -
Color Map
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 22 of 25
FPD-Link Evaluation Kit User’s Manual
Appendix
Tx PCB Schematic
Transmitter Board: HSL Demo Board Schematic
Document Number: HSL8TXR3
Rev: 3.0
Rx PCB Schematic
Receiver Board: HSL Demo Board Schematic
Document Number: HSL8RXR3
Rev: 3.0
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 23 of 25
J1
49
51
53
55
57
59
41
43
45
47
33
35
37
39
25
27
29
31
17
19
21
23
9
11
13
15
5
7
1
3
IDC30X2
50
52
54
56
58
60
42
44
46
48
34
36
38
40
26
28
30
32
18
20
22
24
10
12
14
16
6
8
2
4
TXIN0
TXIN1
TXIN2
TXIN3
TXIN4
TXIN5
TXIN6
TXIN7
TXIN8
TXIN9
TXIN10
TXIN11
TXIN12
TXIN13
TXIN14
TXIN15
TXIN16
TXIN17
TXIN18
TXIN19
TXIN20
TXIN21
TXIN22
TXIN23
TXIN24
TXIN25
TXIN26
TXIN27
TXCLKIN
R21
R22
R23
R24
R25
R26
R15
R16
R17
R18
R19
R20
R6
R7
R8
R9
R10
R11
R12
R13
R14
TXIN5
TXIN6
TXIN7
TXIN8
TXIN9
TXIN10
TXIN11
TXIN12
TXIN13
TXIN14
TXIN15
TXIN16
TXIN17
TXIN18
TXIN19
TXIN20
TXIN21
TXIN22
TXIN23
TXIN24
TXIN25
R1
R2
R3
R4
R5
TXIN0
TXIN1
TXIN2
TXIN3
TXIN4
+3.6V MAX
VCC
VCC
TXIN5
TXIN6
TXIN7
GND
TXIN8
TXIN9
TXIN10
VCC
TXIN11
TXIN12
TXIN13
GND
TXIN14
TXIN15
TXIN16
R_FB
TXIN17
TXIN18
TXIN19
GND
TXIN20
TXIN21
TXIN22
TXIN23
VCC
TXIN24
TXIN25
10
11
8
9
12
13
14
6
7
4
5
1
2
3
25
26
27
28
21
22
23
24
15
16
17
18
19
20
U1
TXIN4
TXIN3
TXIN2
GND
TXIN1
TXIN0
TXIN27
LVDS GND
TXOUT0-
TXOUT0+
TXOUT1-
TXOUT1+
LVDS VCC
LVDS GND
TXOUT2-
TXOUT2+
TXCLK OUT-
TXCLK OUT+
TXOUT3-
TXOUT3+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PWR DWN
TXCLK IN
TXIN26
GND
DS90C385 A
52
51
50
49
48
47
46
45
56
55
54
53
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
R27
R28
R29
TXIN26
TXIN27
TXCLKIN
VCC1
GND1
R32
R33
R34
VCC
VCC
LVDS_VCC
PLL_VCC
R35
R36
R37
PLL_GND
LVDS_GND
GND
VCC
C3
GND 22uF
LVDS_VCC
C4
0.001uF
C5
0.01uF
C6
0.1uF
LVDS_GND
PLL_VCC
C8 C9
0.001uF
0.01uF
C10
0.1uF
PLL_GND
C12 C13
0.001uF
0.01uF
C14
0.1uF
C7
22uF
C11
22uF
C15
22uF
R_FB
VCC
JP1
R31
3_PIN_HEADER
TP1
TP_.2"X.2"
TP2
TP_.2"X.2"
+3.6V MAX
VCC1
+
C1
10uF
+
C2
0.1uF
GND1
VCC
JP2
3_PIN_HEADER
/PD
TXOUT0-
TXOUT0+
TXOUT1-
TXOUT1+
LVDS_VCC
LVDS_GND
TXOUT2-
TXOUT2+
TXCLKOUT-
TXCLKOUT+
TXOUT3-
TXOUT3+
PLL_GND
PLL_VCC
LVDS_GND
TXOUT0+
TXOUT1+
TXOUT2+
TXCLKOUT+
TXOUT3+
J2
9
11
13
15
5
7
1
3
17
19
IDC10X2
10
12
14
16
18
20
6
8
2
4
TXOUT0-
TXOUT1-
TXOUT2-
TXCLKOUT-
TXOUT3-
Title
Size
Date:
HSL DEMO BOARD SCHEMATIC
Document Number
HSL8TXR3
Friday, March 5, 2004 Sheet 1 of 1
Rev
3
LVDS_GND
RXIN0+
RXIN1+
RXIN2+
RXCLKIN+
RXIN3+
J2
9
11
13
15
5
7
1
3
17
19
IDC10X2
1 0
12
14
16
18
20
6
8
2
4
RXIN0-
RXIN1-
RXIN2-
RXCLKIN-
RXIN3-
RXIN0-
RXIN0+
RXIN1-
RXIN1+
RXIN2-
RXIN2+
RXCLKIN-
RXCLKIN+
RXIN3-
RXIN3+
R30
100
R31
100
R34
100
R33
100
LVDS_VCC
LVDS_GND
VCC
JP1
/PD
3_PIN_HEADER
R32
100
PLL_VCC
PLL_GND
U1
10
11
8
9
12
13
14
6
7
4
5
1
2
3
25
26
27
28
21
22
23
24
15
16
17
18
19
20
RXOUT22
RXOUT23
RXOUT24
GND
RXOUT25
RXOUT26
RXOUT27
LVDS GND
RXIN0-
RXIN0+
RXIN1-
RXIN1+
LVDS VCC
LVDS GND
RXIN2-
RXIN2+
RXCLK IN-
RXCLK IN+
RXIN3-
RXIN3+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PWR DWN
RXCLK OUT
RXOUT0
GND
DS90CF386
VCC
RXOUT21
RXOUT20
RXOUT19
GND
RXOUT18
RXOUT17
RXOUT16
VCC
RXOUT15
RXOUT14
RXOUT13
GND
RXOUT12
RXOUT11
RXOUT10
VCC
RXOUT9
RXOUT8
RXOUT7
GND
RXOUT6
RXOUT5
RXOUT4
RXOUT3
VCC
RXOUT2
RXOUT1
52
51
50
49
48
47
46
45
56
55
54
53
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
+3.6V MAX
VCC
RXOUT27
RXOUT26
RXOUT25
RXOUT24
RXOUT23
RXOUT22
RXOUT21
RXOUT20
RXOUT19
RXOUT18
RXOUT17
RXOUT16
RXOUT15
RXOUT14
RXOUT13
RXOUT12
RXOUT11
RXOUT10
RXOUT9
RXOUT8
RXOUT7
RXOUT6
RXOUT5
RXOUT4
RXOUT3
RXOUT2
RXOUT1
R28
R29
RXOUT0
RXCLKOUT
R13
R14
R15
R16
R17
R18
R19
R20
R21
R7
R8
R9
R10
R11
R12
R22
R23
R24
R25
R26
R27
R1
R2
R3
R4
R5
R6
RXOUT27
RXOUT26
RXOUT25
RXOUT24
RXOUT23
RXOUT22
RXOUT21
RXOUT20
RXOUT19
RXOUT18
RXOUT17
RXOUT16
RXOUT15
RXOUT14
RXOUT13
RXOUT12
RXOUT11
RXOUT10
RXOUT9
RXOUT8
RXOUT7
RXOUT6
RXOUT5
RXOUT4
RXOUT3
RXOUT2
RXOUT1
RXOUT0
RXCLKOUT
J1
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57
55
53
51
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47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
IDC30X2
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
VCC1
GND1
R35
R36
R37
VCC
VCC
LVDS_VCC
PLL_VCC
R38
R39
R40
PLL_GND
LVDS_GND
GND
VCC
C3
GND 22uF
LVDS_VCC
C4
0.001uF
C5
0.01uF
LVDS_GND
PLL_VCC
C8 C9
0.001uF
0.01uF
PLL_GND
C12 C13
0.001uF
0.01uF
C6
0.1uF
C10
0.1uF
C14
0.1uF
C7
22uF
C11
22uF
C15
22uF
TP1
TP_.2"X.2"
TP2
+3.6V MAX
VCC1
+
C1
10uF
+
C2
0.1uF
GND1
TP_.2"X.2"
Title
Size
Date:
HSL DEMO BOARD SCHEMATIC
Document Number
HSL8RXR3
Friday, October 27, 2000 Sheet 1 of 1
Rev
3
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments
:
FLINK3V8BT-85/NOPB
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