ASIC Prototyping. Cypress Semiconductor CY7C1360C

ASIC Prototyping

Why use FPGAs for ASIC prototyping?

In the modern ASIC design flow, the use of logic simulator software had been a relevant choice of technique for ASIC designers for long time as the older process ASIC had limited size of the designs.

Also, the lower cost of the mask iterations allowed the designers to spin the design several times per project.

The traditional design and verification flow is a sequential flow as follows:

(1) Verify the ASIC design using logic simulator and static timing analyzer tools

(2) Develop the evaluation board and ASIC engineering sample (ES)

(3) Verify both hardware and software (system verification) using the outcome of (2)

(4) Redesign and build (2) if any bugs are found because the mask cost was reasonable

The mask cost for the latest ASIC process exceeds multiple million dollars recently, and it is almost prohibitive to reiterate the ASIC design while the product life cycle is shortening and the workload for software verification is widening.

The following illustration explains how the introduction of prototyping by FPGA dramatically changes the

ASIC development flow.

Advantages of FPGA prototyping

The verification of design using FPGA can be done at faster speed in operation and in parallel by which shorter time of total verification can be attained. It is also effective for reducing the risk of ASIC chip design reiteration by specification change.

Faster operation speed of verification

The prototype design in FPGA can operate in the speed of as fast as hundreds of MHz. Even the very expensive emulator costing more than a few million dollars and the high level verification tools using C language can attain only a few

MHz at the fastest. The verification speed using FPGA prototype is predominantly higher and closer to the speed of the final product.

Moreover, because the test pattern is input directly from the system, the verification engineers can skip the process of generating detailed test bench and expectation values but the result is observed in the actual system.

This will result in reduction of workload to check and match the actual output and the expected results in great deal.

The recommended verification flow in general is:

(1) Design the system architecture by C language and verify

(2) Verify the logic between function blocks using logic simulator

(3) Build the FPGA prototype and verify the system

For instance, it is very difficult to use waveform for evaluating the picture images by different algorithms. The verification using the FPGA prototype enables the engineers actually see the output images against various image source data.

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Parallel verification

The FPGA prototyping method allows the hardware design and software verification simultaneously (hardware-software co-design).

The verification period can be dramatically reduced by verifying software by functionality on multiple prototype boards in parallel.

The figure shows how the parallel verification improves the verification process in the design flow.

Hardware Development



Board Development Software Development

FPGA

Development

Build multiple

FPGA boards

Software

Design

First

FPGA

Design Software

Verification of

Software





FPGA

Redesign &

Verification

ASIC Design

Development

Build boards for ASIC

Spec

Change



ASIC

Tape Out



 First Level FPGA Design

The FPGA designers first design the internal block of FPGA to communicate with software and external devices so that the software and board hardware design verification can be started even before the completion of the

FPGA design. The FPGA designers pass out the FPGA functional block design to software engineers after verifying basic functionality by logic simulation.

 Software Verification

Software designers verify the software using the FPGA board and FPGA design passed to them as the result of the process 1. It is common that the verification is done in multiple boards by functionality or by the engineer in parallel. (Parallel software verification; Parallel board – software verification)

During this process the FPGA designers continue the work on the design to add other functional blocks needed and improve the design quality of the total FPGA design. As the design of the FPGA is improved, it is passed each time to software engineers for verification. (Parallel logic design – software verification)

 Specification Change

As the verification of the system continues, there can be the need to revise the partitioning between hardware and software processes, changes in other devices on the board, I/O specification changes on the FPGA, etc. As needed, project managers discuss the changes in specification and work on the changes to improve the system operation.

Going through this process, the risk of revisions in the ASIC design by specification changes can be minimized. (Parallel specification making – system verification)

 ASIC Design Development

As the design quality of the FPGA design continues to improve, the ASIC design development is started in parallel with the system verification using the FPGA prototype.

The verification using the FPGA prototype will be continued until the availability of ASIC engineering sample (ES) as small corner bugs can be found. (Parallel ASIC design – system verification)

Frequently Asked Questions

Following is the list of questions and answers for

ASIC designers without experience of using

FPGA.

Q1. Do we have to build the FPGA board on our own?

A1. There are off the shelf ASIC prototyping board using FPGAs from various vendors.

Please consult with your local Altera distributors (Altima, Elsene, Cytech, Galaxy) for details.

If these boards satisfy your specifications and functions (FPGA density per board, architecture for scaling the density, I/O types and speed, memory requirements, etc), it is highly recommended to use those to reduce the time and efforts to design, build and verify the board. If not, you are encouraged to build your own board.

Q2. How do you do the debugging on the

FPGA?

A2. Unlike in ASICs, you can check the internal operation of the FPGA while it is in operation. You will not need oscilloscope or logic analyzer but you can observe the waveform of internal signals in operation by just preparing the FPGA design environment.

However, the debugging with FPGA in operation is not easier compared with the use of logic simulator. It is recommended to use logic simulator for basic and main functionalities first, and move to FPGA system verification for smaller bugs.

Q3. As the high level design methodology like

C language becomes common, will the

FPGA prototyping be obsolete?

A3. The high level design methodology like C language is effective for applications with frequent update of algorithms as it requires less man power than RTL design. However, the simulation speed is usually very slow as several MHz and the total time needed for

FPGA prototyping is much faster.

It is more realistic to use the high level verification for algorithm and FPGA prototyping for system verification. It is also said that while C language is more sophisticated for algorithm development, the experiment on the physical level is very much important to utilize the human intellectual activities in the brain.

This is the reason why the FPGA prototyping method is widely utilized at laboratories for concept building and proof of concept works.

High level design:

Verify the idea in mind by simulator (no more evolving of the idea)

FPGA prototyping:

New idea can be found from the results different from initial expectation

Q4. Do you have to design ASIC and FPGA differently?

A4. In the case the ASIC design is too big to fit in one FPGA, you have to partition the design.

Also in the case the performance of FPGA does not meet requirements, the design need to be changed to fit the architecture of the FPGA.

Normally the same RTL design can be shared between ASIC and FPGA.

In the logic emulator you can use the ASIC design as is, but in reality the emulators use multiple FPGAs for the hardware part. The emulators tend to operate at lower performance than FPGA prototype as emulators are coupled with gimmicks to automatically partitioning the design and improve the ease of debugging.

Q5. Can you do the timing verification?

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A5. Unfortunately, you cannot do the timing verification on the FPGA prototype as the timing for ASIC and FPGA are different.

However, doing the functional verification on the FPGA board is a very effective way to reduce reiteration of ASIC designs as the most common reason for ASIC re-spin is the functional errors.

Altera FPGAs use the same Synopsys Design

Constraints (SDC) used in ASIC design for

FPGA timing constraints. So, the transition of timing constraint information is smoothly done between FPGA and ASIC.

Q6. What are the drawbacks in FPGA prototyping?

A6. Those relying too much on FPGA prototyping sometimes start skipping the process of specification writing and logic simulation.

Without specification sheet the development can be delayed by going back and forth between physical verification and small specification changes again and again, or it may take more time to debug on the board by skipping logic simulation. However, these are not the disadvantage of FPGA prototyping but it is more of a lack of design flow or project management.

The FPGA prototyping method is effective in reducing the total time for development by operating the verification and design in parallel, but it requires more human resources. In the case you choose to employ the FPGA prototyping, our recommendation is to consult with design houses with FPGA design experience.

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ASIC Prototyping Board Solutions

Stratix IV ASIC Prototyping Board

EK4SEH40

Galaxy Far East Corp.

Altera Stratix IV-E FBGA1517 FPGA Prototyping

Module

The module use Altera Stratix IV-E family FPGA with FBGA (Fine Line Ball Array) 1517 pin package device . Each extended I/O signal through protection buffer, provide 5V tolerance feature.

Features

• Altera Stratix IV Family FineLine BGA 1517 pin

Package Device(EP4SE530 to P4SE820) up to

813,050 LEs, 23,130K RAM Bits, 960 18X18

Multipliers & 12 PLLs

• Altera Serial Configuration Device EPCS128

• 2 UART Serial Communication Port

• Oscillator Socket

• Provide 757 In/Out Pin (With I/O Protection buffer)

• 1 Mictor Connector

• Power System For Altera device (1.1V/3.0V/2.5V)

• 8 Separate I/O Bank

• Heat Sink Fan

• JTAG Port Connector

• AS Port Connector

• Battery for Stratix IV Security System

• Accessories

 AC-Adapter x 1 piece（Power Adaptor of AC

110V/220V to DC 12V/5A）

 GFEC USB Download Cable x 1

Altera Stratix IV-E FBGA1517 FPGA Prototyping

Module

The module use Altera Stratix IV-E family FPGA with FBGA (Fine Line Ball Array) 1517 pin package device . Each extended I/O signal through protection buffer, provide 5V tolerance feature.

Features

• Altera Stratix IV Family FineLine BGA 1517 pin

Package Device(EP4SE530 to P4SE820) up to

813,050 LEs, 23,130K RAM Bits, 960 18X18

Multipliers & 12 PLLs

• Altera Serial Configuration Device EPCS128

 2 UART Serial Communication Port

Board Solutions from Third Party Board Partners

ALL-IN-ONE Base Board B-11

(Stratix III Edition)

Accverinos Co.,Ltd.

Features

• EP3SL340F1517 or EP3SL200F1517 (-2 or -3)

• DDR2 DIMM

• DVI I/O Support: 1 each of input and output port using TI TFP403 & 410 chips. Max 165MHz

• 1 x Gigabit Ethernet PHY & RJ45 Connector.

• 1 x USB2.0 Connector, Cypress EZ-USB and ULPI supporting PHY - Can use either of USB MCU or

PHY

• 8 pairs each of input and output signals through

C44LVDS connectors. Tested 1.2Gbps/pair operation

• SD Card support (connected directly to FPGA and controlled by MegaCore IP)

• 1 x Altera standard HSMC connector

• 5 x Samtec 120-pin connectors

StarFire-2D820/530/340

Beijing HyperSilicon Co., LTD

Features

• Two Altera Stratix IV (EP4SE820 / EP4SE530 /

EP3SL340F1760) FPGAs with capacity of 13.6

Million ASIC gates

• 760 connections between two FPGAs, with support for the AXI / APB / AHB bus standards.

• Stackable for two or more StarFire-2D820/530/340

• Optional SODIMM memory expansion slot, covering SDRAM, DDR, Mobile DDR, DDRII memory, with clock frequency up to 400MHz.

• 480 user IOs

• 4 crystal sockets to provide clock input

• 4 SMA coaxial high speed I/Os

• A number of high-end power modules guarantee the power for the entire mother board and the extension of daughter boards as well

Cyclone III SOPC board

Hangzhou Free Electron Co. Ltd

This board offer Ethernet, DDR2 interface, enough test port and expend IO. It is suitable for SOPC system design and small/middle density IP/ASIC verification.

Features

• Cyclone III EP3C80F780C8N or

EP3C120F780C8N

• 256M DDR2 SO-DIMM (up to 2G)

• 12 layer PCB

• 216 expand IO/CLK/PLLOUT (include 9 LVDS in,

LVDS out)

• Marvel 10M/100M/1000M Ethernet PHY

• SMA clock/data input/output

• 32M FLASH

• 4 x LED, one reset

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S4 TAI Logic Module for SOC prototype

S2C Inc.

This platform used 2 pcs Altera StratixIV (EP4SE530

/EP4SE820) FPGA, can verify 16.4M ASIC gate design.

Features

• Up to 66Mbits of FPGA iternal memory

• Up to 2720 embedded 18x8 Multipliers

• One on-board DDR2 SO-DIMM socket

• One on-board DDR3 SO-DIMM socket

• Stackable to meet even larger gate count needs

• Up to 416 dedicated IO per FPGA

• Up to 454 shared nets and IOs for dual FPGA

• 20 user clocks from

 2 oscillator sockets

 3 pairs of differential SMB clock inputs

 3 programmable clock source (1-195MHz)

 12 feedback clocks from any user FPGA

 20 clock sources from J1 connector

DE3 Development System

Terasic Technologies

Features

• Stratix III 3SL150, 260 or 340

• DDR2 SO-DIMM socket

• 4 push-button switches, 1 DIP switch (x8) and 4 slide switches

• 8 RGB LEDs

• 2 seven-segment displays

• USB Host/Slave Controller with one mini-AB for host/device and two type A for device

• SD Card socket

• 50MHz onboard oscillator for clock source

• 1 SMA connector for external clock input

• 1 SMA connector for PLL clock output

• Eight 180-pin High Speed Terasic Connectors

(HSTC), where 4 male and 4 female connectors are on the top and bottom of DE3, respectively.

• Two 40-pin Expansion Headers

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