7 Application, Implementation, and Layout. Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING

DP83848C, DP83848I

DP83848VYB, DP83848YB

SNLS266E – MAY 2007 – REVISED MARCH 2015

7 Application, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

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7.1

Application Information

The device is a physical layer Ethernet transceiver. Typical operating voltage is 3.3 V with power consumption less than 270 mW. When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation of device. Following typical application and design requirements can be used for selecting appropriate component values for DP83848.

7.2

Typical Application

Figure 7-1. Typical Application Schematic

7.2.1

Design Requirements

The design requirements for DP83848 are:

• Vin = 3.3 V

• Vout = Vcc – 0.5 V

• Clock Input = 25 MHz for MII and 50 MHz for RMII

7.2.1.1

TPI Network Circuit

Figure 7-2

shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.

• Pulse H1102

• Pulse H2019

• Pulse J0011D21

• Pulse J0011D21B

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Vdd

TPRDM

49.9 :

Vdd

COMMON MODE CHOKES

MAY BE REQUIRED

0.1 P F

49.9 : 1:1

TDRDP

TPTDM

Vdd

0.1 P F*

0.1 P F*

RD-

RD+

TD-

TD+

RJ45

49.9 :

1:1

T1

49.9 :

0.1 P F NOTE: CENTER TAP IS PULLED TO VDD

*PLACE CAPACITORS CLOSE TO THE

TRANSFORMER CENTER TAPS

TPTDP

All values are typical and are +/- 1%

PLACE RESISTORS AND

CAPACITORS CLOSE TO

THE DEVICE

Figure 7-2. 10/100 Mb/s Twisted Pair Interface

7.2.1.2

Clock IN (X1) Requirements

The DP83848VYB supports an external CMOS level oscillator source or a crystal resonator device.

7.2.1.2.1 Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in

Table 7-1

and

Table 7-2

.

7.2.1.2.2 Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired.

Figure 7-4

shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of

100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, C

L1 and C

L2 should be set at 33 pF, and R

1 should be set at 0 Ω.

Specification for 25-MHz crystal are listed in

Table 7-3 .

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Figure 7-3. Crystal Oscillator Circuit

Table 7-1. 25-MHz Oscillator Specification

PARAMETER

Frequency

Frequency Tolerance

Frequency Stability

Rise / Fall Time

Jitter

Jitter

Symmetry

CONDITION

Operational Temperature

1 year aging

20% - 80%

Short term

Long term

Duty Cycle

MIN TYP

25

MAX

±50

±50

6

800

(1)

800

(1)

60% 40%

(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to AN-1548 ( SNLA091 ),

PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance.

UNIT

MHz ppm ppm nsec psec psec

Table 7-2. 50-MHz Oscillator Specification

PARAMETER

Frequency

Frequency Tolerance

Frequency Stability

Rise / Fall Time

Jitter

Jitter

Symmetry

CONDITION

Operational Temperature

Operational Temperature

20% - 80%

Short term

Long term

Duty Cycle

MIN TYP

50

MAX

±50

±50

6

800

(1)

800

(1)

60% 40%

(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to AN-1548 ( SNLA091 ),

PHYTER 100 Base-TX Reference Clock Jitter Tolerance for details on jitter performance.

UNIT

MHz ppm ppm nsec psec psec

PARAMETER

Frequency

Frequency Tolerance

Frequency Stability

Load Capacitance

Table 7-3. 25-MHz Crystal Specification

CONDITION MIN

Operational Temperature

1 year aging

25

TYP

25

MAX

±50

±50

40

UNIT

MHz ppm ppm pF

7.2.1.3

Power Feedback Circuit

To ensure correct operation for the DP83848VYB, parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31

(PFBOUT), each pin requires a small capacitor (.1 µF). See

Figure 7-4

below for proper connections.

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Figure 7-4. Power Feedback Connection

7.2.1.3.1 Power Down and Interrupt

The Power Down and Interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power-down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR

(0x11h) will configure the pin as an active low interrupt output.

7.2.1.3.1.1 Power Down Control Mode

The PWRDOWN_INT pins can be asserted low to put the device in a Power Down mode. This is equivalent to setting bit 11 (Power Down) in the Basic Mode Control Register, BMCR (0x00h). An external control signal can be used to drive the pin low, overcoming the weak internal pullup resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the PWRDOWN_INT pin. Since the device will still respond to management register accesses, setting the INT_OE bit in the MICR register will disable the PWRDOWN_INT input, allowing the device to exit the

Power Down state.

7.2.1.3.1.2 Interrupt Mechanisms

The interrupt function is controlled through register access. All interrupt sources are disabled by default.

Setting bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (0x12h). The PWRDOWN_INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the MISR clears ALL pending interrupts.

Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be:

• Write 0003h to MICR to set INTEN and INT_OE

• Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN

• Monitor PWRDOWN_INT pin

When PWRDOWN_INT pin asserts low, the user would read the MISR register to see if the ED_INT or

LINK_INT bits are set, for example, which source caused the interrupt. After reading the MISR, the interrupt bits should clear and the PWRDOWN_INT pin will deassert.

7.2.1.4

Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed below, others may be compatible following the requirements listed in Table 6-4. It is recommended that the magnetics include both an isolation transformer and an integrated common mode choke to reduce

EMI. When doing the layout, do not run signals under the magnetics. This could cause unwanted noise crosstalk. Likewise void the planes under discrete magnetics, this will help prevent common mode noise coupling. To save board space and reduce component count, an RJ-45 with integrated magnetics may be used.

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PARAMETER

Turn Ratio

Insertion Loss

Return Loss

Differential to Common Rejection Ratio

Crosstalk

Isolation

Table 7-4. Magnetics Requirements

-30

-20

-35

-30

1,500

TYP

1:1

-1

-16

-12

10

UNITS

— dB dB dB dB dB dB dB dB

Vrms

CONDITION

±2%

1-100 MHz

1-30 MHz

30-60 MHz

60-80 MHz

1-50MHz

50-150 MHz

30 MHz

60 MHz

HPOT

7.2.1.5

ESD Protection

Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are less sensitive from ESD events.

See

Section 5.2

for ESD rating.

7.2.2

Detailed Design Procedure

7.2.2.1

MAC Interface (MII/RMII)

The Media Independent Interface (MII) connects the PHYTER component to the Media Access Controller

(MAC). The MAC may in fact be a discrete device, integrated into a microprocessor, CPU or FPGA. On the MII signals, the IEEE specification states the bus should be 68Ω impedance. For space critical designs, the PHYTER family of products also support Reduced MII (RMII). For additional information on this mode of operation, refer to the AN-1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced

Media Independent Interface (RMII) Mode Application Report ( SNLA076 ).

7.2.2.1.1 Termination Requirement

To reduce digital signal energy, 50Ω series termination resistors are recommended for all MII output signals (including RXCLK, TXCLK, and RX Data signals.)

7.2.2.1.2 Recommended Maximum Trace Length

Although RMII and MII are synchronous bus architectures, there are a number of factors limiting signal trace lengths. With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible to noise interference. Longer traces also act as antennas, and if run on the surface layer, can increase EMI radiation. If a long trace is running near and adjacent to a noisy signal, the unwanted signals could be coupled in as cross talk. It is recommended to keep the signal trace lengths as short as possible.

Ideally, keep the traces under 6 inches. Trace length matching, to within 2.0 inches on the MII or RMII bus is also recommended. Significant differences in the trace lengths can cause data timing issues. As with any high speed data signal, good design practices dictate that impedance should be maintained and stubs should be avoided throughout the entire data path.

7.2.2.2

Calculating Impedance

The following equations can be used to calculate the differential impedance of the board. For microstrip traces, a solid ground plane is needed under the signal traces. The ground plane helps keep the EMI localized and the trace impedance continuous. Since stripline traces are typically sandwiched between the ground/supply planes, they have the advantage of lower EMI radiation and less noise coupling. The trade off of using strip line is lower propagation speed.

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7.2.2.2.1 Microstrip Impedance - Single-Ended

Z o

=

F

¥E r

87

+ (1.41)

G ln l5.98

H

0.8 W + T p

DP83848C, DP83848I

DP83848VYB, DP83848YB

SNLS266E – MAY 2007 – REVISED MARCH 2015

(3)

Figure 7-5. Microstrip Impedance - Single-Ended

7.2.2.2.2 Stripline Impedance – Single Ended

Z o

=

F

60

¥E r

G ln F1.98 × l

2 × H + T

0.8 × W + TpG

(4)

Figure 7-6. Stripline Impedance – Single Ended

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7.2.2.2.3 Microstrip Impedance - Differential

Z diff

= 2 × Z o

×

F1 F 0.48 le @F0.96

S

HA pG www.ti.com

(5)

Figure 7-7. Microstrip Impedance - Differential

7.2.2.2.4 Stripline Impedance - Differential

Z diff

= 2 × Z o

F1 F 0.347 le @F2.9

S

HA pG

(6)

Figure 7-8. Stripline Impedance - Differential

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7.2.3

Application Curves

DP83848C, DP83848I

DP83848VYB, DP83848YB

SNLS266E – MAY 2007 – REVISED MARCH 2015

Figure 7-9. Sample 100 Mb/s Waveform (MLT-3) Figure 7-10. Sample 10 Mb/s Waveform

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7.3

Layout

7.3.1

Layout Guidelines

7.3.1.1

PCB Layout Considerations

Place the 49.9Ω,1% resistors and 0.1-μF decoupling capacitor near the PHYTER TD± and RD± pins and via directly to the Vdd plane.

Stubs should be avoided on all signal traces, especially the differential signal pairs. See

Figure 7-11

.

Within the pairs (for example, TD+ and TD-) the trace lengths should be run parallel to each other and matched in length. Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI. See

Figure 7-11 .

Figure 7-11. Differential Signal Pair – Stubs

Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities and should be minimized. Route an entire trace pair on a single layer if possible.

PCB trace lengths should be kept as short as possible.

Signal traces should not be run such that they cross a plane split. See

Figure 7-12

. A signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality as well, potentially creating EMI problems.

Figure 7-12. Differential Signal Pair-Plane Crossing

MDI signal traces should have 50 Ω to ground or 100 Ω differential controlled impedance. Many tools are available online to calculate this.

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7.3.1.2

PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a four layer PCB is recommended for implementing PHYTER components in end user systems. The following layer stack-ups are recommended for four, six, and eight-layer boards, although other options are possible.

Figure 7-13. PCB Stripline Layer Stacking

Within a PCB it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated chassis ground plane is used.

Figure 7-14

illustrates alternative PCB stacking options.

Figure 7-14. Alternative PCB Stripline Layer Stacking

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7.3.2

Layout Example www.ti.com

PHY

Component

Termination

Components

System Power/Ground

Planes

Note:Power/

Ground Planes

Voided under

Transformer

Plane Coupling

Component

Transformer

(if not

Integrated in

RJ45)

RJ45

Connector

Plane Coupling

Component

Chassis Ground

Plane

Figure 7-15. Layout Example

7.4

Power Supply Recommendations

The device Vdd supply pins should be bypassed with low impedance 0.1μF surface mount capacitors. To reduce EMI, the capacitors should be places as close as possible to the component Vdd supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding

EMI beads becomes necessary to meet system level certification testing requirements. (See Figure 6.8) It is recommended the PCB have at least one solid ground plane and one solid Vdd plane to provide a low impedance power source to the component. This also provides a low impedance return path for nondifferential digital MII and clock signals. A 10.0μF capacitor should also be placed near the PHY component for local bulk bypassing between the Vdd and ground planes.

Vdd

PCB

Via

Optional 0 : or Bead

PHY

Component

Vdd

Pin

0.1 P F

Ground Pin

PCB Via

Figure 7-16. Vdd Bypass Layout

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