NXP LPC2460FBD208 Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Data Sheet

Ball

R14 [1]

P0[12]/

USB_PPWR2/

MISO1/AD0[6]

P0[13]/

USB_UP_LED2/

MOSI1/AD0[7]

P0[14]/

USB_HSTEN2/

USB_CONNECT2/S

SEL1

P0[15]/TXD1/

SCK0/SCK

P0[16]/RXD1/

SSEL0/SSEL

P0[17]/CTS1/

MISO0/MISO

P0[18]/DCD1/

MOSI0/MOSI

128

130

126

124

K17

K15

I/O

Type Description

I/O P0[11] — General purpose digital input/output pin.

I/O

RXD2 — Receiver input for UART2.

SCL2 — I 2 C2 clock input/output (this is not an open-drain pin).

MAT3[1] — Match output for Timer 3, channel 1.

P0[12] — General purpose digital input/output pin.

USB_PPWR2 — Port Power enable signal for USB port 2.

MISO1 — Master In Slave Out for SSP1.

AD0[6] — A/D converter 0, input 6.

P0[13] — General purpose digital input/output pin.

USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when host is enabled and detects activity on the bus.

MOSI1 — Master Out Slave In for SSP1.

AD0[7] — A/D converter 0, input 7.

P0[14] — General purpose digital input/output pin.

USB_HSTEN2 — Host Enabled status for USB port 2.

USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 k

 resistor under software control. Used with the SoftConnect USB feature.

SSEL1 — Slave Select for SSP1.

P0[15] — General purpose digital input/output pin.

TXD1 — Transmitter output for UART1.

SCK0 — Serial clock for SSP0.

SCK — Serial clock for SPI.

P0 [16] — General purpose digital input/output pin.

RXD1 — Receiver input for UART1.

SSEL0 — Slave Select for SSP0.

SSEL — Slave Select for SPI.

P0[17] — General purpose digital input/output pin.

CTS1 — Clear to Send input for UART1.

MISO0 — Master In Slave Out for SSP0.

MISO — Master In Slave Out for SPI.

P0[18] — General purpose digital input/output pin.

DCD1 — Data Carrier Detect input for UART1.

MOSI0 — Master Out Slave In for SSP0.

MOSI — Master Out Slave In for SPI.

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

11 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P0[19]/DSR1/

MCICLK/SDA1

P0[20]/DTR1/

MCICMD/SCL1

P0[21]/RI1/

MCIPWR/RD1

P0[22]/RTS1/

MCIDAT0/TD1

P0[23]/AD0[0]/

I2SRX_CLK/

CAP3[0]

P0[24]/AD0[1]/

I2SRX_WS/

CAP3[1]

P0[25]/AD0[2]/

I2SRX_SDA/

TXD3

P0[26]/AD0[3]/

AOUT/RXD3

P0[27]/SDA0

Pin

122

120

118

116

Ball

M17

M16

I/O

Type Description

I/O P0[19] — General purpose digital input/output pin.

DSR1 — Data Set Ready input for UART1.

MCICLK — Clock output line for SD/MMC interface.

SDA1 — I 2 C1 data input/output (this is not an open-drain pin).

P0[20] — General purpose digital input/output pin.

DTR1 — Data Terminal Ready output for UART1.

MCICMD — Command line for SD/MMC interface.

SCL1 — I 2 C1 clock input/output (this is not an open-drain pin).

P0[21] — General purpose digital input/output pin.

RI1 — Ring Indicator input for UART1.

MCIPWR — Power Supply Enable for external SD/MMC power supply.

RD1 — CAN1 receiver input (LPC2460 only).

P0[22] — General purpose digital input/output pin.

RTS1 — Request to Send output for UART1.

MCIDAT0 — Data line 0 for SD/MMC interface.

TD1 — CAN1 transmitter output (LPC2460 only).

P0[23] — General purpose digital input/output pin.

AD0[0] — A/D converter 0, input 0.

I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2 S-bus

specification.

CAP3[0] — Capture input for Timer 3, channel 0.

P0[24] — General purpose digital input/output pin.

AD0[1] — A/D converter 0, input 1.

I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2 S-bus

specification.

CAP3[1] — Capture input for Timer 3, channel 1.

P0[25] — General purpose digital input/output pin.

AD0[2] — A/D converter 0, input 2.

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2 S-bus

specification.

TXD3 — Transmitter output for UART3.

P0[26] — General purpose digital input/output pin.

AD0[3] — A/D converter 0, input 3.

AOUT — D/A converter output.

RXD3 — Receiver input for UART3.

P0[27] — General purpose digital input/output pin.

SDA0 — I 2 C0 data input/output. Open-drain output (for I 2 C-bus compliance).

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

12 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P0[28]/SCL0

P0[29]/USB_D+1

P0[30]/USB_D

P1[0]/

ENET_TXD0

P1[1]/

ENET_TXD1

P1[4]/

ENET_TX_EN

P1[5]/

ENET_TX_ER/

MCIPWR/

PWM0[3]

1

P0[31]/USB_D+2

P1[0] to P1[31]

P1[2]/

ENET_TXD2/

MCICLK/

PWM0[1]

P1[3]/

ENET_TXD3/

MCICMD/

PWM0[2]

P1[6]/

ENET_TX_CLK/

MCIDAT0/

PWM0[4]

Pin

[4]

[5]

196

194

185

177

192

156

171

Ball

A10

A17

B11

I/O

Type Description

I/O

P0[28] — General purpose digital input/output pin.

SCL0 — I 2 C0 clock input/output. Open-drain output (for I 2 C-bus compliance).

I/O P0[29] — General purpose digital input/output pin.

I/O

USB_D+1 — USB port 1 bidirectional D+ line.

P0[30] — General purpose digital input/output pin.

USB_D

1 — USB port 1 bidirectional D line.

P0[31] — General purpose digital input/output pin.

USB_D+2 — USB port 2 bidirectional D+ line.

Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect block.

P1[0] — General purpose digital input/output pin.

I/O

ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface)

(LPC2460 only).

P1[1] — General purpose digital input/output pin.

ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface)

(LPC2460 only).

I/O

P1[2] — General purpose digital input/output pin.

ENET_TXD2 — Ethernet transmit data 2 (MII interface) (LPC2460 only).

MCICLK — Clock output line for SD/MMC interface.

PWM0[1] — Pulse Width Modulator 0, output 1.

P1[3] — General purpose digital input/output pin.

ENET_TXD3 — Ethernet transmit data 3 (MII interface) (LPC2460 only).

I/O

MCICMD — Command line for SD/MMC interface.

PWM0[2] — Pulse Width Modulator 0, output 2.

P1[4] — General purpose digital input/output pin.

ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface)

(LPC2460 only).

P1[5] — General purpose digital input/output pin.

ENET_TX_ER — Ethernet Transmit Error (MII interface) (LPC2460 only).

MCIPWR — Power Supply Enable for external SD/MMC power supply.

PWM0[3] — Pulse Width Modulator 0, output 3.

P1[6] — General purpose digital input/output pin.

ENET_TX_CLK — Ethernet Transmit Clock (MII interface) (LPC2460 only).

MCIDAT0 — Data line 0 for SD/MMC interface.

PWM0[4] — Pulse Width Modulator 0, output 4.

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

13 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol Pin

153

P1[7]/

ENET_COL/

MCIDAT1/

PWM0[5]

Ball

D14 [1]

P1[8]/

ENET_CRS_DV/

ENET_CRS

P1[9]/

ENET_RXD0

P1[10]/

ENET_RXD1

P1[11]/

ENET_RXD2/

MCIDAT2/

PWM0[6]

P1[12]/

ENET_RXD3/

MCIDAT3/

PCAP0[0]

P1[13]/

ENET_RX_DV

P1[16]/

ENET_MDC

P1[17]/

ENET_MDIO

190

188

186

163

157

147

P1[14]/

ENET_RX_ER

184

P1[15]/

ENET_REF_CLK/

ENET_RX_CLK

182

180

178

A14

A16

I/O

Type Description

I/O P1[7] — General purpose digital input/output pin.

ENET_COL — Ethernet Collision detect (MII interface) (LPC2460 only).

MCIDAT1 — Data line 1 for SD/MMC interface.

PWM0[5] — Pulse Width Modulator 0, output 5.

P1[8] — General purpose digital input/output pin.

I/O

ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid

(RMII interface)/ Ethernet Carrier Sense (MII interface) (LPC2460 only).

P1[9] — General purpose digital input/output pin.

ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface)

(LPC2460 only).

I/O

P1[10] — General purpose digital input/output pin.

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface)

(LPC2460 only).

P1[11] — General purpose digital input/output pin.

ENET_RXD2 — Ethernet Receive Data 2 (MII interface) (LPC2460 only).

MCIDAT2 — Data line 2 for SD/MMC interface.

PWM0[6] — Pulse Width Modulator 0, output 6.

P1[12] — General purpose digital input/output pin.

ENET_RXD3 — Ethernet Receive Data (MII interface) (LPC2460 only).

MCIDAT3 — Data line 3 for SD/MMC interface.

PCAP0[0] — Capture input for PWM0, channel 0.

P1[13] — General purpose digital input/output pin.

ENET_RX_DV — Ethernet Receive Data Valid (MII interface)

(LPC2460 only).

I/O

P1[14] — General purpose digital input/output pin.

ENET_RX_ER — Ethernet receive error (RMII/MII interface)

(LPC2460 only).

P1[15] — General purpose digital input/output pin.

ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock

(RMII interface)/ Ethernet Receive Clock (MII interface) (LPC2460 only).

P1[16] — General purpose digital input/output pin.

ENET_MDC — Ethernet MIIM clock (LPC2460 only).

P1[17] — General purpose digital input/output pin.

ENET_MDIO — Ethernet MIIM data input and output (LPC2460 only).

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

14 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol Pin

66 [1]

P1[18]/

USB_UP_LED1/

PWM1[1]/

CAP1[0]

Ball

P1[19]/

USB_TX_E1/

USB_PPWR1/

CAP1[1]

P1[20]/

USB_TX_DP1/

PWM1[2]/SCK0

P1[21]/

USB_TX_DM1/

PWM1[3]/SSEL0

P1[22]/

USB_RCV1/

USB_PWRD1/

MAT1[0]

P1[23]/

USB_RX_DP1/

PWM1[4]/MISO0

P1[24]/

USB_RX_DM1/

PWM1[5]/MOSI0

P1[25]/

USB_LS1/

USB_HSTEN1/

MAT1[1]

T10

I/O

Type Description

I/O P1[18] — General purpose digital input/output pin.

O USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when host is enabled and detects activity on the bus.

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

CAP1[0] — Capture input for Timer 1, channel 0.

P1[19] — General purpose digital input/output pin.

USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).

USB_PPWR1 — Port Power enable signal for USB port 1.

CAP1[1] — Capture input for Timer 1, channel 1.

P1[20] — General purpose digital input/output pin.

USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

SCK0 — Serial clock for SSP0.

P1[21] — General purpose digital input/output pin.

USB_TX_DM1 — D

 transmit data for USB port 1 (OTG transceiver).

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

SSEL0 — Slave Select for SSP0.

P1[22] — General purpose digital input/output pin.

USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).

USB_PWRD1 — Power Status for USB port 1 (host power switch).

MAT1[0] — Match output for Timer 1, channel 0.

P1[23] — General purpose digital input/output pin.

USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

MISO0 — Master In Slave Out for SSP0.

P1[24] — General purpose digital input/output pin.

USB_RX_DM1 — D

 receive data for USB port 1 (OTG transceiver).

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

MOSI0 — Master Out Slave in for SSP0.

P1[25] — General purpose digital input/output pin.

USB_LS1 — Low-speed status for USB port 1 (OTG transceiver).

USB_HSTEN1 — Host Enabled status for USB port 1.

MAT1[1] — Match output for Timer 1, channel 1.

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

15 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol Pin

82 [1]

P1[26]/

USB_SSPND1/

PWM1[6]/

CAP0[0]

Ball

R10 [1]

88 [1]

T12

P1[27]/

USB_INT1/

USB_OVRCR1/

CAP0[1]

P1[28]/

USB_SCL1/

PCAP1[0]/

MAT0[0]

P1[29]/

USB_SDA1/

PCAP1[1]/

MAT0[1]

P1[30]/

USB_PWRD2/

BUS

/AD0[4]

P1[31]/

USB_OVRCR2/

SCK1/AD0[5]

P2[0] to P2[31]

P2[0]/PWM1[1]/

TXD1/

TRACECLK

P2[1]/PWM1[2]/

RXD1/

PIPESTAT0

P2[2]/PWM1[3]/

CTS1/

PIPESTAT1

154

152

150

T13

B17

E14

I/O

Type Description

I/O P1[26] — General purpose digital input/output pin.

O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver).

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

CAP0[0] — Capture input for Timer 0, channel 0.

P1[27] — General purpose digital input/output pin.

USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).

USB_OVRCR1 — USB port 1 Over-Current status.

CAP0[1] — Capture input for Timer 0, channel 1.

P1[28] — General purpose digital input/output pin.

USB_SCL1 — USB port 1 I 2 C-bus serial clock (OTG transceiver).

PCAP1[0] — Capture input for PWM1, channel 0.

MAT0[0] — Match output for Timer 0, channel 0.

P1[29] — General purpose digital input/output pin.

USB_SDA1 — USB port 1 I 2 C-bus serial data (OTG transceiver).

PCAP1[1] — Capture input for PWM1, channel 1.

MAT0[1] — Match output for Timer 0, channel 0.

P1[30] — General purpose digital input/output pin.

USB_PWRD2 — Power Status for USB port 2.

BUS

— Monitors the presence of USB bus power.

Note: This signal must be HIGH for USB reset to occur.

AD0[4] — A/D converter 0, input 4.

P1[31] — General purpose digital input/output pin.

USB_OVRCR2 — Over-Current status for USB port 2.

SCK1 — Serial Clock for SSP1.

AD0[5] — A/D converter 0, input 5.

Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect block.

P2[0] — General purpose digital input/output pin.

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

TXD1 — Transmitter output for UART1.

TRACECLK — Trace Clock.

P2[1] — General purpose digital input/output pin.

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

RXD1 — Receiver input for UART1.

PIPESTAT0 — Pipeline Status, bit 0.

P2[2] — General purpose digital input/output pin.

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

CTS1 — Clear to Send input for UART1.

PIPESTAT1 — Pipeline Status, bit 1.

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

16 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P2[3]/PWM1[4]/

DCD1/

PIPESTAT2

P2[4]/PWM1[5]/

DSR1/

TRACESYNC

P2[5]/PWM1[6]/

DTR1/

TRACEPKT0

P2[6]/PCAP1[0]/

RI1/TRACEPKT1

P2[7]/RD2/

RTS1/

TRACEPKT2

P2[8]/TD2/

TXD2/

TRACEPKT3

P2[9]/

USB_CONNECT1/

RXD2/

EXTIN0

P2[10]/EINT0

P2[11]/EINT1/

MCIDAT1/

I2STX_CLK

Pin

144

142

140

138

136

134

132

110

108

[6]

Ball

E16

D17

F16

E17

G16

T17

I/O

Type Description

I/O P2[3] — General purpose digital input/output pin.

O PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I/O

DCD1 — Data Carrier Detect input for UART1.

PIPESTAT2 — Pipeline Status, bit 2.

P2[4] — General purpose digital input/output pin.

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

DSR1 — Data Set Ready input for UART1.

TRACESYNC — Trace Synchronization.

P2[5] — General purpose digital input/output pin.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

DTR1 — Data Terminal Ready output for UART1.

TRACEPKT0 — Trace Packet, bit 0.

P2[6] — General purpose digital input/output pin.

PCAP1[0] — Capture input for PWM1, channel 0.

I/O

RI1 — Ring Indicator input for UART1.

TRACEPKT1 — Trace Packet, bit 1.

P2[7] — General purpose digital input/output pin.

RD2 — CAN2 receiver input (LPC2460 only).

RTS1 — Request to Send output for UART1.

TRACEPKT2 — Trace Packet, bit 2.

P2[8] — General purpose digital input/output pin.

TD2 — CAN2 transmitter output (LPC2460 only).

TXD2 — Transmitter output for UART2.

TRACEPKT3 — Trace Packet, bit 3.

P2[9] — General purpose digital input/output pin.

USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an external 1.5 k

 resistor under the software control. Used with the SoftConnect USB feature.

RXD2 — Receiver input for UART2.

EXTIN0 — External Trigger Input.

P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset.

EINT0 — External interrupt 0 input.

P2[11] — General purpose digital input/output pin.

EINT1 — External interrupt 1 input.

MCIDAT1 — Data line 1 for SD/MMC interface.

I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2 S-bus

specification.

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

17 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol Pin

106

[6]

P2[12]/EINT2/

MCIDAT2/

I2STX_WS

Ball

N14 [6]

P2[13]/EINT3/

MCIDAT3/

I2STX_SDA

P2[14]/CS2/

CAP2[0]/SDA1

P2[15]/CS3/

CAP2[1]/SCL1

P2[16]/CAS

P2[17]/RAS

P2[18]/

CLKOUT0

P2[19]/

CLKOUT1

P2[20]/DYCS0

P2[21]/DYCS1

P2[22]/DYCS2/

CAP3[0]/SCK0

P2[23]/DYCS3/

CAP3[1]/SSEL0

P2[24]/

CKEOUT0

LPC2420_60

Product data sheet

102

T16

P13

I/O

Type Description

I/O P2[12] — General purpose digital input/output pin.

EINT2 — External interrupt 2 input.

I/O

MCIDAT2 — Data line 2 for SD/MMC interface.

I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2 S-bus

specification.

P2[13] — General purpose digital input/output pin.

EINT3 — External interrupt 3 input.

MCIDAT3 — Data line 3 for SD/MMC interface.

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2 S-bus

specification.

P2[14] — General purpose digital input/output pin.

CS2 — LOW active Chip Select 2 signal.

CAP2[0] — Capture input for Timer 2, channel 0.

SDA1 — I 2 C1 data input/output (this is not an open-drain pin).

P2[15] — General purpose digital input/output pin.

CS3 — LOW active Chip Select 3 signal.

CAP2[1] — Capture input for Timer 2, channel 1.

SCL1 — I 2 C1 clock input/output (this is not an open-drain pin).

P2[16] — General purpose digital input/output pin.

CAS — LOW active SDRAM Column Address Strobe.

P2[17] — General purpose digital input/output pin.

RAS — LOW active SDRAM Row Address Strobe.

P2[18] — General purpose digital input/output pin.

CLKOUT0 — SDRAM clock 0.

P2[19] — General purpose digital input/output pin.

CLKOUT1 — SDRAM clock 1.

P2[20] — General purpose digital input/output pin.

DYCS0 — SDRAM chip select 0.

P2[21] — General purpose digital input/output pin.

DYCS1 — SDRAM chip select 1.

P2[22] — General purpose digital input/output pin.

DYCS2 — SDRAM chip select 2.

CAP3[0] — Capture input for Timer 3, channel 0.

SCK0 — Serial clock for SSP0.

P2[23] — General purpose digital input/output pin.

DYCS3 — SDRAM chip select 3.

CAP3[1] — Capture input for Timer 3, channel 1.

SSEL0 — Slave Select for SSP0.

P2[24] — General purpose digital input/output pin.

CKEOUT0 — SDRAM clock enable 0.

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

18 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P2[25]/

CKEOUT1

Pin

54 [1]

Ball

57 [1] T4 [1]

P2[26]/

CKEOUT2/

MAT3[0]/MISO0

P2[27]/

CKEOUT3/

MAT3[1]/MOSI0

P2[28]/

DQMOUT0

P2[29]/

DQMOUT1

P2[30]/

DQMOUT2/

MAT3[2]/SDA2

P2[31]/

DQMOUT3/

MAT3[3]/SCL2

P3[0] to P3[31]

P3[0]/D0

P3[1]/D1

P3[2]/D2

P3[3]/D3

P3[4]/D4

P3[5]/D5

P3[6]/D6

P3[7]/D7

LPC2420_60

Product data sheet

197

201

207

F2 [1]

I/O

Type Description

I/O P2[25] — General purpose digital input/output pin.

I/O

CKEOUT1 — SDRAM clock enable 1.

P2[26] — General purpose digital input/output pin.

CKEOUT2 — SDRAM clock enable 2.

MAT3[0] — Match output for Timer 3, channel 0.

MISO0 — Master In Slave Out for SSP0.

P2[27] — General purpose digital input/output pin.

CKEOUT3 — SDRAM clock enable 3.

MAT3[1] — Match output for Timer 3, channel 1.

MOSI0 — Master Out Slave In for SSP0.

P2[28] — General purpose digital input/output pin.

DQMOUT0 — Data mask 0 used with SDRAM and static devices.

P2[29] — General purpose digital input/output pin.

DQMOUT1 — Data mask 1 used with SDRAM and static devices.

P2[30] — General purpose digital input/output pin.

DQMOUT2 — Data mask 2 used with SDRAM and static devices.

MAT3[2] — Match output for Timer 3, channel 2.

SDA2 — I 2 C2 data input/output (this is not an open-drain pin).

P2[31] — General purpose digital input/output pin.

DQMOUT3 — Data mask 3 used with SDRAM and static devices.

MAT3[3] — Match output for Timer 3, channel 3.

SCL2 — I 2 C2 clock input/output (this is not an open-drain pin).

Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin Connect block.

P3[0] — General purpose digital input/output pin.

D0 — External memory data line 0.

P3[1] — General purpose digital input/output pin.

D1 — External memory data line 1.

P3[2] — General purpose digital input/output pin.

D2 — External memory data line 2.

P3[3] — General purpose digital input/output pin.

D3 — External memory data line 3.

P3[4] — General purpose digital input/output pin.

D4 — External memory data line 4.

P3[5] — General purpose digital input/output pin.

D5 — External memory data line 5.

P3[6] — General purpose digital input/output pin.

D6 — External memory data line 6.

P3[7] — General purpose digital input/output pin.

D7 — External memory data line 7.

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P3[8]/D8

P3[9]/D9

P3[10]/D10

P3[11]/D11

P3[12]/D12

P3[13]/D13

P3[14]/D14

P3[15]/D15

P3[16]/D16/

PWM0[1]/TXD1

P3[17]/D17/

PWM0[2]/RXD1

P3[18]/D18/

PWM0[3]/CTS1

P3[19]/D19/

PWM0[4]/DCD1

P3[20]/D20/

PWM0[5]/DSR1

LPC2420_60

Product data sheet

Pin

191

199

205

208

137

143

151

161

167

Ball

F17

F15

B14

A13

I/O

Type Description

I/O P3[8] — General purpose digital input/output pin.

I/O

D8 — External memory data line 8.

P3[9] — General purpose digital input/output pin.

D9 — External memory data line 9.

P3[10] — General purpose digital input/output pin.

I/O

D10 — External memory data line 10.

P3[11] — General purpose digital input/output pin.

D11 — External memory data line 11.

P3[12] — General purpose digital input/output pin.

D12 — External memory data line 12.

P3[13] — General purpose digital input/output pin.

D13 — External memory data line 13.

P3[14] — General purpose digital input/output pin.

D14 — External memory data line 14. On POR, this pin serves as the

BOOT0 pin.

P3[15] — General purpose digital input/output pin.

D15 — External memory data line 15. On POR, this pin serves as the

BOOT1 pin.

BOOT[1:0] = 00 selects 8-bit external memory on CS1.

BOOT[1:0] = 01 is reserved. Do not use.

BOOT[1:0] = 10 selects 32-bit external memory on CS1.

BOOT[1:0] = 11 selects 16-bit external memory on CS1.

P3[16] — General purpose digital input/output pin.

D16 — External memory data line 16.

PWM0[1] — Pulse Width Modulator 0, output 1.

TXD1 — Transmitter output for UART1.

P3[17] — General purpose digital input/output pin.

D17 — External memory data line 17.

PWM0[2] — Pulse Width Modulator 0, output 2.

RXD1 — Receiver input for UART1.

P3[18] — General purpose digital input/output pin.

D18 — External memory data line 18.

PWM0[3] — Pulse Width Modulator 0, output 3.

CTS1 — Clear to Send input for UART1.

P3[19] — General purpose digital input/output pin.

D19 — External memory data line 19.

PWM0[4] — Pulse Width Modulator 0, output 4.

DCD1 — Data Carrier Detect input for UART1.

P3[20] — General purpose digital input/output pin.

D20 — External memory data line 20.

PWM0[5] — Pulse Width Modulator 0, output 5.

DSR1 — Data Set Ready input for UART1.

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P3[21]/D21/

PWM0[6]/DTR1

Pin

175

Ball

C10 [1]

P3[22]/D22/

PCAP0[0]/RI1

P3[23]/D23/

CAP0[0]/

PCAP1[0]

P3[24]/D24/

CAP0[1]/

PWM1[1]

P3[25]/D25/

MAT0[0]/

PWM1[2]

P3[26]/D26/

MAT0[1]/

PWM1[3]

P3[27]/D27/

CAP1[0]/

PWM1[4]

P3[28]/D28/

CAP1[1]/

PWM1[5]

P3[29]/D29/

MAT1[0]/

PWM1[6]

P3[30]/D30/

MAT1[1]/

RTS1

195

203

I/O

Type Description

I/O P3[21] — General purpose digital input/output pin.

I/O D21 — External memory data line 21.

I/O

PWM0[6] — Pulse Width Modulator 0, output 6.

DTR1 — Data Terminal Ready output for UART1.

P3[22] — General purpose digital input/output pin.

D22 — External memory data line 22.

PCAP0[0] — Capture input for PWM0, channel 0.

RI1 — Ring Indicator input for UART1.

P3[23] — General purpose digital input/output pin.

D23 — External memory data line 23.

CAP0[0] — Capture input for Timer 0, channel 0.

PCAP1[0] — Capture input for PWM1, channel 0.

P3[24] — General purpose digital input/output pin.

D24 — External memory data line 24.

CAP0[1] — Capture input for Timer 0, channel 1.

PWM1[1] — Pulse Width Modulator 1, output 1.

P3[25] — General purpose digital input/output pin.

D25 — External memory data line 25.

MAT0[0] — Match output for Timer 0, channel 0.

PWM1[2] — Pulse Width Modulator 1, output 2.

P3[26] — General purpose digital input/output pin.

D26 — External memory data line 26.

MAT0[1] — Match output for Timer 0, channel 1.

PWM1[3] — Pulse Width Modulator 1, output 3.

P3[27] — General purpose digital input/output pin.

D27 — External memory data line 27.

CAP1[0] — Capture input for Timer 1, channel 0.

PWM1[4] — Pulse Width Modulator 1, output 4.

P3[28] — General purpose digital input/output pin.

D28 — External memory data line 28.

CAP1[1] — Capture input for Timer 1, channel 1.

PWM1[5] — Pulse Width Modulator 1, output 5.

P3[29] — General purpose digital input/output pin.

D29 — External memory data line 29.

MAT1[0] — Match output for Timer 1, channel 0.

PWM1[6] — Pulse Width Modulator 1, output 6.

P3[30] — General purpose digital input/output pin.

D30 — External memory data line 30.

MAT1[1] — Match output for Timer 1, channel 1.

RTS1 — Request to Send output for UART1.

LPC2420_60

Product data sheet

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P3[31]/D31/

MAT1[2]

P4[0] to P4[31]

P4[0]/A0

P4[1]/A1

P4[2]/A2

P4[3]/A3

P4[4]/A4

P4[5]/A5

P4[6]/A6

P4[7]/A7

P4[8]/A8

P4[9]/A9

P4[10]/A10

P4[11]/A11

P4[12]/A12

P4[13]/A13

P4[14]/A14

P4[15]/A15

P4[16]/A16

Pin

25 [1]

103

107

113

121

127

131

135

145

149

155

159

173

101

Ball

T11

M14

G17

F14

C16

B16

B15

A11

U17

I/O

Type Description

I/O P3[31] — General purpose digital input/output pin.

D31 — External memory data line 31.

I/O

MAT1[2] — Match output for Timer 1, channel 2.

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the Pin Connect block.

P4[0] — ]General purpose digital input/output pin.

A0 — External memory address line 0.

P4[1] — General purpose digital input/output pin.

A1 — External memory address line 1.

P4[2] — General purpose digital input/output pin.

A2 — External memory address line 2.

P4[3] — General purpose digital input/output pin.

A3 — External memory address line 3.

P4[4] — General purpose digital input/output pin.

A4 — External memory address line 4.

P4[5] — General purpose digital input/output pin.

A5 — External memory address line 5.

P4[6] — General purpose digital input/output pin.

A6 — External memory address line 6.

P4[7] — General purpose digital input/output pin.

A7 — External memory address line 7.

P4[8] — General purpose digital input/output pin.

A8 — External memory address line 8.

P4[9] — General purpose digital input/output pin.

A9 — External memory address line 9.

P4[10] — General purpose digital input/output pin.

A10 — External memory address line 10.

P4[11] — General purpose digital input/output pin.

A11 — External memory address line 11.

P4[12] — General purpose digital input/output pin.

A12 — External memory address line 12.

P4[13] — General purpose digital input/output pin.

A13 — External memory address line 13.

P4[14] — General purpose digital input/output pin.

A14 — External memory address line 14.

P4[15] — General purpose digital input/output pin.

A15 — External memory address line 15.

P4[16] — General purpose digital input/output pin.

A16 — External memory address line 16.

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Product data sheet

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P4[17]/A17

P4[18]/A18

P4[19]/A19

P4[20]/A20/

SDA2/SCK1

P4[21]/A21/

SCL2/SSEL1

P4[22]/A22/

TXD2/MISO1

P4[23]/A23/

RXD2/MOSI1

P4[24]/OE

P4[25]/WE

P4[26]/BLS0

P4[27]/BLS1

P4[28]/BLS2/

MAT2[0]/TXD3

P4[29]/BLS3/

MAT2[1]/RXD3

P4[30]/CS0

Pin

104

105

111

109

115

123

129

183

179

119

139

170

176

187

Ball

P14

P15

P16

M15

K14

G15

B10

I/O

Type Description

I/O P4[17] — General purpose digital input/output pin.

I/O

A17 — External memory address line 17.

P4[18] — General purpose digital input/output pin.

A18 — External memory address line 18.

P4[19] — General purpose digital input/output pin.

A19 — External memory address line 19.

P4[20] — General purpose digital input/output pin.

A20 — External memory address line 20.

SDA2 — I 2 C2 data input/output (this is not an open-drain pin).

SCK1 — Serial Clock for SSP1.

P4[21] — General purpose digital input/output pin.

A21 — External memory address line 21.

SCL2 — I 2 C2 clock input/output (this is not an open-drain pin).

SSEL1 — Slave Select for SSP1.

P4[22] — General purpose digital input/output pin.

A22 — External memory address line 22.

TXD2 — Transmitter output for UART2.

MISO1 — Master In Slave Out for SSP1.

P4[23] — General purpose digital input/output pin.

A23 — External memory address line 23.

RXD2 — Receiver input for UART2.

MOSI1 — Master Out Slave In for SSP1.

P4[24] — General purpose digital input/output pin.

OE — LOW active Output Enable signal.

P4[25] — General purpose digital input/output pin.

WE — LOW active Write Enable signal.

P4[26] — General purpose digital input/output pin.

BLS0 — LOW active Byte Lane select signal 0.

P4[27] — General purpose digital input/output pin.

BLS1 — LOW active Byte Lane select signal 1.

P4 [28] — General purpose digital input/output pin.

BLS2 — LOW active Byte Lane select signal 2.

MAT2[0] — Match output for Timer 2, channel 0.

TXD3 — Transmitter output for UART3.

P4[29] — General purpose digital input/output pin.

BLS3 — LOW active Byte Lane select signal 3.

MAT2[1] — Match output for Timer 2, channel 1.

RXD3 — Receiver input for UART3.

P4[30] — General purpose digital input/output pin.

CS0 — LOW active Chip Select 0 signal.

LPC2420_60

Product data sheet

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol

P4[31]/CS1

ALARM

USB_D

DBGEN

TDO

TDI

TMS

TRST

TCK

RTCK

2

RSTOUT

RESET

XTAL1

XTAL2

RTCX1

RTCX2

SSIO

SSCORE

SSA

DD(3V3) n.c.

Pin

193

206

Ball

33, 63,

77, 93,

114,

133, 148,

169, 189,

200

32, 84,

172

22 [7]

L3, T5,

R9,

P12,

N16,

H14,

E15, A12,

B6, A2 [7]

K4, P10,

D12 [7]

15, 60,

71, 89,

112,

125, 146,

165,

181,

198

30, 117,

141

G3,

P6, P8,

U13,

P17,

K16,

C17,

B13,

C9,

J4, L14,

G14

Type Description

I/O P4[31] — General purpose digital input/output pin.

I/O

CS1 — LOW active Chip Select 1 signal.

ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated.

USB_D

2 — USB port 2 bidirectional D line.

DBGEN — JTAG interface control signal. Also used for boundary scanning.

TDO — Test data out for JTAG interface.

TDI — Test data in for JTAG interface.

TMS — Test Mode Select for JTAG interface.

I/O

TRST — Test Reset for JTAG interface.

TCK — Test Clock for JTAG interface. This clock must be slower than

1 ⁄

of the CPU clock (CCLK) for the JTAG interface to operate.

RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET is LOW enables ETM pins

(P2[9:0]) to operate as Trace port after reset.

RSTOUT — This is a 3.3 V pin. LOW on this pin indicates

LPC2420/2460 being in Reset state.

external reset input: A LOW on this pin resets the device, causing

I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator amplifier.

Input to the RTC oscillator circuit.

Output from the RTC oscillator circuit.

ground: 0 V reference for the digital I/O pins.

ground: 0 V reference for the core.

analog ground: 0 V reference. This should nominally be the same voltage as V

SSIO

SSCORE

, but should be isolated to minimize noise and error.

3.3 V supply voltage: This is the power supply voltage for the I/O ports.

not connected pins: These pins must be left unconnected (floating).

LPC2420_60

Product data sheet

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 4.

Pin description …continued

Symbol Pin Ball

DD(DCDC)(3V3)

DDA

26, 86,

174

H4, P11,

VREF

VBAT

typical USB interfacing solutions can be found in Section 14.2 “Suggested USB interface solutions” on page 69

Type Description

3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip DC-to-DC converter.

analog 3.3 V pad supply voltage: This should be nominally the same voltage as V

DD(3V3)

but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC.

ADC reference: This should be nominally the same voltage as

DD(3V3)

but should be isolated to minimize noise and error. The level on this pin is used as a reference for ADC and DAC.

RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O pad, compatible with I 2 C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I 2 C-bus is floating and does not disturb the I 2 C-bus lines. Open-drain configuration applies to all functions on this pin.

[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7] Pad provides special analog functionality.

[8] This pin has a built-in pull-up resistor.

[9] This pin has no built-in pull-up and no built-in pull-down resistor.

[10] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[12] If the RTC is not used, these pins can be left floating.

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LPC2420/2460

Flashless 16-bit/32-bit microcontroller

LPC2420_60

Product data sheet

7.1 Architectural overview

The LPC2420/2460 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions.

The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order.

The LPC2460 only implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the VIC, GPDMA controller, and EMC.

The second AHB (LPC2460 only), referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB

ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the

AHB address space. Lower speed peripheral functions are connected to the APB. The

AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a

2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• the standard 32-bit ARM set

• a 16-bit Thumb set

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Flashless 16-bit/32-bit microcontroller

The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance.

7.2 On-chip SRAM

The LPC2420/2460 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller (LPC2460 only) and a

16 kB SRAM associated with the second AHB can be used both for data and code storage, too. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply.

7.3 Memory map

The LPC2420/2460 memory map incorporates several distinct regions as shown in

Table 5 and

Figure 4 .

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either boot ROM or SRAM (see

Section 7.25.6

Table 5.

LPC2420/2460 memory usage and details

Address range General use Address range details and description

0x3FFF C000 to 0x3FFF FFFF fast GPIO registers 0x0000 0000 to

0x3FFF FFFF

fast I/O

0x4000 0000 to

0x7FFF FFFF on-chip RAM 0x4000 0000 to 0x4000 FFFF RAM (64 kB)

0x7FE0 0000 to 0x7FE0 3FFF Ethernet RAM (16 kB)

(LPC2460 only)

0x7FD0 0000 to 0x7FD0 3FFF USB RAM (16 kB)

0x8000 0000 to

0xDFFF FFFF off-chip memory Four static memory banks, 16 MB each

0x8000 0000 to 0x80FF FFFF static memory bank 0

0x8100 0000 to 0x81FF FFFF static memory bank 1

0x8200 0000 to 0x82FF FFFF static memory bank 2

0x8300 0000 to 0x83FF FFFF static memory bank 3

Four dynamic memory banks, 256 MB each

0xA000 0000 to 0xAFFF FFFF dynamic memory bank 0

0xB000 0000 to 0xBFFF FFFF dynamic memory bank 1

0xC000 0000 to 0xCFFF FFFF dynamic memory bank 2

0xD000 0000 to 0xDFFF FFFF dynamic memory bank 3

0xE000 0000 to

0xEFFF FFFF

APB peripherals 36 peripheral blocks, 16 kB each

0xF000 0000 to

0xFFFF FFFF

AHB peripherals

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4.0 GB

3.75 GB

3.5 GB

2.0 GB

AHB PERIPHERALS

APB PERIPHERALS

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

0xFFFF FFFF

0xF000 0000

0xE000 0000

EXTERNAL STATIC AND DYNAMIC MEMORY

0x8000 0000

0x7FFF FFFF

BOOT ROM

RESERVED ADDRESS SPACE

1.0 GB

ON-CHIP STATIC RAM

SPECIAL REGISTERS

RESERVED ADDRESS SPACE

0x4000 0000

0x3FFF FFFF

0x3FFF 8000

0.0 GB

002aad316

0x0000 0000

Fig 4.

LPC2420/2460 memory map

LPC2420_60

Product data sheet

7.4 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast

Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ

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Flashless 16-bit/32-bit microcontroller service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority. When more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered VIC channel will be serviced first.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register.

7.4.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from port 0 and/or port 2 will be combined with the EINT3 interrupt requests.

7.5 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.6 External memory controller

The LPC2420/2460 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash.

In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.

7.6.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16/32 data and 24 address lines wide static memory support.

• 16 bit and 32 bit wide chip select SDRAM memory support.

• Static memory features include:

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– Asynchronous page mode read

– Programmable Wait States

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

• Four chip selects for synchronous memory and four chip selects for static memory devices.

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2048, 4096, and 8192 row address synchronous memory parts.

That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device.

• Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.7 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2420/2460 peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master.

7.7.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 16 kB SRAM, external memory, and peripherals such as the SD/MMC, two SSPs, and the I 2 S interface.

• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

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• One AHB master for transferring data. This interface transfers data when a DMA request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral.

• Internal four-word FIFO per channel.

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

• An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins.

LPC2420/2460 use accelerated GPIO functions:

• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an analog input/output can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake the chip up from Power-down mode.

7.8.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy port 0 and port 1 registers appearing at the original addresses on the APB.

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7.9 Ethernet (LPC2460 only)

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2420/2460 takes place on a different AHB subsystem, effectively separating

Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Media

Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media

Independent Interface Management (MIIM) serial bus.

7.9.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

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– Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through standard MII or RMII interface.

– PHY register access is available via the MIIM interface.

7.10 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller.

The LPC2420/2460 USB interface includes a device, host, and OTG controller. Details on

7.10.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB

RAM.

7.10.1.1

Features

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, LPC2420/2460 can enter one of the reduced power modes and wake up on USB activity.

• Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.

• Allows dynamic switching between CPU-controlled and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

7.10.2 USB host controller

The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the OHCI specification.

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7.10.2.1

Features

• OHCI compliant.

• Two downstream ports.

• Supports per-port power switching.

7.10.3 USB OTG controller

USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to

USB peripherals.

The OTG controller integrates the host controller, device controller, and a master-only

I 2 C-bus interface to implement OTG dual-role device functionality. The dedicated I 2 C-bus interface controls an external OTG transceiver.

7.10.3.1

Features

• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

1.0a.

• Hardware support for Host Negotiation Protocol (HNP).

• Includes a programmable timer required for HNP and Session Request Protocol

(SRP).

• Supports any OTG transceiver compliant with the OTG Transceiver Specification

(CEA-2011), Rev. 1.0.

7.11 CAN controller and acceptance filters (LPC2460 only)

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

7.11.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses.

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• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.

• FullCAN messages can generate interrupts.

7.12 10-bit ADC

The LPC2420/2460 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.

7.12.1 Features

• 10-bit successive approximation ADC

• Input multiplexing among 8 pins

• Power-down mode

• Measurement range 0 V to V i(VREF)

• 10-bit conversion time

 2.44 s

• Burst conversion mode for single or multiple inputs

• Optional conversion on transition of input pin or Timer Match signal

• Individual result registers for each ADC channel to reduce interrupt overhead

7.13 10-bit DAC

The DAC allows the LPC2420/2460 to generate a variable analog output. The maximum output value of the DAC is V i(VREF)

7.13.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

7.14 UARTs

The LPC2420/2460 contains four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.14.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.

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• Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS).

• UART3 includes an IrDA mode to support infrared communication.

7.15 SPI serial I/O controller

The LPC2420/2460 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.

7.15.1 Features

• Compliant with SPI specification

• Synchronous, Serial, Full Duplex Communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

7.16 SSP serial I/O controller

The LPC2420/2460 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.16.1 Features

• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave mode) of the input clock rate

• DMA transfers supported by GPDMA

7.17 SD/MMC card interface

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification

Version 2.11.

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7.17.1 Features

• The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer.

• Conforms to Multimedia Card Specification v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

• Can be used as a multimedia card bus or a secure digital memory card bus host. The

SD/MMC can be connected to several multimedia cards or a single secure digital memory card.

• DMA supported through the GPDMA controller.

7.18 I

C-bus serial I/O controller

The LPC2420/2460 contains three I 2 C-bus controllers.

The I 2 C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2 C-bus is a multi-master bus and can be controlled by more than one bus master connected to it.

The I 2 C-bus implemented in LPC2420/2460 supports bit rates up to 400 kbit/s (Fast

I 2 C-bus).

7.18.1 Features

• I 2 C0 is a standard I 2 C compliant bus interface with open-drain pins.

• I 2 C1 and I 2 C2 use standard I/O pins and do not support powering off of individual devices connected to the same bus lines.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.

• The I 2 C-bus can be used for test and diagnostic purposes.

7.19 I 2 S-bus serial I/O controllers

The I 2 S-bus provides a standard communication interface for digital audio applications.

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The I 2 S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I 2 S connection has one master, which is always the master, and one slave. The I 2 S interface on the LPC2420/2460 provides a separate transmit and receive channel, each of which can operate as either a master or a slave.

7.19.1 Features

• The interface has separate input/output channels each of which can operate in master or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,

48) kHz.

• Configurable word select period in master mode (separately for I 2 S-bus input and output).

• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block.

• Controls include reset, stop and mute options separately for I 2 S-bus input and I 2 S-bus output.

7.20 General purpose 32-bit timers/external event counters

The LPC2420/2460 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.20.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

• Counter or Timer operation.

• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

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– Do nothing on match.

7.21 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2420/2460. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers.

The PWM function is in addition to these features and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.

Two match registers can be used to provide a single edge controlled PWM output. A dedicated match register controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, a dedicated match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

7.21.1 Features

• LPC2420/2460 has two PWMs with the same operational features. These may be operated in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave for this use.

• Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source).

• Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.

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• Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.22 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

7.22.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (T cy(WDCLK)

 256  4) to (T cy(WDCLK) multiples of T cy(WDCLK)

 4.

 2

 4) in

• The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the

Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability.

7.23 RTC and battery RAM

The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down and Deep power-down modes. On the

LPC2420/2460, the RTC can be clocked by a separate 32.768 kHz oscillator or by a programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device.

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The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation.

7.23.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.

• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

• An alarm output pin is included to assist in waking up when the chip has had power removed to all functions except the RTC and Battery RAM.

• Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. This enhancement enables the RTC to be used as a System Timer.

• 2 kB data SRAM powered by VBAT.

• RTC and Battery RAM power supply is isolated from the rest of the chip.

7.24 Clocking and power control

7.24.1 Crystal oscillators

The LPC2420/2460 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU.

Following reset, the LPC2420/2460 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

7.24.1.1

Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy.

Upon power-up or any chip reset, the LPC2420/2460 uses the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.24.1.2

Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using the

PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the

PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The

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PCLK. Refer to Section 7.24.2

for additional information.

7.24.1.3

RTC oscillator

The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the

RTC oscillator can be used to drive the PLL and the CPU.

7.24.2 PLL

The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and the USB block.

The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value

‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency.

The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source.

7.24.3 Wake-up timer

The LPC2420/2460 begins operation at power-up and when awakened from Power-down and Deep-power down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down and Deep power-down modes, any wake-up of the processor from Power-down modes makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit

Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V

DD(3V3)

ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

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7.24.4 Power control

The LPC2420/2460 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and

Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control.

The LPC2420/2460 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM.

7.24.4.1

Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

7.24.4.2

Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The

32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and

USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value.

On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconfigure the PLL and clock dividers accordingly.

7.24.4.3

Power-down mode

Power-down mode does everything that Sleep mode does but also turns off the IRC oscillator.

On the wake-up from Power-down mode, if the IRC was used before entering

Power-down mode, it will take IRC 60

s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. The customers need to reconfigure the PLL and clock dividers accordingly after a wake-up from Power-down mode.

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7.24.4.4

Deep power-down mode

Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off. This produces the lowest possible power consumption without removing power from the entire chip. Since the Deep power-down mode shuts down the on-chip logic power supply, there is no register or memory retention, and resumption of operation involves the same activities as a full chip reset.

If power is supplied to the LPC2420/2460 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset.

While in Deep power-down mode, external device power may be removed. In this case, the LPC2420/2460 will start up when external power is restored.

Essential data may be retained through Deep power-down mode (or through complete powering off of the chip) by storing data in the Battery RAM, as long as the external power to the VBAT pin is maintained.

7.24.4.5

Power domains

The LPC2420/2460 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery

RAM.

On the LPC2420/2460, I/O pads are powered by the 3.3 V (V

DD(3V3)

) pins, while the

DD(DCDC)(3V3)

pins power the on-chip DC-to-DC converter which in turn provides power to the CPU and most of the peripherals.

Although both the I/O pad ring and the core require a 3.3 V supply, different powering schemes can be used depending on the actual application requirements.

The first option assumes that power consumption is not a concern and the design ties the

DD(3V3)

and V

DD(DCDC)(3V3)

pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (V

DD(3V3)

) and a dedicated 3.3 V supply for the CPU (V

DD(DCDC)(3V3)

). Having the on-chip DC-DC converter powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation.

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7.25 System control

7.25.1 Reset

Reset has four sources on the LPC2420/2460: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in

Section 7.24.3 “Wake-up timer”

), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, and a fixed number of clocks have passed.

Once the internal reset is removed, all of the processor and peripheral registers have been initialized to predetermined values and the LPC2420/2460 continues with booting from an external static memory.

7.25.2 Boot process

The processor always boots from the off-chip static memory bank 1, executing code from address 0x8100 0000 (see

Table 5 “LPC2420/2460 memory usage and details”

). During the boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled, and the external memory banks 0 and 1 are configured with the same data bus width. The data bus width is determined by the setting of the two boot pins. Unused address pins are configured as GPIO. See

Section 14.1 “Suggested boot memory interface solutions” for

an example of address and data bus interfacing.

Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped.

The user code residing in the external boot memory must be linked to execute from address location 0x8000 0000.

When booting from external memory, the interrupt vectors are mapped to the bottom of the external memory. Once booting is over, the application must map interrupt vectors to the proper domain.

7.25.3 Brownout detection

The LPC2420/2460 includes 2-stage monitoring of the voltage on the V

DD(DCDC)(3V3)

pins.

If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored

Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable

Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register.

The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if this reset source is enabled in software) to inactivate the LPC2420/2460 when the voltage on the V

DD(DCDC)(3V3)

pins falls below 2.65 V. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition.

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7.25.4 AHB

The LPC2460 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, is implemented on LPC2420 as well and includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM.

The second AHB, referred to as AHB2, is implemented on LPC2460 only and includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on

AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the

GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

7.25.5 External interrupt inputs

The LPC2420/2460 includes up to 68 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode.

7.25.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot

ROM, the SRAM, or external memory. This allows code running in different memory spaces to have control of the interrupts.

7.26 Emulation and debugging

The LPC2420/2460 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself.

7.26.1 EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug

Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present on the target system.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The

DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core.

The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic.

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The JTAG clock (TCK) must be slower than 1 ⁄

of the CPU clock (CCLK) for the JTAG interface to operate.

7.26.2 Embedded trace

Since the LPC2420/2460 have significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins.

The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external

Trace Port Analyzer captures the trace information under software debugger control. The trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers.

Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.

7.26.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2420/2460 contain a specific configuration of

RealMonitor software programmed into the on-chip ROM memory.

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Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

DD(3V3)

Parameter supply voltage (3.3 V)

Conditions core and external rail

DD(DCDC)(3V3)

DC-to-DC converter supply voltage

(3.3 V)

DDA

V i(VBAT)

V i(VREF)

IA analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREF analog input voltage for the RTC

I input voltage on ADC related pins

5 V tolerant I/O pins; only valid when the V

DD(3V3) supply voltage is present other I/O pins

Min

3.0

0.5

Max

3.6

+4.6

+5.1

+6.0

Unit

V stg tot(pack)

ESD supply current ground current per supply pin per ground pin storage temperature non-operating total power dissipation (per package) based on package heat transfer, not device power consumption electrostatic discharge voltage human body model; all pins

0.5

65

2500

DD(3V3)

0.5

100

+150

1.5

+2500

V mA mA

C

[1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SSIO

SSCORE unless otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

 series resistor.

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The average chip junction temperature, T j

(

C), can be calculated using the following equation:

T j

= T amb







– a



• T amb

= ambient temperature (

C),

• R th(j-a)

= the package junction-to-ambient thermal resistance (

C/W)

• P

= sum of internal and I/O power dissipation

(1)

The internal power dissipation is the product of I

and V

. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.

Table 7.

Thermal characteristics

= 3.0 V to 3.6 V; T amb





C to +85



C unless otherwise specified;

Symbol Parameter Conditions

T j(max) maximum junction temperature

Min

Typ Max

125

Unit

C

Table 8.

Thermal resistance value (C/W): ±15 %

= 3.0 V to 3.6 V; T amb





C to +85



C unless otherwise specified;

LQFP208

ja

JEDEC (4.5 in

 4 in)

TFBGA208

ja

JEDEC (4.5 in

 4 in)

0 m/s 27.4

0 m/s

1 m/s 25.7

1 m/s

24.4

2.5 m/s

Single-layer (4.5 in

 3 in)

0 m/s

1 m/s

2.5 m/s

jc

jb

35.4

31.2

29.2

8.8

15.4

2.5 m/s

8-layer (4.5 in

 3 in)

0 m/s

1 m/s

2.5 m/s

jc

jb

34.9

30.9

8.3

13.6

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10. Static characteristics

Table 9.

Static characteristics

T amb





C to +85



C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min

DD(3V3)

DD(DCDC)(3V3) supply voltage (3.3 V) core and external rail 3.0

3.0

DDA

V i(VBAT)

DC-to-DC converter supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin

VBAT

3.0

2.0

V i(VREF)

DD(DCDC)act(3V3) input voltage on pin

VREF active mode

DC-to-DC converter supply current (3.3 V)

DD(DCDC)(3V3)

= 3.3 V;

T amb

= 25

C; code while(1){} executed from the on-chip

SRAM; no peripherals enabled; PCLK = CCLK /

CCLK = 12 MHz

2.5

CCLK = 72 MHz

DD(DCDC)pd(3V3)

Power-down mode

DC-to-DC converter supply current (3.3 V)

DD(DCDC)dpd(3V3)

Deep power-down mode DC-to-DC converter supply current (3.3 V)

BATact active mode battery supply current

BAT battery supply current Deep power-down mode

Standard port pins, RESET, RTCK

= 0 V; no pull-up

LOW-level input current

HIGH-level input current

= V

DD(3V3) pull-down

; no

OZ latch

OFF-state output current

I/O latch-up current input voltage output voltage

HIGH-level input voltage

= 0 V; V no pull-up/down

(0.5V

DD(3V3)

) < V

(1.5V

DD(3V3)

);

T j

< 125

C

O pin configured to provide a digital function output active

= V

DD(3V3)

;

2.0

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17.4

66.1

113

Typ [1]

3.3

100

Max

3.6

DDA

5.5

DD(3V3)

V mA mA

A

Unit

A

A mA

A

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Table 9.

Static characteristics …continued

T amb





C to +85



C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min

V hys

LOW-level input voltage hysteresis voltage

HIGH-level output voltage

LOW-level output voltage

4 mA

0.4

DD(3V3)



0.4

HIGH-level output current

= V

DD(3V3)

 0.4 V

4

= 0.4 V

OHS

OLS

LOW-level output current

HIGH-level short-circuit output current

LOW-level short-circuit output current

= 0 V

= V

DDA

[10]

I pd

I pu pull-down current pull-up current

= 5 V

= 0 V

DD(3V3)

< V

< 5 V

[11]

15

[11]

I 2 C-bus pins (P0[27] and P0[28])

0.7V

DD(3V3)

V hys

HIGH-level input voltage

LOW-level input voltage hysteresis voltage

LOW-level output voltage

OLS

= 3 mA input leakage current V

= V

DD(3V3)

= 5 V

[12]

Typ [1]

50

0.05V

DD(3V3)

0.4

Max

0.8

0.4

45

150

85

Unit

V mA mA mA mA

A

0.3V

DD(3V3)

A

Oscillator pins

V i(XTAL1)

0.5

1.8

1.95

V o(XTAL2)

V i(RTCX1)

V o(RTCX2) input voltage on pin

XTAL1 output voltage on pin

XTAL2 input voltage on pin

RTCX1 output voltage on pin

RTCX2

0.5

1.8

1.95

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Table 9.

Static characteristics …continued

T amb





C to +85



C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min

USB pins

BUS

V th(rs)se

C trans

DRV

OFF-state output current bus supply voltage differential input sensitivity voltage

0 V < V

< 3.3 V

(D+)  (D) differential common mode voltage range single-ended receiver switching threshold voltage includes V

range

of 1.5 k

 to 3.6 V

LOW-level output voltage for low-/full-speed

HIGH-level output voltage (driven) for low-/full-speed

of 15 k

 to GND pin to GND transceiver capacitance driver output impedance for driver which is not high-speed capable with 33

 series resistor; steady state drive

0.2

0.8

2.8

[13]

Typ [1]

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages

[2] The RTC typically fails when V i(VBAT)

drops below 1.6 V.

[3] V

DD(DCDC)(3V3)

= 3.3 V; V

DD(3V3)

= 3.3 V; V i(VBAT)

= 3.3 V; T amb

= 25

C.

[4] On pin VBAT.

[5] Including voltage on outputs in 3-state mode.

[6] V

DD(3V3)

supply voltages must be present.

[7] 3-state outputs go into 3-state mode when V

DD(3V3)

is grounded.

[8] Please also see the errata note in errata sheet.

[9] Accounts for 100 mV voltage drop in all supply lines.

[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[11] Minimum condition for V

= 4.5 V, maximum condition for V

= 5.5 V.

[12] To V

SSIO

SSCORE

[13] Includes external resistors of 33

  1 % on D+ and D.

Max

10

5.25

2.5

2.0

0.18

3.5

44.1

V pF



Unit

A

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10.1 Power-down mode

DD(IO)

( μ A)

002aae049

DD(3V3)

= 3.3 V

DD(3V3)

= 3.0 V

−

15 10 35 60 temperature ( ° C)

V i(VBAT)

= V

DD(DCDC)(3V3)

= 3.3 V; T amb

= 25

C.

Fig 5.

I/O maximum supply current I

DD(IO)

versus temperature in Power-down mode

002aae050

BAT

( μ A)

V i(VBAT)

= 3.3 V

V i(VBAT)

= 3.0 V

−

15 10 35 60 temperature ( ° C)

DD(3V3)

= V

DD(DCDC)(3V3)

= 3.3 V; T amb

= 25

C.

Fig 6.

RTC battery maximum supply current I

BAT

versus temperature in Power-down mode

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

53 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

002aae051

800

DD(DCDC)pd(3v3)

( μ A)

600

400

200

DD(DCDC)(3V3)

= 3.3 V

DD(DCDC)(3V3)

= 3.0 V

− 40 − 15 10 35 60 temperature ( ° C)

DD(3V3)

= V i(VBAT)

= 3.3 V; T amb

= 25

C.

Fig 7.

Total DC-to-DC converter supply current I

DD(DCDC)pd(3V3)

at different temperatures in Power-down mode

10.2 Deep power-down mode

300

DD(IO)

( μ A)

200

002aae046

100

DD(3V3)

= 3.3 V

−

DD(3V3)

= 3.0 V

−

15 10 35 60 temperature ( ° C)

DD(3V3)

= V

DD(DCDC)(3V3)

= 3.3 V; T amb

= 25

C.

Fig 8.

I/O maximum supply current I

DD(IO)

versus temperature in Deep power-down mode

LPC2420_60

Product data sheet

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Rev. 6.2 — 16 October 2013

54 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

V i(VBAT)

= 3.3 V

V i(VBAT)

= 3.0 V

002aae047

BAT

(

− 40 − 15 10 35 60 temperature (

DD(3V3)

= V

DD(DCDC)(3V3)

= 3.3 V; T amb

= 25

C

Fig 9.

RTC battery maximum supply current I

BAT

versus temperature in Deep power-down mode

002aae048

100

DD(DCDC)dpd(3v3)

( μ A)

DD(DCDC)(3V3)

= 3.3 V

DD(DCDC)(3V3)

= 3.0 V

−

15 10 35 60 temperature ( ° C)

DD(3V3)

= V i(VBAT)

= 3.3 V; T amb

= 25

C.

Fig 10. Total DC-to-DC converter maximum supply current I

DD(DCDC)dpd(3V3)

versus temperature in Deep power-down mode

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

55 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

10.3 Electrical pin characteristics

3.6

(V)

3.2

T = 85 ° C

−

2.8

002aaf112

2.4

2.0

0 8 16 24

(mA)

Conditions: V

DD(3V3)

= 3.3 V; standard port pins.

Fig 11. Typical HIGH-level output voltage V

versus HIGH-level output source current

002aaf111

(mA)

T = 85

− 40 ° C

0 0.2

0.4

0.6

(V)

Conditions: V

DD(3V3)

= 3.3 V; standard port pins.

Fig 12. Typical LOW-level output current I

versus LOW-level output voltage V

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

56 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

11. Dynamic characteristics

Table 10.

Dynamic characteristics

T amb





C to +85



C for commercial applications; V

DD(3V3)

over specified ranges.

[1]

Symbol Parameter Conditions Min t t

External clock f osc

T cy(clk) t

CHCX t

CLCX oscillator frequency clock cycle time clock HIGH time clock LOW time t

CLCH clock rise time t

CHCL clock fall time

I 2 C-bus pins (P0[27] and P0[28]) f(o)

SSP interface output fall time su(SPI_MISO)

SPI_MISO set-up time

to V

20 + 0.1

 C b

Dynamic characteristic: I/O pins [1]

T amb

= 25

C; measured in

SPI Master mode; see

Figure 17

T cy(clk)

 0.4

T cy(clk)

 0.4

Typ [2]

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[3] Bus capacitance C b

in pF, from 10 pF to 400 pF.

Max

1000 ns ns

Unit

MHz ns ns ns ns ns t

CHCL t

CLCX

T cy(clk) t

CHCX t

CLCH

Fig 13. External clock timing (with an amplitude of at least V i(RMS)

= 200 mV)

002aaa907

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

57 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

11.1 Internal oscillators

Table 11.

Dynamic characteristic: internal oscillators

T amb

40 C to +85 C; 3.0 V  V

DD(3V3)

 3.6 V. [1]

Symbol Parameter Conditions f osc(RC) f i(RTC) internal RC oscillator frequency

RTC input frequency

Min

3.96

Typ [2]

Max

4.02

32.768

4.04

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

11.2 I/O pins t r t f

Table 12.

T amb

40 C to +85 C; V

DD(3V3) over specified ranges.

Symbol Parameter Conditions rise time fall time pin configured as output pin configured as output

[1] Applies to standard I/O pins and RESET pin.

Min

3.0

2.5

Typ Max

5.0

11.3 USB interface

Table 13.

Dynamic characteristics of USB pins (full-speed)

= 50 pF; R pu

= 1.5 k



on D+ to V

DD(3V3)

,unless otherwise specified.

Symbol Parameter Conditions t r t f t

FRFM

CRS t

FEOPT t

FDEOP t

JR1 t

JR2 t

EOPR1 t

EOPR2 rise time fall time differential rise and fall time matching

10 % to 90 %

t r

/ t f output signal crossover voltage source SE0 interval of EOP see

source jitter for differential transition to SE0 transition see

receiver jitter to next transition receiver jitter for paired transitions 10 % to 90 %

EOP width at receiver

EOP width at receiver must reject as

EOP; see

must accept as

EOP; see

[1] Characterized but not implemented as production test. Guaranteed by design.

Min

8.5

7.7

1.3

160

2

18.5

9

Typ

Max

13.8

13.7

109

2.0

175

+18.5

Unit

MHz kHz

Unit ns ns ns ns ns ns

V ns ns

Unit ns ns

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

58 of 87

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11.4 Static external memory interface

Table 14.

Dynamic characteristics: Static external memory interface

= 30 pF, T amb





C to 85



C, V

DD(DCDC)(3V3)

= V

DD(3V3)

= 3.0 V to 3.6 V.

Symbol Parameter

Common to read and write cycles [1]

Conditions Min

0.29

CSLAV

CS LOW to address valid time

Read cycle parameters

[1][2]

OELAV

OE LOW to address valid time

0.29

CSLOEL t am t h(D) t

CSHOEH t

OEHANV

CS LOW to OE LOW time memory access time data input hold time

CS HIGH to OE HIGH time

OE HIGH to address invalid time

Typ

0.20

Max

2.54

Unit ns ns

[3][4]

[5]

0.78 + T cy(CCLK)

 WAITOEN 0 + T cy(CCLK)

 WAITOEN

(WAITRD

 WAITOEN + 1) 

T cy(CCLK)

 12.70

(WAITRD

 WAITOEN + 1) 

T cy(CCLK)

 9.57

0.49

0.20

0.20

0.49 + T cy(CCLK)

 WAITOEN ns

(WAITRD

 WAITOEN + 1) 

T cy(CCLK)

 8.11

ns ns

0.20

2.44

ns ns t

OELOEH t

BLSLAV

OE LOW to OE HIGH time

BLS LOW to address valid time

0.59 + (WAITRD 

WAITOEN + 1)

 T cy(CCLK)

0.39

0 + (WAITRD

 WAITOEN +

 T cy(CCLK)

0.10 + (WAITRD



WAITOEN + 1)

 T cy(CCLK)

2.54

ns t

CSHBLSH

CS HIGH to BLS HIGH time

Write cycle parameters [1][6]

0.88

0.49

0.68

ns t

CSLWEL t

CSLBLSL t

WELDV t

CSLDV t

WELWEH t

BLSLBLSH t

WEHANV

CS LOW to WE LOW time

CS LOW to BLS LOW time

WE LOW to data valid time

CS LOW to data valid time

WE LOW to WE HIGH time

BLS LOW to BLS HIGH time

WE HIGH to address invalid time

0.88 + T cy(CCLK)

 (1 +

WAITWEN)

0.88

0.68

0.78 + T cy(CCLK)



(WAITWR

 WAITWEN + 1)

0.88 + T cy(CCLK)



(WAITWR

 WAITWEN + 3)

0 + T cy(CCLK)

0.10 + T cy(CCLK)

 (1 +

WAITWEN)

0.49

2.54

2.64

0 + T cy(CCLK)

 (WAITWR 

WAITWEN + 1)

0 + T cy(CCLK)

 (WAITWR 

WAITWEN + 3)

0.20 + T cy(CCLK)

 (1 +

WAITWEN)

0.98

5.86

4.79

0.10 + T cy(CCLK)



(WAITWR

 WAITWEN + 1)

0.59 + T cy(CCLK)



(WAITWR

 WAITWEN + 3)

2.74 + T cy(CCLK) ns ns ns ns ns ns ns

Table 14.

Dynamic characteristics: Static external memory interface …continued

= 30 pF, T amb





C to 85



C, V

DD(DCDC)(3V3)

= V

DD(3V3)

= 3.0 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit t

WEHDNV

WE HIGH to data invalid time

0.78 + T cy(CCLK)

2.54 + T cy(CCLK)

5.96 + T cy(CCLK) ns t

BLSHANV

BLS HIGH to address invalid time

0.29

0.20

2.54

ns t

BLSHDNV

BLS HIGH to data invalid time

0 2.54

5.37

[1] V

= 2.5 V, V

= 0.2 V.

[2] V

= 2.5 V, V

= 0.5 V.

[3] T cy(CCLK)

= 1 ⁄

CCLK

[4] Latest of address valid, CS LOW, OE LOW to data valid.

[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.

[6] Byte lane state bit (PB) = 1.

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

11.5 Dynamic external memory interface

Table 15.

Dynamic characteristics: Dynamic external memory interface

= 30 pF, T amb

40 C to 85 C, V

DD(DCDC)(3V3)

= V

DD(3V3)

= 3.0 V to 3.6 V, EMC Dynamic Read Config Register = 0x0

(RD = 00)

Symbol Parameter Conditions Min Typ Max Unit

Common t d(SV) t h(S) t d(RASV) t h(RAS) t d(CASV) t h(CAS) t d(WV) t h(W) t d(GV) chip select valid delay time chip select hold time row address strobe valid delay time row address strobe hold time column address strobe valid delay time column address strobe hold time write valid delay time write hold time output enable valid delay time t h(G) t d(AV) output enable hold time address valid delay time t h(A) address hold time

Read cycle parameters t su(D) data input set-up time t h(D) data input hold time

Write cycle parameters t d(QV) t h(Q) data output valid delay time data output hold time

0.1

0.5

0.1

0.1

0.1

0.1

0.57

1.05

1.02

1.51

0.98

0.97

0.84

0.95

0.87

0.81

0.51

2.24

2.41

2.65

0.49

2.61

1.76

1.95

1.27

1.95

1.86

1.95

4.36

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

[1] See

Figure 18

LPC2420_60

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 — 16 October 2013

61 of 87

NXP Semiconductors

LPC2420/2460

Flashless 16-bit/32-bit microcontroller

Table 16.

Dynamic characteristics: Dynamic external memory interface

= 30 pF on all pins, T amb





C to 85



C, V

DD(DCDC)(3V3)

= V

DD(3V3)

= 3.3 V, EMC Dynamic Read Config Register = 0x1

(RD = 01), T cy(CCLK)

= 1/CCLK

Symbol Parameter Conditions Min Typ Max Unit t t t t t t

Common d(SV) h(S) d(RASV) h(RAS) d(CASV) h(CAS) chip select valid delay time chip select hold time row address strobe valid delay time row address strobe hold time column address strobe valid delay time column address strobe hold time t d(WV) t h(W) t d(GV) write valid delay time write hold time output enable valid delay time t h(G) t d(AV) output enable hold time address valid delay time t h(A) address hold time

Read cycle parameters t t su(D) t h(D) data input set-up time data input hold time

Write cycle parameters t d(QV) h(Q) data output valid delay time data output hold time

4 + T cy(CCLK)

3 + T cy(CCLK)

4 + T cy(CCLK)

4 + T cy(CCLK)

4 + T cy(CCLK)

3 + T cy(CCLK)

2.3 + T cy(CCLK)

3.4 + T cy(CCLK)

3 + T cy(CCLK)

3.4 + T cy(CCLK)

3 + T cy(CCLK)

2.1 + T cy(CCLK)

2.6 + T cy(CCLK)

2.3 + T cy(CCLK)

2.6 + T cy(CCLK)

1.5 + T cy(CCLK)

1.3 + T cy(CCLK)