STMicroelectronics L6562 Datasheet

L6562

TRANSITION-MODE PFC CONTROLLER

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1 Features

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REALISED IN BCD TECHNOLOGY

TRANSITION-MODE CONTROL OF PFC PRE-

REGULATORS

PROPRIETARY MULTIPLIER DESIGN FOR

MINIMUM THD OF AC INPUT CURRENT

VERY PRECISE ADJUSTABLE OUTPUT

OVERVOLTAGE PROTECTION

ULTRA-LOW (

≤70µA) START-UP CURRENT

LOW ( ≤4 mA) QUIESCENT CURRENT

EXTENDED IC SUPPLY VOLTAGE RANGE

ON-CHIP FILTER ON CURRENT SENSE

DISABLE FUNCTION

1% (@ Tj = 25 °C) INTERNAL REFERENCE

VOLTAGE

-600/+800mA TOTEM POLE GATE DRIVER WITH

UVLO PULL-DOWN AND VOLTAGE CLAMP

DIP-8/SO-8 PACKAGES ECOPACK

®

1.1 APPLICATIONS

■ PFC PRE-REGULATORS FOR:

– IEC61000-3-2 COMPLIANT SMPS (TV,

Figure 2. Block Diagram

COMP

2

1

INV

2.5V

-

+

Figure 1. Packages

DIP-8

Table 1. Order Codes

Part Number

L6562N

L6562D

L6562DTR

2

MULT

3 4

CS

Package

DIP-8

SO-8

Tape & Reel

DESKTOP PC, MONITOR) UP TO 300W

– HI-END AC-DC ADAPTER/CHARGER

– ENTRY LEVEL SERVER & WEB SERVER

Description

SO-8

The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible with the predecessor L6561, it offers improved performance.

MULTIPLIER AND

THD OPTIMIZER

40K

5pF

VOLTAGE

REGULATOR

OVERVOLTAGE

DETECTION

+

V

CC

V CC

8

25 V

R2

INTERNAL

SUPPLY 7V

R1

V REF2

+

-

UVLO

R

S

Q

Starter stop

DRIVER

15 V

7

GD

2.1 V

1.6 V

+

ZERO CURRENT

DETECTOR

-

STARTER

DISABLE

6

GND

5

ZCD

November 2005

Rev. 8

1/16

L6562

2 Description (continued)

The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj =

25°C) internal voltage reference.

The device features extremely low consumption ( ≤70 µA before start-up and <4 mA running) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.).

An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection.

The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOS-

FET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS's up to 300W.

Table 2. Absolute Maximum Ratings

Symbol

V

CC

---

IZCD

Pin

8

Parameter

IC Supply voltage (Icc = 20 mA)

1 to 4 Analog Inputs & Outputs

5 Zero Current Detector Max. Current

P tot

T j

T stg

Power Dissipation @Tamb = 50°C (DIP-8)

(SO-8)

Junction Temperature Operating range

Storage Temperature

Figure 3. Pin Connection (Top view)

Value self-limited

-0.3 to 8

-50 (source)

10 (sink)

1

0.65

-40 to 150

-55 to 150

Unit

V

V mA

W

°C

°C

INV

COMP

MULT

CS

3

4

1

2

6

5

8

7

Vcc

GD

GND

ZCD

Table 3. Thermal Data

Symbol

R th j-amb

Parameter

Max. Thermal Resistance, Junction-to-ambient

SO8

150

Minidip

100

Unit

°C/W

2/16

L6562

Table 4. Pin Description

N°

1

2

3

4

5

6

7

8

Pin

INV

COMP

MULT

CS

ZCD

GND

GD

Vcc

Function

Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider.

Output of the error amplifier. A compensation network is placed between this pin and INV (pin

#1) to achieve stability of the voltage control loop and ensure high power factor and low THD.

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop.

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off.

Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on.

Ground. Current return for both the signal part of the IC and the gate driver.

Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high

Vcc.

Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes.

Table 5. Electrical Characteristics

(T j

= -25 to 125°C, V

CC

= 12, C

O

= 1 nF; unless otherwise specified)

Test Condition Symbol

SUPPLY VOLTAGE

Parameter

V

CC

V

CCon

Operating range

Turn-on threshold

V

CCOff

Hys

Turn-off threshold

Hysteresis

V

Z

Zener Voltage

SUPPLY CURRENT

I start-up

I q

I

CC

I q

Start-up Current

Quiescent Current

Operating Supply Current

Quiescent Current

After turn-on

(1)

(1)

I

CC

= 20 mA

Before turn-on, V

CC

=11V

After turn-on

@ 70 kHz

During OVP (either static or dynamic) or V

ZCD

=150 mV

MULTIPLIER INPUT

I

MULT

Input Bias Current

V

MULT

Linear Operation Range

∆

V

∆

V

MU L T

Output Max. Slope

K

Gain

(2)

ERROR AMPLIFIER

V

INV

Voltage Feedback Input

Threshold

I

INV

Line Regulation

Input Bias Current

V

VFF

= 0 to 4 V

V

MULT

= 0 to 0.5V

V

COMP

= Upper clamp

V

MULT

= 1 V, V

COMP

= 4 V

T j

= 25 °C

10.3 V < Vcc < 22 V

(1)

Vcc = 10.3 V to 22V

V

INV

= 0 to 3 V

Min. Typ.

Max.

Unit

10.3

11

8.7

2.2

22

12

9.5

25

22

13

10.3

2.8

28

V

V

V

V

V

40

2.5

3.5

70

3.75

5

2.2

µA mA mA mA

0 to 3

1.65

1.9

-1 µA

V

V/V

0.5

0.6

0.7

1/V

2.465

2.44

2.5

2

2.535

2.56

5

-1

V mV

µA

3/16

L6562

Table 5. Electrical Characteristics (continued)

(T j

= -25 to 125°C, V

CC

= 12, C

O

= 1 nF; unless otherwise specified)

Symbol

G v

GB

I

COMP

V

COMP

Parameter

Voltage Gain

Gain-Bandwidth Product

Source Current

Sink Current

Upper Clamp Voltage

Lower Clamp Voltage

Test Condition

Open loop

V

COMP

= 4V, V

INV

= 2.4 V

V

COMP

= 4V, V

INV

= 2.6 V

I

SOURCE

= 0.5 mA

I

SINK

= 0.5 mA

(1)

CURRENT SENSE COMPARATOR

I

CS t d(H-L)

V

CS clamp

V

CSoffset

Input Bias Current

Delay to Outpu t

Current sense reference clamp

Current sense offset

V

CS

= 0

V

COMP

= Upper clamp

V

MULT

= 0

V

MULT

= 2.5V

ZERO CURRENT DETECTOR

V

ZCDH

Upper Clamp Voltage

V

ZCDL

V

ZCDA

Lower Clamp Voltage

Arming Voltage

(positive-going edge)

V

ZCDT

Triggering Voltage

(negative-going edge)

I

ZCDb

Input Bias Current

I

ZCDsrc

I

ZCDsnk

Sink Current Capability

V

ZCDdis

Disable threshold

V

ZCDen

I

ZCDres

Source Current Capability

Restart threshold

Restart Current after Disable

STARTER t

START

Start Timer period

OUTPUT OVERVOLTAGE

I

OVP

Hys

Dynamic OVP triggering current

Hysteresis

Static OVP threshold

GATE DRIVER

V

OH

Dropout Voltage

V

OL t f t r

V

Oclamp

Voltage Fall Time

Voltage Rise Time

Output clamp voltage

UVLO saturation

I

ZCD

= 2.5 mA

I

ZCD

= -2.5 mA

(3)

(3)

V

ZCD

(3)

(1)

= 1 to 4.5 V

I

GDsource

= 20 mA

I

GDsource

= 200 mA

I

GDsink

= 200 mA

I

GDsource

= 5mA; Vcc = 20V

V

CC

= 0 to V

CCon

, I sink

=10mA

(1) All parameters are in tracking

(2) The multiplier output is given by: V c s

=

M U L T

⋅ (

V

C O M P

– 2.5

)

(3) Parameters guaranteed by design, functionality tested in production.

Min. Typ.

60 80

1

-2 -3.5

2.5

5.3

2.1

4.5

5.7

2.25

Max.

-5

6

2.4

Unit dB

MHz mA mA

V

V

75

35

2.1

1.6

5.0

0.3

-2.5

2.5

150

30

200

1.7

30

5

5.7

0.65

2.1

1.6

2

-1

350

1.8

6.5

1

200

-5.5

250

350

75

µA ns

V mV

V

µA mA mA mV mV

µA

V

V

V

µs

µA

µA

V

10

130

40

30

2.25

2

2.5

0.9

30

40

12

300

45

2.4

2.6

3

1.9

70

80

15

1.1

V

V ns ns

V

V

4/16

L6562

3 Typical Electrical Characteristics

Figure 4. Supply current vs. Supply voltage

I

CC

(mA)

10

5

1

0.5

0.1

0.05

0.01

0.005

0

0 5

Co = 1nF f = 70 kHz

T j

= 25°C

20 25 10

Vcc(V)

15

Figure 5. Start-up & UVLO vs. T j

12.5

V

CC-ON

(V) 12

11.5

11

10.5

10

V CC-OFF

9.5

(V)

9

-50 0 50

Tj (°C)

100 150

Figure 6. IC consumption vs. T j

Icc 10

[mA]

5

Operating

Quiescent

2

1

0.5

0.2

0.1

0.05

Vcc = 12 V

Co = 1 nF f = 70 kHz

Disabled or

during OVP

Before start-up

0.02

-50 0 50

Tj (°C)

100 150

Figure 7. Vcc Zener voltage vs. T j

Vcc Z

(V)

28

27

26

25

24

23

22

-50 0 50

Tj (°C)

100 150

5/16

L6562

Figure 8. Feedback reference vs. T j

V

REF

(V)

2.6

Vcc = 12 V

2.55

2.5

2.45

2.4

-50 0 50

Tj (°C)

Figure 9. OVP current vs. T j

I OVP

(µA)

41

40.5

100

Vcc = 12 V

150

40

39.5

39

-50 0 50

Tj (°C)

100

Figure 10. E/A output clamp levels vs. T j

Vpin2

(V)

6

150

5

Upper clamp

Vcc = 12 V

4

3

2

-50

Lower clamp

0 50

Tj (°C)

100 150

Figure 11. Delay-to-output vs. T j t

D(H-L)

500

(ns)

Vcc = 12 V

400

300

200

100

0

-50 0 50

Tj (°C)

100 150

Figure 12. Multiplier characteristic

V

CS

(pin 4)

(V) upper voltage clamp

1.6

5.0

1.4

4

.5

4.0

1.2

V

COMP

3.5

(pin 2)

(V)

3.2

1.0

0.8

3.0

0.6

0.4

2.8

0.2

2.6

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

V

MULT

(pin 3) (V)

Figure 13. Multiplier gain vs. T j

K

1

0.8

Vcc = 12 V

V

COMP

=4 V

V

MULT

=1V

0.6

0.4

0.2

0

-50 0 50

Tj (°C)

100 150

6/16

Figure 14. Vcs clamp vs. T j

V

CSx

(V)

2

1.8

1.6

1.4

1.2

Vcc = 12 V

V COMP = Upper clamp

1

-50 0 50

Tj (°C)

Figure 15. Start-up timer vs. T j

Tstart

(µs)

150

Vcc = 12 V

140

100

130

120

110

150

100

-50 0 50

Tj (°C)

100 150

Figure 16. ZCD clamp levels vs. T j

V

ZCD

7

(V)

6

Upper clamp

Vcc = 12 V

I

ZCD = ±2.5 mA

5

4

3

2

1

0

-50 0 50

Tj (°C)

Lower clamp

100 150

L6562

Figure 17. ZCD source capability vs. T j

I

ZCDsrc

(mA)

0

Vcc = 12 V

V

ZCD

= lower clamp

-2

-4

-6

-8

-50 0 50

Tj (°C)

100 150

Figure 18. Gate-drive output low saturation

V pin7 [V]

4

Tj = 25 °C

Vcc = 11 V

SINK

3

2

1

0

0 200 400

I

GD

[mA]

600 800 1,000

Figure 19. Gate-drive output high saturation

V pin7

[V]

-1.5

Tj = 25 °C

Vcc = 11 V

SOURCE

-4.5

0 100 200 300 400 500 600 700

I

GD

[mA]

7/16

L6562

Figure 20. Gate-drive clamp vs. T j

Vpin7 clamp

(V)

15

Vcc = 20 V

14

13

12

11

10

-50 0 50

Tj (°C)

100 150

Figure 21. UVLO saturation vs. T j

Vpin7

(V)

1.1

Vcc = 0 V

1

0.9

0.8

0.7

0.6

0.5

-50 0 50

Tj (°C)

100 150

4 Application Information

4.1 Overvoltage protection

Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple components, the current through R1, I

R1

, equals that through R2, I

R2

. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then:

I

R2

=

2.5

I

R2

=

R1

=

Vo –

R1

2.5

.

If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and

COMP that introduces a long time constant to achieve high PF (this is why ∆Vo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become:

I'

R1

=

Vo – 2.5

+

R 1

∆

.

The difference current ∆I

R1

=I'

R1

-I

R2

=I'

R1

-I

R1

= ∆Vo/R1 will flow through the compensation network and enter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about

37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is maintained until the current falls below approximately 10 µA, which re-enables the internal starter and allows switching to restart. The output

∆Vo that is able to trigger the Dynamic OVP function is then:

∆

Vo =

⋅ ⋅ – 6

.

An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ∆Vo.

Since ∆Vo << Vo, the tolerance on the absolute value will be proportionally reduced.

Example: Vo = 400 V, ∆Vo = 40 V. Then: R1=40V/40µA=1MΩ; R2=1MΩ·2.5/(400-2.5)=6.289kΩ. The tolerance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value.

8/16

L6562

When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier output will saturate low; hence, when this is detected, the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its linear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low.

When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply system.

4.2 THD optimizer circuit

The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total

Harmonic Distortion) of the current is considerably reduced.

A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop.

Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)

Input current Input current

Rectified mains voltage Rectified mains voltage

To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the highfrequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key waveforms of a standard TM PFC controller are compared to those of the L6562.

Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to

9/16

L6562 the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid.

To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC preregulator - thus making the action of the optimizer circuit little effective.

Figure 23. Typical application circuit (250W, Wide-range mains)

FUSE

5A/250V

Vac

(85V to 265V)

-

R4

180 k

Ω

R5

180 k

Ω

R1

1.5 M

Ω

D8

1N4150

C5 12 nF

R14

100 Ω

D2

1N5248B

R6

68 k

Ω

+

BRIDGE

STBR606

C1

1 µF

400V

R2

1.5 M Ω

8

3

D3 1N5406

T

R50 10 k

Ω

C3 2.2 µF

5 2

L6562

6

C23

680 nF

4

1

7

R7

10

Ω

R3

22 k

Ω

C2

10nF C29

22 µF

25V

C4

100 nF

D1

STTH5L06

NTC

2.5

Ω

MOS

STP12NM50

7 °C/W heat sink

R9

0.33

Ω

1W

R10

0.33

Ω

1W

R13

9.53 k

Ω

R11

750 k

Ω

R12

750 k Ω

Vo=400V

Po=250W

C6

100 µF

450V

-

Boost Inductor Spec: EB0057-C (COILCRAFT)

Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic

FUSE

4A/250V

Vac

(85V to 265V)

-

2

T

R4

180 k Ω

R5

180 k

Ω

R1

750 k Ω

D8

1N4150

D2

1N5248B

C5 12 nF

R14

100

Ω

R6

68 k

Ω

+

BRIDGE

DF06M

C1

0.47 µF

400V

R2

750 k

Ω

8 5

3 L6562

6

R50 12 k

Ω

C3 680 nF

C23

330 nF

4

1

7

R7

33

Ω

R3

10 k

Ω

C2

10nF C29

22 µF

25V

C4

100 nF

D1

STTH1L06

NTC

2.5 Ω

MOS

STP8NM50

R9

0.82

Ω

0.6 W

R10

0.82

Ω

0.6 W

R13

9.53 k Ω

R11

750 k

Ω

R12

750 k

Ω

Vo=400V

Po=80W

C6

47 µF

450V

-

Boost Inductor Spec (ITACOIL E2543/E)

E25x13x7 core, 3C85 ferrite

1.5 mm gap for 0.7 mH primary inductance

Primary: 105 turns 20x0.1 mm

Secondary: 11 turns 0.1 mm

10/16

Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm)

L6562

Table 6. EVAL6562N: Evaluation results at full load

Vin (V

AC

) Pin (W) Vo (V

DC

)

∆Vo(V pk-pk

) Po (W)

85

110

135

175

220

265

86.4

84.6

83.8

83.2

82.9

82.7

394.79

394.86

394.86

394.87

394.87

394.87

12.8

12.8

12.8

15.5

15.7

15.9

80.16

80.20

80.20

80.20

80.20

80.20

Note: measurements done with the line filter shown in figure 23

Table 7. EVAL6562N: Evaluation results at half load

Vin (V

AC

) Pin (W) Vo (V

DC

)

∆Vo(V pk-pk

) Po (W)

85 42.8

394.86

6.6

40.20

110

135

175

220

42.5

42.5

42.5

42.6

394.90

394.91

394.93

394.94

6.6

6.7

8.0

8.2

40.20

40.20

40.19

40.19

265 42.6

394.94

8.3

Note: measurements done with the line filter shown in figure 23

40.19

η (%)

92.8

94.8

95.7

96.4

96.7

97.0

η (%)

93.9

94.6

94.6

94.6

94.3

94.3

PF

0.998

0.996

0.991

0.981

0.956

0.915

THD (%)

3.6

4.2

4.9

6.5

7.8

9.2

PF

0.994

0.985

0.967

0.939

0.869

0.776

THD (%)

5.5

6.2

7.1

8.3

9.8

11.4

11/16

L6562

Table 8. EVAL6562N: No-load measurements

Vin (V

AC

)

85

110

135

175

(*)

220

(*)

265

(*)

(*)

Vcc = 12V supplied externally

Pin (W)

0.4

0.3

0.3

0.4

0.4

0.5

Vo (V

DC

)

396.77

396.82

396.83

396.90

396.95

396.98

∆Vo(V pk-pk

)

0.45

0.55

0.60

1.00

1.40

1.65

Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation

Po (W)

0

0

0

0

0

0 to the AC source

B81133

470 nF, X2

EPCOS

B81133

680 nF, X2

EPCOS to

EVAL6562N

B82732

47 mH, 1.3A

EPCOS

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L6562

5 Package Information

In order to meet environmental requirements, ST offers these devices in ECOPACK

®

packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an

ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 27. DIP-8 Mechanical Data & Package Dimensions

I

L

Z e e3 e4

F

A a1

B

DIM.

mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

3.32

0.131

0.51

1.15

1.65

0.020

0.045

0.065

0.022

b b1

0.356

0.204

0.55

0.014

0.304

0.008

D

E 7.95

10.92

9.75

0.313

0.012

0.430

0.384

2.54

7.62

7.62

0.100

0.300

0.300

3.18

6.6

5.08

3.81

0.125

1.52

0.260

0.200

0.150

0.060

OUTLINE AND

MECHANICAL DATA

DIP-8

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L6562

Figure 28. SO-8 Mechanical Data & Package Dimensions

DIM.

B

C

D

(1)

E

A

A1

A2 mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

1.35

1.75

0.053

0.069

0.10

1.10

0.33

0.19

4.80

0.25

1.65

0.51

0.25

5.00

0.004

0.043

0.013

0.007

0.189

3.80

4.00

0.15

0.157

h

L e

H k

5.80

0.25

0.40

1.27

6.20

0.228

0.50

0.010

1.27

0.016

0˚ (min.), 8˚ (max.)

0.050

0.244

0.020

0.050

ddd 0.10

0.004

Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs.

Mold flash, potrusions or gate burrs shall not exceed

0.15mm (.006inch) in total (both side).

0.010

0.065

0.020

0.010

0.197

OUTLINE AND

MECHANICAL DATA

SO-8

0016023 C

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L6562

6 Revision History

Table 9. Revision History

Date

January 2004

June 2004

Revision

5

6

May 2005

November 2005

7

8

Description of Changes

First Issue

Modified the Style-look in compliance with the “Corporate Technical

Publications Design Guide”.

Changed input of the power amplifier connected to Multiplier (Fig. 2).

Modified Table 2: Absolute Maximim Ratings.

Added in Section 5 the ECOPACK

®

certicate of conformity.

15/16

L6562

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

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