Phytec phyCORE-i.MX35 Hardware manual

phyCORE-i.MX35
HARDWARE MANUAL
EDITION JUNE 2010
A product of a PHYTEC Technology Holding company
phyCORE-i.MX35
In this manual are descriptions for copyrighted products that are not explicitly indicated
as such. The absence of the trademark () and copyright () symbols does not imply
that a product is not protected. Additionally, registered patents and trademarks are
similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for
any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts
any liability whatsoever for consequential damages resulting from the use of this manual
or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the
information contained herein without prior notification and accepts no responsibility for
any damages which might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability
for damages arising from the improper usage or improper installation of the hardware or
software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout
and/or design of the hardware without prior notification and accepts no liability for doing
so.
 Copyright 2010 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part - are
reserved. No reproduction may occur without the express written consent from PHYTEC
Messtechnik GmbH.
EUROPE
NORTH AMERICA
Address:
PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information:
+49 (800) 0749832
[email protected]
1 (800) 278-9913
[email protected]
Technical
Support:
+49 (6131) 9221-31
[email protected]
1 (800) 278-9913
[email protected]
Fax:
+49 (6131) 9221-33
1 (206) 780-9135
Web Site:
http://www.phytec.de
http://www.phytec.com
1rst Edition June 2010
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Contents
1
Preface...................................................................................................1
1.1 Introduction.....................................................................................2
1.2 Block Diagram ................................................................................4
1.3 View of the phyCORE-i.MX35 ........................................................5
2
Pin Description .....................................................................................7
3
Jumpers...............................................................................................21
4
Power Requirements..........................................................................26
5
Real Time Clock U1 Backup-Voltage................................................27
6
System Configuration ........................................................................28
6.1 System Startup Configuration ......................................................28
6.1.1
Power-Up-Mode..............................................................28
6.1.2
Boot Mode Select ...........................................................29
7
System Memory ..................................................................................30
7.1 Memory Model..............................................................................31
7.2 DDR2-SDRAM (U6-U7)................................................................32
7.3 NOR-Flash (U9)............................................................................33
7.4 NAND Flash Memory (U10) .........................................................34
7.5 I²C EEPROM (U2) ........................................................................35
7.5.1
Setting the EEPROM Lower Address Bits
(J11, J14, J15) ................................................................36
7.5.2
EEPROM Write Protection Control (J1)..........................37
8
RS-232 .................................................................................................38
8.1 RS232 Transceiver (U12).............................................................38
8.1.1
UART2 Routing (RN4) ....................................................39
9
USB ......................................................................................................40
9.1 USB-OTG .....................................................................................40
9.2 USB-Host......................................................................................40
10
Ethernet Controller / Ethernet-Phy (U5) ...........................................41
11
CAN......................................................................................................42
12
JTAG Interface (X2) ............................................................................44
13
Technical Specifications ...................................................................48
 PHYTEC Messtechnik GmbH 2010
L-734e_1
phyCORE-i.MX35
14
Hints for Handling the phyCORE-i.MX35 .........................................50
15
The phyCORE i.MX35 on the i.MX Carrier Board ............................52
15.1 Concept of the phyCORE-i.MX Development Kits .......................53
15.2 phyMAP-i.MX35............................................................................54
15.2.1 phyMAP-i.MX35 Jumper Settings...................................56
15.2.2 phyMAP-i.MX35 Signal Mapping....................................59
15.2.3 phyMAP-i.MX35 USB-Host Interface..............................66
15.2.4 phyMAP-i.MX35 CAN Interface ......................................68
15.2.5 phyMAP-i.MX35 Boot Select Switch...............................70
15.2.6 phyMAP-i.MX35 Mapper Physical Dimensions ..............72
15.3 Cooperation of phyCORE-i.MX35 and
phyCORE-i.MX Carrier Board ......................................................73
15.3.1 Power Supply..................................................................74
15.3.2 CAN Interface .................................................................78
15.3.3 Push Buttons and LEDs .................................................80
15.3.4 Keypad Interface.............................................................82
15.3.5 Compact Flash Card.......................................................83
15.3.6 Security Digital Card/ MultiMedia Card...........................84
15.3.7 Audio and Touchscreen..................................................86
15.3.8 USB Host ........................................................................88
15.3.9 LCD Connectors .............................................................90
15.3.10 Camera Interface ............................................................92
15.3.11 JTAG Interface................................................................95
15.3.12 Complete Jumper Setting List for phyCORE-i.MX35
on the i.MX Carrier Board ...............................................97
16
Revision History ...............................................................................100
17
Component Placement Diagram .....................................................102
Index ..........................................................................................................104
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Contents
Index of Figures
Figure 1: Block Diagram of the phyCORE-i.MX35 ......................................4
Figure 2: Top View of the phyCORE-i.MX35 (Controller Side)....................5
Figure 3: Bottom View of the phyCORE-i.MX35 (Connector Side) .............6
Figure 4: Pin-Out of the phyCORE-Connector
(Top View, with Cross Section Insert) ..........................................8
Figure 5: Typical Jumper Pad Numbering Scheme...................................21
Figure 6: Jumper Locations (Top View).....................................................22
Figure 7: Jumper Locations (Bottom View) ...............................................23
Figure 8: JTAG Interface at X2 (Top View)................................................44
Figure 9: JTAG Interface at X2 (Bottom View) ..........................................45
Figure 10: Physical Dimensions of phyCORE-i.MX35 Module....................48
Figure 11: phyCORE-i.MX35 Carrier Board Connection Using
the phyMAP-i.MX35....................................................................53
Figure 12: phyMAP-i.MX35 Top View..........................................................54
Figure 13: phyMAP-i.MX35 Bottom View ...................................................55
Figure 14: Jumper Location on PMA-005 ....................................................56
Figure 15: PMA-005 USB-Host Interface.....................................................66
Figure 16: PMA-005 CAN Interface .............................................................68
Figure 17: PMA-005 Boot Select Dip-Switch ...............................................70
Figure 18: Physical Dimensions of phyMAP-i.MX35 Mapper ......................72
Figure 19: pyhCORE-i.MX Carrier Board and phyCORE-i.MX35
Power Supply .............................................................................74
Figure 20: phyCORE-i.MX Carrier Board CAN Interface.............................78
Figure 21: phyCORE-i.MX Carrier Board Buttons and LEDs ......................80
Figure 22: phyCORE-i.MX Carrier Board Keypad Interface ........................82
Figure 23: phyCORE-i.MX Carrier Board SD/MMC Card Interface.............84
Figure 24: phyCORE-i.MX Carrier Board Audio/Touch Interface ................86
Figure 25: phyCORE-iMX Carrier Board USB-Host Interface .....................88
Figure 26: phyCORE-i.MX Carrier Board LCD Interfaces ...........................90
 PHYTEC Messtechnik GmbH 2010
L-734e_1
phyCORE-i.MX35
Figure 27: phyCORE-i.MX Carrier Board Camera Interface .......................92
Figure 28: phyCORE-iMX Carrier Board JTAG Interface ............................95
Figure 29: phyCORE-i.MX35 Component Placement (Top View).............102
Figure 30: phyCORE-i.MX35 Component Placement
(Bottom View) ...........................................................................103
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Contents
Index of Tables
Table 1:
Pin-out of the phyCORE-Connector X1........................................9
Table 2:
Jumper settings ..........................................................................24
Table 3:
i.MX35 default power input voltages ..........................................26
Table 4:
Basic Boot Modes of i.MX35x Module........................................29
Table 5:
Advanced Boot Modes of i.MX35x Module ................................29
Table 6:
i.MX35 Memory Map ..................................................................31
Table 7:
Compatible NOR Flash Devices.................................................33
Table 8:
Compatible NAND Flash Devices ..............................................34
Table 9:
U2 EEPROM I²C Address via J11, J14, and J15 .......................36
Table 10: EEPROM Write Protection States via J1....................................37
Table 11: RN4 UART2 Signal Routing .......................................................39
Table 12: Fast Ethernet Controller Memory Map .......................................41
Table 13: CAN Controller Memory Map .....................................................42
Table 14: JTAG Connector X2 Signal Assignment ....................................46
Table 15: Jumper Settings of PMA-005......................................................58
Table 16: PMA-005 Mapping List ...............................................................59
Table 17: PMA-005 USB-Host Jumper Settings ........................................67
Table 18: PMA-005 CAN Jumper Settings .................................................69
Table 19: x_BOOT3 Selection....................................................................71
Table 20: x_BOOT4 Selection....................................................................71
Table 21: Jumper settings for i.MX35 Power Supply via
Power Plug .................................................................................75
Table 22: Jumper Settings for i.MX35 Power Supply via POE...................76
Table 23: Jumper Settings for i.MX35 Power Supply via Battery...............77
Table 24: CAN2 Interface Jumper Settings ................................................79
Table 25: x_BOOT_MODE0 Selection .......................................................81
Table 26: x_BOOT_MODE1 Selection .......................................................81
Table 27: x_Switch .....................................................................................81
 PHYTEC Messtechnik GmbH 2010
L-734e_1
phyCORE-i.MX35
Table 28: SD/MMC Interface Jumper Settings for
i.MX35 Module............................................................................85
Table 29: Audio/Touchscreen Interface Jumper Settings for
i.MX35 Module............................................................................87
Table 30: UBS Host Interface Jumper Settings for i.MX35
Module ........................................................................................89
Table 31: Camera Interface Jumper Settings for i.MX35 Module ..............93
Table 32: JTAG Jumper Settings for phyCORE-i.MX35 Module................96
Table 33: Jumper Settings for i.MX35 Module on i.MX
Carrier Board ..............................................................................97
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Preface
1 Preface
This hardware manual describes the phyCORE-i.MX35 Single Board Computer’s design and function.
Precise specifications for the Freescale i.MX35 microcontrollers can be found in the enclosed
microcontroller Data Sheet/User's Manual.
In this hardware manual and in the attached schematics, active low signals are denoted by a "/" or “#”
preceding the signal name (e.g.: /RD or #RD). A "0" indicates a logic zero or low-level signal, while a
"1" represents a logic one or high-level signal.
Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE-I.MX35
PHYTEC Single Board Computers (henceforth products) are designed for installation
in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype
platform for hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only
be unpacked, handled or operated in environments in which sufficient precautionary measures have
been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel
(such as electricians, technicians and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry if connections to the product's
pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity
only in accordance to the descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power connector and serial interface to a
host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions
of PHYTEC products, is subject to renewed establishment of conformity to, and certification of,
Electro Magnetic Directives. Users should ensure conformance following any modifications to the
products as well as implementation of the products into target systems.
The phyCORE-i.MX35 is one of a series of PHYTEC Single Board Computers that can be populated
with different controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1)
as the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2)
as insert-ready, fully functional phyCORE OEM modules, which can be embedded directly
into the user’s peripheral hardware design.
PHYTEC's microcontroller modules allow engineers to shorten development horizons, reduce design
costs and speed project concepts from design to market. For more information go to:
http://www.phytec.com/services/phytec-advantage.html
 PHYTEC Messtechnik GmbH 2010
L-734e_1
1
phyCORE-i.MX35
1.1 Introduction
The phyCORE-i.MX35 belongs to PHYTEC’s phyCORE Single Board Computer module family. The
phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all
core elements of a microcontroller system on a subminiature board and are designed in a manner
that ensures their easy expansion and embedding in peripheral hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference)
problems stem from insufficient supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin package. The increased pin
package allows dedication of approximately 20 % of all pin header connectors on the phyCORE
boards to ground. This improves EMI and EMC characteristics and makes it easier to design complex
applications meeting EMI and EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In
accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyCORE users with access to this cutting edge
miniaturization technology for integration into their own design.
The phyCORE-i.MX35 is a subminiature (85 x 58 mm) insert-ready Single Board Computer populated
with the Freescale i.MX35x microcontroller. Its universal design enables its insertion in a wide range
of embedded applications. All controller signals and ports extend from the controller to high-density
pitch (0.635 mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip"
into a target application.
Precise specifications for the controller populating the board can be found in the applicable controller
User’s Manual or datasheet. The descriptions in this manual are based on the Freescale i.MX35x. No
description of compatible microcontroller derivative functions is included, as such functions are not
relevant for the basic functioning of the phyCORE-i.MX35.
2
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Introduction
The phyCORE-I.MX35 offers the following features:























1:
Subminiature Single Board Computer (85 x 58 mm) achieved through modern SMD technology
Populated with the Freescale i.MX35x microcontroller (MAPBGA 1568-01, 17x17mm, 0.8 Pitch
packaging)
Improved interference safety achieved through multi-layer PCB technology and dedicated ground
pins
Controller signals and ports extend to two 200-pin high-density (0.635 mm) Molex connectors
aligning two sides of the board, enabling it to be plugged like a "big chip" into target application
Max. 532 MHz core clock frequency
Boot from NOR or NAND Flash
32 MByte (up to 64MByte) Intel Strata NOR Flash
1 GByte (up to 32 GByte) on-board NAND Flash 1
128 MByte (up to 256 MByte) DDR2 SDRAM on-board
RS-232 transceiver supporting one UART at data rates of up to 460kbps
UART Interface without transceiver
32 KB I2C EEPROM
Separate I²C RTC with backup function
Integrated High-Speed USB OTG and Full-Speed USB Host PHYs
Integrated 10/100MBit Ethernet Controller, Ethernet-PHY onboard
Two integrated CAN Controllers
All controller required supplies generated on board by Power-Supply device
Synchronous 24Bit LCD-Interface
12-/16-bit CMOS Camera Interface
Support of standard 20 pin debug interface through JTAG connector
Keyboard support for up to 16 keys in a 4 * 4 matrix
Two I2C interfaces
SD/MMC card interface with DMA
Please contact PHYTEC for more information about additional module configurations.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
3
phyCORE-i.MX35
1.2 Block Diagram
Figure 1:
4
Block Diagram of the phyCORE-i.MX35
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Introduction
1.3 View of the phyCORE-i.MX35
PHYTEC
PCM-043
C97
C182
R83
C87
L15
C94
TP6
C102
TP7
C179
C177
L14
C106
C142
U16
C176
R28 J23
U17
C171
C175
R93
R52
Q1
R26R75
C173
R84
L16
C178
C174
R79 R80 R77
RN4
C57
C186
R78
C61
U18
C169
C180
C181
C183
TP8
R73
C74
C25
C187
C75
C84 C63
C70
C115
R72
C185
C72
C81
C73
C189
U13
J12
U14
C190
R71 R69
R70
C188
U15
C104
C88
C145
R45
C121
C45
C50 C54
C89
C143
R47
C111
C124
C6
R35
C116 C114 C31
C86
C191
R50 R20
U9
C69
U19
C113
R94
C42
C112
C154
C32
C91 TP9
C67
C153 R22
U8
U7
C55
U6
R21
C33 C159
R51
U1
J10
C13
C120
R49
C184
C46
C40
C110
C123
U10
C96
C15
C168
C161
U4
R39
R40
R38
J8 J5 J7 J9
XT2
R37
R23
C79
R4 R5
R30
C68
J1
J24 J21
TP4
RN2
J15 J14 J11
C164
TP3
C76
TP1
C77
C90
TP2
U2
RN1
R29
C160
C165
XT3
R43
C49
TP5
X2
Figure 2:
Top View of the phyCORE-i.MX35 (Controller Side)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
5
phyCORE-i.MX35
R82
X1B
X1A
TP11
R81
C170 C172
C71
TP16
L7 C151
L6
C149
C27
C152
RN3
C11
C12
U12
C1
R48
C30
C108
U5
C28
R46
C109
R42
R44
C166
C93
XT1
C163
C29
C156
R41
TP15
C92
C162
C37
C78
C24
C80
TP17 TP18
C43
C118
C44
C36
C82
C158
C95
C10
R36
C122
R68
C38
U11
U20
C21
C20 C150
C8
R27
C157 C119
C196 C197
TP13 C22 C192
C155
C193
R99 R98
C194
TP12
C128
C103
C144
C136 C56 C146
C125
C58
L3
C17
C14
R32
R1
C16
C18
R34
R33
R3
R2
R6
C107
TP10
C105
C66
C85
C100
L12 L4 L13 L5
R31
R9
R7
C134
C139
C60
L2
R76
C98
C9
L1
C101
C167
C140
C48
C51
C130 C53
C52
C47C147 C133
C3
C131
C35 C7
C2
C129
C62
C59
C117
R24
C34 R74
C126
C4
C65 C39
C64
C83
C137
C99
C26
R25 C148
R96
C127
C23
C141 C138
C195
R97 R100
C132
TP14
R95
C135
C41
R8
C5
R13
U3
C19
R17
R11 R15 R19
R12 R16
R10
R14
R18
J13 J22
J2 J3 J4
X2
Figure 3:
6
Bottom View of the phyCORE-i.MX35 (Connector Side)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
2 Pin Description
Please note that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller manuals/data
sheets. As damage from improper connections varies according to use and application, it is the user's
responsibility to take appropriate safety measures to ensure that the module connections are
protected from overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors
(0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the
phyCORE-i.MX35 to be plugged into any target application like a "big chip".
A new numbering scheme for the pins on the phyCORE-connector has been introduced with the
phyCORE specifications. This enables quick and easy identification of desired pins and minimizes
errors when matching pins on the phyCORE-module with the phyCORE-connector on the appropriate
PHYTEC Development Board or in user target circuitry.
The numbering scheme for the phyCORE-connector is based on a two dimensional matrix in which
column positions are identified by a letter and row position by a number. Pin 1A, for example, is
always located in the upper left hand corner of the matrix. The pin numbering values increase moving
down on the board. Lettering of the pin connector rows progresses alphabetically from left to right
(refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-i.MX35 (viewed from above;
phyCORE-connector pointing down) or with the socket of the corresponding phyCORE Development
Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus
covered with the corner of the phyCORE-i.MX35 marked with a triangle. The numbering scheme is
always in relation to the PCB as viewed from above, even if all connector contacts extend to the
bottom of the module.
The numbering scheme is thus consistent for both the module’s phyCORE-connector as well as
mating connectors on the phyCORE Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix previously described, the
phyCORE-connector is usually assigned a single designator for its position (X1 for example). In this
manner the phyCORE-connector comprises a single, logical unit regardless of the fact that it could
consist of more than one physical socketed connector.
The location of row 1 on the board is marked by a triangle on the PCB to allow easy identification.
The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-i.MX35
with SMT phyCORE-connectors on its underside (defined as dotted lines) mounted on a Development
Board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a
cross-view of the phyCORE-module showing these phyCORE-connectors mounted on the underside
of the module’s PCB.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
7
phyCORE-i.MX35
Figure 4:
Pin-Out of the phyCORE-Connector (Top View, with Cross Section
Insert)
Table 1 provides an overview of the pin-out of the phyCORE-connector, as well as descriptions of
possible alternative functions.
Table 1 also provides the appropriate signal level interface voltages listed in the SL (Signal Level)
column. The Freescale i.MX35 is a multi-voltage operated microcontroller and as such special
attention should be paid to the interface voltage levels to avoid unintentional damage to the
microcontroller and other on-board components. Please refer to the Freescale i.MX35 User’s
Manual/Data Sheet for details on the functions and features of controller signals and port pins.
8
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
Note:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin.
Table 1:
Pin-out of the phyCORE-Connector X1
PIN ROW X1A
PIN #
SIGNAL
I/O
SL
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
23A
24A
25A
26A
27A
28A
29A
30A
31A
VDD_3V3
GND
not connected
not connected
X_LCD_VSYNC
not connected
GND
X_LCD_REV
X_LCD_SPL
X_LCD_DRDY
not connected
GND
X_LCD_LD0
X_LCD_LD2
X_LCD_LD3
X_LCD_LD5
GND
X_LCD_LD8
X_LCD_LD10
X_LCD_LD11
X_LCD_LD13
GND
X_LCD_LD17
X_LCD_LD18
X_LCD_LD19
X_LCD_LD21
GND
#CS0_3V3
#CS1_3V3
#CS4_3V3
EB1_3V3
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
VDD_3V3
0
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
32A
GND
-
0
 PHYTEC Messtechnik GmbH 2010
L-734e_1
DESCRIPTION
LCD reference voltage (3.3 V)
Ground 0 V
Pin left unconnected
Pin left unconnected
Display vertical synchronization pulse
Pin left unconnected
Ground 0 V
REV signal for display
SPL/SPR signal for display
Data enable signal for display
Pin left unconnected
Ground 0 V
Input/Output data 0 to display
Input/Output data 2 to display
Input/Output data 3 to display
Input/Output data 5 to display
Ground 0 V
Input/Output data 8 to display
Input/Output data 10 to display
Input/Output data 11 to display
Input/Output data 13 to display
Ground 0 V
Input/Output data 17 to display
Input/Output data 18 to display
Input/Output data 19 to display
Input/Output data 21 to display
Ground 0 V
Chip Select 0 output
Chip Select 1 output
Chip Select 4 output
Active low external enable byte signal that
controls
D[7:0]
Ground 0 V
9
phyCORE-i.MX35
33A
34A
35A
36A
37A
38A
39A
40A
41A
42A
43A
44A
45A
46A
47A
48A
49A
50A
51A
52A
53A
54A
55A
56A
57A
58A
59A
60A
61A
62A
63A
64A
65A
66A
67A
68A
69A
70A
71A
72A
10
#OE_3V3
LBA_3V3
BCLK_3V3
A2_3V3
GND
A4_3V3
A5_3V3
A7_3V3
A10_3V3
GND
A12_3V3
A13_3V3
A15_3V3
A18_3V3
GND
A20_3V3
A21_3V3
A23_3V3
D0
GND
D2
D3
D5
D8
GND
D10
D11
D13
VDD_1V8
GND
not connected
not connected
not connected
not connected
GND
not connected
X_FEC_TDATA3
X_FEC_RX_ER
R
X_FEC_RDATA2
GND
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_1V8
0
0
VDD_3V3
VDD_3V3
Memory Output Enable
Load Burst Address
Burst Clock
Address-Line A2
Ground 0 V
Address-Line A4
Address-Line A5
Address-Line A7
Address-Line A10
Ground 0 V
Address-Line A12
Address-Line A13
Address-Line A15
Address-Line A18
Ground 0 V
Address-Line A20
Address-Line A21
Address-Line A23
Data_Bus D0
Ground 0 V
Data_Bus D2
Data_Bus D3
Data_Bus D5
Data_Bus D8
Ground 0 V
Data_Bus D10
Data_Bus D11
Data_Bus D13
1.8V supply voltage
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
Pin left unconnected
Fast Ethernet Transmit Data 3
Fast Ethernet Receive Data Error
I
-
VDD_3V3
0
Fast Ethernet Receive Data 2
Ground 0 V
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
73A
74A
75A
76A
77A
78A
79A
80A
81A
82A
83A
84A
85A
86A
87A
88A
89A
90A
91A
92A
93A
94A
95A
96A
97A
98A
99A
100A
X_FEC_MDC
X_FEC_TX_CLK
X_FEC_RDATA0
X_FEC_RX_CLK
GND
X_CSI_D6
X_CSI_D8
X_CSI_D9
X_CSI_D11
GND
X_CSI_D14
X_CSI_MCLK
X_CSI_VSYNC
X_CSI_PIXCLK
GND
VDD_3V3
X_FEC_TX_EN
X_KEY_COL0
X_KEY_COL1
GND
X_KEY_COL2
X_KEY_COL3
not connected
X_GPIO2_6
GND
X_GPIO2_7
X_GPIO2_23
X_GPIO2_24
O
I
I
I
I
I
I
I
I
O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
 PHYTEC Messtechnik GmbH 2010
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
L-734e_1
Fast Ethernet Management Data Clock
Fast Ethernet Transmit Clock signal
Fast Ethernet Receive Data 0
Fast Ethernet Receive Clock signal
Ground 0 V
Camera Sensor D6
Camera Sensor D8
Camera Sensor D9
Camera Sensor D11
Ground 0 V
Camera Sensor D14
Camera Sensor Master Clock
Camera Sensor vertical sync
Camera Sensor pixel clock
Ground 0 V
CSI and FEC supply voltage (3.3V)
Fast Ethernet transmit enable signal
Keypad Port Column 0
Keypad Port Column 1
Ground 0 V
Keypad Port Column 2
Keypad Port Column 3
Pin left unconnected
GPIO2_6
Ground 0 V
GPIO2_7
GPIO2_23
GPIO2_24
11
phyCORE-i.MX35
PIN ROW X1B
PIN #
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
23B
24B
25B
26B
27B
28B
29B
30B
31B
32B
33B
34B
35B
36B
37B
38B
12
SIGNAL
I/O
SL
VDD_ALIVE
X_VSTBY
X_OWIRE
GND
X_LCD_HSYNC
not connected
X_LCD_CONTRAST
X_LCD_CLS
GND
X_LCD_FPSHIFT
not connected
not connected
X_LCD_LD1
GND
X_LCD_LD4
X_LCD_LD6
X_LCD_LD7
X_LCD_LD9
GND
X_LCD_LD12
X_LCD_LD14
X_LCD_LD15
X_LCD_LD16
GND
X_LCD_LD20
X_LCD_LD22
X_LCD_LD23
#CS3_3V3
GND
#CS5_3V3
EB0_3V3
#RW_3V3
ECB_WAIT_3V3
GND
A0_3V3
A1_3V3
A3_3V3
A6_3V3
O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
O
O
O
O
VDD_ALIVE
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
DESCRIPTION
VDD-ALIVE from LDO of power-supply (1.2 V)
I/O signal to PMIC
One-Wire bus
Ground 0 V
Display horizontal synchronization pulse
Pin left unconnected
Contrast control for display
CLS signal for display
Ground 0 V
Display Shift Clock
Pin left unconnected
Pin left unconnected
Input/Output data 1 to display
Ground 0 V
Input/Output data 4 to display
Input/Output data 6 to display
Input/Output data 7 to display
Input/Output data 9 to display
Ground 0 V
Input/Output data 12 to display
Input/Output data 14 to display
Input/Output data 15 to display
Input/Output data 16 to display
Ground 0 V
Input/Output data 20 to display
Input/Output data 22 to display
Input/Output data 23 to display
Chip Select 3 output
Ground 0 V
Chip Select 5 output
WEIM enable byte signal
WEIM Read/Write signal
WEIM End Current Burst / Wait signal
Ground 0 V
Address-Line A0
Address-Line A1
Address-Line A3
Address-Line A6
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
39B
40B
41B
42B
43B
44B
45B
46B
47B
48B
49B
50B
51B
52B
53B
54B
55B
56B
57B
58B
59B
60B
61B
62B
63B
64B
65B
66B
67B
68B
69B
70B
71B
72B
73B
74B
75B
76B
77B
78B
79B
GND
A8_3V3
A9_3V3
A11_3V3
A14_3V3
GND
A16_3V3
A17_3V3
A19_3V3
A22_3V3
GND
A24_3V3
A25_3V3
D1
D4
GND
D6
D7
D9
D12
GND
D14
D15
#X_FL_WP
not connected
GND
not connected
not connected
not connected
not connected
GND
X_FEC_RDATA1
X_FEC_RDATA3
X_FEC_MDIO
X_FEC_CRS
GND
X_FEC_RX_DV
X_FEC_COL
X_FEC_TX_ERR
X_CSI_D7
GND
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/O
I
I
I
O
I
-
 PHYTEC Messtechnik GmbH 2010
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
0
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
L-734e_1
Ground 0 V
Address-Line A8
Address-Line A9
Address-Line A11
Address-Line A14
Ground 0 V
Address-Line A16
Address-Line A17
Address-Line A19
Address-Line A22
Ground 0 V
Address-Line A24
Address-Line A25
Data_Bus D1
Data_Bus D4
Ground 0 V
Data_Bus D6
Data_Bus D7
Data_Bus D9
Data_Bus D12
Ground 0 V
Data_Bus D14
Data_Bus D15
NOR-Flash write-protect signal
Pin left unconnected
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
Fast Ethernet Receive Data 1
Fast Ethernet Receive Data 3
Fast Ethernet Management Data Input/Output
Fast Ethernet Carrier Sense enable
Ground 0 V
Fast Ethernet Receive data valid signal
Fast Ethernet Collision signal
Fast Ethernet Transmit Data Error
Camera Sensor D7
Ground 0 V
13
phyCORE-i.MX35
80B
81B
82B
83B
84B
85B
86B
87B
88B
89B
90B
91B
92B
93B
94B
95B
96B
97B
98B
99B
100B
14
X_CSI_D10
X_CSI_D12
X_CSI_D13
X_CSI_D15
GND
X_CSI_HSYNC
X_FEC_TDATA0
X_FEC_TDATA1
X_FEC_TDATA2
GND
X_KEY_ROW0
X_KEY_ROW1
X_KEY_ROW2
X_KEY_ROW3
GND
not connected
not connected
not connected
not connected
GND
X_CLKO
I
I
I
I
I
O
O
O
I/O
I/O
I/O
I/O
O
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
0
VDD_3V3
Camera Sensor D10
Camera Sensor D12
Camera Sensor D13
Camera Sensor D15
Ground 0 V
Camera Sensor horizontal sync
Fast Ethernet Transmit Data 0
Fast Ethernet Transmit Data 1
Fast Ethernet Transmit Data 2
Ground 0 V
Keypad Port Row 0
Keypad Port Row 1
Keypad Port Row 2
Keypad Port Row 3
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
Clock out signal selected from internal clock
signals
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
PIN ROW X1C
PIN #
SIGNAL
I/O
SL
DESCRIPTION
1C
2C
3C
4C
5C
6C
7C
8C
9C
10C
11C
12C
13C
VIN
VIN
GND
VIN
VIN
X_BKUP_SUPPLY
GND
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
GND
X_MVDD_BKUP
-
Power
Power
0
Power
Power
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
MVDD_BKUP
Main Power Input (3.6 V - 5.5 V)
Main Power Input (3.6 V - 5.5 V)
Ground 0 V
Main Power Input (3.6 V - 5.5 V)
Main Power Input (3.6 V - 5.5 V)
Backup power supply for the ext. RTC
Ground 0 V
Power for 3.3 V devices
Power for 3.3 V devices
Power for 3.3 V devices
Power for 3.3 V devices
Ground 0 V
14C
X_PVCC_BKUP
-
PVCC_BKUP
alternate PPLL supply for i.MX35x
15C
16C
17C
18C
19C
20C
21C
22C
23C
not connected
not connected
GND
not connected
not connected
not connected
not connected
GND
X_SCK4
I/O
0
0
VDD_3V3
Pin left unconnected
Pin left unconnected
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
24C
X_STXFS4
I/O
VDD_3V3
SSI serial transmit frame sync
25C
X_STXD4
O
VDD_3V3
SSI serial transmit Data
26C
27C
28C
29C
30C
31C
32C
33C
34C
35C
X_SRXD4
GND
not connected
not connected
not connected
not connected
GND
X_ETH_LINK
X_ETH_SPEED
X_ETH_RX-
I
O
O
I/O
VDD_3V3
0
0
VDD_3V3
VDD_3V3
VDD_3V3
36C
X_ETH_TX-
I/O
VDD_3V3
SSI serial receive Data
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
Ethernet Link & Activity Indicator (Open Drain)
Ethernet Speed Indicator (Open Drain)
Receive negative input (normal)
Transmit negative output (reversed)
Transmit negative output (normal)
Receive negative input (reversed)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
alternate MPLL supply for i.MX35x
SSI serial clock
15
phyCORE-i.MX35
37C
38C
39C
40C
41C
42C
43C
44C
45C
46C
47C
48C
GND
#X_ETH_INT
#X_CPU_DE
X_CPU_RTCK
#X_CPU_TRST
GND
X_SCKT
X_FST
X_HCKT
X_SCKR
GND
X_FSR
O
I
O
I
I/O
I/O
I/O
I/O
I/O
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
Ground 0 V
Ethernet Phy interrupt output
JTAG debug enable
JTAG test clock
JTAG test reset
Ground 0 V
Audio transmitter serial clock
Audio frame sync for transmitter
Audio high frequency clock for transmitter
Audio receiver serial clock
Ground 0 V
49C
50C
51C
52C
53C
54C
55C
56C
VDD_3V3
X_SD2_CLK
X_SD2_CMD
GND
X_USBPHY1_VBUS
X_USBPHY1_DM
X_USBPHY1_DP
X_USBPHY1_UID
O
I/O
I/O
I/O
I/O
I/O
VDD_3V3
VDD_3V3
VDD_3V3
0
5V (SW3)
VDD_3V3
VDD_3V3
VDD_3V3
SD reference voltage (3.3 V)
Clock for MMC/SD/SDIO 2 card
SD2 CMD line connect to card
Ground 0 V
USB1 VBUS Voltage
USB1 transceiver cable interface, DUSB1 transceiver cable interface, D+
57C
58C
59C
60C
61C
62C
63C
64C
65C
66C
67C
68C
GND
not connected
X_USBOTG_CLK
X_USBH2_CLK
X_USBOTG_DIR
GND
X_USBOTG_DATA2
X_USBOTG_DATA4
X_USBOTG_DATA6
not connected
GND
X_SD1_DATA0
I
I
I
I/O
I/O
I/O
I/O
0
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
69C
X_SD1_DATA1
I/O
VDD_3V3
70C
X_SD1_DATA2
I/O
VDD_3V3
71C
X_SD1_DATA3
I/O
VDD_3V3
Ground 0 V
Pin left unconnected
USB OTG clock signal
USB Host2 clock signal
USB OTG data direction
Ground 0 V
USB OTG data line 2
USB OTG data line 4
USB OTG data line 6
Pin left unconnected
Ground 0 V
SD/MMC 1 Data0 line in all modes also used
to detect busy state
SD/MMC 1 Data1 line in 4/8-bit mode also
used to detect interrupt in 1/4-bit mode
SD/MMC 1 Data2 line or Read wait in 4-bit
mode Read wait in 1-bit mode
SD/MMC 1 Data3 line in 4/8-bit mode or
Audio frame sync for receiver
USB1 on the go transceiver cable ID resistor
connection
configured as card detection pin may be configured
as card detection pin in 1-bit mode
72C
16
GND
-
0
Ground 0 V
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
73C
74C
75C
76C
77C
78C
79C
80C
81C
82C
83C
84C
85C
86C
87C
88C
89C
90C
91C
92C
93C
94C
95C
96C
97C
98C
99C
100C
X_UART1_RTS
X_UART1_CTS
X_UART1_RI
X_UART1_DCD
GND
not connected
not connected
not connected
not connected
GND
X_I2C3_SCL
X_I2C3_SDA
X_I2C1_DAT
X_CSPI1_SCLK
GND
X_CSPI1_SS0
X_CSPI1_SPI_RDY
X_CSPI2_MOSI
X_CSPI2_SCLK
GND
not connected
not connected
not connected
not connected
GND
X_BOOT0
X_BOOT1
VDD_3V3
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
 PHYTEC Messtechnik GmbH 2010
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
0
VDD_3V3
VDD_3V3
VDD_3V3
L-734e_1
Request to send UART 1
Clear to send UART 1
Ring Indicator UART 1
Data carrier detect UART1
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
I²C 3 Serial Clock
I²C 3 Serial Data
I²C 1 Serial Data
SPI 1 clock
Ground 0 V
SPI 1 Chip select 0
SPI 1 SPI data ready in Master mode
SPI 2 Master data out; slave data in
SPI 2 clock
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
Boot-Mode 0
Boot-Mode 1
Boot-Mode reference voltage (3.3 V)
17
phyCORE-i.MX35
PIN ROW X1D
PIN #
SIGNAL
I/O
SL
DESCRIPTION
1D
2D
3D
4D
5D
6D
7D
VIN
VIN
GND
not connected
#X_MASTER_RESET
#X_RESET_MCU
X_FUSE_VDD
I
O
-
Power
Power
0
VDD_3V3
VDD_3V3
FUSE_VDD
8D
X_TOUT
O
VDD_3V3
9D
10D
11D
12D
13D
14D
15D
16D
17D
18D
19D
20D
21D
22D
23D
24D
25D
26D
27D
28D
29D
30D
31D
32D
33D
34D
35D
GND
not connected
not connected
not connected
not connected
GND
X_EN_VDD_3V3
X_EN_VDD_1V8
X_EN_VDD_1V375
X_EN_LDO1_2
GND
X_EN_VDD_ALIVE
not connected
X_UART2_RXD
X_UART2_TXD
GND
X_UART2_RTS
X_UART2_CTS
X_CAPTURE
X_COMPARE
GND
X_CAN2_TX
X_CAN2_RX
X_CAN1_TX
X_CAN1_RX
GND
X_ETH_RX+
I
I
I
I
I
I
O
I
O
I
O
O
I
O
I
I/O
0
0
VIN
VIN
VIN
VIN
0
VIN
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
18
Main Power Input (3.6 V - 5.5 V)
Main Power Input (3.6 V – 5.5 V)
Ground 0 V
Pin left unconnected
Master Reset Input/Reset button
Reset Output from reset unit
Fusebox write (program) Supply Voltage
(3.3 V)
Open-Drain Thermostat Output of U3
(DS75)
Ground 0 V
Pin left unconnected
Pin left unconnected
Pin left unconnected
Pin left unconnected
Ground 0 V
Enable for 3.3 V power switch
Enable for 1.8 V power switch
Enable for 1.375 V power switch
Enable for power-supply LDO (3.3 V,1.8 V)
Ground 0 V
Enable for VDD_ALIVE LDO (1.2 V)
Pin left unconnected
Serial Data receive line UART 2
Serial Data transmit line UART 2
Ground 0 V
Request to send UART 2
Clear to send UART 2
Timer input capture
Timer output compare
Ground 0 V
CAN 2 transmit
CAN 2 receive
CAN 1 transmit
CAN 1 receive
Ground 0 V
Receive positive input (normal)
Transmit positive output (reversed)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Pin Description
36D
X_ETH_TX+
I/O
VDD_3V3
37D
38D
39D
40D
41D
42D
43D
44D
45D
46D
47D
48D
49D
50D
VDD_3V3
X_CPU_TCK
GND
X_CPU_TDI
X_CPU_TDO
X_CPU_TMS
X_JTAG_MODE
GND
X_MLB_CLK
X_MLB_DAT
X_MLB_SIG
VDD_3V3
GND
X_SD2_DATA0
I
I
O
I
I
I
I/O
I/O
I/O
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
51D
X_SD2_DATA1
I/O
VDD_3V3
Transmit positive output (normal)
Receive positive input (reversed)
JTAG reference voltage (3.3 V)
JTAG clock
Ground 0 V
JTAG Data In
JTAG Data Out
JTAG Mode select
JTAG Mode
Ground 0 V
Media local bus clock input
Media local bus data input/output
Media local bus signal information I/O
SD/MMC reference voltage (3.3 V)
Ground 0 V
SD/MMC 2 Data0 line in all modes also
used to detect busy state
SD/MMC 2 Data1 line in 4/8-bit mode also
used to detect interrupt in 1/4-bit mode
52D
X_SD2_DATA2
I/O
VDD_3V3
SD/MMC 2 Data2 line or Read wait in 4-bit
mode Read wait in 1-bit mode
53D
X_SD2_DATA3
I/O
VDD_3V3
SD/MMC 2 Data3 line in 4/8-bit mode or
configured as card detection pin may be
configured as card detection pin in 1-bit mode
54D
55D
56D
57D
58D
59D
60D
61D
62D
63D
64D
65D
66D
67D
68D
69D
70D
71D
GND
X_USBOTG_PWR
X_USBOTG_OC
X_USBPHY2_DP
X_USBPHY2_DM
GND
X_USBOTG_STP
X_USBOTG_NXT
X_USBOTG_DATA0
X_USBOTG_DATA1
GND
X_USBOTG_DATA3
X_USBOTG_DATA5
X_USBOTG_DATA7
X_SD1_CMD
GND
X_SD1_CLK
not connected
O
I
I/O
I/O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
O
-
 PHYTEC Messtechnik GmbH 2010
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
-
L-734e_1
Ground 0 V
USB Generic Power switch output
USB Generic Over Current input
USB2 transceiver cable interface, D+
USB2 transceiver cable interface, DGround 0 V
USB OTG stop signal
USB OTG next signal
USB OTG data line 0
USB OTG data line 1
Ground 0 V
USB OTG data line 3
USB OTG data line 5
USB OTG data line 7
SD1 CMD line connect to card
Ground 0 V
Clock for MMC/SD/SDIO 1 card
Pin left unconnected
19
phyCORE-i.MX35
72D
73D
74D
75D
76D
77D
78D
79D
80D
81D
82D
X_UART1_TXD
X_UART1_RXD
GND
X_UART1_DSR
X_UART1_DTR
not connected
not connected
GND
not connected
not connected
X_#IRQRTC
O
I
I/O
I/O
O
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
0
VDD_3V3
83D
84D
85D
86D
87D
88D
89D
90D
91D
92D
93D
94D
95D
96D
97D
98D
99D
100D
not connected
GND
X_I2C1_CLK
X_CSPI1_MOSI
X_CSPI1_MISO
X_CSPI1_SS1
GND
X_CSPI2_MISO
X_CSPI2_SPI_RDY
X_CSPI2_SS0
not connected
GND
not connected
X_BOOT3
X_BOOT4
X_BOOT5
GND
X_PWMO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
0
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
VDD_3V3
VDD_3V3
0
VDD_3V3
20
Serial data transmit signal UART 1
Serial data receive signal UART 1
Ground 0 V
Data set ready UART1
Data terminal ready
Pin left unconnected
Pin left unconnected
Ground 0 V
Pin left unconnected
Pin left unconnected
Interrupt Output from RTC U1
(RTC-8564JE)
Pin left unconnected
Ground 0 V
I²C 1 Serial Clock
SPI 1 Master data out; slave data in
SPI 1 Master data in; slave data out
SPI 1 Chip select 1
Ground 0 V
SPI 2 Master data in; slave data out
SPI 2 SPI data ready in Master mode
SPI 2 Chip select 0
Pin left unconnected
Ground 0 V
Pin left unconnected
Boot-Mode 3
Boot-Mode 4
Boot-Mode 5
Ground 0 V
Pulse Width Modulator Output
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Jumpers
3 Jumpers
For configuration purposes, the phyCORE-i.MX35 has 18 solder jumpers, some of which have been
installed prior to delivery. Figure 5 illustrates the numbering of the solder jumper pads, while Figure 6
and Figure 7 indicate the location of the solder jumpers on the board. 13 solder jumpers are located
on the top side of the module (opposite side of connectors) and 5 solder jumpers are located on the
bottom side of the module (connector side). Table 2 below provides a functional summary of the
solder jumpers, their default positions, and possible alternative positions and functions. A detailed
description of each solder jumper can be found in the applicable section listed in the table.
Figure 5:
Typical Jumper Pad Numbering Scheme
 PHYTEC Messtechnik GmbH 2010
L-734e_1
21
phyCORE-i.MX35
PHYTEC
PCM-043
J23
J12
J10
J8 J5 J7 J9
J1
J24 J21
J15 J14 J11
Figure 6:
22
Jumper Locations (Top View)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Jumpers
J13 J22
J2 J3 J4
Figure 7:
Jumper Locations (Bottom View)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
23
phyCORE-i.MX35
The jumpers (J = solder jumper) have the following functions:
Table 2:
Jumper settings
DEFAULT SETTING
ALTERNATIVE SETTING
J1
closed
open
J2
closed
J3
closed
J4
closed
J5
closed
J7
closed
Connects NFRB-signal from
open
the i.MX35x to R/#B1 pin of the
NAND-Flash
J8
closed
Connects NFRB-signal from
open
the i.MX35x to R/#B3 pin of the
NAND-Flash
J9
closed
open
J10
closed
J11
2+3
J12
closed
Connects NFRB-signal from
the i.MX35x to R/#B pin of the
NAND-Flash
#CS1_3V3 is connected to
NANDF_CE3_3V3 to use
alternate function NF_CE3
EEPROM A2 is connected to
GND (low)
only 1 DDR bank populated,
CSD1 can be used as
CS3_3V3 connected to the
molex connector
J13
2+3
1+2
J14
2+3
J15
2+3
DS75 A2 is connected to GND
(low)
EEPROM A1 is connected to
VDD_3V3 (high)
EEPROM A0 is connected to
GND (low)
24
EEPROM U2 is not write
protected
10k pull-down resistor to DipSwitch for boot select
X_BOOT2 (NOR/NAND)
10k pull-down resistor to DipSwitch for boot select
X_BOOT3 (MEM_TYPE[0])
10k pull-down resistor to DipSwitch for boot select
X_BOOT4 (MEM_TYPE[1])
Connects NFRB-signal from
the i.MX35x to R/#B2 pin of the
NAND-Flash
open
EEPROM U2 is write
protected
X_BOOT2 is not connected
to Dip-Switch
open
X_BOOT3 is not connected
to DIP-Switch
open
X_BOOT4 is not connected
to DIP-Switch
open
NFRB-signal from the
i.MX35x is not connected to
R/#B2 pin of the NANDFlash
NFRB-signal from the
i.MX35x is not connected to
R/#B1 pin of the NANDFlash
NFRB-signal from the
i.MX35x is not connected to
R/#B3 pin of the NANDFlash
NFRB-signal from the
i.MX35x is not connected to
R/#B pin of the NAND-Flash
#CS1_3V3 is not connected
to NANDF_CE3_3V3
open
1+2
open
1+2
1+2
EEPROM A2 is connected to
VDD_3V3 (high)
2 DDR banks populated,
CSD1 is used for the 2nd
DDR bank, signal is not
connected to the molex
connector
DS75 A2 is connected to
VDD_3V3 (high)
EEPROM A1 is connected to
GND (low)
EEPROM A0 is connected to
VDD_3V3 (high)
 PHYTEC Messtechnik GmbH 2010
SEE
SECTION
7.5.2
6.1.2
7.5.1
7.5.1
L-734e_1
Jumpers
J22
2+3
DS75 A1 is connected to
VDD_3V3 (high)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
1+2
DS75 A1 is connected to
GND (low)
25
phyCORE-i.MX35
4 Power Requirements
The phyCORE-i.MX35 normally operates off of one voltage supply denoted as VIN. The TPS650241
primary on-board voltage regulator operates off of VIN and generates all on-board supply voltages.
The phyCORE-i.MX Carrier Board generates VIN. VIN is sourced from either the wall socket input, or
a battery.
The input voltage VIN should be 5 V, with a nominal current allowance of at least 3 A.
See Table 1 from section 2 above for applicable VIN power pins on the phyCORE-connector.
Caution!
Connect all VIN input pins to your power supply.
As a general design rule we recommend connecting all GND pins which are neighboring signals
being used in the application circuitry.
The i.MX35x CPU is supplied by different power domains.
Table 3:
i.MX35 default power input voltages
POWER OUTPUT
Power switch 1 of U17
Power switch 2 of U17
Power switch 3 of U17
LDO 1 of U17
LDO 2 of U17
LDO VDD_ALIVE of U17
POWER-DOMAIN
VDD_3V3
VDD_1V8
VDD_1V375
LDO_3V3
LDO_1V5
VDD_ALIVE
STARTUP VOLTAGE-LEVEL
3.3 V
1.8 V
1.375 V
3.3 V
1.5 V
1.2 V
Note:
Phytec recommends to use the different power sources that are connected to the molex connectors of
the phyCORE-i.MX35 only as reference.
The current that could be externally drawn from the VCC_3V3 supply is max 500 mA..
26
 PHYTEC Messtechnik GmbH 2010
L-734e_1
System Configuration
5 Real Time Clock U1 Backup-Voltage
In case of a power fail or a user off event the backup-voltage X_BKUP_SUPPLY provides power to
the I²C Real Time Clock U1 (RTC8564JE). In this case a backup coincell could supply the RTC via
X_BKUP_SUPPLY.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
27
phyCORE-i.MX35
6
System Configuration
Although most features of the Freescale phyCORE-i.MX35 microcontroller are configured and/or programmed during the initialization routine, other features, which impact program execution, must be
configured prior to initialization via pin termination.
6.1
System Startup Configuration
During the reset cycle the i.MX35 processor reads the state of selected controller signals to determine
the basic system configuration. The configuration circuitries (pull-up or pull-down resistors) are
located on the phyCORE module. They are already set, so no further settings are necessary.
6.1.1 Power-Up-Mode
Note:
The i.MX35x controller has a defined power up sequence. Refer to the i.MX35 Data Sheet,
chapter 3.3 Power-Up sequence.
28
 PHYTEC Messtechnik GmbH 2010
L-734e_1
System Configuration
6.1.2 Boot Mode Select
The i.MX35x controller has different boot modes, which can be selected. The system boot mode of
the processor is determined by the configuration of the five external input pins, BOOT[4:0].
Table 4:
Basic Boot Modes of i.MX35x Module
Boot Mode Selection
BOOT 1
0
1
1
Table 5:
Boot Mode / Device
BOOT 0
0
0
1
Internal boot
External boot
Enter wait mode
Advanced Boot Modes of i.MX35x Module
Boot Mode Selection
BOOT 4
BOOT 3
Boot Mode / Device
BOOT 2
BOOT 1
BOOT 0
0
0
0
1
0
Boot from NOR Flash
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
0
Boot from NAND-Flash
( 3 address cycles)
Boot from NAND-Flash
(4 address cycles)
Boot from NAND-Flash
(5 address cycles)
Boot from NAND-Flash
(6 address cycles)
The phyCORE-i.MX35 module comes with a standard boot configuration of ‘00010’, so the system
will boot from the 16-bit NOR-Flash at CS0.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
29
phyCORE-i.MX35
7 System Memory
The phyCORE-i.MX35 provides three types of on-board memory:




DDR2-SDRAM:
NAND Flash:
NOR Flash:
I²C-EEPROM:
128MByte
1GByte
32MByte
32KB
(up to 256MByte)
(up to 32GByte)
(up to 64MByte)
(up to 32KByte)
It should be noted that the DDR2-SDRAM has a dedicated memory bus to the i.MX35x
microcontroller. The DDR2-SDRAM bus is therefore not made available at the phyCORE-connector
X1.
30
 PHYTEC Messtechnik GmbH 2010
L-734e_1
System Memory
7.1
Memory Model
The i.MX35x memory map is summarized in Table 6 below. For a detailed view of the memory map
please consult the Freescale i.MX35 User’s Manual.
Table 6:
i.MX35 Memory Map
ADDRESS
CHIP-SELECT
FUNCTION
0x8000 0000 – 0x8FFF FFFF
0x9000 0000 – 0x9FFF FFFF
0xA000 0000 – 0xA7FF FFFF
0xA800 0000 – 0xAFFF
FFFF
0xB000 0000 – 0xB1FF FFFF
0xB200 0000 – 0xB3FF FFFF
0xB400 0000 – 0xB5FF FFFF
0xB600 0000 – 0xB7FF FFFF
CSD0
CSD1
WEIM CS0 (flash 128)¹
WEIM CS1 (flash 64)
DDR2-SDRAM Bank 0 (U6, U7)
not used on phyCORE-i.MX35
NOR-Flash (U9)
0xBB00 0000 – 0xBB00 11FF
1.
WEIM CS2 (SRAM)
WEIM CS3
WEIM CS4
WEIM CS5
NFC memory region¹
(4K, NAND Flash)
multiplexed with NANDF_CE3
used as CSD0
not used on phyCORE-i.MX35
not used on phyCORE-i.MX35
not used on phyCORE-i.MX35
NAND-Flash (U10)
Can be used as a boot memory region
 PHYTEC Messtechnik GmbH 2010
L-734e_1
31
phyCORE-i.MX35
7.2
DDR2-SDRAM (U6-U7)
The phyCORE-i.MX35 has one bank of DDR2-SDRAMs on the i.MX35x module.
The RAM bank is comprised of two 16-bit wide DDR2-SDRAM chips, configured for 32-bit access,
and operating at 133MHz. In lower density configurations, U6 and U7 populate the module and are
accessed via SDRAM memory bank 0 using chip select signal /CSD0 starting at 0x8000 0000.
Actually there is no RAM bank 1 for the i.MX35x. So the /CSD1 chip select line is freed and can be
used as /CS3.
Typically the DDR2-SDRAM initialization is performed by a boot loader or operating system following
a power-on reset and must not be changed at a later point by any application code. When writing
custom code independent of an operating system or boot loader, SDRAM must be initialized by
accessing the appropriate SDRAM configuration registers on the i.MX35x controller. Refer to the
i.MX35 User Manual for accessing and configuring these registers.
32
 PHYTEC Messtechnik GmbH 2010
L-734e_1
System Memory
7.3
NOR-Flash (U9)
The phyCORE-i.MX35 can be populated with an Intel Strata Flash at U9. This NOR-Flash is
connected to /CS0 which is located at memory address 0xA000 0000. The entire Flash can be write
protected by pulling the x_/FL_WP signal, located at the phyCORE-connector X1 on pin 62B, low.
The following NOR-Flash devices can be used on the phyCORE-i.MX35:
Table 7:
Compatible NOR Flash Devices
MANUFACTURER
Intel/Numonyx
Intel/Numonyx
Intel/Numonyx
NOR FLASH P/N
PC28F640P33
PC28F128P33
PC28F256P33
 PHYTEC Messtechnik GmbH 2010
DENSITY (MBYTE)
8
16
32
L-734e_1
33
phyCORE-i.MX35
7.4
NAND Flash Memory (U10)
Use of Flash as non-volatile memory on the phyCORE-i.MX35 provides an easily reprogrammable
means of code storage. The following Flash devices can be used on the phyCORE-i.MX35:
Table 8:
Compatible NAND Flash Devices
MANUFACTURER
Numonyx
Numonyx
NAND FLASH P/N
NAND01G-xxx
NAND02G-xxx
DENSITY (MBYTE)
1024
2048
Additionally, any parts that are footprint (TSOP) and functionally compatible with the NAND Flash
devices listed above may also be used with the phyCORE-i.MX35.
These Flash devices are programmable with 3.3 V. No dedicated programming voltage is required.
As of the printing of this manual these NAND Flash devices generally have a life expectancy of at
least 100,000 erase/program cycles and a data retention rate of 10 years.
34
 PHYTEC Messtechnik GmbH 2010
L-734e_1
System Memory
7.5
I²C EEPROM (U2)
The phyCORE-i.MX35 is populated with a ST 24W32C 1 non-volatile 32 KByte EEPROM (U2) with an
I²C interface to store configuration data or other general purpose data. This device is accessed
through I²C port 1 on the i.MX35x. The serial clock signal and serial data signal for I²C port 1 are
made available at the phyCORE-connector as X_I2C1_DAT on X1 pin 85C and X_I2C1_CLK on X1
pin 85D.
Three solder jumpers are provided to set the lower address bits: J11, J14, and J15. Refer to
section 7.5.1 for details on setting these jumpers.
Write protection to the device is accomplished via jumper J1. By default this jumper is closed, allowing
write access to the EEPROM. Removing this jumper will cause the EEPROM to enter write protect
mode, thereby disabling write access to the device. Refer to section 7.5.2 for further details on setting
this jumper.
1:
See the manufacturer’s data sheet for interfacing and operation.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
35
phyCORE-i.MX35
7.5.1 Setting the EEPROM Lower Address Bits
(J11, J14, J15)
The 32 KB I²C EEPROM populating U2 on the phyCORE-module has the capability of configuring the
lower address bits A0, A1, and A2. The four upper address bits of the device are fixed at ‘1010’
(see ST 24W32C data sheet). The remaining three lower address bits of the seven bit I²C device
address are configurable using jumpers J11, J14 and J15. J15 sets address bit A0, J14 address
bit A1, and J11 address bit A2.
Table 9 below shows the resulting seven bit I²C device address for the eight possible jumper
configurations.
Table 9:
1:
36
U2 EEPROM I²C Address via J11, J14, and J15 1
U2 I²C DEVICE ADDRESS
J11
J14
J15
1010 010
1010 011
1010 000
1010 001
1010 110
1010 111
1010 100
1010 101
2+3
2+3
2+3
2+3
1+2
1+2
1+2
1+2
2+3
2+3
1+2
1+2
2+3
2+3
1+2
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
Defaults are in bold blue text
 PHYTEC Messtechnik GmbH 2010
L-734e_1
System Memory
7.5.2 EEPROM Write Protection Control (J1)
Jumper J1 controls write access to the EEPROM (U2) device. Closing this jumper allows write access
to the device, while opening this jumper enables write protection.
The following configurations are possible:
Table 10:
EEPROM Write Protection States via J1 1
EEPROM WRITE PROTECTION STATE
Write access allowed
Write protected
1:
J1
closed
open
Defaults are in bold blue text
 PHYTEC Messtechnik GmbH 2010
L-734e_1
37
phyCORE-i.MX35
8
RS-232
8.1 RS232 Transceiver (U12)
One high-speed RS-232 transceiver supporting 460kbps data rates populates the
phyCORE-i.MX35 at U12. This device converts the signal levels for:

RXD/TXD/RTS/CTS (UART2)
The RS-232 interface enables connection of the module to a COM port on a host-PC. In this
instance the RxD line of the transceiver is connected to the TxD line of the COM port; while the
TxD line of the transceiver is connected to the RxD line of the COM port. The ground potential
of the phyCORE-i.MX35 circuitry needs to be connected to the applicable ground pin on the
COM port as well.
The phyCORE-i.MX35 does not convert the remaining available UART (UART1) provided by
the i.MX35x MCU to RS-232 levels. The TTL level signals are made available at the
phyCORE-connector X1 (see Table 1). External RS-232 transceivers must be supplied by the
user if the additional UART requires RS-232 levels.
The maximum baud rate of UART2 is limited to 460,800 bps when used with the on-board
MAX3380 RS-232 transceiver.
38
 PHYTEC Messtechnik GmbH 2010
L-734e_1
RS-232
8.1.1 UART2 Routing (RN4)
RN4 is used to route the signals of UART2 serial interface through the RS-232 transceiver or
around the RS-232 transceiver when populated. When RN4 is not populated
UART2_RXD_TTL, UART2_TXD_TTL, UART2_RTS_TTL and UART2_CTS_TTL are routed
through the RS-232 transceiver U12 and come out as X_UART2_RXD, X_UART2_TXD,
x_UART2_RTS and x_UART2_CTS at the phyCORE-connector pins X1 pin 22D, X1 pin 23D,
X1 pin 25D, X1 pin 26D. If U12 does not populate the module, RN4 is populated to route the
TTL level signals to these same pins.
The standard phyCORE-i.MX35 module will have U12 populated, thereby routing the RS-232
level signals to the phyCORE-connector. Be sure the phyCORE-i.MX35 configuration you are
working with before interfacing these signals outside of the module as incorrect voltage levels
will likely cause damage to on-board and off-board components.
The following configurations are possible:
Table 11:
RN4 UART2 Signal Routing 1
SIGNAL CONFIGURATION
X_UART2_RXD, X_UART2_TXD, X_UART2_ RTS, X_
UART2_CTS as RS-232 level signals at X1 pin 22D, X1 pin
23D, X1 pin 25D and X1 pin 26D
X_UART2_RXD, X_UART2_TXD, X_UART2_ RTS, X_
UART2_CTS as TTL level signals at X1 pin 22D, X1 pin
23D, X1 pin 25D and X1 pin 26D
1:
RN4
not populated
populated
Defaults are in bold blue text
 PHYTEC Messtechnik GmbH 2010
L-734e_1
39
phyCORE-i.MX35
9
USB
The i.MX35x microcontroller has one USB 2.0 Host interface and one USB 2.0 OTG interface
both with integrated USB-Phys.
9.1
USB-OTG
With the phyCORE-i.MX35 USB-OTG is realized with the internal high-speed USB-OTG-Phy of
the i.MX35x. This Phy supports data rates up to 480Mbps. An external USB Standard-A (for
USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector and a
5 V VBUS power supply is all that is needed to interface the phyCORE-i.MX35 USB OTG
functionality. The applicable interface signals (D+/D-/VBUS/ID) can be found in the
phyCORE-connector pin-out Table 1.
Also the whole USB-OTG interface is connected to the phyCORE-connector so that there is the
possibility to use different USB-Phys.
9.2
USB-Host
With the phycore-i.MX35 USB-Host is realized with the internal full-speed USB-Host-Phy of the
i.MX35x microcontroller. This Phy supports data rates up to 12Mbps. An external USB
Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG)
connector is all that is needed to interface the phyCORE-i.MX35 USB Host functionality. The
applicable interface signals (D+/D-) can be found in the phyCORE-connector pin-out Table 1.
40
 PHYTEC Messtechnik GmbH 2010
L-734e_1
USB
10 Ethernet Controller / Ethernet-Phy (U5)
Connection of the phyCORE-i.MX35 to the world wide web (WWW) or a local area network (LAN)
is possible with the internal 10/100 Mbps Fast Ethernet controller. With this Ethernet controller an
external transceiver interface and transceiver function are required to complete the interface to the
media. Therefor the i.MX35x uses an Ethernet-Phy (U5).
The Ethernet-Phy provides MII/RMII/SMII interfaces to transmit and receive data. In addition the
PHY also supports HP Auto-MDIX technology, eliminating the need for the consideration of a direct
connect LAN cable, or a cross-over patch cable. It detects the TX and RX pins of the connected
device and automatically configures the PHY TX and RX pins accordingly. The Ethernet-Phy also
features LinkMD cable diagnostics, which allows detection of common cabling plant problems such
as open and short circuits.
The physical memory area for the Fast Ethernet controller is defined in Table 12.
Table 12:
Fast Ethernet Controller Memory Map
ADDRESS
0x5003_8 + 0x000-1FF
0x5003_8 + 0x200-3FF
FUNCTION
Control/Status Registers
MIB Block Counters
Connection to an external Ethernet transformer should be done using very short signal traces. The
TPI+/TPI- and TPO+/TPO- signals should be routed as 100 Ohm differential pairs. The same
applies for the signal lines after the transformer circuit. The carrier board layout should avoid any
other signal lines crossing the Ethernet signals.
Caution!
Please note the datasheet of the Ethernet-Phy when creating the Ethernet transformer circuitry.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
41
phyCORE-i.MX35
11 CAN
The i.MX35x provides two CAN interfaces (protocol specification version 2.0B). Its programmable
bit rate can be up to 1Mbyte/sec. All available signals (X_CAN1_RX, X_CAN1_TX, X_CAN2_RX,
X_CAN2_TX) are connected to the molex connector.
To use the CAN functionality of the i.MX35x you need an additional CAN transceiver and a CAN
connector for each of the two CAN interfaces which are provided by the phyCORE-i.MX35 module.
Table 13:
CAN Controller Memory Map
Address
0x53FE_4000 - 0x53FE_7FFF
0x53FE_8000 - 0x53FE_BFFF
Funktion
Controller Area Network (CAN)-1
Controller Area Network (CAN)-2
For further details of the Controller Area Network of i.MX35x please refer to the IMX35 Reference
Manual, chapter 24, Controller Area Network (FlexCAN).
42
 PHYTEC Messtechnik GmbH 2010
L-734e_1
CAN
 PHYTEC Messtechnik GmbH 2010
L-734e_1
43
phyCORE-i.MX35
12 JTAG Interface (X2)
The phyCORE-i.MX35 is equipped with a JTAG interface for downloading program code into the
external flash, internal controller RAM or for debugging programs currently executing. The JTAG
interface extends out to a 2.0 mm pitch pin header at X2 on the edge of the module PCB. Figure 8
and Figure 9 show the position of the debug interface (JTAG connector X2) on the phyCOREmodule.
PHYTEC
PCM-043
X2
2
Figure 8:
44
4
6
8
10
12
14
16
18
20
JTAG Interface at X2 (Top View)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
JTAG Interface (X2)
X2
19
Figure 9:
17
15
13
11
9
7
5
3
1
JTAG Interface at X2 (Bottom View)
Pin 1 of the JTAG connector X2 is on the connector side of the module. Pin 2 of the
JTAG connector is on the controller side of the module.
Note:
The JTAG connector X2 only populates phyCORE-i.MX35 modules with order code PCM-043-D.
JTAG connector X2 is not populated on phyCORE modules with order code PCM-043. However,
all JTAG signals are also accessible at the phyCORE-connector X1 (Molex connectors). We
recommend integration of a standard (2.54 mm pitch) pin header connector in the user target
circuitry to allow easy program updates via the JTAG interface. See Table 14 for details on the
JTAG signal pin assignment.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
45
phyCORE-i.MX35
Table 14:
JTAG Connector X2 Signal Assignment
SIGNAL
PIN
ROW*
A
B
VCC(VDD_3V3)
GND
GND
GND
GND
GND
2
4
6
8
10
12
1
3
5
7
9
11
GND
GND
GND
GND
14
16
18
20
13
15
17
19
SIGNAL
VTREF (VDD_3V3 via 100 Ohm)
#X_CPU_TRST
X_CPU_TDI
X_CPU_TMS
X_CPU_TCK
X_CPU_RTCKRTCK
(10k
Ohm
pulldown)
X_CPU_TDO
#X_RESET_MCU
#X_CPU_DE
J_DBGACK (10k Ohm pulldown)
*Note:
Row A is on the controller side of the module and row B is connector side of the module
PHYTEC offers a JTAG-Emulator adapter (order code JA-002) for connecting the
phyCORE-i.MX35 to a standard emulator. The JTAG-Emulator adapter extends the signals of the
module's JTAG connector to a standard ARM connector with 2.54 mm pin pitch. The JA-002
therefore functions as an adapter for connecting the module's non-ARM-compatible JTAG
connector U15 to standard Emulator connectors.
46
 PHYTEC Messtechnik GmbH 2010
L-734e_1
JTAG Interface (X2)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
47
phyCORE-i.MX35
13 Technical Specifications
The physical dimensions of the phyCORE-i.MX35 are represented in Figure 10. The module's profile
is approximately 8.6 mm thick, with a maximum component height of 4.1 mm on the bottom
(connector) side of the PCB and approximately 3.25 mm on the top (microcontroller) side. The board
itself is approximately 1.25 mm thick.
58mm
4.01mm
2.485mm
0.85mm
2.05mm
3.6mm
1.5mm
3.6mm
50.6mm
3.39mm
1.5mm
D
2.05mm
1.653mm
62.865mm
77.47mm
85mm
0.635mm
3.7mm
3.7mm
D
5.045mm
2mm
4.7mm
50.6mm
20mm
18mm
20mm
Figure 10: Physical Dimensions of phyCORE-i.MX35 Module
48
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Technical Specifications
Additional specifications :


Dimensions:
85 mm x 58 mm
Weight:


Storage temperature:
approximately 30 g with all optional
components mounted on the circuit board
-55°C to +125°C



Humidity:
0°C to +70°C (standard)
-40°C to +85°C (optional)
95 % r.F. not condensed
Operating voltage:
VIN 5 V
Power consumption:
VIN / 600 mA max *
Conditions:
VIN = 5 V
32 MByte Flash, 128 MB DDR2-RAM, 1 GB
NAND-Flash, Ethernet, 532 MHz CPU
frequency at 20°C

Operating temperature:
These specifications describe the standard configuration of the phyCORE-i.MX35 as of the printing of
this manual.
*
- booting UBoot:
- UBoot Prompt:
- RAM-Test in UBoot:
- Linux Prompt:
- Ping over Ethernet:
- incl. display, displaytest:
~235 mA (~1,175W)
~220 mA (~1,1W)
~210 mA (~1,05W)
~145 mA (~0,725W)
~145 mA (~0,725W)
~146 mA (~0,73W)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
(max value)
(norm. operation value)
(max value)
(norm. operation value)
(max value)
(max value)
49
phyCORE-i.MX35
14 Hints for Handling the phyCORE-i.MX35
Removal of various components, such as the microcontroller and the standard quartz, is not
advisable given the compact nature of the module. Should this nonetheless be necessary, please
ensure that the board as well as surrounding components and sockets remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module
inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can
be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the
bonds.
50
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Hints for Handling
 PHYTEC Messtechnik GmbH 2010
L-734e_1
51
phyCORE-i.MX35
15 The phyCORE i.MX35 on the i.MX Carrier Board
In this chapter you will find the information about using the phyCORE-i.MX35 module with the
phyCORE i.MX Carrier Board.
You will get an overview of how the phyCORE-i.MX35 module works with the phyCORE-i.MX Carrier
Board, how both boards are connected together over the phyMAPPER and you will also find all
settings that have to be done for a speedy and secure start-up of your i.MX35 module.
In this chapter you will only find specialized information of how the phyCORE-i.MX35 module works
with the phyCORE-i.MX Carrier Board. For further information about the Carrier Board please refer to
the i.MX Carrier Board Hardware Manual.
52
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.1 Concept of the phyCORE-i.MX Development Kits
Phytec decided to use one i.MX Carrier Board for different i.MX modules. Because every i.MX module
has different features and therefore a different pinning it is necessary to map the signals of the
modules to the right place on the Carrier Board.
For this every i.MX module comes with a phyMAPPER that is mapping the signals of the i.MX module
to the i.MX Carrier Board.
An example of the concept is shown in Figure 11 below. For further information about the concept of
the i.MX Carrier Board refer to the i.MX Carrier Board Hardware Manual.
Figure 11: phyCORE-i.MX35 Carrier Board Connection Using the phyMAP-i.MX35
 PHYTEC Messtechnik GmbH 2010
L-734e_1
53
phyCORE-i.MX35
15.2 phyMAP-i.MX35
The phyMAP-i.MX35 is responsible for mapping the signals from the various phyCORE-i.MX modules
to the phyCORE-i.MX Carrier Board. Signal differences at the connectors on the phyCORE-i.MX
modules, along with signal differences between the phyCORE-i.MX module connectors and i.MX
Carrier Board connector do not allow for direct connection of the phyCORE-i.MX modules into a
single, standardized Carrier Board. To allow for the use of a single Carrier Board, despite the signal
differences, the phyMAP-i.MX35 board serves as the gateway to properly map signals from the
i.MX Carrier Board Molex connectors to the various phyCORE-i.MX module connectors.
X3
X1
L1
D1
L2
L1
C2
U1
C1
R1
J8 R2
J5
J2 J3 J4
J6
J7
J9
C3
J1
R3
R3
X1
U2
R4
J10
J12
J11
S1
U3
X4
Figure 12: phyMAP-i.MX35 Top View
54
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
X2
X2
X2
Figure 13:
phyMAP-i.MX35 Bottom View
 PHYTEC Messtechnik GmbH 2010
L-734e_1
55
phyCORE-i.MX35
15.2.1
phyMAP-i.MX35 Jumper Settings
X3
X1
L1
D1
L2
L1
C2
U1
C1
R1
J8 R2
J5
J2 J3 J4
J6
J7
J9
C3
J1
R3
R3
X1
U2
R4
J10
J12
J11
S1
U3
X4
Figure 14: Jumper Location on PMA-005
There are 12 solder jumpers (0805) available on the phyMAP-i.MX35 Mapper. They are used to set
different functions partially in relation with the i.MX Carrier Board.
An individual description of the jumpers and a list of all jumper settings you will find subsequent.
J1
56
With jumper J1 the two FETs Q17 and Q18 on the i.MX Carrier Board can be enabled
or disabled. They allow a current flow to charge a battery connected to X21 on the
Carrier Board. If J1 is opened there is no current flow. If J1 is closed the FETs and
also the battery charge path are active.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
J2
If this jumper is set to 1+2 the FETs Q13 and Q14 of the i.MX Carrier Board are
disabled. In this case there is no power supply connection from the wall charger or
POE to VIN. If J2 is set to 2+3 the power supply is connected to VIN. It is necessary to
set J2 to 1+2 if you want to supply your board with a battery.
J3
If this jumper is set to 1+2 the FETs Q15 and Q16 of the i.MX Carrier Board are
disabled. In this case there is no power supply connection from the battery connector
X21 to VIN. If J3 is set to 2+3 the battery supply is connected to VIN. It is necessary to
set J2 to 1+2 if you want to supply your board via the wall charger or POE.
J4
With this jumper you can select the backup power supply of the module. If it is set to
1+2 the backup power supply device is the goldcap C161 of the Carrier Board. If J4 is
set to 2+3 the backup power is provided by a Li-Cell at connector X20 of the Carrier
Board.
J5
Selects whether the One-Wire or the PMIC-Ready function of the i.MX35 is used.
Setting 1+2 connects the One-Wire function to the baseboard connector, setting 2+3
connects the PMIC-Ready function to the baseboard.
J6
This jumper selects where the signal X_USBH2_OC of the i.MX35 is connected to. If
the USB-Host interface of the phyMAP-i.MX35 mapper is used this jumper is set to
2+3. If the USB-Host interface of the i.MX Carrier Board is used the jumper is set to
1+2.
J7
This jumper selects where the signal X_USBH2_PWR of the i.MX35 is connected to.
If the USB-Host interface of the phyMAP-i.MX35 mapper is used this jumper is set to
2+3. If the USB-Host interface of the i.MX Carrier Board is used the jumper is set to
1+2.
J8
This jumper selects where the signal X_USBPHY2_DM of the i.MX35 is connected to.
If the USB-Host interface of the phyMAP-i.MX35 mapper is used this jumper is set to
2+3. If the USB-Host interface of the i.MX Carrier Board is used the jumper is set to
1+2.
J9
This jumper selects where the signal X_USBPHY2_DP of the i.MX35 is connected to.
If the USB-Host interface of the phyMAP-i.MX35 mapper is used this jumper is set to
2+3. If the USB-Host interface of the i.MX Carrier Board is used the jumper is set to
1+2.
J10
Jumper J10 selects whether the signal X_SD2_DATA3 is used as data3 signal of SD2
interface on the i.MX Carrier Board or if the multiplexed CAN1_TX signal is used for
the additional CAN interface on the i.MX35 mapper board. If the jumper is set to 1+2
the SD2 signal is connected to the baseboard. If the jumper is set to 2+3 the CAN
signal is used with the CAN interface on the mapper.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
57
phyCORE-i.MX35
J11
Jumper J11 selects whether the signal X_SD2_DATA2 is used as data2 signal of SD2
interface on the i.MX Carrier Board or if the multiplexed CAN1_RX signal is used for
the additional CAN interface on the i.MX35 mapper board. If the jumper is set to 1+2
the SD2 signal is connected to the baseboard. If the jumper is set to 2+3 the CAN
signal is used with the CAN interface on the mapper.
J12
Jumper J12 selects whether the signal X_SD2_DATA1 is used as data1 signal of SD2
interface on the i.MX Carrier Board or if the multiplexed GPIO is used for the
additional CAN interface on the i.MX35 mapper board to enable or disable the CAN
function. If the jumper is set to 1+2 the SD2 signal is connected to the baseboard. If
the jumper is set to 2+3 the GPIO signal is used with the CAN interface on the
mapper.
Table 15:
JUMPER
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
58
Jumper Settings of PMA-005
SETTING
open
closed
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
DESCRIPTION
Battery charger path on PCM-970 not active
Battery charger path on PCM-970 active
FETs Q13, Q14 on PCM-970 disabled
FETs Q13, Q14 on PCM-970 enabled
FETs Q15, Q16 on PCM-970 disabled
FETs Q15, Q16 on PCM-970 enabled
x_BKUP_SUPPLY supplied by X_VBAT
x_BKUP_SUPPLY supplied by X_LICELL
X_OWIRE connected to X_1WIRE
X_OWIRE connected to X_PMIC_RDY
USB Host on Mapper is not used
USB Host on Mapper is used
USB Host on Mapper is not used
USB Host on Mapper is used
USB Host on Mapper is not used
USB Host on Mapper is used
USB Host on Mapper is not used
USB Host on Mapper is used
CAN on Mapper is not used
CAN on Mapper is used
CAN on Mapper is not used
CAN on Mapper is used
X_SD2_DATA1 is mapped to PCM-970
X_SD2_DATA1 is used as GPIO for CAN enable
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.2.2
phyMAP-i.MX35 Signal Mapping
In the following table you will find all signals of the phyCORE-i.MX35 module (PCM-043) connected
through the phyMAP-i.MX35 mapper (PMA-005) to the phyCORE-i.MX Carrier Board (PCM-970).
Take care that there are some signals connected to jumpers on the phyMAP-i.MX35 mapper. With
this signals it depends on the individual jumper setting where this signals are connected to. This
signals are in bold text.
Table 16:
PMA-005 Mapping List
SIGNAL NAME ON
PMA-005 MAPPER
A0_3V3
A1_3V3
A2_3V3
A3_3V3
A4_3V3
A5_3V3
A6_3V3
A7_3V3
A8_3V3
A9_3V3
A10_3V3
A11_3V3
A12_3V3
A13_3V3
A14_3V3
A15_3V3
A16_3V3
A17_3V3
A18_3V3
A19_3V3
A20_3V3
A21_3V3
A22_3V3
A23_3V3
A24_3V3
A25_3V3
BCLK_3V3
X1 PIN #
35B
36B
36A
37B
38A
39A
38B
40A
40B
41B
41A
42B
43A
44A
43B
45A
45B
46B
46A
47B
48A
49A
48B
50A
50B
51B
35A
 PHYTEC Messtechnik GmbH 2010
TO
X2 PIN # SIGNAL NAME ON I.MX
CARRIER BOARD
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
27B
28A
28B
29A
30A
30B
31A
31B
32B
33A
33B
34A
35A
35B
36A
36B
37B
38A
38B
39A
40A
40B
41A
41B
42B
43A
4E
MAPPED
L-734e_1
x_A0
x_A1
x_A2
x_A3
x_A4
x_A5
x_A6
x_A7
x_A8
x_A9
x_A10
x_A11
x_A12
x_A13
x_A14
x_A15
x_A16
x_A17
x_A18
x_A19
x_A20
x_A21
x_A22
x_A23
x_A24
x_A25
x_EXP005
59
phyCORE-i.MX35
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
EB0_3V3
EB1_3V3
ECB_WAIT_3V3
LBA_3V3
VDD_ALIVE
VDD_1V8
X_BKUP_SUPPLY
X_BOOT0
X_BOOT1
X_BOOT2
X_BOOT3
X_BOOT4
X_CAN2_RX
X_CAN2_TX
X_CAPTURE
X_CLKO
X_COMPARE
X_CPU_RTCK
X_CPU_TCK
X_CPU_TDI
X_CPU_TDO
X_CPU_TMS
60
51A
52B
53A
54A
53B
55A
55B
56B
56A
57B
58A
59A
58B
60A
60B
61B
31B
31A
33B
34A
1B
61A
6C
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
43B
44A
45A
45B
46A
46B
47B
48A
48B
49A
50A
50B
51A
51B
52B
53B
55B
56B
5E
54A
44E
43E
6C
x_D0
x_D1
x_D2
x_D3
x_D4
x_D5
x_D6
x_D7
x_D8
x_D9
x_D10
x_D11
x_D12
x_D13
x_D14
x_D15
x_/EB0
x_/EB1
x_EXP006
x_LBA
x_EXP069
x_EXP067
x_VBAT
98C
99C
98D
96D
97D
31D
30D
27D
100B
28D
40C
38D
40D
41D
42D
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
53C
53D
100B, 36F
37F
38F
38D
37D
50F
47F
50E
42D
40D
39C
40C
41C
x_BOOT_MODE0
x_BOOT_MODE1
x_switch, x_EXP057
x_EXP058
x_EXP060
x_CAN_RXD
x_CAN_TXD
x_EXP079
x_EXP074
x_EXP078
x_CPU_RTCK
x_CPU_TCK
x_CPU_TDI
x_CPU_TDO
x_CPU_TMS
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
X_CSI_D6
X_CSI_D7
X_CSI_D8
X_CSI_D9
X_CSI_D10
X_CSI_D11
X_CSI_D12
X_CSI_D13
X_CSI_D14
X_CSI_D15
X_CSI_HSYNC
X_CSI_MCLK
X_CSI_PIXCLK
X_CSI_VSYNC
X_CSPI1_MISO
X_CSPI1_MOSI
X_CSPI1_SCLK
X_CSPI1_SPI_RDY
X_CSPI1_SS0
X_CSPI1_SS1
X_CSPI2_MISO
X_CSPI2_MOSI
X_CSPI2_SCLK
X_CSPI2_SPI_RDY
X_CSPI2_SS0
X_EN_LDO1_2
X_EN_VDD_1V8
X_EN_VDD_1V375
X_EN_VDD_3V3
X_ETH_LINK
X_ETH_RX+
X_ETH_RXX_ETH_SPEED
X_ETH_TX+
X_ETH_TXX_FEC_COL
X_FEC_CRS
X_FEC_MDC
78A
78B
79A
80A
80B
81A
81B
82B
83A
83B
85B
84A
86A
85A
87D
86D
86C
89C
88C
88D
90D
90C
91C
91D
92D
18D
16D
17D
15D
33C
35D
35C
34C
36D
36C
76B
73B
73A
 PHYTEC Messtechnik GmbH 2010
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
73A
74A
75A
75B
76A
76B
77B
78A
78B
79A
73B
69A
71B
72B
25E
24E
23E
27F
26F
26E
96B
95B
97B
28F
98B
43F
41F
42F
40F
32D
30C
31C
33D
30D
31D
16E
15E
15F
L-734e_1
x_CSI_D0
x_CSI_D1
x_CSI_D2
x_CSI_D3
x_CSI_D4
x_CSI_D5
x_CSI_D6
x_CSI_D7
x_CSI_D8
x_CSI_D9
x_CSI_HSYNC
x_CSI_MCLK
x_CSI_PCLK
x_CSI_VSYNC
x_EXP038
x_EXP037
x_EXP035
x_EXP042
x_EXP041
x_EXP040
x_MISO
x_MOSI
x_SPICLK
x_EXP044
x_CE
x_EXP068
x_EXP065
x_EXP066
x_EXP063
x_ETH_/LED1
x_ETH_TPI+
x_ETH_TPIx_ETH_/LED2
x_ETH_TPO+
x_ETH_TPOx_EXP024
x_EXP022
x_EXP023
61
phyCORE-i.MX35
X_FEC_MDIO
X_FEC_RDATA0
X_FEC_RDATA1
X_FEC_RDATA2
X_FEC_RDATA3
X_FEC_RX_CLK
X_FEC_RX_DV
X_FEC_RX_ERR
X_FEC_TDATA0
X_FEC_TDATA1
X_FEC_TDATA2
X_FEC_TDATA3
X_FEC_TX_CLK
X_FEC_TX_EN
X_FEC_TX_ERR
X_FSR
X_FST
X_FUSE_VDD
X_GPIO2_6
X_GPIO2_7
X_GPIO2_23
X_GPIO2_24
X_HCKT
X_I2C1_CLK
X_I2C1_DAT
X_I2C3_SCL
X_I2C3_SDA
X_JTAG_MODE
X_KEY_COL0
X_KEY_COL1
X_KEY_COL2
X_KEY_COL3
X_KEY_ROW0
X_KEY_ROW1
X_KEY_ROW2
72B
75A
70B
71A
71B
76A
75B
70A
86B
87B
88B
69A
74A
89A
77B
48C
44C
7D
96A
98A, (38C)
99A
100A
45C
85D
85C
83C
84C
43D
90A
91A
93A
94A
90B
91B
92B
X_KEY_ROW3
X_LCD_CLS
X_LCD_CONTRAST
62
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
16F
8E
9E
10E
11E
6E
13E
14E
7F
8F
10F
11F
6F
12F
13F
73D
74C
6D
58C, 76D
75D
95A, 77D
94A, 78D
75C
39E
40E
99A
100A
43C
48D
49C
50C
50D
45C
45D
46C
x_EXP025
x_EXP011
x_EXP013
x_EXP014
x_EXP016
x_EXP008
x_EXP019
x_EXP021
x_EXP010
x_EXP012
x_EXP015
x_EXP017
x_EXP009
x_EXP018
x_EXP020
x_EXP089
x_EXP090
x_iMX_FUSE
X_LED, x_EXP094
x_EXP092
x_SD_W, x_EXP095
x_SD_D, x_EXP097
x_EXP091
x_EXP061
x_EXP062
x_I2C_SCL
x_I2C_SDA
x_CPU_SJC_MOD
x_KEY_COL0
x_KEY_COL1
x_KEY_COL2
x_KEY_COL3
x_KEY_ROW0
x_KEY_ROW1
x_KEY_ROW2
93B
<->
46D
x_KEY_ROW3
8B
<->
8B
x_LC_D3_CLS
7B
<->
7B
x_LC_CONTRAST
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
X_LCD_DRDY
10A
<->
10A
x_LC_DRDY0
X_LCD_FPSHIFT
10B
<->
10B
x_LC_BCLK
X_LCD_HSYNC
5B
<->
11A
x_LC_FPLINE
X_LCD_LD0
13A
<->
13A
x_LC_D0
X_LCD_LD1
13B
<->
13B
x_LC_D1
X_LCD_LD2
14A
<->
14A
x_LC_D2
X_LCD_LD3
15A
<->
15A
x_LC_D3
X_LCD_LD4
15B
<->
15B
x_LC_D4
X_LCD_LD5
16A
<->
16A
x_LC_D5
X_LCD_LD6
16B
<->
16B
x_LC_D6
X_LCD_LD7
17B
<->
17B
x_LC_D7
X_LCD_LD8
18A
<->
18A
x_LC_D8
X_LCD_LD9
18B
<->
18B
x_LC_D9
X_LCD_LD10
19A
<->
19A
x_LC_D10
X_LCD_LD11
20A
<->
20A
x_LC_D11
X_LCD_LD12
20B
<->
20B
x_LC_D12
X_LCD_LD13
21A
<->
21A
x_LC_D13
X_LCD_LD14
21B
<->
21B
x_LC_D14
X_LCD_LD15
22B
<->
22B
x_LC_D15
X_LCD_LD16
23B
<->
23B
x_LC_D16
X_LCD_LD17
23A
<->
23A
x_LC_D17
X_LCD_LD18
24A
<->
17F
x_EXP026
X_LCD_LD19
25A
<->
18F
x_EXP028
X_LCD_LD20
25B
<->
20F
x_EXP031
X_LCD_LD21
26A
<->
19E
x_EXP029
X_LCD_LD22
26B
<->
20E
x_EXP030
X_LCD_LD23
27B
<->
21F
x_EXP033
X_LCD_REV
8A
<->
8A
x_LC_D3_REV
X_LCD_SPL
9A
<->
9A
x_LC_D3_SPL
X_LCD_VSYNC
5A
<->
5B
x_LC_FPFRAME
X_MLB_CLK
45D
<->
71A, 23F
x_SNAPSHOT, x_EXP036
X_MLB_DAT
46D
<->
70A, 25F
x_TRIGGER, x_EXP039
X_MLB_SIG
47D
<->
70B, 21E
x_CSI_ENABLE, x_EXP032
X_MVDD_BKUP
13C
<->
45E
x_EXP070
X_OWIRE
X_PVCC_BKUP
X_PWMO
X_SCKR
X_SCKT
X_SCK4
3B
<->
58D
x_1Wire
14C
100D
46C
43C
23C
<->
<->
<->
<->
<->
46E
46F
76C
73C
21D
x_EXP072
x_EXP073
x_EXP093
x_EXP088
x_BITCLK
 PHYTEC Messtechnik GmbH 2010
L-734e_1
63
phyCORE-i.MX35
X_SD1_CLK
X_SD1_CMD
X_SD1_DATA0
X_SD1_DATA1
X_SD1_DATA2
X_SD1_DATA3
X_SD2_CLK
X_SD2_CMD
X_SD2_DATA0
X_SD2_DATA1
70D
68D
68C
69C
70C
71C
50C
51C
50D
51D
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
91A
90B
91B
92B
93A
93B
68C
68D
69C
70C
x_SD1_CLK
x_SD1_CMD
x_SD1_DATA0
x_SD1_DATA1
x_SD1_DATA2
x_SD1_DATA3
x_EXP080
x_EXP081
x_EXP082
x_EXP083
X_SD2_DATA2
52D
<->
70D
x_EXP084
X_SD2_DATA3
X_SRXD4
X_STXD4
X_STXFS4
X_TOUT
X_UART1_CTS
X_UART1_DCD
X_UART1_DSR
X_UART1_DTR
X_UART1_RI
X_UART1_RTS
X_UART1_RXD
X_UART1_TXD
X_UART2_CTS
X_UART2_RTS
X_UART2_RXD
X_UART2_TXD
X_USBH2_CLK
53D
<->
71C
x_EXP085
26C
25C
24C
8D
74C
76C
75D
76D
75C
73C
73D
72D
26D
25D
22D
23D
60C
33D
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
22D
20D
23D
48E
61D
63D
63C
64C
62D
60D
61C
60C
65C
66C
65D
66D
83A
72D
x_SDATA_IN
x_SDATA_OUT
x_SYNC
x_EXP075
x_CTS_DCE1_TTL
x_DCD_DCE1_TTL
x_DSR_DCE1_TTL
x_DTR_DCE1_TTL
x_RI_DCE1_TTL
x_RTS_DCE1_TTL
x_RXD_DCE1_TTL
x_TXD_DCE1_TTL
x_CTS_RS232
x_RTS_RS232
x_RXD_RS232
x_TXD_RS232
x_USBHOST2_CLK
x_EXP087
X_USBH2_PWR
X_USBOTG_CLK
X_USBOTG_DATA0
X_USBOTG_DATA1
X_USBOTG_DATA2
32D
<->
71D
x_EXP086
59C
62D
63D
63C
<->
<->
<->
<->
30E
31F
31E
32F
x_EXP046
x_EXP049
x_EXP048
x_EXP050
X_USBOTG_DATA3
65D
<->
33F
x_EXP052
X_USBOTG_DATA4
64C
<->
33E
x_EXP051
X_USBOTG_DATA5
66D
<->
35F
x_EXP055
X_USBH2_OC
64
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
X_USBOTG_DATA6
65C
<->
34E
x_EXP053
X_USBOTG_DATA7
67D
<->
35E
x_EXP054
X_USBOTG_DIR
61C
<->
28E
x_EXP043
X_USBOTG_NXT
61D
<->
30F
x_EXP047
X_USBOTG_OC
56D
<->
36D
x_USB_HS_FAULT
X_USBOTG_PWR
55D
<->
35D
x_USB_HS_/PSW
X_USBOTG_STP
60D
<->
29E
x_EXP045
X_USBPHY1_DM
54C
<->
34C
x_UDM
X_USBPHY1_DP
55C
<->
35C
x_UDP
X_USBPHY1_UID
56C
<->
36C
x_UID
X_USBPHY1_VBUS
53C
<->
33C
x_VBUS
X_USBPHY2_DM
58D
<->
38E
x_EXP059
X_USBPHY2_DP
57D
<->
36E
x_EXP056
X_VSTBY
2B
<->
79C
x_EXP098
#CS0_3V3
28A
<->
1E
x_EXP000
#CS1_3V3
29A
<->
1F
x_EXP001
#CS3_3V3
28B
<->
2F
x_EXP002
#CS4_3V3
30A
<->
3E
x_EXP003
#CS5_3V3
30B
<->
3F
x_EXP004
#OE_3V3
33A
<->
53A
x_/OE
#RW_3V3
32B
<->
55A
x_/WR
#X_CPU_DE
39C
<->
41D
x_CPU_/DE
#X_CPU_TRST
41C
<->
43D
x_CPU_/TRST
#X_EN_VDD_ALIVE
20D
<->
45F
x_EXP071
#X_FL_WP
62B
<->
49E
x_EXP077
#X_IRQRTC
82D
<->
48F
x_EXP076
#X_MASTER_RESET
5D
<->
5D
x_/Reset_Btn
#X_RESET_MCU
6D
<->
44C, 4D
x_/RESET_3V3
Note:
Signals in bold text are connected to jumpers. The mapping of this signals could differ from the
mapping list. Please check the positions of the affected jumpers to find out how the signals are
mapped.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
65
phyCORE-i.MX35
15.2.3
phyMAP-i.MX35 USB-Host Interface
X3
X1
L1
D1
L2
L1
C2
U1
C1
R1
J8 R2
J5
J2 J3 J4
J6
J7
J9
C3
J1
R3
R3
X1
U2
R4
J10
J12
J11
S1
U3
X4
Figure 15: PMA-005 USB-Host Interface
With the phyCORE-i.MX Carrier Board PCB versions 1280.0, 1280.1 and 1280.2 there is no
possibility to use the onboard USB-Host interface with the phyCORE-i.MX35 module. That’s why
Phytec decided to put a separate USB-Host interface on the i.MX35 mapper board. This USB-Host
interface is populated when the pyhCore-i.MX35 module should be used with phyCore-i.MX Carrier
Board version before 1280.3.
After a workaround with PCB version 1280.3 it is possible that the phyCORE-i.MX35 module uses the
USB-Host interface of the phyCORE-i.MX Carrier Board. This functionality is given with PCB
version 1280.3 or higher.
66
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
To have a decision which USB-Host interface should be used, there are solder jumpers located on the
mapper board that can be set.
Table 17:
J6
J7
J8
J9
PMA-005 USB-Host Jumper Settings
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
USB Host on Carrier Board is used
USB Host on Mapper is used
USB Host on Carrier Board is used
USB Host on Mapper is used
USB Host on Carrier Board is used
USB Host on Mapper is used
USB Host on Carrier Board is used
USB Host on Mapper is used
For further information of the separate jumpers J6 to J9 please refer to chapter 15.2.1,
“phyMAP-i.MX35 Jumper Settings”.
Note:
The USB-Host interface is only populated with the Upgrade (UPG) version of the phyMAP-i.MX35
mapper.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
67
phyCORE-i.MX35
15.2.4
phyMAP-i.MX35 CAN Interface
X3
X1
L1
D1
L2
L1
C2
U1
C1
R1
J8 R2
J5
J2 J3 J4
J6
J7
J9
C3
J1
R3
R3
X1
U2
R4
J10
J12
J11
S1
U3
X4
Figure 16: PMA-005 CAN Interface
The i.MX35x microcontroller provides two CAN controllers. Because there is only one CAN interface
available on the i.MX Carrier Board, Phytec designed a second CAN interface on the i.MX35 mapper
board. With this interface the CAN1 controller is used.
Its signals are multiplexed with the SD2-Card interface. Jumpers J10 to J12 can select whether the
CAN1 interface is used or the SD2 signals are mapped to the Carrier Board.
68
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 18:
J10
J11
J12
PMA-005 CAN Jumper Settings
1+2
2+3
1+2
2+3
1+2
2+3
X_SD2_DATA3 is mapped to PCM-970
CAN1 on Mapper is used
X_SD2_DATA2 is mapped to PCM-970
CAN1 on Mapper is used
X_SD2_DATA1 is mapped to PCM-970
X_SD2_DATA1 is used as GPIO for CAN enable
 PHYTEC Messtechnik GmbH 2010
L-734e_1
69
phyCORE-i.MX35
15.2.5
phyMAP-i.MX35 Boot Select Switch
X3
X1
L1
D1
L2
L1
C2
U1
C1
R1
J8 R2
J5
J2 J3 J4
J6
J7
J9
C3
J1
R3
R3
X1
U2
R4
J10
J12
J11
S1
U3
X4
Figure 17: PMA-005 Boot Select Dip-Switch
The i.MX35x controller is able to boot from different devices as described in chapter 6.1.2 Boot Mode
Select. To have a choice from which device the controller should boot, the boot signals BOOT0 to
BOOT4 are connected to two different dip-switches. These two switches are S5 on the i.MX35 Carrier
Board and S1 on the phyMAP-i.MX35 mapper.
With S1 on the i.MX35 mapper board it is possible to select the status of BOOT3 and BOOT 4. For
detailed information see Table 19 and Table 20 below.
70
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 19:
x_BOOT3 Selection
STATE OF SW NUMBER
1
STATE OF SW NUMBER
2
ON
OFF
OFF
ON
Table 20:
STATE OF X_BOOT3
1
0
x_BOOT4 Selection
STATE OF SW NUMBER
3
STATE OF SW NUMBER
4
ON
OFF
OFF
ON
 PHYTEC Messtechnik GmbH 2010
STATE OF X_BOOT4
1
0
L-734e_1
71
phyCORE-i.MX35
15.2.6
phyMAP-i.MX35 Mapper Physical Dimensions
1.18mm
4mm
70mm
50.6mm
20.78mm
13mm
26.35mm
L1
77.37mm
107mm
R3
50.6mm
9.76mm
Figure 18: Physical Dimensions of phyMAP-i.MX35 Mapper
72
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3 Cooperation of phyCORE-i.MX35 and
phyCORE-i.MX Carrier Board
In this chapter you will find specific information and settings to adapt the i.MX Carrier Board to the
i.MX35 module.
For information about the general functionality of the various interfaces of the phyCORE-i.MX Carrier
Board, please refer to the phyCORE-i.MX Carrier Board Hardware Manual.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
73
phyCORE-i.MX35
Power Supply
Line I N
MI C
CAN
Line OUT
X27
USB
USB-OTG
P1
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
15.3.1
1
CAN- by
JP31
CAN-pwr
3V3
JP38
VI N
JP36
JP33
JP34
JP40
1
SJC-Mode
5V
Reset
Power On
GPI O
Suspend
Char ging
1
Boot Mode/ CLK-Sel.
PHYTEC
St andby
JP39
MATRI X KEYBOARD
JTAG
DMC
S/ N
PCM-970
COMPACT FLASH
X21
MAI N-LI -Cell
JP35
At t ent ion see manual
5V DC 3A
CHARGER
VCC CF
CAN-PLD
JP32
X26
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 19: pyhCORE-i.MX Carrier Board and phyCORE-i.MX35 Power Supply
Subsequent you will find the different jumper settings for the three power supply modes described in
the phyCORE-i.MX Carrier Board Hardware Manual.
Caution!
With the phyCORE-i.MX35 module there is no Power Management IC MC13783 provided. So
compared to the phyCORE modules i.MX31 and i.MX27 there have to be different jumper settings on
the phyCORE-i.MX Carrier Board. Also battery charging is not provided with the i.MX35 module.
74
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3.1.1
Power Supply via Power Plug
Table 21 below shows the jumper settings to supply the phyCORE-i.MX35 module and the
phyCORE-i.MX Carrier Board with a wall charger at X26 of the i.MX Carrier Board.
Table 21:
JUMPER
SETTING
JP31
1+3,2+4
3+5,4+6
Power source is Power Over Ethernet (POE)
Power source is 5V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path
JP34
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path
JP35
Open
Closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
Open
Closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP38
1+2,3+4
Open,Open
1+2,3+4
Open,Open
JP39
JP40
1:
Jumper settings for i.MX35 Power Supply via Power Plug 1
Open
Closed
DESCRIPTION
Power switching, supply from 5V adapter or POE
No power switching, direct supply from VCC_3V3
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
Settings for the phyCORE-i.MX35 power supply via power plug are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
75
phyCORE-i.MX35
15.3.1.2
Power Supply via Power over Ethernet
Table 22 below shows the jumper settings to supply the phyCORE-i.MX35 module and the
phyCORE-i.MX Carrier Board with Power over Ethernet at X27.
Table 22:
Jumper Settings for i.MX35 Power Supply via POE 2
JUMPER
SETTING
JP31
1+3,2+4
3+5,4+6
Power source is Power Over Ethernet (POE)
Power source is 5V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path
JP34
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path
JP35
Open
Closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
Open
Closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP38
1+2,3+4
Open,Open
1+2,3+4
Open,Open
JP39
JP40
2:
76
Open
Closed
DESCRIPTION
Power switching, supply from 5V adapter or POE
No power switching, direct supply from VCC_3V3
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
Settings for the phyCORE-i.MX35 power supply via Power over Ethernet are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3.1.3
Power Supply via Battery
Table 23 below shows the jumper settings to supply the phyCORE-i.MX35 module and the
phyCORE-i.MX Carrier Board with a battery at X21 of the i.MX Carrier Board.
Table 23:
Jumper Settings for i.MX35 Power Supply via Battery 3
JUMPER
SETTING
JP31
1+3,2+4
3+5,4+6
Open,Open
1+3,2+4
3+5,4+6
Power source is Power Over Ethernet (POE)
Power source is 5V adapter
No Power supply from wall charger or POE
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path
JP34
1+2,3+4
Open,Open
No power switching, direct supply from VCC_3V3
Separate supply path
JP35
Open
Closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
Open
Closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP38
1+2,3+4
Open,Open
1+2,3+4
Open,Open
JP32
JP39
JP40
Open
Closed
DESCRIPTION
Power switching, supply from 5V adapter or POE
No power switching, direct supply from VCC_3V3
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
Note:
Instead of setting JP33 to 1+2, 2+3 there is the possibility to set solder jumper J3 of the phyMAPi.MX35 mapper to 2+3. In this case the two FETs Q15 and Q16 of the i.MX Carrier Board will connect
battery power to VIN.
3:
Settings for the phyCORE-i.MX35 power supply via battery are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
77
phyCORE-i.MX35
15.3.2
CAN Interface
P1
1-WIRE
MI C
RS232 disable
JP11 JP7
1
RS232 aut oshut down
SERI AL 1+2
Line I N
CAN
Line OUT
USB
USB-OTG
P2
JP10
CAN- by
JP9JP8
Power On
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
CAN-pwr
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 20: phyCORE-i.MX Carrier Board CAN Interface
The phyCORE-i.MX35 provides two CAN controllers. The CAN1 interface is realized on the
phyMAP-i.MX35 mapper. For further information about CAN1 please have a look at chapter 15.2.4
phyMAP-i.MX35 CAN Interface.
The CAN2 interface is located on the i.MX Carrier Board. Because the i.MX35x controller already has
an integrated CAN controller, the CAN controller populated on the Carrier Board will not be used.
Refer to Table 24 below for the jumper settings of the CAN2 interface.
78
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 24:
CAN2 Interface Jumper Settings 4
JUMPER
SETTING
JP7
1+2
2+3
CANTxD signal is routed to the CAN transceiver
x_CAN_TxD signal is routed to the CAN transceiver
JP8
1+2
2+3
Digital Isolator is supplied by VCC_CAN
Digital Isolator supply is VCC_5V
JP9
1+2
2+3
1+2
2+3
CANV- is connected to GND of i.MX Carrier Board
CANV- is not connected to GND of i.MX Carrier Board
CANRxd signal is routed to the CAN transceiver
x_CAN_RxD signal is routed to the CAN transceiver
1+2
2+3
CANV+ is connected to VCC_5V of i.MX Carrier Board
CANV+ is connected to CAN_OUT (external supply)
JP10
JP11
4:
DESCRIPTION
Default settings for the phyCORE-i.MX35 CAN2 interface are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
79
phyCORE-i.MX35
Push Buttons and LEDs
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
15.3.3
RS232 disable
D19
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
D42
3V3
VI N
S3
S4
GPI O
Suspend
MAI N-LI -Cell
St andby
Char ging
D21
D22
D23
D40
D41
VCC CF
1
S5
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
DMC
BACKUP-LI - Cell
D20
S/ N
PCM-970
COMPACT FLASH
5V
Reset
Power On
SJC-Mode
S1
S2
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
D50
LCD-SW
D24
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 21: phyCORE-i.MX Carrier Board Buttons and LEDs
The phyCORE-i.MX35 module does not use the MC13783 power management IC so the push
buttons S2, S3 and S4 are not supported. Also D20 and D41 should not be supported with the i.MX35
module.
The GPIO signal to drive D40 high or low is the X_GPIO2_6 signal of the i.MX35 module.
80
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3.3.1
Boot-Mode and Clock Selection
Note:
Clock selection is not available with the i.MX35 module.
The i.MX35x controller is able to boot from different devices as described in chapter 6.1.2 Boot Mode
Select. To have a choice from which device the controller should boot the boot signals BOOT0 to
BOOT4 are connected to two different dip-switches. These two switches are S5 on the i.MX Carrier
Board and S1 on the phyMAP-i.MX35 mapper.
With S5 on the i.MX Carrier Board it is possible to select the status of BOOT0, BOOT1 and BOOT2.
For detailed information see Table 25, Table 26 and Table 27 below.
Note:
A standard Boot Configuration is already set on the i.MX35 module. Here you can change the Boot
Mode to an alternatively mode. For standard Boot Configuration all dip switches have to be in OFF
position.
Table 25:
x_BOOT_MODE0 Selection
STATE OF SW NUMBER
3
STATE OF SW NUMBER
4
ON
OFF
OFF
ON
Table 26:
0
1
x_BOOT_MODE1 Selection
STATE OF SW NUMBER
5
STATE OF SW NUMBER
6
ON
OFF
OFF
ON
Table 27:
STATE OF X_BOOT0
STATE OF X_BOOT1
0
1
x_Switch
STATE OF SW NUMBER
7
STATE OF SW NUMBER
8
ON
OFF
OFF
ON
 PHYTEC Messtechnik GmbH 2010
STATE OF X_BOOT2
0
1
L-734e_1
81
phyCORE-i.MX35
Keypad Interface
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
15.3.4
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
3V3
Power On
VI N
VCC CF
X18
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
GPI O
1
1
MATRI X KEYBOARD
JTAG
Char ging
St andby
8
8
7
7
6
5
6
5
4
3
2
1
A
4
3
2
1
B
COMPACT FLASH
Suspend
MAI N-LI -Cell
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 22: phyCORE-i.MX Carrier Board Keypad Interface
Although the phyCORE-i.MX Carrier Board supports a 6x6 keypad matrix interface, the i.MX35
module only provides a 4x4 matrix. So only the first four of the row and column lines (ROW0 to ROW3
and COL0 to COL3) are used.
82
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3.5
Compact Flash Card
Note:
Compact Flash Card is not supported by the phyCORE-i.MX35 module, because there is no PCMCIA
controller provided with the i.MX35x microcontroller.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
83
phyCORE-i.MX35
Security Digital Card/ MultiMedia Card
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
15.3.6
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
VCC LCD
MMC-SD
X15
JP50
CAMERA
DI SPLAY
JP18
1
C
A
D
B
1
Figure 23: phyCORE-i.MX Carrier Board SD/MMC Card Interface
The MMC_DETECT signal is connected to GPIO signal X_GPIO2_24 of the i.MX35 module.
MMC_WP is connected to GPIO signal X_GPIO2_23.
84
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 28:
JUMPER
5:
SD/MMC Interface Jumper Settings for i.MX35 Module 5
SETTING
DESCRIPTION
JP50
2+3
1+2
MMC_WP signal of SD/MMC Interface is connected to GPIO
MMC_WP signal of SD/MMC Interface is not connected to GPIO
JP18
2+3
1+2
Level shifter U25 is enabled
Level shifter U25 is disabled
Default settings for the phyCORE-i.MX35 SD/MMC interface are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
85
phyCORE-i.MX35
15.3.7
Audio and Touchscreen
P1
RS232 disable
JP47
JP48
JP49
RS232 aut oshut down
SERI AL 1+2
JP28
JP25
JP27
JP26
1-W
I RE
MI C
CAN
Line I N
JP24
JP23
JP20
JP19
JP21
JP22
Line OUT
USB
USB-OTG
X13 X12 X11
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
5V
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
MMC-SD
VCC LCD
CAMERA
DI SPLAY
X23
1
C
A
D
B
1
Figure 24: phyCORE-i.MX Carrier Board Audio/Touch Interface
With the phyCORE-i.MX35 module there is no audio/touchscreen device onboard, so the i.MX35
module has to use the audio/touchscreen device (U24) on the i.MX Carrier Board.
To select that this device should be used, there are a variety of jumpers which have to be set.
A detailed list of all jumper settings you will find in Table 29 below.
86
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 29:
Audio/Touchscreen Interface Jumper Settings for i.MX35 Module 6
JUMPER
SETTING
JP21
2+3
1+2
x_MC1RIN is connected to X11
MIC1 is connected to X11
JP22
2+3
1+2
x_MC1LIN is connected to X11
MIC2 is connected to X11
JP19
2+3
1+2
x_RXOUTL is connected to X12
LINE_INR is connected to X12
JP20
2+3
1+2
x_RXOUTR is connected to X12
LINE_INL is connected to X12
JP23
2+3
1+2
x_RXINL is connected to X13
LINE_OUTR is connected to X13
JP24
2+3
1+2
x_RXINR is connected to X13
LINE_OUTL is connected to X13
JP25
2+3
1+2
x_TSY1 is connected to X23
TP_Y- is connected to X23
JP26
2+3
1+2
x_TSX2 is connected to X23
TP_X+ is connected to X23
JP27
2+3
1+2
x_TSY2 is connected to X23
TP_Y+ is connected to X23
JP28
2+3
1+2
X_TSX1 is connected to X23
TP_X- is connected to X23
JP47
open
closed
open
closed
open
closed
JP48
JP49
6:
DESCRIPTION
Reset is held high, no asserting by GPIO of i.MX module
Reset can be asserted by GPIO of i.MX module
No access to IRQ via GPIO of i.MX module
Access to IRQ via GPIO of i.MX module
No access to PENDOWN via GPIO of i.MX module
Access to PENDOWN via GPIO of i.MX module
Settings for the phyCORE-i.MX35 audio/touchscreen interface are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
87
phyCORE-i.MX35
X17
Line I N
JP6
MI C
CAN
Line OUT
USB
USB Host
USB-OTG
15.3.8
1
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
VI N
SJC-Mode
3V3
At t ent ion see manual
5V
Reset
Power On
1-W
I RE
CAN- by
CAN-pwr
CAN-PLD
5V DC 3A
CHARGER
RS232 aut oshut down
SERI AL 1+2
J13
RS232 disable
JP43
JP46
JP42
JP45
JP44
P1
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 25: phyCORE-iMX Carrier Board USB-Host Interface
The i.MX35x controller comes with an integrated USB-Host-Phy, so that there is nothing more needed
than an USB connector.
So the USB Host Transceiver (U26) that is realized on the i.MX Carrier Board is not needed with the
phyCORE-i.MX35 module. There is a possibility to bypass the USB Host Transceiver (U24) via the
jumpers JP42 to JP46 on the i.MX Carrier Board.
For further details and jumper settings have a look at Table 30.
88
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 30:
UBS Host Interface Jumper Settings for i.MX35 Module 7
JUMPER
SETTING
JP13
open
closed
USB Host transceiver U26 is disabled, USB Host is out of operation
USB Host transceiver U26 is active, USB Host is in operation
JP6
open
closed
1+2
2+3
1+2
2+3
Reset pin is held HIGH, no Reset asserted
Reset pin is connected to GPIO2_0, Reset can be asserted
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
open
closed
1+2
2+3
1+2
2+3
USB Host is managed on the i.MX module
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
JP42
JP43
JP44
JP45
JP46
7:
DESCRIPTION
Settings for the phyCORE-i.MX35 USB-Host interface are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
89
phyCORE-i.MX35
LCD Connectors
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
15.3.9
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
SW1
MMC-SD
VCC LCD
X23
CAMERA
DI SPLAY
X22
1
C
A
D
B
1
Figure 26: phyCORE-i.MX Carrier Board LCD Interfaces
The phyCORE-i.MX35 module comes with a 24-bit LCD interface. This 24-bit LCD interface is fully
connected to the molex connectors X1 of the i.MX35 module and can be used in the customers
application.
The phyCORE-i.MX Carrier Board has to support different i.MX modules, also modules with less than
24-bit LCD interfaces. That’s why Phytec designed LCD connectors for 18-bit LCD interfaces but also
for 24-bit LCDs.
So only the first 18-bits of the phyCORE-i.MX35 modules LCD interface (LD0 to LD17) are used on
the i.MX Carrier Board LCD connectors.
90
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3.9.1
Serial LCD
Note:
Serial LCD is not supported by the phyCORE-i.MX35 module, because the i.MX35x microcontroller
does not provide Serial LCD.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
91
phyCORE-i.MX35
Camera Interface
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
15.3.10
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
MMC-SD
VCC LCD
DI SPLAY
JP16
JP15
CAMERA
JP3
1
C
A
D
B
1
X8
X7
Figure 27: phyCORE-i.MX Carrier Board Camera Interface
The camera interface can be managed by the signal x_CSI_ENABLE connected to GPIO3_5 of the
i.MX35 module.
92
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
Table 31:
JUMPER
JP3
Camera Interface Jumper Settings for i.MX35 Module
SETTING
closed
open
DESCRIPTION
JP16
1+2
2+3
Outputs of level shifter U12 are enabled, CSI is active
Outputs of U12 are disabled or GPIO x_CSI_ENABLE can be used to
control U12
Jumper settings to chance camera sensor specific I²C address. For more
information refer to the manual of the used camera sensor.
JP15
1+2
2+3
Use of Camera Connector X7 with VCC_CAM supply (3.3 V)
Use of Camera Connector X8 with external VCC_CAM_EXT supply
 PHYTEC Messtechnik GmbH 2010
L-734e_1
93
phyCORE-i.MX35
15.3.10.1
PHYTEC Camera Connector
Note:
The phyCORE-i.MX35 module uses a 10-bit camera interface (CSI_D6 to CSI_D15) at the Camera
Connectors.
94
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
JTAG Interface
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
15.3.11
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
JP12
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
X6
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 28: phyCORE-iMX Carrier Board JTAG Interface
Two JTAG modes are provided by the phyCORE-i.MX35 module dependent on the status of the
sjc_mod signal of the i.MX35x controller.
Jumper JP12 can be used to select the JTAG mode the controller should operate in.
 PHYTEC Messtechnik GmbH 2010
L-734e_1
95
phyCORE-i.MX35
Table 32:
JUMPER
JP12
8:
96
JTAG Jumper Settings for phyCORE-i.MX35 Module 8
SETTING
closed
NAME
Daisy chain ALL
open
SJC only
DESCRIPTION
For common software debug
production)
IEEE 1149.1 JTAG compatible mode
(High
speed,
Default settings for the phyCORE-i.MX35 JTAG mode are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
15.3.12 Complete Jumper Setting List for
phyCORE-i.MX35 on the i.MX Carrier Board
The following table contains all jumper settings that can be set on the phyCORE-i.MX Carrier Board. Also it
shows the default jumper settings for using the phyCORE-i.MX35 module with the i.MX Carrier Board.
These default jumper settings are normally done prior to delivery.
Table 33:
JUMPER
SETTING
JP1
Open
Closed
RS-232 transceivers are enabled
RS-232 transceivers are disabled
JP2
Open
Closed
RS-232 auto shutdown is disabled
RS-232 auto shutdown is enabled
JP3
Open
Closed
Camera interface is managed by x_CSI_ENABLE
Camera interface is always enabled
JP4
Open
Closed
Open
Closed
Compact Flash is in overwrite mode
Compact Flash is usable
Compact-Flash is Slave
Compact-Flash is Master
Open
Closed
1+2
2+3
USBH2 transceiver Reset is not controllable
USBH2 transceiver Reset is controllable via GPIO
CAN is managed on the Carrier Board
CAN is managed on the module
JP5
JP6
JP7
DESCRIPTION
JP8
1+2
2+3
CAN signals is are on the level VCC_CAN (from mapper)
CAN signals is are on the level VCC_5V
JP9
1+2
2+3
1+2
2+3
CAN is supplied via on Board 5 V Power-Supply
CAN is supplied via an external Power-Supply
CAN is managed on the Carrier Board
CAN is managed on the module
JP10
JP11
1+2
2+3
Open
Closed
CAN is supplied via on Board Power-Supply
CAN is supplied via an external Power-Supply
Only the System JTAG Controller
All core's TAPS in a single daisy chain
JP13
Open
Closed
USB Host transceiver is disabled
USB Host transceiver is enabled
JP14
Open
Closed
VCC_FUSE = 2.775 V (no FUSE programming)
VCC_FUSE = 3.3 V (use only for FUSE programming)
JP15
1+2
2+3
JP12
9:
Jumper Settings for i.MX35 Module on i.MX Carrier Board 9
Camera interface supplied via on-board 3.3 V supply
Camera interface is supplied via external supply
Default settings are in bold blue
 PHYTEC Messtechnik GmbH 2010
L-734e_1
97
phyCORE-i.MX35
JP16
JP17
JP18
CMOS-Sensor I²C address is 0x55
CMOS-Sensor I²C Address is 0x33
Compact Flash expansion connector is enabled
Compact Flash expansion connector is disabled
MMC driver is disabled
MMC driver is enabled
JP19
1+2
2+3
Stereo output is managed on the baseboard
Stereo output is managed on the module
JP20
1+2
2+3
Stereo output is managed on the baseboard
Stereo output is managed on the module
JP21
1+2
2+3
Stereo MIC is managed on the baseboard
Stereo MIC is managed on the module
JP22
1+2
2+3
Stereo MIC is managed on the baseboard
Stereo MIC is managed on the module
JP23
1+2
2+3
Stereo LINE IN is managed on the baseboard
Stereo LINE IN is managed on the module
JP24
1+2
2+3
Stereo LINE IN is managed on the baseboard
Stereo LINE IN is managed on the module
JP25
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP26
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP27
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP28
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP29
1+2
2+3
1+2
3+4
5+6
1+3,2+4
3+5,4+6
Backup voltage is supplied by ext. LICELL
Backup voltage is supplied by onboard Goldcap
VCC_BOOT is deep-sleep test voltage
VCC_CLK is deep-sleep test voltage
VCC_JTAG is deep-sleep test voltage
Power source is Power Over Ethernet (POE)
Power source is 5 V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
Open,Open
JP30
JP31
98
1+2
2+3
open
Closed
1+2
2+3
No power switching, direct supply from VCC_3V3
Separate supply path
 PHYTEC Messtechnik GmbH 2010
L-734e_1
The phyCORE-i.MX on the Development Board
JP34
1+2,3+4
Open,Open
JP35
Open
Closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
Open
Closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP37
Open
Closed
Chargemode is Single Path
Chargemode is Dual Path
JP38
1+2,3+4
Open,Open
1+2,3+4
Open,Open
JP39
JP40
No power switching, direct supply from VCC_3V3
Separate supply path
Power switching, supply from 5 V adapter or POE
No power switching, direct supply from VCC_3V3
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
Open
Closed
1+2
2+3
1+2
2+3
No power switching active, minimum circuit
Power switching active
USB VBUS power enable managed on baseboard
USB VBUS power enable managed on module
USB VBUS overcurrent managed on the baseboard
USB VBUS overcurrent managed on the module
open
closed
1+2
2+3
1+2
2+3
open
closed
open
closed
open
closed
open
closed
USB Host is managed on the module
USB Host is managed on the baseboard
USB Host is managed on the baseboard
USB Host is managed on the module
USB Host is managed on the baseboard
USB Host is managed on the module
Reset of audio/touch device is not controllable
Reset of audio/touch device is controllable via GPIO
IRQ of audio/touch device is not controllable
IRQ of audio/touch device is controllable via GPIO
PENDOWN of audio/touch device is not controllable
PENDOWN of audio/touch device is controllable via GPIO
SD card write protect is not connected to the module
SD card write protect is connected to the module
JP602
Open
Closed
PC_RW inverted
PC_RW non-inverted
JP604
Open
Closed
CF power is manged by x_EXP007
Force enabling VCC_CFL
JP42
JP43
JP44
JP45
JP46
JP47
JP48
JP49
JP50
 PHYTEC Messtechnik GmbH 2010
L-734e_1
99
phyCORE-i.MX35
16 Revision History
Date
Version numbers
Changes in this manual
04-June-2009
Manual L-734e_0
PCM-043
PCB# 1315.2
PMA-005
PCB# 1318.2
PCM-970
PCB# 1280.4
Manual L-734e_1
PCM-043
PCB# 1315.4
PMA-005
PCB# 1318.2
PCM-970
PCB# 1280.4
First draft, Preliminary documentation.
Describes the phyCORE-i.MX35 with the i.MX35
Mapper and the i.MX Carrier Board.
17-June-2010
100
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Revision History
 PHYTEC Messtechnik GmbH 2010
L-734e_1
101
phyCORE-i.MX35
17 Component Placement Diagram
PHYTEC
PCM-043
C97
C182
R83
C87
L15
C94
TP6
C102
TP7
C179
C177
L14
C106
C142
U16
C176
R28 J23
U17
C171
C175
R93
R52
Q1
R26R75
C173
R84
L16
C178
C174
R79 R80 R77
RN4
C57
C186
R78
C61
U18
C169
C180
C181
C183
TP8
R73
C74
C25
C75
C187
C84 C63
C70
C115
R72
C185
C72
C81
C73
C189
U13
J12
U14
C190
R71 R69
R70
C188
U15
C104
C88
C145
R45
C121
C45
C50 C54
C89
C143
R47
C111
C124
C6
R35
C116 C114 C31
C86
C191
R50 R20
U9
C69
U19
C113
R94
C42
C112
C154
C32
C91 TP9
C67
C153 R22
U8
U7
C55
U6
R21
C33 C159
R51
U1
J10
C13
C120
R49
C184
C123
C46
C40
C110
U10
C96
C15
C168
C161
U4
R39
R40
R38
J8 J5 J7 J9
XT2
R37
R23
C79
R4 R5
R30
C68
J24 J21
TP4
RN2
J15 J14 J11
C164
TP3
C76
TP1
C77
C90
TP2
U2
J1
RN1
R29
C160
C165
XT3
R43
C49
TP5
X2
Figure 29:
102
phyCORE-i.MX35 Component Placement (Top View)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Component Placement
R82
X1B
X1A
TP11
R81
C170 C172
C71
TP16
L7 C151
L6
C149
C27
C152
RN3
C11
C12
U12
C1
R48
C30
C108
U5
C28
R46
C109
R42
R44
C166
C93
XT1
C163
C29
C156
R41
TP15
C92
C162
C37
C78
C24
C80
TP17 TP18
C43
C118
C44
C36
C82
C158
C95
C10
R36
C122
R68
C38
U11
U20
C21
C20 C150
C8
R27
C157 C119
C196 C197
TP13 C22 C192
C155
C193
R99 R98
C194
TP12
L3
C17
R32
R1
R3
R2
C107
TP10
C105
C66
C85
C100
R31
R34
R33
C139
L12 L4 L13 L5
C16
C18
C14
C134
C167
C60
L2
R76
C98
C9
L1
C125
C83
C101
C103
C144
C140
C136 C56 C146
C48
C51
C130
C53
C58
C52
C47C147 C133
C3
C131
C35 C7
C2
C129
C62
C59
C117
R24
C34 R74
C126
C4
C65 C39
C64
C137
C128
C99
C26
R25 C148
R96
C127
C23
C141 C138
C195
R97 R100
C132
TP14
R95
C135
C41
R9
R7
R6
R8
C5
R13
U3
C19
R17
R11 R15 R19
R12 R16
R10
R14
R18
J13 J22
J2 J3 J4
X2
Figure 30: phyCORE-i.MX35 Component Placement (Bottom View)
 PHYTEC Messtechnik GmbH 2010
L-734e_1
103
phyCORE-i.MX35
Index
1
N
10/100 Mbps Ethernet................. 41
NAND Flash...........................30, 34
B
O
Block Diagram ............................... 4
Operating Temperature ...............47
Operating Voltage........................47
C
COM Port .................................... 38
D
Debug Interface........................... 43
Dimensions.................................. 47
E
P
phyCORE-connector .................7, 8
Physical Dimensions ...................46
Pin Description ..............................7
Pinout.............................................9
Power Consumption ....................47
R
EEPROM............................... 30, 35
EEPROM Write Protection .......... 37
EMC .............................................. 1
Emulator ...................................... 45
RS-232 Interface .........................38
RS-232 Level...............................38
RS-232 Transceiver.....................38
F
S
Features ........................................ 3
SDR SDRAM ...................30, 32, 33
SDRAM..................................32, 33
SMT Connector .............................7
Storage Temperature ..................47
System Memory...........................30
H
Humidity ...................................... 47
I
I²C EEPROM ............................... 35
ISP1301....................................... 40
J
T
Technical Specifications ..............46
TTL Level.....................................38
J603............................................. 37
JA-002 ......................................... 45
JTAG Interface ............................ 43
JTAG-Emulator Adapter .............. 45
104
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Index
U
U300............................................ 40
U301............................................ 38
U302............................................ 38
U600............................................ 34
U601............................................ 35
U602...................................... 32, 33
U603...................................... 32, 33
UART3......................................... 38
UART5......................................... 38
USB Device ................................. 40
 PHYTEC Messtechnik GmbH 2010
L-734e_1
USB Host .....................................40
USB On-The-Go ..........................40
USB OTG ....................................40
W
Weight..........................................47
X
X201 ............................................43
105
phyCORE-i.MX35
Document:
Document number:
phyCORE-i.MX35
L-734e_1
How would you improve this manual?
Did you find any mistakes in this manual?
page
Submitted by:
Customer number:
Name:
Company:
Address:
Return to:
PHYTEC Technologie Holding AG
Postfach 100403
D-55135 Mainz, Germany
Fax : +49 (6131) 9221-33
106
 PHYTEC Messtechnik GmbH 2010
L-734e_1
Published by
 PHYTEC Messtechnik GmbH 2010
Ordering No. L-734_1
Printed in Germany