Apple Macbook Pro A1386 (MBP 15MLB)

C

B

D

8 7

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

(.csa)

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TABLE_TABLEOFCONTENTS_ITEM 45


Contents

Table of Contents

System Block Diagram

Power Block Diagram

Power Block Diagram

BOM Configuration

JTAG Scan Chain

Functional / ICT Test

Power Aliases

Signal Aliases

CPU FSB

CPU Power & Ground

CPU Decoupling & VID eXtended Debug Port(MiniXDP)

MCP CPU Interface

MCP Memory Interface

MCP Memory Misc

MCP PCIe Interfaces

MCP Ethernet & Graphics

MCP PCI & LPC

MCP SATA & USB

MCP HDA & MISC

MCP Power & Ground

MCP79 A01 Silicon Support

MCP Standard Decoupling

MCP Graphics Support

SB Misc

FSB/DDR3/FRAMEBUF Vref Margining

DDR3 SO-DIMM Connector A

DDR3 SO-DIMM Connector B

DDR3 Support

Right Clutch Connector

SECUREDIGITAL CARD READER

Ethernet PHY (RTL8211CL)

Ethernet & AirPort Support

Ethernet Connector

FireWire LLC/PHY (FW643)

FireWire Port Power

FireWire Ports

SATA Connectors

External USB Connectors

Front Flex Support

SMC

SMC Support

LPC+SPI Debug Connector

K19 SMBUS CONNECTIONS

6

Date

Sync

12/05/2008

DDR

12/12/2007

T18_MLB

12/12/2007

T18_MLB

N/A

N/A

12/18/2008

DDR

07/22/2008

DDR

N/A

N/A

(MASTER)

(MASTER)

(MASTER)

(MASTER)

11/12/2008

M98_MLB

11/12/2008

M98_MLB

10/17/2007

M87_MLB

11/12/2008

M98_MLB

12/12/2008

T18_MLB

12/12/2008

T18_MLB

12/12/2008

T18_MLB

04/04/2008

T18_MLB

12/12/2008

T18_MLB

12/12/2008

T18_MLB

12/12/2008

T18_MLB

12/12/2008

T18_MLB

12/12/2008

T18_MLB

03/31/2008

T18_MLB

06/18/2008

T18_MLB

06/18/2008

AMASON_M98_MLB

12/15/2008

DDR

12/05/2008

DDR

07/22/2008

DDR

07/22/2008

DDR

12/12/2008

T18_MLB

12/08/2008

MUXGFX

01/30/2009

VEMURI

07/01/2008

SUMA_M98_MLB

07/01/2008

SUMA_M98_MLB

12/16/2008

AMASON_M98_MLB

08/14/2008

SENSOR

12/22/2008

YUN_K19_MLB

08/14/2008

SENSOR

12/04/2008

PWRSQNC

11/14/2008

M98_MLB

12/04/2008

PWRSQNC

12/12/2008

T18_MLB

12/19/2008

DDR

05/09/2008

CHANGZHANG

12/19/2008

DDR

5 4

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TABLE_TABLEOFCONTENTS_ITEM 90


Contents

Current & Voltage Sensing

Current Sensing

Thermal Sensors

Fan Connectors

WELLSPRING 1

WELLSPRING 2

Sudden Motion Sensor (SMS)

DEBUG SENSORS AND ADC

SPI ROM

AUDIO: CODEC/REGULATOR

AUDIO: LINE INPUT FILTER

AUDIO: HEADPHONE FILTER

AUDIO: SPEAKER AMP

AUDIO: JACKS

AUDIO: JACK TRANSLATORS

DC-In & Battery Connectors

PBus Supply & Battery Charger

IMVP6 CPU VCore Regulator

5V / 3.3V Power Supply

1.5V DDR3 Supply

MCP CORE REGULATOR

CPU VTT / 1V05 S0 Power Supply

Misc Power Supplies

Power Control

Power FETs

NV G96 PCI-E

NV G96 Core/FB Power

NV G96 Frame Buffer I/F

GDDR3 Frame Buffer A (Top)

GDDR3 Frame Buffer B (Top)

NV G96 GPIO/MIO/Misc

G96 GPIOs & Straps

NV G96 Video Interfaces

GPU (G96) CORE SUPPLY

LVDS Display Connector

Muxed Graphics Support

DisplayPort Connector

1.1V / 1V8 FB Power Supply

Graphics MUX (GMUX)

LCD BACKLIGHT DRIVER

LCD Backlight Support

Misc Power Supplies

CPU/FSB Constraints

Memory Constraints

MCP Constraints 1

Date

Sync

08/14/2008

SENSOR

YUN_K19_MLB

12/10/2008

YUN_K19_MLB

12/22/2008

10/17/2007

M87_MLB

06/18/2008

AMASON_M98_MLB

01/05/2009

PWRSQNC

08/14/2008

SENSOR

12/19/2008

DDR

07/01/2008

CHANG_M98_MLB

03/16/2009

AUDIO

03/16/2009

AUDIO

03/16/2009

AUDIO

03/16/2009

AUDIO

03/16/2009

AUDIO

03/16/2009

AUDIO

YUN_K19_MLB

12/16/2008

12/10/2007

M99_MLB

10/17/2007

M87_MLB

12/17/2008

PWRSQNC

12/05/2008

DDR

11/14/2008

M98_MLB

12/14/2007

M99_MLB

12/14/2007

M99_MLB

12/17/2008

PWRSQNC

12/05/2008

DDR

07/10/2008

MUXGFX

07/10/2008

MUXGFX

07/10/2008

MUXGFX

07/10/2008

MUXGFX

07/10/2008

MUXGFX

07/10/2008

MUXGFX

07/09/2008

MUXGFX

07/10/2008

MUXGFX

10/17/2007

M87_MLB

12/19/2008

DDR

12/05/2008

AMASON_M98_MLB

07/10/2008

MUXGFX

07/10/2008

MUXGFX

07/10/2008

MUXGFX

12/12/2008

DDR

07/02/2008

YITE_M98_MLB

02/01/2008

MUXGFX

02/18/2008

MUXGFX

02/18/2008

MUXGFX

02/18/2008

MUXGFX

3

SCHEM,CORNHOLE,K19

PVT 04/24/2009

?

REV ZONE

2

?

ECN

?

DESCRIPTION OF CHANGE

1

CK

APPD

DATE

ENG

APPD

DATE

?

?

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Contents

MCP Constraints 2

Ethernet Constraints

FireWire Constraints

SMC Constraints

GPU (G96) CONSTRAINTS

Project Specific Constraints

PCB Rule Definitions

Date

Sync

02/18/2008

MUXGFX

02/18/2008

MUXGFX

02/18/2008

MUXGFX

02/18/2008

MUXGFX

02/18/2008

MUXGFX

02/21/2008

MUXGFX

01/22/2008

M99_MLB

D

C

B

A

ALIASES RESOLVED

Schematic / PCB #’s

PART NUMBER QTY DESCRIPTION

051-7892

820-2523

1

1

SCHEM,CORNHOLE,K19

PCBF,CORNHOLE,K19

DRAWING

ABBREV=DRAWING

TITLE=MLB

LAST_MODIFIED=Fri Apr 24 15:23:24 2009

REFERENCE DES

SCH

PCB

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

8

7 6 5 4

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

3

APPLE INC.

METRIC

DRAFTER

ENG APPD

QA APPD

DESIGN CK

MFG APPD

DESIGNER

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

SCHEM,MBP 15MLB

RELEASE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SCALE

NONE

SIZE

D

2

DRAWING NUMBER

051-7892

SHT

1

REV.

A.0.0

1

OF

97

A

D

C

B

A

8

8

7

J4510

J4520

SATA

Conn

HD

PG 38

SATA

Conn

ODD

PG 38

J9000

LVDS

CONN

PG 71

J9400

DISPLAY PORT

CONN

PG 71

1.05V/3GHZ.

1.05V/3GHZ.

6

GPIOs

CLK

SYNTH

SATA

PG 19

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 17

U1000

5 4 3 2

U1300

INTEL CPU

2.X OR 3.X GHZ

PENRYN

PG 9

FSB

64-Bit

800/1067/1333 MHz

PG 13

FSB INTERFACE

XDP CONN

PG 12

MAIN

MEMORY

PG 14

2 UDIMMs

DDR2-800MHZ

DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

Misc

PG 24

SPI

PG 20

U6100

SPI

Boot ROM

PG 52

NVIDIA

MCP79

U1400

LPC

PG 18

J4900

B,0 BSB

SMC

ADC Fan

Ser

Prt

PG 41

J6950

DC/BATT

PG 60

U4900

TEMP SENSOR

PG 41

POWER SENSE

PG 45

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

PG 48,49

J5100

LPC Conn

Port80,serial

PG 43

POWER SUPPLY

PWR

CTRL

J4720

Bluetooth

PG 40

J4700

TRACKPAD/

KEYBOARD

PG 40

J4710

IR

PG 40

J4710

CAMERA

PG 40

J3900,4635,4655

EXTERNAL

USB

Connectors

PG 39

RGMII

PG 17

PCI

(UP TO FOUR PORTS)

PG 18

SMB

PG 20

HDA

PG 20

DIMM’s

SMB

CONN

PG 44

J3400

Mini PCI-E

AirPort

PG 28

7 6

U3700

GB

E-NET

88E1116

PG 31

U3900

E-NET

Conn

PG 33

5

U6200

Audio

Codec

PG 53

U6301

Line In

Amp

PG 54

U6400

HEADPHONE

Amp

PG 55

U6500

Line Out

Amp

PG 56

U6600,6605,6610,6620

Speaker

Amps

PG 57

J6800,6801,6802,6803

Audio

Conns

PG 59

4 3

1

D

C

B

System Block Diagram

SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

2

OF

97

2 1

8 7 6 5 4 3 2 1

D

B

A

AC

ADAPTER

IN

J6950

C

3S2P

(9 TO 12.6V)

MCP79

SLP_S5#(H17)

SLP_S3#(G17)

U1400

(PAGE 14~22)

DCIN(16.5V)

M98 POWER SYSTEM ARCHITECTURE

CHGR_EN

(S5)

6A FUSE

U5705

A

ENABLES

LIO_DCIN_ISENSE

VIN

(PAGE 60)

PBUS SUPPLY/

BATTERY CHARGER

VOUT

D6905

D6905

PPVBAT_G3H_CHGR_REG

8A FUSE

PPVIN_G3H_P3V42G3H

PBUSB_VSENSE

PPBUS_G3H

V

Q5315

GPU VCORE

VIN

ISL6263B

VOUT

PM_GPUVCORE_EN U8900

EN_PSV

PGOOD

(PAGE 78)

ENABLE

3.425V G3HOT

LT3470

U6990

(PAGE 59)

PP3V42_G3H_REG

SMC_GPU_VSENSE

U5498

A

V

GPUVCORE_IOUT

PPVCORE_GPU_REG

(18A MAX CURRENT)

GPUVCORE_PGOOD

A U5715

SMC_BATT_ISENSE

SMC PWRGD

RN5VD30A-F

U5000

(PAGE 43)

CPUVTTS0_EN

BATT_POS_F

Q7055

ISL6258A

U7000

PPVBAT_G3H_CHGR_R

IMVP_VR_ON_R

CPU VCORE

VIN

ISL9504B

VOUT

VR_ON

U7100

PGOOD

(PAGE 61)

U5400 V

SMC_CPU_VSENSE

A

CPUVCORE_IOUT

VR_PWRGD_CLKEN_L

PPVCORE_CPU_S0

VR_PWRGOOD_DELAY

Q7920

PP5V_S0_FET

CHGR_BGATE

PPBUS_G3H

P3V3S3_EN

P5VS0_SS

Q7900

PP5V_S3_FET

Q3801

WOW_EN

Q3805

PM_ENET_EN

PM_ENET_EN_L

P5VS3_EN

LIO_S3_EN

PM_WLAN_EN_L

PM_ENET_EN_L

RC

DELAY

RC

DELAY

RC

DELAY

P1V8S0_EN

MCPDDR_EN

RC

DELAY

CPUVTTS0_EN

MCPCORES0_EN

RC

DELAY

PM_SLP_S3_L

P5VRIGHT_EN

Q3800

WOL_EN

SMC_ADAPTER_EN

RC

DELAY

P5VS0_EN

(S0)

P3V3S0_EN

(S0)

PBUSVSENS_EN

(S0)

PM_SLP_S3_DELAY_L

(S0)

SMC

U4900

P60

(PAGE 42)

P5V_RT_EN

SMC_PM_G2_EN

(S5)

U7859

P1V1GPU_EN

P1V8FB_EN

EN1 VIN

1.103V(L/H)

VOUT1

EN2

1.8V(R/H)

VOUT2

TPS51124

U9500

(PAGE 82)

VIN

U7400

EN/PSV

SC417

VOUT

(PAGE 64)

ENL

PGOOD

PP5V_RT_REG

P5V_RT_PGOOD

P3V3S5_EN

PP1V1_S0GPU_REG

PP1V8_GPU_REG

VIN

5V

(L/H)

VOUT1

3.3V

(R/H)

VOUT2

EN0

TPS51125

U7201

(PAGE 62)

PGOOD1,2 VREG3

PP5V_S5_REG

(8A MAX CURRENT)

PP3V3_S5_REG

(5.5A MAX CURRENT)

P5V3V3_S5_PGOOD

BKLT_EN

DDRREG_EN

DDRVTT_EN

VIN

GOSHAWK6P

U9701

ENA

(PAGE 84)

VOUT

PPVOUT_S0_LCDBKLT

P1V2ENET_EN

ENETAVDD_EN

VIN LTC3407

RUN2 VOUT1

(PAGE 33)

RUN1

U3850

VOUT2

PPVIN_S0_DDRREG_LDO

VIN

1.8V

S5

VLDOIN

VOUT1

PPDDR_S3_REG

(12A MAX CURRENT)

S3 0.9V

VOUT2 PPVTT_S0_DDR_LDO

TPS51116

U7300

(PAGE 63)

MCPCORES0_EN

P1V05S0_EN

MCP_CORE

EN2

VOUT2

1.1V

EN1

VIN

ISL6236

U7500

(PAGE 65)

VOUT1

PP1V9_ENET_REG

PP1V2_ENET_REG

MCPCPCORE_S0_REG

PP5V_RT_REG

(5A MAX CURRENT)

P5VS3_SS

Q7910

P3V3S3_SS

Q7930

PP3V3_S0GPU_FET

P3V3S0_SS

Q7970

P3V3GPU_SS

Q3810

PP3V3_S0_FET

P3V3_ENET_FET

P3V3ENET_EN_L

(25A MAX CURRENT)

PP5V_S3

PP3V3_S5

PP3V3_S3_FET

SMC_RESET_L

PP5V_S0

PP3V3_S0

PP1V5_S0_REG

RST*

V1

V2

V3

V4

LTC2900

U7870

(PAGE 68)

EN_PSV

VIN

VOUT

1.05V

TPS51117

U7600

(PAG 66)

PGOOD

P1V05S0_PGOOD

P5VRIGHT_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

P1V8S0_PGOOD

P1V5S0_PGOOD

S0PGOOD_PWROK

U2850

PPCPUVTT_S0_REG

(6A MAX CURRENT)

CPUVTTS0_PGOOD

U2830

VR_PWRGD_CLKEN

MCP_PS_PWRGD

MCP79

CK_PWRGD

PWRBTN#

VRMPWRGD

PLTRST*

RSMRST*

PLT_RST_L

CPU_PWRGD

PWROK

CPUPWRGD(GPIO49)

U1400

(PAGE 14~22)

V4

ISL8009

U7750

(PAGE 66)

ALL_SYS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

CPU

PWRGOOD

U1000

(PAGE 10,11)

RESET*

PP1V05_S5_MCP

SMC

RSMRST_OUT(P15)

PM_RSMRST_L

PWRGD(P12) 99ms DLY

IMVP_VR_ON(P16)

RSMRST_IN(P13)

PLT_RST*

PWR_BUTTON(P90)

P17(BTN_OUT)

IMVP_VR_ON

PM_PWRBTN_L

SMC_RESET_L

RST*

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

U4900

(PAGE 42)

D

C

B

Power Block Diagram



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

3

OF

97

8

7 6 5 4 3 2 1

D

8 7 6 5 4 3 2 1

D

C C

B B

A

8

7 6 5 4 3

Power Block Diagram

SYNC_MASTER=N/A SYNC_DATE=N/A


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

4

OF

97

2 1

8

D

BOM Variants

BOM NUMBER

630-9965

630-9966

630-9967

630-9968

630-9969

630-9970

085-0736

BOM NAME

PCBA,2.66GHZ,256SAM_VRAM,HB_AUDIO,K19

PCBA,2.66GHZ,256HYN_VRAM,HB_AUDIO,K19





K19 MLB DEVELOPMENT

7

K19 BOM Groups

BOM GROUP

K19_COMMON

K19_COMMON1

K19_COMMON2

K19_DEVEL_ENG

K19_DEVEL_PVT

K19_PROD

K19_PROGPARTS

6

BOM OPTIONS

K19_COMMON,DEVEL_BOM,EEE_6XN,CPU_2_66GHZ,FB_256_SAMSUNG

K19_COMMON,DEVEL_BOM,EEE_6XP,CPU_2_66GHZ,FB_256_HYNIX

K19_COMMON,DEVEL_BOM,EEE_6XQ,CPU_2_80GHZ,FB_512_SAMSUNG

K19_COMMON,DEVEL_BOM,EEE_6XR,CPU_2_80GHZ,FB_512_HYNIX

K19_COMMON,DEVEL_BOM,EEE_6XS,CPU_3_06GHZ,FB_512_SAMSUNG

K19_COMMON,DEVEL_BOM,EEE_6XT,CPU_3_06GHZ,FB_512_HYNIX

K19_DEVEL_PVT

BOM OPTIONS

ALTERNATE,COMMON,K19,K19_COMMON1,K19_COMMON2,K19_PROGPARTS

BOOT_MODE_USER,DPMUX_EN_S0,DP_CA_DET_EG_PLD,DP_ESD,EG_PWRSEQ_HW,EXTRACT_BUFF

GMUX_1V8,GPUVID_1P00V,GPU_SS_INT,ISL6258A,MCP_B03,MCPSEQ_SMC,MIKEY,MUXGFX,SMC_DEBUG_YES,XDP

BMON_ENG,DEBUG_ADC,GMUX_JTAG,LPCPLUS,VREFMRGN,XDP_CONN

BMON_PROD,LPCPLUS,NO_VREFMRGN,XDP_CONN

BMON_PROD,LPCPLUS_NOT,NO_VREFMRGN

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

BOM GROUP

FB_256_SAMSUNG

FB_256_HYNIX

FB_512_SAMSUNG

FB_512_HYNIX

C

Bar Code Labels / EEE #’s


826-4393

826-4393

1

1

LBL,P/N LABEL,PCB,28MM X 6 MM


826-4393

826-4393

826-4393

826-4393

1

1

1

1





BOM OPTIONS

VRAM4,VRAM_256_SAMSUNG

VRAM4,VRAM_256_HYNIX

VRAM4,VRAM_512_SAMSUNG

VRAM4,VRAM_512_HYNIX

REFERENCE DES

[EEE:6XN]

[EEE:6XP]

[EEE:6XQ]

[EEE:6XR]

[EEE:6XS]

[EEE:6XT]

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

EEE_6XN

EEE_6XP

EEE_6XQ

EEE_6XR

EEE_6XS

EEE_6XT

B

Module Parts

PART NUMBER QTY

337S3761 1

337S3682

337S3744

338S0710

338S0694

338S0654

341S2384

338S0563

341S2462

341S2503

335S0384

341S2456

338S0554

333S0507

333S0483

333S0511

333S0506

4

4

4

4

1

1

1

1

1

1

1

1

1

1

1

1

DESCRIPTION

IC,PDC,SLGLA,PRQ,2.66G,25W,1066,R0,3M,BGA

IC,PDC,SLGEM,PRQ,2.80G,35W,1066,E0,6M,BGA

IC,PDC,SLGKH,QS,3.06G,35W,1066,E0,6M,BGA

IC,MCP79MXT-B3,35X35MM,BGA1437

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IR,ENCORE II, CY7C63803-LQXC

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT,K19

IC,PSOC +W/USB,56PIN,MLF,K19

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

IC,EFI ROM,DEVELOPMENT,K19

IC,GPU,55nm,NV G96-GS,BGA969,LF

IC,SGRAM,GDDR3,16Mx32,1000MHZ,136 FBGA




Development BOM


085-0736 1 K19 MLB DEVELOPMENT

REFERENCE DES

U1000

U1000

U1000

U1400

U3700

U4100

U4800

U4900

U4900

U5701

U6100

U6100

U8000

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

REFERENCE DES

DEVEL

CRITICAL

CRITICAL

BOM OPTION

CPU_2_66GHZ

CPU_2_80GHZ

CPU_3_06GHZ

MCP_B03

SMC_BLANK

SMC_PROG

TPAD_PROG

BOOTROM_BLANK

BOOTROM_PROG

VRAM_256_SAMSUNG

VRAM_256_HYNIX

VRAM_512_SAMSUNG

VRAM_512_HYNIX

BOM OPTION

DEVEL_BOM

A

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

5

8

7 6 5

4

4 3

3 2

PART NUMBER

138S0603

ALTERNATE FOR

PART NUMBER

BOM OPTION

138S0602

353S1681

152S0276

341S2367

152S1034

157S0058

152S0915

128S0220

127S0062

152S0968

311S0447

338S0714

107S0138

107S0139

353S1294

152S0683

341S2366

152S0867

157S0055

152S0796

128S0262

127S0108

152S0966

311S0406

338S0554

107S0074

107S0075

REF DES COMMENTS:

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

Murata alt to Samsung

LMV2011,OPAMP. GBW

Maglayers alt to Dale/Vishay

Macronix alt to SST

Toko alt to Delta

Delta alt to TDK Magnetics

Maglayers alt to Cyntec IND

KEMET ALT TO SANYO

ROHM ALT TO KEMET

Maglayer alt to Delta

NXP alt to TI

Low Leakage G96 GPU

CYNTEC alt to YDS

CYNTEC alt to YDS

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

1

D

C

BOM Configuration

SYNC_MASTER=DDR SYNC_DATE=12/18/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

5

OF

97

2 1

B

8 7 6 5 4 3 2

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

D

82 81 80 77 70 69 68 63 60 59

28 25 24 22

55 51 49

21 19 18 13

48 47 45 43

8 7 6

39 37 29

PP3V3_S0

96 85 84

PPCPUVTT_S0

20 18 17 14 13 12 11 10

67 63

9

25

8 7

24 22

1

2

JTAG_ALLDEV

C0601

0.1UF

20%

10V

CERM

402

1

2

JTAG_ALLDEV

C0602

0.1UF

20%

10V

CERM

402

JTAG_ALLDEV

R0601

1

10K

5%

1/16W

MF-LF

402

2

C

B

NOSTUFF

R0602 1

0

5%

1/16W

MF-LF

402

2

From XDP connector

88 13 10 6 IN

88 13 10

IN

88 13 10 6 IN

88 13 10 6 IN

XDP_TCK

XDP_TDI

XDP_TMS

XDP_TRST_L

U1000

CPU

To XDP connector and/or level translator

88 10

XDP_TDO

XDP

1

R0603

0

2

5%

1/16W

MF-LF

402

PLACEMENT_NOTE=Place near pin U1000.AB3

XDP_TDO_CONN

OUT 13

XDP connector

88 13 10 6

88 13 10 6

88 13 10 6

XDP_TCK

XDP_TMS

XDP_TRST_L

JTAG_LVL_TRANS_EN_L

GMUX CPLD Programming Port

GMUX_JTAG

CRITICAL

J0600

1909782

M-RT-SM

7

1

2

3

4

5

6

PP3V3_S0

TDO

TDI

TMS

TCK

8

2

3

4

5

A1

A2

A3

A4

VCCA VCCB

U0600

NLSV4T244

UQFN

B1

B2

JTAG_ALLDEV

B3

B4

10

9

8

7

12 OE*

GND

From XDP connector or via level translator

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_MCP_TCK

JTAG_MCP_TDI

JTAG_MCP_TMS

JTAG_MCP_TRST_L

1

R0606

10K

2

5%

1/16W

MF-LF

402

6 13 21 76

U1400

MCP

13 21

13 21

6 13 21 76

NC

VCC

U0601

74LVC1G07

2 A

1 NC

Y

4

SOT886

GND

NC 5

NC

JTAG_MCP_TCK

GPU_JTAG_TDI

GPU_JTAG_TMS

JTAG_MCP_TRST_L

PLACEMENT_NOTE=Place close to U0600

1

R0607

0

2

5%

1/16W

MF-LF

402

6 13 21 76

76

6 76

U8000

GPU

6 13 21 76

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

JTAG_GMUX_TCK

JTAG_GMUX_TDI

JTAG_GMUX_TMS

84

9 19 84

9 19 84

U9200

GMUX

21

JTAG_MCP_TDO

76 6

TP_GPU_JTAG_TDO

84 17 9

JTAG_GMUX_TDO

XDP

1

R0604

0

2

5%

1/16W

MF-LF

402

PLACEMENT_NOTE=Place near pin U1400.F19

JTAG_MCP_TDO_CONN

OUT

13

XDP connector

81 79 77 76 70 69 8

PP3V3_S0GPU

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

6 76

NOSTUFF

1

R0605

10K

2

5%

1/16W

MF-LF

402


GPU_JTAG_TMS

6 76

1

D

C

B

A

8

7 6 5 4 3

JTAG Scan Chain



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

6

OF

97

2 1

D

C

B

A

8

Fan Connectors

FUNC_TEST

PP5V_S0

TRUE

TRUE

TRUE

TRUE

TRUE

FAN_LT_PWM

FAN_LT_TACH

FAN_RT_PWM

FAN_RT_TACH

GND

TRUE

7

66 67 70

8 39 44

49 51 63

83 85

49

49

49

49

3 TPs

5 TPs

LVDS Connector

FUNC_TEST

TRUE

TRUE

TRUE

PP3V3_S0

PP3V3_SW_LCD

PPVOUT_S0_LCDBKLT

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

80

84 85 96

7 53 80 85

LVDS_DDC_CLK

LVDS_DDC_DATA

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<0>





LVDS_CONN_A_CLK_F_N

LVDS_CONN_A_CLK_F_P

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<0>





LVDS_CONN_B_CLK_F_N

LVDS_CONN_B_CLK_F_P

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

BKL_ISEN1

BKL_ISEN2

BKL_ISEN3

BKL_ISEN4

BKL_ISEN5

BKL_ISEN6

80 81

80 81

80 81 95

80 81 95

80 81 95

80 81 95

80 81 95

80 81 95

80 95

80 95

80 81 95

80 81 95

80 81 95

80 81 95

80 81 95

80 81 95

80 95

80 95

80 85

80 85

80 85

80 85

80 85

80 85

85

85

85

85

85

85

TRUE

GND

5 TPs

IPD Flex Connector

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

PP3V3_S3_LDO

PP18V5_S3

Z2_CS_L

Z2_DEBUG3

Z2_MOSI

Z2_MISO

Z2_SCLK

Z2_BOOST_EN

Z2_HOST_INTN

Z2_CLKIN

Z2_KEY_ACT_L

Z2_RESET

PSOC_MISO

PSOC_MOSI

PSOC_SCLK

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

PSOC_F_CS_L

PICKB_L

GND

7 51

7 51

50 51

50 51

50 51

50 51

50 51

51

50 51

50 51

50 51

50 51

50 51

50 51

50 51

7 31 42 45 51 94

7 31 42 45 51 94

50 51

50 51

2 TPs

SD Card Connector

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

SD_D<7..0>

SD_CMD

SD_CLK

SD_CD_L

SD_WP

GND

TRUE

Speaker Connectors

32 93

32 93

32 93

32

32

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

BI_MIC_LO

BI_MIC_SHIELD

BI_MIC_HI

SPKRCONN_L_OUT_P

SPKRCONN_L_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

SPKRCONN_S_OUT_P

SPKRCONN_S_OUT_N

GND

59 60

59 60

59 60

58 59 96

58 59 96

58 59 96

58 59 96

58 59 96

58 59 96

2 TPs

6 TPs

8

7

6 5

Functional Test Points

SATA ODD Connectors

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

PP5V_SW_ODD

SMC_ODD_DETECT

SATA_ODD_R2D_P

SATA_ODD_R2D_N

SATA_ODD_D2R_C_N

SATA_ODD_D2R_C_P

GND

7 39 53

4 TPs

39 42

39 90

39 90

39 90

39 90

3 TPs

Keyboard Connector

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

PP3V3_S3

PP3V42_G3H

WS_KBD1

WS_KBD2

WS_KBD3

WS_KBD4

WS_KBD5

WS_KBD6

WS_KBD7

WS_KBD8

WS_KBD9

WS_KBD10

WS_KBD11

WS_KBD12

WS_KBD13

WS_KBD14

WS_KBD15_CAP

WS_KBD16_NUM

WS_KBD17

WS_KBD18

WS_KBD19

WS_KBD20

WS_KBD21

WS_KBD22

WS_KBD23

WS_KBD_ONOFF_L

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

KBDLED_ANODE

GND

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

7 51

7 8 21 27 31 32 45 50 52 70

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

50

50

50

50

50

50

50

2 TPs

Airport/BT/Camera Conn.

FUNC_TEST

TRUE

PCIE_MINI_D2R_P

TRUE

PCIE_MINI_D2R_N

TRUE

PCIE_MINI_R2D_P

TRUE

PCIE_MINI_R2D_N

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

MINI_CLKREQ_Q_L

TRUE

PCIE_WAKE_L

TRUE

MINI_RESET_CONN_L

TRUE

PP5V_WLAN

TRUE

PP3V3_S3_BT_F

TRUE

PP5V_S3_BTCAMERA_F

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

USB_CAMERA_CONN_P

TRUE

USB_CAMERA_CONN_N

TRUE

CONN_USB2_BT_P

TRUE

CONN_USB2_BT_N

17 31 90

17 31 90

31 90 96

31 90 96

31 96

31 96

31

17 31

31

31

31

31

7 31 42 45 51 94

7 31 42 45 51 94

31 96

31 96

31 96

31 96

TRUE

GND

10 TPs

SATA HDD Connector

FUNC_TEST

TRUE

TRUE

PP5V_S0_HDD_FLT

PP5V_S3_IR_R

7 39

39

4 TPs

4

DC Power Connector

FUNC_TEST

TRUE

TRUE

PP18V5_DCIN_FUSE

ADAPTER_SENSE

61

61

3 TPs

GND

TRUE 3 TPs

Battery Connector

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

PPVBAT_G3H_CONN

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SYS_DETECT_L

GND

61 62

3 TPs

7 42 45 61 62 94

7 42 45 61 62 94

61

6 TPs

Batt Signal Connector

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

PP3V42_G3H

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMC_BIL_BUTTON_L

SMC_LID_R

GND

Power Nets

45 46 50 61 62 64 69

44

43

40 42

7 8 21

22 26

3 TPs

7 42 45 61 62 94

7 42 45 61 62 94

42 43 61

61

3 TPs

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

PPVCORE_S0_CPU

PPVCORE_S0_MCP_REG

PP0V9R0V75_S0_DDRVTT

PPCPUVTT_S0

PP1V8R1V5_S0_FET

PP1V8_S0

PP3V3_S0

PP1V8R1V5_S3

PP3V3_S3

PP1V2R1V05_S5

PP3V3_S5

PP3V42_G3H

PPBUS_G3H

PP3V3_ENET_PHY

PP1V2R1V05_ENET

PP5V_S3

PP3V3_S5_AVREF_SMC

PP18V5_S3

PP3V3_S3_LDO

PPVOUT_S0_LCDBKLT

PP4V5_AUDIO_ANALOG

SMC_PM_G2_EN

PM_SLP_S4_L

PM_SLP_S3_L

PP1V05_S0_MCP_PLL_UF

PP5V_SW_ODD

PP5V_S0_HDD_FLT

BKL_VLDO

GND

8 11 12 46 63

8 22 24 46 66

8 28 29 65 70

6 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

8 11 12 16 24 28 29 39 68 69 70

8 18 25 55 69 70 84 87

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

8

28 29 30 65 70

7 8 21 27 31 32 45 50 52 70

8 22 24 34 68

8 18 20 22 24 26 30 34 37 38 44

54 64 68 69 70 82 87 96

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

8 37 46 61 62 64 65 66 67 79 83

86

8 18 24 33 34

8 18 24 33 34 37

8 9 31 39 40 41 43 51 53 55 64

65 70 79

42 43

7 51

7 51

7 53 80 85

55

42 64 69

21 40 42 43 69 70

21 34 37 42 69 82 84

8 24 68

7 39 53

7 39

85

6 TPs

3

55 7

55 7

20 7

20 7

18 7

18 7

NC_AUD_LO1_N_L

NC_AUD_LO1_P_L

NC_USB_10N

NC_USB_10P

NC_ENET_INTR_L

NC_ENET_PWRDWN_L

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

FSB_A_L<31..3>

FSB_ADS_L

FSB_ADSTB_L<1..0>

FSB_D_L<63..0>

FSB_DINV_L<3..0>

FSB_DSTB_L_N<3..0>

FSB_DSTB_L_P<3..0>

FSB_HIT_L

FSB_HITM_L

FSB_LOCK_L

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

SATA_HDD_R2D_P

SATA_HDD_R2D_N

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

IR_RX_OUT

SYS_LED_ANODE_R

GND

39 90

39 90

39 90

39 90

39 41

39

KBD Backlight Conn.

FUNC_TEST

TRUE

TRUE

TRUE

KBDLED_ANODE

SMC_KDBLED_PRESENT_L

GND

7 51

51

6 TPs

2 TPs

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

2

ICT Test Points

19 7

NC_LPC_DRQ0_L

15 7

16 7

16 7

16 7

16 7

TP_MEM_A_CKE<3..2>

NC_MEM_A_CLK2N

NC_MEM_A_CLK3N

NC_MEM_A_CLK3P

NC_MEM_A_CLK4P

NC_MEM_A_CS_L<3>

TP_MEM_A_ODT<3..2>

16 7

16 7

16 7

16 7

16 7

16 7

21 7

50 7

NC_MEM_B_CKE<2>

NC_MEM_B_CLK3P

NC_MEM_B_CLK4N

NC_MEM_B_CLK4P

NC_MEM_B_CLK5N

NC_MEM_B_ODT<2>

NC_MLB_RAM_SIZE

NC_P7_7

TP_PCI_AD<31..8>

TP_PCI_C_BE_L<3..0>

19 7

19 7

19 7

19 7

17 7

17 7

17 7

17 7

17 7

17 7

17 7

17 7

50 7

50 7

20 7

20 7

20 7

20 7

20 7

21 7

19 7

19 7

19 7

19 7

19 7

19 7

19 7

19 7

19 7

19 7

19 7

NC_PCI_CLK0

NC_PCI_CLK1

NC_PCI_DEVSEL_L

NC_PCI_FRAME_L

NC_PCI_GNT0_L

NC_PCI_GNT1_L

NC_PCI_INTW_L

NC_PCI_INTX_L

NC_PCI_INTZ_L

NC_PCI_IRDY_L

NC_PCI_PERR_L

NC_PCI_RESET1_L

NC_PCI_SERR_L

NC_PCI_STOP_L

NC_PCI_TRDY_L

NC_PCIE_CLK100M_PE4N

NC_PCIE_CLK100M_PE4P




NC_PCIE_PE4_D2RN

NC_PCIE_PE4_R2D_CN

NC_PE4_PRSNT_L

NC_PSOC_P1_3

NC_PSOC_SDA

NC_SATA_C_D2RP

NC_SATA_C_R2D_CN

NC_SATA_C_R2D_CP

NC_SATA_D_D2RN

NC_SATA_D_D2RP

NC_SB_A20GATE

USB_BT_N

USB_BT_P

USB_CAMERA_N

USB_CAMERA_P

SATA_ODD_D2R_UF_N

SATA_ODD_D2R_UF_P

DP_ML_C_P<3..0>

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

20 31 91

20 31 91

20 31 91

20 31 91

39 96

39 96

82 95

NC_AUD_LO1_N_L

NC_AUD_LO1_P_L

NC_USB_10N

NC_USB_10P

NC_ENET_INTR_L

NC_ENET_PWRDWN_L

NC_LPC_DRQ0_L

NC_MEM_A_CKE<3..2>

NC_MEM_A_CLK2N

NC_MEM_A_CLK3N

NC_MEM_A_CLK3P

NC_MEM_A_CLK4P

NC_MEM_A_CS_L<3>

NC_MEM_A_ODT<3..2>

NC_MEM_B_CKE<2>

NC_MEM_B_CLK3P

NC_MEM_B_CLK4N

NC_MEM_B_CLK4P

NC_MEM_B_CLK5N

NC_MEM_B_ODT<2>

NC_MLB_RAM_SIZE

NC_P7_7

NC_PCI_AD<31..8>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3..0>

NC_PCI_CLK0

NC_PCI_CLK1

NC_PCI_DEVSEL_L

NC_PCI_FRAME_L

NC_PCI_GNT0_L

NC_PCI_GNT1_L

NC_PCI_INTW_L

NC_PCI_INTX_L

NC_PCI_INTZ_L

NC_PCI_IRDY_L

NC_PCI_PERR_L

NC_PCI_RESET1_L

NC_PCI_SERR_L

NC_PCI_STOP_L

NC_PCI_TRDY_L






NC_PCIE_PE4_D2RN

NC_PCIE_PE4_R2D_CN

NC_PE4_PRSNT_L

NC_PSOC_P1_3

NC_PSOC_SDA

NC_SATA_C_D2RP

NC_SATA_C_R2D_CN

NC_SATA_C_R2D_CP

NC_SATA_D_D2RN

NC_SATA_D_D2RP

NC_SB_A20GATE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

7 55

7 55

7 20

7 20

7 18

7 18

Note.

NO_TEST properties are also on page9,26,43,50

6 5 4 3

19

7 17

7 17

7 17

7 17

7 17

7 17

7 19

7 19

7 19

7 19

7 17

7 17

7 50

7 50

7 20

7 20

7 20

7 20

7 20

7 21

7 19

7 19

7 19

7 19

7 19

7 19

7 19

7 19

7 19

7 19

7 19

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

7 19

7 16

7 16

7 16

7 16

7 16

7 16

7 21

7 50

19

16

7 15

7 16

7 16

7 16

7 16

16

D

C

B

Functional / ICT Test

SYNC_MASTER=N/A SYNC_DATE=N/A


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

7

OF

97

2 1

8 7

86

66 65

37 8

64

7

62 61 46

83 79 67

PPBUS_G3H

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=12.6V

PPBUS_G3H

6

7 8 37 46 61

PP3V3_S5

62 64 65 66 67 79 83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

D

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

63 46 8

PPBUS_CPU_IMVP_ISNS PPBUS_CPU_IMVP_ISNS



VOLTAGE=12.6V

MAKE_BASE=TRUE

PPBUS_CPU_IMVP_ISNS

62 61 8

PPDCIN_G3H

69

61 50

44 43

26 22 21 8 7

42 40

46 45

64 62

PP3V42_G3H

C

PPDCIN_G3H



VOLTAGE=16.5V

MAKE_BASE=TRUE

PPDCIN_G3H

PP3V42_G3H



VOLTAGE=3.42V

MAKE_BASE=TRUE

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

5V Rails

B

53

79

51

70

43

31 9

41

8 7

40 39

65 64 55

PP5V_S3 PP5V_S3

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.17MM

VOLTAGE=5.0V

MAKE_BASE=TRUE

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

PP5V_S3

51 49

85 83

44 39

70

8 7

67 66 63

A

11

63

8

46

7

12

PPVCORE_S0_CPU

22 8 7

66 46 24

PP5V_S0 PP5V_S0

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

Chipset "VCore" Rails

PPVCORE_S0_MCP_REG

PPVCORE_S0_CPU



VOLTAGE=1.25V

MAKE_BASE=TRUE

PPVCORE_S0_CPU

PPVCORE_S0_MCP_REG



VOLTAGE=1.05V

MAKE_BASE=TRUE

PPVCORE_S0_MCP_REG

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

7 8 37 46 61 62 64 65 66 67 79

83 86

8 46 63

8 46 63

70 52 50 45 32 31 27 21 8 7

PP3V3_S3

8 61 62

8 61 62

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40

PP3V3_S0

42 43 44 45 46 50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 39 44 49 51 63 66 67 70 83

85

7 8 11 12 46 63

7 8 11 12 46 63

7 8 22 24 46 66

PP1V2_S0

87 84 8

7 8 22 24 46 66

8

7 6

3.3V-2.5V Rails

PP3V3_S5



VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S3



VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

5 4 3 2 1

69 70 82 87 96

7 8 18 20 22

PP1V8_S0

24 26 30 34 37 38 44 54 64 68

500 mA max supply

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

96

18 20 22 24 26 30 34 37 38

7 44 54 64 68 69 70 82 87

82 87 96

30 34 37 38 44 54 64 68 69 70

70

7 8 18 20 22 24

65 30 29 28 8

26

PP1V8R1V5_S3

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

1.8V/DDR 1.5V Rails

190 mA

PP1V8_S0



VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_S0

PP1V8_S0

PP1V8_S0

PP1V8_S0

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

82 87 96

30 34 37 38 44 54 64 68 69 70

68 39

7 8 18 20 22 24

29 28 24 16 12 11 8

26

PP1V8R1V5_S0_FET

70 69

PP1V8R1V5_S3



VOLTAGE=1.5V

MAKE_BASE=TRUE

PP1V8R1V5_S3

PP1V8R1V5_S3

PP1V8R1V5_S3

PP1V8R1V5_S3

PP1V8R1V5_S3

PP1V8R1V5_S0_FET

MIN_LINE_WIDTH=0.6mm

MIN_NECK_WIDTH=0.17mm

VOLTAGE=1.5V

MAKE_BASE=TRUE

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

130 mA

500 mA

PP1V8R1V5_S0_FET

7 8 21 27 31 32 45 50 52 70

4771 mA

PP1V8R1V5_S0_FET

PP1V8R1V5_S0_FET

PP1V8R1V5_S0_FET

PP1V8R1V5_S0_FET

PP1V8R1V5_S0_FET

PP1V8R1V5_S0_FET

7 8 21 27 31 32 45 50 52 70

7 8 21 27 31 32 45 50 52 70

18 17 14 13

50 52 70

7 8 21 27 31 32

12

67

11 10

63 25

9 8

24

7 6

22 20

45

PPCPUVTT_S0 PPCPUVTT_S0

PPCPUVTT_S0

7 8 21 27 31 32 45 50 52 70

24

7 8 21 27 31 32

17 8

45 50 52 70

PP1V05_S0_MCP_PEX_AVDD

7 8 21 27 31 32 45

50 52 70

MAKE_BASE=TRUE

7 8 21 27 31 32 45 50 52 70

7 8 21 27 31

32 45 50 52 70

PPCPUVTT_S0

7 8 21 27 31 32 45 50 52 70

24 20 8

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

PPCPUVTT_S0


7 8 18 25 55 69 70 84 87

7 8 18 25 55 69 70 84 87 8

38 37

7 8 18 25 55 69 70 84 87

7 8 18 25 55 69 70 84 87

7 8 18 25 55 69 70 84 87



7 8 28 29 30 65 70

7 8 28 29 30 65 70

7 8 28 29 30 65 70

8 17 24

8 17 24

PPVP_FW

7 8 28 29 30 65 70

7 8 11 12 16 24 28

29 39 68 69 70


7 8 11 12 16 24 28 29 39 68 69

70

7 8 11 12 16 24 28 29 39 68 69

70

7 8 11 12 16 24 28 29 39 68 69

70




VOLTAGE=1.05V

MAKE_BASE=TRUE

"GPU" Rails

7 8 11 12 16 24 28

29 39 68 69 70

6

PP3V3_S0GPU

81 79 77 76 70 69 8

PP3V3_S0GPU



VOLTAGE=3.3V

MAKE_BASE=TRUE

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

PP3V3_S0GPU

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

8 20 24

37 36 8

7 8 28 29 30 65 70

37 36 8

29 30 65 70

PP1V0_FW

7 8 11 12 16 24 28 29 39 68 69

70

7 8 11 12 16 24 28 29 39 68 69

70

7 8 11 12 16 24 28 29 39 68 69

70

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

"FW" (FireWire) Rails

PP3V3_FW_FWPHY

PPVP_FW



VOLTAGE=12.6V

MAKE_BASE=TRUE

PPVP_FW

PPVP_FW

PP1V0_FW



VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V0_FW

PP3V3_FW_FWPHY



VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_FW_FWPHY

PP3V3_FW_FWPHY

PP3V3_S0GPU

PP3V3_S0GPU

PP3V3_S0GPU

PP3V3_S0GPU

8 37 38

8 37 38

8 37 38

8 36 37

8 36 37

8 36 37 38

8 36 37 38

8 36 37 38

7 8 24 68

6 8 69 70 76 77 79 81

6 8 69 70 76 77 79 81

6 8 69 70 76 77 79 81

6 8 69 70 76 77 79 81

6 8 69 70 76 77 79 81

D

6 8 69 70 76 77 79 81

C

PP3V3_S0



VOLTAGE=3.3V

MAKE_BASE=TRUE

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

18 17 14 13 12 11 10 9 8 7 6

67 63 25 24 22 20

PPCPUVTT_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

82 84 85 96

51 55 59 60 63 68 69 70 77 80

6 7 8 13 18 19 21 22 24 25 28

85 96

29 37 39 43 45 47 48 49

59 60 63 68 69 70 77 80 81

25 28 29 37 39 43 45 47 48 49

19 21 22 24

6 7 8 13 18 6600 MA

51 55

82 84

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

77 80 81 82 84 85 96

43 45 47 48 49 51 55 59 60 63

6 7 8 13 18 19 21 22 24 25 28

29 37 39

241 mA max load

68 69 70

84 85 96

59 60 63 68 69 70 77 80 81 82

29 37 39 43 45 47 48 49 51 55

6 7 8 13 18 19 21 22 24 25 28

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

4500 mA

1182 mA

1034 mA

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

70 77 80 81 82 84 85 96

47 48 49 51 55 59 60 63 68 69

21 22 24 25 28 29 37 39 43 45

6 7 8 13 18 19 PP1V2R1V05_S5

68 34 24 22 8 7

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

84 85 96

59 60 63 68 69 70 77 80 81 82

29 37 39 43 45 47 48 49 51 55

6 7 8 13 18 19 21 22 24 25 28

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

105 mA/241 mA

139 mA/ 0 mA

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PPCPUVTT_S0



VOLTAGE=1.05V

MAKE_BASE=TRUE

PPCPUVTT_S0

PPCPUVTT_S0

PPCPUVTT_S0

PPCPUVTT_S0

PPCPUVTT_S0

PPCPUVTT_S0

PP1V2R1V05_S5



VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V2R1V05_S5

PP1V2R1V05_S5

80 81 82 84 85 96

47 48 49 51 55 59 60 63 68 69

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45

70 77

65 27 8

PPVTTDDR_S3

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

68 69 70 77 80 81 84

39 43 45 47 48 49 51 55 59 60

8 13 18 19 21 22 24 25 28 29

6

7

85 96

85 96

80 81 82 84


37 39 43 45 47 48 49 51 55

82

84 85 96

7

59 60 63 68 69 70 77

29 37 39 43 45 47 48 49 51 55

6 7 8 13 18 19 21 22 24 25 28

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

85 96

47 48 49 51 55 59

PP1V2R1V05_ENET

6 7 8 13 18 19

21 22 24 25 28 29 37 39 43 45

60 63 68 69 70 77 80 81 82 84

80 81 82 84 85 96

37 39 43 45 47 48 49 51 55

13 18 19 21 22 24 25 28 29

8 59 60 63 68 69 70 77

6

59 60 63 68 69 70 77 80 81 82

29 37 39 43 45 47 48 49 51 55

6 7 8 13 18 19 21 22 24 25 28

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

PPVTTDDR_S3



VOLTAGE=0.75V

MAKE_BASE=TRUE


MIN_LINE_WIDTH=2 mm


VOLTAGE=0.9V

MAKE_BASE=TRUE




OR 0.75V

ENET Rails

PP1V2R1V05_ENET



VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V2R1V05_ENET

PP1V2R1V05_ENET

PP1V2R1V05_ENET

PP1V2R1V05_ENET

PP1V2R1V05_ENET

PP1V2_S0



VOLTAGE=1.2V

MAKE_BASE=TRUE

PP1V2_S0

34 33 24 18 8 7

PP3V3_ENET_PHY

8 84 87

PP3V3_ENET_PHY



VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_ENET_PHY

PP3V3_ENET_PHY

8 84 87

5 4 3

83 78 76 73 71

6 7 8 9 10 11 12 8

PP1V1_S0GPU_REG

13 14 17 18 20 22 24 25 63 67

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

8 27 65

7 8 28 29 65 70

7 8 28 29 65 70

7 8 28 29 65 70

7 8 18 24 33 34 37

7 8 18 24 33 34 37

7 8 18 24 33 34 37

7 8 18 24 33 34 37

7 8 18 24 33 34 37

7 8 18 24 33 34 37

7 8 18 24 33 34

7 8 18 24 33 34

7 8 18 24 33 34

78 70 8

PP1V8_GPUIFPX

7 8 22 24 34 68

75 74 73 72 47 9 8

PP1V8_S0GPU_ISNS

7 8 22 24 34 68

7 8 22 24 34 68

7 8 28 29 65 70

79 72 46 8

PPVCORE_GPU

83 47 8

PP1V8_S0GPU_ISNS_R

PP1V1_S0GPU_REG



VOLTAGE=1.1V

MAKE_BASE=TRUE

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V8_GPUIFPX



VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS



VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS

PP1V8_S0GPU_ISNS

PP1V8_S0GPU_ISNS

PP1V8_S0GPU_ISNS

PPVCORE_GPU



VOLTAGE=1.0V

MAKE_BASE=TRUE

PPVCORE_GPU

PP1V8_S0GPU_ISNS_R



VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS_R







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

8

OF

97

2

Power Aliases

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)


A

1

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 71 73 76 78 83

8 70 78

8 70 78

8 9 47 72 73 74 75

8 9 47 72 73 74 75

8 9 47 72 73 74 75

8 9 47 72 73 74 75

8 9 47 72 73 74 75

8 46 72 79

8 46 72 79

8 47 83

8 47 83

B

8 7 6 5 4 3 2 1

D

C

B

A

ZT0915

3R2P5

1

ZT0940

3R2P5

1

CPU signals

Left CPU

TM Hole

Thermal Module Holes

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

1

Right CPU

TM Hole

ZT0984

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Top GPU Right

TM Hole

ZT0980

STDOFF-4.5OD.98H-1.1-3.48-TH

1

1

TOP MCP LEFT

ZT0981

63

TP_IMVP6_CLKEN_L

9

MAKE_BASE=TRUE

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0985

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SH0900

STDOFF-4.5OD.98H-1.1-3.48-TH

SH0902

88 11

88 10


1

SM

70 65 26 9

CPU_VID<0..6>

MAKE_BASE=TRUE

CPU_BSEL<0..2>

MAKE_BASE=TRUE

MEM_VTT_EN

MAKE_BASE=TRUE

1

1

ZT0986

STDOFF-4.5OD.98H-1.1-3.48-TH

1

SH0903


SM

ZT0930

STDOFF-4.5OD.98H-1.1-3.48-TH

1

1 SH0916


SM

90 71

90 71

90 71

90 71

GPU signals

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

TP_IMVP6_CLKEN_L

IMVP6_VID<0..6>

=MCP_BSEL<0..2>

MEM_VTT_EN

63 88

14

9 26 65 70

=PEG_D2R_P<0..15>

=PEG_D2R_N<0..15>

17

17

=PEG_R2D_C_P<0..15>

=PEG_R2D_C_N<0..15>

9 63

17

17

ZT0987

STDOFF-4.5OD.98H-1.1-3.48-TH

TM Hole

SH0904


SM

1

RTL8211_CLK125

1

1

33 9

RTL8211_CLK125

MAKE_BASE=TRUE

GND

ZT0950

TH

1 GND

SL-3.1X2.7-6CIR-NSP

ZT0960

3R2P5

1 GND

ZT0990

3R2P5

1 GND

ZT0934

1

ZT0935

1

75 74 73 72 47 8

Frame Holes

STDOFF-4.0OD3.0H-TH

STDOFF-4.0OD3.0H-TH

GND

PP1V8_S0GPU_ISNS

90 18 9

90 18 9

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_IG_B_CLKN


18 9

NC_LVDS_IG_BKL_PWM


90 18 9

90 18 9

NC_LVDS_IG_A_DATAP<3>


NC_LVDS_IG_A_DATAN<3>


90 18 9

NC_LVDS_IG_B_DATAP<3>


90 18 9

NC_LVDS_IG_B_DATAN<3>


ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

STDOFF-4.5OD.98H-1.1-3.48-TH

1

R0900

10

1

1%

1/16W

MF-LF

402

2

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

GPU_FB_A_VREF_DIV

Extra FSB Pull-ups

88 63 14 10 OUT

88 14 10

88 14 13 10

OUT

OUT

88 14 10

88 14 10

OUT

OUT

CPU_DPRSTP_L

FSB_BREQ0_L

FSB_CPURST_L

CPU_INTR

CPU_NMI

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

NC_LVDS_IG_BKL_PWM





9 18 90

9 18 90

9 18

9 18 90

9 18 90

9 18 90

9 18 90

9 27 74

9 27 74

SH0910

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1 SH0911


SM

1

SH0914


SM

1

GND_CHASSIS_AUDIO_JACK

59

ZT0951

4.0OD1.85H-M1.6X0.35

1

ZT0952

4.0OD1.5H-M1.6X0.35

1

ZT0953

4.0OD1.5H-M1.6X0.35

1

ZT0954

4.0OD1.85H-M1.6X0.35

1

Bosses

84 17 9 6

JTAG_GMUX_TDO

MAKE_BASE=TRUE

84 18 9

84 18 9

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

MCP79 PCIe PRSNT# Straps

These need work. Add other PRSNT# straps if needed. .

18 9

MCP_MII_PD

MAKE_BASE=TRUE

1 R0930

47K

2

5%

1/16W

MF-LF

402

MCP_MII_PD

MCP_MII_PD

MCP_MII_PD

1

R0931

2

22

5%

1/16W

MF-LF

402

NC_USB_EXTDP

91 20 9


91 20 9

NC_USB_EXTDN


91 20 9

91 20 9

NC_USB_MINIP

NC_USB_MININ

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

96 32 20 9

96 32 20 9

91 20 9

91 20 9

USB_CARDREADER_P

MAKE_BASE=TRUE

USB_CARDREADER_N

MAKE_BASE=TRUE

NC_USB_EXCARDP


NC_USB_EXCARDN


JTAG_GMUX_TDO

6 9 17 84

55 53 51 43 41 40 39 31 8

79 70 65

7

64

PP5V_S3

LVDS_IG_BKL_ON

9 18 84

ETHERNET ALIASES

LVDS_IG_PANEL_PWR

9 18 84

NO STUFF

R0925

0

1 2

PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

5%

1/16W

MF-LF

402

R0927

0

1 2

5%

1/16W

MF-LF

402

NO STUFF

PEG_PRSNT_L

MAKE_BASE=TRUE

R0926

0

1 2

5%

1/16W

MF-LF

402

OUT

OUT

17 37

17

EG_CLKREQ_OUT_L

9 18

9 18

9 18

IN

84

GND

GND

SM

NC_USB_EXTDP

NC_USB_EXTDN

NC_USB_MINIP

NC_USB_MININ

USB_CARDREADER_P

USB_CARDREADER_N

NC_USB_EXCARDP

NC_USB_EXCARDN

84 18 9

GMUX_INT

MAKE_BASE=TRUE

21

MCP_SPKR

R0903

0

1 2

5%

1/16W

MF-LF

402

28 9

TP_MEM_A_A<15>

MAKE_BASE=TRUE

29 9

TP_MEM_B_A<15>

MAKE_BASE=TRUE

91 20 9

NC_USB_EXTCP


91 20 9

NC_USB_EXTCN


14 9

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

GMUX_INT

SMC_MCP_SAFE_MODE

TP_MEM_A_A<15>

TP_MEM_B_A<15>

NC_USB_EXTCP

NC_USB_EXTCN

TP_CPU_PECI_MCP

2 1

XW0901

Digital Ground

GND



VOLTAGE=0V

Signal Aliases

9 20 91

9 20 91

9 18 84

42

9 28

9 29

9 20 91

R0901

10

1

1%

1/16W

MF-LF

402

2

17 14 13

67

12

63

11 10

25 24

8

22

7 6

20 18

PPCPUVTT_S0

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

GPU_FB_B_VREF_DIV

9 27 75

9 27 75

SH0912


Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa

NO STUFF

R0950 1

220

5%

1/16W

MF-LF

402

2

NO STUFF

R0970 1

200

5%

1/16W

MF-LF

402

2

NO STUFF

1 R0960

62

5%

1/16W

MF-LF

2

402

NO STUFF

R0990 1

150

1%

1/16W

MF-LF

402

2

NO STUFF

1 R0980

150

2

1%

1/16W

MF-LF

402

SM

1

SH0901


SM

1

SH0917


SM

1

9 20 91

9 14

SH0913


SM

1

GMUX ALIASES

86 84 9

LCD_BKLT_EN

MAKE_BASE=TRUE

90 81

DP_IG_ML_P<3>

MAKE_BASE=TRUE

90 81

DP_IG_ML_N<3>

MAKE_BASE=TRUE

90 81

DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

90 81

DP_IG_ML_N<2..0>

MAKE_BASE=TRUE

81 77 18 9

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_DATA

81 77 18 9

MAKE_BASE=TRUE

81 18 9

DP_IG_HPD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

84 83 69 9

MAKE_BASE=TRUE

84 9

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

84 71

EG_RESET_L

9

MAKE_BASE=TRUE

84 19 9 6

84 19 9 6

JTAG_GMUX_TDI

MAKE_BASE=TRUE

JTAG_GMUX_TMS

MAKE_BASE=TRUE

LCD_BKLT_EN

=MCP_HDMI_TXC_P

9 84 86

18

=MCP_HDMI_TXC_N

18

=MCP_HDMI_TXD_P<0..2>

18

=MCP_HDMI_TXD_N<0..2>

18

DP_IG_DDC_CLK

DP_IG_DDC_DATA

9 18 77 81

9 18 77 81

DP_IG_HPD

9 18 81

PM_ALL_GPU_PGOOD

9 69 83 84

TP_LVDS_MUX_SEL_EG

EG_RESET_L

9 84

9 71 84

JTAG_GMUX_TDI

JTAG_GMUX_TMS

6 9 19 84

6 9 19 84

37 19 9

FW_PLUG_DET_L

MAKE_BASE=TRUE

37 36 9

FW643_WAKE_L

MAKE_BASE=TRUE

FW_PLUG_DET_L

FW643_WAKE_L

UNUSED EXPRESS CARD LANE

90 17 9

TP_PCIE_EXCARD_D2R_P

90 17 9

TP_PCIE_EXCARD_D2R_N

90 17 9

TP_PCIE_EXCARD_R2D_C_P

90 17 9

TP_PCIE_EXCARD_R2D_C_N

17 9

TP_PCIE_EXCARD_PRSNT_L

17 9

TP_EXCARD_CLKREQ_L

90 17 9

TP_PCIE_CLK100M_EXCARD_P

90 17 9

TP_PCIE_CLK100M_EXCARD_N


AUDIO ALIASES

9 19 37

9 36 37

9 17 90

MAKE_BASE=TRUE


9 17 90

MAKE_BASE=TRUE


MAKE_BASE=TRUE


MAKE_BASE=TRUE

9 17 90

9 17 90


9 17

MAKE_BASE=TRUE

TP_EXCARD_CLKREQ_L

9 17

MAKE_BASE=TRUE


9 17 90

MAKE_BASE=TRUE


9 17 90

MAKE_BASE=TRUE

PP5V_S3_AUDIO_AMP



VOLTAGE=5V

58

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)








9 20 91

9 20 91

9 20 32 96

9 20 32 96

9 20 91

9 20 91

34 21 9

PM_SLP_RMGT_L

34 21 9

PM_SLP_RMGT_L

PM_SLP_RMGT_L

MAKE_BASE=TRUE

9 21 34

33 9

TP_PP3V3_ENET_PHY_VDDREG TP_PP3V3_ENET_PHY_VDDREG

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

GND

NO_TEST=TRUE

9 33

9 33

D

C

B

A

APPLE INC.

SIZE

D

DRAWING NUMBER

051-7892

SCALE

NONE

SHT

9

OF

REV.

A.0.0

97

8

7 6 5 4 3 2 1

D

C

B

A

8 7 6 5 4 3

OMIT

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

FSB_A_L<3>

FSB_A_L<4>

FSB_A_L<5>

FSB_A_L<6>

FSB_A_L<7>

FSB_A_L<8>

FSB_A_L<9>

FSB_A_L<10>

FSB_A_L<11>

FSB_A_L<12>

FSB_A_L<13>

FSB_A_L<14>

FSB_A_L<15>

FSB_A_L<16>

FSB_ADSTB_L<0>

J4

L5

L4

K5

M3

N2

J1

N3

P5

P2

L2

P4

P1

R1

M1

A3*

A4*

A5*

A6*

A7*

A8*

A9*

A10*

A11*

A12*

A13*

A14*

A15*

A16*

ADSTB0*

U1000

PENRYN

FCBGA

1 OF 4

ADS*

BNR*

BPRI*

H1

E2

G5

DEFER*

DRDY*

DBSY*

H5

F21

E1

BR0*

F1

IERR*

INIT*

D20

B3

88

CPU_IERR_L

CPU_INIT_L

LOCK*

H4

FSB_ADS_L

FSB_BNR_L

FSB_BPRI_L

FSB_DEFER_L

FSB_DRDY_L

FSB_DBSY_L

FSB_BREQ0_L

FSB_LOCK_L

BI

BI

BI

BI

BI

BI

BI

IN 14 88

BI

7 14 88

14 88

14 88

14 88

14 88

14 88

9 14 88

7 14 88

1

PPCPUVTT_S0

R1002

54.9

2

1%

1/16W

MF-LF

402

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

PLACE TESTPOINT ON

FSB_IERR_L WITH A GND

0.1" AWAY

88 14 BI

88 14 BI

88 14

BI

88 14

BI

88 14 BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

88 14

BI

88 14

BI

88 14 BI

88 14

BI

88 14 7

BI

88 14

IN

88 14 9 IN

88 14 9 IN

88 14

IN

FSB_REQ_L<0>

FSB_REQ_L<1>

FSB_REQ_L<2>

FSB_REQ_L<3>

FSB_REQ_L<4>

FSB_A_L<17>

FSB_A_L<18>

FSB_A_L<19>

FSB_A_L<20>

FSB_A_L<21>

FSB_A_L<22>

FSB_A_L<23>

FSB_A_L<24>

FSB_A_L<25>

FSB_A_L<26>

FSB_A_L<27>

FSB_A_L<28>

FSB_A_L<29>

FSB_A_L<30>

FSB_A_L<31>

FSB_A_L<32>

FSB_A_L<33>

FSB_A_L<34>

FSB_A_L<35>

FSB_ADSTB_L<1>

88 14

IN

88 14

OUT

88 14 IN

CPU_A20M_L

CPU_FERR_L

CPU_IGNNE_L

CPU_STPCLK_L

CPU_INTR

CPU_NMI

CPU_SMI_L

TP_CPU_RSVD0

TP_CPU_RSVD1

TP_CPU_RSVD2

TP_CPU_RSVD3

TP_CPU_RSVD4

TP_CPU_RSVD5

TP_CPU_RSVD6

TP_CPU_RSVD7

TP_CPU_RSVD8

88 13 10 6

T5

T3

W2

W5

Y4

U2

V4

W3

AA4

AB2

AA3

V1

Y2

U5

R3

W6

U4

Y5

U1

R4

A17*

A18*

A19*

A20*

A21*

A22*

A23*

A24*

A25*

A26*

A27*

A28*

A29*

A30*

A31*

A32*

A33*

A34*

A35*

ADSTB1*

B2

F6

D2

D22

D3

M4

N5

T2

V3

RSVD0

RSVD1

RSVD2

RSVD3

RSVD4

RSVD5

RSVD6

RSVD7

RSVD8

XDP_TMS

K3

H2

K2

J3

L1

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

A6

A5

C4

A20M*

FERR*

IGNNE*

D5

C6

B4

A3

STPCLK*

LINT0

LINT1

SMI*

RESET*

RS0*

RS1*

RS2*

TRDY*

C1

F3

F4

G3

G2

THERMAL

1

PROCHOT*

THERMDA

THERMDC

THERMTRIP*

H CLK

BCLK0

BCLK1

R1020

1

54.9

1%

1/16W

MF-LF

402

2

R1021

54.9

1 2

1%

1/16W

MF-LF

402

88 13 10 6

XDP_TDI

XDP_TDO

1%

1/16W

MF-LF

402

R1024

1

54.9

88 10 6

PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1%

1/16W

MF-LF

402

2

88 13 10 6

XDP_TCK

88 13 10 6

XDP_TRST_L

R1023

1

649

1%

1/16W

MF-LF

402

2

HIT*

HITM*

BPM0*

BPM1*

BPM2*

BPM3*

PRDY*

PREQ*

TCK

TDI

TDO

TMS

TRST*

DBR*

R1022

54.9

2

FSB_CPURST_L

FSB_RS_L<0>

FSB_RS_L<1>

FSB_RS_L<2>

FSB_TRDY_L

IN

IN

IN

IN

IN

9 13 14 88

14 88

14 88

14 88

14 88

OMIT

G6

E4

AD4

AD3

AD1

AC4

AC2

AC1

AC5

AA6

AB3

AB5

AB6

C20

FSB_HIT_L

FSB_HITM_L

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TRST_L

XDP_DBRESET_L

BI

BI

BI

BI

BI

BI

BI

7 14 88

7 14 88

13 88

13 88

13 88

13 88

13 88

IN

IN

OUT

6 10 13 88

6 10 13 88

6 10 88

6 10 13 88

IN

IN

OUT

6 10 13 88

13 26

R1003 1

54.9

1%

1/16W

MF-LF

402

2

1

PPCPUVTT_S0

BI

R1004

2

68

5%

1/16W

MF-LF

402

13 88

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7

BI

FSB_D_L<0>

FSB_D_L<1>

FSB_D_L<2>

FSB_D_L<3>

FSB_D_L<4>

FSB_D_L<5>

FSB_D_L<6>

FSB_D_L<7>

FSB_D_L<8>

FSB_D_L<9>

FSB_D_L<10>

FSB_D_L<11>

FSB_D_L<12>

E22

F24

E26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

FSB_D_L<13>

FSB_D_L<14>

FSB_D_L<15>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

FSB_DINV_L<0>

F26

K22

H23

J26

H26

H25 D21

A24

B25

CPU_PROCHOT_L

CPU_THERMD_P

CPU_THERMD_N

48 96

OUT

14 43 63 88

OUT

OUT 48 96

C7

A22

A21

PM_THRMTRIP_L

FSB_CLK_CPU_P

FSB_CLK_CPU_N

PPCPUVTT_S0

OUT

IN

IN

14 43 88

14 88

14 88

18 17 14 13 12 11

67 63

10 9 8 7 6

25 24 22 20

PPCPUVTT_S0

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

PM_THRMTRIP#

SHOULD CONNECT TO ICH AND

GMCH WITHOUT T (NO STUB)

PLACE C1000 CLOSE TO CPU_TEST4

PIN. MAKE SURE CPU_TEST4 IS

REFERENCED TO GND

R1005

1K

1%

1/16W

MF-LF

402

2

R1006

1

1

2.0K

1%

1/16W

MF-LF

402

2

88 14 7

BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

88 14 7

BI

FSB_D_L<16>

FSB_D_L<17>

FSB_D_L<18>

FSB_D_L<19>

FSB_D_L<20>

FSB_D_L<21>

N22

K25

P26

R23

L23

M24

88 14 7 BI

88 14 7 BI

88 14 7

BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

FSB_D_L<22>

FSB_D_L<23>

FSB_D_L<24>

FSB_D_L<25>

FSB_D_L<26>

FSB_D_L<27>

FSB_D_L<28>

L22

M23

P25

P23

P22

T24

R24

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7 BI

88 14 7

BI

1

2

88 14 7 BI

0.5" MAX LENGTH FOR CPU_GTLREF

88 27

CPU_GTLREF

CPU_TEST1

NOSTUFF

C1000

0.1uF

10%

16V

X5R

402

88 9 OUT

88 9 OUT

CPU_TEST2

TP_CPU_TEST3

CPU_TEST4

TP_CPU_TEST5

TP_CPU_TEST6

TP_CPU_TEST7

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

88 9

OUT

FSB_D_L<29>

FSB_D_L<30>

FSB_D_L<31>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<1>

L25

T25

N25

L26

M26

N24

AD26

C23

D25

C24

AF26

AF1

A26

C3

B22

B23

C21

NOSTUFF

R1012 1

1K

5%

1/16W

MF-LF

402

2

NOSTUFF

R1030

0

1 2

5%

1/16W

MF-LF

402

NOSTUFF

1 R1007

1K

2

5%

1/16W

MF-LF

402

GTLREF

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

TEST7

BSEL0

BSEL1

BSEL2

D16*

D17*

D18*

D19*

D20*

D21*

D22*

D23*

D24*

D25*

D26*

D27*

D28*

D29*

D30*

D31*

DSTBN1*

DSTBP1*

DINV1*

D0*

D1*

D2*

D3*

D4*

D5*

D6*

D7*

D8*

D9*

D10*

D11*

D12*

D13*

D14*

D15*

DSTBN0*

DSTBP0*

DINV0*

U1000

PENRYN

FCBGA

2 OF 4

MISC

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D32*

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

Y22

AB24

V24

V26

V23

T22

U25

U23

2 1

FSB_D_L<32>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<38>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<45>

FSB_D_L<46>

FSB_D_L<47>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<2>

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<3>

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

7 14 88

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

88

CPU_COMP<0>

88

CPU_COMP<1>

88

CPU_COMP<2>

88

CPU_COMP<3>

CPU_DPRSTP_L

CPU_DPSLP_L

FSB_DPWR_L

CPU_PWRGD

FSB_CPUSLP_L

CPU_PSI_L

IN

IN

IN

IN

IN

OUT

9 14 63 88

14 88

14 88

13 14 88

14 88

63

LAYOUT NOTE:

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

R1016

27.4

2 1

R1017 1/16W

54.9

1 2

1%

MF-LF

402

1%

1/16W

MF-LF

402

R1018

1

27.4

2

R1019 1/16W

54.9

1 2

1%

MF-LF

402

1%

1/16W

MF-LF

402

8

7 6 5 4 3

D

C

B

CPU FSB

SYNC_MASTER=M98_MLB SYNC_DATE=11/12/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

10

OF

97

2 1

D

C

B

8 7 6 5 4

B20

C9

C10

C12

C13

C15

C17

C18

D9

D10

D12

D14

D15

D17

D18

E7

E9

E10

E12

E13

E15

E17

E18

E20

F7

F9

F10

AA7

AA9

AA10

AA12

AA13

AA15

AA17

F12

F14

F15

F17

F18

F20

AA18

AA20

AB9

AC10

AB10

AB12

AB14

AB15

AB17

AB18

A7

A9

A10

A12

A13

A15

A17

A18

A20

B7

B9

B10

B12

B14

B15

B17

B18

VCC

OMIT

U1000

PENRYN

FCBGA

3 OF 4

VCC

AD10

AD12

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

VCCP

N21

N6

R21

R6

T21

T6

V21

W21

G21

V6

J6

K6

M6

J21

K21

M21

VCCA

B26

C26

VID0

VID1

VID2

VID3

VID4

VID5

VID6

AD6

AF5

AE5

AF4

AE3

AF3

AE2

VCCSENSE AF7

(CPU CORE POWER)

PPVCORE_S0_CPU

7 8 11 12 46 63

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)

25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

(CPU IO POWER 1.05V)

PPCPUVTT_S0

6 7 8 9 10 12 13 14 17 18 20 22

24 25 63 67

4500 mA (before VCC stable)

2500 mA (after VCC stable)

(CPU INTERNAL PLL POWER 1.5V)

PP1V8R1V5_S0_FET

7 8 12 16 24 28 29 39 68 69

70

130 mA

CPU_VID<0>

CPU_VID<1>

CPU_VID<2>

CPU_VID<3>

CPU_VID<4>

CPU_VID<5>

CPU_VID<6>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

9 88

9 88

9 88

9 88

9 88

9 88

9 88

CPU_VCCSENSE_P

VSSSENSE AE7 CPU_VCCSENSE_N

Low Voltage:


21.0 A (HFM)

18.7 A (LFM)

TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)

TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)

TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

PPVCORE_S0_CPU

7 8 11 12 46 63

1 R1100

100

1%

1/16W

2

MF-LF

402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

OUT 63 88

OUT 63 88

1 R1101

100

1%

1/16W

2

MF-LF

402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

Ultra Low Voltage:


TBD A (HFM)

TBD A (LFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep HFM)

TBD A (Sleep LFM)

TBD A (Deep Sleep HFM)

TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

A

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

8

7 6 5 4

3

OMIT

U1000

PENRYN

FCBGA

4 OF 4

VSS

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

P6

P21

P24

R2

R5

R22

R25

T1

T4

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

D16

D19

D23

D26

E3

E6

E8

E11

E14

E16

E19

E21

E24

F5

F8

F11

F13

F16

F19

F2

F22

F25

G4

G1

G23

G26

H3

C11

C14

C16

C19

C2

C22

C25

D1

D4

D8

D11

D13

H6

H21

H24

J2

J5

J22

J25

K1

K4

K23

K26

L3

L6

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26

P3

B1

A4

A8

A11

A14

A16

A19

A23

AF2

B6

B8

B11

B13

B16

B19

B21

B24

C5

C8

VSS

2

3

1

D

C

B

CPU Power & Ground



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

11

OF

97

2 1

8 7 6 5 4

D

C

B

CPU VCORE HF AND BULK DECOUPLING

63 46 11 8 7

PPVCORE_S0_CPU

CRITICAL

4x 330uF, 20x 22uF 0805

CRITICAL

C1250

330UF

20%

2.0V

POLY-TANT

D2T-SM2

1

2 3

C1251

330UF

20%

2.0V

POLY-TANT

D2T-SM2

1

2

PLACEMENT_NOTE=Place in CPU center cavity.


3

1

2

CRITICAL

C1200

22UF

20%

6.3V

X5R-CERM

603

CRITICAL CRITICAL

C1252

330UF

20%

2.0V

POLY-TANT

D2T-SM2

1

2 3

C1253

330UF

20%

2.0V

POLY-TANT

D2T-SM2

1

2



3

1

2

CRITICAL

C1210

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1201

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1202

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1203

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1211

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1212

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1213

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1204

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1205

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1206

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1207

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1214

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1215

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1216

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1217

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1208

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1218

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1209

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

C1219

22UF

20%

6.3V

X5R-CERM

603

VCCP (CPU I/O) DECOUPLING

20 18 17 14 13

PPCPUVTT_S0

11

67

10

63

9 8

25

7

24

6

22

1x 470uF, 6x 0.1uF 0402

CRITICAL

C1235

470UF

20%

2.5V

POLY

D2T

1

2 3

1

2

C1236

0.1UF

20%

10V

CERM

402

1

2

C1237

0.1UF

20%

10V

CERM

402

1

2

C1238

0.1UF

20%

10V

CERM

402

WF: Consider sharing bulk cap with NB Vtt?

1

2

C1239

0.1UF

20%

10V

CERM

402

1

2

C1240

0.1UF

20%

10V

CERM

402

1

2

C1241

0.1UF

20%

10V

CERM

402

VCCA (CPU AVdd) DECOUPLING

69 68 39 29 28 24 16 11 8 7

70

PP1V8R1V5_S0_FET

1x 10uF, 1x 0.01uF

C1280

10uF

20%

6.3V

X5R

603

1

2

1

2

C1281

0.01UF

10%

16V

CERM

402

PLACEMENT_NOTE=Place near CPU pin B26.

3

A

8

7 6 5 4 3

2 1

D

C

B

CPU Decoupling & VID



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

12

OF

97

2 1

D

C

B

A

8

8

7 6 5 4 3 2

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

Use with 920-0620 adapter board to support CPU, MCP debugging.

MCP79-specific pinout

88 14 10 IN

84 82

59 55

81

29 28 25 24

51

80

22

49

77 70

21

48 47

69

19

45

68

18

63

8 7

43 39

60

6

37

20

67 63

18 17 14 12

25 24 22

11 10 9 8 7

PP3V3_S0

PPCPUVTT_S0

88 10 BI

88 10

BI

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP

R1315 1

54.9

1%

1/16W

MF-LF

402

2

88 10 BI

88 10

IN

XDP_BPM_L<3>

XDP_BPM_L<2>

88 10 IN

88 10

IN

XDP_BPM_L<1>

XDP_BPM_L<0>

TP_XDP_OBSFN_B0

TP_XDP_OBSFN_B1

CPU_PWRGD

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B1

XDP

R1399

1K

1 2

5%

1/16W

MF-LF

402

19

IN

76 21 6 OUT

TP_XDP_OBSDATA_B2

TP_XDP_OBSDATA_B3

XDP_PWRGD

PM_LATRIGGER_L

JTAG_MCP_TCK

91 45 29 28 21

BI

91 45 29 28 21 BI

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

XDP_TCK

88 10 6

OUT

XDP_OBS20

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2

HOOK3

SDA

SCL

TCK1

TCK0

XDP

C1300

0.1uF

10%

16V

X5R

402

1

2

10

12

14

2

4

6

8

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

NC

58

60

CRITICAL

XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

F-ST-SM

1

9

11

13

3

5

7

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

JTAG_MCP_TDO_CONN

JTAG_MCP_TRST_L

IN

OUT

6

6 21 76

MCP_DEBUG<0>

MCP_DEBUG<1>

BI

BI

19 91

19 91

MCP_DEBUG<2>

MCP_DEBUG<3>

BI

BI

19 91

19 91

JTAG_MCP_TDI

JTAG_MCP_TMS

OUT

OUT

6 21

6 21

MCP_DEBUG<4>

MCP_DEBUG<5>

BI

BI

19 91

19 91

MCP_DEBUG<6>

MCP_DEBUG<7>

BI

BI

19 91

19 91

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

FSB_CLK_ITP_P

FSB_CLK_ITP_N

88

XDP_CPURST_L

XDP_DBRESET_L

DBR#/HOOK7

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TDO

XDP_TDO_CONN

TRSTn

XDP_TRST_L

TDI

XDP_TDI

TMS

XDP_TMS

1

2

XDP_PRESENT#

XDP

C1301

0.1uF

10%

16V

X5R

402

IN

IN

14 88

14 88

OUT 10 26

IN

OUT

OUT

OUT

6

6 10 88

6 10 88

6 10 88

998-1571

Direction of XDP module

Please avoid any obstructions on even-numbered side of J1300

XDP

R1303

1K

1 2 FSB_CPURST_L

IN

9 10 14 88

PLACEMENT_NOTE=Place close to CPU to minimize stub.

5%

1/16W

MF-LF

402

1

D

C

B

7 6 5 4 3 eXtended Debug Port(MiniXDP)



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

13

OF

97

2 1

D

C

B

A

8

18 17 14 13 12 11

67 63

10 9 8 7 6

25 24 22 20

PPCPUVTT_S0

7

R1410

54.9

1

1%

1/16W

MF-LF

402

2

88 43 10 IN

88 10

IN

PM_THRMTRIP_L

CPU_FERR_L

R1415

62

1

5%

1/16W

MF-LF

402

2

9 IN

9 IN

9

IN

NO STUFF

R1420 1

1K

5%

1/16W

MF-LF

402

2

=MCP_BSEL<2>

=MCP_BSEL<1>

=MCP_BSEL<0>

NO STUFF

R1421

1K

5%

1

1/16W

MF-LF

402

2

1 R1416

62

2

5%

1/16W

MF-LF

402

NO STUFF

1 R1422

1K

5%

2

1/16W

MF-LF

402

R1430

49.9

1

1%

1/16W

MF-LF

402

2

R1431

49.9

1

1%

1/16W

MF-LF

402

2

6

1 R1435

49.9

2

1%

1/16W

MF-LF

402

1 R1436

49.9

2

1%

1/16W

MF-LF

402

88 10 7 BI

88 10 7 BI

88 10 7 BI

88 10 7 BI

88 10 7 BI

88 10 7 BI

88 10 7

BI

88 10 7 BI

88 10 7 BI

88 10 7

BI

88 10 7 BI

88 10 7 BI

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_DINV_L<0>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_DINV_L<1>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_DINV_L<2>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_DINV_L<3>

88 10 7 BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7

BI

88 10 7

BI

88 10 7 BI

88 10 7 BI

88 10 7

BI

88 10 BI

88 10 BI

88 10

BI

88 10

BI

88 10 7 BI

88 10 7

BI

88 10 BI

88 10 BI

88 10 BI

88 10 BI

88 10 BI

FSB_REQ_L<0>

FSB_REQ_L<1>

FSB_REQ_L<2>

FSB_REQ_L<3>

FSB_REQ_L<4>

88 10 7 BI

88 10 BI

88 10 9

BI

88 10 BI

88 10

BI

88 10 7 BI

88 10 7 BI

88 10 7

IN

88 10 OUT

FSB_ADS_L

FSB_BNR_L

FSB_BREQ0_L

88

FSB_BREQ1_L

FSB_DBSY_L

FSB_DRDY_L

FSB_HIT_L

FSB_HITM_L

FSB_LOCK_L

FSB_TRDY_L

FSB_A_L<3>

FSB_A_L<4>

FSB_A_L<5>

FSB_A_L<6>

FSB_A_L<7>

FSB_A_L<8>

FSB_A_L<9>

FSB_A_L<10>

FSB_A_L<11>

FSB_A_L<12>

FSB_A_L<13>

FSB_A_L<14>

FSB_A_L<15>

FSB_A_L<16>

FSB_A_L<17>

FSB_A_L<18>

FSB_A_L<19>

FSB_A_L<20>

FSB_A_L<21>

FSB_A_L<22>

FSB_A_L<23>

FSB_A_L<24>

FSB_A_L<25>

FSB_A_L<26>

FSB_A_L<27>

FSB_A_L<28>

FSB_A_L<29>

FSB_A_L<30>

FSB_A_L<31>

FSB_A_L<32>

FSB_A_L<33>

FSB_A_L<34>

FSB_A_L<35>

FSB_ADSTB_L<0>

FSB_ADSTB_L<1>

9 OUT

88 63 43 10

OUT

TP_CPU_PECI_MCP

CPU_PROCHOT_L

(MCP_BSEL<2>)

(MCP_BSEL<1>)

(MCP_BSEL<0>)

88 10 OUT

88 10

OUT

88 10

OUT

FSB_RS_L<0>

FSB_RS_L<1>

FSB_RS_L<2>

24

PP1V05_S0_MCP_PLL_FSB

270 mA (A01) 206 mA

20 mA

29 mA

15 mA

88

MCP_BCLK_VML_COMP_VDD

88

MCP_BCLK_VML_COMP_GND

88

MCP_CPU_COMP_VCC

88

MCP_CPU_COMP_GND

5 4

OMIT

CPU_A3#

CPU_A4#

CPU_A5#

CPU_A6#

CPU_A7#

CPU_A8#

CPU_A9#

CPU_A10#

CPU_A11#

CPU_A12#

CPU_A13#

CPU_A14#

CPU_A15#

CPU_A16#

CPU_A17#

CPU_A18#

CPU_A19#

CPU_A20#

CPU_A21#

CPU_A22#

CPU_A23#

CPU_A24#

CPU_A25#

CPU_A26#

CPU_A27#

CPU_A28#

CPU_A29#

CPU_A30#

CPU_A31#

CPU_A32#

CPU_A33#

CPU_A34#

CPU_A35#

AC34

AE38

AE34

AC37

AE37

AE35

AB35

AF35

AG35

AG39

AE33

AG37

AG38

AG34

AN38

AL39

AG33

AL33

AJ33

AN36

AJ35

AJ37

AJ36

AJ38

AL37

AL34

AN37

AJ34

AL38

AL35

AN34

AR39

AN35

U1400

MCP79-TOPO-B

BGA

(1 OF 11)

T40

U40

V41

CPU_DSTBP0#

CPU_DSTBN0#

CPU_DBI0#

W39

W37

V35

CPU_DSTBP1#

CPU_DSTBN1#

CPU_DBI1#

N37

L36

N35

CPU_DSTBP2#

CPU_DSTBN2#

CPU_DBI2#

M39

M41

J41

CPU_DSTBP3#

CPU_DSTBN3#

CPU_DBI3#

AE36

AK35

CPU_ADSTB0#

CPU_ADSTB1#

AC38

AA33

AC39

AC33

AC35

CPU_REQ0#

CPU_REQ1#

CPU_REQ2#

CPU_REQ3#

CPU_REQ4#

AD42

AD43

AE40

AL32

AD39

AD41

AB42

AD40

AC43

AE41

CPU_ADS#

CPU_BNR#

CPU_BR0#

CPU_BR1#

CPU_DBSY#

CPU_DRDY#

CPU_HIT#

CPU_HITM#

CPU_LOCK#

CPU_TRDY#

CPU_D16#

CPU_D17#

CPU_D18#

CPU_D19#

CPU_D20#

CPU_D21#

CPU_D22#

CPU_D23#

CPU_D24#

CPU_D25#

CPU_D26#

CPU_D27#

CPU_D28#

CPU_D29#

CPU_D30#

CPU_D31#

CPU_D32#

CPU_D33#

CPU_D34#

CPU_D35#

CPU_D36#

CPU_D37#

CPU_D38#

CPU_D39#

CPU_D40#

CPU_D0#

CPU_D1#

CPU_D2#

CPU_D3#

CPU_D4#

CPU_D5#

CPU_D6#

CPU_D7#

CPU_D8#

CPU_D9#

CPU_D10#

CPU_D11#

CPU_D12#

CPU_D13#

CPU_D14#

CPU_D15#

CPU_D41#

CPU_D42#

CPU_D43#

CPU_D44#

CPU_D45#

CPU_D46#

CPU_D47#

CPU_D48#

CPU_D49#

CPU_D50#

CPU_D51#

CPU_D52#

CPU_D53#

CPU_D54#

CPU_D55#

CPU_D56#

CPU_D57#

CPU_D58#

CPU_D59#

CPU_D60#

CPU_D61#

CPU_D62#

CPU_D63#

R41

T43

W35

AA37

W33

W34

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

Y43

W42

Y40

W41

Y39

V42

Y41

Y42

P42

U41

R42

T39

T42

T41

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

K41

J40

H39

M43

CPU_BPRI#

CPU_DEFER#

AA41

AA40

E41

AJ41

AG43

AH40

CPU_PECI

CPU_PROCHOT#

CPU_THERMTRIP#

CPU_FERR#

F42

D42

F41

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

AC41

AB41

AC42

CPU_RS0#

CPU_RS1#

CPU_RS2#

BCLK_OUT_CPU_P

BCLK_OUT_CPU_N

G42

G41

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

AL43

AL42

BCLK_OUT_NB_P

BCLK_OUT_NB_N

AL41

AK42

BCLK_IN_N

BCLK_IN_P

AK41

AJ40

AG27

AH27

AG28

AH28

+V_DLL_DLCELL_AVDD

+V_PLL_MCLK

+V_PLL_FSB

+V_PLL_CPU

AM39

AM40

BCLK_VML_COMP_VDD

BCLK_VML_COMP_GND

AM43

AM42

CPU_COMP_VCC

CPU_COMP_GND

CPU_A20M#

CPU_IGNNE#

CPU_INIT#

CPU_INTR

CPU_NMI

CPU_SMI#

AF41

AH39

AH42

AF42

AG41

AH41

CPU_PWRGD

CPU_RESET#

AH43

H38

CPU_SLP#

CPU_DPSLP#

CPU_DPWR#

CPU_STPCLK#

CPU_DPRSTP#

AM33

AN33

AM32

AG42

AN32

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6 5 4

3 2 1

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

7 10 88

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

10 88

10 88

OUT

OUT

10 88

10 88

OUT

OUT

13 88

13 88

FSB_D_L<28>

FSB_D_L<29>

FSB_D_L<30>

FSB_D_L<31>

FSB_D_L<32>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<38>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<45>

FSB_D_L<46>

FSB_D_L<47>

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<0>

FSB_D_L<1>

FSB_D_L<2>

FSB_D_L<3>

FSB_D_L<4>

FSB_D_L<5>

FSB_D_L<6>

FSB_D_L<7>

FSB_D_L<8>

FSB_D_L<9>

FSB_D_L<10>

FSB_D_L<11>

FSB_D_L<12>

FSB_D_L<13>

FSB_D_L<14>

FSB_D_L<15>

FSB_D_L<16>

FSB_D_L<17>

FSB_D_L<18>

FSB_D_L<19>

FSB_D_L<20>

FSB_D_L<21>

FSB_D_L<22>

FSB_D_L<23>

FSB_D_L<24>

FSB_D_L<25>

FSB_D_L<26>

FSB_D_L<27>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_BPRI_L

FSB_DEFER_L

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_CLK_ITP_N

88

FSB_CLK_MCP_P

88

FSB_CLK_MCP_N

Loop-back clock for delay matching.

CPU_A20M_L

CPU_IGNNE_L

CPU_INIT_L

CPU_INTR

CPU_NMI

CPU_SMI_L

CPU_PWRGD

FSB_CPURST_L

FSB_CPUSLP_L

CPU_DPSLP_L

FSB_DPWR_L

CPU_STPCLK_L

CPU_DPRSTP_L

OUT 10 88

10 88

OUT

OUT

OUT

10 88

9 10 88

9 10 88

OUT

OUT

10 88

OUT

9 10 13 88

OUT 10 88

10 88

OUT

OUT

OUT

10 88

10 88

OUT

9 10 63 88

PPCPUVTT_S0

NO STUFF

1 R1440

150

2

5%

1/16W

MF-LF

402

OUT

10 13 88

3

D

C

B

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63 67

MCP CPU Interface



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

14

OF

97

2 1

D

C

B

8 7

89 28 BI

89 28 BI

89 28 BI

89 28 BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28

BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28

BI

89 28 BI

89 28 BI

89 28 BI

89 28 OUT

89 28

89 28

OUT

OUT

89 28 OUT

89 28

89 28

OUT

OUT

89 28 OUT

89 28

OUT

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

OMIT

AN29

AV29

AN31

AU31

AR33

AV37

AW37

AP27

AR27

AP29

AR29

AP31

AR31

AV27

AT31

AV31

AT37

AU37

AW39

AV39

AR37

AR38

AV38

AW38

AR35

AP35

AV13

AW13

AR11

AT11

AR14

AU13

AR26

AU25

AT27

AU27

AP25

AR25

AP11

AW6

AY5

AU9

AV9

AU11

AV11

AR5

AU6

AV5

AU7

AU8

AW9

AN7

AR6

AR7

AV6

AW5

AN10

AL8

AL9

AP9

AN9

AL6

AL7

AN6

MDQ0_63

MDQ0_62

MDQ0_61

MDQ0_60

MDQ0_59

MDQ0_58

MDQ0_57

MDQ0_56

MDQ0_55

MDQ0_54

MDQ0_53

MDQ0_52

MDQ0_51

MDQ0_50

MDQ0_49

MDQ0_48

MDQ0_47

MDQ0_46

MDQ0_45

MDQ0_44

MDQ0_43

MDQ0_42

MDQ0_41

MDQ0_40

MDQ0_39

MDQ0_38

MDQ0_37

MDQ0_36

MDQ0_35

MDQ0_34

MDQ0_33

MDQ0_32

MDQ0_31

MDQ0_30

MDQ0_29

MDQ0_28

MDQ0_27

MDQ0_26

MDQ0_25

MDQ0_24

MDQ0_23

MDQ0_22

MDQ0_21

MDQ0_20

MDQ0_19

MDQ0_18

MDQ0_17

MDQ0_16

MDQ0_15

MDQ0_14

MDQ0_13

MDQ0_12

MDQ0_11

MDQ0_10

MDQ0_9

MDQ0_8

MDQ0_7

MDQ0_6

MDQ0_5

MDQ0_4

MDQ0_3

MDQ0_2

MDQ0_1

MDQ0_0

U1400

MCP79-TOPO-B

BGA

(2 OF 11)

MDQS0_7_P

MDQS0_7_N

MDQS0_6_P

MDQS0_6_N

MDQS0_5_P

MDQS0_5_N

MDQS0_4_P

MDQS0_4_N

MDQS0_3_P

MDQS0_3_N

MDQS0_2_P

MDQS0_2_N

MDQS0_1_P

MDQS0_1_N

MDQS0_0_P

MDQS0_0_N

AL10

AL11

AR8

AR9

AW7

AW8

AP13

AR13

AV25

AW25

AU30

AU29

AT35

AU35

AU39

AT39

MRAS0#

MCAS0#

MWE0#

AV17

AP17

AR17

MBA0_2

MBA0_1

MBA0_0

AP23

AP19

AW17

MA0_14

MA0_13

MA0_12

MA0_11

MA0_10

MA0_9

MA0_8

MA0_7

MA0_6

MA0_5

MA0_4

MA0_3

MA0_2

MA0_1

MA0_0

AR23

AU15

AN23

AW21

AN19

AV21

AR22

AU21

AP21

AR21

AN21

AV19

AU19

AT19

AR19

MEMORY

CONTROL

0A

MCLK0A_2_P

MCLK0A_2_N

AW33

AV33

MCLK0A_1_P

MCLK0A_1_N

BA24

AY24

MCLK0A_0_P

MCLK0A_0_N

BB20

BC20

AN5

AU5

AR10

AN13

AN27

AW29

AV35

AR34

MDQM0_7

MDQM0_6

MDQM0_5

MDQM0_4

MDQM0_3

MDQM0_2

MDQM0_1

MDQM0_0

MCS0A_1#

MCS0A_0#

AT15

AR18

MODT0A_1

MODT0A_0

AP15

AV15

MCKE0A_1

MCKE0A_0

AU23

AT23

6

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

OUT

OUT

28 89

28 89

OUT

28 89

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

OUT

OUT

OUT

28 89

28 89

28 89

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

OUT

OUT

OUT

28 89

28 89

28 89

OUT

OUT

OUT

28 89

28 89

28 89

OUT

OUT

OUT

OUT

28 89

28 89

28 89

28 89

OUT

OUT

OUT

28 89

28 89

28 89

OUT

OUT

28 89

28 89

TP_MEM_A_CLK2P

NC_MEM_A_CLK2N

7

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

OUT

OUT

28 89

28 89

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

OUT

OUT

28 89

28 89

MEM_A_CS_L<1>

MEM_A_CS_L<0>

OUT

OUT

28 89

28 89

MEM_A_ODT<1>

MEM_A_ODT<0>

OUT

OUT

28 89

28 89

MEM_A_CKE<1>

MEM_A_CKE<0>

OUT

OUT

28 89

28 89

5

A

8

7 6 5

4

4

89 29 BI

89 29 BI

89 29 BI

89 29 BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29

BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29

BI

89 29 BI

89 29 BI

89 29 BI

89 29 OUT

89 29

OUT

89 29 OUT

89 29 OUT

89 29

OUT

89 29

OUT

89 29 OUT

89 29

OUT

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<3>

MEM_B_DM<2>

MEM_B_DM<1>

MEM_B_DM<0>

3 2

OMIT

MDQ1_39

MDQ1_38

MDQ1_37

MDQ1_36

MDQ1_35

MDQ1_34

MDQ1_33

MDQ1_32

MDQ1_31

MDQ1_30

MDQ1_29

MDQ1_28

MDQ1_27

MDQ1_26

MDQ1_25

MDQ1_24

MDQ1_23

MDQ1_22

MDQ1_21

MDQ1_20

MDQ1_19

MDQ1_18

MDQ1_17

MDQ1_63

MDQ1_62

MDQ1_61

MDQ1_60

MDQ1_59

MDQ1_58

MDQ1_57

MDQ1_56

MDQ1_55

MDQ1_54

MDQ1_53

MDQ1_52

MDQ1_51

MDQ1_50

MDQ1_49

MDQ1_48

MDQ1_47

MDQ1_46

MDQ1_45

MDQ1_44

MDQ1_43

MDQ1_42

MDQ1_41

MDQ1_40

MDQ1_16

MDQ1_15

MDQ1_14

MDQ1_13

MDQ1_12

MDQ1_11

MDQ1_10

MDQ1_9

MDQ1_8

MDQ1_7

MDQ1_6

MDQ1_5

MDQ1_4

MDQ1_3

MDQ1_2

MDQ1_1

MDQ1_0

BB36

BA38

AY39

BB40

AW40

AV42

AV41

BA34

AY35

BC36

AW36

BA39

AY40

BA36

BA40

BC40

AW42

AW41

AT40

AT41

AP41

AN40

AU40

AU41

AR41

AP42

BB12

AW12

BB8

BB9

AY12

BA12

BC32

AW32

BA35

AY36

BA32

BB32

BC8

BB4

BC4

BA7

AY8

BA9

BB10

AW3

BA3

BB2

BB5

BA5

BA8

AU3

AY4

AY3

BB3

BC3

AW4

AT4

AT3

AV2

AV3

AR4

AR3

AU2

U1400

MCP79-TOPO-B

BGA

(3 OF 11)

MDQS1_7_P

MDQS1_7_N

MDQS1_6_P

MDQS1_6_N

MDQS1_5_P

MDQS1_5_N

MDQS1_4_P

MDQS1_4_N

MDQS1_3_P

MDQS1_3_N

MDQS1_2_P

MDQS1_2_N

MDQS1_1_P

MDQS1_1_N

MDQS1_0_P

MDQS1_0_N

AT2

AT1

AY2

AY1

BB6

BA6

BA10

AY11

BB33

BA33

BB37

BA37

BA43

AY42

AT42

AT43

MRAS1#

MCAS1#

MWE1#

AW16

BA15

BA16

MBA1_2

MBA1_1

MBA1_0

BB29

BB18

BB17

MA1_14

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_5

MA1_4

MA1_3

MA1_2

MA1_1

MA1_0

BA29

BA14

AW28

BC28

BA17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BB25

BA18

MEMORY

CONTROL

1A

MCLK1A_2_P

MCLK1A_2_N

BA42

BB42

MCLK1A_1_P

MCLK1A_1_N

BB22

BA22

MCLK1A_0_P

MCLK1A_0_N

BA19

AY19

AT5

BA2

AY7

BA11

BB34

BB38

AY43

AR42

MDQM1_7

MDQM1_6

MDQM1_5

MDQM1_4

MDQM1_3

MDQM1_2

MDQM1_1

MDQM1_0

MCS1A_1#

MCS1A_0#

BB14

BB16

MODT1A_1

MODT1A_0

BB13

AY15

MCKE1A_1

MCKE1A_0

AY31

BB30

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

OUT

OUT

OUT

29 89

29 89

29 89

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

OUT

OUT

OUT

29 89

29 89

29 89

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

29 89

TP_MEM_B_CLK2P

TP_MEM_B_CLK2N

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CKE<1>

MEM_B_CKE<0>

OUT

OUT

29 89

29 89

OUT

OUT

29 89

29 89

OUT

OUT

29 89

29 89

OUT

OUT

29 89

29 89

OUT

OUT

29 89

29 89

1

3

D

C

B

MCP Memory Interface



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

15

OF

97

2 1

D

C

B

A

8 7

68 39 29 28 24 16 12 11 8 7

70 69

PP1V8R1V5_S0_FET

R1610

40.2

1

1%

1/16W

MF-LF

402

2

R1611

40.2

1

1%

1/16W

MF-LF

402

2

6 5 4 3

TP_MEM_A_CLK5P

TP_MEM_A_CLK5N

7

NC_MEM_A_CLK4P

TP_MEM_A_CLK4N

7

7

NC_MEM_A_CLK3P

NC_MEM_A_CLK3N

7

TP_MEM_A_CS_L<2>

NC_MEM_A_CS_L<3>

7

7

NC_MEM_A_ODT<2>

NC_MEM_A_ODT<3>

7

7

NC_MEM_A_CKE<2>

NC_MEM_A_CKE<3>

24

PP1V05_S0_MCP_PLL_CORE

87 mA (A01) 17 mA

12 mA

19 mA

39 mA

AU33

AU34

OMIT

U1400

MCP79-TOPO-B

BGA

(4 OF 11)

MCLK0B_2_P

MCLK0B_2_N

MCLK1B_2_P

MCLK1B_2_N

BA41

BB41

BB24

BC24

MCLK0B_1_P

MCLK0B_1_N

BA21

BB21

MCLK0B_0_P

MCLK0B_0_N

MCLK1B_1_P

MCLK1B_1_N

AY23

BA23

MCLK1B_0_P

MCLK1B_0_N

BA20

AY20

AU17

AR15

MCS0B_0#

MCS0B_1#

AN17

AN15

MODT0B_0

MODT0B_1

AV23

AN25

MCKE0B_0

MCKE0B_1

MCS1B_0#

MCS1B_1#

BC16

BA13

MODT1B_0

MODT1B_1

AY16

BC13

MCKE1B_0

MCKE1B_1

BA30

BA31

T27

U28

U27

T28

+V_PLL_XREF_XS

+V_PLL_DP

+V_PLL_CORE

+V_VPLL

MRESET0#

AY32

89

MCP_MEM_COMP_VDD

89

MCP_MEM_COMP_GND

AN41

AM41

MEM_COMP_VDD

MEM_COMP_GND

K7

M38

M5

M6

M7

M9

N39

N8

P33

P34

P37

P4

P40

P7

R36

R40

R43

R5

T18

T20

AK11

T24

T26

AM28

AT25

AP30

AR36

AU10

F28

BC21

AY9

BC9

D34

F24

G32

H31

AA22

AP12

G30

P10

T10

T6

V10

V34

W5

AA39

AB22

AB7

AD22

AE20

AF24

AG24

AH35

AK7

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND20

GND21

GND22

GND23

GND24

GND25

GND26

GND27

GND28

GND29

GND30

GND31

GND32

GND33

GND34

GND35

GND36

GND37

GND38

GND39

GND40

GND41

GND42

GND43

GND44

GND45

GND46

GND47

GND48

GND49

GND50

GND51

GND52

GND53

GND54

TP_MEM_B_CLK5P

NC_MEM_B_CLK5N

NC_MEM_B_CLK4P

NC_MEM_B_CLK4N

NC_MEM_B_CLK3P

TP_MEM_B_CLK3N

TP_MEM_B_CS_L<2>

TP_MEM_B_CS_L<3>

7

7

7

7

NC_MEM_B_ODT<2>

TP_MEM_B_ODT<3>

7

NC_MEM_B_CKE<2>

TP_MEM_B_CKE<3>

7

MCP_MEM_RESET_L

TP or NC for DDR2.

OUT

30

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AY26

AW19

AW24

BC25

AL30

AM31

AM17

AM19

AM21

AM23

AM25

AM27

AM29

AN16

BC29

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AR24

+VDD_MEM1

+VDD_MEM2

+VDD_MEM3

+VDD_MEM4

+VDD_MEM5

+VDD_MEM6

+VDD_MEM7

+VDD_MEM8

+VDD_MEM9

+VDD_MEM10

+VDD_MEM11

+VDD_MEM12

+VDD_MEM13

+VDD_MEM14

+VDD_MEM15

+VDD_MEM16

+VDD_MEM17

+VDD_MEM18

+VDD_MEM19

+VDD_MEM20

+VDD_MEM21

+VDD_MEM22

+VDD_MEM23

+VDD_MEM24

+VDD_MEM25

+VDD_MEM26

+VDD_MEM27

+VDD_MEM28

+VDD_MEM29

+VDD_MEM30

+VDD_MEM31

+VDD_MEM32

+VDD_MEM33

+VDD_MEM34

+VDD_MEM35

+VDD_MEM36

+VDD_MEM37

+VDD_MEM38

+VDD_MEM39

+VDD_MEM40

+VDD_MEM41

+VDD_MEM42

+VDD_MEM43

+VDD_MEM44

+VDD_MEM45

GND55

GND56

GND57

GND58

GND59

GND60

GND61

GND62

GND63

GND64

T33

T34

T35

T37

T38

T7

T9

U18

U20

U22

PP1V8R1V5_S0_FET

4771 mA (A01, DDR3)

70

7 8 11 12 16 24 28 29 39 68 69


8

7 6 5 4 3

2 1

D

C

B

MCP Memory Misc



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

16

OF

97

2 1

D

C

B

A

8 7

9

IN

9 IN

9 IN

9 IN

9 IN

9 IN

9 IN

9 IN

9 IN

9

IN

9

IN

9 IN

9

IN

9

IN

9 IN

9

IN

9

IN

9

IN

9 IN

9

IN

9

IN

9 IN

9

IN

9

IN

9 IN

9 IN

9 IN

9 IN

9

IN

9 IN

9 IN

9

IN

=PEG_D2R_P<0>

=PEG_D2R_N<0>

=PEG_D2R_P<1>

=PEG_D2R_N<1>

=PEG_D2R_P<2>

=PEG_D2R_N<2>

=PEG_D2R_P<3>

=PEG_D2R_N<3>

=PEG_D2R_P<4>

=PEG_D2R_N<4>

=PEG_D2R_P<5>

=PEG_D2R_N<5>

=PEG_D2R_P<6>

=PEG_D2R_N<6>

=PEG_D2R_P<7>

=PEG_D2R_N<7>

=PEG_D2R_P<8>

=PEG_D2R_N<8>

=PEG_D2R_P<9>

=PEG_D2R_N<9>

=PEG_D2R_P<10>

=PEG_D2R_N<10>

=PEG_D2R_P<11>

=PEG_D2R_N<11>

=PEG_D2R_P<12>

=PEG_D2R_N<12>

=PEG_D2R_P<13>

=PEG_D2R_N<13>

=PEG_D2R_P<14>

=PEG_D2R_N<14>

=PEG_D2R_P<15>

=PEG_D2R_N<15>

9 IN

PEG_PRSNT_L

31

31

IN

IN

MINI_CLKREQ_L

PCIE_MINI_PRSNT_L

37

IN

37 9 IN

FW_CLKREQ_L

PCIE_FW_PRSNT_L

9

IN

9 IN

TP_EXCARD_CLKREQ_L


7

TP_PE4_CLKREQ_L

NC_PE4_PRSNT_L

60

84

OUT

AUD_IP_PERIPHERAL_DET

GMUX_JTAG_TCK_L

32 OUT

84 9 6

IN

CARDREADER_RESET

JTAG_GMUX_TDO

31 7 IN

PCIE_WAKE_L

90 31 7 IN

90 31 7 IN

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

90 36

90 36

IN

IN

90 9 IN

90 9 IN

PCIE_FW_D2R_P

PCIE_FW_D2R_N



7

TP_PCIE_PE4_D2RP

NC_PCIE_PE4_D2RN

18 17 14 13 12 11

67 63

10

25

9 8 7 6

24 22 20

PPCPUVTT_S0

57 mA (A01, DVDD0 & 1)

6

18 17 14 13 12 11

67 63

10

25

9 8 7 6

24 22 20

PPCPUVTT_S0

24

PP1V05_S0_MCP_PLL_PEX

84 mA (A01)

90

MCP_PEX_CLK_COMP

NO STUFF

1 R1710

2.37K

1%

1/16W

MF-LF

2

402

PLACEMENT_NOTE=Place within 12.7mm of U1400

5

F7

E7

D7

C7

E6

F6

E5

F5

E4

E3

C3

D3

G5

H5

J7

J6

J5

J4

L11

L10

L9

L8

L7

L6

N11

N10

N9

P9

N7

N6

N5

N4

PE0_RX0_P

PE0_RX0_N

PE0_RX1_P

PE0_RX1_N

PE0_RX2_P

PE0_RX2_N

PE0_RX3_P

PE0_RX3_N

PE0_RX4_P

PE0_RX4_N

PE0_RX5_P

PE0_RX5_N

PE0_RX6_P

PE0_RX6_N

PE0_RX7_P

PE0_RX7_N

PE0_RX8_P

PE0_RX8_N

PE0_RX9_P

PE0_RX9_N

PE0_RX10_P

PE0_RX10_N

PE0_RX11_P

PE0_RX11_N

PE0_RX12_P

PE0_RX12_N

PE0_RX13_P

PE0_RX13_N

PE0_RX14_P

PE0_RX14_N

PE0_RX15_P

PE0_RX15_N

OMIT

U1400

MCP79-TOPO-B

BGA

(5 OF 11)

C5

D4

C4

B4

A4

A3

B3

B2

C1

D1

D2

E1

E2

F2

F3

F4

G3

H4

H3

H2

H1

J1

J2

J3

K2

K3

L4

L3

M4

M3

M2

M1

PE0_TX8_N

PE0_TX9_P

PE0_TX9_N

PE0_TX10_P

PE0_TX10_N

PE0_TX11_P

PE0_TX11_N

PE0_TX12_P

PE0_TX12_N

PE0_TX13_P

PE0_TX13_N

PE0_TX14_P

PE0_TX14_N

PE0_TX15_P

PE0_TX15_N

PE0_TX0_P

PE0_TX0_N

PE0_TX1_P

PE0_TX1_N

PE0_TX2_P

PE0_TX2_N

PE0_TX3_P

PE0_TX3_N

PE0_TX4_P

PE0_TX4_N

PE0_TX5_P

PE0_TX5_N

PE0_TX6_P

PE0_TX6_N

PE0_TX7_P

PE0_TX7_N

PE0_TX8_P

C9

Int PU

PE0_PRSNT_16#

D5

D9

Int PU

PEB_CLKREQ#/GPIO_49

PEB_PRSNT# Int PU

E8

C10

Int PU

PEC_CLKREQ#/GPIO_50

PEC_PRSNT# Int PU

M15

B10

Int PU

PED_CLKREQ#/GPIO_51

PED_PRSNT# Int PU

L16

L18

M16

M18

M17

M19

F17

Int PU

PEE_CLKREQ#/GPIO_16

PEE_PRSNT#/GPIO_46

Int PU

Int PU

PEF_CLKREQ#/GPIO_17

PEF_PRSNT#/GPIO_47

Int PU

Int PU

PEG_CLKREQ#/GPIO_18

PEG_PRSNT#/GPIO_48

Int PU

PE_WAKE# Int PU (S5)

K9

J9

PE1_RX0_P

PE1_RX0_N

H9

G9

PE1_RX1_P

PE1_RX1_N

F9

E9

PE1_RX2_P

PE1_RX2_N

H7

G7

PE1_RX3_P

PE1_RX3_N

PE0_REFCLK_P

PE0_REFCLK_N

E11

D11

PE1_REFCLK_P

PE1_REFCLK_N

PE2_REFCLK_P

PE2_REFCLK_N

PE3_REFCLK_P

PE3_REFCLK_N

PE4_REFCLK_P

PE4_REFCLK_N

G11

F11

J11

J10

G13

F13

J13

H13

PE5_REFCLK_P

PE5_REFCLK_N

L14

K14

PE6_REFCLK_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PE1_TX2_P

PE1_TX2_N

PE1_TX3_P

PE1_TX3_N

N14

M14

K11

D8

C8

B8

A8

A7

B7

B6

C6

4

T17

W19

U17

V19

W16

W17

W18

U16

+DVDD0_PEX1

+DVDD0_PEX2

+DVDD0_PEX3

+DVDD0_PEX4

+DVDD0_PEX5

+DVDD0_PEX6

+DVDD0_PEX7

+DVDD0_PEX8

T19

U19

+DVDD1_PEX1

+DVDD1_PEX2

T16 +V_PLL_PEX

A11 PEX_CLK_COMP

+AVDD0_PEX1

+AVDD0_PEX2

+AVDD0_PEX3

+AVDD0_PEX4

+AVDD0_PEX5

+AVDD0_PEX6

+AVDD0_PEX7

+AVDD0_PEX8

+AVDD0_PEX9

+AVDD0_PEX10

+AVDD0_PEX11

+AVDD0_PEX12

+AVDD0_PEX13

Y12

AA12

AB12

M12

P12

R12

N12

T12

U12

AC12

AD12

V12

W12

+AVDD1_PEX1

+AVDD1_PEX2

+AVDD1_PEX3

M13

N13

P13

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<5>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<6>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<9>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<10>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<12>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<13>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<15>

PEG_CLK100M_P

PEG_CLK100M_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N








TP_PCIE_CLK100M_PE6N


OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

OUT

OUT

71 90

71 90

OUT

OUT

31 90

31 90

7

7

OUT

OUT

36 90

36 90

OUT

OUT

9 90

9 90

7

7

7

8 17 24

3

PCIE_RESET_L

OUT 26 37

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N



TP_PCIE_PE4_R2D_CP

NC_PCIE_PE4_R2D_CN

OUT

OUT

31 90

31 90

OUT

OUT

36 90

36 90

OUT

OUT

9 90

9 90

7


206 mA (A01, AVDD0 & 1)

8 17 24

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.


8

7 6 5 4 3

2 1

D

C

B

MCP PCIe Interfaces



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

17

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

OMIT

U1400

MCP79-TOPO-B

BGA

(6 OF 11)

+3.3V_DUAL_RMGT1

+3.3V_DUAL_RMGT2

J24

K24

34 33 24 18 8 7

PP3V3_ENET_PHY

92 33

IN

92 33 IN

92 33 IN

92 33

IN

ENET_RXD<0>

ENET_RXD<1>

ENET_RXD<2>

ENET_RXD<3>

92 33 IN

92 33 IN

18 9

IN

18 9 IN

18 9

IN

ENET_CLK125M_RXCLK

ENET_RX_CTRL

MCP_MII_PD

MCP_MII_PD

MCP_MII_PD

7

NC_ENET_INTR_L

24

PP1V05_ENET_MCP_PLL_MAC

5 mA (A01)

92

MCP_MII_COMP_VDD

92

MCP_MII_COMP_GND

C23

B23

E24

A24

RGMII_RXD0

RGMII_RXD1

RGMII_RXD2

RGMII_RXD3

A23

C22

RGMII_RXC/MII_RXCLK

RGMII_RXCTL/MII_RXDV

F23

B26

B22

MII_RXER/GPIO_36

MII_COL/GPIO_20/MSMB_DATA

MII_CRS/GPIO_21/MSMB_CLK

J22

RGMII_INTR/GPIO_35

+V_DUAL_RMGT1

+V_DUAL_RMGT2

U23

V23

MII_VREF

E28

RGMII_TXD0

RGMII_TXD1

RGMII_TXD2

RGMII_TXD3

B24

C24

C25

D25

RGMII_TXC/MII_TXCLK

RGMII_TXCTL/MII_TXEN

D24

C26

RGMII_MDC

RGMII_MDIO

D21

C21

RGMII_PWRDWN/GPIO_37 G23

R1810

49.9

1

1%

1/16W

MF-LF

402

2

T23

+V_DUAL_MACPLL

C27

B27

MII_COMP_VDD

MII_COMP_GND

BUF_25MHZ

E23

MII_RESET#

J23

R1811

49.9

1

1%

1/16W

MF-LF

402

2

25

25

NC_MCP_RGB_DAC_RSET

NC_MCP_RGB_DAC_VREF

C39

B38

RGB_DAC_RSET

RGB_DAC_VREF

+V_RGB_DAC

+V_TV_DAC

J32

K32

DDC_CLK0

DDC_DATA0

B31

A31

38 37 34

96 87

30

82

26 24

70 69

22

68

20

64

8 7

54 44

PP3V3_S5

90 25

OUT

90 25 OUT

NC_MCP_TV_DAC_RSET

NC_MCP_TV_DAC_VREF

E36

A35

TV_DAC_RSET

TV_DAC_VREF

R1820

47K

1

5%

1/16W

MF-LF

402

2

25

IN

25 OUT

NC_MCP_CLK27M_XTALIN

NC_MCP_CLK27M_XTALOUT

C38

D38

XTALIN_TV

XTALOUT_TV

44 BI

LPCPLUS_GPIO

DP_CA_DET

E16 GPIO_6/FERR*/IGPU_GPIO_6

B15

GPIO_7/NFERR*/IGPU_GPIO_7

84 82 81 77

IN

MCP Signal TMDS/HDMI

Interface Mode

DisplayPort

9 OUT

84 9 OUT

84 9 OUT

NC_LVDS_IG_BKL_PWM

(See below)

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

=MCP_HDMI_TXC_P/N

=MCP_HDMI_TXD_P/N<0>



=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

DP_IG_AUX_CH_P/N

TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<2>

TMDS_IG_DDC_CLK

TMDS_IG_DDC_DATA

TMDS_IG_HPD

TP_DP_IG_AUX_CHP/N

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<2>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<0>

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_IG_HPD

DP_IG_AUX_CH_P/N

9 OUT

9 OUT

9 OUT

9 OUT

9 OUT

9 OUT

9 OUT

9 OUT

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<2>

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

NOTE: 20K pull-down required on DP_HPD_DET.

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: HDMI port requires level-shifting. IFP interface can

be used to provide HDMI or dual-channel TMDS without

level-shifters.

LVDS: Power +VDD_IFPx at 1.8V

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

90 81 OUT

90 81

OUT

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

84 9 IN

81 9

IN

GMUX_INT

DP_IG_HPD

87 84 70 69 55 25 8 7

PP1V8_S0

190 mA (A01, 1.8V)

(See below)

25

PP3V3_S0_MCP_VPLL

16 mA (A01) 8 mA

8 mA

20 17 14 13 12 11 10

67 63

9 8 7 6

25 24 22

90 25

OUT

PPCPUVTT_S0

95 mA (A01)

MCP_HDMI_RSET

90 25

OUT

MCP_HDMI_VPROBE

G39

E37

F40

LCD_BKL_CTL/GPIO_57

LCD_BKL_ON/GPIO_59

LCD_PANEL_PWR/GPIO_58

D35

E35

HDMI_TXC_P/ML0_LANE3_P

HDMI_TXC_N/ML0_LANE3_N

G35

F35

F33

G33

J33

H33

HDMI_TXD0_P/ML0_LANE2_P

HDMI_TXD0_N/ML0_LANE2_N





D43

C43

DP_AUX_CH0_P

DP_AUX_CH0_N

C31

F31

HPLUG_DET2/GPIO_22

HPLUG_DET3

M27

M26

+VDD_IFPA

+VDD_IFPB

M28

M29

+V_PLL_IFPAB

+V_PLL_HDMI

T25

+VDD_HDMI

J31

J30

HDMI_RSET

HDMI_VPROBE

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

B39

A39

B40

RGB_DAC_HSYNC

RGB_DAC_VSYNC

TV / Component

C / Pr

Y / Y

TV_DAC_RED

TV_DAC_GREEN

Comp / Pb TV_DAC_BLUE

A40

A41

A36

B36

C36

TV_DAC_HSYNC/GPIO_44

TV_DAC_VSYNC/GPIO_45

D36

C37

IFPA_TXC_P

IFPA_TXC_N

B35

C35

IFPA_TXD0_P

IFPA_TXD0_N

IFPA_TXD1_P

IFPA_TXD1_N

IFPA_TXD2_P

IFPA_TXD2_N

B32

A32

D32

C32

D33

IFPA_TXD3_P

IFPA_TXD3_N

C33

B34

C34

IFPB_TXC_P

IFPB_TXC_N

L31

K31

IFPB_TXD4_P

IFPB_TXD4_N

IFPB_TXD5_P

IFPB_TXD5_N

IFPB_TXD6_P

IFPB_TXD6_N

IFPB_TXD7_P

IFPB_TXD7_N

J29

H29

L29

K29

L30

K30

N30

M30

DDC_CLK2/GPIO_23

DDC_DATA2/GPIO_24

C30

B30

DDC_CLK3

DDC_DATA3

D31

E31

IFPAB_RSET

IFPAB_VPROBE

E32

G31

A

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

=DVI_HPD_GMUX_INT:

Alias to DVI_HPD for systems using IFP for DVI.

Alias to GMUX_INT for systems with GMUX.

Alias to HPLUG_DET2 for other systems.

Pull-down (20k) required in all cases.


8

7 6 5 4

PP3V3_ENET_PHY

7 8 18 24 33 34

83 mA (A01)

PP1V2R1V05_ENET

7 8 24 33 34 37

131 mA (A01)

D

MCP_MII_VREF

ENET_TXD<0>

ENET_TXD<1>

ENET_TXD<2>

ENET_TXD<3>

ENET_CLK125M_TXCLK

ENET_TX_CTRL

ENET_MDC

ENET_MDIO

NC_ENET_PWRDWN_L

IN 24

OUT

OUT

OUT

OUT

33 92

33 92

33 92

33 92

OUT

OUT

33 92

33 92

OUT

BI

33 92

33 92

7

MCP_CLK25M_BUF0_R

OUT

34 92

ENET_RESET_L

33 92

OUT

PP3V3_S0_MCP_DAC

103 mA

103 mA

25

206 mA (A01)

MCP_DDC_CLK0

MCP_DDC_DATA0

NC_MCP_RGB_RED

NC_MCP_RGB_GREEN

NC_MCP_RGB_BLUE

NC_MCP_RGB_HSYNC

NC_MCP_RGB_VSYNC

25

25

25

25

25

NC_CRT_IG_R_C_PR

NC_CRT_IG_G_Y_Y

NC_CRT_IG_B_COMP_PB

NC_CRT_IG_HSYNC

NC_CRT_IG_VSYNC

OUT

OUT

OUT

25 90

25 90

25 90

OUT

OUT

25 90

25 90

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

OUT

OUT

LVDS_IG_A_DATA_P<0>

OUT

LVDS_IG_A_DATA_N<0>

OUT

LVDS_IG_A_DATA_P<1>

OUT

LVDS_IG_A_DATA_N<1>

OUT

LVDS_IG_A_DATA_P<2>

OUT

LVDS_IG_A_DATA_N<2>

OUT


OUT

84 90

84 90

84 90

84 90

84 90

84 90

84 90

84 90

9 90

9 90

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

OUT

OUT

LVDS_IG_B_DATA_P<0>

OUT

LVDS_IG_B_DATA_N<0>

OUT

LVDS_IG_B_DATA_P<1>

OUT

LVDS_IG_B_DATA_N<1>

OUT

LVDS_IG_B_DATA_P<2>

OUT

LVDS_IG_B_DATA_N<2>

OUT


OUT


OUT

9 90

9 90

84 90

84 90

84 90

84 90

84 90

84 90

9 90

9 90

LVDS_IG_DDC_CLK

LVDS_IG_DDC_DATA

DP_IG_DDC_CLK

DP_IG_DDC_DATA

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

2

1 R1850

10K

5%

1/16W

MF-LF

402

OUT

BI

81

81

OUT

BI

9 77 81

9 77 81

OUT

OUT

25 90

25 90

R1860

100K

1

5%

1/16W

MF-LF

402

2

1 R1861

100K

2

5%

1/16W

MF-LF

402

Network Interface Select

Interface

RGMII

ENET_TXD<0>

1

MII 0

NOTE: All Apple products set strap to

MII, RGMII products will enable

feature via software. This

avoids a leakage issue since

MCP79 requires a S5 pull-up.

PP3V3_S0 60 63 68 69 70 77 80 81 82 84

6 7 8 13 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

85 96

RGB DAC Disable:

Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

TV DAC Disable:

Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.

DDC_CLK0/DDC_DATA0 pull-ups still required.

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

3

C

B

MCP Ethernet & Graphics



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

18

OF

97

2 1

D

C

B

A

8

8

7 6

91 19

91 19

37 19

OUT

60 OUT

19 IN

PCI_REQ0_L

PCI_REQ1_L

FW_PWR_EN

AUD_IPHS_SWITCH_EN

MCP_RS232_SIN_L

91 13 BI

91 13 BI

91 13

BI

91 13 BI

91 13 BI

91 13 BI

91 13

BI

91 13 BI

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

MCP_DEBUG<0>

MCP_DEBUG<1>

MCP_DEBUG<2>

MCP_DEBUG<3>

MCP_DEBUG<4>

MCP_DEBUG<5>

MCP_DEBUG<6>

MCP_DEBUG<7>

NC_PCI_AD<8>

NC_PCI_AD<9>

NC_PCI_AD<10>

NC_PCI_AD<11>

NC_PCI_AD<12>

NC_PCI_AD<13>

NC_PCI_AD<14>

NC_PCI_AD<15>

NC_PCI_AD<16>

NC_PCI_AD<17>

NC_PCI_AD<18>

NC_PCI_AD<19>

NC_PCI_AD<20>

NC_PCI_AD<21>

NC_PCI_AD<22>

NC_PCI_AD<23>

NC_PCI_AD<24>

NC_PCI_AD<25>

NC_PCI_AD<26>

NC_PCI_AD<27>

NC_PCI_AD<28>

NC_PCI_AD<29>

NC_PCI_AD<30>

NC_PCI_AD<31>

T2

V9

T3

U9

T4

OMIT

U1400

MCP79-TOPO-B

BGA

(7 OF 11)

PCI_REQ0#

PCI_REQ1#/FANRPM2

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ3#/GPIO_38/RS232_CTS#

PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_GNT0#

PCI_GNT1#/FANCTL2

PCI_GNT2#/GPIO_41/RS232_DTR#

PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

R3

U10

R4

U11

P3

AC3

AE10

AC4

AE11

AB3

AC6

AB2

AC7

AC8

AA2

AC9

AC10

AC11

AA1

AA5

Y5

W3

W6

W4

W7

V3

W8

V2

W9

U3

W11

U2

U5

U1

U6

T5

U7

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

PCI_AD21

PCI_AD22

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD26

PCI_AD27

PCI_AD28

PCI_AD29

PCI_AD30

PCI_AD31

PCI_AD0

PCI_AD1

PCI_AD2

PCI_AD3

PCI_AD4

PCI_AD5

PCI_AD6

PCI_AD7

PCI_AD8

PCI_AD9

PCI_AD10

PCI_AD11

PCI_AD12

PCI_AD13

PCI_AD14

PCI_CBE0#

PCI_CBE1#

PCI_CBE2#

PCI_CBE3#

AA3

AA6

AA11

W10

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_SERR#

PCI_STOP#

AA9

Y4

AA10

Y1

AB9

AA7

Y2

PCI_PME#/GPIO_30

Int PU (S5)

T1

PCI_RESET0#

PCI_RESET1#

R10

R11

PCI_CLK0

PCI_CLK1

PCI_CLK2

R6

R7

R8

PCI_CLKIN

R9

7

7

7

NC_PCI_INTW_L

NC_PCI_INTX_L

TP_PCI_INTY_L

NC_PCI_INTZ_L

7

NC_PCI_TRDY_L

44 42 IN

PM_CLKRUN_L

37 9 IN

44 42 BI

7

FW_PLUG_DET_L

NC_LPC_DRQ0_L

LPC_SERIRQ

P2

N3

N2

N1

PCI_INTW#

PCI_INTX#

PCI_INTY#

PCI_INTZ#

Y3 PCI_TRDY#

AD11 PCI_CLKRUN#/GPIO_42

AE2

AE1

AE6

LPC_DRQ1#/GPIO_19

LPC_DRQ0#

Int PU

Int PU

LPC_SERIRQ Int PU

LPC_FRAME#

LPC_PWRDWN#/GPIO_54/EXT_NMI#

AD4

AE12

LPC_RESET0# AE5

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

AD3

AD2

AD1

AD5

LPC_CLK0 AE9

V24

V26

V27

V28

V33

V37

V4

V40

V7

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

U24

U26

U39

U4

U8

V16

V17

V18

V20

V22

GND76

GND77

GND78

GND79

GND80

GND81

GND82

GND83

GND84

GND85

GND86

GND87

GND88

GND65

GND66

GND67

GND68

GND69

GND70

GND71

GND72

GND73

GND74

GND75

GND89

GND90

GND91

GND92

GND93

GND94

GND95

GND96

GND97

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

Y26

Y27

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

GND109

GND110

GND111

GND112

GND113

GND114

GND115

GND116

GND117

GND118

GND119

GND120

GND121

GND98

GND99

GND100

GND101

GND102

GND103

GND104

GND105

GND106

GND107

GND108

GND122

GND123

GND124

GND125

GND126

GND127

GND128

GND129

GND130

5 4

NC_PCI_GNT0_L

NC_PCI_GNT1_L

JTAG_GMUX_TMS

JTAG_GMUX_TDI

MCP_RS232_SOUT_L

NC_PCI_C_BE_L<0>

NC_PCI_C_BE_L<1>

NC_PCI_C_BE_L<2>

NC_PCI_C_BE_L<3>

NC_PCI_DEVSEL_L

NC_PCI_FRAME_L

NC_PCI_IRDY_L

TP_PCI_PAR

NC_PCI_PERR_L

NC_PCI_SERR_L

NC_PCI_STOP_L

PM_LATRIGGER_L

7

7

7

7

7

7

OUT

OUT

OUT

6 9 84

6 9 84

19

7

7

7

7

7

7

OUT

13

MEM_VTT_EN_R

NC_PCI_RESET1_L

OUT

7

26

NC_PCI_CLK0

NC_PCI_CLK1

91

PCI_CLK33M_MCP_R

7

7

1 R1910

22

2

5%

1/16W

MF-LF

402

PLACEMENT_NOTE=Place close to pin R8

91

PCI_CLK33M_MCP

3

LPC_FRAME_R_L

LPC_PWRDWN_L

LPC_RESET_L

LPC_AD_R<0>

LPC_AD_R<1>

LPC_AD_R<2>

LPC_AD_R<3>

LPC_CLK33M_SMC_R

R1960

R1950

R1951

R1952

R1953

22

1

22

22

22

22

1

1

1

1

2

5% 1/16W MF-LF 402

LPC_FRAME_L

OUT

OUT

42 44 84 91

42 44

OUT 26 84 91

2

2

2

2

5% 1/16W MF-LF

5% 1/16W MF-LF

402

402

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

LPC_AD<0>

LPC_AD<1>

LPC_AD<2>

LPC_AD<3>

BI

BI

BI

BI

42 44 84 91

42 44 84 91

42 44 84 91

42 44 84 91

OUT 26 91

1 R1961

10K

5%

1/16W

MF-LF

2

402

Strap for Boot ROM Selection (See HDA_SDOUT)

2 1

19

MCP_RS232_SOUT_L

91 19

91 19

37 19

19

PCI_REQ0_L

PCI_REQ1_L

FW_PWR_EN

MCP_RS232_SIN_L

84 82 81 80 77 70 69 68 63 60

29 28 25 24 22

59 55 51 49

21

48

18

47

13 8

45 43

7 6

39 37

96 85

PP3V3_S0

R1989 8.2K

1 2

5% 1/16W

R1990

R1991

R1992

R1994

8.2K

8.2K

8.2K

8.2K

1

1

1

1

2

2

2

2

5%

5%

1/16W

1/16W

MF-LF

MF-LF

MF-LF

402

402

402

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

D

C

B

7 6 5 4 3

MCP PCI & LPC



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

19

OF

97

2 1

D

C

B

A

8 7 6 5 4 3

90 39 OUT

90 39 OUT

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

90 39 IN

90 39 IN

SATA_HDD_D2R_N

SATA_HDD_D2R_P

90 39 OUT

90 39

OUT

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

90 39 IN

90 39

IN

SATA_ODD_D2R_N

SATA_ODD_D2R_P

7

7

NC_SATA_C_R2D_CP

NC_SATA_C_R2D_CN

7

TP_SATA_C_D2RN

NC_SATA_C_D2RP

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

7

7

NC_SATA_D_D2RN

NC_SATA_D_D2RP

AJ7

AJ6

SATA_A0_TX_P

SATA_A0_TX_N

AJ5

AJ4

SATA_A0_RX_N

SATA_A0_RX_P

AJ11

AJ10

SATA_A1_TX_P

SATA_A1_TX_N

AJ9

AK9

SATA_A1_RX_N

SATA_A1_RX_P

AK2

AJ3

SATA_B0_TX_P

SATA_B0_TX_N

AJ2

AJ1

SATA_B0_RX_N

SATA_B0_RX_P

AM4

AL3

SATA_B1_TX_P

SATA_B1_TX_N

AL4

AK3

SATA_B1_RX_N

SATA_B1_RX_P

OMIT

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_E_D2RP

USB0_P

USB0_N

C29

D29

USB1_P

USB1_N

C28

D28

USB2_P

USB2_N

A28

B28

USB3_P

USB3_N

F29

G29

USB4_P

USB4_N

K27

L27

USB5_P

USB5_N

J26

J27

USB6_P

USB6_N

F27

G27

USB7_P

USB7_N

D27

E27

USB8_P

USB8_N

K25

L25

USB9_P

USB9_N

H25

J25

External A

USB_EXTA_P

USB_EXTA_N

AirPort (PCIe Mini-Card)

NC_USB_MINIP

NC_USB_MININ

External D

NC_USB_EXTDP

NC_USB_EXTDN

Camera

USB_CAMERA_P

USB_CAMERA_N

IR

USB_IR_P

USB_IR_N

Geyser Trackpad/Keyboard

USB_TPAD_P

USB_TPAD_N

Bluetooth

USB_BT_P

USB_BT_N

External B

USB_EXTB_P

USB_EXTB_N

ExpressCard

NC_USB_EXCARDP

NC_USB_EXCARDN

External C

NC_USB_EXTCP

NC_USB_EXTCN

BI

BI

40 91

40 91

BI

BI

9 91

9 91

BI

BI

9 91

9 91

BI

BI

7 31 91

7 31 91

BI

BI

41 91

41 91

BI

BI

50 91

50 91

BI

BI

7 31 91

7 31 91

BI

BI

40 91

40 91

BI

BI

9 91

9 91

BI

BI

9 91

9 91

USB10_P

USB10_N

F25

G25

USB11_P

USB11_N

K23

L23

NC_USB_10P

NC_USB_10N

SD Card Reader

USB_CARDREADER_P

USB_CARDREADER_N

7

7

BI

BI

9 32 96

9 32 96

AN1

AM1

SATA_C0_TX_P

SATA_C0_TX_N

AM2

AM3

SATA_C0_RX_N

SATA_C0_RX_P

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_F_D2RP

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26

USB_OC2#/GPIO_27/MGPIO

USB_OC3#/GPIO_28/MGPIO

L21

K21

J21

H21

TP_MCP_SATALED_L

24

PP1V05_S0_MCP_PLL_SATA

84 mA (A01)

18 17 14 13

PPCPUVTT_S0

12 11

67

10

63

9 8 7 6

25 24 22

43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

GND


24 8

127 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 support

GND

AP3

AP2

SATA_C1_TX_P

SATA_C1_TX_N

AN3

AN2

SATA_C1_RX_N

SATA_C1_RX_P

E12 SATA_LED#

AE16 +V_PLL_SATA

AF19

AG16

AG17

AG19

+DVDD0_SATA1

+DVDD0_SATA2

+DVDD0_SATA3

+DVDD0_SATA4

AH17

AH19

+DVDD1_SATA1

+DVDD1_SATA2

AJ12

AN11

AK12

AK13

AL12

AM11

AM12

AN12

AL13

+AVDD0_SATA1

+AVDD0_SATA2

+AVDD0_SATA3

+AVDD0_SATA4

+AVDD0_SATA5

+AVDD0_SATA6

+AVDD0_SATA7

+AVDD0_SATA8

+AVDD0_SATA9

AN14

AL14

AM13

AM14

+AVDD1_SATA1

+AVDD1_SATA2

+AVDD1_SATA3

+AVDD1_SATA4

AE3

SATA_TERMP

+V_PLL_USB

L28

USB_RBIAS_GND A27

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

GND131

GND132

GND133

GND134

GND135

GND136

GND137

GND138

GND139

GND140

GND141

GND142

GND143

GND144

GND145

GND146

GND147

GND148

GND149

GND150

GND151

GND152

GND153

GND154

GND155

GND156

GND157

GND158

GND159

GND160

PP3V3_S0_MCP_PLL_USB

19 mA (A01)

24

91

MCP_USB_RBIAS_GND

R2060

806

1

1%

1/16W

MF-LF

402

2

90

MCP_SATA_TERMP

1 R2010

2.49K

2

1%

1/16W

MF-LF

402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

2

PP3V3_S5

R2050

8.2K

1

5%

1/16W

MF-LF

402

2

1 R2051

8.2K

2

5%

1/16W

MF-LF

402

R2052

8.2K

1

5%

1/16W

MF-LF

402

2

1 R2053

8.2K

2

5%

1/16W

MF-LF

402

USB_EXTA_OC_L

USB_EXTB_OC_L

USB_EXTC_OC_L

EXCARD_OC_L

40

40

43

7 8 18 22 24 26 30 34 37 38 44

54 64 68 69 70 82 87 96


8

7 6 5 4 3

1

D

C

B

MCP SATA & USB



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

20

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

77 70

25 24

69

22

68 63 60 59

21 19 18 13

55 51

8 7 6

49 48 47 45

96

43 39

85 84

37

82

29

81

28

80

PP3V3_S0

1 R2110

49.9

1%

1/16W

MF-LF

2

402

46 45 44 43 42 40 26

69 64

22 8 7

62 61 50

PP3V42_G3H

R2120

49.9K

1

1%

1/16W

MF-LF

402

2

1 R2121

49.9K

2

1%

1/16W

MF-LF

402

OMIT

U1400

MCP79-TOPO-B

BGA

(9 OF 11)

+V_DUAL_HDA1

+V_DUAL_HDA2

J16

K16

HDA_SDATA_OUT

F15

91 55 IN

7

HDA_SDIN0

NC_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

(MXM_OK for MXM systems)

G15

HDA_SDATA_IN0

Int PD

J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

Int PD

J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

Int PD

HDA_BITCLK E15

HDA_RESET* K15

HDA_SYNC L15

91

MCP_HDA_PULLDN_COMP

24

PP1V05_S0_MCP_PLL_NV

37 mA (A01) 20 mA

17 mA

A15

HDA_PULLDN_COMP

AE18

AE17

+V_PLL_NV_H

+V_PLL_SP_SPREF

44

OUT

43 42 37 34 IN

SPIROM_USE_MLB

SMC_ADAPTER_EN

42 IN

42

IN

7

NC_SB_A20GATE

TP_MCP_KBDRSTIN_L

SMC_WAKE_SCI_L

SMC_RUNTIME_SCI_L

SM_INTRUDER_L

42 IN

88 63

IN

TP_MCP_LID_L

PM_BATLOW_L

PM_DPRSLPVR

42 IN

26

IN

PM_PWRBTN_L

PM_SYSRST_DEBOUNCE_L

RTC_RST_L

42 IN

26 IN

PM_RSMRST_L

MCP_PS_PWRGD

MCP_CPU_VLD

26 IN

13 6 IN

6 OUT

13 6 IN

76 13 6 IN

76 13 6

IN

JTAG_MCP_TDI

JTAG_MCP_TDO

JTAG_MCP_TMS

JTAG_MCP_TRST_L

JTAG_MCP_TCK

26 IN

26

OUT

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

26 IN

26

OUT

RTC_CLK32K_XTALIN

RTC_CLK32K_XTALOUT

R2150 1

10K

5%

1/16W

MF-LF

402

2

L24

L26

GPIO_1/PWRDN_OK/SPI_CS1

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

K13

L13

C19

C18

A20GATE

Int PU

KBRDRSTIN* Int PU

SIO_PME* Int PU (S5)

EXT_SMI/GPIO_32* Int PU (S5)

B20 INTRUDER*

M25

M24

LID*

LLB*

Int PU (S5)

Int PU (S5)

M22 CPU_DPRSLPVR

C16

D16

PWRBTN*

RSTBTN*

Int PU (S5)

Int PU

1 R2151

2

100K

5%

1/16W

MF-LF

402

C20 RTC_RST*

D20

E20

PWRGD_SB

PS_PWRGD

C17

CPU_VLD

E19

F19

J19

J18

G19

JTAG_TDI Int PU

JTAG_TDO

JTAG_TMS

Int PU

JTAG_TRST*

JTAG_TCK

A16

B16

XTALIN

XTALOUT

A19

B19

XTALIN_RTC

XTALOUT_RTC

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

K17

L17

SLP_S3*

SLP_RMGT*

SLP_S5*

G17

J17

H17

THERM_DIODE_P

THERM_DIODE_N

B11

C11

MCP_VID0/GPIO_13

MCP_VID1/GPIO_14

MCP_VID2/GPIO_15

L20

M20

M21

SPKR C13

SMB_CLK0

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

L19

K19

G21

F21

M23

(MGPIO2)

(MGPIO3)

FANRPM0/GPIO_60

FANCTL0/GPIO_61

FANRPM1/GPIO_63

FANCTL1/GPIO_62

B12

A12

D12

C12

CPUVDD_EN

D17

SPI_CS0/GPIO_10

SPI_CLK/GPIO_11

SPI_DI/GPIO_8

SPI_DO/GPIO_9

C14

D13

C15

B14

SUS_CLK/GPIO_34

BUF_SIO_CLK

B18

AE7

TEST_MODE_EN

PKG_TEST

K22

L22

PP3V3_S0

81 82 84 85 96

45 47 48 49 51 55 59 60 63 68

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43

2

1 R2160

8.2K

5%

1/16W

MF-LF

402

91 21

HDA_SDOUT_R

91 21

HDA_BIT_CLK_R

91 21

HDA_RST_R_L

91 21

HDA_SYNC_R

MCP_GPIO_4

AUD_I2C_INT_L

PM_SLP_S3_L

PM_SLP_RMGT_L

PM_SLP_S4_L

MCP_THMDIODE_P

MCP_THMDIODE_N

MCP_VID<0>

MCP_VID<1>

MCP_VID<2>

MCP_SPKR

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

AP_PWR_EN

R2171

22

1 2

5%

1/16W

MF-LF

402

R2170

22

1 2

5%

1/16W

MF-LF

402

R2172

22

1 2

5%

1/16W

MF-LF

402

R2173

22

1 2

5%

1/16W

MF-LF

402

21

IN

21 60

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

OUT

OUT

OUT

7 34 37 42 69 82 84

9 34

7 40 42 43 69 70

OUT

OUT

48 96

48 96

OUT

OUT

21 66

21 66

OUT

21 66

OUT 13 28 29 45 91

13 28 29 45 91

BI

OUT

BI

OUT

45 60 85 91

45 60 85 91

21 31 34

OUT 55 91

OUT 55 91

OUT 55 91

OUT

55 91

PP3V3_S0

BOOT_MODE_SAFE

2

1 R2180

10K

5%

1/16W

MF-LF

402

51 55 59 60 63 68 69 70 77

6 7 8 13 18 19 21 22 24 25

28 29 37 39 43 45 47 48 49

80 81 82 84 85 96

9

OUT

BOOT_MODE_USER

1 R2181

10K

5%

1/16W

MF-LF

USER mode: Normal

SAFE mode: For ROMSIP

2

402

recovery

Connects to SMC for automatic recovery.

I/F

LPC

PCI

SPI0

SPI1

BIOS Boot Select

HDA_SDOUT

0

LPC_FRAME#

0

0

1

1

1

0

1

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

LPC_FRAME# high for SPI1 ROM override.

NOTE: MCP79 does not support FWH, only

LPC ROMs. So Apple designs will

not use LPC for BootROM override.

NOTE: MCP79 rev A01 does not support

SPI1 option. Rev B01 will.

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

HDA_SYNC

1

0

MEM_EVENT_L

ODD_PWR_EN_L

SMC_IG_THROTTLE_L

ARB_DETECT

MCP_CPUVDD_EN

SPI_CS0_R_L

SPI_CLK_R

SPI_MISO

SPI_MOSI_R

IN

OUT

21 28 29 42

39

21 42 43

IN

21

OUT 26

OUT

OUT

IN

OUT

44 91

44 91

44 91

44 91

SPI Frequency Select

Frequency SPI_DO SPI_CLK

31 MHz

42 MHz

25 MHz

1 MHz

1

1

0

0

0

1

0

1

NOTE: Straps not provided on this page.

PM_CLK32K_SUSCLK_R

TP_MCP_BUF_SIO_CLK

MCP_TEST_MODE_EN

1 R2163

10K

2

5%

1/16W

MF-LF

402

OUT 26 91

1 R2190

1K

2

1%

1/16W

MF-LF

402

D

C

B

A

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SYNC_R

21 91

21 91

21 91

21 91

C2170

10PF

5%

50V

CERM

402

1

2

C2172

10PF

5%

50V

CERM

402

1

2

1

2

C2171

10PF

5%

50V

CERM

402

1

2

C2173

10PF

5%

50V

CERM

402


8

7 6

PP3V3_S0

1 R2140

10K

5%

1/16W

2

MF-LF

402

1 R2141

10K

5%

1/16W

2

MF-LF

402

1 R2142

10K

5%

1/16W

2

MF-LF

402

1 R2143

10K

5%

1/16W

2

MF-LF

402

MCP_GPIO_4

AUD_I2C_INT_L

MEM_EVENT_L

SMC_IG_THROTTLE_L

ARB_DETECT

1 R2147

100K

2

5%

1/16W

MF-LF

402

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

21

21 60

21 28 29 42

21 42 43

21

PP3V3_S3

2 R2154

100K

5%

1/16W

1

MF-LF

402

AP_PWR_EN

21 31 34

1 R2155

22K

2

5%

1/16W

MF-LF

402

1 R2156

22K

2

5%

1/16W

MF-LF

402

MCP_VID<0>

MCP_VID<1>

MCP_VID<2>

21 66

21 66

21 66

1 R2157

22K

2

5%

1/16W

MF-LF

402

7 8 27 31 32 45 50 52 70

5 4 3







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

21

OF

97

2

MCP HDA & MISC



1

A

D

C

B

A

8

OMIT

U1400

MCP79-TOPO-B

BGA

(11 OF 11)

AL5

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28

AN30

AN39

AN4

Y7

AP10

AU26

AH26

AH33

AH34

AH37

AH38

AJ39

AJ8

AK10

AK33

AK34

AK37

AK4

AK40

AL36

AL40

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP4

AP40

AP7

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AU4

G28

F20

AV28

AV32

AV36

AV4

AV7

AW11

G20

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

GND203

GND204

GND205

GND206

GND207

GND208

GND209

GND210

GND211

GND212

GND213

GND214

GND215

GND186

GND187

GND188

GND189

GND190

GND191

GND192

GND193

GND194

GND195

GND196

GND197

GND198

GND199

GND200

GND201

GND202

GND174

GND175

GND176

GND177

GND178

GND179

GND180

GND181

GND182

GND183

GND184

GND185

GND161

GND162

GND163

GND164

GND165

GND166

GND167

GND168

GND169

GND170

GND171

GND172

GND173

GND229

GND230

GND231

GND232

GND233

GND234

GND235

GND236

GND237

GND238

GND239

GND240

GND241

GND242

GND243

GND216

GND217

GND218

GND219

GND220

GND221

GND222

GND223

GND224

GND225

GND226

GND227

GND228

GND244

GND245

GND246

GND247

GND248

GND249

GND250

GND251

GND252

GND253

GND254

GND255

GND256

GND257

GND258

GND259

GND260

GND261

GND262

GND263

GND264

GND265

GND266

GND267

GND268

GND269

GND270

GND271

GND272

GND273

GND274

GND275

GND276

GND277

GND278

GND279

GND280

GND281

GND282

GND283

GND284

GND285

GND286

GND287

GND288

GND289

GND290

GND291

GND292

GND293

GND294

GND295

GND296

GND297

GND298

GND299

GND300

GND301

GND302

GND303

GND304

GND305

GND306

GND307

GND308

GND309

GND310

GND311

GND312

GND313

GND314

GND315

GND316

GND317

GND318

GND319

GND320

GND321

GND322

GND323

GND324

GND325

GND326

GND327

GND328

GND329

GND330

GND331

GND332

GND333

GND334

GND335

GND336

GND337

GND338

GND339

GND340

GND341

GND342

GND343

D18

D19

D22

D23

D26

D30

D37

D6

E13

E17

E21

E25

E29

E33

F12

F16

F32

F8

G10

G12

G14

G16

BC12

G22

G24

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

C2

D10

D14

D15

AW20

G34

G4

G43

G6

G8

H11

H15

AW35

H23

AN8

G40

J12

J8

K10

K12

K18

K26

K37

K4

K40

K8

AU1

L40

L43

L5

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

Y6

T11

V11

Y11

AH16

T22

7


8

7 6

6 5 4

66 46 24 8 7

PPVCORE_S0_MCP_REG

23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AF2

AF21

AF23

AF25

AF3

AF4

AF7

AH23

AF9

AA20

AG11

AG12

AG21

AG23

AG25

AG3

AG4

AA21

AG6

AG7

AG8

AG9

AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

AH21

AA24

W21

W23

W25

AF12

AH3

AH4

AH5

AH6

AH7

AH9

AA25

AC23

U25

AH12

AG10

AG5

Y21

Y23

AA16

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC24

AC25

AC26

AC27

AC28

AD21

AD23

W27

V25

AA18

AE19

OMIT

U1400

MCP79-TOPO-B

BGA

(10 OF 11)

R32

AC32

E40

J36

N32

T32

U32

V32

W32

P31

AF32

AE32

AH32

AJ32

AK31

C40

C41

C42

D39

D40

D41

AK32

AD32

AL31

AB32

B41

B42

E38

E39

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

P32

Y32

AA32

+VTT_CPU1

+VTT_CPU2

+VTT_CPU3

+VTT_CPU4

+VTT_CPU5

+VTT_CPU6

+VTT_CPU7

+VTT_CPU8

+VTT_CPU9

+VTT_CPU10

+VTT_CPU11

+VTT_CPU12

+VTT_CPU13

+VTT_CPU14

+VTT_CPU15

+VTT_CPU16

+VTT_CPU17

+VTT_CPU18

+VTT_CPU19

+VTT_CPU20

+VTT_CPU21

+VTT_CPU22

+VTT_CPU23

+VTT_CPU24

+VTT_CPU25

+VTT_CPU26

+VTT_CPU27

+VTT_CPU28

+VTT_CPU29

+VTT_CPU30

+VTT_CPU31

+VTT_CPU32

+VTT_CPU33

+VTT_CPU34

+VTT_CPU35

+VTT_CPU36

+VTT_CPU37

+VTT_CPU38

+VTT_CPU39

+VTT_CPU40

+VTT_CPU41

+VTT_CPU42

+VTT_CPU43

+VTT_CPU44

+VTT_CPU45

+VTT_CPU46

+VTT_CPU47

+VTT_CPU48

+VTT_CPU49

+VTT_CPU50

+VTT_CPU51

+VTT_CPU52

+VDD_CORE43

+VDD_CORE44

+VDD_CORE45

+VDD_CORE46

+VDD_CORE47

+VDD_CORE48

+VDD_CORE49

+VDD_CORE50

+VDD_CORE51

+VDD_CORE52

+VDD_CORE53

+VDD_CORE54

+VDD_CORE55

+VDD_CORE56

+VDD_CORE57

+VDD_CORE58

+VDD_CORE59

+VDD_CORE60

+VDD_CORE61

+VDD_CORE62

+VDD_CORE63

+VDD_CORE64

+VDD_CORE65

+VDD_CORE66

+VDD_CORE67

+VDD_CORE68

+VDD_CORE69

+VDD_CORE70

+VDD_CORE71

+VDD_CORE72

+VDD_CORE73

+VDD_CORE74

+VDD_CORE75

+VDD_CORE76

+VDD_CORE77

+VDD_CORE78

+VDD_CORE79

+VDD_CORE80

+VDD_CORE81

+VDD_CORE1

+VDD_CORE2

+VDD_CORE3

+VDD_CORE4

+VDD_CORE5

+VDD_CORE6

+VDD_CORE7

+VDD_CORE8

+VDD_CORE9

+VDD_CORE10

+VDD_CORE11

+VDD_CORE12

+VDD_CORE13

+VDD_CORE14

+VDD_CORE15

+VDD_CORE16

+VDD_CORE17

+VDD_CORE18

+VDD_CORE19

+VDD_CORE20

+VDD_CORE21

+VDD_CORE22

+VDD_CORE23

+VDD_CORE24

+VDD_CORE25

+VDD_CORE26

+VDD_CORE27

+VDD_CORE28

+VDD_CORE29

+VDD_CORE30

+VDD_CORE31

+VDD_CORE32

+VDD_CORE33

+VDD_CORE34

+VDD_CORE35

+VDD_CORE36

+VDD_CORE37

+VDD_CORE38

+VDD_CORE39

+VDD_CORE40

+VDD_CORE41

+VDD_CORE42

+VTT_CPUCLK

AG32

+3.3V_1

+3.3V_2

+3.3V_3

+3.3V_4

+3.3V_5

+3.3V_6

+3.3V_7

+3.3V_8

AD10

AE8

AB10

AD9

Y10

AB11

AA8

Y9

+3.3V_DUAL1

+3.3V_DUAL2

+3.3V_DUAL3

+3.3V_DUAL4

G18

H19

J20

K20

+3.3V_DUAL_USB1

+3.3V_DUAL_USB2

+3.3V_DUAL_USB3

+3.3V_DUAL_USB4

G26

H27

J28

K28

46 45 44 43 42

69

40

64

26

62

21 8 7

61 50

PP3V42_G3H

10 uA (G3)

80 uA (S0)

A20

+VBAT

+VDD_AUXC1

+VDD_AUXC2

+VDD_AUXC3

T21

U21

V21

PPCPUVTT_S0

1139 mA

43 mA

PP3V3_S0

PP3V3_S5

16 mA

250 mA

PP1V2R1V05_S5

7 8 24 34 68

105 mA (A01)

3

6 7 8 9 10 11 12 13 14 17 18 20

24 25 63 67

1182 mA (A01)

82 84 85 96

47 48 49 51 55 59 60 63 68 69

6 7 8 13 18 19 21 24 25 28 29

37 39 43 45

450 mA (A01)

70 82 87 96

7 8 18 20 24 26 30 34 37 38 44

54 64 68 69

266 mA (A01)

5 4 3

2 1

D

C

B

MCP Power & Ground



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

22

OF

97

2 1

D

8 7 6 5 4 3 2 1

D

C C

B B

A

8

7 6 5 4 3

MCP79 A01 Silicon Support



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

23

OF

97

2 1

8 7 6 5 4

MCP Core Power

66 46 22 8 7

PPVCORE_S0_MCP_REG

23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)

(No IG vs. EG data)

C2500

4.7UF

20%

4V

X5R

402

1

2

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

C2501

4.7UF

20%

4V

X5R

402

1

2

C2502

4.7UF

20%

4V

X5R

402

1

2

C2503

4.7UF

20%

4V

X5R

402

1

2

1

2

C2504

1UF

10%

10V

X5R

402-1

1

2

C2505

1UF

10%

10V

X5R

402-1

1

2

C2506

1UF

10%

10V

X5R

402-1

1

2

C2507

1UF

10%

10V

X5R

402-1

1

2

C2508

0.1UF

20%

10V

CERM

402

1

2

C2509

0.1UF

20%

10V

CERM

402

1

2

C2510

0.1UF

20%

10V

CERM

402

1

2

C2511

0.1UF

20%

10V

CERM

402

1

2

C2512

0.1UF

20%

10V

CERM

402

1

2

C2513

0.1UF

20%

10V

CERM

402

D

MCP PCIE (DVDD) Power

17 14 13 12 11 10 9 8 7 6

67 63 25 24 22 20 18

PPCPUVTT_S0

57 mA (A01)

C2515

4.7UF

20%

4V

X5R

402

1

2

1

2

C2516

1UF

10%

10V

X5R

402-1

1

2

C2517

1UF

10%

10V

X5R

402-1

MCP SATA (DVDD) Power

18 17 14 13 12 11

67 63

10 9 8 7

25 24 22

6

20

PPCPUVTT_S0

43 mA (A01)

1

2

C2518

0.1uF

20%

10V

CERM

402

1

2

C2519

0.1uF

20%

10V

CERM

402

C2520

4.7UF

20%

4V

X5R

402

1

2

1

2

C2521

0.1uF

20%

10V

CERM

402

18 17 14 13 12

67

11 10

63 25

9 8

24

7 6

22 20

PPCPUVTT_S0

333 mA (A01)

MCP 1.05V AUX Power

68 34 22 8 7

PP1V2R1V05_S5

105 mA (A01)

1

2

C2525

0.1uF

20%

10V

CERM

402

1

2

C2526

0.1uF

20%

10V

CERM

402

MCP 1.05V RMGT Power

37 34 33 24 18 8 7

PP1V2R1V05_ENET

131 mA (A01)

C2528

4.7uF

20%

4V

X5R

402

1

2

1

2

C2529

0.1uF

20%

10V

CERM

402

MCP FSB (VTT) Power

17 14 13 12 11 10

67 63 25 24

9 8

22

7 6

20 18

PPCPUVTT_S0

1182 mA (A01)

C

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)

1

2

C2530

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2531

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2532

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2533

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2534

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2535

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2536

2.2UF

20%

6.3V

CERM

402-LF

68 8 7


562 mA (A01)

MCP Memory Power

29 28 16 12 11 8 7

70 69 68 39

PP1V8R1V5_S0_FET

4771 mA (A01, DDR3)

C2540

4.7UF

20%

4V

X5R

402

1

2

1

2

C2541

0.1UF

20%

10V

CERM

402

1

2

C2542

0.1UF

20%

10V

CERM

402

1

2

C2543

0.1UF

20%

10V

CERM

402

1

2

C2544

0.1UF

20%

10V

CERM

402

1

2

C2545

0.1UF

20%

10V

CERM

402

1

2

C2546

0.1UF

20%

10V

CERM

402

1

2

C2547

0.1UF

20%

10V

CERM

402

1

2

C2548

0.1UF

20%

10V

CERM

402

1

2

C2549

0.1UF

20%

10V

CERM

402

MCP 3.3V Power

68 63 60 59 55 51

96

49 48 47 PP3V3_S0

45 43

85 84

21

39

19

37

18 13

29 28

8

25

7 6

24 22

82 81 80 77 70 69

450 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)

82 81 80 77 70 69 68 63 60 59

28 25

55

24 22

51 49

21 19

48 47

18 13

45 43

8

39

7

37

6

29

96 85 84

PP3V3_S0

19 mA (A01)

1

2

C2550

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2551

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2552

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2553

2.2UF

20%

6.3V

CERM

402-LF

L2555

30-OHM-1.7A

1 2

0402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

PP3V3_S0_MCP_PLL_USB



VOLTAGE=3.3V

20

19 mA (A01)

1

2

C2555

2.2UF

20%

6.3V

CERM

402-LF

B

MCP 3.3V AUX/USB Power

96 87 82

30 26 22 20 18 8 7

70 69 68 64 54 44 38 37 34

PP3V3_S5

266 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

C2560

2.2UF

20%

6.3V

CERM

402-LF

MCP 3.3V Ethernet Power

34 33 24 18 8 7

PP3V3_ENET_PHY

83 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

C2564

2.2UF

20%

6.3V

CERM

402-LF

MCP 3.3V/1.5V HDA Power

68 63

96

60 59

21

55 51

19 18

49 48

13 8

47

7 6

45 43

85 84

39 37 29 28

82 81 80 77

25 24 22

70 69

PP3V3_S0

7 mA (A01)

A

37 34 33 24 18 8 7

PP1V2R1V05_ENET

5 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

C2562

2.2UF

20%

6.3V

CERM

402-LF

L2595

30-OHM-1.7A

1 2

0402

C2595

4.7UF

20%

4V

X5R

402

1

2

PP1V05_ENET_MCP_PLL_MAC



VOLTAGE=1.05V

18

5 mA (A01)

1

2

C2596

0.1UF

20%

10V

CERM

402

MCP79 Ethernet VRef

34 33 24 18 8 7

PP3V3_ENET_PHY

R2591

1.47K

1

1%

1/16W

MF-LF

402

2

MCP_MII_VREF

OUT

18

R2590

1.47K

1

1%

1/16W

MF-LF

402

2

1

2

C2591

0.1UF

20%

10V

CERM

402


8

7 6 5 4

3 2 1

1

L2570

30-OHM-5A

2

0603

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 5x 2.2uF 0402 (11 uF)




VOLTAGE=1.05V

8 17

206 mA (A01)

1

2

C2570

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2571

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2572

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2573

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2574

2.2UF

20%

6.3V

CERM

402-LF

D

1

L2575

30-OHM-5A

2

0603

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)




VOLTAGE=1.05V

8 20

127 mA (A01)

1

2

C2575

2.2UF

20%

6.3V

CERM

402-LF

1

2

C2576

2.2UF

20%

6.3V

CERM

402-LF

L2580

30-OHM-1.7A

1 2

0402

C2580

4.7UF

20%

4V

X5R

402

1

2

PP1V05_S0_MCP_PLL_FSB



VOLTAGE=1.05V

14

270 mA (A01)

1

2

C2581

0.1UF

20%

10V

CERM

402

L2582

30-OHM-1.7A

1 2

0402

C2582

4.7UF

20%

4V

X5R

402

1

2

PP1V05_S0_MCP_PLL_PEX



VOLTAGE=1.05V

17

84 mA (A01)

1

2

C2583

0.1UF

20%

10V

CERM

402

C

L2584

30-OHM-1.7A

1 2

0402

C2584

4.7UF

20%

4V

X5R

402

1

2

PP1V05_S0_MCP_PLL_SATA



VOLTAGE=1.05V

20

84 mA (A01)

1

2

C2585

0.1UF

20%

10V

CERM

402

B

L2586

30-OHM-1.7A

1 2

0402

C2586

4.7UF

20%

4V

X5R

402

1

2

PP1V05_S0_MCP_PLL_CORE



VOLTAGE=1.05V

16

87 mA (A01)

1

2

C2587

0.1UF

20%

10V

CERM

402

L2588

30-OHM-1.7A

1 2

0402

C2588

4.7UF

20%

4V

X5R

402

1

2

3

1

2

C2589

0.1UF

20%

10V

CERM

402

PP1V05_S0_MCP_PLL_NV



VOLTAGE=1.05V

1

2

C2590

0.1UF

20%

10V

CERM

402

21

37 mA (A01)

MCP Standard Decoupling



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

24

OF

97

2 1

D

8 7 6

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

87 84 70 69 55 18 8 7

PP1V8_S0

190 mA (A01, 1.8V)

1

2

C2610

2.2UF

20%

6.3V

CERM

402-LF

C

5

18 17 14 13 12 11

67

10 9 8 7

63 24 22

6

20

PPCPUVTT_S0

95 mA (A01)

C2615

4.7UF

20%

4V

X5R

402

1

2

1

2

C2616

2.2UF

20%

6.3V

CERM

402-LF

90 18

90 18

MCP_HDMI_RSET

MCP_HDMI_VPROBE

NO STUFF

C2620

0.1UF

20%

10V

CERM

402

1

2

84

29

82 81

28 24

80 77 70 69 68

22 21 19 18

63 60

13 8 7 6

59 55 51 49 48 47 45 43

96

39 37

85

PP3V3_S0

16 mA (A01)

1 R2620

1K

1%

1/16W

2

MF-LF

402

90 18

90 18

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

NO STUFF

C2630

0.1UF

20%

10V

CERM

402

1

2

NO STUFF

1 R2630

1K

1%

1/16W

2

MF-LF

402

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

1

L2640

30-OHM-1.7A

2

0402

C2640

4.7UF

20%

6.3V

CERM

603

1

2

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: ???

PP3V3_S0_MCP_VPLL



VOLTAGE=3.3V

1

2

C2641

0.1uF

20%

10V

CERM

402

18

16 mA (A01)

B

4 3 2

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

PP3V3_S0_MCP_DAC



VOLTAGE=3.3V

18

206 mA (A01)

1

R2651

0

5%

1/16W

2

MF-LF

402

1

D

25 18

25 18

25 18

25 18

25 18

90 25 18

90 25 18

90 25 18

NC_MCP_RGB_RED

NC_MCP_RGB_GREEN

NC_MCP_RGB_BLUE

NC_MCP_RGB_HSYNC

NC_MCP_RGB_VSYNC

NC_CRT_IG_R_C_PR

NC_CRT_IG_G_Y_Y

NC_CRT_IG_B_COMP_PB

NC_CRT_IG_HSYNC

NC_CRT_IG_VSYNC

90 25 18

90 25 18

25 18

NC_MCP_RGB_DAC_RSET

25 18

NC_MCP_RGB_DAC_VREF

90 25 18

NC_MCP_TV_DAC_RSET

90 25 18

NC_MCP_TV_DAC_VREF

25 18


25 18


NC_MCP_RGB_RED

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

18 25

NO_TEST=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

18 25 90

NO_TEST=TRUE


MAKE_BASE=TRUE

18 25

NO_TEST=TRUE



18 25

C

B

A

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

8

7 6 5 4 3

MCP Graphics Support

SYNC_MASTER=AMASON_M98_MLB SYNC_DATE=06/18/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

25

OF

97

2 1

D

C

B

A

8

45 44 43 42 40 26 22 21 8 7

69 64 62 61 50 46

PP3V42_G3H

7 6

RTC Power Sources

C2803 1

4.7UF

20%

6.3V

X5R

402

2

C2802 1

4.7UF

20%

6.3V

X5R 2

402

C2801 1

0.1UF

10%

16V

X5R

402

2

5

PP3V42_G3H

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

8

21

IN

RTC_CLK32K_XTALOUT

21

OUT

NO STUFF

R2811

10M

1

5%

1/16W

MF-LF

402

2

RTC_CLK32K_XTALIN

21

IN

21 OUT

NO STUFF

R2816

1

1M

5%

1/16W

MF-LF

402

2

MCP_CLK25M_XTALIN

RTC Crystal

R2810

0

1 2

5%

1/16W

MF-LF

402

RTC_CLK32K_XTALOUT_R

CRITICAL

Y2810

32.768K

7X1.5X1.4-SM

MCP_CLK25M_XTALOUT

MCP 25MHz Crystal

R2815

0

1 2

5%

1/16W

MF-LF

402

MCP_CLK25M_XTALOUT_R

CRITICAL

Y2815

25.0000M

SM-3.2X2.5MM

C2810

12pF

1 2

5%

50V

CERM

402

C2811

12pF

1 2

5%

50V

CERM

402

C2815

12pF

1 2

5%

50V

CERM

402

NC

NC

C2816

12pF

1 2

5%

50V

CERM

402

MCP S0 PWRGD & CPU_VLD

38 37 34

96 87

30

82

24 22

70 69

20 18 8 7

68 64 54 44

PP3V3_S5

1

2

MCPSEQ_SMC

C2850

0.1UF

20%

10V

CERM

402

69 42

IN

63 IN

21

IN

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

MCP_CPUVDD_EN

2

1

5

TC7SZ08AFEAPE

SOT665

A

U2850

Y

B

4

S0_AND_IMVP_PGOOD

MCPSEQ_SMC

3

MCPSEQ_SMC

R2853

0

1 2

5%

1/16W

MF-LF

402

MCPSEQ_MIX

R2852

0

1 2

MCPSEQ_MIX

R2851

0

1 2

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

MCPSEQ_SMC

R2850

0

1 2


5%

1/16W

MF-LF

402

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up.

MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before

CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

MCP_PS_PWRGD

OUT 21

MCP_CPU_VLD

OUT

21

7 6 5

4 3 2 1

91 84 19 IN

LPC_RESET_L

Platform Reset Connections

LPC Reset (Unbuffered)


R2881

33

1 2

5%

1/16W

MF-LF

402

R2883

33

1 2


5%

1/16W

MF-LF

402

DEBUG_RESET_L

SMC_LRESET_L

OUT 44

OUT 42

37 26 17

IN

PCIE_RESET_L

MAKE_BASE=TRUE

19 IN

MEM_VTT_EN_R

91 19

IN

LPC_CLK33M_SMC_R

91 21 IN

PM_CLK32K_SUSCLK_R

PCIE Reset (Unbuffered)

PCIE_RESET_L

OUT

17 26 37

R2890

0

1 2

5%

1/16W

MF-LF

402

GMUX_PCIE_RESET_L

MAKE_BASE=TRUE

GMUX_PCIE_RESET_L

26 84

OUT

26 84

R2893

0

1 2

5%

1/16W

MF-LF

402

R2891

0

1 2 PCA9557D_RESET_L

5%

1/16W

MF-LF

402

BKLT_PLT_RST_L

R2895

1

0

5%

1/16W

MF-LF

402

2

R2894

0

1 2 MINI_RESET_L

5%

1/16W

MF-LF

402

CARDREADER_PLT_RST_L

OUT 27

OUT 86

OUT 31

OUT 32

R2870

33

1 2

5%

1/16W

MF-LF

402

MEM_VTT_EN

OUT 9 65 70


R2825

33

1 2 LPC_CLK33M_SMC

42 91

OUT

1

5%

1/16W

MF-LF

402

R2827

33

2

R2826

33

1

5%

1/16W

MF-LF

402

2 LPC_CLK33M_LPCPLUS

OUT

44 91


LPC_CLK33M_GMUX

5%

1/16W

MF-LF

402


OUT

84


R2829

22

1 2

5%

1/16W

MF-LF

402

PM_CLK32K_SUSCLK

OUT 42 91

D

C

B

42

IN

13 10

IN

Reset Button

PM_SYSRST_L

XDP_DBRESET_L

XDP

R2896

0

1 2

5%

1/16W

MF-LF

402

OMIT

R2897

0

1

5%

1/16W

MF-LF

402

2

SILK_PART=FP SYS RESET

R2899

33

1 2

5%

1/16W

MF-LF

402

10K pull-up to 3.3V S0 inside MCP

PM_SYSRST_DEBOUNCE_L

1

2

NO STUFF

C2899

1UF

10%

10V

X5R

402

OUT

21

4 3

SB Misc



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

26

OF

97

2 1

D

C

B

8 7 6 5 4 3 2

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

VREFMRGN

NO_VREFMRGN

70 52 50 45 32 31 21 8 7

PP3V3_S3

94 45 42 39 27

IN

94 45 42 39 27

BI

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

ADDR=0x98(WR)/0x99(RD)

ADDR=0x30(WR)/0x31(RD)

94 45 42 39 27 IN

94 45 42 39 27

BI

1

2

VREFMRGN

C2900

2.2UF

20%

6.3V

CERM

402-LF

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

MEM A VREF DQ MEM A VREF CA MEM B VREF DQ MEM B VREF CA CPU FSB VREF

DAC channel A B A B C D

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

(per DAC LSB)

FRAME BUFFER VREF

1

2

1

2

VREFMRGN

C2901

0.1UF

20%

10V

CERM

402

VREFMRGN

C2902

0.1UF

20%

10V

CERM

402

6

SCL

7

SDA

9

A0

10

A1

8

U2900

VDD

VREFMRGN

VOUTA

1

MSOP

VREFMRGN_DQ_SODIMM

VOUTB

2 VREFMRGN_CA_SODIMM

GND

3

VOUTC

4

VOUTD

5

VREFMRGN

VREFMRGN_CPUFSB

VREFMRGN_FRAMEBUF

3

A0

4

A1

5

A2

1

SCL

2

SDA

VCC

U2901

PCA9557

QFN

THRM

PAD

P0

P1

P2 9

P3

P4

P5

6

7

10

11

12

P6

P7

13

14

GND

RESET* 15

NC

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

27

27

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_FRAMEBUF_EN

27

27

27

27

NC

PCA9557D_RESET_L

IN

26

1

2

1

2

1

2

VREFMRGN

C2903

0.1UF

20%

10V

CERM

402

VREFMRGN

C2904

0.1UF

20%

10V

CERM

402

VREFMRGN

C2905

0.1UF

20%

10V

CERM

402

A2

A3

C2

C3

A2

A3

C2

C3

V-

B4

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

65 8

PPVTTDDR_S3

10mA max load

B1

V+

U2902

MAX4253

UCSP

VREFMRGN A1

A4

VREFMRGN_DQ_SODIMMA_BUF

27

VREFMRGN_DQ_SODIMMA_EN

R2901

100K

5%

1/16W

MF-LF

402

VREFMRGN

B1

V+

U2902

MAX4253

UCSP

VREFMRGN C1

C4

V-

B4

VREFMRGN_DQ_SODIMMB_BUF

27

VREFMRGN_DQ_SODIMMB_EN

R2902

100K

5%

1/16W

MF-LF

402

VREFMRGN

B1

V+

U2903

MAX4253

UCSP

VREFMRGN A1

A4

V-

B4

VREFMRGN_CA_SODIMMA_BUF

27

VREFMRGN_CA_SODIMMA_EN

R2907

100K

5%

1/16W

MF-LF

402

VREFMRGN

B1

V+

U2903

MAX4253

UCSP

VREFMRGN C1

C4

V-

B4

VREFMRGN_CA_SODIMMB_BUF

27

VREFMRGN_CA_SODIMMB_EN

A2

A3

R2908

100K

5%

1/16W

MF-LF

402

VREFMRGN

B1

V+

U2904

MAX4253

UCSP

VREFMRGN A1

A4

V-

B4

VREFMRGN_FRAMEBUF_BUF

27

VREFMRGN_FRAMEBUF_EN

R2915

100K

5%

1/16W

MF-LF

402

VREFMRGN

C2

C3

B1

V+

U2904

MAX4253

UCSP

VREFMRGN C1

C4

V-

B4

VREFMRGN_CPUFSB_BUF

27

VREFMRGN_CPUFSB_EN

R2913

100K

5%

1/16W

MF-LF

402

VREFMRGN

R2903

200

1 2

1%

1/16W

MF-LF

402

R2904

100

1 2

VREFMRGN

VREFMRGN

PP0V75_S3_MEM_VREFDQ_A

28



1%

1/16W

MF-LF

402

R2905

200

1 2

Place close to J3100.1

VREFMRGN

1%

1/16W

MF-LF

402

R2906

100

1 2

1%

1/16W

MF-LF

402

VREFMRGN

PP0V75_S3_MEM_VREFDQ_B

29




R2909

200

1 2

1%

1/16W

MF-LF

402

R2910

100

1 2

1%

1/16W

MF-LF

402

VREFMRGN

VREFMRGN

PP0V75_S3_MEM_VREFCA_A

28




VREFMRGN R2911

200

1 2

1%

1/16W

MF-LF

402

R2912

100

1 2

VREFMRGN

PP0V75_S3_MEM_VREFCA_B

29



1%

1/16W

MF-LF

402


R2916

49.9

1 2

1%

1/16W

MF-LF

402

R2917

49.9

1 2

1%

1/16W

MF-LF

402

R2914

100

1 2

1%

1/16W

MF-LF

402

VREFMRGN

GPU_FB_A_VREF_DIV

OUT

Place close to U8400, U8450

VREFMRGN

GPU_FB_B_VREF_DIV

OUT

Place close to U8500, U8550

VREFMRGN

CPU_GTLREF

Place close to U1000.AD26

9 74

9 75

OUT 10 88

A

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004

116S0004

116S0004

116S0004

QTY

1

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF

REFERENCE DES

R2903

1 RES,MTL FILM,0,5%,0402,SM,LF



R2905

R2909

R2911

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

NO_VREFMRGN

NO_VREFMRGN

NO_VREFMRGN

NO_VREFMRGN

8

7 6 5 4 3

1

D

C

B

FSB/DDR3/FRAMEBUF Vref Margining



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

27

OF

97

2 1

8

D

Page Notes


- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)


- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA


(NONE)

C

B

85 84 82 81

51 49 48 47

19 18 13

80

45

8 7 6

PP3V3_S0

43 39 37

77 70 69

29 25

68 63

24 22 21

60 59 55

96

A

8

7

69 68 39 29 24 16 12 11 8 7

PP1V8R1V5_S0_FET

70

70 65 30 29 8 7

PP1V8R1V5_S3

7

6

6

5 4 3

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

2

1

2

C3110

0.1UF

20%

10V

CERM

402

1

2

C3111

0.1UF

20%

10V

CERM

402

1

2

C3112

0.1UF

20%

10V

CERM

402

1

2

C3113

0.1UF

20%

10V

CERM

402

1

2

C3114

0.1UF

20%

10V

CERM

402

1

2

C3115

0.1UF

20%

10V

CERM

402

1

2

C3116

0.1UF

20%

10V

CERM

402

1

2

C3117

0.1UF

20%

10V

CERM

402

1

2

C3118

0.1UF

20%

10V

CERM

402

1

2

C3119

0.1UF

20%

10V

CERM

402

1

2

C3120

0.1UF

20%

10V

CERM

402

1

2

C3121

0.1UF

20%

10V

CERM

402

1

2

C3122

0.1UF

20%

10V

CERM

402

1

2

C3123

0.1UF

20%

10V

CERM

402

1

2

C3100

10UF

20%

6.3V

X5R

603

1

2

C3101

10UF

20%

6.3V

X5R

603

1

2

C3140

2.2UF

20%

6.3V

CERM

402-LF

89 15 IN

MEM_A_CKE<0>

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15 IN

89 15

IN

89 15 IN

89 15

IN

89 15 IN

89 15

IN

MEM_A_BA<2>

MEM_A_A<12>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_A<10>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_CS_L<1>

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15

IN

89 15 BI

89 15

BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 IN

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<44>

MEM_A_DQ<41>

MEM_A_DM<5>

MEM_A_DQ<45>

MEM_A_DQ<42>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DM<7>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_SA<0>

MEM_A_SA<1>

1 R3140

10K

2

5%

1/16W

MF-LF

402

1 R3141

10K

2

5%

1/16W

MF-LF

402

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

KEY

CKE0

VDD

NC

BA2

VDD

J3100

F-RT-THB

A12/BC*

A9

VDD

A8

VDD

ODT1

NC

VDD

VREFCA

VSS

DQ36

CK1*

VDD

BA1

RAS*

VDD

S0*

ODT0

DQ37

VSS

DM4

VSS

DQ38

DQ39

VSS

DQ44

DQ45

VSS

DQS5*

DQS5

VSS

CKE1

VDD

A15

A14

VDD

A11

A7

VDD

A6

A4

VDD

A2

A0

VDD

CK1

DQ46

DQ47

VSS

DQ52

DQ53

VSS

DM6

VSS

DQ54

DQ55

VSS

DQ60

DQ61

VSS

DQS7*

DQS7

VSS

DQ62

DQ63

VSS

EVENT*

SDA

SCL

VTT

A5

VDD

A3

A1

VDD

CK0

VDD

A13

S1*

VDD

TEST

VSS

DQ32

CK0*

VDD

A10/AP

BA0

VDD

WE*

CAS*

DQ33

VSS

DQS4*

DQS4

VSS

DQ34

DQ35

VSS

DQ40

DQ41

VSS

DM5

VSS

DQ42

DQ43

VSS

DQ48

DQ49

VSS

DQS6*

DQS6

VSS

DQ50

DQ51

VSS

DQ56

DQ57

VSS

DM7

VSS

DQ58

DQ59

VSS

SA0

VDDSPD

SA1

VTT

87

89

91

93

95

97

99

73

75

77

79

81

83

85

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

185

187

189

191

193

195

173

175

177

179

181

183

197

199

201

203

516-0196

SPD ADDR=0xA0(WR)/0xA1(RD)

MEM_A_CKE<1>

IN 15 89

TP_MEM_A_A<15>

MEM_A_A<14>

IN

IN

9

15 89

MEM_A_A<11>

MEM_A_A<7>

IN

IN

15 89

15 89

MEM_A_A<6>

MEM_A_A<4>

IN

IN

15 89

15 89

MEM_A_A<2>

MEM_A_A<0>

IN

IN

15 89

15 89

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

IN

IN

15 89

15 89

MEM_A_BA<1>

MEM_A_RAS_L

IN

IN

15 89

15 89

MEM_A_CS_L<0>

MEM_A_ODT<0>

IN

IN

15 89

15 89

MEM_A_ODT<1>

IN 15 89

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DM<4>

IN

15 89

MEM_A_DQ<38>

MEM_A_DQ<39>

BI

BI

15 89

15 89

MEM_A_DQ<47>

MEM_A_DQ<40>

BI

BI

15 89

15 89

MEM_A_DQS_N<5>

BI

MEM_A_DQS_P<5>

BI

15 89

15 89

MEM_A_DQ<46>

MEM_A_DQ<43>

BI

BI

15 89

15 89

MEM_A_DQ<48>

MEM_A_DQ<53>

BI

BI

15 89

15 89

MEM_A_DM<6>

BI

BI

15 89

15 89

IN 15 89

MEM_A_DQ<50>

MEM_A_DQ<49>

BI

BI

15 89

15 89

MEM_A_DQ<57>

MEM_A_DQ<56>

BI

BI

15 89

15 89

MEM_A_DQS_N<7>

BI

MEM_A_DQS_P<7>

BI

15 89

15 89

MEM_A_DQ<62>

MEM_A_DQ<63>

BI

BI

15 89

15 89

MEM_EVENT_L

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

OUT 21 29 42

BI

IN

13 21 29 45 91

13 21 29 45 91

27

PP0V75_S3_MEM_VREFDQ_A

1

2

C3130

2.2UF

20%

6.3V

CERM

402-LF

1

2

C3131

0.1UF

20%

10V

CERM

402

89 15 BI

89 15 BI

89 15

IN

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15 BI

89 15 IN

89 15

BI

89 15 BI

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DM<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<9>

MEM_A_DQ<13>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQ<23>

MEM_A_DQ<19>

MEM_A_DQ<24>

MEM_A_DQ<30>

MEM_A_DM<3>

MEM_A_DQ<27>

MEM_A_DQ<25>

25

27

29

31

33

35

37

39

41

43

45

13

15

17

19

21

23

7

9

11

1

3

5

47

49

51

53

55

57

59

61

63

65

67

69

71

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

DQ11

VSS

DQ16

DQ17

VSS

DQS2*

DQS2

VREFDQ

VSS

DQ0

DQ1

CRITICAL

VSS

DQ4

DQ5

VSS

VSS

DM0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1*

DQS1

VSS

DQ10

J3100

DQS0*

DQS0

F-RT-THB

VSS

DQ6

DQ7

VSS

DQ12

DQ13

VSS

DM1

RESET*

VSS

DQ14

DQ22

DQ23

VSS

DQ28

DQ29

VSS

DQS3*

DQS3

VSS

DQ30

DQ31

VSS

DQ15

VSS

DQ20

DQ21

VSS

DM2

VSS

KEY

516-0196

14

16

18

20

22

24

26

28

30

32

2

4

6

8

10

12

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

PP0V75_S3_MEM_VREFCA_A

27

1

2

C3135

2.2UF

20%

6.3V

CERM

402-LF

1

2

C3136

0.1UF

20%

10V

CERM

402


7 8 29 65 70

5 4 3

MEM_A_DQ<4>

MEM_A_DQ<5>

BI

BI

15 89

15 89

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

BI

BI

15 89

15 89

MEM_A_DQ<6>

MEM_A_DQ<7>

BI

BI

15 89

15 89

MEM_A_DQ<8>

MEM_A_DQ<12>

BI

BI

15 89

15 89

MEM_A_DM<1>

MEM_RESET_L

IN

IN

15 89

29 30

MEM_A_DQ<15>

MEM_A_DQ<10>

BI

BI

15 89

15 89

MEM_A_DQ<21>

MEM_A_DQ<20>

BI

BI

15 89

15 89

MEM_A_DM<2>

IN 15 89

MEM_A_DQ<17>

MEM_A_DQ<22>

BI

BI

15 89

15 89

MEM_A_DQ<29>

MEM_A_DQ<28>

BI

BI

15 89

15 89

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

BI

BI

15 89

15 89

MEM_A_DQ<26>

MEM_A_DQ<31>

BI

BI

15 89

15 89

"Factory" (top) slot

1

D

C

B

DDR3 SO-DIMM Connector A



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

28

OF

97

2 1

D

8

Page Notes


- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)


- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA


(NONE)

C

B

60 59 55

21 19 18

51

96

49

85

48

13 8 7 6

PP3V3_S0

47 45

84 82

43 39 37 28 25 24 22

81 80 77 70 69 68 63

A

8

7

69 68 39 28 24 16 12 11 8 7

PP1V8R1V5_S0_FET

70

70 65 30 28 8 7

PP1V8R1V5_S3

6

1

2

C3200

10UF

20%

6.3V

X5R

603

1

2

C3201

10UF

20%

6.3V

X5R

603

7 6

5

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

5

4

4

3

3

2

1

2

C3210

0.1UF

20%

10V

CERM

402

1

2

C3211

0.1UF

20%

10V

CERM

402

1

2

C3212

0.1UF

20%

10V

CERM

402

1

2

C3213

0.1UF

20%

10V

CERM

402

1

2

C3214

0.1UF

20%

10V

CERM

402

1

2

C3215

0.1UF

20%

10V

CERM

402

1

2

C3216

0.1UF

20%

10V

CERM

402

1

2

C3217

0.1UF

20%

10V

CERM

402

1

2

C3218

0.1UF

20%

10V

CERM

402

1

2

C3219

0.1UF

20%

10V

CERM

402

1

2

C3220

0.1UF

20%

10V

CERM

402

1

2

C3221

0.1UF

20%

10V

CERM

402

1

2

C3222

0.1UF

20%

10V

CERM

402

1

2

C3223

0.1UF

20%

10V

CERM

402

1 R3240

10K

2

5%

1/16W

MF-LF

402

1

2

C3240

2.2UF

20%

6.3V

CERM

402-LF

89 15 IN

MEM_B_CKE<0>

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15

IN

89 15 IN

89 15

IN

89 15 IN

89 15

IN

89 15 IN

89 15

IN

MEM_B_BA<2>

MEM_B_A<12>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_A<10>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_CS_L<1>

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15

IN

89 15 BI

89 15

BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 BI

89 15 IN

MEM_B_DQ<32>

MEM_B_DQ<37>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DM<5>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<55>

MEM_B_DQ<49>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DM<7>

MEM_B_DQ<63>

MEM_B_DQ<59>

MEM_B_SA<0>

MEM_B_SA<1>

1 R3241

2

10K

5%

1/16W

MF-LF

402

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

206

208

210

212

CKE0

VDD

NC

BA2

VDD

KEY

J3200

F-RT-BGA3

A12/BC*

A9

VDD

A8

A5

VDD

A3

A1

VDD

CK0

CK0*

VDD

A10/AP

BA0

VDD

WE*

CAS*

VDD

A13

S1*

VDD

TEST

VSS

DQ32

DQ33

VSS

DQS4*

DQS4

VSS

DQ34

DQ35

VSS

DQ40

DQ41

VSS

DM5

VSS

DQ42

DQ43

VSS

DQ48

DQ49

VSS

DQS6*

DQS6

VSS

DQ50

DQ51

VSS

DQ56

DQ57

VSS

DM7

VSS

DQ58

DQ59

VSS

SA0

VDDSPD

DQ63

VSS

EVENT*

SDA

SA1

VTT

SCL

VTT

MTG PIN

MTG PINS

MTG PIN

MTG PIN MTG PIN

MTG PIN

MTG PIN

MTG PIN

MTG PIN

DM6

VSS

DQ54

DQ55

VSS

DQ60

DQ61

VSS

DQS7*

DQS7

VSS

DQ62

VSS

DQS5*

DQS5

VSS

DQ46

DQ47

VSS

DQ52

DQ53

VSS

VDD

ODT1

NC

VDD

VREFCA

VSS

DQ36

DQ37

VSS

DM4

CK1*

VDD

BA1

RAS*

VDD

S0*

ODT0

VSS

DQ38

DQ39

VSS

DQ44

DQ45

CKE1

VDD

A15

A14

VDD

A11

A7

VDD

A6

A4

VDD

A2

A0

VDD

CK1

87

89

91

93

95

97

99

73

75

77

79

81

83

85

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

185

187

189

191

193

195

173

175

177

179

181

183

197

199

201

203

205

207

209

211

516s0704

SPD ADDR=0xA2(WR)/0xA3(RD)

MEM_B_CKE<1>

IN 15 89

TP_MEM_B_A<15>

MEM_B_A<14>

IN

IN

9

15 89

MEM_B_A<11>

MEM_B_A<7>

IN

IN

15 89

15 89

MEM_B_A<6>

MEM_B_A<4>

IN

IN

15 89

15 89

MEM_B_A<2>

MEM_B_A<0>

IN

IN

15 89

15 89

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

IN

IN

15 89

15 89

MEM_B_BA<1>

MEM_B_RAS_L

IN

IN

15 89

15 89

MEM_B_CS_L<0>

MEM_B_ODT<0>

IN

IN

15 89

15 89

MEM_B_ODT<1>

IN 15 89

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_B_DM<4>

IN

15 89

MEM_B_DQ<38>

MEM_B_DQ<39>

BI

BI

15 89

15 89

MEM_B_DQ<44>

MEM_B_DQ<45>

BI

BI

15 89

15 89

MEM_B_DQS_N<5>

BI

MEM_B_DQS_P<5>

BI

15 89

15 89

MEM_B_DQ<47>

MEM_B_DQ<46>

BI

BI

15 89

15 89

MEM_B_DQ<48>

MEM_B_DQ<54>

BI

BI

15 89

15 89

MEM_B_DM<6>

BI

BI

15 89

15 89

IN 15 89

MEM_B_DQ<53>

MEM_B_DQ<50>

BI

BI

15 89

15 89

MEM_B_DQ<60>

MEM_B_DQ<61>

BI

BI

15 89

15 89

MEM_B_DQS_N<7>

BI

MEM_B_DQS_P<7>

BI

15 89

15 89

MEM_B_DQ<58>

MEM_B_DQ<62>

BI

BI

15 89

15 89

MEM_EVENT_L

SMBUS_MCP_0_DATA

OUT 21 28 42

BI

13 21 28 45 91

SMBUS_MCP_0_CLK

IN

13 21 28 45 91

27

PP0V75_S3_MEM_VREFDQ_B

1

2

C3230

2.2UF

20%

6.3V

CERM

402-LF

1

2

C3231

0.1UF

20%

10V

CERM

402

89 15 BI

89 15 BI

89 15

IN

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15

BI

89 15 BI

89 15 BI

89 15 IN

89 15

BI

89 15 BI

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<28>

MEM_B_DQ<24>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQ<15>

MEM_B_DQ<10>

MEM_B_DQ<21>

MEM_B_DQ<17>

MEM_B_DM<2>

MEM_B_DQ<18>

MEM_B_DQ<22>

25

27

29

31

33

35

37

39

41

43

45

13

15

17

19

21

23

7

9

11

1

3

5

47

49

51

53

55

57

59

61

63

65

67

69

71

VREFDQ

VSS

DQ0

DQ1

CRITICAL

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

VSS

DQS2*

DQS2

VSS

DQ18

DQ19

VSS

VSS

DM0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1*

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

J3200

DQS0*

DQS0

F-RT-BGA3

VSS

DQ6

DQ7

VSS

DQ12

DQ13

VSS

DM1

RESET*

VSS

DQ14

DQ15

VSS

DQ20

DQ21

VSS

DM2

VSS

DQ22

DQ23

VSS

DQ28

DQ29

VSS

DQS3*

DQS3

VSS

DQ30

DQ31

VSS

KEY

VSS

DQ4

DQ5

VSS

516s0704

14

16

18

20

22

24

26

28

30

32

2

4

6

8

10

12

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

PP0V75_S3_MEM_VREFCA_B

27

1

2

C3235

2.2UF

20%

6.3V

CERM

402-LF

1

2

C3236

0.1UF

20%

10V

CERM

402


7 8 28 65 70

MEM_B_DQ<4>

MEM_B_DQ<5>

BI

BI

15 89

15 89

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

BI

BI

15 89

15 89

MEM_B_DQ<6>

MEM_B_DQ<7>

BI

BI

15 89

15 89

MEM_B_DQ<29>

MEM_B_DQ<25>

BI

BI

15 89

15 89

MEM_B_DM<3>

MEM_RESET_L

IN

IN

15 89

28 30

MEM_B_DQ<26>

MEM_B_DQ<27>

BI

BI

15 89

15 89

MEM_B_DQ<13>

MEM_B_DQ<12>

BI

BI

15 89

15 89

MEM_B_DM<1>

IN 15 89

MEM_B_DQ<14>

MEM_B_DQ<11>

BI

BI

15 89

15 89

MEM_B_DQ<20>

MEM_B_DQ<16>

BI

BI

15 89

15 89

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

BI

BI

15 89

15 89

MEM_B_DQ<19>

MEM_B_DQ<23>

BI

BI

15 89

15 89

"Expansion" (bottom) slot

1

D

C

B

DDR3 SO-DIMM Connector B



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

29

OF

97

2 1

D

8 7 6 5 4 3 2 1

D

C

DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

16 IN

MCP_MEM_RESET_L

70 65 29 28 8 7

PP1V8R1V5_S3

R3309

0

2 1

5%

1/16W

MF-LF

402

MEM_RESET_L

OUT 28 29

CRITICAL

Q3305

DMB53D0UDW

SOT-363

R3310

1K

1

5%

1/16W

MF-LF

402

2

R3300

10K

1

5%

1/16W

MF-LF

402

2

R3301

20K

1

5%

1/16W

MF-LF

402

2

MEM_RESET_RC_L

1

2

C3300

0.1UF

20%

10V

CERM

402

PP3V3_S5

7 8 18 20 22 24 26 34 37 38 44

54 64 68 69 70 82 87 96

R3305

100K

1

5%

1/16W

MF-LF

402

2

MEM_RESET

3.3V S5 is used because MEM_RESET must be high before 1.5V starts to rise to avoid glitch on MEM_RESET_L.

C

B B

A

8

7 6 5 4 3

DDR3 Support



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

30

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

CRITICAL

J3401

20347-325E-12

F-RT-SM

31

26

27

28

29

30

10

11

12

13

14

15

1

2

3

4

5

6

7

8

9

16

17

18

19

20

21

22

23

24

25

NC

32

518S0610

17

OUT

PCIE_MINI_PRSNT_L

17 OUT

MINI_CLKREQ_L

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

96

90 7

PCIE_MINI_R2D_P

96

90 7

PCIE_MINI_R2D_N

96 7


96 7


OUT

OUT

7 17 90

7 17 90

7

MINI_CLKREQ_Q_L

PCIE_WAKE_L

7

MINI_RESET_CONN_L

7

PP5V_WLAN

OUT 7 17

7

PP5V_S3_BTCAMERA_F

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

CONN_USB2_BT_P

CONN_USB2_BT_N

1

2

C3422

0.1uF

20%

10V

CERM

402

BI

IN

7 42 45 51 94

7 42 45 51 94

3 D Q3401

SSM6N15FEAPE

SOT563

4

S G 5

AP_PWR_EN

IN 21 34

6 D Q3401

SSM6N15FEAPE

SOT563

1

S G 2

5V S3 WLAN FET

Part

Type

Rds(on)

Loading

TPCP8102

P-Channel

14 mOhm @4.5V

0.8 A (EDP)

1000 mA peak

750 mA nominal max

PLACEMENT_NOTE=Place close to J3401.

L3404

FERR-120-OHM-1.5A

2

0402-LF

1

C3421

0.1uF

20%

10V

CERM

402

1

2

53

PP5V_WLAN_F

MIN_LINE_WIDTH=1 mm


VOLTAGE=5V

1

2

C3420

10UF

20%

10V

X5R

805

PLACEMENT_NOTEs:

(C3420 & C3421)

XW3450

SM

1 2 PP5V_WLAN_R

MIN_LINE_WIDTH=1 mm


VOLTAGE=5V

CRITICAL

Q3450

TPCP8102

23V1K-SM

1

2

XW3451

SM

2

XW3452

SM

1

C3450

0.1UF

1

ISNS_AIRPORT_P

ISNS_AIRPORT_N

10%

16V

X5R

402

OUT

OUT

53 96

53 96

2

PP5V_S3

C3451

0.033UF

10%

16V

X5R

402

1

2

P5VWLAN_SS

1 R3451

10K

5%

1/16W

MF-LF

R3450 402

100K

1 2

2

PM_WLAN_EN_L

5%

1/16W

MF-LF

402

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

IN

34

D

AIRPORT

C3431

0.1uF

1 2


PCIE_MINI_R2D_C_P

IN 17 90

C3430

0.1uF

1 2

10%

16V

X5R

402 PCIE_MINI_R2D_C_N


10%

16V

X5R

402

IN 17 90

4

CRITICAL

L3401

90-OHM-100MA

DLP11S

SYM_VER-1

3 PCIE_CLK100M_MINI_P

IN

17 90

1 2 PCIE_CLK100M_MINI_N

PLACE_NEAR=J3401.8,2mm

IN 17 90

MIN_LINE_WIDTH=1 mm


VOLTAGE=5V



VOLTAGE=5V

ALS

4

CRITICAL

L3402

90-OHM

DLP0NS

SYM_VER-1

3

CAMERA

USB_CAMERA_P

BI

7 20 91

BI 7 20 91

1 2 USB_CAMERA_N


4

CRITICAL

L3403

90-OHM

DLP0NS

SYM_VER-1

3

BLUETOOTH

USB_BT_P

BI

7 20 91

1 2 USB_BT_N


BI

7 20 91

275 mA peak

206 mA nominal max

TC7SZ08AFEAPE

SOT665

5

4

3

PP3V3_S3

A

2

B

1

7 8 21 27 31 32 45 50 52 70

U3402

74LVC1G17DRL

SOT-553

WLAN_SMIT_BUF 4

5

3

NC

1

NC

2

R3453

33K

1

5%

1/16W

MF-LF

402

2

WLAN_SMIT_RC

1

2

C3453

1UF

10%

6.3V

CERM

402

R3454

62K

1

5%

1/16W

MF-LF

402

2

R3455

1

1 2

5%

1/16W

MF-LF

402

WLAN_SMIT_DISCHRG

3 D

Q3455

SSM3K15FV

SOD-VESM-HF

2

S G 1

MINI_RESET_L

IN 26

L3406

2 1

FERR-120-OHM-1.5A

0402-LF

PP3V3_S3

7 8 21 27 31 32 45 50 52 70

7

PP3V3_S3_BT_F



VOLTAGE=3.3V


L3405

FERR-120-OHM-1.5A

2 1 PP5V_S3

0402-LF

1

2

C3452

0.1uF

20%

10V

CERM

402

C3462

0.1uF

20%

10V

CERM

402

1

2

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

C

B

A

8

7 6 5 4 3

Right Clutch Connector

SYNC_MASTER=MUXGFX SYNC_DATE=12/08/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

31

OF

97

2 1

D

C

B

A

8

8

7 6 5 4 3 2 1

70 52 50 45 31 27 21 8 7

PP3V3_S3



VOLTAGE=3.3V

R3511

0

1 2

5%

1/16W

MF-LF

402

1

2

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

32

PP3V3_S3_CARDREADER_DVDD

C3500

10UF

20%

6.3V

X5R

603

1

2

C3501

0.1UF

20%

10V

CERM

402

1

2

C3502

0.1UF

20%

10V

CERM

402

1

2


C3503

0.1UF

20%

10V

CERM

402


VOLTAGE=3.3V

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

PP3V3_S3_CARDREADER_AVDD



1

2

C3514

10UF

20%

6.3V

X5R

603

1

2

C3504

0.1UF

20%

10V

CERM

402

1

VOLTAGE=3.3V

C3508

2

0.1UF

20%

10V

CERM

402

1

L3500

0.22UH

0805-1

2

PP1V8_S3_CARDREADER


1

2


VOLTAGE=1.8V

C3506

0.1UF

20%

10V

CERM

402

96 20 9

BI

96 20 9 BI

USB_CARDREADER_N

USB_CARDREADER_P

1

NO STUFF

R3503

1M

2

5%

1/16W

MF-LF

402

CRITICAL

Y3500

12.000M-100PPM

1 2

8X4.5X1.4-SM

C3511

33PF

1 2

C3512

33PF

1 2

5%

50V

CERM

402

5%

50V

CERM

402

CARDREADER_XTAL1

CARDREADER_XTAL2

1

R3506

715

2

1%

1/16W

MF-LF

402

32

32

CARDREADER_GPIO1

CARDREADER_GPIO2

48

47

46

NC

NC

NC

NC

NC

19

20

21

22

13

14

7

8

DM

DP

GPIO1

GPIO2

GPIO3

SK

CS

DO

DI /IPD

X1

X2

U3500

GL137A

LQFP

IPD/

IPD/

IPU/

IPU/

D4

D5

D6

D7

D0

D1

D2

D3

CLK

SD_WP

SD_CMD

PDMOD

SD_CDZ

39

3

41

2

23

40

43

37

29

28

30

32

38

CARDREADER_RREF 10

RREF

CARDREADER_TEST_MOD

17

TESTMOD /IPD

CARDREADER_RESET_L

18

EXTRSTZ* /IPU

IPD/

IPU/ XD_CDZ

XD_CE

XD_WEZ IPD/

IPD/

IPD/

XD_RBZ

XD_WPZ

1

31

42

44

45

IPU/ MS_INS

MS_BS

24

33

1

R3502

0

5%

2

1/16W

MF-LF

402

1

2

NO STUFF

C3513

0.1UF

20%

10V

CERM

402

GND

SD_CLK_R

CARDREADER_PDMOD

NC

NC

NC

NC

NC

NC

NC

17 IN

CARDREADER_RESET

Q3500

SSM6N15FEAPE

SOT563

D 3

5 G S

4

CARDREADER_PLT_RST

D 6 Q3500

SSM6N15FEAPE

SOT563

2 G S

1

26

IN

CARDREADER_PLT_RST_L

32


PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE

1

2

C3507

2.2UF

20%

6.3V

CERM1

603

1

2

C3505

0.1UF

20%

10V

CERM

402

1 R3505

39K

2

5%

1/16W

MF-LF

402

MAX CURRENT = 250MA

PP3V3_SW_SD_PWR



VOLTAGE=3.3V

93 7

SD_CLK

93 7

SD_CMD

93 7

SD_D<0>

93 7

SD_D<1>

93 7

SD_D<2>

93 7

SD_D<3>

93 7

SD_D<4>

93 7

SD_D<5>

93 7

SD_D<6>

93 7

SD_D<7>

7

SD_CD_L

7

SD_WP

OMIT

J3500

SD-CARD-K19

F-RT-TH

1

10

11

7

8

9

3

6

5

2

12

13

14

15

16

4

VSS

VSS

CLK

CMD

DAT0

DAT1

DAT2

CD/DAT3

DAT4

DAT5

DAT6

DAT7

CARD_DETECT_SW

CARD_DETECT_GND

WRITE_PROTECT_SW

VDD

17

18

19

20

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

1

R3504

0

2

5%

1/16W

MF-LF

402

1

2

NO STUFF

C3515

10PF

5%

50V

CERM

402-1

PDMOD: POWER DOWN MODES

NC = DISABLE (DEFAULT)

10K LOW = POWER SAVING MODE ENABLE

10K HIGH = REMOTE WAKE UP ENABLE

32


1

R3512

2

10K

5%

1/16W

MF-LF

402

PART#

516-0225

QTY DESCRIPTION

1 CONN,SD CARD READER,OPTN B

REFERENCE DESIGNATOR(S) CRITICAL

J3500 CRITICAL

BOM OPTION

(PDMOD)

1

NO STUFF

R3513

10K

5%

1/16W

MF-LF

2

402

TABLE_5_HEAD

TABLE_5_ITEM

D

C

B

32

CARDREADER_GPIO1

1

R3507

10K

2

5%

1/16W

MF-LF

402

1

NO STUFF

R3508

10K

2

5%

1/16W

MF-LF

402

CARDREADER_GPIO2

32

1

NO STUFF

R3509

10K

5%

1/16W

MF-LF

2

402

1

R3510

10K

5%

1/16W

MF-LF

2

402

7 6 5 4 3







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

32

OF

97

2

SECUREDIGITAL CARD READER

SYNC_MASTER=VEMURI SYNC_DATE=01/30/2009


A

1

8 7 6 5 4 3 2 1

D

C

B

PP3V3_ENET_PHY

34 24 18 8 7

(43mA typ - 1000base-T)

(19mA typ - Energy Detect)

WF: Marvell numbers, update for Realtek

1

CRITICAL

L3705

FERR-120-OHM-1.5A

0402-LF

2

PP3V3_ENET_PHYAVDD



VOLTAGE=3.3V

1

2

C3700

0.1UF

10%

16V

X5R

402

1

2

C3701

0.1UF

10%

16V

X5R

402

1

2

C3702

0.1UF

10%

16V

X5R

402

1

2

C3705

0.1UF

10%

16V

X5R

402

1

2

C3706

0.1UF

10%

16V

X5R

402

92 18

IN

Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.

IN

GND

ENET_CLK125M_TXCLK

R3796

1

22

2

5%

1/16W

402

MF-LF

PLACE R3796 CLOSE TO U1400, PIN D24

ENET_CLK125M_TXCLK_R

92 18

IN

92 18

IN

92 18 IN

92 18 IN

ENET_TXD<0>

ENET_TXD<1>

ENET_TXD<2>

ENET_TXD<3>

R3720

10K

1

5%

1/16W

MF-LF

402

2

92 18 IN

ENET_TX_CTRL

NO STUFF

1 R3725

4.7K

2

5%

1/16W

MF-LF

402

39

ENSWREG

22

TXC

23

24

25

26

TXD[0]

TXD[1]

TXD[2]

TXD[3]

27

TXCTL

92 18 IN

ENET_RESET_L

ENET_RESET_L is not asserted when WOL is active.

Hence, RC (R3725 and C3725) are made NOSTUFF.

R3724

0

1 2

5%

1/16W

MF-LF

402

1

NO STUFF 2

C3725

0.1UF

20%

10V

CERM

402

R3730 1

2.49K

1%

1/16W

MF-LF

402

2

92 18 IN

92 18 BI

ENET_MDC

ENET_MDIO

RTL8211_PHYRST_L

RTL8211_RSET

9

RTL8211_CLK125

92 34 IN

RTL8211_CLK25M_CKXTAL1

TP_RTL8211_CKXTAL2

30

31

MDC

MDIO

29

PHYRSTB*

46

RSET

32

CLK125

42

43

CKXTAL1

CKXTAL2

C3714

0.1UF

10%

16V

X5R

402

1

2

C3710

0.1UF

10%

16V

X5R

402

1

2

C3715

0.1UF

10%

16V

X5R

402

1

2

C3711

0.1UF

10%

16V

X5R

402

1

2

CRITICAL

L3715

FERR-120-OHM-1.5A

0402-LF

1

PP1V2R1V05_ENET

7 8 18 24 34 37

(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)

WF: Marvell numbers, update for Realtek

C3716

0.1UF

10%

16V

X5R

402

1

2

PP1V05_ENET_PHYAVDD



VOLTAGE=1.05V

2

R3750 1

4.7K

5%

1/16W

MF-LF

402

2

1 R3751

2

4.7K

5%

1/16W

MF-LF

402

R3752 1

4.7K

5%

1/16W

MF-LF

402

2

TP_PP3V3_ENET_PHY_VDDREG

9

If internal switcher is used, must place 1x 22uF &

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

NC_RTL8211_REGOUT

9

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

If internal switcher is not used, VDDREG and REGOUT can float.

OMIT

U3700

RTL8211CLGR

TQFP

RGMII/MII

REGOUT

48

RXC

19

RXD[0]

RXD[1]/TXDLY

RXD[2]/AN0

RXD[3]/AN1

14

16

17

18

RXCTL

13

92

ENET_CLK125M_RXCLK_R

92

92

92

92

ENET_RXD_R<0>

ENET_RXD_R<1>

ENET_RXD_R<2>

ENET_RXD_R<3>

ENET_RXCTL_R

R3790

R3791

R3792

R3793

R3794

R3795

MANAGEMENT

RESET

MEDIA DEPENDENT

REFERENCE

MDI+[0]

MDI-[0]

1

2

MDI+[1]

MDI-[1]

MDI+[2]

MDI-[2]

MDI+[3]

MDI-[3]

4

5

8

9

11

12

CLOCK

LED

GND

ENET_MDI_P<0>

ENET_MDI_N<0>

ENET_MDI_P<1>

ENET_MDI_N<1>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_MDI_P<3>

ENET_MDI_N<3>

BI

BI

35 92

35 92

BI

BI

35 92

35 92

BI

BI

35 92

35 92

BI

BI

35 92

35 92

LED0/PHYAD0

LED1/PHYAD1

LED2/RXDLY

34

35

38

C3790

10PF

5%

50V

CERM

402

1

2

Reserved for EMI per RealTek request.

RTL8211_PHYAD0

RTL8211_PHYAD1

RTL8211_RXDLY

R3755 1

4.7K

5%

1/16W

MF-LF

402

2

R3756 1

4.7K

5%

1/16W

MF-LF

402

2

1 R3757

4.7K

2

5%

1/16W

MF-LF

402

22

22

22

22

22

22

1

1

1

1

1

1

2

5% 1/16W MF-LF 402

ENET_CLK125M_RXCLK

OUT

18 92

2

2

2

2

5%

5%

5%

5%

1/16W

1/16W

1/16W

1/16W

MF-LF

MF-LF

MF-LF

MF-LF

402

402

402

402

ENET_RXD<0>

ENET_RXD<1>

ENET_RXD<2>

ENET_RXD<3>

2

5% 1/16W MF-LF 402

ENET_RX_CTRL

OUT

OUT

OUT

OUT

18 92

18 92

18 92

18 92

OUT 18 92

D

C

B

A

Configuration Settings:

PHYAD = 01 (PHY Address 00001)

AN[1:0] = 11 (Full auto-negotiation)

RXDLY = 0 (RXCLK transitions with data)

TXDLY = 0 (No TXCLK Delay)

8

7 6 5 4 3

Ethernet PHY (RTL8211CL)

SYNC_MASTER=SUMA_M98_MLB SYNC_DATE=07/01/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

33

OF

97

2 1

D

C

B

8 7 6

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

D 6

PM_WLAN_EN_L

31

OUT

Pull-up is with power FET.

Q3805

SSM6N15FEAPE

SOT563

2 G

31 21 IN

AP_PWR_EN

Q3805

SSM6N15FEAPE

SOT563

S

1

AC_OR_S0_L

D 3 6 D Q3801

SSM6N15FEAPE

SOT563

43 42 37 21

IN

SMC_ADAPTER_EN

5 G S

4 1

S G 2

84 82 69 42 37 21 7

IN

PM_SLP_S3_L

5 4 3 2

37 34

96 87

30

82

26 24 22 20

70 69 68 64

18 8 7

54 44 38

PP3V3_S5

3.3V ENET FET

@ 2.5V Vgs:

Rds(on) = 90mOhm max

I(max) = 1.7A (85C)

CRITICAL

Q3810

NTR4101P

SOT-23-HF

R3800

1

10K

5%

1/16W

MF-LF

402

2

Q3801

SSM6N15FEAPE

SOT563

D 3

P3V3ENET_EN_L

R3810

100K

1 2

5%

1/16W

MF-LF

402

2 S D 3

1

2

C3811

0.033UF

10%

16V

X5R

402

P3V3ENET_SS

1

G

C3810

0.01UF

2 1

10%

16V

CERM

402

34 21 9

IN

MOBILE:

PM_SLP_RMGT_L

5 G S

4

Recommend aliasing PM_SLP_RMGT_L and

=P3V3ENET_EN. Nets separated on

ARB for alternate power options.

PP3V3_ENET_PHY

7 8 18 24 33

1.05V ENET FET

68 24 22 8 7

PP1V2R1V05_S5

37

96

34 30

87 82

26

70

24

69

22 20

68 64

18

54

8 7

44 38

PP3V3_S5

R3840

1

100K

2

5%

1/16W

MF-LF

402

C3840

0.1UF

20%

10V

CERM

402

P1V05ENET_SS

Q3841

SSM6N15FEAPE

SOT563

1

2

D 6

R3842 1

69.8K

1%

1/16W

MF-LF

402

2

Q3841

SSM6N15FEAPE

SOT563

D 3

P1V05ENET_EN_L

R3841

10K

1 2

1%

1/16W

MF-LF

402

2 G S

1

1 G

P1V05ENET_EN_L_RC

1.8V Vgs

3

D

CRITICAL

Q3840

SI2312BDS

SOT23

S

2

PP1V2R1V05_ENET

7 8 18 24 33 37

1

2

C3841

0.01UF

10%

16V

CERM

402

PM_SLP_RMGT_L

34 21 9 IN

Non-ARB:

5 G S

4

Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on

ARB for alternate power options.

A

8

7 6

RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

92 18 IN

MCP_CLK25M_BUF0_R

R3895

22

1 2 RTL8211_CLK25M_CKXTAL1

5%

1/16W

MF-LF

402


OUT 33 92

5 4 3

1

D

C

B

Ethernet & AirPort Support

SYNC_MASTER=SUMA_M98_MLB SYNC_DATE=07/01/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

34

OF

97

2 1

D

8

Page Notes


(NONE)


(NONE)


(NONE)

7 6 5 4 3

C

B

Place one of 0.1uf cap close to each centertap pin of transformer

ENETCONN_CTAP

1

2

C3900 1

0.1UF

10%

16V

X5R

402

2

C3902 1

0.1UF

10%

16V

X5R

402

2

C3904 1

0.1UF

10%

16V

X5R

402

2

C3906

0.1UF

10%

16V

X5R

402

92 33 BI

92 33

BI

92 33

BI

92 33

BI

92 33 BI

92 33

BI

92 33 BI

92 33 BI

CRITICAL

T3900

SM

96

12 ENETCONN_P<0> ENET_MDI_P<0>

ENET_MDI_N<0>

1

2

96

11 ENETCONN_N<0>

3 10 ENET_CTAP0

TX

4

TLA-6T213HF

9 ENET_CTAP1

5 8

96

ENETCONN_N<1> ENET_MDI_N<1>

ENET_MDI_P<1> 6 7

96

ENETCONN_P<1>

RX

CRITICAL

T3901

SM

96

12 ENETCONN_N<2> ENET_MDI_N<2>

ENET_MDI_P<2>

1

2

96

11 ENETCONN_P<2>

3 10 ENET_CTAP2

TX

4

TLA-6T213HF

9 ENET_CTAP3

5 8

96

ENETCONN_N<3> ENET_MDI_N<3>

ENET_MDI_P<3> 6 7

96

ENETCONN_P<3>

RX

Transformers should be mirrored on opposite sides of the board

R3900 1

75

5%

1/16W

MF-LF

402

2

R3901 1

75

5%

1/16W

MF-LF

402

2

1

2

CRITICAL

C3910

10PF

5%

50V

CERM

402-1

2

10PF

5%

50V

CERM

402-1

1

CRITICAL

2

1

C3911

10PF

5%

50V

CERM

402-1

CRITICAL

C3920

2

1

C3921

10PF

5%

50V

CERM

402-1

CRITICAL

C3930

2

10PF

5%

50V

CERM

402-1

1

CRITICAL

1

2

CRITICAL

C3940

10PF

5%

50V

CERM

402-1

CRITICAL

1

2

C3931

10PF

5%

50V

CERM

402-1

1

2

CRITICAL

C3941

10PF

5%

50V

CERM

402-1

1 R3902

75

2

5%

1/16W

MF-LF

402

1 R3903

75

2

5%

1/16W

MF-LF

402

CRITICAL

C3908

ENET_BOB_SMITH_CAP 1



1000PF

2

10%

2KV

CERM

1206

CRITICAL

J3900

RJ45-M97-3

F-RT-TH

9

10

1

2

3

4

5

6

7

8

11

12

514-0636

2

A

8

7 6 5 4 3

1

D

C

B

Ethernet Connector



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

35

OF

97

2 1

D

C

B

A

8 7 6 5 4 3 2 1

PART#

114S0557

QTY DESCRIPTION

1 RES,0.475 ohm,1%,1/16W,0402


R4100 CRITICAL

BOM OPTION

37 8

PP1V0_FW

135 mA

TABLE_5_HEAD

TABLE_5_ITEM

OMIT

R4100

0.2

1 2

1%

1/16W

MF-LF

402

PP1V0_FW_R



VOLTAGE=1.0V

L4110

120-OHM-0.3A-EMI

1 2

0402-LF

PP1V0_FW_FWPHY_AVDD



VOLTAGE=1.0V

25 mA PCIe SerDes

1

2

C4110

1UF

10%

6.3V

CERM

402

1

2

C4111

1UF

10%

6.3V

CERM

402

C4120 1

1UF

10%

6.3V

CERM

402

2

7 mA I/O

C4121 1

1UF

10%

6.3V

CERM

402

2

C4122 1

1UF

10%

6.3V

CERM

402

2

C4123 1

1UF

10%

6.3V

CERM

402

2

C4124 1

1UF

10%

6.3V

CERM

402

2

C4130 1

1UF

10%

6.3V

CERM

402

2

114 mA FireWire PHY

C4131

1UF

10%

6.3V

CERM

402

1

2

C4132 1

1UF

10%

6.3V

CERM

402

2

PP3V3_FW_FWPHY_VDDA



VOLTAGE=3.3V

L4130

120-OHM-0.3A-EMI

1 2

0402-LF

17 mA PCIe SerDes

C4135

1UF

10%

6.3V

CERM

402

1

2

C4136 1

1UF

10%

6.3V

CERM

402

2

PP3V3_FW_FWPHY_VP25



VOLTAGE=3.3V

L4135

120-OHM-0.3A-EMI

1 2

0402-LF

PP3V3_FW_FWPHY

138 mA

8 36 37 38

D

C4150

22PF

1 2

5%

50V

CERM

402 NC

C4151

22PF

NC

1 2

5%

50V

CERM

402

8

110 mA Digital Core

1

2

C4100

1UF

10%

6.3V

CERM

402

1

2

C4101

1UF

10%

6.3V

CERM

402

1

2

C4102

1UF

10%

6.3V

CERM

402

1 C4103

1UF

10%

6.3V

2 CERM

402

1

2

C4104

1UF

10%

6.3V

CERM

402

1

2

C4105

1UF

10%

6.3V

CERM

402

1

2

C4106

1UF

10%

6.3V

CERM

402

0 mA VReg PWR

C4141 1

0.1UF

20%

10V

CERM

402

2

1

2

C4140

1UF

10%

6.3V

CERM

402

38

PPVP_FW_CPS

FW_CLK24P576M_XO

CRITICAL

Y4150

24.576MHZ

SM-3.2X2.5MM

R4150

412

1 2

1%

1/16W

MF-LF

402

R4160 1

200K

1%

1/16W

MF-LF

402

2

R4161 1

2.94K

1%

1/16W

MF-LF

402

2

R4162 1

470K

5%

1/16W

MF-LF

402

2

1 R4170

191

1%

1/16W

MF-LF

2

402

1

2

C4162

0.33UF

10%

6.3V

CERM-X5R

402

38

IN

38 IN

38 IN

93 38

BI

93 38 BI

93 38 BI

93 38

BI

38 BI

38 BI

93 38

BI

93 38 BI

93 38 BI

93 38

BI

38 BI

38 BI

38

BI

38 37 BI

38 BI

FWPHY_DS0

FWPHY_DS1

FWPHY_DS2

NC_FW0_TPAN

NC_FW0_TPAP

FW_PORT1_TPA_N

FW_PORT1_TPA_P

NC_FW2_TPAN

NC_FW2_TPAP

NC_FW0_TPBN

NC_FW0_TPBP

FW_PORT1_TPB_N

FW_PORT1_TPB_P

NC_FW2_TPBN

NC_FW2_TPBP

NC_FW0_TPBIAS

FW_P1_TPBIAS

NC_FW2_TPBIAS

FW643_R0

FW643_TPCPS

TP_FW643_NAND_TREE

FW643_REXT

FW_CLK24P576M_XO_R

FW_CLK24P576M_XI

TP_FW643_SE

TP_FW643_SM

TP_FW643_MODE_A

TP_FW643_CE

TP_FW643_FW620_L

TP_FW643_JASI_EN

TP_FW643_AVREG

TP_FW643_VBUF

FW643_PU_RST_L

TP_FW643_OCR10_CTL

NC

NC

NC

B13

A13

A11

ATBUSB

ATBUSH

ATBUSN

F12

E12

E13

DS0

DS1

DS2

(IPD) NT-19

(IPD) NT-20

(IPD) NT-21

B9

A9

B6

A6

B4

A4

B8

A8

B5

A5

B3

A3

TPA0N

TPA0P

TPA1N

TPA1P

TPA2N

TPA2P

TPB0N

TPB0P

TPB1N

TPB1P

TPB2N

TPB2P

B7

C3

A2

TPBIAS0

TPBIAS1

TPBIAS2

B11

B10

R0

TPCPS

VDD10 VDD33

CRITICAL

1394 PHY

OMIT

U4100

FW643

NC

K1

L8

F13

G13

NAND_TREE

REXT

XO

XI NT-9

NT-OUT

NOTE: NT-xx notes show

NAND tree order.

M13

N13

J2

SE

SM

L13

D12

D1

(IPD)

(IPD)

MODE_A

CE

(IPD) NT-18

(IPD)

FW620* (IPU)

A10

H13

K13

JASI_EN (IPD) NT-11

AVREG

VBUF

FW_RESET* (IPU) NT-8

J12

J13

OCR_CTL_V10

OCR_CTL_V12 (Reserved)

MISCELLANEOUS

VSS

BGA

VDDH

PCI EXPRESS PHY

TEST CONTROLLER

NT-4 (IPU) TCK

NT-3 (IPU) TDI

(IPU) TDO

NT-1 (IPU) TMS

M4

N2

M1

M3

NT-2 (IPU) TRST* N1

POWER MANAGEMENT

NT-12 (IPD)

NT-10 (IPD)

FIXME!!! - TYPO IN SYMBOL REGCTL

WAKE*

REGCLT

VAUX_DETECT

VAUX_DISABLE

NT-13 (OD) CLKREQN

C2

D13

E1

D2

L2

SCIF

SERIAL EEPROM

CONTROLLER

CHIP RESET

VP VP25

VREG_PWR

PCIE_RXD0N

PCIE_RXD0P

PCIE_TXD0N

PCIE_TXD0P

N8

N7

N5

N6

REFCLKN

REFCLKP

N9

N10

NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN

NT-17

NT-15 (IPD)

SCIFDOUT

SCIFMC

G2

G1

H1

F2

NT-7

NT-6

SCL

SDA

N12

M11

NT-5 PERST*

N4

VREG_VSS

90

PCIE_FW_R2D_N

90

PCIE_FW_R2D_P

90

PCIE_FW_D2R_C_N

90

PCIE_FW_D2R_C_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P

TP_FW643_TCK

TP_FW643_TDI

TP_FW643_TDO

TP_FW643_TMS

FW643_TRST_L

FW643_WAKE_L

FW643_REGCTL

FW643_VAUX_DETECT

TP_FW643_VAUX_ENABLE

FW_CLKREQ_PHY_L

OUT 9 37

OUT 37

TP_FW643_SCIFCLK

TP_FW643_SCIFDAIN

TP_FW643_SCIFDOUT

TP_FW643_SCIFMC

FW643_SCL

TP_FW643_SDA

FW_RESET_L

1 R4163

10K

5%

1/16W

MF-LF

2

402

IN

37

IN

IN

17 90

17 90

C4170

0.1UF

C4171

0.1UF

PLACEMENT_NOTE=Place C4170 close to U1400


2 16V

X5R 402

2 16V

X5R 402

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

IN

17 90

IN

17 90

C4175

0.1UF

2 16V PCIE_FW_D2R_N

X5R 402

C4176

0.1UF

2 16V

X5R 402

PCIE_FW_D2R_P



OUT 17 90

OUT 17 90

PP3V3_FW_FWPHY

8 36 37 38

FW643_LDO

R4165 1

10K

5%

1/16W

MF-LF

402

2

1 R4166

10K

5%

1/16W

MF-LF

2

402

1

R4164

10K

5%

1/16W

MF-LF

2

402

7 6 5 4 3

C

B

FireWire LLC/PHY (FW643)

SYNC_MASTER=SENSOR SYNC_DATE=08/14/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

4.12.0

APPLE INC.

SCALE

NONE

SHT

36

OF

97

2 1

D

C

8

Page Notes


- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPVP_FW_SUMNODE (power passthru summation node)


(NONE)

7 6

81

28

80 77

25 24

70 69 68 63 60 59

22 21 19 18 13 8 7 6

PP3V3_S0

55 51 49 47 45 43 39

96 85

37 29

84 82

5

3.3V FW FET

@ 2.5V Vgs:

Rds(on) = 90mOhm max

I(max) = 1.7A (85C)

CRITICAL

Q4291

NTR4101P

SOT-23-HF

4

PP3V3_FW_FWPHY


38 37 36 8

PP3V3_FW_FWPHY

R4277 1

10K

5%

1/16W

MF-LF

402

2

36 9

FW643_WAKE_L

R4290 1

10K

5%

1/16W

MF-LF

402

2

Q4290

SSM6N15FEAPE

SOT563

D 3

P3V3FW_EN_L R4291

100K

1 2

5%

1/16W

MF-LF

402

1

2

C4290

0.033UF

10%

16V

X5R

402

P3V3FW_SS

FW_PLUG_DET_L

9 19 37

CRITICAL

6

D

2 G

S

1

1 R4276

2

100K

5%

1/16W

MF-LF

402

FW_WAKE 5

1

2

NOSTUFF

C4276

0.1UF

10%

16V

X5R

402

4

3

CRITICAL

Q4276

DMB53D0UV

SOT-563

Q4276

DMB53D0UV

SOT-563

96

26

87

24

82 70 69 68

22 20 18 8 7

PP3V3_S5

64 54 44 38 37 34 30

37 19 IN

FW_PWR_EN

38 36 8

PP3V3_FW_FWPHY

R4295 1

10K

5%

1/16W

MF-LF

402

2

Q4293

SSM6N15FEAPE

SOT563

D 3

P1V05_FW_EN_L

5 G S

4

1.05V FW FET

37 34 33 24 18 8 7

PP1V2R1V05_ENET

1

R4297

220K

2

5%

1/16W

MF-LF

402

C4296

0.1UF

20%

10V

CERM

402

1

2

P1V05FW_SS 1 G

3

D

S

CRITICAL

Q4295

SI2312BDS

SOT23

Q4293

SSM6N15FEAPE

SOT563

D 6 2

PP1V0_FW

2 G S

1

R4296

100K

1 2

5%

1/16W

MF-LF

402

P1V05_FW_EN_L_RC

1

2

NOSTUFF

C4295

0.068UF

10%

10V

CERM

402

8 36 37

2 S D 3

1

G

C4291

0.01UF

2 1

10%

16V

CERM

402

Q4264

SSM6N15FEAPE

SOT563

5 G

37 19

FW_PWR_EN

D 3

S

4

37 36

IN

FW_CLKREQ_PHY_L

8 36 37 38

PCIE_FW_PRSNT_L

OUT

MAKE_BASE=TRUE

9 17

Q4264

SSM6N15FEAPE

SOT563

2 G

D 6

37

36

FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

3

FW_CLKREQ_L

OUT 17

S

1

81 80

28 25

70 69 68

24 22 21 19

63 60 59

13 8 7 6

PP3V3_S0

55 51 49 48 47 45 43 39 37 29

96 85 84 82

37 36 8

PP1V0_FW

C4281

1UF

10%

6.3V

CERM

402

1

2

P1V0_FW_RC

CRITICAL

6

D

2 G

FireWire Port Power Switch

S

1

2

R4280

10K

1 2

1%

1/16W

MF-LF

402

5

1 R4281

100K

5%

1/16W

2

MF-LF

402

4

3 CRITICAL

Q4299

DMB53D0UV

SOT-563

P1V0_RESET_GATE

Q4299

DMB53D0UV

SOT-563

1

R4283

10K

1 2

5%

1/16W

MF-LF

402

PCIE_RESET_L

IN

17 26

FW_RESET_L

PP1V05_FW PGOOD/FW_RESET_L

OUT

36

D

C

5 G S

4

37 19

FW_PWR_EN

B

A

96 87 82

54

22

44

20

38 37

18 8 7

PP3V3_S5

34 30 26 24

70 69 68 64 PP2V4_FW_LATEVG

R4211 1

10K

5%

1/16W

MF-LF

402

2

8

C4211

100pF

5%

50V

CERM

402

1

2

79 67 66 65 64 62 61 46 8 7

PPBUS_G3H

86 83

NOSTUFF

C4263

1UF

10%

10V

X5R

402-1

1

2

LATEVG_RETRY_RC

Late-VG Event Detection

NOSTUFF

R4263

1

100

1%

1/16W

MF-LF

402

2

R4265

10K

2 1

5%

1/16W

MF-LF

402

LATEVG_FAULT_EVENT_PNP

LATEVG_FAULT_EVENT

1 R4212

2

10K

1%

1/16W

MF-LF

402

FWLATEGV_3V_REF

P2V4_FWLATEVG_RC

1 R4213

2

80.6K

1%

1/16W

MF-LF

402

7

4

3

V+

2

1

2

C4210

0.1UF

20%

10V

CERM

402

U4210

LMC7211

SM-HF

1 LATEVG_EVENT

V-

5

R4210

200K

1 2

1%

1/16W

MF-LF

402

CRITICAL

Q4262

DMB54D0UV

SOT-563

FWLATEVG Hysteresis:

3.08V when port power is on

2.91V when late Vg event and port power is off

6

Q4261

SSM6N15FEAPE

SOT563

42 34 21

43

IN

84 82 69 42 34 21 7 IN

SMC_ADAPTER_EN

PM_SLP_S3_L

2 G

Enables port power when machine is running or on AC.

5

D 6

CRITICAL

Q4260

NDS9407

SOI-HF

3

2

1

6

5

8

7

1 R4260

2

470K

5%

1/16W

MF-LF

402

C4260

0.1UF

10%

25V

X5R

402

FWPWR_EN_L_DIV

1

2

1 R4261

2

330K

5%

1/16W

MF-LF

402

FWPWR_EN_L

4

37 34 24 18 8 7

PP1V2R1V05_ENET

Q4261

SSM6N15FEAPE

SOT563

D 3

PPBUS_FW_FWPWRSW_F



VOLTAGE=12.6V

MINISMDC110H24

1 R4275

2

1K

5%

1/16W

MF-LF

402

CRITICAL

1

F4260

1.1A-24V

2 PPBUS_FW_FWPWRSW_D



VOLTAGE=12.6V

1 R4271

2

56K

5%

1/16W

MF-LF

402

FW_PLUG_DET

FW_PWR_EN_L

2

1 R4270

330K

5%

1/16W

MF-LF

402

FW_DET_MIRROR

S

1

5 G S

4 CRITICAL

Q4270

BC847CDXV6TXG

SOT563

3

4

FW_P1_TPBIAS_R

5 2

FW_DET_EMIT

6

CRITICAL

Q4270

BC847CDXV6TXG

SOT563

1

37 19

IN

FW_PWR_EN

CRITICAL

6

D

2 G

Q4275

DMB53D0UV

SOT-563

2

1 R4272

1K

5%

1/16W

MF-LF

402

1 R4273

2

12K

5%

1/16W

MF-LF

402

CRITICAL

D4260

SM

1 2

CRS08-1.5A-30V

1

2

C4270

0.1UF

10%

16V

X5R

402

5

PPVP_FW

PP3V3_S0

4

1 R4274

100K

5%

1/16W

2

MF-LF

402

FW_PLUG_DET_L

3 CRITICAL

Q4275

DMB53D0UV

SOT-563

38 36 IN

FW_P1_TPBIAS

S

1

8 38

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

OUT 9 19 37

B

FireWire Port Power

SYNC_MASTER=YUN_K19_MLB SYNC_DATE=12/22/2008


A







APPLE INC.

SIZE

D

DRAWING NUMBER

SCALE

NONE

051-7892

SHT

37

OF

REV.

A.0.0

97

4 3 2 1

8

Page Notes


- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

D

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_EMI_R


(NONE)

NOTE: This page is expected to contain

the necessary aliases to map the

FireWire TPA/TPB pairs to their

appropriate connectors and/or to

properly terminate unused signals.


(NONE)

NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is

assumed that FireWire PHY page will

provide the appropriate constraints

to apply to entire TPA/TPB XNets.

1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)

C

B

7

FireWire PHY Config Straps

Configures PHY for:

- 1-port Portable Power Class (0)

- Port "1" Bilingual (1394B)

6 5

38 37 36 8

PP3V3_FW_FWPHY

4

R4382 1

10K

1%

1/16W

MF-LF

402

2

R4380 1

10K

1%

1/16W

MF-LF

402

2

38 36

FWPHY_DS0

MAKE_BASE=TRUE

38 36

FWPHY_DS2

MAKE_BASE=TRUE

38 36

FWPHY_DS1

MAKE_BASE=TRUE

R4381

1

10K

1%

1/16W

MF-LF

402

2

FWPHY_DS0

FWPHY_DS2

FWPHY_DS1

36 38

36 38

36 38

3 2

Termination

Place close to FireWire PHY

37 36

FW_P1_TPBIAS

TI PHYs require 1uF even though

FW spec calls out 0.33uF

1

2

C4360

0.33UF

10%

6.3V

CERM-X5R

402

SIGNAL_MODEL=EMPTY

1

SIGNAL_MODEL=EMPTY

R4360

2

56.2

1%

1/16W

MF-LF

402

R4361

1

56.2

1%

1/16W

MF-LF

402

2

93 38 36

FW_PORT1_TPA_P

93 38 36

FW_PORT1_TPA_N

93 38 36

FW_PORT1_TPB_P

93 38 36

FW_PORT1_TPB_N

SIGNAL_MODEL=EMPTY

1

SIGNAL_MODEL=EMPTY

R4362

2

56.2

1%

1/16W

MF-LF

402

R4363 1

56.2

1%

1/16W

MF-LF

402

2

FW_PORT1_TPB_C

38 37 8

PPVP_FW

R4311 1

470K

5%

1/16W

MF-LF

402

2

CPS_EN_L_DIV

R4312 1

330K

5%

1/16W

MF-LF

402

2 CPS_EN_L

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

36 38 93

36 38 93

36 38 93

36 38 93

38 37 36 8

PP3V3_FW_FWPHY 2 G

1

2

C4364

220pF

5%

25V

CERM

402

R4364 1

4.99K

1%

1/16W

MF-LF

402

2

38 36

38 36

93 38 36

93 38 36

38 36

38 36

NC_FW0_TPBIAS

NC_FW2_TPBIAS

NC_FW0_TPAN

NC_FW0_TPAP

NC_FW2_TPAN

NC_FW2_TPAP

93 38 36

93 38 36

38 36

38 36

NC_FW0_TPBN

NC_FW0_TPBP

NC_FW2_TPBN

NC_FW2_TPBP

93 38 36

FW_PORT1_TPA_N

93 38 36

FW_PORT1_TPA_P

CRITICAL

DP4311

BAV99DW-X-G

SOT-363

2

6

1

C4313

0.01uF

10%

50V

X7R

402

1

2

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

36 38

36 38

36 38 93

36 38 93

36 38

36 38

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW2_TPBN

MAKE_BASE=TRUE

NC_FW2_TPBP

MAKE_BASE=TRUE

36 38 93

36 38 93

36 38

36 38

S

1

6

D

Cable Power

38 36

PPVP_FW_CPS

MAKE_BASE=TRUE



VOLTAGE=12.6V

PPVP_FW_CPS

36 38

38 37 8

PPVP_FW

"Snapback" & "Late VG" Protection

38 37

PP2V4_FW_LATEVG CRITICAL

DP4310

BAV99DW-X-G

SOT-363

5

C4310

0.01uF

10%

50V

X7R

402

1

2

C4311

0.01uF

CRITICAL

10%

50V

X7R

402

DP4310

BAV99DW-X-G

SOT-363

2

1

2

6

4

3

1

Q4300

BSS8402DW

SOT-363

(SYM-VER1)

93 38 36

FW_PORT1_TPB_N

93 38 36

FW_PORT1_TPB_P

C4312

0.01uF

10%

50V

X7R

402

1

2

CRITICAL

L4310

FERR-250-OHM

1 2

Note: Trace PPVP_FW_PORT1 must handle up to 5A

PPVP_FW_PORT1_F



VOLTAGE=33V

1

2

SM

C4314

0.01UF

10%

50V

X7R

402

(FW_PORT1_BREF)

(GND_FW_PORT1_VG)

FW_PORT1_AREF

CRITICAL

DP4311

BAV99DW-X-G

SOT-363

5

4

3

C4319

0.1uF

10%

50V

X7R

603-1

1

2

1 R4319

1M

5%

1/16W

2

MF-LF

402

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

AREF needs to be isolated from all local grounds per 1394b spec

When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue)

BREF should be hard-connected to logic ground for speed signaling and connection

PORT 1

BILINGUAL

8

NC

7

6

3

5

4

1

9

2

CRITICAL

J4310

1394B-M97

F-RT-TH

TPBTPB(R)

TPB-

TPB+

TPA-

TPB<R>

VP

VG

TPA+

TPA<R>

TPA(R)

TPA+

OUTPUT

INPUT

10

11

12

13

CHASSIS

GND

514S0605

1

A

8

Late-VG Protection Power

37 34

96

30 26

87 82

24 22

70 69

20

68

18 8

64 54

7

PP3V3_S5

44

PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin

R4390 should be 390 Ohms max for a 3.3V rail

R4390

332

1 2

1%

1/16W

MF-LF

402

3

1

PP2V4_FW_LATEVG



VOLTAGE=2.4V

37 38

ESD and late-VG rail

CRITICAL for snap-back diodes

D4390

(Common to all ports)

MMBZ5227BLT1H

SOT23

7 6 5 4 3







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

38

OF

97

2

FireWire Ports

D

C

B



A

1

8 7 6 5 4 3 2 1

D

C

ODD Power Control

70 67 66 63 51 49 44 39 8 7

PP5V_S0

85 83

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.

81 80 77

28 25 24

55 51

70

22

49

69

21

48

68

19

63

18

47 45

60 59

13

43

8

39

7

37

6

29

96 85 84 82

PP3V3_S0

R4597 1

100K

5%

1/16W

MF-LF

402

2

ODD_PWR_EN

R4596

Q4596

SSM6N15FEAPE

SOT563

1

100K

5%

1/16W

MF-LF

402

2

D 6

ODD_PWR_EN_LS5V_L

2 G

Q4596

SSM6N15FEAPE

SOT563

D 3

S

1

R4595

100K

1 2

5%

1/16W

MF-LF

402

1

2

C4595

0.068UF

10%

10V

CERM

402

ODD_PWR_SS

CRITICAL

Q4590

TPCP8102

23V1K-SM

C4596

0.01UF

1

10%

16V

CERM

402

2

PP5V_SW_ODD_R



VOLTAGE=5V

21

IN

ODD_PWR_EN_L

5 G S

4

CRITICAL

J4500

54722-0164

F-ST-SM

1 2

9

11

13

15

3

5

7

4

6

8

10

12

14

16

516S0616

53 7

PP5V_SW_ODD



VOLTAGE=5V

SATA ODD Port

FL4520

90-OHM-100MA

DLP11S

CRITICAL

3 4

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

96

SATA_ODD_R2D_UF_P 1 2

C4521

SATA_ODD_R2D_C_P

10% 16V CERM 402

0.01UF

2

C4520

2 1

96

SATA_ODD_R2D_UF_N 1 SATA_ODD_R2D_C_N

10% 16V CERM 402 0.01UF

PLACEMENT_NOTE=Place FL4520 close to J4500

90 7

SATA_ODD_R2D_P

90 7

SATA_ODD_R2D_N

SATA_ODD_D2R_C_N

SATA_ODD_D2R_C_P

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

C4526

1

0.01UF

2

96 7

SATA_ODD_D2R_UF_N

10% 16V CERM 402

C4525

1

0.01UF

2

96 7

SATA_ODD_D2R_UF_P

10% 16V CERM 402

FL4525

90-OHM-100MA

DLP11S

SYM_VER-1

4

1 2

IN

20 90

IN

20 90

SATA_ODD_D2R_N

OUT 20 90

SATA_ODD_D2R_P

OUT 20 90

PLACEMENT_NOTE=Place FL4525 close to J4500

XW4504

SM

1 2

1

2

XW4503

SM

XW4505

SM

1 2

ISNS_ODD_P

ISNS_ODD_N

OUT 53 96

OUT 53 96

D

C

81

28

80

25

77 70

24 22

69

21

68 63

19 18

60 59

13 8 7 6

55 51 49 48 47 45 43

96

39

85

37 29

84 82

PP3V3_S0

R4590 1

33K

5%

1/16W

MF-LF

402

2

42 7

OUT

SMC_ODD_DETECT

Indicates disc presence

B B

A

L4502

FERR-220-OHM

68 29 28 24 16 12 11 8 7

70 69

PP1V8R1V5_S0_FET

1

2

1

0402

2 PP1V5_S0_HDD_FLT

VOLTAGE=1.5V



C4503

1UF

10%

6.3V

CERM

402


8

64 55 53 51 43 41 40 31 9 8 7

PP5V_S3

79 70 65

94 45 42 27

IN

94 45 42 27

BI

402

2

R4532

10

1

1/16W

5%

MF-LF

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

7

PP5V_S3_IR_R

1

2

C4532

0.1UF

10%

16V

X7R-CERM

402

516S0687

7

21

19

17

15

13

11

9

7

5

3

1

F-ST-SM

54722-0224

J4501

22

20

18

16

14

12

10

8

6

4

2

6

1

2

C4501

0.1UF

20%

10V

CERM

402

CRITICAL

L4500

FERR-70-OHM-4A

1

2



VOLTAGE=5V

7

PP5V_S0_HDD_FLT 1 2

0603

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

CRITICAL

FL4501

90-OHM-100MA

DLP11S

SYM_VER-1

90 7

SATA_HDD_R2D_P

90 7

SATA_HDD_R2D_N

3 4

C4502

0.1UF

20%

10V

CERM

402



PP5V_S0_HDD_R



VOLTAGE=5V

SATA HDD Port

PLACEMENT_NOTE=Place C4510 close to MCP79

PLACEMENT_NOTE=Place C4511 next to C4510

2 1

96

SATA_HDD_R2D_UF_P

96

SATA_HDD_R2D_UF_N

C4510

1

0.01UF

C4511

1

0.01UF

2 SATA_HDD_R2D_C_P

10% 16V CERM 402

2 SATA_HDD_R2D_C_N

10% 16V CERM 402

90 7

SATA_HDD_D2R_C_N

90 7

SATA_HDD_D2R_C_P

PLACEMENT_NOTE=Place FL4501 close to J4501 FL4502

90-OHM-100MA

DLP11S

CRITICAL

4 3

C4515

0.01UF

C4516

0.01UF

1

1

2

10% 16V

96

SATA_HDD_D2R_UF_N

CERM 402

SATA_HDD_D2R_N

2

10% 16V

96

SATA_HDD_D2R_UF_P

CERM 402

1 2 SATA_HDD_D2R_P

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

OUT

7 41

PLACEMENT_NOTE=Place C4515 next to C4516

7

IR_RX_OUT

SYS_LED_ANODE_R

1

2

C4531

0.001UF

10%

50V

CERM

402

2

402

R4531

4.7

1

5%

MF-LF

1/16W

PLACEMENT_NOTE=Place C4516 close to J4501

SYS_LED_ANODE

43

IN

IN

OUT

OUT

20 90

1

20 90

20

90

20 90

XW4500

SM

1 2

2

XW4501

SM

1

2

XW4502

SM

SATA Connectors

SYNC_MASTER=PWRSQNC






SIZE

D

PP5V_S0

ISNS_HDD_P

ISNS_HDD_N

DRAWING NUMBER

051-7892

OUT

OUT


7 8 39 44 49 51 63 66 67 70

83 85

53 96

53 96

SYNC_DATE=12/04/2008


REV.

A.0.0

A

APPLE INC.

SCALE SHT OF

39 97

NONE

5 4 3 2 1

8 7 6 5 4 3 2 1

D

D

C

64 55 53 51 43 41 39 31 9

79

8 7

70 65

PP5V_S3

70 69 43 42 21 7

PM_SLP_S4_L

1 R4690

5.1K

2

5%

1/16W

MF-LF

402

C4692

0.47UF

10%

10V

X5R

402

1

2

Port Power Switch

USB_PWR_EN

20

OUT

USB_EXTA_OC_L

20 OUT

USB_EXTB_OC_L

C4690

10UF

20%

6.3V

X5R

603

1

2

1

2

C4691

0.1UF

20%

10V

CERM

402

CRITICAL

Q4690

2

TPS2064DGN

7

IN OUT1

MSOP

8

OC1*

3 6

EN1 OUT2

5

OC2*

4

EN2

GND

1

TPAD

9

C4695

10UF

20%

6.3V

X5R

603

1

2

PP5V_S3_RTUSB_A_ILIM



VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM



VOLTAGE=5V

CRITICAL

1

2

C4696

100UF

20%

6.3V

POLY-TANT

CASE-B2-SM

C4617

10UF

20%

6.3V

X5R

603

1

2

CRITICAL

1

2

C4616

100UF

20%

6.3V

POLY-TANT

CASE-B2-SM

B

A

USB/SMC Debug Mux

SMC_DEBUG_YES

69 64 62

42 26 22 21 8 7

61 50 46 45 44 43

PP3V42_G3H

SIGNAL_MODEL=USB_MUX

44 43 42

44 43 42

IN

OUT

SMC_DEBUG_YES

SMC_RX_L

C4650

0.1UF

20%

10V

CERM

402

SMC_TX_L

1

2

91 20

BI

91 20

BI

USB_EXTA_P

USB_EXTA_N

VCC

5

4

7

6

M+ Y+

MU4650 Y-

PI3USB102ZLE

D+

TQFN

CRITICAL

D-

1

2

8 OE* SEL 10

GND

SMC_DEBUG_NO

R4651

0

1 2

5%

1/16W

MF-LF

402

SMC_DEBUG_NO

R4652

0

1 2

5%

1/16W

MF-LF

402

8

7

1 R4650

10K

2

5%

1/16W

MF-LF

402

USB_DEBUGPRT_EN_L

SEL=0 Choose SMC

SEL=1 Choose USB

IN 42

6 5

Left USB Port A

CRITICAL

L4605

FERR-220-OHM-2.5A

1 2

0603

PP5V_S3_RTUSB_A_F



VOLTAGE=5V

C4605

0.01uF

20%

16V

CERM

402

1

2

CRITICAL

L4600

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

96

USB2_LT1_N

CRITICAL

J4600

USB

F-RT-TH-M97-4

5

6

96

USB2_EXTA_MUXED_N

96

USB2_EXTA_MUXED_P 1 2

96

USB2_LT1_P

1

2

3

4

91 20 BI

91 20 BI

2 5 3 4

6 VBUS

1 GND

7

8

514-0606

D4600

RCLAMP0502N

SLP1210N6

USB_EXTB_N

USB_EXTB_P

CRITICAL

CRITICAL

L4615

FERR-220-OHM-2.5A

We can add protection to 5V if we want, but leaving NC for now

Place L4600 and L4605 at connector pin

1 2 PP5V_S3_RTUSB_B_F



VOLTAGE=5V

1

2

C4615

0.01uF

20%

16V

CERM

402

0603

CRITICAL

J4610

USB

F-RT-TH-M97-4

5

CRITICAL

L4610

90-OHM-100MA

DLP11S

SYM_VER-1

6

1

4

96

3

96

USB_LT2_N

USB_LT2_P

2

3

4

1 2

2 5 3 4

7

8

6 VBUS

1

GND

D4610

RCLAMP0502N

SLP1210N6

CRITICAL

4

Left USB Port B

3

C

B

External USB Connectors



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

40

OF

97

2 1

D

C

8 7 6 5 4

IR SUPPORT

64 55 53 51 43 40

PP5V_S3

39 31 9

79

8 7

70 65

91 20

BI

91 20 BI

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

1

2

1

2

C4801

0.1UF

10%

16V

X7R-CERM

402

C4803

1UF

10%

10V

X5R

402-1

VCC

8

9

10

20

21

22

NC

23

24

12

13

15

U4800

CY7C63803-LQXC

QFN

P1.0/D+

P1.1/D-

16

P1.3/SSEL

17

19

P1.4/SCLK

18

P1.5/SMOSI

P1.6/SMISO

P0.0

7

P0.1

6

INT0/P0.2

5

INT1/P0.3

4

INT2/P0.4

3

TIO0/P0.5

2

TIO1/P0.6

1

CRITICAL

OMIT

P/N 338S0633

THRML

PAD VSS

IR_RX_OUT_RC

R4800

100

1 2

5%

1/16W

MF-LF

402

1

2

C4804

0.001UF

10%

50V

CERM

402

IR_RX_OUT

IN 7 39

3 2 1

D

C

B B

A

8

7 6 5 4 3

SYNC_MASTER=PWRSQNC

Front Flex Support

SYNC_DATE=12/04/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

41

OF

97

2 1

8 7

NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,

those designated as inputs require pull-ups.

6 5 4 3 2 1

D

C

43

OUT

43 OUT

69 26 IN

69

IN

NC_EXCARD_PWR_EN

TP_SMC_RSTGATE_L

ALL_SYS_PWRGD

RSMRST_PWRGD

NC

21 OUT

63

OUT

21

OUT

PM_RSMRST_L

IMVP_VR_ON

PM_PWRBTN_L

43 OUT

NC_ESTARLDO_EN

91 84 44 19

BI

91 84 44 19 BI

91 84 44 19

BI

91 84 44 19

BI

91 84 44 19 IN

26

91 26

IN

IN

44 19 BI

NC

NC

NC

43

TP_SMC_P24

46 43

SMC_BMON_MUX_SEL

NC

NC

LPC_AD<0>

LPC_AD<1>

LPC_AD<2>

LPC_AD<3>

LPC_FRAME_L

SMC_LRESET_L

LPC_CLK33M_SMC

LPC_SERIRQ

94 45 39 27 BI

52

OUT

77 OUT

51

OUT

NC

43

TP_SMC_P41

SMBUS_SMC_MGMT_SDA (OC)

SMS_PWRDN

NC

SMC_GFX_THROTTLE_L

NC

SMC_SYS_KBDLED

44 43 42 40 OUT

44 43 42 40 IN

94 78 53 48 45

BI

SMC_TX_L

SMC_RX_L

SMBUS_SMC_0_S0_SCL (OC)

B12

A13

A12

B13

D11

C13

C12

D10

P10

P11

P12

P13

P14

P15

P16

P17

D13

E11

D12

F11

E13

E12

F13

E10

P20

P21

P22

P23

P24

P25

P26

P27

A9

D9

C8

B7

A8

D8

D7

D6

P30

P31

P32

P33

P34

P35

P36

P37

D4

A5

B4

A1

C2

B2

C1

C3

P40

P41

P42

P43

P44

P45

P46

P47

G2

F3

E4

P50

P51

P52

U4900

H8S2117

LGA-HF

(1 OF 3)

OMIT

B

(DEBUG_SW_1)

(DEBUG_SW_2)

26 OUT

40 OUT

29 28 21

BI

61 BI

21

OUT

43

SMC_PA0

SMC_PA1

43

PM_SYSRST_L

USB_DEBUGPRT_EN_L

MEM_EVENT_L

SMC_PA5

43

SYS_ONEWIRE

PM_BATLOW_L

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

A

43

77

IN

IN

NC

21 OUT

39 7

IN

SMC_RUNTIME_SCI_L

SMC_ODD_DETECT

43 IN

43 21

SMC_EXCARD_CP

SMC_EXCARD_OC_L

SMC_GFX_OVERTEMP_L

NC

49

OUT

49 OUT

43 OUT

43

OUT

49

IN

49 IN

43

43

IN

IN

SMC_FAN_0_CTL

SMC_FAN_1_CTL

NC_SMC_FAN_2_CTL

NC_SMC_FAN_3_CTL

SMC_FAN_0_TACH

SMC_FAN_1_TACH

NC_SMC_FAN_2_TACH

NC_SMC_FAN_3_TACH

52 IN

52

52

IN

IN

47 43 IN

47 43

47 43

46 43

IN

IN

IN

46 43

IN

SMS_X_AXIS

SMS_Y_AXIS

SMS_Z_AXIS

SMC_GPU_1V8_ISENSE

SMC_MCP_CORE_ISENSE

SMC_MCP_DDR_ISENSE

SMC_MCP_VSENSE

SMC_CPU_HI_ISENSE

SMC_PB3:

SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

N3

N1

M3

M2

N2

L1

K3

L2

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

B8

C9

B9

A10

C10

B10

C11

A11

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

G11

G13

F12

H13

G10

G12

H11

J13

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

M10

N9

K10

L8

M9

N8

K9

L7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

U4900

H8S2117

LGA-HF

(2 OF 3)

OMIT

8

7 6

P90

P91

P92

P93

P94

P95

P96

P97

P80

P81

P82

P83

P84

P85

P86

J4

G3

H2

G1

H4

G4

F4

F1

N10

M11

L10

N11

N12

M13

N13

L12

A7

B6

C7

D5

A6

B5

C6

P70

P71

P72

P73

P74

P75

P76

P77

P60

P61

P62

P63

P64

P65

P66

P67

L13

K12

K11

J12

K13

J10

J11

H12

43 7

PP3V3_S5_AVREF_SMC

46 45 44 43 40 26 22

69 64

21

62

8 7

61 50

PP3V42_G3H

C4902

22UF

20%

6.3V

CERM

805

1

2

1

2

C4903

0.1UF

20%

10V

CERM

402

1

2

C4904

0.1UF

20%

10V

CERM

402

1

2

C4905

0.1UF

20%

10V

CERM

402

SMC_PM_G2_EN

NC

NC

NC

SMC_ADAPTER_EN

NC

SMC_PROCHOT_3_3_L

SMC_BIL_BUTTON_L

SMC_CPU_ISENSE

SMC_CPU_VSENSE

SMC_GPU_ISENSE

SMC_GPU_VSENSE

SMC_DCIN_ISENSE

SMC_PBUS_VSENSE

SMC_BATT_ISENSE

SMC_CPU_FSB_ISENSE

SMC_WAKE_SCI_L

NC

(OC)

PM_CLKRUN_L

LPC_PWRDWN_L

SMC_TX_L

SMC_RX_L

SMBUS_SMC_MGMT_SCL

SMC_ONOFF_L

SMC_BC_ACOK

SMC_BS_ALRT_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S4_L

PM_CLK32K_SUSCLK

(OC) SMBUS_SMC_0_S0_SDA

OUT

7 64 69

OUT

21 34 37 43

IN

IN

43

7 43 61

IN

IN

IN

IN

IN

IN

IN

IN

46

46

47

46

46

46

46

43 47

OUT

21

OUT

IN

OUT

19 44

19 44

40 42 43 44

IN

BI

40 42 43 44

27 39 45 94

R4999

1

4.7

5%

1/16W

MF-LF

402

2 PP3V3_S5_SMC_AVCC



VOLTAGE=3.3V

C4920

0.1UF

20%

10V

CERM

402

1

2

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

44 43

IN

SMC_RESET_L

43

43

SMC_XTAL

SMC_EXTAL

IN

IN

IN

IN

43 50

43 61 62

43

7 21 34 37 69 82 84

IN

IN

IN

BI

7 21 40 42 43 69 70

7 21 40 42 43 69 70

NOTE: P94 and P95 are shorted, P95 could be spare.

26 91

45 48 53 78 94

1

2

C4906

0.1UF

20%

10V

CERM

402

AVCC

D3 RES*

A3

A2

XTAL

EXTAL

VCC VCL AVREF

U4900

H8S2117

LGA-HF

NC

(3 OF 3)

OMIT MD1

MD2

VSS

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

SMC_VCL

E5

NC

D1

H1

NMI E3

ETRST

AVSS

H3

L9

XW4900

SM

2 1

C4907

0.47UF

10%

6.3V

CERM-X5R

402

1

2

1 R4902

10K

5%

1/16W

2

MF-LF

402

R4909 1

10K

5%

1/16W

MF-LF

402

2

SMC_KBC_MDE

1 R4998

10K

2

5%

1/16W

MF-LF

402

GND_SMC_AVSS

43 46 47

1 R4901

10K

2

5%

1/16W

MF-LF

402

SMC_MD1

SMC_NMI

IN 44

IN

44

SMC_TRST_L

NO STUFF

1 R4903

0

2

5%

1/16W

MF-LF

402

IN

44

PE0

PE1

PE2

PE3

PE4

PF0

K1

J3

K2

J1

K4

K5

PF1

PF2

PF3

PF4

PF5

PF6

PF7

N5

M6

L5

M5

N4

L4

M4

PH0

PH1

PH2

PH3

PH4

PH5

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

E2

F2

J2

A4

B3

C4

M8

N7

K8

K7

K6

N6

M7

L6

SMC_CASE_OPEN

SMC_TCK

SMC_TDI

SMC_TDO

SMC_TMS

NC

SMC_SYS_LED

SMC_LID

NC

NC

SMC_MCP_SAFE_MODE

NC

NC

IN

IN

IN

OUT

IN

43

43 44

43 44

43 44

43 44

OUT

IN

43

43 50 61

OUT

9

NC

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

SMS_INT_L

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMC_PROCHOT

SMC_THRMTRIP

SMC_PH2

NC_ALS_GAIN

43

IN

BI

43

7 45 61 62 94

7 45 61 62 94

BI

BI

BI

7 31 45 51 94

7 31 45 51 94

45 48 94

BI

BI

45 48 94

OUT

OUT

43

43

OUT 43

NC

NC

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

If SMS interrupt is not used, pull up to SMC rail.

5 4 3







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

42

OF

97

2

SMC



1

D

C

B

A

D

C

B

8

45 44 43 42 40

69

26 22

64 62

21

61

8 7

50 46

PP3V42_G3H

PART NUMBER ALTERNATE FOR

PART NUMBER

BOM OPTION

353S1381 353S1912

1

2

C5020

0.47UF

10%

6.3V

CERM-X5R

402

REF DES

ALL

7

45 44 43 42 40 26

69 64

22

62

21

61

8 7

50 46

PP3V42_G3H

50

SMC_TPAD_RST_L

50 43 42

SMC_ONOFF_L

1

2

SMC AVREF Supply

1

CRITICAL

IN

VR5020

REF3333

SOT23-3

OUT

GND

3

2

C5025

10uF

20%

6.3V

X5R

603

1

2

PP3V3_S5_AVREF_SMC



VOLTAGE=3.3V

7 42

1

2

C5026

0.01UF

10%

16V

CERM

402

COMMENTS:

TABLE_ALT_HEAD

GND_SMC_AVSS



VOLTAGE=0V

TABLE_ALT_ITEM

Intersil ISL60002-33

42 46 47

6

SMC Reset "Button" / Brownout Detect

45 44 43 42 40 26

69 64

22

62

21

61

8 7

50 46

PP3V42_G3H

SILK_PART=SMC_RST

C5000

0.1uF

20%

10V

CERM

402

1

2

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5%

1/10W

2

MF-LF

603

C5001 1

0.01UF

10%

16V

CERM 2

402

NC

U5000

NCP303LSN

SOT23-5-HF

5

4

CD

NC

OUT 1

IN

2

GND

3

CRITICAL

1

R5000

1K

5%

1/16W

2

MF-LF

402

SMC_RESET_L

OUT

Q5032

SSM6N15FEAPE

SOT563

D 3

42 44

5 G

02

5

U5001

SN74LVC1G02

SOT553-5

4 SMC_TPAD_RST

3

S

4

5

43 42

NC_SMC_FAN_2_CTL

43 42

NC_SMC_FAN_2_TACH

43 42

NC_SMC_FAN_3_CTL

43 42

NC_SMC_FAN_3_TACH

43 42

NC_ESTARLDO_EN

4

NC_SMC_FAN_2_CTL


NC_SMC_FAN_2_TACH


NC_SMC_FAN_3_CTL


NC_SMC_FAN_3_TACH


42 43

42 43

42 43

42 43

NC_ESTARLDO_EN


42 43

3 2

SMC FSB to 3.3V Level Shifting

82 81 80 77 70 69 68 63 60 59

28 25 24

55 51

22 21

49 48

19 18

47 45

13 8 7 6

43 39 37 29

96 85 84

PP3V3_S0

1 R5061

100K

2

5%

1/16W

MF-LF

402

CPU_PROCHOT_BUF

62 61 43 42

46 43 42

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_MCP_VSENSE

46 43 42

SMC_CPU_HI_ISENSE

47 43 42

SMC_MCP_CORE_ISENSE

47 43 42

SMC_MCP_DDR_ISENSE

47 43 42

SMC_CPU_FSB_ISENSE

47 43 42

SMC_GPU_1V8_ISENSE

43 42

NC_EXCARD_PWR_EN

43 42

TP_SMC_P24

46 43 42

SMC_BMON_MUX_SEL

43 42

TP_SMC_P41

43 42

NC_ALS_GAIN

43 42 21

SMC_IG_THROTTLE_L

43 42

TP_SMC_RSTGATE_L

42

OUT

SMC_EXCARD_OC_L

SMC_BC_ACOK

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

MAKE_BASE=TRUE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

NC_EXCARD_PWR_EN


TP_SMC_P24

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

42 43

42 43 61 62

42 43 46

42 43 47

42 43 47

42 43 47

42 43 47

42 43

42 43

42 43 46

42 43

42 43

21 42 43

TO CPU

88 63 14 10

42 43 46

BI

88 14 10

OUT

CPU_PROCHOT_L

PM_THRMTRIP_L

1

S

3 D

4

S

6 D

R5062

1

3.3K

2 CPU_PROCHOT_L_R

5%

1/16W

MF-LF

402

Q5059

SSM6N15FEAPE

SOT563

5

G 2

SMC_PROCHOT

Q5059

SSM6N15FEAPE

SOT563

G 5

SMC_THRMTRIP

IN 42

IN

42

R5095

0

1 2

5%

1/16W

MF-LF

402

EXCARD_OC_L

IN

20

42

42

SMC_PA0

SMC_PA1

43 42

SMS_INT_L

MAKE_BASE=TRUE

SMS_INT_L

42 43

50 43 42

61 50 42

42

44 42 40

44 42 40

SMC_ONOFF_L

SMC_LID

SMC_PH2

SMC_TX_L

SMC_RX_L

42

SMC_XTAL

42

SMC_EXTAL

SMC Crystal Circuit

C5010

15pF

1 2

5%

50V

CERM

402

R5010

0

1 2 SMC_XTAL_R

5%

1/16W

MF-LF

402

CRITICAL

Y5010

20.00MHZ

5X3.2-SM

1

2

C5011

15pF

1

5%

50V

CERM

402

2

SILK_PART=PWR_BTN

Debug Power "Button"

SMC_ONOFF_L

OMIT

1

R5015

0

5%

1/10W

2

MF-LF

603

OUT 42 43 50

Place R5015,R5001 on bottom side

3

4

Q5060

DMB53D0UV

SOT-563

44 42

44 42

44 42

44 42

61 42 7

62 61 43 42

43 42

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

SMC_BIL_BUTTON_L

SMC_BC_ACOK

SMS_INT_L

R5070

R5071

R5072

R5073

R5074

R5077

R5078

R5079

R5080

R5081

R5087

R5093

2 G

S

1

1

6

D

1 R5060

2

10K

5%

1/16W

MF-LF

402

TO SMC

SMC_PROCHOT_3_3_L

OUT 42

Q5060

DMB53D0UV

SOT-563

45 44 43 42 40

69

26 22

64 62

21

61

8 7

50 46

PP3V42_G3H

R5091

R5092

100K

100K

1

1

10K

100K

10K

10K

100K

1

1

1

1

1

10K

10K

10K

10K

10K

470K

10K

1

1

1

1

1

1

1

2

2

5%

5%

1/16W

1/16W

MF-LF 402

MF-LF 402

2

2

2

2

2

5% 1/16W

5% 1/16W

5%

5%

1/16W

1/16W

5% 1/16W

MF-LF 402

MF-LF 402

MF-LF 402

MF-LF 402

MF-LF 402

2

2

2

2

2

2

2

5% 1/16W

5% 1/16W

5% 1/16W

5% 1/16W

MF-LF 402

MF-LF 402

MF-LF 402

MF-LF 402

5% 1/16W

5% 1/16W

5% 1/16W

MF-LF 402

MF-LF 402

MF-LF 402

D

C

B

System (Sleep) LED Circuit

64 55 53 51 41 40 39 31 9 8 7

79 70 65

PP5V_S3

R5031 1

523

1%

1/16W

MF-LF

402

2

1 R5030

20

2

1%

1/16W

MF-LF

402

SYS_LED_ILIM

SYS_LED_L_VDIV

42

42 37 34 21

42

SMC_BS_ALRT_L

SMC_ADAPTER_EN

SMC_CASE_OPEN

42

SMC_EXCARD_CP

70 69 43 42 40 21 7

70 69 43 42 40 21 7

PM_SLP_S4_L

PM_SLP_S4_L

R5076

R5085

R5086

100K

10K

10K

1

1

1

R5088

10K

1

R5090

100K 1

2

2

2

5% 1/16W

5% 1/16W

MF-LF 402

MF-LF 402

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

42

SMC_PA5

82 81 80 77 70 69 68 63 60 59

28 25 24 22 21

55 51 49 48

19 18 13 8

47 45 43 39

7 6

37 29

96 85 84

PP3V3_S0

R5089

10K 1 2

5% 1/16W MF-LF 402

A

8

R5032 1

1.47K

1%

1/16W

MF-LF

402

2

SYS_LED_L

42

IN

SMC_SYS_LED

7

Q1

S

1

6

D

G

2

5

B

Q2

C

3

4

E

Q5030

DMB54D0UV

SOT-563

SYS_LED_ANODE

OUT

39

6 5 4 3

SMC Support



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

43

OF

97

2 1

8 7 6 5 4 3

D

Alternate SPI ROM Support

LPC+SPI Connector

CRITICAL

LPCPLUS

J5100

55909-0374

M-ST-SM

31 32

45 44 43 42 40 26 22 21 8 7

69 64 62 61 50 46

PP3V42_G3H

83 70 67 66 63 51 49 39 8 7

85

PP5V_S0

91 84 42 19 BI

91 84 42 19 BI

LPC_AD<0>

LPC_AD<1>

LPC_CLK33M_LPCPLUS

LPC_AD<2>

LPC_AD<3>

44 IN

44 OUT

91 84 42 19

IN

42 19 OUT

43 42 OUT

26

IN

43 42

OUT

42 IN

42

OUT

IN

SPI_ALT_MOSI

SPI_ALT_MISO

LPC_FRAME_L

PM_CLKRUN_L

SMC_TMS

DEBUG_RESET_L

SMC_TDO

SMC_TRST_L

SMC_MD1

SMC_TX_L

11

13

7

9

15

17

19

1

3

5

21

23

25

27

29

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

SPIROM_USE_MLB

SPI_ALT_CLK

SPI_ALT_CS_L

LPC_SERIRQ

LPC_PWRDWN_L

SMC_TDI

SMC_TCK

SMC_RESET_L

SMC_NMI

SMC_RX_L

LPCPLUS_GPIO

IN

BI

BI

26 91

19 42 84 91

19 42 84 91

OUT

IN

21 44

44

44

IN

BI

IN

19 42

19 42

42 43

OUT

OUT

OUT

42 43

42 43

42

OUT

OUT

OUT

40 42 43

18

33 34

C

91 44 21

IN

37 34

96 87

30

82

26 24

70 69

22

68

20

64

18 8

54 44

7

38

45

PP3V3_S5

44 43 42 40 26 22 21 8

69 64 62 61

7

PP3V42_G3H

50 46

SPI_CLK_R

R5190

10K

1

5%

1/16W

MF-LF

402

2

SPI_MOSI_R

LPCPLUS

R5191 1

10K

5%

1/16W

MF-LF

402

2

91 44 21

IN

1

2

VCC

Y+

TQFN

M+

YU5110 M-

PI3USB102ZLE

D+

D-

7

6

CRITICAL

5

4

10 SEL OE* 8

GND

LPCPLUS

1

2

C5114

0.1UF

20%

10V

CERM

402

SPI_ALT_CLK

SPI_ALT_MOSI

SPI_CLK_MUX

SPI_MOSI_MUX

B

SEL HIGH OUTPUTS TO D (ON BOARD ROM)

SEL LOW OUTPUTS TO M (FRANKCARD ROM)

40

69

26

64 62

22 21

61

8 7

50 46 45 44 43 42

PP3V42_G3H

R5140

44 21 BI

1

100K

5%

1/16W

MF-LF

402

2

SPIROM_USE_MLB

91 44 21 OUT

91 21

IN

SPI_MISO

SPI_CS0_R_L

44

21

SPIROM_USE_MLB

MAKE_BASE=TRUE

LPCPLUS

VCC

1

2

Y+ M+

YU5120 M-

PI3USB102ZLE

TQFN

D+

5

4

10

D-

SEL

CRITICAL

OE*

GND

7

6

8

LPCPLUS

1

2

C5124

0.1UF

20%

10V

CERM

402

LPCPLUS_NOT

R5146

0

1 2

5%

1/16W

MF-LF

402

PLACEMENT_NOTE=PLACE NEXT TO U1400

OUT

OUT

44

44

OUT

OUT

44 54

44 54

SPI_ALT_MISO

IN

44

Pull-up on debug card

SPI_ALT_CS_L

OUT

44

SPI_MISO_MUX

IN 44 54

SPI_MLB_CS_L

OUT 54

PP3V3_S5 R5144 1

20K

5%

1/16W

MF-LF

402

2

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

516S0573

A

54 44 OUT

SPI_CLK_MUX

54 44 OUT

SPI_MOSI_MUX

54 44 IN

SPI_MISO_MUX

SPI MUX BYPASS

LPCPLUS_NOT

R5156

0

1 2

5%

1/16W

MF-LF

402

LPCPLUS_NOT

R5158

1

0

2

LPCPLUS_NOT

R5157

0

1 2

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

SPI_CLK_R

IN 21 44 91

SPI_MOSI_R

IN 21 44 91

SPI_MISO

OUT 21 44 91

8

7 6 5 4 3

2 1

D

C

B

LPC+SPI Debug Connector

SYNC_MASTER=CHANGZHANG SYNC_DATE=05/09/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

44

OF

97

2 1

D

8 7 6

MCP79 SMBus "0" Connections

81 80

28 25

77

24

70

22

69 68

21 19

63

18

60 59

13 8 7 6

55 51 49 48 47 45 43

96

39

85

37 29

84 82

PP3V3_S0

MCP79

U2300

(MASTER)

29 28 21 13

91 45

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

29 28 21 13

91 45

MAKE_BASE=TRUE

R5200

1

1.6K

5%

1/16W

MF-LF

402

2

1

R5201

1.6K

5%

1/16W

2

MF-LF

402

SO-DIMM "A"

J3100

(Write: 0xA0 Read: 0xA1)

SMBUS_MCP_0_CLK

13 21 28 29

45 91

SMBUS_MCP_0_DATA

13 21 28 29

45 91

SO-DIMM "B"

J3200

(Write: 0xA2 Read: 0xA3)

SMBUS_MCP_0_CLK

13 21 28 29

45 91

SMBUS_MCP_0_DATA

13 21 28 29

45 91

5 4

SMC "0" SMBus Connections

81 80 77 70

28 25 24 22

69 68 63 60

21 19 18 13

59

8 7 6

PP3V3_S0

55 51 49 48 47 45 43

96

39 37

85 84

29

82

SMC

U4900

(MASTER)

R5250

1

1.6K

5%

1/16W

MF-LF

402

2

53 48 45 42

94 78

SMBUS_SMC_0_S0_SCL

53 48 45 42

94 78

94

78

53

48 45

42

SMBUS_SMC_0_S0_SCL

94 78 53

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

48 45

42

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

1

R5251

1.6K

2

5%

1/16W

MF-LF

402

GPU Temp (Ext)

EMC1413: U5550

(Write: 0x98 Read: 0x99)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

42 45 48

53 78 94

42 45 48

53 78 94

GPU Temp (Int)

GT216: U8000

(Write: 0x9E Read: 0x9F)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

42 45 48

53 78 94

42 45 48

53 78 94

Sensor ADCs

U5930


SMBUS_SMC_0_S0_SCL 78 94

42 45

48 53

SMBUS_SMC_0_S0_SDA 78 94

42 45

48 53

3 2 1

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

70 52 50 45 32 31 27 21 8 7

PP3V3_S3

SMC

U4900

(MASTER)

45 42 31 7

94 51

SMBUS_SMC_A_S3_SCL

45 42 31 7

94 51

SMBUS_SMC_A_S3_SDA

R5270

1

2.2K

5%

1/16W

MF-LF

402

2

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

1

R5271

2

2.2K

5%

1/16W

MF-LF

402

TRACKPAD

J5800


SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

94

7 31

42 45 51

94

7 31

42 45 51

D

ALS

J3401


SMBUS_SMC_A_S3_SCL

7 31 42 45

51 94

SMBUS_SMC_A_S3_SDA

7 31 42 45

51 94

C

B

MCP79 SMBus "1" Connections

81 80

28 25

77

24

70

22

69 68

21 19

63

18

60 59

13 8 7 6

55 51 49 48 47 45 43

96

39

85

37 29

84 82

PP3V3_S0

MCP79

U2300

(MASTER?)

85 60 45 21

91

SMBUS_MCP_1_CLK

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

85 60 45 21

91

MAKE_BASE=TRUE

R5230

1

2.0K

5%

1/16W

MF-LF

402

2

1

R5231

2.0K

5%

1/16W

2

MF-LF

402

Mikey

U6860

(WRITE: 0X72 READ: 0X73)

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

21 45 60

85 91

21 45 60

85 91

LED BACKLIGHT

U9701

(WRITE: 0x58 READ: 0x59)

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

21 45 60 85

91

21 45 60 85

91

A

8

7 6

SMC "Battery A" SMBus Connections

46 44 43 42 40 26 22 21 8

69 64 62 61

7

PP3V42_G3H

50

SMC

U4900

(MASTER)

61 45 42

94

7

62

SMBUS_SMC_BSA_SCL

61 45 42 7

94 62

SMBUS_SMC_BSA_SDA

R5280

2.61K

1

1%

1/16W

MF-LF

402

2

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

1 R5281

2.61K

2

1%

1/16W

MF-LF

402

Battery

J6955

(See Table)

SMBUS_SMC_BSA_SCL

7 42 45

61 62 94

SMBUS_SMC_BSA_SDA

7 42 45

61 62 94

Battery

Battery Manager - (Write: 0x16 Read: 0x17)

Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery Temp - (Write: 0x90 Read: 0x91)

Battery Charger

ISL6258A - U7000


SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

7 42 45 61

62 94

7 42 45 61

62 94

SMC "B" SMBus Connections

81

28

80

25

77 70

24 22

69 68

21 19

63

18

60

13 8

59

7 6

PP3V3_S0

55 51 49 48 47 45 43 39 37

96 85 84

29

82

SMC

U4900

(MASTER)

94 48 45 42

SMBUS_SMC_B_S0_SCL

94 48 45 42

SMBUS_SMC_B_S0_SDA

R5260 1

3.3K

5%

1/16W

MF-LF

402

2

94

48 45

94

42

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

48 45

42

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

1 R5261

2

3.3K

5%

1/16W

MF-LF

402

CPU Temp

EMC1413: U5570


SMBUS_SMC_B_S0_SCL

42 45

48 94

SMBUS_SMC_B_S0_SDA

42 45

48 94

MCP TEMP

EMC1413: U5500

(WRITE: 0XD8 READ: 0XD9)

SMBUS_SMC_B_S0_SCL

42 45

48 94

SMBUS_SMC_B_S0_SDA

42 45

48 94

SMC "Management" SMBus Connections

The bus formerly known as "Battery B"

70 52 50 45 32 31 27 21 8 7

PP3V3_S3

45 42 39 27

94

45 42 39 27

94

SMC

U4900

(MASTER)

R5290 1

1.6K

5%

1/16W

MF-LF

402

2

SMBUS_SMC_MGMT_SCL

94

45

42 39

27

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

94 45

42 39 SMBUS_SMC_MGMT_SDA

27

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

1 R5291

1.6K

5%

1/16W

2

MF-LF

402

Vref DACs

U2900


SMBUS_SMC_MGMT_SCL 94

27 39

42 45

SMBUS_SMC_MGMT_SDA 94

27 39

42 45

Margin Control

U2901



27 39

42 45


27 39

42 45

5 4

HDD Margin Control

J4501

(Write: 0xXX Read: 0xXX)


27 39

42 45


27 39

42 45

3

C

B

K19 SMBUS CONNECTIONS



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

45

OF

97

2 1

D

8 7 6 5 4

79 72 8

PPVCORE_GPU

CPU Voltage Sense / Filter

63 12 11 8 7

PPVCORE_S0_CPU

XW5309

SM

Place short near U1000 center

1 2 CPUVSENSE_IN

R5309

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_CPU_VSENSE

OUT 42

1

2

C5309

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

Place RC close to SMC

GPU Voltage Sense / Filter

XW5359

SM

1 2 GPUVSENSE_IN

Place short near U8000 center

R5359

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_GPU_VSENSE

OUT 42

1

2

C5359

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47


PBUS Voltage Sense & Filter

Q5315

FDG6332CG

SC70-6

P-CHN

67 66 65 64 62 61 46 37

86

8 7

83 79

PPBUS_G3H

R5315 1

100K

5%

1/16W

MF-LF

402

2

4 S

5

G

D 3 PPBUS_G3H_VSENSE



VOLTAGE=18.5V

R5385 1

27.4K

1%

1/16W

MF-LF

402

2

PBUSVSENS_EN_DIV

R5316 1

100K

5%

1/16W

MF-LF

402

2

PBUSVSENS_EN_L

Rthevanin = 4573 ohms

SMC_PBUS_VSENSE

OUT 42

R5386 1

5.49K

1%

1/16W

MF-LF

402

2

1

2

C5385

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47


6

D

70 69

PM_SLP_S3_L_R

Enables PBUS VSense divider when high.

2 G

S

1

Q5315

FDG6332CG

SC70-6

MCP Voltage Sense / Filter

66 24 22 8 7

PPVCORE_S0_MCP_REG

XW5399

SM

1 2 MCPVSENSE_IN

PLACEMENT_NOTE=Place near U1400 center

R5399

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_MCP_VSENSE

OUT

42 43

1

2

C5399

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47


C

3

B

BMON Current Sense - Entire circuit must be near SMC (U4900)

45 44 43 42 40

69

26 22

64 62

21

61

8 7

50 46

PP3V42_G3H

REGULATOR SIDE:

96 62

OUT

96 62 IN

CHGR_CSO_R_P

CHGR_CSO_R_N

LOAD SIDE:

Monitors battery discharge current from battery to PBUS

BMON_ENG

1

2

C5318

0.1uF

20%

10V

CERM

402

5

IN-

BMON_ENG

V+

U5303

INA213

SC70 OUT

6

4

IN+ REF

1

GND

BMON_INA_OUT

62

IN

CHGR_BMON

BMON_PROD

R5330

0

2

5%

1/16W

MF-LF

402

1

BMON_ENG

U5313

NC7SB3157P6XG

SC70

1 B1 SEL 6

1

2

GND VCC

5

0

3

B0 A

4

VER 1

SMC_BMON_MUX_SEL

IN 42 43

BMON_AMUX_OUT

BMON_ENG

1

R5371

100K

5%

1/16W

2

MF-LF

402

R5391

1

4.53K

2

1%

1/16W

MF-LF

402

1

2

BMON_ENG

C5369

0.1uF

20%

10V

CERM

402

SMC_BATT_ISENSE

OUT

42

1

2

C5390

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

INA213 has gain of 50V/V

2

62 IN

CHGR_AMON

DCIN Current Sense Filter


R5380

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_DCIN_ISENSE

OUT 42

1

2

C5380

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

1

D

C

B

42 40 26 22 21 8 7

69 64 62 61 50 46 45 44 43

PP3V42_G3H

63 8 OUT

PPBUS_CPU_IMVP_ISNS

A

62 61

79 67

86 83

46 37 8 7

66 65 64

IN

PPBUS_G3H

CPU VCore High Side Current Sensor

CRITICAL

R5388 1

0.001

1%

0.5W

MF

1206

2

3

4

96

ISNS_CPU_N

96

ISNS_CPU_P

1

2

C5388

0.1UF

20%

10V

CERM

402

5 IN-

V+

U5388

INA210

SC70 OUT

6

4

IN+ REF

1

GND

CPUVCORE_HISIDE_IOUT

R5335

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_CPU_HI_ISENSE

1

2

C5335

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47


OUT 42 43

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388

8

7 6 5 4

63

IN

CPU VCore Load Side Current Sense / Filter


R5331

6.19K

2 SMC_CPU_ISENSE

OUT

1%

1/16W

MF-LF

402

R5332

17.4K

1

1%

1/16W

MF-LF

402

2

1

2

C5330

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

42

3

Current & Voltage Sensing



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

46

OF

97

2 1

D

C

B

8 7

MCP VCore Current Sense

6 5 4 3 2 1

GPU VCore Current Sense

66

IN

82 81 80 77 70 69 68 63 60

28 25 24

55 51

22

49

21 19

48 47

18

45

13

43

8 7

39

96

37

85

59

6

29

84

PP3V3_S0

MCP VCore Current Sense Filter

MCPCORES0_IMON


R5470

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_MCP_CORE_ISENSE

OUT

1

2

C5470

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

42 43

MCP MEM VDD Current Sense

79 IN

R5493

GFXIMVP6_IMON 1

2.87K

2

1%

1/16W

MF-LF

402

96

GPUISENS_P

R5491

10K

1 2

96

GPUISENS_N

1%

1/16W

MF-LF

402

1.4X GAIN FOR SENSING CURRENT UP TO 25 AMPS

3

2

NC

V+

8

U5410

OPA2330

DFN

1 GPUVCORE_IOUT

THRM

9

V-

4

NC

NC

R5498

1

4.02K

2

1%

1/16W

MF-LF

402

C5498

470PF

1 2

10%

50V

CERM

402

GPU VCore Current Sense Filter


R5475

1

4.53K

2 SMC_GPU_ISENSE

1%

1/16W

MF-LF

402

OUT 42

1

2

C5475

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

D

P1V5_S0_KELVIN

70

IN

70

IN

P1V5_S0_SENSE

1 R5441

0

2

5%

1/16W

MF-LF

402

P1V5_S0_SENSE_E

2

C5441

0.1UF

1 2

1

10%

16V

X5R

402

Q5441

2SA2154MFV-YAE

SOD

P1V5_S0_SENSE_B

R5442

0

1 2

3

5%

1/16W

MF-LF

402

1 R5443

118

2

1%

1/16W

MF-LF

402

3

2

8

V+

CRITICAL

U5440

OPA2330

DFN

1

THRM

9

V-

4

1

2

C5440

0.1UF

20%

10V

CERM

402

MCP MEM VDD Current Sense Filter


R5440

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_MCP_DDR_ISENSE

1

2

C5490

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

OUT 42 43

P1V5_S0_SENSE_AMP

P1V5_S0_SENSE_C

MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share dual package opamp U5440

CPU FSB 1.05V Current Sense

GPU VCore Current Sense and GPU 1.8V Current Sense share dual package opamp U5410

GPU 1.8V Current Sense

C

83 8 IN

75 74 73 72 9 8

OUT

82 81

28 25

80

24

77

22

70 69

21 19

68

18

63 60

13 8

59

7 6

55 51 49 48 47 45 43 39 37 29

96 85 84

PP3V3_S0

PP1V8_S0GPU_ISNS_R

CRITICAL

R5413

0.002

1%

1/4W

MF

1206

1

2

3

4

PP1V8_S0GPU_ISNS

96

P1V8GPU_P

R5415

1

3.65K

2

96

P1V8GPUISNS_R_P

96

P1V8GPU_N

1%

1/16W

MF-LF

R5414

1

3.65K

2

96

P1V8GPUISNS_R_N

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY

C5412

470PF

10%

50V

CERM

402

1

2

SIGNAL_MODEL=EMPTY

1 R5412

1M

2

1%

1/16W

MF-LF

402

5

6

V+

8

THRM

9

V-

4

CRITICAL

U5410

OPA2330

DFN

1

2

C5410

0.1UF

20%

10V

CERM

402

7

R5411

1M

1 2

SIGNAL_MODEL=EMPTY

1%

1/16W

MF-LF

402

C5411

470PF

1 2

10%

50V

CERM

402

SIGNAL_MODEL=EMPTY

Gain: 274x

GPU 1.8V Current Sense Filter


R5465

4.53K

2

1%

1/16W

MF-LF

402

1

2

SMC_GPU_1V8_ISENSE

C5465

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47

OUT 42 43

B

A

8

96 67

CPUVTT_ISNS_P

R5431

1

3.65K

2

96

CPUVTTISNS_R_P

96 67

CPUVTT_ISNS_N

1%

1/16W

MF-LF

R5436

1

3.65K

2

96

CPUVTTISNS_R_N

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY

C5472

470PF

10%

50V

CERM

402

1

2

SIGNAL_MODEL=EMPTY

1 R5437

1M

2

1%

1/16W

MF-LF

402

5

6

NC

NC

V+

8

THRM

9

V-

4

NC

U5440

OPA2330

DFN

7

SIGNAL_MODEL=EMPTY

R5432

1M

1 2

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY

C5432

470PF

1 2

10%

50V

CERM

402

Gain: 274x

1.05V CPU Current Sense Filter

CPU1V05_S0_IOUT

R5495

1

4.53K

2

1%

1/16W

MF-LF

402

SMC_CPU_FSB_ISENSE

1

2

C5435

0.22UF

20%

6.3V

X5R

402

GND_SMC_AVSS

42 43 46 47


OUT 42 43

7 6 5 4 3

Current Sensing



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

47

OF

97

2 1

D

C

8 7 6 5

CPU Proximity/CPU Die/Right Fin Stack

82 81 80 77 70 69 68 63 60 59

28 25 24

55 51

22 21 19 18

49 48

13 8

47 45 43 39

7 6

37 29

96 85 84

PP3V3_S0

Detect CPU Die Temperature

96 10 BI

96 10 BI

R5570

47

1

5%

1/16W

MF-LF

402

2 PP3V3_S0_CPUTHMSNS_R



VOLTAGE=3.3V

CPU_THERMD_P

SIGNAL_MODEL=EMPTY

C5580

0.0022UF

10%

50V

CERM

402

CPU_THERMD_N

1

2

2

3

1

VDD

U5570

EMC1413

DFN

DP1 THERM*/ADDR

DN1

CRITICAL

ALERT*

4

DP2/DN3

5

DN2/DP3

GND

6

SMDATA

SMCLK

THRM_PAD

11

1

2

C5570

0.1uF

20%

10V

CERM

402

R5571 1

10K

1%

1/16W

MF-LF

402

2

7 CPUTHMSNS_THM_L

1 R5572

2

10K

5%

1/16W

MF-LF

402

8 CPUTHMSNS_ALERT_L

9 SMBUS_SMC_B_S0_SDA

10 SMBUS_SMC_B_S0_SCL

BI

BI

42 45 48 94

42 45 48 94

Detect Right Fin Stack Temperature

3

Q5501

BC846BMXXH

SOT732-3

2

1

96

CPUTHMSNS_D2_P

SIGNAL_MODEL=EMPTY

C5590

0.0022uF

10%

50V

CERM

402

96

CPUTHMSNS_D2_N

1

2

Placement note:

Place U5570 under CPU and close to left fin stack

Placement note:

Place Q5501 on bottom side close to right fin stack

4 3

MCP Proximity/MCP Die/Battery Charger Proximity

82 81

28 25

80

24

77 70

22 21

69 68

19 18

63 60

13 8

59

7 6

55 51 49 48 47 45 43 39

96

37 29

85 84

PP3V3_S0

Detect MCP Die Temperature

Detect Battery Charger Temperature

3

Q5502

BC846BMXXH

SOT732-3

2

Placement note:

Place Q5502 near battery charger circuit

96 21

BI

96 21

BI

1

R5500

47

1 2

5%

1/16W

MF-LF

402

MCP_THMDIODE_P

PP3V3_S0_REMTHMSNS_R



VOLTAGE=3.3V

SIGNAL_MODEL=EMPTY

C5511

0.0022uF

10%

50V

CERM

402

MCP_THMDIODE_N

96

MCPTHMSNS_D_P

1

2

96

SIGNAL_MODEL=EMPTY

C5521

0.0022uF

10%

50V

CERM

402

MCPTHMSNS_D_N

1

2

2

3

1

VDD

U5500

EMC1413

DFN

DP1

DN1

THERM*/ADDR

CRITICAL

ALERT*

4

DP2/DN3

5

DN2/DP3

GND

6

SMDATA

SMCLK

THRM_PAD

11

1

2

C5500

0.1uF

20%

10V

CERM

402

R5501 1

15.0K

1%

1/16W

MF-LF

402

2

1 R5502

10K

5%

1/16W

2

MF-LF

402

7 REMTHMSNS_THM_L

8 REMTHMSNS_ALERT_L

9

10

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

Placement note:

Place U5500 near MCP

BI 42 45 48 94

BI

42 45 48 94

Placement note:

Keep 2 caps as close to IC pins as possible

B

A

GPU Proximity/GPU Die/Left Heat Pipe

Detect Left Heat Pipe Temperature

Placement note:

Place on top side under left heat pipe near CPU

82

55

81

28 25

51

80

24

49

77

22

70

21

48 47

69

19

45

68

18

43

63

39

60

13 8 7

37

59

6

29

96 85 84

PP3V3_S0

Detect GPU Die Temperature

3

Q5503

BC846BMXXH

SOT732-3

2

1

96 77 76

BI

96 77 76

BI

96

GPUTHMSNS_D_P

R5550

47

1 2

5%

1/16W

MF-LF

402

GPU_TDIODE_P

PP3V3_S0_GPUTHMSNS_R



VOLTAGE=3.3V

SIGNAL_MODEL=EMPTY

C5551

0.0022uF

10%

50V

CERM

402

GPU_TDIODE_N

SIGNAL_MODEL=EMPTY

C5552

0.0022uF

10%

50V

CERM

402

96

GPUTHMSNS_D_N

1

2

1

2

2

DP1

3

DN1

4

DP2/DN3

5

DN2/DP3

GND

6

1

VDD

U5550

EMC1413

DFN

THERM*/ADDR

SMDATA

SMCLK

THRM_PAD

11

1

2

C5550

0.1uF

20%

10V

CERM

402

R5551 1

10K

1%

1/16W

MF-LF

402

2

Placement note:

Place U5550 near GPU

1 R5552

10K

5%

1/16W

2

MF-LF

402

7 GPUTHMSNS_THM_L

8 GPUTHMSNS_ALERT_L

9

10

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

BI 42 45 53 78 94

BI

42 45 53 78 94

Placement note:

Keep 2 caps as close to IC pins as possible

8

7 6 5 4 3

2 1

Note: EMC1413 can perform Beta

Compensation for External Diode 1 only

D

C

B

Thermal Sensors



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

48

OF

97

2 1

D

8 7 6 5 4 3 2 1

D

C Left Fan

70 67 66 63 51 49 44 39 8 7

PP5V_S0

77 70 69 68 63

85 83

60 59

28 25

55

24 22 21 19

51 49 48 47

18 13 8 7

45 43 39 37

6

PP3V3_S0

29

96 85 84 82 81 80

42 OUT

SMC_FAN_0_TACH

R5655

47K

1 2

5%

1/16W

MF-LF

402

R5650 1

47K

5%

1/16W

MF-LF

402

2

7

FAN_LT_TACH

R5651 1

100K

5%

1/16W

MF-LF

402

2

SMC_FAN_0_CTL 4 S

G

5

D

Q5660

2N7002DW-X-G

SOT-363

3

7

FAN_LT_PWM

42 IN

CRITICAL

J5650

78171-0004

M-RT-SM

5

1

2

3

4

6

518S0369

Right Fan

70 67 66 63 51 49 44 39 8 7

PP5V_S0

77 70 69 68 63

85 83

60 59

28 25

55

24 22 21 19

51

18

49 48 47 45

13

43

8 7

39 37

6

PP3V3_S0

29

96 85 84 82 81 80

42 OUT

SMC_FAN_1_TACH

R5665

47K

1 2

5%

1/16W

MF-LF

402

R5660 1

47K

5%

1/16W

MF-LF

402

2

7

FAN_RT_TACH

42 IN

R5661 1

100K

5%

1/16W

MF-LF

402

2

SMC_FAN_1_CTL 1 S

G

2

D

Q5660

2N7002DW-X-G

SOT-363

6

7

FAN_RT_PWM

CRITICAL

J5660

78171-0004

M-RT-SM

5

1

2

3

4

6

518S0369

C

B B

A

8

7 6 5 4 3

Fan Connectors



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

49

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

A

PSOC USB CONTROLLER

USB INTERFACES TO MLB

SPI HOST TO Z2

51 7

50

51 7

50

50

PICKB_L

BUTTON_DISABLE

Z2_HOST_INTN

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

50

51 7

51 7

51 7

51 7

51 7

51 7

51 7

51 7

51 7

51 7

51 7

WS_CONTROL_KEY

Z2_KEY_ACT_L

TP_BOOT_CFG1

TP_P4_5

Z2_DEBUG3

Z2_RESET

PSOC_MISO

PSOC_F_CS_L

PSOC_MOSI

PSOC_SCLK

Z2_MISO

Z2_CS_L

Z2_MOSI

Z2_SCLK

1

P2_3

2

P2_1

3 P4_7

4

P4_5

5

P4_3

6 P4_1

7

P3_7

8

P3_5

9 P3_3

10 P3_1

11

P5_7

12

P5_5

13 P5_3

14

P5_1

TP_PSOC_SCL

7

NC_PSOC_SDA

7

NC_PSOC_P1_3

TRACKPAD PICK BUTTONS

KEYBOARD SCANNER

PP3V3_S3_PSOC

50

CRITICAL

U5701

CY8C24794

MLF

(SYM-VER2)

APN 337S2983

OMIT

TMP102

3V3 LDO

IC

PSOC

18V BOOSTER

PIN NAME

V+

VDD

VOUT

VDD

VIN

CURRENT

10UA

80UA

60MA MAX

60MA MAX

8MA (TYP)

14MA (MAX)

4MA (MAX)

R_SNS

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

V_SNS

0.0255 V

0.204 V

0.6 V

0.012 V

0.012 V

0.021 V

0.0188 V

POWER

0.255E-6 W

16.32E-6 W

36E-3 W

0.72E-3 W

96E-6 W

294E-6 W

75.2E-6 W

PSOC PROGRAMMING CONNECTOR

TEST POINTS ARE FOR ON BOARD PROGRAMMING

P2_2

P2_0

42

41

P4_6 40

P4_4

39

P4_2

P4_0

38

37

P3_6

P3_4

36

35

P3_2

P3_0

34

33

P5_6

32

31

P5_4

P5_2 30

P5_0

29

THRML

PAD 57

WS_KBD17

7 50

WS_KBD16N

50

WS_KBD15_C

50

WS_KBD14

7 50

WS_KBD13

7 50

WS_KBD12

7 50

WS_KBD11

7 50

WS_KBD10

7 50

WS_KBD9

7 50

WS_KBD8

7 50

WS_KBD7

7 50

WS_KBD1

7 50

WS_KBD2

7 50

WS_KBD3

7 50

70 52 50 45 32 31 27 21 8 7

PP3V3_S3

50

ISSP_SCLK_P1_1

50

ISSP_SDATA_P1_0

WS_KBD4

7 50

WS_KBD5

7 50

WS_KBD6

7 50

ISSP_SDATA_P1_0

50

ISSP SDATA/I2C SDA

Z2_CLKIN

7 51

TPAD_DEBUG

APN 518S0430

J5702

FH19C-4S-0.5SH25

F-RT-SM1

5

NC

1

2

3

4

ISSP CLOCK

ISSP DATA

6

NC

ISOLATION CIRCUIT

46 45 44 43 42 40 26

69 64

22 21 8 7

PP3V42_G3H

62 61 50

52 50 45 32 31 27 21 8 7

PP3V3_S3

70

50 7

WS_LEFT_SHIFT_KBD

C5725

0.1UF

2 1

2

1

A

5

CRITICAL

TC7SZ08AFEAPE

SOT665

20%

10V

CERM

402

4

U5725

Y

B

3

WS_LEFT_SHIFT_KEY

50

NC_P7_7

7

50

ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

DIFFERENTIAL_PAIR=USB2_TPAD

USB_TPAD_P

91 20

R5701

24

1 2

5%

1/16W

MF-LF

402

USB_TPAD_R_P


NET_SPACING_TYPE=USB

NET_PHYSICAL_TYPE=USB_90D

TO MLB CONNECTOR

USB_TPAD_N

91 20


R5702

24

1 2

5%

1/16W

MF-LF

402

USB_TPAD_R_N


NET_SPACING_TYPE=USB

NET_PHYSICAL_TYPE=USB_90D

PP3V3_S3_PSOC

50

45 44 43 42 40 26 22

69 64 62 61

21

50

8 7

46

PP3V42_G3H

70 52 50 45 32 31 27 21 8 7

PP3V3_S3

50 7

WS_LEFT_OPTION_KBD

PP3V42_G3H

46 45 44 43 42 40 26

69

22 21

64 62

8 7

61 50

70 52 50 45 32 31 27 21 8 7

PP3V3_S3

50 7

WS_CONTROL_KBD

2

A

1

B

5

CRITICAL

SOT665

4

3

U5701 CHIP DECOUPLING

PLACE C5701, C5702 & C5703

CLOSE TO U5701 VDD PIN 22

50

PP3V3_S3_PSOC

1

2

C5701

4.7UF

20%

6.3V

X5R

603

1

2



C5702

100PF

5%

50V

CERM

402

1

2

C5703

0.1UF

10%

16V

X7R-CERM

402

PLACE C5704, C5705 & C5706

CLOSE TO U5701

VDD PIN 49

1

2

C5704

100PF

5%

50V

CERM

402

1

2

C5705

0.1UF

10%

16V

X7R-CERM

402

R5704

1.5

1 2

PP3V3_S3

7 8 21 27 31 32 45 50 52 70

1

2

5%

1/16W

MF-LF

C5706

4.7UF

20%

6.3V

X5R

603

2

1

5

CRITICAL

TC7SZ08AFEAPE

SOT665

A

U5726

Y

B

4

3

WS_LEFT_OPTION_KEY

50

TPAD BUTTONS DISABLE

50

BUTTON_DISABLE

PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

Q5701

SSM3K15FV

SOD-VESM-HF

D 3

WS_CONTROL_KEY

50

50

WS_KBD15_C

R5714

470

1 2

1%

1/16W

MF-LF

402

50

WS_KBD16N

R5715

10K

1 2

1%

1/16W

MF-LF

402

43 42

OUT

SMC_ONOFF_L

1

2

C5710

0.1UF

20%

10V

CERM

402

PLACEMENT_NOTE=NEAR J5713

KEYBOARD CONNECTOR

J5713

APN 518S0637

NC 32

IN

PP3V3_S3

50 7

50 7

WS_KBD1

WS_KBD2

50 7

50 7

WS_KBD3

WS_KBD4

50 7

WS_KBD5

50 7

50 7

WS_KBD6

WS_KBD7

50 7

50 7

WS_KBD8

WS_KBD9

50 7

WS_KBD10

50 7

50 7

50 7

WS_KBD11

WS_KBD12

WS_KBD13

50 7

WS_KBD14

7

WS_KBD15_CAP

7

WS_KBD16_NUM

50 7

50 7

WS_KBD17

WS_KBD18

50 7

50 7

WS_KBD19

WS_KBD20

50 7

WS_KBD21

R5710

1

50 7

50 7

WS_KBD22

WS_KBD23

1K

2

7

WS_KBD_ONOFF_L

5%

1/16W

44 43 42 40 26 22 21

69 64 62 61 50

8 7

46 45

MF-LF

402

50 7

PP3V42_G3H

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KBD

50 7

50 7

WS_CONTROL_KBD

4

3

2

1

11

10

9

8

7

6

5

18

17

16

15

14

13

12

25

24

23

22

21

20

19

30

29

28

27

26

NC

31

F-RT-SM

FF14-30A-R11B-B-3H

SMC_MANUAL_RESET LOGIC

45 44 43 42 40 26

69 64

22

62

21 8

61 50

7

46

PP3V42_G3H

1

2

C5758

0.1UF

10%

16V

X7R-CERM

402

50 7

WS_LEFT_SHIFT_KBD

50 7

WS_LEFT_OPTION_KBD

50 7

WS_CONTROL_KBD

1 R5769

33K

2

5%

1/16W

MF-LF

402

1 R5770

33K

2

5%

1/16W

MF-LF

402

1 R5771

33K

2

5%

1/16W

MF-LF

402

APN 311S0406

CRITICAL

1

3

6

A

5 SN74LVC1G10

SC70

4

U5703

Y

SMC_TPAD_RST_L

C

43

2

8

7 6

61 43 42 IN

SMC_LID

1 G S

2

THE TPAD BUTTONS WILL BE DISABLE

WHEN THE LID IS CLOSED

LID OPEN => SMC_LID_LC ~ 3.42V

LID CLOSE => SMC_LID_LC < 0.50V

5 4 3

D

C

B

WELLSPRING 1









SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

50

OF

97

A

2 1

D

C

B

8 7 6 5

BOOSTER +18.5VDC FOR SENSORS

4 3 2 1

55 53 51 43 41 40 39 31

79

9 8 7

PP5V_S3

70 65 64

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

- DROOP LINE REGULATION

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

APN 152S0504

CRITICAL

L5801

3.3UH-870MA

INPUT_SW

0.50MM

0.20MM

1 2

VLF3010AT-SM-HF

PP5V_S3_BOOSTER


APN 353S1401

1

2

C5816

0.1UF

10%

16V

X7R-CERM

402

1

2

C5817

2.2UF

10%

16V

X5R

603

1

3

VIN

L

DO

U5805

TPS61045

FB

QFN

CTRL

CRITICAL

SW

THRML

PAD

4

5

8

D5802

SOD-323

1 2 BOOST_SW



B0520WSXG

SWITCH_NODE=TRUE

APN 371S0313


1

2

C5818

39PF

5%

50V

CERM

402

1

R5812

1M

2

1%

1/16W

MF-LF

402

Z2_BOOST_EN

7 51

1

BOOST_FB

R5811

100K

2

1%

1/16W

MF-LF

402

1 R5813

71.5K

2

1%

1/16W

MF-LF

402

1

2

C5819

1UF

10%

25V

X5R

603-1

R5806

0

1 2

PP18V5_S3

7 51

5%

1/16W

MF-LF

402

IPD FLEX CONNECTOR

50 7

Z2_CS_L

50 7

Z2_DEBUG3

50 7

Z2_MOSI

50 7

Z2_MISO

50 7

Z2_SCLK

51 7

Z2_BOOST_EN

50 7

Z2_HOST_INTN

50 7

Z2_CLKIN

51 7

PP3V3_S3_LDO

APN 516S0689

0.50MM

0.20MM

CRITICAL

J5800

55560-0228

M-ST-SM

12

14

16

18

20

22

2

4

6

8

10

11

13

15

17

19

21

1

3

5

7

9

Z2_KEY_ACT_L

Z2_RESET

7 50

7 50

PSOC_F_CS_L

7 50

PICKB_L

PSOC_MISO

7 50

7 50

PSOC_MOSI

7 50

0.50MM

0.20MM

PSOC_SCLK

7 50

SMBUS_SMC_A_S3_SDA

7 31 42 45

94 SMBUS_SMC_A_S3_SCL

7 31 42 45

94

PP18V5_S3

7 51

D

C

55 53 51 43 41 40

PP5V_S3

39 31 9 8 7

79 70 65 64

3V3 LDO FOR IPD

R5873

10

1 2

1%

1/16W

MF-LF

402

PP5V_S3_VR

1

2

C5853

2.2UF

10%

16V

X5R

603

51 7

PP3V3_S3_LDO

CRITICAL

APN 353S1364

1

VDD

VR5802

MM3243DRRE

MLF

CE VOUT

GND

3

PP3V3_S3_LDO_R

1

2

C5838

0.1UF

10%

16V

X7R-CERM

402

1

2

C5854

4.7UF

20%

6.3V

X5R

603

B

A

8

To detect Keyboard backlight, SMC will tristate SMC_SYS_KBDLED:

LOW = keyboard backlight present

HIGH= keyboard backlight not present

BOM OPTION: KBDLED_YES

R5853 ALWAYS PRESENT

7

Keyboard LED Driver

82

28 25

81 80 77 70

24 22 21 19

69 68 63 60

18 13 8 7 6

PP3V3_S0

59 55 49 48 47 45 43 39

96

37

85

29

84

83 70 67 66 63 49 44 39 8 7

85

PP5V_S0

R5853

470K

1

5%

1/16W

MF-LF

402

2

C5850

1UF

10%

10V

X5R

402-1

1

2

42

SMC_SYS_KBDLED

R5854 1

4.7K

5%

1/16W

MF-LF

402

2

NO STUFF

R5852 1

10K

5%

1/16W

MF-LF

402

2


51 7

6

6

CTRL

CRITICAL

L5850

10UH-0.58A-0.35OHM

VIN

1

CRITICAL

U5850

LT3491

DFN

GND

1098AS-SM

SW

3

LED

5

CAP 4

THRML

PAD

2 KBDLED_SW



SWITCH_NODE=TRUE

1

R5855

10

2

1%

1/16W

MF-LF

402

KBDLED_CAP



1

2

C5855

1UF

10%

35V

X5R

603

J5815 pin 1 is grounded

CRITICAL on keyboard backlight flex

J5815

FF18-4A-R11AD-B-3H

F-RT-SM

51 7


1

2

3

7

KBDLED_ANODE



4

APN 518S0612

KBD BACKLIGHT CONNECTOR

WELLSPRING 2

SYNC_MASTER=PWRSQNC SYNC_DATE=01/05/2009








SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

51

OF

97

A

5 4 3 2 1

D

8 7 6 5 4 3 2 1

D

C C

B

Analog SMS

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

70 50 45 32 31 27 21 8 7

PP3V3_S3

52 42

IN

SMS_PWRDN

52 42

R5921

1

10K

5%

1/16W

MF-LF

402

2

SMS_PWRDN

MAKE_BASE=TRUE

NC

1 R5922

10K

5%

1/16W

2

MF-LF

402

NC

NC

NC

1

5

15

4

VDD

FS

U5920

AP344ALH

LGA

VOUTX

PD

CRITICAL

VOUTY

ST

VOUTZ

RES

RES

3

6

9

NC

NC

NC

GND

12

10

8

SMS_X_AXIS

SMS_Y_AXIS

SMS_Z_AXIS

NC

NC

NC

11

13

16

NC

NC

NC

1

2

C5922

0.1UF

10%

16V

X5R

402

1

2

C5926

10UF

20%

4V

X5R

603

OUT 42

OUT 42

OUT 42

1

2

C5923

0.01UF

10%

16V

CERM

402

1

2

C5924

0.01UF

10%

16V

CERM

402

1

2

C5925

0.01UF

10%

16V

CERM

402

Desired orientation when placed on board top-side:

+Y

+X

Front of system

+Z (up)

Circle indicates pin 1 location when placed in correct orientation

A

8

7 6 5 4 3

B

Sudden Motion Sensor (SMS)



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

52

OF

97

2 1

D

8 7 6 5

PLACEMENT_NOTE=PLACE NEAR Q3450

31

PP5V_WLAN_F

PLACEMENT_NOTE=PLACE NEAR Q4590

XW6010

SM

1 2 PP5V_WLAN_F_XW

39 7

PP5V_SW_ODD

DEBUG_ADC

1 R6010

1M

1%

1/16W

2

MF-LF

402

PLACEMENT_NOTE=PLACE RC NEAR U6000

PP5V_WLAN_F_DIV

DEBUG_ADC

DEBUG_ADC

R6012

1

226K

2 ADC_CH0

53

1 R6011

681K

1%

1/16W

MF-LF

2

402

1%

1/16W

MF-LF

402 1

2

DEBUG_ADC

C6012

2.2UF

10%

6.3V

X5R

402

XW6020

SM

1 2 PP5V_SW_ODD_XW

DEBUG_ADC

1 R6020

1M

1%

1/16W

2

MF-LF

402


PP5V_SW_ODD_DIV

DEBUG_ADC

DEBUG_ADC

R6022

1

226K

2 ADC_CH1

53

1 R6021

681K

1%

1/16W

2

MF-LF

402

1%

1/16W

MF-LF

402 1

2

DEBUG_ADC

C6022

2.2UF

10%

6.3V

X5R

402

DIVIDER: ~ 2/5

DIVIDER: ~ 2/5

4 3

55 53 51 43 41 40 39 31 9

79 70

8

65

7

PP5V_S3

64

1

2

DEBUG_ADC

C6000

0.1UF

20%

10V

CERM

402

55 53 51 43 41 40 39 31 9

79 70

8

65

PP5V_S3

64

1

2

DEBUG_ADC

C6001

10UF

20%

6.3V

X5R

603

2

1

2

DEBUG_ADC

C6002

0.1UF

20%

10V

CERM

402

1

2

DEBUG_ADC

C6003

10UF

20%

6.3V

X5R

603

53

ADC_CH0

53

ADC_CH1

53

ADC_CH2

53

ADC_CH3

53

ADC_CH4

53

ADC_CH5

53

ADC_CH6

53

ADC_CH7

I2C ADDRESS: 0X10 / 0X11

ADC RANGE: 0V TO 4.096V

LSB: 0.001V

1

22

23

24

1

2

3

4

5

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

6

COM

AVDD DVDD

U6000

LTC2309

QFN

DEBUG_ADC

AD0

AD1

SDA

SCL

VREF

7

14

15

17

16

ADC_SDA

ADC_SCL

DEBUG_ADC

R6001

0

1 2

PLACEMENT_NOTE=PLACE CLOSE TO U4900

SMBUS_SMC_0_S0_SDA

5%

1/16W

MF-LF

402

ADC_VREF

BI

DEBUG_ADC

R6002

0

1 2


SMBUS_SMC_0_S0_SCL

IN

5%

1/16W

MF-LF

402

42 45 48

78 94

42 45 48 78 94

D

GND

REFCOMP 8

THRM

PAD

ADC_REFCOMP

1

2

DEBUG_ADC

C6004

0.1UF

20%

10V

CERM

402

1

2

DEBUG_ADC

C6005

10UF

20%

6.3V

X5R

603

1

2

DEBUG_ADC

C6006

2.2UF

20%

6.3V

CERM

402-LF

C

B

A

96 31 IN

96 31 IN

96 65 IN

96 65 IN

96 85

IN

96 85

IN

55 53 51 43 41 40 39 31 9 8

79 70 65

7

64

PP5V_S3

ISNS_AIRPORT_P

DEBUG_ADC

R6030

243

1 2

1%

1/16W

MF-LF

402

96

ISNS_AIRPORT_R_P

ISNS_AIRPORT_N

DEBUG_ADC

R6031

243

1 2

1%

1/16W

MF-LF

402

96

ISNS_AIRPORT_R_N

DEBUG_ADC

C6032

470PF

10%

50V

CERM

402

1

2

ISNS_1V5_S3_P

DEBUG_ADC

R6040

1

3.65K

2

1%

1/16W

MF-LF

402

96

ISNS_1V5_S3_R_P

ISNS_1V5_S3_N

DEBUG_ADC

R6041

1

3.65K

2

1%

1/16W

MF-LF

402

96

ISNS_1V5_S3_R_N

DEBUG_ADC

C6042

470PF

10%

50V

CERM

402

1

2

55 53 51 43 41 40 39 31 9 8 7

79 70 65 64

PP5V_S3

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

5

4

R6032

2

301K

1%

1/16W

MF-LF

402

DEBUG_ADC

1 R6042

2

1M

1%

1/16W

MF-LF

402

V+

3

2

THRM

9

V+

8

DEBUG_ADC

U6030

OPA2330

DFN

1


ISNS_AIRPORT_IOUT

DEBUG_ADC

R6034

226K

1 2 ADC_CH2

53

V-

4

GAIN: 1239X

1%

1/16W

MF-LF

402

1

2

DEBUG_ADC

C6034

2.2UF

10%

6.3V

X5R

402

DEBUG_ADC

R6033

301K

1 2

1

2

DEBUG_ADC

C6030

0.1UF

20%

10V

CERM

402

1%

1/16W

MF-LF

402

DEBUG_ADC

C6033

470PF

1 2

10%

50V

CERM

402

5

6


V+

8

U6030

OPA2330

DFN

7 ISNS_1V5_S3_IOUT

DEBUG_ADC

R6044

226K

1 2 ADC_CH3

53

THRM

9

V-

4

GAIN: 273X

1%

1/16W

MF-LF

402

1

2

DEBUG_ADC

C6044

2.2UF

10%

6.3V

X5R

402

DEBUG_ADC

R6043

1M

1 2

1%

1/16W

MF-LF

402

DEBUG_ADC

C6043

470PF

1 2

10%

50V

CERM

402

IN-

U6050

INA210

SC70 OUT

DEBUG_ADC

IN+

GND

6

REF

1

96 39 IN

96 39 IN

96 39 IN

96 39 IN

ISNS_ODD_P

ISNS_ODD_N

ISNS_HDD_P

ISNS_HDD_N

DEBUG_ADC

R6050

499

1 2

1%

1/16W

MF-LF

402

96

ISNS_ODD_R_P

DEBUG_ADC

R6051

499

1 2

1%

1/16W

MF-LF

402

96

ISNS_ODD_R_N

DEBUG_ADC

C6052

470PF

10%

50V

CERM

402

1

2

DEBUG_ADC

R6060

412

1 2

1%

1/16W

MF-LF

402

96

ISNS_HDD_R_P

DEBUG_ADC

R6061

412

1 2

1%

1/16W

MF-LF

402

96

ISNS_HDD_R_N

DEBUG_ADC

C6062

470PF

10%

50V

CERM

402

1

2

R6052

280K

1%

1/16W

2

MF-LF

402

R6062

348K

1%

1/16W

2

MF-LF

402

DIVIDER: ~ 1/22

3

2

THRM

9

V+

8

DEBUG_ADC

U6040

OPA2330

DFN

1


ISNS_ODD_IOUT

DEBUG_ADC

R6054

226K

1 2 ADC_CH4

53

V-

4

GAIN: 561X

1%

1/16W

MF-LF

402

1

2

DEBUG_ADC

C6054

2.2UF

10%

6.3V

X5R

402

DEBUG_ADC

R6053

280K

1 2

1

2

DEBUG_ADC

C6040

0.1UF

20%

10V

CERM

402

1%

1/16W

MF-LF

402

DEBUG_ADC

C6053

470PF

1 2

10%

50V

CERM

402

5

6


V+

8

U6040

OPA2330

DFN

7 ISNS_HDD_IOUT

DEBUG_ADC

R6064

226K

1 2 ADC_CH5

53

THRM

9

V-

4

GAIN: 845X

1%

1/16W

MF-LF

402

1

2

DEBUG_ADC

C6064

2.2UF

10%

6.3V

X5R

402

DEBUG_ADC

R6063

348K

1 2

1%

1/16W

MF-LF

402

DEBUG_ADC

C6063

470PF

1 2

10%

50V

CERM

402 PLACEMENT_NOTE=PLACE NEAR D9701

1

2

DEBUG_ADC

C6050

0.1UF

20%

10V

CERM

402


ISNS_LCDBKLT_IOUT

DEBUG_ADC

R6074

226K

1 2

GAIN: 200X

1%

1/16W

MF-LF

402 1

2

ADC_CH6

53

DEBUG_ADC

C6074

2.2UF

10%

6.3V

X5R

402

85 80 7

PPVOUT_S0_LCDBKLT

XW6080

SM

1 2 PPVOUT_S0_LCDBKLT_XW

DEBUG_ADC

1 R6080

1M

1%

1/16W

2

MF-LF

402

PPVOUT_S0_LCDBKLT_DIV

DEBUG_ADC

1 R6081

47.0K

2

1%

1/16W

MF-LF

402


DEBUG_ADC

R6082

226K

1 2

1%

1/16W

MF-LF

402 1

2

ADC_CH7

53

DEBUG_ADC

C6082

2.2UF

10%

6.3V

X5R

402

DEBUG SENSORS AND ADC









SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

53

OF

97

C

B

A

8

7 6 5 4 3 2 1

8 7 6 5 4 3 2 1

D

D

C

B

A

8

7

37 34 30 26 24

96

22 20 18 8 7

87 82 70 69 68 64 44 38

PP3V3_S5

44

IN

SPI_CLK_MUX


SPI_MLB_CS_L

NO STUFF

R6190 1

10K

5%

1/16W

MF-LF

402

2

R6150

0

1 2

5%

1/16W

MF-LF

402

44 IN

R6100 1

3.3K

5%

1/16W

MF-LF

402

2

1 R6101

3.3K

2

5%

1/16W

MF-LF

402

91

SPI_CLK

C6100

0.1UF

20%

10V

CERM

402

1

2

SPI_WP_L

SPI_HOLD_L

CRITICAL

VCC

1

3

6

SCLK

U6100

32MBIT

SOP

SI/SIO0

5

MX25L3205DM2I-12G

CE*

WP*/ACC

OMIT

SO/SIO1

2

7

HOLD*

GND

91

SPI_MOSI

91

SPI_MISO_R

NO STUFF

1 R6191

10K

2

5%

1/16W

MF-LF

402

R6105

0

1 2

5%

1/16W

MF-LF

402

R6152

0

1 2

5%

1/16W

MF-LF

402

SPI_MOSI_MUX

IN

44


SPI_MISO_MUX


OUT

44

MCP79 SPI Frequency Select

Frequency SPI_MOSI SPI_CLK

31 MHz

42 MHz

25 MHz

1 MHz

1

1

0

0

0

1

0

1

25MHz is selected with R5190 and R5191

Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191

6 5 4 3

C

B

SPI ROM

SYNC_MASTER=CHANG_M98_MLB SYNC_DATE=07/01/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

54

OF

97

2 1

D

C

B

A

8 7 6 5 4 3 2

87 84 70 69 25 18 8 7 IN

PP1V8_S0

CRITICAL

L6201

FERR-220-OHM

1

0402

59 57 55

GND_AUDIO_HP_AMP

55 7 IN

PP4V5_AUDIO_ANALOG

28

70

25

69 68

24 22

55 51 49

63

21

48

96

60

19

47 45 43 39

85

59

18

84

13

82

8 7 6

81

37 29

80 77

PP3V3_S0

K19

1 R6218

2

10K

5%

1/16W

MF-LF

402

NC TP_AUD_GPIO_0

NC TP_AUD_GPIO_2

AUD_GPIO_3

58

OUT

AUD_SENSE_A

60 IN

K19I

1 R6219

2

10K

5%

1/16W

MF-LF

402

1

2

CRITICAL

C6210

4.7UF

20%

4V

X5R

402

R6210

2.67K

2

1%

1/16W

MF-LF

402

1

2

AUD_GPIO_1

1

2

C6211

0.1UF

10%

16V

X5R

402

PP1V8_S0_AUDIO_DIG

VOLTAGE=1.8V



CRITICAL

CRITICAL

C6221

10UF

20%

6.3V

X5R

603-1

1

2

1

2

C6219

20%

16V

TANT-POLY

2012-LLP

CRITICAL

10UF

C6220

10UF

20%

6.3V

X5R

603-1

1

2

VBIAS_DAC

CS4206_FP

CS4206_FN

CRITICAL

C6222

2.2UF

20%

6.3V

CERM

402-LF

1

2

1

2

CS4206_FLYP

CS4206_FLYC

CRITICAL

C6223

2.2UF

20%

6.3V

CERM

402-LF

CS4206_FLYN

AUDIO CODEC

APPLE P/N 353S2355

29

44

41

C6218

0.1UF

10%

16V

X5R

402

1

2

VD VA_REF

VBIAS_DAC

VA_HP VA

VHP_FILT+

VHP_FILT-

HPOUT_L

HPOUT_R

HPREF

38

40

39

1

2

C6217

2

12

14

15

GPIO0/DMIC_SDA1 LINEOUT_L1+

GPIO1/DMIC_SDA2

GPIO2

/SPDIF_OUT2

LINEOUT_L1-

LINEOUT_R1+

GPIO3 LINEOUT_R1-

13 SENSE_A

45

43

42

FLYP

FLYC

FLYN

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

LINEOUT_R2-

3 VL_HD

MICBIAS

U6201

CS4206ACNZC

QFN

CRITICAL

VCOM

1 VL_IF

31

30

32

33

35

34

36

37

16

28

CS4206_VCOM

CRITICAL

10UF

20%

16V

TANT-POLY

2012-LLP

C6216

1UF

CRITICAL

X5R

402-1




1

2

C6215

0.1UF

10%

16V

X5R

402

1

2

C6214 1

0.1UF

10%

16V

X5R 2

402




91 21 IN

91 21

IN

HDA_BIT_CLK

HDA_SYNC

6 BITCLK

LINEIN_L+

LINEIN_C-

LINEIN_R+

21

22

23

91 21 OUT

HDA_SDIN0

91 21 IN

91 21

59

IN

IN

HDA_SDOUT

HDA_RST_L

AUD_SPDIF_IN

R6211

39

1 2

5%

1/16W

MF-LF

402

AUD_SDI_R

AUD_SPDIF_OUT_CHIP

10 SYNC

8

5

SDI

SDO

11 RESET*

47

48

SPDIF_IN

SPDIF_OUT

MICIN_L+

MICIN_L-

MICIN_R+

MICIN_R-

18

17

19

20

VREF+_ADC 27

59

OUT

AUD_SPDIF_OUT

R6212

39

1 2

5%

1/16W

MF-LF

402 DGND THRM_PAD AGND

DMIC_SCL 4

CS4206_VREF_ADC NC

CRITICAL

C6224

1UF

20%

16V

TANT

0603-SM

1

2

1

2

CRITICAL

C6225

10UF

20%

16V

POLY-TANT

CASE-B2-SM

1 R6213

100K

5%

1/16W

2

MF-LF

402

PP5V_S3

7 8 9 31 39 40 41 43 51 53 55

64 65 70 79

1

2

CRITICAL

C6213

10UF

20%

6.3V

X5R

603

PP3V3_S0 59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

PP4V5_AUDIO_ANALOG

IN

VOLTAGE=4.5V



7 55

GND_AUDIO_HP_AMP

GND_AUDIO_CODEC

55 57 59

55 56 60

AUD_HP_PORT_L

AUD_HP_PORT_R

OUT

OUT

OUT

OUT

OUT

OUT

57

57

AUD_HP_PORT_REF

IN

NC_AUD_LO1_P_L

NC_AUD_LO1_N_L

AUD_LO1_P_R

AUD_LO1_N_R

59

NC

7

NC

7

58

OUT

OUT

58

AUD_LO2_P_L

AUD_LO2_N_L

AUD_LO2_P_R

AUD_LO2_N_R

58

58

58

58

AUD_CODEC_MICBIAS

OUT

60

AUD_LI_P_L

AUD_LI_REF

AUD_LI_P_R

IN

IN

IN

56

56

56

AUD_MIC_INP_L

AUD_MIC_INN_L

AUD_MIC_INP_R

AUD_MIC_INN_R

IN

IN

IN

IN

60

60

60

60

TP_AUD_DMIC_CLK NC

60 56 55

GND_AUDIO_CODEC



VOLTAGE=0V

8

55 53 51 43 41 40 39

79

31 9

70 65

8 7

64

IN

PP5V_S3

80

28

77 70

25 24

69 68

22 21

63

19

60

18

59

13 8

55

7 6

51 49 48 47 45 43

96 85

39 37 29

84 82 81

IN

PP3V3_S0

4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2234

CRITICAL

L6200

FERR-220-OHM

1 2



VOLTAGE=5V

4V5_REG_IN

0402

R6200

1

2.21K

2

4V5_REG_EN 3

CRITICAL

1

U6200

MAX8840-4.5V

UDFN

IN OUT

6

SHDN*

BP

NC

4 4V5_NR

5

1%

1/16W

MF-LF

402

1

2

C6200

1UF

10%

10V

X5R

402-1

XW6200

SM

1 2

1

2

CRITICAL

C6201

1UF

10%

10V

X5R

402-1

GND



VOLTAGE=4.5V

C6202

0.1UF

1 2

10%

16V

X7R-CERM

402

PP4V5_AUDIO_ANALOG

OUT

1

2

CRITICAL

C6203

1UF

10%

10V

X5R

402-1

GND_AUDIO_CODEC

VOLTAGE=0V

7 55

55 56 60

NOSTUFF

R6201

0

1 2

5%

1/16W

MF-LF

402

XW6201

SM

1 2



VOLTAGE=0V

GND_AUDIO_HP_AMP

55 57 59

7 6 5 4

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS

SE FSINPUT= 1.22VRMS

DAC1 FSOUTPUT= 1.34VRMS

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

DAC2/3 FSOUTPUTSE= 1.34VRMS

3

1

AUDIO: CODEC/REGULATOR








SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

55

OF

97

2 1

D

C

B

A

D

C

B

8 7 6 5 4 3

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS

NET RIN = 20K OHMS

FC = 8 HZ

VIN = 2VRMS, CODEC VIN = 1.21 VRMS

59

IN

AUD_LI_L

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

59 IN

AUD_LI_GND

60 55 IN

GND_AUDIO_CODEC

1

R6300

10

1%

1/16W

MF-LF

2

402

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

59 IN

AUD_LI_R

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

R6301

1

6.04K

2

1%

1/16W

MF-LF

402

AUD_LI_L_DIV

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

R6311

1

6.04K

2

1%

1/16W

MF-LF

402

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

CRITICAL

C6301

3.3UF

1 2

10%

10V

CERM-X5R

805-1

1 R6302

16.5K

1%

1/16W

2

MF-LF

402

CRITICAL

C6302

3.3UF

1 2

10%

10V

CERM-X5R

805-1

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

OUT

55

1

2

CRITICAL

NOSTUFF

C6303

15PF

5%

50V

CERM

402

AUD_LI_REF

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

OUT 55

CRITICAL

C6312

3.3UF

1 2

10%

10V

CERM-X5R

805-1

1 R6312

16.5K

1%

1/16W

2

MF-LF

402

CRITICAL

C6311

3.3UF

1 2

10%

10V

CERM-X5R

805-1

1

2

CRITICAL

NOSTUFF

C6313

15PF

5%

50V

CERM

402

AUD_LI_P_R

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

OUT 55

A

8

7 6 5 4 3

2 1

AUDIO: LINE INPUT FILTER








SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

56

OF

97

2 1

D

C

B

A

D

8 7 6 5 4 3 2 1

D

C

B

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

55

IN

NC

AUD_HP_PORT_L

AUD_HP_ZOBEL_L

CRITICAL

C6500

0.1UF

10%

16V

X7R-CERM

402

1

2

R6501

0

1 2

5%

1/10W

MF-LF

603

NO STUFF

CRITICAL

C6501

0.0022UF

10%

50V

CERM

402

1

2

R6500

1

39

5%

1/16W

MF-LF

402

2

59 55

IN

GND_AUDIO_HP_AMP

R6510

1

39

5%

1/16W

MF-LF

402

2

NC AUD_HP_ZOBEL_R

CRITICAL

C6510

0.1UF

10%

16V

X7R-CERM

402

1

2

AUD_HP_PORT_R

55 IN

NO STUFF

CRITICAL

C6511

0.0022UF

10%

50V

CERM

402

R6511

1

0

5%

1/10W

MF-LF

603

2

1

2

AUD_HP_L

OUT

59

1 R6502

2.21K

1%

1/16W

2

MF-LF

402

1 R6512

2.21K

1%

1/16W

2

MF-LF

402

AUD_HP_R

OUT 59

C

B

A

8

7 6 5 4 3

AUDIO: HEADPHONE FILTER

SYNC_MASTER=AUDIO SYNC_DATE=03/16/2009


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

57

OF

97

2 1

D

C

8 7 6 5 4

58 9

PP5V_S3_AUDIO_AMP

3X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500

GAIN = 6DB

1ST ORDER FC (L&R) = 120 HZ +/- 30%

1ST ORDER FC (SUB) = 58HZ +/- 30%

55

55

55

IN

IN

IN

L6610

FERR-1000-OHM

CRITICAL

CRITICAL

C6610

0.033UF

1 2 AUD_LO2_P_L 1 2 AUD_SPKRAMP_INP_L

0402

L6611

FERR-1000-OHM

NO_TEST=TRUE

CRITICAL

AUD_LO2_N_L 1 2 AUD_SPKRAMP_INN_L

L6601 0402

FERR-1000-OHM

CRITICAL

NO_TEST=TRUE

AUD_GPIO_3 1 2

CRITICAL

C6611

0.033UF

1 2

10%

16V

X5R

402

10%

16V

X5R

402

0402

58

AUD_SPKRAMP_SHUTDOWN_L

R6601 1

100K

5%

1/16W

MF-LF

402

2

CRITICAL

C6612

47UF

20%

6.3V 2

TANT-POLY

CASE-A4

1

SSM2315L_P

SSM2315L_N

PLACE C6610 CLOSE TO VDD PIN

1

2

CRITICAL

C6613

0.1UF

10%

16V

X5R

402

C1

A1

C2

VDD PVDD

IN-

U6610

SSM2315

WLCSP

OUT+

IN+ OUT_

CRITICAL

SD*

GND

C3

A3

SPKRAMP_L_OUT_P

SPKRAMP_L_OUT_N

58 96

58 96


58 9

PP5V_S3_AUDIO_AMP

L6620

FERR-1000-OHM CRITICAL

55

IN

55 IN

58

AUD_LO2_P_R

AUD_LO2_N_R 1

1

0402

L6621

FERR-1000-OHM

0402

2

2 AUD_SPKRAMP_INP_R

NO_TEST=TRUE CRITICAL

CRITICAL

AUD_SPKRAMP_INN_R

C6621

0.033UF

1 2

NO_TEST=TRUE

10%

16V

X5R

402


CRITICAL

C6620

0.033UF

1 2 SSM2315R_P

SSM2315R_N

10%

16V

X5R

402

CRITICAL

C6622

47UF

20%

6.3V

TANT-POLY

CASE-A4

1

2

C1

A1

C2

VDD PVDD

IN-

U6620

SSM2315

WLCSP

OUT+

IN+ OUT_

SD*

CRITICAL

GND

C3

A3

1

2

CRITICAL

C6623

0.1UF

10%

16V

X5R

402

SPKRAMP_R_OUT_P

SPKRAMP_R_OUT_N

58 96

58 96

B


58 9

PP5V_S3_AUDIO_AMP

55

IN

55

IN

CRITICAL

C6632

100UF

20%

6.3V

TANT

CASE-AL1

1

2

58

AUD_LO1_P_R

AUD_LO1_N_R

CRITICAL

L6630

FERR-1000-OHM

CRITICAL

1 2 AUD_SPKRAMP_INP_SUB

1

L6631

0402

FERR-1000-OHM

2

NO_TEST=TRUE

CRITICAL

AUD_SPKRAMP_INN_SUB

CRITICAL

C6631

0.068UF

1 2

C6630

0.068UF

1 2

10%

10V

CERM

402

0402 NO_TEST=TRUE

10%

10V

CERM

402


SSM2315S_P

SSM2315S_N

C1

A1

C2

VDD PVDD

IN-

U6630

SSM2315

WLCSP

OUT+

IN+ OUT_

CRITICAL

SD*

GND

C3

A3

1

2

CRITICAL

C6633

0.1UF

10%

16V

X5R

402

SPKRAMP_S_OUT_P

SPKRAMP_S_OUT_N

58 96

58 96

A

8

7 6 5 4

3 2 1

D

SPEAKER CHECKPOINTS



96 58

SPKRAMP_L_OUT_P



96 58

SPKRAMP_L_OUT_N

R6610

0

2 1

5%

1/16W

MF-LF

402

R6611

0

2 1

5%

1/16W

MF-LF

402



SPKRCONN_L_OUT_P

OUT

7 59 96



SPKRCONN_L_OUT_N

OUT

7 59 96



96 58

SPKRAMP_R_OUT_P



96 58

SPKRAMP_R_OUT_N

R6620

0

2 1

5%

1/16W

MF-LF

402

R6621

0

2 1

5%

1/16W

MF-LF

402



SPKRCONN_R_OUT_P

OUT 7 59 96



SPKRCONN_R_OUT_N

OUT

7 59 96



96 58

SPKRAMP_S_OUT_P


96 58


SPKRAMP_S_OUT_N

R6630

0

2 1

5%

1/16W

MF-LF

402

R6631

0

2 1

5%

1/16W

MF-LF

402



SPKRCONN_S_OUT_P

OUT 7 59 96



SPKRCONN_S_OUT_N

OUT 7 59 96

C

B

3

AUDIO: SPEAKER AMP



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

58

OF

97

2 1

8 7 6 5 4 3 2 1

D

96 85 84

22 21

69 68 63

47 45

19 18

43

13 8

60

39

7 6

PP3V3_S0

37 29 28

59 55 51

82 81 80

25 24

49 48

77 70

APN: 514-0671

C

J6700

SPDIF-TXRX-K24

F-RT-TH

MIC

DETECT

SWITCH

LEFT

RIGHT

GND

AUDIO

A - VIN

B - VCC

C - GND

OPERATING VOLTAGE 3.3

POF

7

8

9

SHELL

SHIELD

PINS

10

11

12

13

1

3

4

6

5

2

84 82 81 80

49 48 47 45

77

43 PP3V3_S0

39

19

37 29

18 13

28 25

8

24

7

22

6

21

70 69 68 63 60 59 55 51

96 85

B

A

APN: 514-0635

J6750

AUDIO-RCVR-M97

F-RT-TH5

DETECT FOR PLUG TYPE 5

SWITCH 2

LEFT

RIGHT

GROUND

1

3

4

AUDIO

A - VDD

B - GND

C - VOUT

OPERATING VOLTAGE 3.3

POF

6

7

8

SHELL

SHIELD

PINS

9

10

11

12

8

AUDIO JACK 1 LO/HP JACK, SPDIF TX

1

2

1

2

0.1UF

10%

16V

X5R

402

1UF

10%

10V

X5R

402-1

AUD_CONNJ1_SLEEVE2

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_TIPDET

AUD_CONNJ1_TIP

AUD_CONNJ1_RING

AUD_CONNJ1_SLEEVE

C6700

C6750

1

2

C6701

2.2UF

20%

6.3V

CERM

402-LF

AUD_J2_OPT_OUT

GND PATCH

59 9


R6749

4.7

1 2

5%

1/16W

MF-LF

402

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_TIPDET

AUD_CONNJ2_RING

AUD_CONNJ2_TIP

AUD_CONNJ2_SLEEVEDET

CRITICAL

DZ6703

6.8V-100PF

402

2

1



VOLTAGE=0V

2

1

2

1

CRITICAL

DZ6704

6.8V-100PF

402

CRITICAL

DZ6706

6.8V-100PF

402

2

1

XW6701

SM

1 2

XW6702

SM

1 2

R6701

0

1 2

5%

1/16W

MF-LF

402

2

1

CRITICAL

DZ6700

6.8V-100PF

402

CRITICAL

DZ6701

6.8V-100PF

402

AUD_SPDIF_OUT

IN

55

1

2

L6703


1 2

0402

L6702


HS_MIC_HI

OUT

1 2 AUD_HP_R

0402

CRITICAL

L6706

FERR-220-OHM

1 2 AUD_HP_L

0402

R6700

10K

1 2 AUD_J1_SLEEVEDET_R

5%

1/16W

MF-LF

402

L6705


1 2 AUD_J1_TIPDET_R

0402

BI

BI

OUT

OUT

60

1 2 HS_MIC_LO

OUT 60

0402

L6707

CRITICAL

FERR-220-OHM

2 AUD_HP_PORT_REF 1

CRITICAL

L6701

FERR-220-OHM-2.5A

1 2

0603

0402

CRITICAL

L6704

FERR-220-OHM

GND_AUDIO_HP_AMP

BI

OUT 55 57

55

57

57

60

60

1

2

C6705

100PF

5%

50V

CERM

402


9 59

CRITICAL

DZ6754

6.8V-100PF

CRITICAL 402

DZ6756

6.8V-100PF

402

2

1

2

CRITICAL

DZ6758

6.8V-100PF

402

CRITICAL

DZ6751

6.8V-100PF

402

2

1

1

2

AUD_SPDIF_IN

OUT 55

L6751

FERR-220-OHM

1 2

0402

CRITICAL

L6754

FERR-1000-OHM

CRITICAL

1 2

0402

CRITICAL

L6756

FERR-1000-OHM

1 2

0402

CRITICAL

L6758

FERR-220-OHM

1 2

1

0402

CRITICAL

L6752

FERR-1000-OHM

2

0402

AUD_LI_R

AUD_LI_L

AUD_J2_TIPDET_R

BI

BI

AUD_LI_GND

56

56

56

OUT 60

C6756

100PF

5%

50V

CERM

402

1


9 59

AUDIO JACK 2 LINE IN JACK, SPDIF RX

7 6 5 4 3

MIC CONNECTOR

APN: 518S0520

60 7 OUT

60 7 OUT

60 7

OUT

BI_MIC_LO

BI_MIC_SHIELD

BI_MIC_HI

CRITICAL

J6780

78171-0003

M-RT-SM

4

1

2

3

5

SPEAKER CONNECTOR

96 58 7

IN

96 58 7 IN

SPKRCONN_L_OUT_P

SPKRCONN_L_OUT_N

96 58 7 IN

96 58 7 IN

96 58 7 IN

96 58 7

IN

SPKRCONN_S_OUT_P

SPKRCONN_S_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

NOSTUFF

CRITICAL

C6781

33PF

5%

50V

CERM

402

1

2

APN: 518S0519

APN: 518S0521

NOSTUFF

CRITICAL

1

2

C6783

33PF

NOSTUFF

CRITICAL

5%

50V

CERM

402

C6782

33PF

5%

50V

CERM

402

1

2

NOSTUFF

1

2

CRITICAL

C6784

33PF

5%

50V

CERM

402

CRITICAL

J6781

78171-0002

M-RT-SM

3

1

2

4

CRITICAL

J6782

78171-0004

M-RT-SM

5

1

2

3

4

6

D

C

B

AUDIO: JACKS



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

59

OF

97

2 1

D

C

B

8 7

CODEC OUTPUT SIGNAL PATHS

FUNCTION

HP/LINE OUT

SATELLITES

SUB

SPDIF OUT

VOLUME

0X02 (2)

0X04 (4)

0X03 (3)

N/A

CONVERTER

0X02 (2)

0X04 (4)

0X03 (03)

0X08 (8)

CODEC INPUT SIGNAL PATHS

FUNCTION

LINE IN

SPDIF IN

BUILT-IN MIC

HEADSET MIC

CONVERTER

0X05 (5)

0X07 (7)

0X06 (6)

0X06 (6)

6

PIN COMPLEX

0X09 (9,A)

0X0B (11)

0X0A (10)

0X10 (16)

MUTE CONTROL

N/A

GPIO_3

GPIO_3

N/A

DET ASSIGNMENT

0X09 (A)

N/A

N/A

0X0C (B)

PIN COMPLEX

0X0C (12,C)

0X0F (15)

0X0D (13,B,RIGHT)

0X0D (13,V22,B,LEFT)

VREF

N/A

N/A

MIC_BIAS (80%)

MIKEY

DET ASSIGNMENT

0X0C (12,C)

N/A

N/A

MIKEY

5

PORT A DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE)

60 55

OUT

AUD_SENSE_A

60

PP3V3_S0_AUDIO_F

1 R6801

220K

2

5%

1/16W

MF-LF

402

APN:376S0613

AUD_OUTJACK_INSERT_L

Q6800

SSM6N15FEAPE

SOT563

D 3

60 59

IN

AUD_J1_TIPDET_R

R6802

47K

1

5%

1/16W

MF-LF

402

2 AUD_J1_DET_RC

5

1

2

C6801

0.1UF

20%

CERM

10V

402

G S

4

60 56 55

GND_AUDIO_CODEC

60

PP3V3_S0_AUDIO_F

1 R6804

AUD_J1_SLEEVEDET_R

220K

2

5%

1/16W

MF-LF

402

R6803

1

220K

2 AUD_J1_SLEEVEDET_INV

5%

1/16W

MF-LF

402

Q6800

SSM6N15FEAPE

SOT563

D 6

60 59 IN

60 56 55

GND_AUDIO_CODEC

1

2

C6802

0.01UF

10%

16V

CERM

402

2 G S

1

Q6801

SSM6N15FEAPE

SOT563

5 G

D 3

1 R6806

39.2K

2

1%

1/16W

MF-LF

402

AUD_PORTA_DET_L

S

4

NC

Q6801

SSM6N15FEAPE

SOT563

60 59

AUD_J1_SLEEVEDET_R

2 G S

1

D 6

1 R6805

20.0K

1%

1/16W

MF-LF

2

402

AUD_PORTB_DET_L

NC

8

60

PP3V3_S0_AUDIO_F

EXTRACT_BUFF

R6865

R6864

100K

220K

2

1

EXTRACT_BUFF

1 AUD_J1_TIPDET_INV

5%

1/16W

MF-LF

402

2

60

5%

1/16W

MF-LF

402

EXTRACT_BUFF

Q6803

D 6 SSM6N15FEAPE

EXTRACT_BUFF SOT563

R6860

15K

59

AUD_J1_TIPDET_R 1 2 TIPDET_FILT

EXTRACT_BUFF

Q6803

SSM6N15FEAPE

SOT563

D

5%

1/16W

MF-LF

402

1

2

C6860

0.1UF

20%

CERM

10V

402

2 G

EXTRACT_BUFF

S

1

S

3

4

60 56 55

GND_AUDIO_CODEC

5 G

A

80 77

28 25

70

24

69 68

22 21

63 60

19 18

59

13 8

55

7 6

51 49 48 47 45

96

43 39 37

85 84 82

29

81


IN

60


EXTRACTION NOTIFICATION

PP3V3_S0_AUDIO_F

VOLTAGE=3.3V

CRITICAL

L6862

FERR-1000-OHM

APN:353S2401

EXTRACT_DEBOUNCE

PP3V3_S0 1 2

0402

60 59

AUD_J1_TIPDET_R

C6861

0.1UF

10V 20%

402 CERM

1

2

5

TPS3801E18DCK

4

VDD

U6860

MR* RST*

SC-70-1

GND

3

1 2

60 56 55

GND_AUDIO_CODEC

PLACE L6800/C6800 CLOSE TO U6800

7

R6861

100

2

5%

1/16W

MF-LF

402

AUD_IP_PERIPHERAL_DET

OUT

17

6 5

4 3 2 1

82

28

81 80

25 24

77

22

70

21

69 68

19 18

63

13

60 59

8 7 6

PP3V3_S0

55 51 49 48 47 45 43 39

96

37 29

85 84

PULLUPS ON MCP PAGE

PORT B LEFT(HEADSET MIC)

CRITICAL HP=80HZ, LP=8.82KHZ

MIKEY MIN_LINE_WIDTH=0.1MM

L6880

FERR-1000-OHM


VOLTAGE=3.3V

1 2 PP3V3_S0_HS_RX

DRC MIKEY

0402

SMBUS_MCP_1_CLK

CRITICAL

MIKEY

C6880

10UF

6.3V

20%

603 X5R

1

2

6

SCL

APN:353S2256

AVDD

MIKEY

U6880

CD3275

DRC

MICBIAS

1 HS_MIC_BIAS

91 85 45 21 IN

SMBUS_MCP_1_DATA 5 2 HS_SW_DET

91 85 45 21

BI

SDA DETECT

AUD_I2C_INT_L 7

INT* BYPASS

10 HS_RX_BP

21 OUT

AUD_IPHS_SWITCH_EN 8

19

IN

ENABLE

GND THM

MIKEY

R6880 1

100K

5%

1/16W

MF-LF

402

2

55 OUT

55

OUT

AUD_MIC_INP_L

AUD_MIC_INN_L

MIKEY

CRITICAL

C6886

0.1UF

1 2

MIKEY

CRITICAL

C6883

0.1UF

1 2

10%

25V

X5R

402

60 56 55

GND_AUDIO_CODEC

10%

25V

X5R

402

XW6880

1

SM

2

MIKEY

HS_MIC_HI_RC

1

C6881

0.01UF

16V 10%

402 CERM

MIKEY

2

R6881 1

MIKEY

1K

1%

1/16W

MF-LF

402

2

R6884

1

2.2K

2

MIKEY

1 R6883

2

100K

5%

1/16W

MF-LF

402

1

2

MIKEY

5%

1/16W

MF-LF

402

C6884

0.0082UF

10%

X7R

25V

402

CRITICAL

MIKEY

1 R6882

2.2K

2

5%

1/16W

MF-LF

402

MIKEY

CRITICAL

1

2

C6882

2.2UF

20%

6.3V

TANT

402

GND_AUDIO_CODEC

55 56 60

HS_MIC_HI

IN 59

1

MIKEY

2

C6885

27PF

5%

CERM

50V

402

CRITICAL

HS_MIC_LO

IN

59

D

C

PORT B RIGHT(BUILT-IN MIC)

55

IN

AUD_CODEC_MICBIAS

R6850

100

1

1%

1/16W

MF-LF

402

2

60 56 55

GND_AUDIO_CODEC

55 OUT

AUD_MIC_INP_R

55 OUT

AUD_MIC_INN_R

CRITICAL

C6850

0.1UF

1 2

CRITICAL

C6851

0.1UF

10%

25V

X5R

402

1 2

MIC_BIAS_FILT

R6851

2.4K

1 2

CRITICAL

1

2

C6852

2.2UF

20%

6.3V

TANT

402

1%

1/16W

MF

402-1

1

BI_MIC_HI_F

R6852

100K

2

5%

1/16W

MF-LF

402

C6853

0.001UF

50V 10%

402 CERM

BI_MIC_LO_F

2

60 56 55

GND_AUDIO_CODEC

XW6851

1

SM

2

10%

25V

X5R

402

R6853

2.4K

1 2

1%

1/16W

MF

402-1

L6850

FERR-1000-OHM

1 2 BI_MIC_HI

0402

1

2

CRITICAL

C6854

27PF

5%

CERM

50V

402

L6851

FERR-1000-OHM

1 2 BI_MIC_LO

0402

BI_MIC_SHIELD

HP=80HZ

IN 7 59

IN 7 59

IN

7 59

B

PORT C DETECT (LINE-IN)

60 55

OUT

AUD_SENSE_A

59

IN

60

PP3V3_S0_AUDIO_F

AUD_J2_TIPDET_R

R6813

10K

1

1%

1/16W

MF-LF

402

2 1 R6811

270K

2

5%

1/16W

MF-LF

402

Q6802

SSM3K15FV

SOD-VESM-HF

R6812

47K

1 2

5%

1/16W

MF-LF

402

AUD_J2_DET_RC

1

2

C6811

0.1UF

20%

CERM

10V

402

1 G

60 56 55

GND_AUDIO_CODEC

D 3

S

2

APN:376S0612

4 3







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

60

OF

97

2

AUDIO: JACK TRANSLATORS



A

1

D

C

B

A

8 7 6 5 4 3 2 1

MagSafe DC Power Jack

CRITICAL

J6900

78048-0573

M-RT-SM

PWR

PWR

GND

GND

SIG

1

2

3

4

5

7

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=1mm


VOLTAGE=18.5V

CRITICAL

1

F6905

6AMP-24V

2

1

2

1206-2

C6905

0.01UF

20%

50V

CERM

603

PLACEMENT_NOTE=Place near L6900

42 BI

SC-75

RCLAMP2402B

D6900

CRITICAL

NO STUFF

SYS_ONEWIRE

SMC_BC_ACOK_VCC

1 R6929

2.0K

5%

2

1/16W

MF-LF

402

VCC

4

INT

U6900

MAX9940

SC70-5

EXT

CRITICAL

5

GND NC

NC

1-Wire OverVoltage Protection

7

ADAPTER_SENSE

The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is connected.

PP3V42_G3H

5

TC7SZ08AFEAPE

SOT665

2

A

4

Y U6901

1

B

3

1

2

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

C6908

0.1UF

20%

10V PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

CERM

402

SMC_BC_ACOK

IN 42 43 62

PPDCIN_G3H

50 43 42

OUT

SMC_LID

45 44 43 42 40

69

26 22

64 62

21 8

61 50

7

PP3V42_G3H

46

C6951

0.1UF

10%

25V

X5R

402

1

2

2

402

R6961

100

5%

MF-LF

1

1/16W

C6955

0.001UF

10%

50V

CERM

402

1

2

7

SMC_LID_R

94 62

45 42 7

61

94

45 42

62 61

7

BI

BI

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

C6953

47PF

5%

50V

CERM

402

1

2

C6952

47PF

5%

50V

CERM

402

1

2

BIL CONNECTOR

516S0523

CRITICAL

J6955

CPB6312-0101F

F-ST-SM

14 13

NC

2

10

12

4

6

8

1

3

5

7

9

11

NC

16 15

SMC_BIL_BUTTON_L

C6954

0.001UF

10%

50V

CERM

402

1

2

TO SMC

OUT 7 42 43

8 61 62

62 61 8

PPDCIN_G3H

R6905

47

1 2

5%

1/8W

MF-LF

805

79 67 66 65 64 62 46 37 8 7

86 83

PPDCIN_S5_P3V42G3H



VOLTAGE=18.5V

PPBUS_G3H

518-0358

CRITICAL

J6950

BAT-K19

M-RT-TH

1

2

P1

P2

P3

P4

P5

P6

P7

P8

P9

3

4

5

6

7

8

9

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

10

11

12

13

BATTERY CONNECTOR

SMBUS_SMC_BSA_SCL

7

SYS_DETECT_L

SMBUS_SMC_BSA_SDA

CRITICAL

D6950

RCLAMP2402B

SC-75

PPVBAT_G3H_CONN

7 62

7 42 45 61 62 94

7

42 45 61 62 94

R6950

1

10K

5%

1/16W

MF-LF

402

2

C6950

0.1UF

10%

25V

X5R

402

1

2

GND

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

D6905

HN2D01JEAPE

SOT665

1 5

3 4

NC

2

NC

PPVIN_G3H_P3V42G3H



VOLTAGE=18.5V

C6990 1

10UF

10%

25V

X5R 2

805

NC

8

7

VIN BOOST

U6990

LT3470A

DFN

SHDN*

CRITICAL

SW

BIAS

NC

GND

FB

THRM

PAD

1

4

2

P3V42G3H_BOOST

C6994

0.22UF

20%

6.3V

X5R

402

1

2

P3V42G3H_SW



SWITCH_NODE=TRUE DIDT=TRUE

CRITICAL

L6995

33UH

1 2

CDPH4D19FHF-SM

C6995

22pF

5%

50V

CERM

402

1

2

P3V42G3H_FB

<Ra>

1

R6995

348K

1%

1/16W

2

MF-LF

402

<Rb>

1

R6996

200K

1%

1/16W

2

MF-LF

402

PP3V42_G3H

Vout = 3.425

250mA max output

(Switcher limit)

1

2

C6999

22UF

20%

6.3V

X5R-CERM

603

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

Vout = 1.25V * (1 + Ra / Rb)

8

7 6 5 4 3

D

C

B

DC-In & Battery Connectors



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

61

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

A

FROM ADAPTER

61 8

PPDCIN_G3H

2

1

D7005

1SS418

SOD-723-HF

Inrush Limiter

1

R7060

470K

2

5%

1/16W

MF-LF

402

0.1UF

10%

25V

X5R 2

402

CHGR_AGATE_DIV



1

R7061

330K

2

5%

1/16W

MF-LF

402

C7060 1

4

G

1 2 3

S

D

5 6 7 8

CRITICAL CRITICAL

Q7060 Q7065

HAT1128R01

SOI HAT1128R01

SOI

PPDCIN_S5_INRUSH



VOLTAGE=18.5V

8

3

7

2

6

S

D

1

5

Reverse-Current Protection

PPDCIN_S5_CHGR_R



VOLTAGE=18.5V

G

4

R7065

1

100K

5%

1/16W

MF-LF

402

2

CHGR_SGATE_DIV



R7066

1

62K

5%

1/16W

MF-LF

402

2

CHGR_SGATE



U7070

TL331

SOT23-5

4

5

VCC

GND

2

1

3

1

2

C7070

0.1uF

10%

16V

X5R

402

R7070 1

57.6K

1%

1/16W

MF-LF

402

2

SGATE_P0V1_VREF

R7071 1

1.82K

1%

1/16W

MF-LF

402

2

3 D Q7074

SSM6N15FEAPE

SOT563

4

S G 5

AMON_CLAMP

R7010

1

30.1K

1%

1/16W

MF-LF

402

2

R7011

1

9.31K

1%

1/16W

MF-LF

402

2

45 44 43 42 40

69

26 22

64 62

21

61

8

50

7

46

PP3V42_G3H

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.07V

Input impedance of ~40K meets sparkitecture requirements

1

R7015

56.2K

2

1%

1/16W

MF-LF

402

1

2

94 61 45 42 7 IN

94 61 45 42 7

BI

CHGR_VCOMP_R

C7015

0.001UF

10%

50V

CERM

402

R7016 1

3.01K

1%

1/16W

MF-LF

402

2

CHGR_VNEG_R

C7016

470PF

10%

50V

CERM

402

1

2

CHGR_ICOMP

CHGR_VCOMP

CHGR_VNEG

94

CHGR_CSO_P

94

CHGR_CSO_N

1

2

C7002

1UF

10%

10V

X5R

402-1

C7050

0.1uF

10%

16V

X5R

402

1

2

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

VREF = 3.2V, < 300uA

CHGR_ACIN

62

PP5V1_CHGR_VDD



VOLTAGE=5.1V

30mA max load

NC

R7001

4.7

1

5%

1/16W

MF-LF

402

2

12

11

10

VDD VDDP

CRITICAL

VHST AGATE

U7000

SCL CSIP

QFN

SDA CSIN

4

3

VREF

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

1

28

27

OMIT

BGATE

DCIN

16

2

BOOT

UGATE

PHASE

25

24

23

20V/V

LGATE

(OD) TRKL*

AMON

32V/V

(OD)

BMON

ACOK

21

13

9

15

14

XW7000

SM

1 2

(CHGR_AGATE)

(CHGR_DCIN)

PP5V1_CHGR_VDDP



VOLTAGE=5.1V

C7001

1UF

10%

10V

X5R 2

402-1

1

CHGR_AGATE

94

CHGR_CSI_P

94

CHGR_CSI_N

CHGR_BGATE

CHGR_DCIN

CHGR_BOOT

CHGR_UGATE

CHGR_PHASE

CHGR_LGATE

TP_CHGR_TRKL

CHGR_AMON

CHGR_BMON

SMC_BC_ACOK

OUT

OUT

OUT

46 62

46

42 43 61

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

1

2

C7020

0.047UF

10%

10V

CERM

402

R7021

10

1 2

5%

1/16W

MF-LF

402

96

CHGR_CSI_R_P

4

3

CRITICAL

1

2

R7020

0.02

0.5%

1W

MF

0612-1

PPDCIN_S5_FET_CHGR



VOLTAGE=18.5V

CRITICAL

1

2

C7030

22UF

20%

25V

POLY-TANT

CASE-D2-SM

NOSTUFF

D7040

1 2

1SS418

SOD-723-HF

1

CRITICAL

F7040

8AMP-24V

1206-2

C7022

0.1UF

10%

25V

X5R

402

1

2

R7022

10

1 2

5%

1/16W

MF-LF

402

1

2

C7021

0.1UF

10%

25V

X5R

402

96

CHGR_CSI_R_N

CRITICAL

1

2

C7031

22UF

20%

25V

POLY-TANT

CASE-D2-SM

2

5

1

2

C7035

0.1UF

10%

25V

X5R

402

4

1 2 3

CRITICAL

Q7030

RJK0305DPB

LFPAK-HF

3

1

2

C7032

1UF

10%

25V

X5R

603-1

CRITICAL

L7030

4.7UH-10.2A

1

2

C7033

1UF

10%

25V

X5R

603-1

1

2

C7034

0.001UF

10%

50V

X7R

402

DIDT=TRUE



SWITCH_NODE=TRUE

DIDT=TRUE

DIDT=TRUE

Max Current = 8.5A

(L7030 limit) f = 400 kHz

4

R7051

1

10

5%

1/16W

MF-LF

402

2

5

1 2 3

1

CRITICAL

Q7035

FDA1254F-SM

RJK0305DPB

LFPAK-HF

152S0542

2 PPVBAT_G3H_CHGR_REG



VOLTAGE=12.6V

CRITICAL

CRITICAL

R7050

0.01

2

0.5%

1W

MF

0612-1

1

C7040

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

96 46

CHGR_CSO_R_P

4 3

PPVBAT_G3H_CHGR_R



VOLTAGE=12.6V

C7055

1UF

10%

25V

X5R

603-1

1

2

1

C7057

0.01uF

10%

16V

CERM

402

2

C7056

0.1UF

10%

16V

X5R

402

R7052

10

1 2

96

46

CHGR_CSO_R_N

5%

1/16W

MF-LF

402

1

2

1

2

C7041

0.001UF

10%

50V

X7R

402

CRITICAL

Q7055

SI7137DP

SO-8

PP3V42_G3H

1 R7074

1M

2

5%

1/16W

MF-LF

402

CHGR_AMON

46 62

R7075 clamps CHGR_AMON when charger is not powered to counter TL331 bias current.

6 D

PPVBAT_G3H_CONN

7 61



VOLTAGE=12.6V

7 8 21 22 26 40 42 43 44 45 46

50 61 62 64 69

Q7074

SSM6N15FEAPE

SOT563

1

S G 2

PP5V1_CHGR_VDD

62

TO SYSTEM

PPBUS_G3H

7 8 37 46 61 64 65 66 67 79 83

86

1

2

C7042

0.033UF

10%

16V

X5R

402

C7000

1UF

10%

10V

X5R

402-1

1

2

1

2

C7011

0.01UF

10%

16V

CERM

402

C7005

0.1UF

10%

25V

X5R

402

1

2

GND_CHGR_AGND



VOLTAGE=0V

1

2

C7026

0.001UF

10%

50V

CERM

402

PART NUMBER

353S1811

353S1832

QTY

1

1

DESCRIPTION

IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L

IC,ISL6258A,BAT CHARGER,4X4MM,QFN28

REFERENCE DES

U7000

U7000

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

ISL6258

ISL6258A

2S Battery Default

3S Battery Default

8

7 6 5 4 3

D

C

B

PBus Supply & Battery Charger



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

62

OF

97

2 1

8 7 6 5 4 3

D

C

B

A

46 8

PPBUS_CPU_IMVP_ISNS

51 49 44 39

85 83 70

8 7

67 66

PP5V_S0

42

IMVP_VR_ON

R7120

10

1

1%

1/16W

MF-LF

402

2 PPVIN_S5_IMVP6_VIN



VOLTAGE=12.6V

C7196

0.1UF

10%

16V

X5R

402

1

2

84 82 81 80 77 70

49 48 47 45 43 39

21 19 18 13 8 7 6

37

69

29 28

68 60

25

59

24 22

55 51

96 85

PP3V3_S0

12

22

11 10

20 18

67 25 24

9 8

17

7 6

14 13

PPCPUVTT_S0

R7112

10

1 2

1%

1/16W

MF-LF

402

R7121

10

1 2

1%

1/16W

MF-LF

402

88 21

IN

88 43 14 10

OUT

LAYOUT NOTE:

Place R7126 in hot

PM_DPRSLPVR

CPU_PROCHOT_L

R7119

499

1 2

1%

1/16W

MF-LF

402

R7198

0

1 2

5%

1/16W

MF-LF

402

(IMVP6_NTC) spot of reg circuit.

1

CRITICAL

R7126

470K

402

C7105

0.015UF

10%

16V

X7R

402

1

2

2

IMVP6_NTC_R

1

R7108

147K

1%

1/16W

2

MF-LF

402

C7110

0.01uF

10%

16V

CERM

402

R7127 1

4.02K

1%

1/16W

MF-LF

402

2

1

2

PP5V_S0_IMVP6_VDD



VOLTAGE=5V

PP3V3_S0_IMVP6_3V3



VOLTAGE=3.3V

1

2

C7106

0.001UF

10%

50V

CERM

402

IMVP6_VDIFF_RC

R7113 1

1K

1%

1/16W

MF-LF

402

2

R7111

1

255

1%

1/16W

MF-LF

402

2

1

R7109

1K

1%

1/16W

2

MF-LF

402

(IMVP6_FB)

1

2

C7114

470PF

10%

50V

CERM

402

C7113

220PF

10%

50V

X7R-CERM

402

1

2

IMVP6_COMP_RC

R7114

1

97.6K

1%

1/16W

MF-LF

402

2

C7126

1UF

10%

10V

X5R

402-1

1

2

DPRSLPVR

0

0

1

1

1 R7199

68

5%

1/16W

2

MF-LF

402

C7130

0.1uF

10%

16V

X5R

402

1

2

88 9

IN

88 9

IN

88 9 IN

88 9

IN

88 9

IN

88 9 IN

88 9

IN

IMVP6_VID<6>

IMVP6_VID<5>

IMVP6_VID<4>

IMVP6_VID<3>

IMVP6_VID<2>

IMVP6_VID<1>

IMVP6_VID<0>

88 14 10 9 IN

10

IN

46 OUT

CPU_DPRSTP_L

88

IMVP_DPRSLPVR

CPU_PSI_L

IMVP6_IMON

9

OUT

63 IN

26

OUT

TP_IMVP6_CLKEN_L

IMVP_VR_ON_R

VR_PWRGOOD_DELAY

IMVP6_VR_TT_L

IMVP6_NTC

(GND_IMVP6_SGND)

63

IMVP6_SOFT

63

IMVP6_RBIAS

(GND_IMVP6_SGND)

63

IMVP6_VDIFF

63

IMVP6_FB2

63

IMVP6_FB

63

IMVP6_COMP

63

IMVP6_VW

1 R7197

10K

5%

1/16W

2

MF-LF

402

1

2

C7135

4.7UF

20%

6.3V

X5R-CERM

402

20 22 31

43

42

41

40

39

38

37

VID6

VID5

VID4

VID3

VIN VDD PVCC

BOOT1

36

26

U7100

QFN

BOOT2

35

UGATE1

63

IMVP6_BOOT1

63

IMVP6_BOOT2

63

IMVP6_UGATE1

VID2

PHASE1

34

63

IMVP6_PHASE1

VID1

VID0 LGATE1

32

63

IMVP6_LGATE1

PGND1

33

(GND)

ISEN1

24

63

IMVP6_ISEN1

46

45

2

3

DPRSTP*

DPRSLPVR

PSI*

IMON

(PGD_IN)

(ISL9504A)

48

47

44

1

5

6

3V3

CLK_EN*

VR_ON

PGOOD

VR_TT*

NTC

UGATE2

27

63

IMVP6_UGATE2

PHASE2

28

63

IMVP6_PHASE2

LGATE2

30

63

IMVP6_LGATE2

PGND2

29

(GND)

ISEN2

23

63

IMVP6_ISEN2

7

SOFT

4

RBIAS

VSUM

19

8

OCSET

18

VO

16

DROOP

IMVP6_VSUM

63

IMVP6_OCSET

IMVP6_VO

IMVP6_DROOP

13

VDIFF

DFB

17

63

IMVP6_DFB

12

11

10

9

FB2

FB

COMP

VW

VSEN

14

15

RTN

25

NC

GND

21

TPAD

49

C7131

0.01UF

10%

16V

CERM

402

1

2

GND_IMVP6_SGND



VOLTAGE=0V

(IMVP6_VW)

C7107

0.001UF

10%

50V

CERM

402

(IMVP6_COMP)

1

2

1

R7110

2

6.81K

1%

1/16W

MF-LF

402

DPRSTP*

1

1

0

0

PSI*

1

0

1

0

C7127 1

0.22UF

20%

25V

X5R 2

603

XW7100

1

SM

2

C7121

0.22UF

20%

6.3V

X5R

402

1

2

1

2

Operation

2-Phase

1-Phase

1-Phase

1-Phase

C7115

0.22UF

20%

25V

X5R

603

Mode

CCM

CCM

DCM

DCM

1

R7117

1

4.42K

2

1%

1/16W

MF-LF

402

R7118

2

1K

1%

1/16W

MF-LF

402

1

2

C7134

0.068UF

10%

10V

CERM

402

OUT

OUT

63

63

NO STUFF

C7116

0.001uF

10%

50V

CERM

402

1

2

1

2

C7129

180pF

5%

50V

CERM

402

1 R7116

13.3K

1%

1/16W

2

MF-LF

402

(IMVP6_VO)

1 R7115

2

11K

1%

1/16W

MF-LF

402

R7130 1

2.61K

1%

1/16W

MF-LF

402

2

IMVP6_VO_R

C7128

0.22UF

10%

6.3V

CERM-X5R

402

1

2

1

CRITICAL

R7131

10KOHM-5%

0603-LF

2

These caps are for Q7100

C7108

0.001UF

10%

50V

X7R

402

1

2

CRITICAL

C7117

68UF

20%

16V

POLY-TANT

CASE-D2E-SM

1

2

DIDT=TRUE

1

2

C7109

1UF

10%

25V

X5R

603-1 CRITICAL

Q7100

IRF6710

S1

1

D

2

CRITICAL

C7155

68UF

20%

16V

POLY-TANT

CASE-D2E-SM

1

2

5

4 6 G

S

3

DIDT=TRUE

DIDT=TRUE

5 G

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

5 G

C7133

0.01uF

10%

16V

CERM

402

1

2

Place R7131 Between L7100,L7101 and CPU

88 63

IMVP6_VSEN_P

88 63

IMVP6_VSEN_N

1

2

NO STUFF

C7132

0.01uF

10%

16V

CERM

402

R7122

0

1 2

5%

1/16W

MF-LF

402

R7123

0

1

5%

1/16W

MF-LF

402

2

CPU_VCCSENSE_P

IN

11 88

CPU_VCCSENSE_N

IN

11 88

1 2 6

D

7

CRITICAL

Q7101

IRF6795

DIRECTFET-MX

S

3 4

3

4

CRITICAL

Q7102

IRF6710

S1

D

1

2

5

6 G

S

1 2 6

D

7

CRITICAL

Q7103

IRF6795

DIRECTFET-MX

S

3 4

(IMVP6_PHASE1)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

(IMVP6_ISEN2)

(IMVP6_VSUM)

(IMVP6_VO)

63

IMVP6_OCSET

63

63

63

63

63

63

63

63

63

63

IMVP6_VO

IMVP6_DROOP

IMVP6_DFB

IMVP6_SOFT

IMVP6_RBIAS

IMVP6_VDIFF

IMVP6_FB2

IMVP6_FB

IMVP6_COMP

IMVP6_VW

R7160

0

1 2 IMVP_VR_ON_R

5%

1/16W

MF-LF

402


63






















63

63

63

63

63

63

63

88 63

IMVP6_PHASE1

IMVP6_BOOT1

IMVP6_UGATE1

IMVP6_LGATE1

IMVP6_ISEN1

IMVP6_VSUM1

IMVP6_VO1

IMVP6_VSEN_P

















I849

63

63

63

63

63

63

63

88 63

IMVP6_PHASE2

IMVP6_BOOT2

IMVP6_UGATE2

IMVP6_LGATE2

IMVP6_ISEN2

IMVP6_VSUM2

IMVP6_VO2

IMVP6_VSEN_N

















I848

8

7 6 5 4 3

2

C7152

0.001UF

10%

50V

X7R

402

1

2

These caps are for Q7102

CRITICAL

C7153

68UF

20%

16V

POLY-TANT

CASE-D2E-SM

1

2

1

2

C7154

1UF

10%

25V

X5R

603-1

1

CRITICAL

L7100

0.36UH-26A-1.05MOHM

1 2

MPCG1040-SM

XW7103

SM

1 2

63

IMVP6_VSUM1

PPVCORE_S0_CPU

44A MAX CURRENT

XW7104

SM

2 1

63

IMVP6_VO1

C7156

0.001UF

10%

50V

X7R

402

7 8 11 12 46

1

2

R7100

1

10K

1%

1/16W

MF-LF

402

1 R7101

3.65K

1%

1/10W

2

MF-LF

603

2

C7103

0.22UF

1 2

10%

10V

CERM

402

1 R7104

1

2

5%

1/16W

MF-LF

402

CRITICAL

L7101

0.36UH-26A-1.05MOHM

1

1

MPCG1040-SM

XW7101

SM

2

2

XW7102

SM

2 1

63

IMVP6_VSUM2

63

IMVP6_VO2

R7105

1

10K

1%

1/16W

MF-LF

402

1 R7106

3.65K

1%

1/10W

2

MF-LF

603

2

C7104

0.22UF

1 2

10%

10V

CERM

402

1 R7107

2

1

5%

1/16W

MF-LF

402

C7157

0.001UF

10%

50V

X7R

402

1

2

D

C

B

IMVP6 CPU VCore Regulator



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

63

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

A

D

69 42 7

SMC_PM_G2_EN

79 67 66 65 62 61 46 37 8 7

86 83

PPBUS_G3H

C7243

0.001UF

10%

50V

CERM

402

1

2

CRITICAL

C7240

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

1

2

C7241

1UF

10%

25V

X5R

603-1

5 f=365KHz

55 53 51 43 41 40 39 31 9 8 7

PP5V_S3

79 70 65

Vout = 5.0V

CRITICAL

Q7220

STL11NH3LL

PWRFLAT-SM

D

G

10.5A max output

(Q7220 limit)

CRITICAL

C7252

330UF

20%

6.3V 2

POLY-TANT

CASE-D3L-SM1

1 C7250

10UF

20%

10V

X5R

805

1

2

1

2

C7251

0.001UF

10%

50V

CERM

402

S

CRITICAL

L7220 3 2 1

1 2

4.7UH-13A-15MOHM

PCMB104E4R7-SM

NO STUFF

1

R7222

10

5%

1/16W

MF-LF

402

2

CRITICAL

Q7225

STL15N3LLH5

P5VS5_RC

2

XW7220

SM

NO STUFF

C7222 1

100PF

5%

50V

CERM

402

2

1

PLACEMENT_NOTE=Place XW7220 next to L7220.

P5V_S5_REG_XW

1

PATH=I623

R7220

15K

2

5%

1/16W

MF-LF

402

1 R7221

10K

2

1%

1/16W

MF-LF

402

4

2

0

P5VS5_VBST_R

D

S

1

2

3 2 1

G

R7224

C7224

5%

1/16W

MF-LF

402

0.1UF

10%

50V

X7R

603-1

4

PWRFLAT-SM

1

C7200

1UF

10%

25V

X5R

603-1

5









1

2

P5VS5_VBST

1 R7200

86.6K

1%

2

1/16W

MF-LF

402

P5VS5_DRVH

GATE_NODE=TRUE

DIDT=TRUE

P5VS5_LL


P5VS5_DRVL

GATE_NODE=TRUE

DIDT=TRUE

(P5VS5_VO1)

P5VS5_VFB

P5VS5_ENTRIP

GND_P5VP3V3_SGND



VOLTAGE=0V

P5VP3V3_VREG5

P5VP3V3_VREG3

R7264

0

2 1

5%

1/16W

MF-LF

402

P3V3S5_VBST_R

P5VP3V3_VREF

VIN

14

SKIPSEL

VREF

VREG3

8

4

TONSEL

22

VBST1

U7201

QFN

21

TPS51125

DRVH1

20

LL1

VREG5

17

VBST2

9

DRVH2

10

LL2

11

19

DRVL1

24

VO1

2

VFB1

1

ENTRIP1

DRVL2

12

VO2

7

VFB2

5

ENTRIP2

6

VCLK

18

PGOOD

23

GND THRM_PAD

EN0

13

5V3V3_REG_EN

PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.

1

C7203

10UF

20%

6.3V

X5R

603

1

2

2

1

2

C7201

0.22UF

10%

10V

CERM

402

P3V3S5_VBST

C7205

10UF

20%

6.3V

X5R

603

C7264

0.1UF

10%

50V

X7R

603-1



P3V3S5_DRVH

GATE_NODE=TRUE

DIDT=TRUE

P3V3S5_LL


P3V3S5_DRVL

GATE_NODE=TRUE

DIDT=TRUE





(P3V3S5_V02)



1

2

P3V3S5_VFB

P3V3S5_ENTRIP

1

2

NO STUFF

C7208

220PF

5%

25V

CERM

402

1 R7206

75K

2

1%

1/16W

MF-LF

402

CRITICAL

Q7260

FDMS9600S

1

8

MLP

CRITICAL

C7280

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

9 4 3 2

Q1

Q2

7 6 5

10

NO STUFF

R7262 1

10

5%

1/16W

MF-LF

402

2

NO STUFF

C7262

100PF

5%

50V

CERM

402

1

2

C7282

0.001UF

C7281

1UF

10%

25V

X5R

603-1

10%

50V

CERM

402

1

2

1

2

P3V3S5_RC

CRITICAL

L7260

4.7UH-5.5A

1

IHLP2525CZ

2

PLACEMENT_NOTE=Place XW7260 next to L7260.

2

XW7260

SM

1

C7290

10UF

20%

6.3V

X5R

603

1

2 f=460KHz

PP3V3_S5

Vout = 3.3V

5.5A max output

(L7260 limit)

1

2

P3V3_S5_REG_XW

CRITICAL

C7292

150UF-.025-OHM

20%

6.3V

TANT

CASE-B2-SM

1

2

68 69 70

30 34 37

7 8 18 20

22 24 26

38 44 54

82 87 96

C7291

0.001UF

10%

50V

CERM

402

XW7200

1

SM

2

1

PATH=I621

R7260

6.49K

2

1%

1/16W

MF-LF

402

C

B

69 68 67 66

One master PGOOD for both 5V and 3V3

S0_PWR_PGOOD

OUT

1 R7261

10K

2

1%

1/16W

MF-LF

402

Q7210

SSM6N15FEAPE

SOT563

D 6

45 44 43 42 40 26 22 21 8 7

69 62 61 50 46

PP3V42_G3H

1 R7273

100K

2

5%

1/16W

MF-LF

402

PART NUMBER ALTERNATE FOR

PART NUMBER

BOM OPTION

152S0778 152S0693

REF DES

ALL

TABLE_ALT_HEAD

COMMENTS:

Cyntec alternate to MagLayers

TABLE_ALT_ITEM

Q7210

SSM6N15FEAPE

SOT563

D 3

2 G

1 R7210

10K

2

5%

1/16W

MF-LF

402

P5VS3_EN_L

S

1

Q7211

SSM6N15FEAPE

SOT563

5 G

D 3

S

4

69

P3V3S5_EN_L

69

P5VS3_EN

5 G S

4

M99 differences from last sync on 11/01/07 to M88 MLB:

1. L7260 changed from M88 MLB inductors to 152S0693.

2. Q7220 changed to 372S0512. Q7225 changed to 376S0511.

3. U7200 changed to 353S2087.

4. Added R7200, R7220,R7221, R7260,R7261, C7201. 5V / 3.3V Power Supply



A







.

DRAWING NUMBER SIZE

D

051-7892

APPLE INC.

SCALE SHT OF

64

NONE

REV.

97

A.0.0

8

7 6 5 4 3 2 1

D

C

B

8 7 6 5 4 3 2 1

D

70 65 30 29 28 8 7

PP1V8R1V5_S3

1

2

C7355

10UF

20%

6.3V

X5R

603

86 83 79 67

46 37 8 7

66 64 62 61

PPBUS_G3H

CRITICAL

C7330

22UF

20%

25V 2

POLY-TANT

CASE-D2-SM

1

CRITICAL

C7331

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

55 53 51 43 41 40 39 31 9

79

8 7

70 64

PP5V_S3

70 26 9

IN

69

IN

69 OUT

MEM_VTT_EN

DDRREG_EN

TP_DDRREG_PGOOD

27 8

PPVTTDDR_S3

70 29 28 8 7


MIN_LINE_WIDTH=2 mm


CRITICAL

C7360

22UF

20%

6.3V

X5R-CERM

603

1

2

R7305

4.7

1 2

5%

1/16W

MF-LF

402

PP5V_S3_DDRREG_V5FILT



VOLTAGE=5V

C7300

4.7UF

20%

6.3V

CERM

603

1

2

10mA max load

Vout = VDDQSNS/2

XW7360

SM

Vout = VTTREF

1 2 DDRREG_VTTSNS

1

2

CRITICAL

C7361

22UF

20%

6.3V

X5R-CERM

603

C7305

1UF

10%

10V

X5R

402-1

1

2 V5IN V5FILT

6

10

11

13

5

24

COMP

CRITICAL

S3 VTT Enable

S5

PGOOD

VTTREF

VDDQ/VTTREF Enable

VDDQ PGOOD U7300

TPS51116

QFN

SYM (2 OF 2)

VTT

NC

NC

2 VTTSNS

7

12

NC0

NC1

VTTGND THRM_PAD GND

VLDOIN

VDDQSNS 8

MODE 4

VBST 22

DRVH 21

LL 20

DRVL 19

CS 16

VDDQSET 9

PGND CS_GND

DDRREG_VDDQSNS

R7310

10K

1

1%

1/16W

MF-LF

402

2

DDRREG_VBST

DDRREG_DRVH

GATE_NODE=TRUE

DIDT=TRUE

DDRREG_LL

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_DRVL

GATE_NODE=TRUE

DIDT=TRUE

DDRREG_CS

DDRREG_FB

C7350

0.033UF

10%

16V

X5R

402

1

2

GND_DDRREG_SGND



VOLTAGE=0V

2

XW7300

SM

1

DDRREG_CSGND

1

2

C7332

1UF

10%

25V

X5R

603-1

1

2

C7333

0.001UF

10%

50V

X7R

402

(DDRREG_DRVH)



(DDRREG_VBST)



C7325

0.1UF

1 2

10%

50V

X7R

603-1

(DDRREG_LL)



(DDRREG_DRVL)



4

G

4 G

5

ISNS_1V5_S3_P

53 96

OUT

CRITICAL

1

1

D

S

5

2

D

S

2

3

Q7330

SI7110DN

PWRPK-1212-8-HF

3

CRITICAL

L7330

1.0UH-13A-5.6MOHM

1

PCMB065T-SM

2

CRITICAL

Q7335

SI7108DN

PWRPK-1212-8-HF

VOLTAGE=1.5V



PPDDR_S3_REG_R

1

2

CRITICAL

C7340

270UF

20%

2V

TANT

CASE-B4-SM

CRITICAL

C7341

270UF

20%

2V

TANT

CASE-B4-SM

1

2

1

2

C7345

10UF

20%

6.3V

X5R

603

1

2

1

2

XW7331

SM

C7346

0.001UF

10%

50V

X7R

402

XW7330

SM

2

1 2

1

ISNS_1V5_S3_N

2

XW7332

SM

PP1V8R1V5_S3

OUT

Vout = 1.5V

15A max output

(Q7335 limit) f = 400 kHz

XW7345

SM

PLACEMENT_NOTE=Place next to C7345

1

53 96

7 8 28 29 30 65 70

C

PLACEMENT_NOTE=Place next to Q7335

XW7335

SM

1 2 (DDRREG_CSGND)



(DDRREG_VDDQSNS)



(DDRREG_FB)

NO STUFF

C7320

100PF

5%

50V

CERM

402

1

2

1 R7320

15.0K

1%

1/16W

MF-LF

2

402

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

1 R7321

15.0K

1%

1/16W

2

MF-LF

402

<Rb>

B

A

8

7 6 5 4 3

1.5V DDR3 Supply



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

65

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

A

47

MCPCORES0_IMON

21

IN

21

IN

21

IN

MCP_VID<0>

MCP_VID<1>

MCP_VID<2>

R7593

0

1

5%

1/16W

MF-LF

402

2

R7590

0

1 2

5%

1/16W

MF-LF

402

R7592

0

1 2

5%

1/16W

MF-LF

402

R7591

0

1 2

5%

1/16W

MF-LF

402

1

NOSTUFF

R7580

20.0K

1%

1/16W

MF-LF

2

402

1

VOLTAGE=5V



5V_S0_MCPREG_VIN

NOSTUFF

R7581

20.0K

2

1%

1/16W

MF-LF

402

1 R7561

1K

2

5%

1/16W

MF-LF

402

C7550

MCPCORES0_VW

1UF

10%

16V

X5R 2

402

MCPCORES0_RBIAS 1

MCPCORES0_SOFT

MCPCORES0_IMON_R

68

64

67

69

OUT

69

S0_PWR_PGOOD

MCP_VID0_R

MCP_VID1_R

MCP_VID2_R

MCPCORES0_OS0

IN

MCPCORES0_OS1

MCPCORES0_EN

MCPCORES0_FDE

MCPCORES0_VSEN

MCPCORES0_RTN

1

2

28

31

25

26

27

23

24

29

30

32

8

9

4

RBIAS

SOFT

IMON

PGOOD

VID0

VID1

VID2

OFFSET0

OFFSET1

VR_ON

AF_EN

FDE

VSEN

RTN

VW

79 67 65 64 62 61 46 37 8

86

7

PPBUS_G3H

83

R7560

2.2

1 2 PP5V_S0

5%

1/10W

MF-LF

603

VDD

QFN

PVCC

U7500

VIN

UGATE

BOOT

PHASE

LGATE

14

18

17

19

21

1

2

C7562

1UF

10%

16V

X5R

402

CRITICAL

7 8 39 44 49 51

63 67 70 83 85

C7540

68UF

20%

16V

POLY-TANT

CASE-D2E-SM

MCPCORES0_LGATE

(MCPCORES0_LGATE)

4



GATE_NODE=TRUE

DIDT=TRUE

G

1

2

1

2

CRITICAL

C7560

68UF

20%

16V

POLY-TANT

CASE-D2E-SM

1

2

R7565

0

MCPCORES0_UGATE 1 2

MCPCORES0_BOOT

0.2 MM

0.25 MM

5%

1/10W

MF-LF

603

MCPCORES0_PHASE



SWITCH_NODE=TRUE

DIDT=TRUE

4 G

(MCPCORES0_UGATE)



GATE_NODE=TRUE

DIDT=TRUE

S

C7564

0.22UF

1

1 2

0.25 MM

0.2 MM CERM-X7R

10V

603

5%

(MCPCORES0_PHASE)

SWITCHNODE

5

CRITICAL

D

3

Q7560

FDMC8676

POWER33-SM

S

1 2

FDMC8678S

MICROFET3X3

3

C7563

0.001UF

10%

50V

X7R

402

5

D

Q7565

CRITICAL

C7589

0.001UF

10%

50V

X7R

402

2

1

2

C7561

1UF

10%

25V

X5R

603-1

CRITICAL

L7560

1.0UH-17A-5M-OHM

1

NO STUFF

HAHF651R0AP-SM

1 R7589

1

5%

1/10W

2

MF-LF

603

MCPCORE_SNUBBER

2 PPMCPCORE_S0_R



VOLTAGE=1V

1 R7582

20.0K

2

1%

1/16W

MF-LF

402

66 46 24 22 8 7

PPVCORE_S0_MCP_REG

66 46 24 22 8 7

PLACE XW NEAR THE MCP,

CONNECT SENSE LINES TO CLOSEST

MCPCORE AND GND BALL

OF MCP

XW7562

SM

2

OMIT

XW7563

SM

1 2

OMIT

R7566

MCPCORES0_RSEN_P

20

2

1%

1/16W

MF-LF

402

R7568

1

20

MCPCORES0_RSEN_N 2

1%

1/16W

MF-LF

402

1 R7563

100

1%

1/16W

MF-LF

2

402

1

2

1 R7583

20.0K

2

1%

1/16W

MF-LF

402

(MCPCORES0_VSEN)

C7570

0.001UF

10%

50V

X7R

402

(MCPCORES0_RTN)

1

R7571

100

2

1%

1/16W

MF-LF

402

MCPCORES0_COMP

MCPCORES0_FB

MCPCORES0_VDIFF

C7576

0.1UF

10%

16V

X7R-CERM

402

1

2

1 R7572

150K

1%

1/16W

2

MF-LF

402

5 COMP

6

FB

7 VDIFF

PGND VSS

GND_MCPCORES0_AGND

VOLTAGE=0V



1

VO

OCSET

ISP

ISN

ICOMP

THRM_PAD

SM

12 MCPCORES0_VO

3

13

11

MCPCORES0_OCSET

MCPCORES0_ISP

MCPCORES0_ISN

10 MCPCORES0_ICOMP

XW7561

2

R7569

1

11.3K

2

1%

1/16W

MF-LF

402

(MCPCORES0_ISN)

(MCPCORES0_ICOMP)

1 R7573

10K

1%

1/16W

2

MF-LF

402

C7573

47PF

5%

50V

CERM

402

1

2

1

R7575

47.0K

1%

1/16W

2

MF-LF

402

1

2

C7575

47PF

5%

50V

CERM

402

(MCPCORES0_VO)

R7500

100

1 2

1%

1/16W

MF-LF

402

MCPCORES0_ISP_R

CRITICAL

R7525

0.001

1%

1W

MF-1

0612

2 1

4 3

C7566

10UF

20%

4V

X5R

603

1

2

1

2

C7567

10UF

20%

4V

X5R

603

MAX CURRENT: 15.5A

(Q7560 Limit)

PPVCORE_S0_MCP_REG

7 8 22 24 46 66 f = 300 kHz

CRITICAL

1

2

C7565

270UF

20%

2V

TANT

CASE-B4-SM

1

2

C7569

0.001UF

10%

50V

X7R

402

CRITICAL

1

2

C7568

270UF

20%

2V

TANT

CASE-B4-SM

8

C7580

68PF

1

R7577

133K

1 2

5%

50V

CERM

402-1

1%

1/16W

MF-LF

402

7

2

R7578

100

1 2

1%

1/16W

MF-LF

402

(MCPCORES0_VW)

C7579

0.001UF

10%

50V

X7R

402

1

2

C7581

560PF

2

1 R7576

6.98K

2

1%

1/16W

MF-LF

402

(MCPCORES0_COMP)

10%

50V

CERM

402

(MCPCORES0_FB)

C7582

560PF

2

R7579

1

2.21K

2

10%

50V

CERM

402

(MCPCORES0_VDIFF)

1%

1/16W

MF-LF

402

6 5

VID<2:0> VOLTAGE

000 1.05V

001 1.00V

010 0.95V

011 0.90V

100 0.85V

101 0.80V

110 0.75V

111 0.70V

4 3

MCP CORE REGULATOR

D

C

B



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

66

OF

97

2 1

D

C

B

8 7 6 5 4 3 2 1

D

83 70 66 63 51 49 44 39 8 7

85

PP5V_S0

R7601

200

1 2

1%

1/16W

MF-LF

402

PP5V_S0_CPUVTTS0_V5FILT



VOLTAGE=5V

C7601

2.2UF

10%

16V

X5R

603

1

2

69 IN

69 68 66 64

OUT

CPUVTTS0_EN

S0_PWR_PGOOD

(=PPCPUVTT_S0_REG)

CPUVTTS0_VFB

CPUVTTS0_TRIP

1 R7685

8.87K

2

1%

1/16W

MF-LF

402

V5FILT V5DRV

CRITICAL

U7600

TPS51117RGY_QFN14

1 EN_PSV TON 2

6 PGOOD VBST 14

3 VOUT

5 VFB

11 TRIP

GND

DRVH 13

LL 12

THRM_PAD

DRVL 9

PGND

XW7600

1

SM

2

79 66 65 64 62 61 46 37 8 7

86 83

PPBUS_G3H

1

2

C7600

1UF

10%

10V

X5R

402-1

CRITICAL

C7690

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

1

2

C7695

1UF

10%

25V

X5R

603-1

CRITICAL

Q7660

FDMS9600S

MLP

1

9 4 3 2

R7679

226K

CPUVTTS0_TON

CPUVTTS0_VBST

C7680 1



0.1UF

10%

50V

X7R 2

603-1

CPUVTTS0_DRVH

GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM


CPUVTTS0_LL


CPUVTTS0_DRVL



GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM


1

1%

1/16W

MF-LF

402

2

8

Q1

Q2

7 6 5

10

SW

CRITICAL

L7660

2.2UH-8.0A

1

PCMB065T-SM

2

XW7665

SM

2

1

1

CPUVTTS0_VSNS

R7670

8.06K

1%

1/16W

MF-LF

402

2

<Ra>

NO STUFF

C7670

100PF

5%

50V

CERM

402

1

2

PPCPUFSB_ISNS



VOLTAGE=1.05V

R7660

0.002

1%

1W

MF

0612

1 2

3 4

96 47

CPUVTT_ISNS_P

96 47

CPUVTT_ISNS_N

PLACEMENT_NOTE=Place XW7665 next to L7660

1

2

C7665

10UF

20%

6.3V

X5R

603

CRITICAL

C7660

330UF

20%

2.0V

POLY-TANT

B2-SM

1

2

(GND)

1 R7671

20.0K

2

1%

1/16W

MF-LF

402

<Rb>

GND_CPUVTTS0_SGND



VOLTAGE=0V

(CPUVTTS0_VFB)

(=PPCPUVTT_S0_REG)

Vout = 0.75V * (1 + Ra / Rb)

PPCPUVTT_S0

Vout = 1.052V

8A max output

(Q7660 limit?) f = 360 kHz

6 7 8 9 10 11 12 13 14 17 18 20

22 24 25 63

C

B

A

8

7 6 5 4

M99 differences from last sync on 12/03/07 to T18 MLB:

1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.

3

CPU VTT / 1V05 S0 Power Supply



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

67

OF

97

2 1

D

8 7 6 5 4 3 2 1

84 82 81 80 77 70 69 63 60 59

28 25

55

24 22

51 49

21

48

19

47

18 13

45 43

8

39

7 6

37

96

29

85

PP3V3_S0

1.05V S0 PLL LDO

R7743

100

1 2

PP3V3_S0_MCP_PLL_VLDO_BIAS

5%

1/16W

MF-LF

402

C7740

1UF

10%

6.3V

CERM 2

402

1

VOUT = 0.8V * (1 + RA / RB)

69 39 29 28 24 16 12 11 8 7

70

PP1V8R1V5_S0_FET

C7741

1UF

10%

6.3V

CERM

402

1

2

P1V05S0_LDO_SS

NOSTUFF

C7743

0.0022UF

10%

50V

CERM

402

1

2

7

1

2

5

IN0

BIAS

CRITICAL

OUT0

9

10

IN1 OUT1

TPS74701

SON

EN FB

8

SS

U7740

PG

3

GND THRML_PAD

P1V05S0_LDO_FB


<Ra>

1 R7744

1.37K

1%

1/16W

MF-LF

2

402

1

2

C7742

4.7UF

20%

4V

X5R

402

7 8 24

Vout = 1.05V

MAX CURRENT = 0.5A

<Rb>

1 R7745

4.42K

2

1%

1/16W

MF-LF

402

P1V05S0_PGOOD

R7746

0

1 2

5%

1/16W

MF-LF

402

S0_PWR_PGOOD

64 66 67 69

D

C C

B

MCP 1.05V S5 (AUXC) SUPPLY

37 34 30

96 87

26

82

24 22

70 69

20 18

64 54

8 7

44 38

PP3V3_S5

69 IN

PM_G2_P1V05S5_EN

69

P1V05_S5_PGOOD

1

2

CRITICAL

C7750

22UF

20%

6.3V

CERM

805

2

EN

3

POR

4

SKIP

1

VIN

U7750

ISL8009B

DFN

CRITICAL

LX

8

VFB

6

RSI

5

GND THRM_PAD

7 9

1V05S5_SW 1

DIDT=TRUE

1V05S5_FB

CRITICAL

L7770

2.2UH-3.25A

IHLP1616BZ-SM

C7776

47PF

5%

50V

CERM

402

2

1

2

1

2

1

2

<Ra>

R7780

255K

1%

1/16W

MF-LF

402

<Rb>

R7781

806K

1%

1/16W

MF-LF

402

1

2

CRITICAL

C7771

22UF

20%

6.3V

CERM

805

PP1V2R1V05_S5

7 8 22 24 34

Vout = 1.053V

MAX CURRENT = 0.8A

FREQ = 1.6MHZ

VOUT = 0.8V * (1 + RA / RB)

A

8

7 6 5 4 3

Misc Power Supplies



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

68

OF

97

2 1

B

8 7 6 5 4 3 2 1

D

61 50 46 45

26 22 21 8 7

44 43

69

42 40

64 62

PP3V42_G3H

R7802

100K

2 1

5%

1/16W

MF-LF

402

Q7800

SSM3K15FV

SMC_PM_G2_EN

SOD-VESM-HF

64 42 7 IN

R7858

1

100K

5%

1/16W

MF-LF

402

2

PLACEMENT_NOTE=near U4900

1 G

D 3

S

2

3.3V 1,05V S5 ENABLE

P3V3S5_EN_L

OUT 64

1

2

NO STUFF

C7802

0.068UF

10%

10V

CERM

402


R7801

5.1K

2 1

5%

1/16W

MF-LF

402


69

PM_G2_P1V05S5_EN

MAKE_BASE=TRUE

1

2

C7801

0.47UF

10%

6.3V

CERM-X5R

402


C

84 82 42 37 34 21 7

IN

R7878

PM_SLP_S3_L

1

100

2

5%

1/16W

MF-LF

402

R7879

1

100K

5%

1/16W

MF-LF

402

2


S0 ENABLE

(PM_SLP_S3_L)

69 65

Unused PGOOD signal

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

65 69

State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L

Run (S0)

Sleep (S3)

Soft-Off (S5)

Battery Off (G3Hot)

68 69

1

1

1

0

1

1

0

0

0

0

1

0 70 69 43 42 40 21 7 IN

PM_SLP_S4_L

MAKE_BASE=TRUE

R7810 1

100K

5%

1/16W

MF-LF

402

2


S5 rail PWRGD

45 44 43 42 40

69 64 62 61

26 22 21

50 46

8 7

PP3V42_G3H

PP3V3_S5

37 34 30

96 87 82

26

70

24 22

69 68

20 18

64 54

8 7

44 38

CT

C7840

0.1uF

20%

10V

CERM

402

1

2

1 R7840

100K

2

5%

1/16W

MF-LF

402

VDD

5

4

SENSE U7840 RESET*

TPS3808G33DBVRG4

SOT23-6

CT MR*

1

3

TPS3808 MR* HAS INTERNAL PULLUP

GND

RSMRST_PWRGD

42

P1V05_S5_PGOOD

68

C7841

0.001UF

20%

50V

CERM 2

402

1

PM_SLP_S3_L_R

46 69 70

MAKE_BASE=TRUE

2

1

R7880

2

22K

5%

1/16W

MF-LF

402

1

PLACEMENT_NOTE=nearU7500

R7881

33K

5%

1/16W

MF-LF

402


2

1

R7882

2

0

5%

1/16W

MF-LF

402

PLACEMENT_NOTE=nearQ7971

1

R7883

10K

5%

1/16W

MF-LF

402


1 R7884

0

2

5%

1/16W

MF-LF

402

69 66

70 69

P3V3S0_EN

MAKE_BASE=TRUE

87 69

P1V2R1V8S0_EN

MAKE_BASE=TRUE

70 69

MCPDDR_EN

MAKE_BASE=TRUE

69 67

CPUVTTS0_EN

MAKE_BASE=TRUE

MCPCORES0_EN

MAKE_BASE=TRUE

1 C7880

0.47UF

2

10%

6.3V

CERM-X5R

402


1

2

C7881

0.47UF

10%

6.3V

CERM-X5R

402

NO STUFF

1 C7882

0.47UF

2

10%

6.3V

CERM-X5R

402

PLACEMENT_NOTE=nearQ7971

1

2

C7883

0.47UF

10%

6.3V

CERM-X5R

402

PLACEMENT_NOTE=nearU7700 PLACEMENT_NOTE=nearQ7600

1

2

NO STUFF

C7884

0.47UF

10%

6.3V

CERM-X5R

402

3.3V,5V S3 ENABLE

1

2 R7811

5.1K

5%

1/16W

MF-LF

402


1

2

C7810

0.47UF

10%

6.3V

CERM-X5R

402


2

1

R7812

5%

1/16W

MF-LF

402


NO STUFF

1

2

C7812

0.47UF

10%

6.3V

CERM-X5R

402


(PM_S4_STATE_L)

7 21 40 42 43 69 70

69 64

P5VS3_EN

MAKE_BASE=TRUE

69 65

DDRREG_EN

MAKE_BASE=TRUE

P5VS3_EN

DDRREG_EN

OUT

64 69

OUT 65 69

Other S0 RAILS PM_ALL_GFX_PGOOD

IG high

EG PM_ALL_GPU_PGOOD

81

28

80 77

25 24

70 69 68 63

22 21 19 18

60 59

13 8 7 6

PP3V3_S0

55 51 49 48 47 45 43 39 37 29

96 85 84 82

PM_SLP_S3_L_R

OUT 46 69 70

PM_SLP_S3_L_R

OUT 46 69 70

P3V3S0_EN

P1V2R1V8S0_EN

MCPDDR_EN

CPUVTTS0_EN

MCPCORES0_EN

OUT

69 70

OUT

69 87

OUT

69 70

OUT

67 69

OUT

66 69

69 68 67 66 64

69 68 67 66 64

IN

69 68 67 66 64 IN

69 68 67 66 64

IN

S0_PWR_PGOOD

69 68 67 66 64 IN

84 83 69 9

R7892 1

10K

5%

1/16W

MF-LF

402

2

S0_PWR_PGOOD

S0_PWR_PGOOD

S0_PWR_PGOOD

S0_PWR_PGOOD

R7894

1

0

5%

1/16W

MF-LF

402

2

69

68

67

66

64


S0_PWR_PGOOD

MAKE_BASE=TRUE

NO STUFF

R7891

PM_ALL_GPU_PGOOD

0

2

2

ALL_GFX_PGOOD_R 1

5%

1/16W

MF-LF

402


A

B

1

2

PP3V3_S5

C7889

0.1UF

20%

10V

CERM

402

7 8 18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

5

TC7SZ08AFEAPE

SOT665

4 ALL_SYS_PWRGD

OUT 26 42

3

D

C

1.1V GPU ENABLE

82 81 80 77 70 69

B

70 69

26 24

55 51 49 48

37 29 28 25

18 13 8 7 6

PP3V3_S0

EG_PWRSEQ_HW

R7851

10K

1 2 P1V1_GPU_EN_RC

24

47

22 21

45 43

68 63 60

96 85

38 37 34

19

39

96 87

59

84

68

22

64 54

20 18

44

8 7

PP3V3_S5

30

82

EG_PWRSEQ_HW

R7850

1

100K

2

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

EG_PWRSEQ_HW

Q7850

SSM6N15FEAPE

D

SOT563

3

EG_PWRSEQ_HW

R7852

0

5%

1/16W

MF-LF

402


84 83 69

P1V1_GPU_EN

MAKE_BASE=TRUE

5 G S

4

1

2

NO STUFF

C7850

0.022UF

20%

16V

CERM

402


84 IN

R7853 1

100K

5%

1/16W

MF-LF

402

2

EG_PWRSEQ_HW

D 6

SSM6N15FEAPE

SOT563

2 G S

1

8

69

GPU_S0_EN_L

MAKE_BASE=TRUE

7

GPU_S0_EN_L

69

6 5

Graphic MEM ENABLE

81 79 77 76 70 69 8 6

PP3V3_S0GPU

EG_PWRSEQ_HW

R7868

100K

1 5%

MF-LF

1/16W

402

2

GPUVCORE_PGOOD

EG_PWRSEQ_HW

R7869

0

P1V8_S0GPU_EN_RC

1 5%

1/16W

MF-LF

402

2


P1V8_S0GPU_EN

MAKE_BASE=TRUE

69 83 84

79

EG_PWRSEQ_HW

Q7861 D

SSM6N15FEAPE

SOT563

3

NO STUFF

C7869

0.022UF

20%

16V

CERM

402


1

2

5 G S

4

69 70 83 84

81 80 77

28 25 24 22

70 69 68 63

21 19 18

60 59

13 8 7 6

PP3V3_S0

55 51 49 48 47 45 43

96

39

85

37 29

84 82

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT place XW0402 if needed to save trace space for pin 7,8

G96 GPU requires rails to come up in the following order:

1) 1.1V

2) GPU_3.3V

3) GPUVcore

4) GDDR3 1.8V

BOMOPTION: EG

68 39 29 28 24 16 12 11 8 7

70

PP1V8R1V5_S0_FET

APN: 353S2310

C7870

0.1uF

20%

10V

CERM

402

1

2

VDD

U7870

ISL88042IRTEZ

TDFN

V2MON MR*

3

5

6

V3MON

V4MON RST*

1

8

GND THRM_PAD

NC

87 84 70 55 25 18 8 7

PP1V8_S0

GPUVCORE ENABLE

A

70

81

69

79

8

77

6

76

PP3V3_S0GPU

EG_PWRSEQ_HW

R7863

100K

1

5%

1/16W

MF-LF

402

2

EG_PWRSEQ_HW

R7864

0

GPUVCORE_EN_RC

1 5%

1/16W

402

MF-LF

2

84

79 69

GPUVCORE_EN

MAKE_BASE=TRUE


EG_PWRSEQ_HW

Q7861

SSM6N15FEAPE

SOT563

2 G

D 6

S

C7861

0.01UF

10%

16V

CERM

402


1

2

69

GPU_S0_EN_L 1

GPUVCORE_EN

OUT 69 79 84

82 81 80 77 70 69 68 63 60 59

28 25 24 22

55 51 49

21 19 18 13

48 47 45 43

8

39

96

7 6

37 29

85 84

PP3V3_S0

EG_PWRSEQ_HW

R7889 1

100K

5%

1/16W

MF-LF

402

2


83

P1V1GPU_PGOOD

EG_PWRSEQ_HW

R7888

0

P3V3GPU_EN

OUT

5%

MF-LF

1/16W

402

70 84

EXT GPU PWRGD Pullup

82 81 80 77 70 69 68 63 60 59

PP3V3_S0

28 25 24

55 51

22 21

49 48

19

47

18 13

45

8

43 39

7

37

6

29

96 85 84

R7890 1

100K

5%

1/16W

MF-LF

402

2

84 83 69 9

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

OUT

9 69 83 84

4 3

V2MON THRESHOLD IS 2.866V



S0_PWR_PGOOD

64 66 67 68 69

B

Power Control



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

69

OF

97

2 1

8 7 6

37 34 30

87 82

26

70

24 22 20 18

69 68 64 54

96

8 7

44 38

PP3V3_S5

D

Q7912

SSM6N15FEAPE

SOT563

D 6

43 42 40 21

69

7 IN

PM_SLP_S4_L

2 G S

1

R7912 1

10K

5%

1/16W

MF-LF

402 2

3.3V S3 FET

P3V3S3_EN_L

4

C7911

0.033UF

10%

16V

X5R

402

R7910

47K

1 2

1

2

5%

1/16W

MF-LF

402

P3V3S3_SS

CRITICAL

Q7910

FDC638P_G

SM

6

5

2

1

3 C7910

0.01UF

1

10%

16V

CERM

402

2

PP3V3_S3

7 8 21 27 31 32 45 50 52

MOSFET

CHANNEL

RDS(ON)

LOADING

3.3V S3 FET

FDC638P

P-TYPE

48 mOhm @4.5V

0.087 A (EDP)

5

1.8V GPU FET

87 84 69 55 25 18 8 7

PP1V8_S0

C

43 41

79

40

70

39

65

31 9 8 7

64 55 53 51

PP5V_S3

R7942 1

69.8K

1%

1/16W

MF-LF

402

2

Q7941

SSM6N15FEAPE

SOT563

D 3

R7940

1

100K

2

5%

1/16W

MF-LF

402

C7940

0.1UF

20%

10V

CERM

402

1

2

P1V8GPU_SS

Q7941

SSM6N15FEAPE

SOT563

D 6

1 G

P1V8GPU_EN_L

R7941

10K

1 2

1%

1/16W

MF-LF

402

2 G S

1

P1V8GPU_EN_L_RC

1.8V Vgs

3

D

CRITICAL

Q7940

SI2312BDS

SOT23

S

2

PP1V8_GPUIFPX

1

2

C7941

0.01UF

10%

16V

CERM

402

5 G S

4

84 83 69

IN

P1V8_S0GPU_EN

8 78

B

41 40 39 31 9 8 7

79 70 65 64 55 53 51 43

PP5V_S3

1.5V S0 FET

65 30 29 28 8 7

PP1V8R1V5_S3

D

9 CRITICAL

Q7901

ROME

DFN

NC

8

MOSFET

CHANNEL

RDS(ON)

LOADING

1.5V S0 FET

Rome SenseFET

N-TYPE

6.3 mOhm @4.5V

5.4 A (EDP)

C7902

0.1UF

20%

10V

CERM

402

1

2

R7901

10K

1 2

5%

1/16W

MF-LF

402

MCPDDR_SS

Q7971

SSM6N15FEAPE

SOT563

D 6

R7903 1

100K

5%

1/16W

MF-LF

402

2

Q7971

SSM6N15FEAPE

SOT563

D 3

MCPDDR_EN_L

R7971

47K

1 2

5%

1/16W

MF-LF

402

2 G S

1

4 G

MCPDDR_EN_L_RC

S

7 1 2 3 5

1

2

KELVIN 6 P1V5_S0_KELVIN

P1V5_S0_SENSE

OUT

47

OUT 47

PP1V8R1V5_S0_FET

7 8 11 12 16 24 28 29 39 68 69

C7903

0.068UF

10%

10V

CERM

402

A

69 IN

MCPDDR_EN

5 G S

4

8

7 6 5

4 3 2 1

3.3V S0 FET

37 34

96 87

30

82

26

70

24 22

69 68

20

64

18 8 7

54 44 38

PP3V3_S5

Q7912

SSM6N15FEAPE

SOT563

D 3

69 IN

P3V3S0_EN

5 G S

4

37 34

96 87

30

82

26

70

24 22

69 68

20

64

18 8 7

54 44 38

PP3V3_S5

CRITICAL

Q7930

FDC606P_G

SOT-6

R7932 1

100K

5%

1/16W

MF-LF

402

2

P3V3S0_EN_L

C7931

0.033UF

10%

16V

X5R

402

R7930

47K

1 2

1

2

5%

1/16W

MF-LF

402

P3V3S0_SS

3.3V GPU FET

C7930

0.01UF

1 2

10%

16V

CERM

402

CRITICAL

Q7970

FDC606P_G

SOT-6

PP3V3_S0 59 60 63 68 69 77 80 81 82 84

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

85 96

3.3V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

FDC606P

P-TYPE

26 mOhm @4.5V

2.9 A (EDP)

R7972 1

51K

5%

1/16W

MF-LF

402

2

Q7972

SSM3K15FV

SOD-VESM-HF

D 3

P3V3GPU_EN_L

C7971

1UF

10%

10V

X5R

402-1

R7970

1K

1 2

1

2

5%

1/16W

MF-LF

402

P3V3GPU_SS

C7970

0.01UF

1 2

10%

16V

CERM

402

PP3V3_S0GPU

6 8 69 76 77 79 81

MOSFET

3.3V GPU FET

FDC606P

CHANNEL P-TYPE

RDS(ON)

LOADING

BOM_OPTION

26 mOhm @4.5V

1.1 A (EDP)

EG

84 69 IN

P3V3GPU_EN

55 53 51 43 41 40 39 31

79

9 8

70 65

7

64

PP5V_S3

1 G S

2

5.0V S0 FET

R7952

47K

5%

1

1/16W

MF-LF

402

2

Q7955

SSM3K15FV

SOD-VESM-HF

D 3

P5V0S0_EN_L

C7951

0.033UF

10%

16V

X5R

402

1

R7950

47K

2

1

2

5%

1/16W

MF-LF

402

P5V0S0_SS

CRITICAL

Q7950

TPCP8102

23V1K-SM

C7950

0.01UF

1 2

10%

16V

CERM

402

PP5V_S0

7 8 39 44 49 51 63 66 67 83 85

MOSFET

CHANNEL

RDS(ON)

LOADING

5.0V S0 FET

FDC606P

P-TYPE

26 MOHM @4.5V

1.7 A (EDP)

69 46

IN

PM_SLP_S3_L_R

1 G S

2

MCP79 DDR FETs

MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.

In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low before rail is turned off, and remains low until after rail turns back on or DIMMs will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp on VTT rail, which pulls all CKE signals low through VTT termination resistors.

D

C

B

65 29 28 8 7


R7975 1

10

5%

1/16W

MF-LF

402

2

VTTCLAMP_L

90mA max load @ 0.9V

81mW max power

55 53 51 43 41 40 39 31 9

79 70

8 7

65 64

PP5V_S3

R7976 1

100K

5%

1/16W

MF-LF

402

2

Q7975

SSM6N15FEAPE

SOT563

VTTCLAMP_EN

2 G

Q7975

SSM6N15FEAPE

SOT563

D 3

NO STUFF

C7976

0.001UF

20%

50V

CERM

402

1

2

65 26 9

IN

MEM_VTT_EN

5 G S

4

D 6

S

1

Power FETs



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

70

OF

97

4 3 2 1

D

8

Page Notes


- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDDQ

- =PP1V2_GPU_PEX_IOVDD


(NONE)


(NONE)

7

83 78 76 73 71 8

83 78 76 73 71 8

83 78 76 73 71 8

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

PP1V1_S0GPU_REG

C

B

PEX 1.1V Current = 2A

250mA

AK15

AL7

E7

E35

F7

A2

H32

M7

P6

P7

R7

U7

V6

AB7

AD6

AF6

AG6

AJ5

D35

NC_GPU_DFM

NO_TEST=TRUE

OMIT

U8000

NB9P-GS

BGA

SYMBOL 2 OF 9

PEX_IOVDD1

PEX_IOVDD2

PEX_IOVDD3

PEX_IOVDD4

PEX_IOVDD5

NC

PEX_IOVDDQ1

PEX_IOVDDQ2

PEX_IOVDDQ3

PEX_IOVDDQ4

PEX_IOVDDQ5

PEX_IOVDDQ6

PEX_IOVDDQ7

PEX_IOVDDQ8

PEX_IOVDDQ9

PEX_IOVDDQ10

PEX_IOVDDQ11

PEX_IOVDDQ12

PEX_IOVDDQ13

PEX_IOVDDQ14

PEX_IOVDDQ15

PEX_IOVDDQ16

PEX_IOVDDQ17

PEX_IOVDDQ18

PEX_IOVDDQ19

PEX_IOVDDQ20

PEX_IOVDDQ21

PEX_IOVDDQ22

PEX_IOVDDQ23

PEX_IOVDDQ24

PEX_IOVDDQ25

AK16

AK17

AK21

AK24

AK27

AG26

AJ14

AJ15

AJ19

AJ21

AJ22

AJ24

AJ25

AJ27

AK18

AK20

AK23

AK26

AL16

AG11

AG12

AG13

AG15

AG16

AG17

AG18

AG22

AG23

AG24

AG25

1500mA

1

2

C8002

1UF

10%

6.3V

CERM

402

1

2

C8001

4.7UF

20%

6.3V

CERM

603

1

2

C8000

22UF

20%

6.3V

CERM-X5R

805

1

2

1

2

1

2

C8003

1UF

10%

6.3V

CERM

402

C8008

1UF

10%

6.3V

CERM

402

C8009

1UF

10%

6.3V

CERM

402

1

2

1

2

C8007

4.7UF

20%

6.3V

CERM

603

1

2

C8004

0.1UF

20%

10V

CERM

402

C8010

0.1UF

20%

10V

CERM

402

1

2

1

2

C8006

22UF

20%

6.3V

CERM-X5R

805

1

2

C8005

0.1UF

20%

10V

CERM

402

C8011

0.1UF

20%

10V

CERM

402

180mA

PP1V1_GPU_PEX_PLLVDD_F



VOLTAGE=1.2V

1

2

C8017

0.1UF

20%

10V

CERM

402

L8015

10NH-600MA

1 2

1

2

0603

C8016

4.7UF

20%

6.3V

CERM

603

C8015

4.7UF

20%

6.3V

CERM

603

1

2

PEX_PLLVDD

AG14

VDD_SENSE

AD20

AD19

GND_SENSE

GPU_VDD_SENSE

GPU_GND_SENSE

79

79

6 5 4

90 9 IN

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

C8020 0.1uF

1

C8021 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<1>

PEG_R2D_C_N<1>

C8022 0.1uF

1

C8023 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

C8024 0.1uF

1

C8025 0.1uF

1

90 9 IN

90 9

IN

PEG_R2D_C_P<3>

PEG_R2D_C_N<3>

C8026 0.1uF

1

C8027 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<4>

PEG_R2D_C_N<4>

C8028 0.1uF

1

C8029 0.1uF

1

90 9

IN

90 9

IN

PEG_R2D_C_P<5>

PEG_R2D_C_N<5>

C8030 0.1uF

1

C8031 0.1uF

1

90 9

IN

90 9

IN

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

C8032 0.1uF

1

C8033 0.1uF

1

90 9

IN

90 9 IN

PEG_R2D_C_P<7>

PEG_R2D_C_N<7>

C8034 0.1uF

1

C8035 0.1uF

1

90 9

IN

90 9

IN

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

C8036 0.1uF

1

C8037 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

C8038 0.1uF

1

C8039 0.1uF

1

90 9

IN

90 9 IN

PEG_R2D_C_P<10>

C8040 0.1uF

1

PEG_R2D_C_N<10>

C8041 0.1uF

1

90 9 IN

90 9

IN

PEG_R2D_C_P<11>

C8042 0.1uF

1

PEG_R2D_C_N<11>

C8043 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<12>

C8044 0.1uF

1

PEG_R2D_C_N<12>

C8045 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<13>

C8046 0.1uF

1

PEG_R2D_C_N<13>

C8047 0.1uF

1

90 9 IN

90 9 IN

PEG_R2D_C_P<14>

C8048 0.1uF

1

PEG_R2D_C_N<14>

C8049 0.1uF

1

90 9

IN

90 9 IN

90 9 IN

PEG_R2D_C_P<15>

C8050 0.1uF

1

PEG_R2D_C_N<15>

C8051 0.1uF

1

2

10% 16V X5R 402

90

PEG_R2D_N<0>

2

90

PEG_R2D_P<0>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<1>

2

90

PEG_R2D_P<1>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<2>

2

90

PEG_R2D_P<2>

10% 16V X5R 402

2

90

PEG_R2D_P<3>

10% 16V X5R 402

90

PEG_R2D_N<3>

2

10% 16V X5R 402

2

90

PEG_R2D_P<4>

10% 16V X5R 402

90

PEG_R2D_N<4>

2

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<5>

2

90

PEG_R2D_P<5>

10% 16V X5R 402

2

90

PEG_R2D_P<6>

10% 16V X5R 402

90

PEG_R2D_N<6>

2

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<7>

2

90

PEG_R2D_P<7>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<8>

2

90

PEG_R2D_P<8>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<9>

2

90

PEG_R2D_P<9>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<10>

2

90

PEG_R2D_P<10>

10% 16V X5R 402

2

90

PEG_R2D_P<11>

10% 16V X5R 402

90

PEG_R2D_N<11>

2

10% 16V X5R 402

2

90

PEG_R2D_P<12>

10% 16V X5R 402

90

PEG_R2D_N<12>

2

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<13>

2

90

PEG_R2D_P<13>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<14>

2

90

PEG_R2D_P<14>

10% 16V X5R 402

2

10% 16V X5R 402

90

PEG_R2D_N<15>

2

90

PEG_R2D_P<15>

10% 16V X5R 402

90 17

90 17

IN

IN

PEG_CLK100M_P

PEG_CLK100M_N

84 9

IN

EG_RESET_L

R8020 0

1

5%

1/16W

MF-LF

402

2 GPU_RESET_R_L

TP_PEX_CLKREQ_L

AP17

AN17

3

OMIT

PEX_RX0

PEX_RX0*

U8000

NB9P-GS

BGA

SYMBOL 1 OF 9

PEX_TX0

PEX_TX0*

AL17

AM17

AN19

AP19

PEX_RX1

PEX_RX1*

AR19

AR20

PEX_RX2

PEX_RX2*

AP20

AN20

PEX_RX3

PEX_RX3*

AN22

AP22

PEX_RX4

PEX_RX4*

AR22

AR23

PEX_RX5

PEX_RX5*

AP23

AN23

PEX_RX6

PEX_RX6*

AN25

AP25

PEX_RX7

PEX_RX7*

AR25

AR26

PEX_RX8

PEX_RX8*

AP26

AN26

PEX_RX9

PEX_RX9*

AN28

AP28

PEX_RX10

PEX_RX10*

AR28

AR29

PEX_RX11

PEX_RX11*

AP29

AN29

PEX_RX12

PEX_RX12*

AN31

AP31

PEX_RX13

PEX_RX13*

AR31

AR32

PEX_RX14

PEX_RX14*

AR34

AP34

PEX_RX15

PEX_RX15*

PEX_TX1

PEX_TX1*

AM18

AM19

PEX_TX2

PEX_TX2*

AL19

AK19

PEX_TX3

PEX_TX3*

AL20

AM20

PEX_TX4

PEX_TX4*

AM21

AM22

PEX_TX5

PEX_TX5*

AL22

AK22

PEX_TX6

PEX_TX6*

AL23

AM23

PEX_TX7

PEX_TX7*

AM24

AM25

PEX_TX8

PEX_TX8*

AL25

AK25

PEX_TX9

PEX_TX9*

AL26

AM26

PEX_TX10

PEX_TX10*

AM27

AM28

PEX_TX11

PEX_TX11*

AL28

AK28

PEX_TX12

PEX_TX12*

AK29

AL29

PEX_TX13

PEX_TX13*

AM29

AM30

PEX_TX14

PEX_TX14*

AM31

AM32

PEX_TX15

PEX_TX15*

AN32

AP32

AR16

AR17

AM16

PEX_REFCLK

PEX_REFCLK*

AR13

PEX_RST*

PEX_CLKREQ*

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT*

AJ17

AJ18

PEX_TERMP

AG21

PEX_RFU1

PEX_RFU2

AG19

NC

AG20

NC

2 1

90

PEG_D2R_C_P<0>

90

PEG_D2R_C_N<0>

90

PEG_D2R_C_P<1>

90

PEG_D2R_C_N<1>

90

PEG_D2R_C_P<2>

90

PEG_D2R_C_N<2>

90

PEG_D2R_C_P<3>

90

PEG_D2R_C_N<3>

90

PEG_D2R_C_P<4>

90

PEG_D2R_C_N<4>

90

PEG_D2R_C_P<5>

90

PEG_D2R_C_N<5>

90

PEG_D2R_C_P<6>

90

PEG_D2R_C_N<6>

90

PEG_D2R_C_P<7>

90

PEG_D2R_C_N<7>

90

PEG_D2R_C_P<8>

90

PEG_D2R_C_N<8>

90

PEG_D2R_C_P<9>

90

PEG_D2R_C_N<9>

90

PEG_D2R_C_P<10>

90

PEG_D2R_C_N<10>

90

PEG_D2R_C_P<11>

90

PEG_D2R_C_N<11>

90

PEG_D2R_C_P<12>

90

PEG_D2R_C_N<12>

90

PEG_D2R_C_P<13>

90

PEG_D2R_C_N<13>

90

PEG_D2R_C_P<14>

90

PEG_D2R_C_N<14>

90

PEG_D2R_C_P<15>

90

PEG_D2R_C_N<15>

PEX_TSTCLK_P

PEX_TSTCLK_N

PEX_TERMP_PD

C8055 0.1uF

1

C8056 0.1uF

1

C8057 0.1uF

C8058 0.1uF

C8059 0.1uF

C8060 0.1uF

1

1

1

1

C8061 0.1uF

1

C8062 0.1uF

1

C8063

C8067

C8068 0.1uF

C8069 0.1uF

C8070 0.1uF

C8071

0.1uF

C8064 0.1uF

C8065 0.1uF

C8066 0.1uF

0.1uF

0.1uF

C8072 0.1uF

C8073 0.1uF

C8074 0.1uF

1

1

1

1

1

1

1

1

1

1

1

1

C8075 0.1uF

1

C8076 0.1uF

1

C8077 0.1uF

C8078 0.1uF

C8079 0.1uF

1

C8080 0.1uF

1

C8081 0.1uF

1

C8082 0.1uF

1

C8083 0.1uF

1

C8084 0.1uF

1

C8085 0.1uF

1

C8086 0.1uF

1

R8050

1

2.49K

2

1%

1/16W

MF-LF

402

1

1

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

2

10% 16V X5R 402

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_N<9>

OUT 9 90

OUT 9 90

OUT 9 90

OUT 9 90

OUT 9 90

OUT

9 90

OUT 9 90

OUT 9 90

OUT

9 90

OUT 9 90

OUT 9 90

OUT

9 90

OUT

9 90

OUT 9 90

OUT

9 90

OUT

9 90

OUT 9 90

OUT

9 90

OUT

9 90

OUT 9 90

PEG_D2R_P<10>

OUT 9 90

PEG_D2R_N<10>

OUT

9 90

PEG_D2R_P<11>

OUT 9 90

PEG_D2R_N<11>

OUT 9 90

PEG_D2R_P<12>

OUT 9 90

PEG_D2R_N<12>

OUT 9 90

PEG_D2R_P<13>

OUT 9 90

PEG_D2R_N<13>

OUT 9 90

2

10% 16V X5R 402

2

10% 16V X5R 402

PEG_D2R_P<14>

OUT

9 90

PEG_D2R_N<14>

OUT 9 90

2

10% 16V X5R 402

2

10% 16V X5R 402

PEG_D2R_P<15>

PEG_D2R_N<15>

R8060

200

1 2

1%

1/16W

MF-LF

402

OUT 9 90

OUT

9 90

A

8

7 6 5 4 3

D

C

B

NV G96 PCI-E



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

71

OF

97

2 1

D

8

Page Notes


- =PPVCORE_GPU

- =PP1V8_GPU_FBVDDQ


(NONE)


(NONE)

C

B

A

7

79

8

46

PPVCORE_GPU

75 74 73 47 9 8

PP1V8_S0GPU_ISNS

6

???A @ ???/???MHz Core/Mem Clk for VDD

1

2

C8100

4.7UF

20%

6.3V

X5R-CERM

402

1

2

C8101

4.7UF

20%

6.3V

X5R-CERM

402

1

2

C8102

4.7UF

20%

6.3V

X5R-CERM

402

1

2

C8103

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8104

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8105

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8106

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8107

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8108

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8109

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8110

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8111

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8112

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8113

0.1UF

20%

10V

CERM

402

1

2

C8114

0.1UF

20%

10V

CERM

402

1

2

C8115

0.1UF

20%

10V

CERM

402

1

2

C8116

0.1UF

20%

10V

CERM

402

1

2

C8117

0.1UF

20%

10V

CERM

402

1

2

C8118

0.1UF

20%

10V

CERM

402

1

2

C8119

0.1UF

20%

10V

CERM

402

1

2

C8120

0.1UF

20%

10V

CERM

402

1

2

C8121

0.1UF

20%

10V

CERM

402

1

2

C8122

0.1UF

20%

10V

CERM

402

5

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

M12

M14

M16

M18

M20

M22

M24

P11

P13

P15

P17

P19

P21

P23

P25

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

T12

T14

T16

T18

T20

T22

T24

V11

V13

V15

V17

VDD

OMIT

U8000

NB9P-GS

BGA

SYMBOL 9 OF 9

VDD

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AD12

AD14

AD16

AD18

AD22

W20

AC12

AC13

AC14

AC15

AC16

AC17

AC18

W24

W25

Y12

Y14

Y16

Y18

W17

W18

W19

AD24

W21

W22

W23

Y20

Y22

Y24

AB11

AB13

AB15

AB17

AB19

AB21

AB23

AB25

AC11

V19

V21

V23

V25

W11

W12

W13

W14

W15

W16

4

Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

???A @ ???MHz 1.8V GDDR3

C8150

4.7UF

20%

6.3V

CERM

603

1

2

C8151

4.7UF

20%

6.3V

CERM

603

1

2

C8156

0.1UF

20%

10V

CERM

402

1

2

C8157

0.1UF

20%

10V

CERM

402

1

2

C8158

0.1UF

20%

10V

CERM

402

1

2

C8159

0.1UF

20%

10V

CERM

402

1

2

C8160

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8161

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8162

0.1UF

20%

10V

CERM

402

1

2

C8163

0.1UF

20%

10V

CERM

402

1

2

C8164

0.1UF

20%

10V

CERM

402

1

2

C8165

0.1UF

20%

10V

CERM

402

1

2

C8166

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8167

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8168

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8169

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8170

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8171

0.47UF

10%

6.3V

CERM-X5R

402

1

2

B18

J17

U27

AB27

AB29

AC27

AD27

AE27

AJ28

E21

G8

G9

G17

G18

G22

H29

J14

J15

J16

FBVDDQ

OMIT

U8000

NB9P-GS

BGA

SYMBOL 7 OF 9

FBVDDQ

J20

J21

J22

J23

J24

J29

N27

P27

R27

T27

U29

V27

V29

V34

W27

Y27

AA27

AA29

AA31

8

7 6 5 4

3

GND

U8000

NB9P-GS

BGA

SYMBOL 8 OF 9

GND

AD15

AD17

AD21

AD23

AD25

AD31

AD34

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AG2

AG5

AG31

AG34

AB12

AB14

AB16

AB18

AB20

AB22

AB24

AC9

AD2

AD5

AD11

AD13

AK2

AK5

AP33

AK31

AK34

AL6

AL9

AL12

AL15

AL18

AL21

AL24

AL27

AL30

AN2

AN34

AP3

AP6

AP9

AP12

AP15

AP18

AP21

AP24

AP27

AP30

Y17

Y19

Y21

Y23

Y25

AA2

AA5

AA11

AA12

AA13

AA14

AA15

AA16

V18

V20

V22

V24

V31

Y11

Y13

Y15

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA34

U17

U18

U19

U20

U21

U22

U23

U24

U25

V2

V5

V9

V12

V14

V16

M5

M11

M13

M15

M17

M19

M21

M23

M25

M31

M34

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

E27

E30

F2

F5

F31

F34

J2

J5

J31

J34

L9

M2

P12

P14

P16

P18

P20

P22

P24

R2

R5

R31

R34

T11

T13

T15

T17

T19

T21

T23

T25

U11

U12

U13

U14

U15

U16

B3

B6

B9

B12

B15

B21

B24

B27

B30

B33

C2

C34

E6

E9

E12

E15

E18

E24

3

2 1

D

C

B

NV G96 Core/FB Power



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

72

OF

97

2 1

D

C

B

8

Page Notes


- =PP1V2_GPU_FBPLLAVDD

- =PP1V8_GPU_FBIO


(NONE)


(NONE)

FB_A_DQ<24>

FB_A_DQ<25>

FB_A_DQ<26>

FB_A_DQ<27>

FB_A_DQ<28>

FB_A_DQ<29>

FB_A_DQ<30>

FB_A_DQ<31>

FB_A_DQ<32>

FB_A_DQ<33>

FB_A_DQ<34>

FB_A_DQ<35>

FB_A_DQ<36>

FB_A_DQ<37>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<40>

FB_A_DQ<41>

FB_A_DQ<42>

FB_A_DQ<43>

FB_A_DQ<44>

FB_A_DQ<45>

FB_A_DQ<46>

FB_A_DQ<47>

FB_A_DQ<48>

FB_A_DQ<49>

FB_A_DQ<50>

FB_A_DQ<51>

FB_A_DQ<52>

FB_A_DQ<53>

FB_A_DQ<54>

FB_A_DQ<55>

FB_A_DQ<56>

FB_A_DQ<57>

FB_A_DQ<58>

FB_A_DQ<59>

FB_A_DQ<60>

FB_A_DQ<61>

FB_A_DQ<62>

FB_A_DQ<63>

FB_A_DQ<0>

FB_A_DQ<1>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<4>

FB_A_DQ<5>

FB_A_DQ<6>

FB_A_DQ<7>

FB_A_DQ<8>

FB_A_DQ<9>

FB_A_DQ<10>

FB_A_DQ<11>

FB_A_DQ<12>

FB_A_DQ<13>

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<16>

FB_A_DQ<17>

FB_A_DQ<18>

FB_A_DQ<19>

FB_A_DQ<20>

FB_A_DQ<21>

FB_A_DQ<22>

FB_A_DQ<23>

95 74 BI

95 74 BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74 BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74

BI

95 74

BI

95 74 BI

95 74 BI

95 74 BI

95 74 BI

95 74 BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

95 74 BI

95 74

BI

95 74 BI

7 6 5 4

AG32

AF31

AF30

AD30

AC32

AE30

AE32

AF33

AF34

AE35

AE33

AE34

G34

K34

E33

E34

G33

AG30

AH31

AC35

AB32

AN33

AK32

AL33

AM33

AL31

AK30

AJ30

AH30

AM35

AH33

AH35

AH32

AH34

AM34

AL35

AJ33

L30

P33

P34

N35

P35

N34

L33

L32

N33

K31

K30

G30

K32

R30

R32

P31

N30

L31

M32

M30

G32

H30

F30

G31

H33

K35

K33

P29

NC

R29

NC

L29

NC

M29

NC

AD29

NC

AE29

NC

AG29

NC

AH29

NC

OMIT

FBA_D0

U8000

NB9P-GS

BGA

SYMBOL 3 OF 9

FBA_CMD0

FBA_D23

FBA_D24

FBA_D25

FBA_D26

FBA_D27

FBA_D28

FBA_D29

FBA_D30

FBA_D31

FBA_D32

FBA_D33

FBA_D34

FBA_D35

FBA_D36

FBA_D37

FBA_D38

FBA_D39

FBA_D40

FBA_D41

FBA_D42

FBA_D43

FBA_D44

FBA_D45

FBA_D46

FBA_D47

FBA_D48

FBA_D49

FBA_D50

FBA_D51

FBA_D52

FBA_D53

FBA_D54

FBA_D55

FBA_D56

FBA_D57

FBA_D58

FBA_D59

FBA_D60

FBA_D61

FBA_D62

FBA_D63

FBA_D1

FBA_D2

FBA_D3

FBA_D4

FBA_D5

FBA_D6

FBA_D7

FBA_D8

FBA_D9

FBA_D10

FBA_D11

FBA_D12

FBA_D13

FBA_D14

FBA_D15

FBA_D16

FBA_D17

FBA_D18

FBA_D19

FBA_D20

FBA_D21

FBA_D22

FBA_CMD1

FBA_CMD2

FBA_CMD3

FBA_CMD4

FBA_CMD5

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9

FBA_CMD10

FBA_CMD11

FBA_CMD12

FBA_CMD13

FBA_CMD14

FBA_CMD15

FBA_CMD16

FBA_CMD17

FBA_CMD18

FBA_CMD19

FBA_CMD20

FBA_CMD21

FBA_CMD22

FBA_CMD23

FBA_CMD24

FBA_CMD25

FBA_CMD26

FBA_CMD27

FBA_CMD28

FBA_CMD29

FBA_CMD30

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CLK1*

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0

FBA_DQS_RN1

FBA_DQS_RN2

FBA_DQS_RN3

FBA_DQS_RN4

FBA_DQS_RN5

FBA_DQS_RN6

FBA_DQS_RN7

FBA_DQS_WP0

FBA_DQS_WP1

FBA_DQS_WP2

FBA_DQS_WP3

FBA_DQS_WP4

FBA_DQS_WP5

FBA_DQS_WP6

FBA_DQS_WP7

FB_DLLAVDD0

FB_PLLAVDD0

FBA_RFU0

FBA_RFU1*

FBA_RFU2

FBA_RFU3*

FBA_RFU4

FBA_RFU5*

FBA_RFU6

FBA_RFU7*

FBA_DEBUG

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

V32

W31

U31

Y32

AB35

AB34

W35

W33

W30

T34

T35

AB31

Y30

Y34

W32

AA30

AA32

Y33

U32

Y31

U34

Y35

W34

V30

U35

U30

U33

AB30

AB33

T33

W29

T32

T31

AC31

AC30

P30

P32

J30

H34

AF32

AF35

AL32

AL34

N32

L35

H31

G35

AD32

AC34

AJ31

AJ35

FB_A_LMA<4>

FB_A_RAS_L

FB_A_LMA<5>

FB_A_BA<1>

FB_A_UMA<2>

FB_A_UMA<4>

FB_A_UMA<3>

NC_FB_A_CS1_L

FB_A_CS0_L

FB_A_MA<11>

FB_A_CAS_L

FB_A_WE_L

FB_A_BA<0>

FB_A_UMA<5>

FB_A_MA<12>

FB_A_DRAM_RST

FB_A_MA<7>

FB_A_MA<10>

FB_A_CKE

FB_A_MA<0>

FB_A_MA<9>

FB_A_MA<6>

FB_A_LMA<2>

FB_A_MA<8>

FB_A_LMA<3>

FB_A_MA<1>

NC_FBA_MA<13>

FB_A_BA<2>

NC_FBA_CMD28

NC_FBA_CMD29

NC_FBA_CMD30

FB_A_CLK_P<0>

FB_A_CLK_N<0>

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_DQM_L<4>

FB_A_DQM_L<5>

FB_A_DQM_L<6>

FB_A_DQM_L<7>

FB_A_RDQS<0>

FB_A_RDQS<1>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_RDQS<4>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<7>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

74 95

74 95

74 95

74 95

74 95

74 95

74 95

77

74

74 95

74 95

74 95

74 95

74 95

74 95

OUT

OUT

74 95

74 95

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

77

74 95

74 95

74 95

74 95

74 95

74 95

74 95

77

74 95

77

77

OUT

OUT

OUT

OUT

74 95

74 95

74 95

74 95

BI

BI

BI

BI

BI

BI

BI

BI

74 95

74 95

74 95

74 95

74 95

74 95

74 95

74 95

IN

IN

IN

IN

IN

IN

IN

IN

74 95

74 95

74 95

74 95

74 95

74 95

74 95

74 95

N31

L34

J32

H35

AE31

AC33

AJ32

AJ34

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<7>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

74 95

74 95

74 95

74 95

74 95

74 95

74 95

74 95

AG27

AF27

T30

K27

L27

M27

FBA_DEBUG

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

R8292

1

40.2

1%

1/16W

PLACEMENT_NOTE=Place close to U8000.

MF-LF

402

2

OUT

74

1 R8201

10K

2

5%

1/16W

MF-LF

402

83 78 76 73 71 8

PP1V1_S0GPU_REG

PP1V1_GPU_FBPLLAVDD0_F



VOLTAGE=1.1V

1

2

C8202

0.1UF

20%

10V

CERM

402

1

2

C8201

0.1UF

20%

10V

CERM

402

R8291

1

33.2

1%

1/16W

MF-LF

402

2

1

OUT 74 95

R8200

10K

2

5%

1/16W

MF-LF

402

1

2

1

L8200

FERR-220-OHM

2

0402

C8200

1UF

10%

6.3V

CERM

402

73 72 47 9 8

75 74

PP1V8_S0GPU_ISNS

R8293

60.4

1%

1

1/16W

MF-LF

402

2

R8290

48.7

1

1%

1/16W

MF-LF

402

2

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75

BI

95 75

BI

95 75

BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75

BI

95 75

BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI

95 75 BI

95 75

BI

95 75 BI



FB_B_DQ<24>

FB_B_DQ<25>

FB_B_DQ<26>

FB_B_DQ<27>

FB_B_DQ<28>

FB_B_DQ<29>

FB_B_DQ<30>

FB_B_DQ<31>

FB_B_DQ<32>

FB_B_DQ<33>

FB_B_DQ<34>

FB_B_DQ<35>

FB_B_DQ<36>

FB_B_DQ<37>

FB_B_DQ<38>

FB_B_DQ<39>

FB_B_DQ<40>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<0>

FB_B_DQ<1>

FB_B_DQ<2>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_DQ<5>

FB_B_DQ<6>

FB_B_DQ<7>

FB_B_DQ<8>

FB_B_DQ<9>

FB_B_DQ<10>

FB_B_DQ<11>

FB_B_DQ<12>

FB_B_DQ<13>

FB_B_DQ<14>

FB_B_DQ<15>

FB_B_DQ<16>

FB_B_DQ<17>

FB_B_DQ<18>

FB_B_DQ<19>

FB_B_DQ<20>

FB_B_DQ<21>

FB_B_DQ<22>

FB_B_DQ<23>

FB_B_DQ<43>

FB_B_DQ<44>

FB_B_DQ<45>

FB_B_DQ<46>

FB_B_DQ<47>

FB_B_DQ<48>

FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<51>

FB_B_DQ<52>

FB_B_DQ<53>

FB_B_DQ<54>

FB_B_DQ<55>

FB_B_DQ<56>

FB_B_DQ<57>

FB_B_DQ<58>

FB_B_DQ<59>

FB_B_DQ<60>

FB_B_DQ<61>

FB_B_DQ<62>

FB_B_DQ<63>

A

8

7 6 5 4

3 2 1

C10

D12

E13

F17

F15

F16

E16

F14

F13

D13

A13

B13

A14

C16

A17

B16

D16

D24

D26

E25

F25

F27

E28

F28

D29

B11

C13

A11

B8

A8

C8

C11

D11

E11

F10

D8

F8

F9

E8

F12

A25

B25

D25

C26

C28

B28

A28

A29

E29

F29

D30

E31

C33

D33

F32

E32

B29

C29

B31

C31

B32

C32

B34

B35

G11

NC

G12

NC

G14

NC

G15

NC

G24

NC

G25

NC

NC

G27

NC

G28

OMIT

FBC_D44

FBC_D45

FBC_D46

FBC_D47

FBC_D48

FBC_D49

FBC_D50

FBC_D51

FBC_D52

FBC_D53

FBC_D54

FBC_D55

FBC_D30

FBC_D31

FBC_D32

FBC_D33

FBC_D34

FBC_D35

FBC_D36

FBC_D37

FBC_D38

FBC_D39

FBC_D40

FBC_D41

FBC_D42

FBC_D43

FBC_D56

FBC_D57

FBC_D58

FBC_D59

FBC_D60

FBC_D61

FBC_D62

FBC_D63

FBC_D14

FBC_D15

FBC_D16

FBC_D17

FBC_D18

FBC_D19

FBC_D20

FBC_D21

FBC_D22

FBC_D23

FBC_D24

FBC_D25

FBC_D26

FBC_D27

FBC_D28

FBC_D29

FBC_D1

FBC_D2

FBC_D3

FBC_D4

FBC_D5

FBC_D6

FBC_D7

FBC_D8

FBC_D9

FBC_D10

FBC_D11

FBC_D12

FBC_D13

U8000

NB9P-GS

BGA

FBC_D0

SYMBOL 4 OF 9

FBC_CMD0

FBC_CMD1

FBC_CMD2

FBC_CMD3

FBC_CMD4

FBC_CMD5

FBC_CMD6

FBC_CMD7

FBC_CMD8

FBC_CMD9

FBC_CMD10

FBC_CMD11

FBC_CMD12

FBC_CMD13

FBC_CMD14

FBC_CMD15

FBC_CMD16

FBC_CMD17

FBC_CMD18

FBC_CMD19

FBC_CMD20

FBC_CMD21

FBC_CMD22

FBC_CMD23

FBC_CMD24

FBC_CMD25

FBC_CMD26

FBC_CMD27

FBC_CMD28

FBC_CMD29

FBC_CMD30

FBC_RFU0

FBC_RFU1*

FBC_RFU2

FBC_RFU3*

FBC_RFU4

FBC_RFU5*

FBC_RFU6

FBC_RFU7*

FBC_CLK0

FBC_CLK0*

FBC_CLK1

FBC_CLK1*

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_RN0

FBC_DQS_RN1

FBC_DQS_RN2

FBC_DQS_RN3

FBC_DQS_RN4

FBC_DQS_RN5

FBC_DQS_RN6

FBC_DQS_RN7

FBC_DQS_WP0

FBC_DQS_WP1

FBC_DQS_WP2

FBC_DQS_WP3

FBC_DQS_WP4

FBC_DQS_WP5

FBC_DQS_WP6

FBC_DQS_WP7

FB_DLLAVDD1

FB_PLLAVDD1

FBC_DEBUG

FB_VREF

E20

G21

F20

F19

F23

A22

C22

B17

F24

C25

C17

B19

D18

F21

A23

D21

B23

D19

F18

C19

F22

C23

B20

E22

C20

B22

A19

D22

D20

E19

A20

E17

D17

D23

E23

F11

D10

D15

A16

D27

D28

D34

A34

E10

A10

D14

C14

E26

B26

D32

A32

D9

B10

E14

B14

F26

A26

D31

A31

J19

J18

G19

J27

FB_B_LMA<4>

FB_B_RAS_L

FB_B_LMA<5>

FB_B_BA<1>

FB_B_UMA<2>

FB_B_UMA<4>

FB_B_UMA<3>

NC_FB_B_CS1_L

FB_B_CS0_L

FB_B_MA<11>

FB_B_CAS_L

FB_B_WE_L

FB_B_BA<0>

FB_B_UMA<5>

FB_B_MA<12>

FB_B_DRAM_RST

FB_B_MA<7>

FB_B_MA<10>

FB_B_CKE

FB_B_MA<0>

FB_B_MA<9>

FB_B_MA<6>

FB_B_LMA<2>

FB_B_MA<8>

FB_B_LMA<3>

FB_B_MA<1>

NC_FBB_MA<13>

FB_B_BA<2>

NC_FBC_CMD28

NC_FBC_CMD29

NC_FBC_CMD30

FB_B_CLK_P<0>

FB_B_CLK_N<0>

FB_B_CLK_P<1>

FB_B_CLK_N<1>

FB_B_DQM_L<0>

FB_B_DQM_L<1>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_RDQS<0>

FB_B_RDQS<1>

FB_B_RDQS<2>

FB_B_RDQS<3>

FB_B_RDQS<4>

FB_B_RDQS<5>

FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_WDQS<1>

FB_B_WDQS<2>

FB_B_WDQS<3>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FBC_DEBUG

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

75 95

75 95

75 95

75 95

75 95

75 95

75 95

77

75

75 95

75 95

75 95

75 95

75 95

75 95

OUT

OUT

75 95

75 95

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

77

75 95

75 95

75 95

75 95

75 95

75 95

75 95

77

75 95

77

77

OUT

OUT

OUT

OUT

75 95

75 95

75 95

75 95

BI

BI

BI

BI

BI

BI

BI

BI

75 95

75 95

75 95

75 95

75 95

75 95

75 95

75 95

IN

IN

IN

IN

IN

IN

IN

IN

75 95

75 95

75 95

75 95

75 95

75 95

75 95

75 95

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

75 95

75 95

75 95

75 95

75 95

75 95

75 95

75 95

NO STUFF

D 6 Q8295

SSM6N15FEAPE

SOT563

GPU_FB_VREF_UNTERM_L



2

G S

1

OUT

75

1 R8251

10K

2

5%

1/16W

MF-LF

402

OUT 75 95

1 R8250

10K

2

5%

1/16W

MF-LF

402

75 74 73 72 47 9 8

PP1V8_S0GPU_ISNS

R8294

1

60.4

1%

1/16W

MF-LF

402

2

NO STUFF

1

R8297

1.02K

1%

1/16W

MF-LF

402

2

R8295

1

1.07K

1%

1/16W

MF-LF

402

2

R8296

1

2.49K

1%

1/16W

MF-LF

402

2

D

C

B

NV G96 Frame Buffer I/F



A

77 76 75 74

IN

FB_VREF_UNTERM

83 78 76 73 71 8

PP1V1_S0GPU_REG

1

L8290

FERR-220-OHM

2 PP1V1_GPU_FBPLLAVDD1_F



1

2

C8290

0.1UF

20%

10V

CERM

402

2

C8291

0.1UF

20%

10V

CERM

402

1

2

C8292

1UF

10%

6.3V

CERM

402

0402

GPU_FB_VREF

NO STUFF

C8296

0.1uF

10%

16V

X5R

402

1

2







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

73

OF

97

3 2 1

D

C

B

A

8

95 74 73

95 74 73

IN

IN

95 73 IN

95 73

95 73

IN

IN

95 73

IN

95 74 73

95 74 73

IN

IN

95 74 73

IN

95 74 73

95 74 73

IN

IN

95 74 73

74 73

IN

IN

95 74 73 IN

FB_A_MA<0>

FB_A_MA<1>

FB_A_LMA<2>

FB_A_LMA<3>

FB_A_LMA<4>

FB_A_LMA<5>

FB_A_MA<6>

FB_A_MA<7>

FB_A_MA<8>

FB_A_MA<9>

FB_A_MA<10>

FB_A_MA<11>

FB_A_CKE

FB_A_MA<12>

95 73

IN

95 73

74 73

IN

IN

95 74 73

IN

95 74 73

95 74 73

IN

IN

FB_A_CLK_P<0>

FB_A_CLK_N<0>

FB_A_CS0_L

FB_A_WE_L

FB_A_CAS_L

FB_A_RAS_L

95 74 73

IN

95 73 IN

95 73

95 73

95 73

IN

IN

IN

FB_A_DRAM_RST

95 73

OUT

95 73 OUT

95 73

OUT

95 73

OUT

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<0>

FB_A_RDQS<1>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<0>

FB_A_WDQS<1>

95 74 73

95 74 73

IN

IN

95 74 73 IN

FB_A_BA<0>

FB_A_BA<1>

FB_A_BA<2>

8

R8440

1

1K

5%

1/16W

MF-LF

402

2

VRAM4

R8442

1

121

1%

1/16W

MF-LF

402

2

7 6

74 73 72 47 9 8

75

PP1V8_S0GPU_ISNS

74 73 72 47 9 8

75

PP1V8_S0GPU_ISNS

C8420

10UF

20%

6.3V

X5R

603

1

2

74 27 9

GPU_FB_A_VREF_DIV

Connect to designated pin, then GND

1

2

C8421

0.1uF

10%

16V

X5R

402

R8430

1

549

1%

1/16W

MF-LF

402

2

R8431

1

1.33K

1%

1/16W

MF-LF

402

2

C8400

10UF

20%

6.3V

X5R

603

1

2

1

2

C8422

0.1uF

10%

16V

X5R

402

R8432

1

931

1%

1/16W

MF-LF

402

2

1

2

C8401

0.1uF

10%

16V

X5R

402

1

2

C8423

0.1uF

10%

16V

X5R

402

1

2

C8402

0.1uF

10%

16V

X5R

402

FB_A0_VREF

1

2

C8431

0.01UF

10%

16V

CERM

402

1

2

C8424

0.1uF

10%

16V

X5R

402

R8433

1

549

1%

1/16W

MF-LF

402

2

R8434

1

1.33K

1%

1/16W

MF-LF

402

2

1

2

C8403

0.1uF

10%

16V

X5R

402

1

2

C8410

0.1uF

10%

16V

X5R

402

U8400.J1

1

2

C8425

0.1uF

10%

16V

X5R

402

1

2

C8404

0.1uF

10%

16V

X5R

402

1

2

C8415

0.1uF

10%

16V

X5R

402

U8400.J12

FB_A2_VREF

R8435

1

931

1%

1/16W

MF-LF

402

2

1

2

C8426

0.1uF

10%

16V

X5R

402

1

2

C8432

0.01UF

10%

16V

CERM

402

OMIT

CRITICAL

A2

A11

F1

F12

M1

M12

V2

V11

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

K1

K12

VDDA0

VDDA1

U8400

BGA

(2 OF 2)

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

A1

A12

C1

C4

C9

C12

E1

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

A3

A10

G1

G12

L1

L12

V3

V10

VSSA0

VSSA1

J1

J12

G2

G11

L2

L11

P1

P4

P9

P12

B1

B4

B9

B12

D1

D4

D9

D12

T1

T4

T9

T12

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

H1

H12

VREF0

VREF1

VRAM4

R8444

1

121

1%

1/16W

MF-LF

VRAM4

402

2

1

R8443

2

121

1%

1/16W

MF-LF

402

R8448

1

243

1%

1/16W

MF-LF

402

2

FB_A2_VREF_UNTERM_L

FB_A0_VREF_UNTERM_L

R8446

1

243

1%

1/16W

VRAM4

MF-LF

402

2

1

R8445

121

1%

2

1/16W

MF-LF

402

FB_A0_ZQ

FB_A0_MF

FB_A0_SEN

FB_A_CLK0_TERM

VOLTAGE=0.9V

C8446

0.01UF

10%

16V

CERM

402

1

2

1

R8447

243

1%

2

1/16W

MF-LF

402

K9

H11

K10

M4

K11

L9

H9

M9

K4

H2

K3

L4

K2

J3

A0

A1

A2

A3

A4

A5

A6

A7

A8/AP

A9

A10

A11

CKE

U8400

BGA

(1 OF 2)

A12/CS1*

J11 CK

J10

F4

CK*

CS0*

WE* H4

F9

H10

CAS*

RAS*

ZQ A4

A9

V4

MF

SEN

V9 RESET

D3

D10

P10

P3

RDQS0

RDQS1

RDQS2

RDQS3

D2

D11

P11

P2

WDQS0

WDQS1

WDQS2

WDQS3

G9

G4

H3

BA0

BA1

BA2

75 74 73

77 76

IN

Q8400

SSM6N15FEAPE

SOT563

FB_VREF_UNTERM

OMIT

CRITICAL

DM0

DM1

DM2

DM3

E3

E10

N10

N3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

B2

B3

C2

C3

E2

F3

F2

G3

DQ7

DQ8

DQ9

DQ10

B11

B10

C11

C10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

E11

F10

F11

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

G10

M11

L10

N11

M10

R11

R10

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

T11

T10

M2

L3

N2

M3

DQ29

DQ30

DQ31

R2

R3

T2

T3

2

G

D

6

S

1

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQ<24>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<31>

FB_A_DQ<28>

FB_A_DQ<27>

FB_A_DQ<25>

FB_A_DQ<26>

FB_A_DQ<20>

FB_A_DQ<22>

FB_A_DQ<21>

FB_A_DQ<23>

FB_A_DQ<19>

FB_A_DQ<18>

FB_A_DQ<16>

FB_A_DQ<17>

FB_A_DQ<5>

FB_A_DQ<4>

FB_A_DQ<6>

FB_A_DQ<7>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<1>

FB_A_DQ<0>

FB_A_DQ<13>

FB_A_DQ<15>

FB_A_DQ<14>

FB_A_DQ<12>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<8>

FB_A_DQ<11>

Q8400

SSM6N15FEAPE

SOT563

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

5

G

IN

IN

IN

IN

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

NC

J2

RFU

1

R8449

2

100

5%

1/16W

MF-LF

402

D

3

S

4

R8490

1

1K

5%

1/16W

MF-LF

402

2

95 74 73

95 74 73

IN

IN

95 73 IN

95 73

95 73

IN

IN

95 73

IN

95 74 73

95 74 73

IN

IN

95 74 73

IN

95 74 73

95 74 73

IN

IN

95 74 73

74 73

IN

IN

95 74 73 IN

FB_A_MA<0>

FB_A_MA<1>

FB_A_UMA<2>

FB_A_UMA<3>

FB_A_UMA<4>

FB_A_UMA<5>

FB_A_MA<6>

FB_A_MA<7>

FB_A_MA<8>

FB_A_MA<9>

FB_A_MA<10>

FB_A_MA<11>

FB_A_CKE

FB_A_MA<12>

95 73

IN

95 73

74 73

IN

IN

95 74 73

IN

95 74 73

95 74 73

IN

IN

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_CS0_L

FB_A_WE_L

FB_A_CAS_L

FB_A_RAS_L

95 74 73

IN

95 73 IN

95 73

IN

95 73

95 73

IN

IN

FB_A_DRAM_RST

95 73

OUT

95 73 OUT

95 73

OUT

95 73

OUT

FB_A_RDQS<7>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<4>

FB_A_WDQS<7>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<4>

95 74 73

IN

95 74 73

95 74 73

IN

IN

FB_A_BA<0>

FB_A_BA<1>

FB_A_BA<2>

7 6

5 4 3

75 74 73 72 47 9 8

PP1V8_S0GPU_ISNS

75 74 73 72 47 9 8

PP1V8_S0GPU_ISNS

C8470

10UF

20%

6.3V

X5R

603

1

2

74 27 9

GPU_FB_A_VREF_DIV

1

2

C8471

0.1uF

10%

16V

X5R

402

R8480

1

549

1%

1/16W

MF-LF

402

2

R8481

1

1.33K

1%

1/16W

MF-LF

402

2

C8450

10UF

20%

6.3V

X5R

603

1

2

1

2

C8472

0.1uF

10%

16V

X5R

402

R8482

1

931

1%

1/16W

MF-LF

402

2

1

2

C8451

0.1uF

10%

16V

X5R

402


1

2

C8473

0.1uF

10%

16V

X5R

402

1

2

C8481

0.01uF

10%

16V

CERM

402

1

2

C8452

0.1uF

10%

16V

X5R

402

1

2

C8474

0.1uF

10%

16V

X5R

402

FB_A1_VREF

R8483

1

549

1%

1/16W

MF-LF

402

2

R8484

1

1.33K

1%

1/16W

MF-LF

402

2

1

2

C8453

0.1uF

10%

16V

X5R

402

1

2

C8460

0.1uF

10%

16V

X5R

402

U8400.J1

1

2

C8475

0.1uF

10%

16V

X5R

402

1

2

C8454

0.1uF

10%

16V

X5R

402

1

2

C8465

0.1uF

10%

16V

X5R

402

U8400.J12

FB_A3_VREF

R8485

1

931

1%

1/16W

MF-LF

402

2

1

2

C8476

0.1uF

10%

16V

X5R

402

1

2

C8482

0.01uF

10%

16V

CERM

402

OMIT

CRITICAL

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

A1

A12

C1

C4

C9

C12

E1

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

A2

A11

F1

F12

M1

M12

V2

V11

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

K1

K12

VDDA0

VDDA1

U8450

BGA

(2 OF 2)

VSS0

VSS1

A3

A10

G1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

G12

L1

L12

V3

V10

VSSA0

VSSA1

J1

J12

G2

G11

L2

L11

P1

P4

P9

P12

B1

B4

B9

B12

D1

D4

D9

D12

T1

T4

T9

T12

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

H1

H12

VREF0

VREF1

5

VRAM4

R8492

1

121

1%

1/16W

MF-LF

402

2

2 1

Page Notes


- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VREFA


(NONE)


VRAM4

1

D

C

VRAM4

R8494

1

121

1%

1/16W

MF-LF

402

VRAM4 2

1

R8493

121

1%

2

1/16W

MF-LF

402

R8498

1

243

1%

1/16W

MF-LF

402

2

R8496

1

243

1%

1/16W

VRAM4

MF-LF

402

2

1

R8495

121

1%

2

1/16W

MF-LF

402

FB_A1_ZQ

FB_A1_MF

FB_A1_SEN

1

R8499

100

5%

1/16W

MF-LF

2

402

FB_A3_VREF_UNTERM_L

FB_A1_VREF_UNTERM_L

FB_A_CLK1_TERM

VOLTAGE=0.9V

C8496

0.01UF

10%

16V

CERM

402

1

2

75 74 73

77 76

IN

Q8450

SSM6N15FEAPE

SOT563

FB_VREF_UNTERM

2

G

1

R8497

243

1%

2

1/16W

MF-LF

402

OMIT

CRITICAL

K9

H11

K10

M4

K11

L9

H9

M9

K4

H2

K3

L4

K2

J3

A0

A1

A2

A3

A4

A5

A6

A7

A8/AP

A9

A10

A11

CKE

J11

J10

F4

H4

F9

H10

A4

A9

V4

V9

CK

CK*

CS0*

WE*

CAS*

RAS*

ZQ

MF

SEN

RESET

D3

D10

P10

P3

RDQS0

RDQS1

RDQS2

RDQS3

U8450

BGA

(1 OF 2)

A12/CS1*

D2

D11

P11

P2

WDQS0

WDQS1

WDQS2

WDQS3

G9

G4

H3

BA0

BA1

BA2

NC

J2

RFU

DM0

DM1

DM2

DM3

E3

E10

N10

N3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

B2

B3

C2

C3

E2

F3

F2

G3

DQ7

DQ8

DQ9

DQ10

B11

B10

C11

C10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

E11

F10

F11

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

G10

M11

L10

N11

M10

R11

R10

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

T11

T10

M2

L3

N2

M3

DQ29

DQ30

DQ31

R2

R3

T2

T3

D

6

S

1

FB_A_DQM_L<7>

FB_A_DQM_L<5>

FB_A_DQM_L<6>

FB_A_DQM_L<4>

FB_A_DQ<59>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<60>

FB_A_DQ<57>

FB_A_DQ<56>

FB_A_DQ<61>

FB_A_DQ<62>

FB_A_DQ<40>

FB_A_DQ<47>

FB_A_DQ<46>

FB_A_DQ<45>

FB_A_DQ<42>

FB_A_DQ<44>

FB_A_DQ<43>

FB_A_DQ<41>

FB_A_DQ<54>

FB_A_DQ<55>

FB_A_DQ<53>

FB_A_DQ<52>

FB_A_DQ<49>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<48>

FB_A_DQ<36>

FB_A_DQ<37>

FB_A_DQ<32>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<34>

FB_A_DQ<33>

FB_A_DQ<35>

Q8450

SSM6N15FEAPE

SOT563

5

G

IN

IN

IN

IN

73 95

73 95

73 95

73 95

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

D

3

S

4

GDDR3 Frame Buffer A (Top)









B

A

APPLE INC.

SIZE

D

DRAWING NUMBER

051-7892

SCALE

NONE

SHT

74

OF

REV.

A.0.0

97

4 3 2

D

C

B

A

8

95 75 73

95 75 73

IN

IN

95 73 IN

95 73

95 73

IN

IN

95 73

IN

95 75 73

95 75 73

IN

IN

95 75 73

IN

95 75 73

95 75 73

IN

IN

95 75 73

75 73

IN

IN

95 75 73 IN

FB_B_MA<0>

FB_B_MA<1>

FB_B_LMA<2>

FB_B_LMA<3>

FB_B_LMA<4>

FB_B_LMA<5>

FB_B_MA<6>

FB_B_MA<7>

FB_B_MA<8>

FB_B_MA<9>

FB_B_MA<10>

FB_B_MA<11>

FB_B_CKE

FB_B_MA<12>

95 73

IN

95 73

75 73

IN

IN

95 75 73

IN

95 75 73

95 75 73

IN

IN

FB_B_CLK_P<0>

FB_B_CLK_N<0>

FB_B_CS0_L

FB_B_WE_L

FB_B_CAS_L

FB_B_RAS_L

95 75 73

IN

95 73 IN

95 73

IN

95 73

95 73

IN

IN

FB_B_DRAM_RST

95 73

OUT

95 73 OUT

95 73

OUT

95 73

OUT

FB_B_RDQS<1>

FB_B_RDQS<0>

FB_B_RDQS<2>

FB_B_RDQS<3>

FB_B_WDQS<1>

FB_B_WDQS<0>

FB_B_WDQS<2>

FB_B_WDQS<3>

95 75 73

95 75 73

IN

IN

95 75 73 IN

FB_B_BA<0>

FB_B_BA<1>

FB_B_BA<2>

8

R8540

1

1K

5%

1/16W

MF-LF

402

2

VRAM4

R8542

1

121

1%

1/16W

MF-LF

402

2

7 6

74 73 72 47 9 8

75

PP1V8_S0GPU_ISNS

74 73 72 47 9 8

75

PP1V8_S0GPU_ISNS

C8520

10UF

20%

6.3V

X5R

603

1

2

75 27 9

GPU_FB_B_VREF_DIV


1

2

C8521

0.1uF

10%

16V

X5R

402

R8530

1

549

1%

1/16W

MF-LF

402

2

R8531

1

1.33K

1%

1/16W

MF-LF

402

2

C8500

10UF

20%

6.3V

X5R

603

1

2

1

2

C8522

0.1uF

10%

16V

X5R

402

R8532

1

931

1%

1/16W

MF-LF

402

2

1

2

C8501

0.1uF

10%

16V

X5R

402

1

2

C8523

0.1uF

10%

16V

X5R

402

1

2

C8502

0.1uF

10%

16V

X5R

402

FB_B0_VREF

1

2

C8531

0.01uF

10%

16V

CERM

402

1

2

C8524

0.1uF

10%

16V

X5R

402

R8533

1

549

1%

1/16W

MF-LF

402

2

R8534

1

1.33K

1%

1/16W

MF-LF

402

2

1

2

C8503

0.1uF

10%

16V

X5R

402

1

2

C8510

0.1uF

10%

16V

X5R

402

U8500.J1

1

2

C8525

0.1uF

10%

16V

X5R

402

1

2

C8504

0.1uF

10%

16V

X5R

402

1

2

C8515

0.1uF

10%

16V

X5R

402

U8500.J12

FB_B2_VREF

R8535

1

931

1%

1/16W

MF-LF

402

2

1

2

C8526

0.1uF

10%

16V

X5R

402

1

2

C8532

0.01uF

10%

16V

CERM

402

OMIT

CRITICAL

A2

A11

F1

F12

M1

M12

V2

V11

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

K1

K12

VDDA0

VDDA1

U8500

BGA

(2 OF 2)

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

A1

A12

C1

C4

C9

C12

E1

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

A3

A10

G1

G12

L1

L12

V3

V10

VSSA0

VSSA1

J1

J12

G2

G11

L2

L11

P1

P4

P9

P12

B1

B4

B9

B12

D1

D4

D9

D12

T1

T4

T9

T12

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

H1

H12

VREF0

VREF1

VRAM4

R8544

1

121

1%

1/16W

MF-LF

VRAM4

402

2

1

R8543

2

121

1%

1/16W

MF-LF

402

R8548

1

243

1%

1/16W

MF-LF

402

2

R8546

1

243

VRAM4

1%

1/16W

MF-LF

402

2

1

R8545

121

1%

2

1/16W

MF-LF

402

FB_B0_ZQ

FB_B0_MF

FB_B0_SEN

FB_B2_VREF_UNTERM_L

FB_B0_VREF_UNTERM_L

FB_B_CLK0_TERM

VOLTAGE=0.9V

C8546

0.01UF

10%

16V

CERM

402

1

2

75 74

77

73

76

IN

Q8500

SSM6N15FEAPE

SOT563

FB_VREF_UNTERM

2

G

1

R8547

243

1%

2

1/16W

MF-LF

402

OMIT

CRITICAL

K9

H11

K10

M4

K11

L9

H9

M9

K4

H2

K3

L4

K2

J3

A0

A1

A2

A3

A4

A5

A6

A7

A8/AP

A9

A10

A11

CKE

J11 CK

J10

F4

CK*

CS0*

WE* H4

F9

H10

CAS*

RAS*

ZQ A4

A9

V4

MF

SEN

V9 RESET

D3

D10

P10

P3

RDQS0

RDQS1

RDQS2

RDQS3

U8500

BGA

(1 OF 2)

A12/CS1*

D2

D11

P11

P2

WDQS0

WDQS1

WDQS2

WDQS3

G9

G4

H3

BA0

BA1

BA2

NC

J2

RFU

DM0

DM1

DM2

DM3

E3

E10

N10

N3

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

B11

B10

C11

C10

E11

F10

F11

B2

B3

C2

C3

E2

F3

F2

G3

G10

M11

L10

N11

M10

R11

R10

R2

R3

T2

T3

T11

T10

M2

L3

N2

M3

D

6

S

1

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_DQ<12>

FB_B_DQ<8>

FB_B_DQ<11>

FB_B_DQ<10>

FB_B_DQ<13>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<9>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_DQ<0>

FB_B_DQ<2>

FB_B_DQ<1>

FB_B_DQ<7>

FB_B_DQ<21>

FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<17>

FB_B_DQ<20>

FB_B_DQ<22>

FB_B_DQ<18>

FB_B_DQ<23>

FB_B_DQ<26>

FB_B_DQ<27>

FB_B_DQ<31>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<25>

FB_B_DQ<29>

FB_B_DQ<30>

Q8500

SSM6N15FEAPE

SOT563

5

G

IN

IN

IN

IN

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

D

3

S

4

R8590

1

1K

5%

1/16W

MF-LF

402

2

95 75 73

95 75 73

IN

IN

95 73 IN

95 73

95 73

IN

IN

95 73

IN

95 75 73

95 75 73

IN

IN

95 75 73

IN

95 75 73

95 75 73

IN

IN

95 75 73

75 73

IN

IN

95 75 73 IN

FB_B_MA<0>

FB_B_MA<1>

FB_B_UMA<2>

FB_B_UMA<3>

FB_B_UMA<4>

FB_B_UMA<5>

FB_B_MA<6>

FB_B_MA<7>

FB_B_MA<8>

FB_B_MA<9>

FB_B_MA<10>

FB_B_MA<11>

FB_B_CKE

FB_B_MA<12>

95 73

IN

95 73

75 73

IN

IN

95 75 73

IN

95 75 73

95 75 73

IN

IN

FB_B_CLK_P<1>

FB_B_CLK_N<1>

FB_B_CS0_L

FB_B_WE_L

FB_B_CAS_L

FB_B_RAS_L

95 75 73

IN

95 73 IN

95 73

IN

95 73

95 73

IN

IN

FB_B_DRAM_RST

95 73

OUT

95 73 OUT

95 73

OUT

95 73

OUT

FB_B_RDQS<6>

FB_B_RDQS<5>

FB_B_RDQS<4>

FB_B_RDQS<7>

FB_B_WDQS<6>

FB_B_WDQS<5>

FB_B_WDQS<4>

FB_B_WDQS<7>

95 75 73

IN

95 75 73

95 75 73

IN

IN

FB_B_BA<0>

FB_B_BA<1>

FB_B_BA<2>

1

R8549

2

100

5%

1/16W

MF-LF

402

7 6

5 4 3

75 74 73 72 47 9 8

PP1V8_S0GPU_ISNS

75 74 73 72 47 9 8

PP1V8_S0GPU_ISNS

C8570

10UF

20%

6.3V

X5R

603

1

2

75 27 9

GPU_FB_B_VREF_DIV

1

2

C8571

0.1uF

10%

16V

X5R

402

R8580

1

549

1%

1/16W

MF-LF

402

2

R8581

1

1.33K

1%

1/16W

MF-LF

402

2

C8550

10UF

20%

6.3V

X5R

603

1

2

1

2

C8572

0.1uF

10%

16V

X5R

402

R8582

1

931

1%

1/16W

MF-LF

402

2

1

2

C8551

0.1uF

10%

16V

X5R

402


1

2

C8573

0.1uF

10%

16V

X5R

402

1

2

C8581

0.01uF

10%

16V

CERM

402

1

2

C8552

0.1uF

10%

16V

X5R

402

1

2

C8574

0.1uF

10%

16V

X5R

402

FB_B1_VREF

R8583

1

549

1%

1/16W

MF-LF

402

2

R8584

1

1.33K

1%

1/16W

MF-LF

402

2

1

2

C8553

0.1uF

10%

16V

X5R

402

1

2

C8560

0.1uF

10%

16V

X5R

402

U8500.J1

1

2

C8575

0.1uF

10%

16V

X5R

402

1

2

C8554

0.1uF

10%

16V

X5R

402

1

2

C8565

0.1uF

10%

16V

X5R

402

U8500.J12

FB_B3_VREF

R8585

1

931

1%

1/16W

MF-LF

402

2

1

2

C8576

0.1uF

10%

16V

X5R

402

1

2

C8582

0.01uF

10%

16V

CERM

402

OMIT

CRITICAL

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

A1

A12

C1

C4

C9

C12

E1

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

A2

A11

F1

F12

M1

M12

V2

V11

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

K1

K12

VDDA0

VDDA1

U8550

BGA

(2 OF 2)

VSS0

VSS1

A3

A10

G1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

G12

L1

L12

V3

V10

VSSA0

VSSA1

J1

J12

G2

G11

L2

L11

P1

P4

P9

P12

B1

B4

B9

B12

D1

D4

D9

D12

T1

T4

T9

T12

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

H1

H12

VREF0

VREF1

5

VRAM4

R8592

1

121

1%

1/16W

MF-LF

402

2

2 1

Page Notes


- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VREF_B


(NONE)


VRAM4

1

D

C

VRAM4

R8594

1

121

1%

1/16W

MF-LF

402

VRAM4 2

1

R8593

121

1%

2

1/16W

MF-LF

402

R8598 1

243

1%

1/16W

MF-LF

402

2

R8596

1

243

1%

1/16W

VRAM4

MF-LF

402

2

1

R8595

121

1%

2

1/16W

MF-LF

402

FB_B1_ZQ

FB_B1_MF

FB_B1_SEN

1 R8599

2

100

5%

1/16W

MF-LF

402

FB_B3_VREF_UNTERM_L

FB_B1_VREF_UNTERM_L

FB_B_CLK1_TERM

VOLTAGE=0.9V

C8596

0.01UF

10%

16V

CERM

402

1

2

75 74 73

77 76

IN

Q8550

SSM6N15FEAPE

SOT563

FB_VREF_UNTERM

2

G

1

R8597

243

1%

2

1/16W

MF-LF

402

OMIT

CRITICAL

K9

H11

K10

M4

K11

L9

H9

M9

K4

H2

K3

L4

K2

J3

A0

A1

A2

A3

A4

A5

A6

A7

A8/AP

A9

A10

A11

CKE

J11

J10

F4

H4

F9

H10

A4

A9

V4

V9

CK

CK*

CS0*

WE*

CAS*

RAS*

ZQ

MF

SEN

RESET

D3

D10

P10

P3

RDQS0

RDQS1

RDQS2

RDQS3

U8550

BGA

(1 OF 2)

A12/CS1*

D2

D11

P11

P2

WDQS0

WDQS1

WDQS2

WDQS3

G9

G4

H3

BA0

BA1

BA2

NC

J2

RFU

DM0

DM1

DM2

DM3

E3

E10

N10

N3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

B2

B3

C2

C3

E2

F3

F2

G3

DQ7

DQ8

DQ9

DQ10

B11

B10

C11

C10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

E11

F10

F11

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

G10

M11

L10

N11

M10

R11

R10

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

T11

T10

M2

L3

N2

M3

DQ29

DQ30

DQ31

R2

R3

T2

T3

D

6

S

1

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_DQM_L<4>

FB_B_DQM_L<7>

FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<48>

FB_B_DQ<51>

FB_B_DQ<53>

FB_B_DQ<55>

FB_B_DQ<54>

FB_B_DQ<52>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<40>

FB_B_DQ<47>

FB_B_DQ<44>

FB_B_DQ<45>

FB_B_DQ<43>

FB_B_DQ<46>

FB_B_DQ<34>

FB_B_DQ<35>

FB_B_DQ<33>

FB_B_DQ<32>

FB_B_DQ<37>

FB_B_DQ<38>

FB_B_DQ<39>

FB_B_DQ<36>

FB_B_DQ<56>

FB_B_DQ<57>

FB_B_DQ<63>

FB_B_DQ<59>

FB_B_DQ<58>

FB_B_DQ<62>

FB_B_DQ<61>

FB_B_DQ<60>

Q8550

SSM6N15FEAPE

SOT563

5

G

IN

IN

IN

IN

73 95

73 95

73 95

73 95

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

73 95

D

3

S

4

GDDR3 Frame Buffer B (Top)









SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

75

OF

97

B

A

4 3 2

D

C

B

A

8

Page Notes


- =PP3V3_GPU_VDD33

- =PP3V3_GPI_MIO

- =PP1V2_GPU_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_VID_PLLVDD


(NONE)


(NONE)

76 70 69 8 6

PP3V3_S0GPU

81 79 77

Typically <??mA

81 79 77 76 70 69 8 6

PP3V3_S0GPU

83 78 76 73 71 8

PP1V1_S0GPU_REG

83 78 76 73 71 8

PP1V1_S0GPU_REG

83 78 76 73 71 8

PP1V1_S0GPU_REG

1

2

C8600

0.47UF

10%

6.3V

CERM-X5R

402

R8620 1

49.9

1%

1/16W

MF-LF

402

2

R8622 1

49.9

1%

1/16W

MF-LF

402

2

C8633

4.7UF

20%

6.3V

CERM

603

1

2

C8637

4.7UF

20%

6.3V

CERM

603

1

2

C8643

4.7UF

20%

6.3V

CERM

603

1

2

7

1

2

C8601

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8602

0.47UF

10%

6.3V

CERM-X5R

402

81 79 77 76 70 69 8 6

PP3V3_S0GPU

1 R8621

49.9

2

1%

1/16W

MF-LF

402

GPU_MIOA_PD_VDDQ

GPU_MIOB_PD_VDDQ

GPU_MIOA_PU_GND

GPU_MIOB_PU_GND

1 R8623

49.9

2

1%

1/16W

MF-LF

402

76

76

76

76

110mA

81 79 77 76 70 69 8 6

PP3V3_S0GPU

1

2

C8690

0.022UF

10%

16V

CERM-X5R

402

1

2

C8691

0.022UF

10%

16V

CERM-X5R

402

R8616 1

10K

5%

1/16W

MF-LF

402

2

R8617 1

10K

5%

1/16W

MF-LF

402

2

1

L8630

FERR-220-OHM

2

0402

PP1V1_GPU_PLLVDD_F



VOLTAGE=1.2V

C8630

4.7UF

20%

6.3V

CERM

603

1

2

1

L8635

FERR-220-OHM

2

0402

PP1V1_GPU_H_PLLVDD_F



VOLTAGE=1.2V

C8635

4.7UF

20%

6.3V

CERM

603

1

2

1

L8640

FERR-220-OHM

2

0402

PP1V1_GPU_VID_PLLVDD_F



VOLTAGE=1.2V

C8640

4.7UF

20%

6.3V

CERM

603

1

2

1

2

C8692

0.022UF

10%

16V

CERM-X5R

402

1

2

C8693

0.022UF

10%

16V

CERM-X5R

402

1

2

C8617

0.1uF

10%

16V

X5R

402

65mA

1

2

C8631

0.1uF

10%

16V

X5R

402

25mA

1

2

C8636

0.1uF

10%

16V

X5R

402

50mA

6

1

2

C8641

0.1uF

10%

16V

X5R

402

1

2

C8694

0.1UF

20%

10V

CERM

402

1

2

C8695

0.1UF

20%

10V

CERM

402

1 R8618

10K

2

5%

1/16W

MF-LF

402

1 R8619

10K

2

5%

1/16W

MF-LF

402

1

2

C8696

0.47UF

10%

6.3V

CERM-X5R

402

1

2

C8697

0.47UF

10%

6.3V

CERM-X5R

402

1 R8696

40.2K

1%

1/16W

2

MF-LF

402

1 R8697

40.2K

1%

1/16W

2

MF-LF

402

1

2

C8698

1UF

10%

6.3V

CERM

402

C8610

1UF

10%

6.3V

CERM

402

1

2

5

77

NC_GPU_ROM_CS_L

77

GPU_ROM_SCLK

77

GPU_ROM_SI

77

GPU_ROM_SO

GPU_STRAP_REF_3V3_PD

GPU_STRAP_REF_MIOB_PD

GPU_TESTMODE_PD

GPU_MIOA_VREF

GPU_MIOB_VREF

1

2

C8619

0.1uF

10%

16V

X5R

402

1

R8660

10K

2

5%

1/16W

MF-LF

402

76

GPU_MIOA_PD_VDDQ

76

GPU_MIOA_PU_GND

76

GPU_MIOB_PD_VDDQ

76

GPU_MIOB_PU_GND

95 77 IN

77 OUT

GPU_CLK27M

GPU_XTALOUT

C8611

1UF

10%

6.3V

CERM

402

1

2

77 OUT

95 77 IN

GPU_XTALOUTBUFF

GPU_CLK27M_SS

4

J25

NC

J26

NC

AK14

K9

AA9

AB9

W9

Y9

AP35

N5

AF1

J9

J10

J11

J12

J13

AF9

AE9

AD9

C3

D4

D3

C4

N9

M9

P9

R9

T9

U9

U5

T5

AA7

AA6

B1

B2

D1

D2

VDD33_1

VDD33_2

VDD33_3

VDD33_4

VDD33_5

RFU0

RFU1

RFU0_GND

RFU1_GND

ROM_CS*

ROM_SCLK

ROM_SI

ROM_SO

STRAP_REF_3V3

STRAP_REF_MIOB

(IPD)

MIOA_VDDQ_1

MIOA_VDDQ_2

MIOA_VDDQ_3

MIOA_VDDQ_4

OMIT

U8000

NB9P-GS

BGA

SYMBOL 6 OF 9

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

HDA_SDI

HDA_SDO

HDA_SYNC

HDA_BCLK

HDA_RST*

SPDIF

A5

C7

B7

A7

D7

D6

H7

J4

J6

L1

L2

L4

M4

L7

L5

K6

L6

M6

K1

K2

K3

H3

H2

H1

H4

H5

H6

J7

K4

K5

A4

BUFRST*

MIOB_VDDQ_1

MIOB_VDDQ_2

MIOB_VDDQ_3

MIOB_VDDQ_4

TESTMODE

MIOA_VREF

MIOB_VREF

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST*

MIOA_CAL_PD_VDDQ

MIOA_CAL_PU_GND

MIOB_CAL_PD_VDDQ

MIOB_CAL_PU_GND

SP_PLLVDD

PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

MIOA_CLKIN

MIOA_CLKOUT

MIOA_CLKOUT*

MIOA_CTL3

MIOA_DE

MIOA_D0

MIOA_D1

MIOA_D2

MIOA_D3

MIOA_D4

MIOA_D5

MIOA_D6

MIOA_D7

MIOA_D8

MIOA_D9

MIOA_D10

MIOA_D11

MIOA_D12

MIOA_D13

MIOA_D14

MIOA_HSYNC

MIOA_VSYNC

N4

R4

T4

P5

N2

N1

P4

P1

P2

P3

T3

R6

T6

N6

N3

L3

T2

T1

U4

U1

U2

U3

AP14

AN14

AN16

AR14

AP16

XTAL_OUTBUFF

XTAL_SSIN

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CLKOUT*

MIOB_CTL3

MIOB_DE

MIOB_D0

MIOB_D1

MIOB_D2

MIOB_D3

MIOB_D4

MIOB_D5

MIOB_D6

MIOB_D7

MIOB_D8

MIOB_D9

MIOB_D10

MIOB_D11

MIOB_D12

MIOB_D13

MIOB_D14

MIOB_D15

MIOB_D16

MIOB_D17

MIOB_HSYNC

MIOB_VSYNC

W7

V7

W1

W2

U6

W6

Y6

W5

AB1

AC4

AC1

AC2

AC3

AE3

AE2

AE1

V4

W4

W3

Y5

Y1

Y2

Y3

AB3

AB2

THERMDP

THERMDN

B5

B4

C5

PGOOD_OUT*

3

NC_GPU_GPIO_0

DP_EG_HPD

TP_LVDS_EG_BKL_PWM

EG_LCD_PWR_EN

EG_BKLT_EN

TP_GPU_GSTATE<0>

GPU_GPIO_6

GPIO7_FBVDD_ALTVO

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_R_L

FB_VREF_UNTERM

GPU_VCORE_VID0

GPU_VCORE_VID1

GPU_VCORE_VID2

TP_GPU_VCORE_VID3

NC_GPU_GPIO_15

GPU_GPIO_16

NC_GPU_GPIO_17

NC_GPU_GPIO_18

NC_GPU_GPIO_19

NC_GPU_GPIO_20

NC_GPU_GPIO_21

NC_GPU_GPIO_22

NC_GPU_GPIO_23

NC_CPU_HDA_SDI

NC_CPU_HDA_SD0

NC_CPU_HDA_SYNC

NC_CPU_HDA_BCLK

NC_CPU_HDA_RST_L

NC_GPU_SPDIF

TP_GPU_BUFRST_L

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

77

77

77

OUT

OUT

77

77

77

77 81

77

77 84

77 84

77

77

77 83

77

77

77

77

77

77

77

77

77

73 74 75 77

77 79

77 79

77 79

77

77

77

IN 77

OUT

JTAG_MCP_TCK

GPU_JTAG_TDI

TP_GPU_JTAG_TDO

GPU_JTAG_TMS

JTAG_MCP_TRST_L

NC_GPU_MIOA_CLKIN

NC_GPU_MIOA_CLKOUT_P

NC_GPU_MIOA_CLKOUT_N

NC_GPU_MIOA_CTL3

TP_GPU_MIOA_DE

TP_GPU_MIOA_D<0>

TP_GPU_MIOA_D<1>

TP_GPU_MIOA_D<2>

TP_GPU_MIOA_D<3>

TP_GPU_MIOA_D<4>

TP_GPU_MIOA_D<5>

TP_GPU_MIOA_D<6>

TP_GPU_MIOA_D<7>

TP_GPU_MIOA_D<8>

TP_GPU_MIOA_D<9>

NC_GPU_MIOA_D<10>

NC_GPU_MIOA_D<11>

NC_GPU_MIOA_D<12>

NC_GPU_MIOA_D<13>

NC_GPU_MIOA_D<14>

NC_GPU_MIOA_HSYNC

NC_GPU_MIOA_VSYNC

NC_GPU_MIOB_CLKIN

NC_GPU_MIOB_CLKOUT_P

NC_GPU_MIOB_CLKOUT_N

NC_GPU_MIOB_CTL3

NC_GPU_MIOB_DE

NC_GPU_MIOB_D<0>

NC_GPU_MIOB_D<1>

NC_GPU_MIOB_D<2>

NC_GPU_MIOB_D<3>

NC_GPU_MIOB_D<4>

NC_GPU_MIOB_D<5>

NC_GPU_MIOB_D<6>

NC_GPU_MIOB_D<7>

NC_GPU_MIOB_D<8>

NC_GPU_MIOB_D<9>

NC_GPU_MIOB_D<10>

NC_GPU_MIOB_D<11>

NC_GPU_MIOB_D<12>

NC_GPU_MIOB_D<13>

NC_GPU_MIOB_D<14>

GPU_STRAP<0>

GPU_STRAP<1>

GPU_STRAP<2>

NC_GPU_MIOB_HSYNC

NC_GPU_MIOB_VSYNC

GPU_TDIODE_P

GPU_TDIODE_N

TP_GPU_PGOOD_OUT_L

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

IN

OUT

48 77 96

48 77 96

OUT

IN

IN

OUT

IN

IN

6 13 21

6

6

6

6 13 21

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

8

7 6 5 4 3

2 1

D

C

B

NV G96 GPIO/MIO/Misc



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

76

OF

97

2 1

D

C

B

A

8 7 6 5 4 3 2 1

Renamed signals Unused signals

Native Func

76

77

GP

76

77

81

76

77

NC_GPU_GPIO_0

DP_EG_HPD

TP_GPU_GSTATE<0>

HPDC

76

77

LCD0_BL_PWM

TP_LVDS_EG_BKL_PWM

LCD0_VDD

84

76

77

84

76

77

EG_LCD_PWR_EN

EG_BKLT_EN

LCD0_BL_EN

VID0

VID1

76

GPU_GPIO_6

VID2/MEM_VID

83

76

77

GPIO7_FBVDD_ALTVO

GPIOs

NC_GPU_GPIO_0

MAKE_BASE=TRUE

DP_EG_HPD

MAKE_BASE=TRUE

TP_LVDS_EG_BKL_PWM

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

GPIO7_FBVDD_ALTVO

MAKE_BASE=TRUE

IN

76 77 81

Physical

Strapping Pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP 2

STRAP 1

76 77

76 77

76 77 84

76 77 84

76 77

76 77 83

OUT

76 77 79

OUT 76 77 79

OUT

76 77 79

77 76

NC_GPU_GPIO_15

76

GPU_GPIO_16

77 76

NC_GPU_GPIO_17

77 76

NC_GPU_GPIO_18

77 76

NC_GPU_GPIO_19

77 76

NC_GPU_GPIO_20

77 76

NC_GPU_GPIO_21

77 76

NC_GPU_GPIO_22

77 76

NC_GPU_GPIO_23

Strapping Bit 3

XCLK_277

PCI_DEVID[4]

RAMCFG[3]

PCI_DEVID[3]

3GIO_PADCFG[3]

Native Func

HPDE

DVI_MODE0

HDMI_DETECT0

DVI_MODE1

HDMI_DETECT1

HPDD

HPDF

SWAPRDY_A

GP

Strapping Bit 2

TVMODE[2]

SUB_VENDOR

RAMCFG[2]

PCI_DEVID[2]

3GIO_PADCFG[2]

GPIOs

NC_GPU_GPIO_15

MAKE_BASE=TRUE

EG_DP_CA_DET

NC_GPU_GPIO_17

MAKE_BASE=TRUE

NC_GPU_GPIO_18

MAKE_BASE=TRUE

NC_GPU_GPIO_19

MAKE_BASE=TRUE

NC_GPU_GPIO_20

MAKE_BASE=TRUE

NC_GPU_GPIO_21

MAKE_BASE=TRUE

NC_GPU_GPIO_22

MAKE_BASE=TRUE

NC_GPU_GPIO_23


Strapping Bit 1

TVMODE[1]

SLOT_CLK_CFG

RAMCFG[1]

PCI_DEVID[1]

3GIO_PADCFG[1]

Strapping Bit 0

TVMODE[0]

PEX_PLLEN_TERM100

RAMCFG[0]

PCI_DEVID[0]

3GIO_PADCFG[0]

76 77

77

76 77

76 77

76 77

76 77

76 77

76 77

76 77

77 76

GPU_XTALOUT

MAKE_BASE=TRUE

95 77 76

GPU_CLK27M

MAKE_BASE=TRUE

95 77 76

GPU_CLK27M_SS

MAKE_BASE=TRUE

96 77 76 48

GPU_TDIODE_P

MAKE_BASE=TRUE

96 77 76 48

GPU_TDIODE_N

MAKE_BASE=TRUE

81 78 77

LVDS_EG_DDC_CLK

MAKE_BASE=TRUE

81 78 77

LVDS_EG_DDC_DATA

MAKE_BASE=TRUE

81 78 77

DP_EG_DDC_CLK

MAKE_BASE=TRUE

81 78 77

DP_EG_DDC_DATA

MAKE_BASE=TRUE

GPU_XTALOUT

GPU_CLK27M

GPU_CLK27M_SS

GPU_TDIODE_P

GPU_TDIODE_N

LVDS_EG_DDC_CLK

LVDS_EG_DDC_DATA

DP_EG_DDC_CLK

DP_EG_DDC_DATA

76 77 76

77

76 77 95

76 77

77 95

76

48 76 77

96

48 77 76

76 77 96

77 76

77 78 81

77 78 81

77 77

78 81

73

77 78 81

77 73

77 73

77 78 73

77

77

78

77 73

77 78 76

77

77

78

77 73

77 78 73

77

NC_GPU_SPDIF

MAKE_BASE=TRUE

NC_CPU_HDA_SDI

MAKE_BASE=TRUE

NC_CPU_HDA_SD0

MAKE_BASE=TRUE

NC_CPU_HDA_SYNC

MAKE_BASE=TRUE

NC_CPU_HDA_BCLK

MAKE_BASE=TRUE

NC_CPU_HDA_RST_L

MAKE_BASE=TRUE

NC_FBA_MA<13>

MAKE_BASE=TRUE

NC_FBB_MA<13>

MAKE_BASE=TRUE

NC_FBA_CMD28

MAKE_BASE=TRUE

NC_FBC_CMD28

MAKE_BASE=TRUE

NC_FBA_CMD29

MAKE_BASE=TRUE

NC_FBC_CMD29

MAKE_BASE=TRUE

NC_FBA_CMD30

MAKE_BASE=TRUE

NC_FBC_CMD30

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L

MAKE_BASE=TRUE

NC_FB_A_CS1_L

MAKE_BASE=TRUE

NC_FB_B_CS1_L

MAKE_BASE=TRUE

77 78

77

78

78 77

78 77

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_GPU_SPDIF

NC_CPU_HDA_SDI

NC_CPU_HDA_SD0

NC_CPU_HDA_SYNC

NC_CPU_HDA_BCLK

NC_CPU_HDA_RST_L

NC_FBA_MA<13>

NC_FBB_MA<13>

NC_FBA_CMD28

NC_FBC_CMD28

76 77

76 77

76 77

76 77

76 77

76 77

73 77

73 77

73 77

73 77


THERM

76

77

FAN_PWM


76

77

77

75

73

74

76

79

76

77

79

76

77

79

76

77

FB_VREF_UNTERM

GPU_VCORE_VID0

GPU_VCORE_VID1

GPU_VCORE_VID2

MEM_VREF

SLI_SYNC

AC_DET

PWR_CTL0

PWR_CTL1

76

77

TP_GPU_VCORE_VID3

Config Straps

81 79 77 76 70 69 8 6

PP3V3_S0GPU

OMIT

R8707

1

2.0K

5%

1/16W

MF-LF

402

2

R8709

1

4.99K

1%

1/16W

MF-LF

402

2


MAKE_BASE=TRUE


MAKE_BASE=TRUE

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

TP_GPU_VCORE_VID3

MAKE_BASE=TRUE

NO STUFF

R8711

1

4.99K

1%

1/16W

MF-LF

402

2

76 77

76 77

73 74 75 76 77

76 77

78 77

NC_GPU_I2CC_SCL

MAKE_BASE=TRUE

78 77

NC_GPU_I2CC_SDA

MAKE_BASE=TRUE

78 77

NC_GPU_I2CD_SCL

MAKE_BASE=TRUE

78 77

NC_GPU_I2CD_SDA

MAKE_BASE=TRUE

78 77

NC_GPU_I2CE_SCL

MAKE_BASE=TRUE

78 77

NC_GPU_I2CE_SDA

MAKE_BASE=TRUE

78 77

NC_GPU_I2CH_SCL

MAKE_BASE=TRUE

78 77

NC_GPU_I2CH_SDA

MAKE_BASE=TRUE

Unused I2C Buses

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_GPU_I2CC_SCL

NC_GPU_I2CC_SDA

NC_GPU_I2CD_SCL

NC_GPU_I2CD_SDA

NC_GPU_I2CE_SCL

NC_GPU_I2CE_SDA

NC_GPU_I2CH_SCL

NC_GPU_I2CH_SDA

I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)

77 78

78 77

78 77

78 77

78 77

TP_LVDS_EG_B_CLK_P

MAKE_BASE=TRUE

TP_LVDS_EG_B_CLK_N

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_FBA_CMD29

NC_FBC_CMD29

NC_FBA_CMD30

NC_FBC_CMD30

NC_GPU_ROM_CS_L

NC_FB_A_CS1_L

NC_FB_B_CS1_L

TP_LVDS_EG_B_CLK_P

TP_LVDS_EG_B_CLK_N





73 77

73 77

73 77

73 77

76 77

73 77

73 77

77 78

77 78

77 78

77 78

77 78

77 78

STRAP 0 USER[3] USER[2] USER[1] USER[0]

76 OUT

GPU_ROM_SI

76

IN

GPU_ROM_SO

76 IN

GPU_ROM_SCLK

81 79 77 76 70 69 8 6

76 BI

76 BI

76 BI

OMIT

R8708

1

45.3K

1%

1/16W

MF-LF

402

2

NO STUFF

R8710

1

2.0K

5%

1/16W

MF-LF

402

2

PP3V3_S0GPU

R8701

1

45.3K

1%

1/16W

MF-LF

402

2

GPU_STRAP<0>

GPU_STRAP<1>

GPU_STRAP<2>

NO STUFF

R8702

1

2.0K

5%

1/16W

MF-LF

402

2

81 79 77 76 70 69 8 6

PP3V3_S0GPU

R8704

1

10K

1%

1/16W

MF-LF

402

2

DP_CA_DET_EG_FET

R8742

100K

1

1%

1/16W

MF-LF

4022

77

EG_DP_CA_DET

R8712

1

15.0K

1%

1/16W

MF-LF

402

2

NO STUFF

R8703

1

10K

1%

1/16W

MF-LF

402

2

NO STUFF

R8705

1

10K

1%

1/16W

MF-LF

402

2

R8706

1

45.3K

1%

1/16W

MF-LF

402

2

Strap S1/S2 Bit[3:0] PU/PD Rval

0 0000 PD 5k

1 0001 PD 10k

2 0010 PD 15k

3 0011 PD 20k

4 0100 PD 25k

5 0101 PD 30k

6 0110 PD 35k

7 0111 PD 45k

PART NUMBER

DP_CA_DET_EG_FET

Q8742

SOD-VESM-HF

SSM3K15FV

114S0378

114S0368

114S0361

114S0343

114S0331

114S0378

114S0361

DP_CA_DET

R8743

0

1 2

5%

1/16W

MF-LF

402

DP_CA_DET_EG

DP_CA_DET_EG_PLD

QTY

1

1

1

1

1

1

1

82 81

28 25 24

80 70 69 68

22 21 19

63 60 59

18 13 8 7 6

PP3V3_S0

55 51 49 48 47 45 43 39

96

37

85

29

84

81 79 77 76 70 69 8 6

PP3V3_S0GPU

81 78 77

IN

81 78 77 BI

81 18 9

IN

81 18 9

BI

IN

18 81 82 84

IN 84

DESCRIPTION

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF







DP_EG_DDC_CLK

R8750 1

4.7K

5%

1/16W

MF-LF

402

2

DP_EG_DDC_DATA

DP_IG_DDC_CLK

DP_IG_DDC_DATA

R8751 1

4.7K

5%

1/16W

MF-LF

402

2

R8752 1

4.7K

5%

1/16W

MF-LF

402

2

R8708

R8708

R8708

R8708

R8708

R8707

R8707

R8753 1

4.7K

5%

1/16W

MF-LF

402

2

G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

Strap S1/S2 Bit[3:0] PU/PD Rval

8 1000 PU 5k

9 1001 PU 10k

A 1010 PU 15k

B 1011 PU 20k

C 1100 PU 25k

D 1101 PU 30k

E 1110 PU 35k

F 1111 PU 45k

REFERENCE DES CRITICAL BOM OPTION

VRAM_512_SAMSUNG

VRAM_512_HYNIX

77 76


MAKE_BASE=TRUE

77 76


MAKE_BASE=TRUE

77 76

NC_GPU_MIOA_CTL3

MAKE_BASE=TRUE

77 76

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

76

TP_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

77 76

NC_GPU_MIOA_CLKIN

MAKE_BASE=TRUE

76

NC_GPU_MIOA_D<14..10>

MAKE_BASE=TRUE

77 76

NC_GPU_MIOA_HSYNC

MAKE_BASE=TRUE

77 76

NC_GPU_MIOA_VSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE



NC_GPU_MIOA_CTL3

TP_GPU_MIOA_DE

GPU_MIOA_D<9..0>

NC_GPU_MIOA_CLKIN

GPU_MIOA_D<14..10>

NC_GPU_MIOA_HSYNC

NC_GPU_MIOA_VSYNC

76 77

76 77

76 77

76 77

76 77

76 77

76 77

NO_TEST=TRUE

VRAM_512_QIMONDA

VRAM_256_SAMSUNG

VRAM_256_HYNIX

VRAM_1024_SAMSUNG

VRAM_1024_QIMONDA

95 77 76 IN

77 76

77 76 OUT

81 79 77 76 70 69 8 6

PP3V3_S0GPU

G96 HDCP ROM APN is 341S2272, blank device is 335S0574.

GPU 27MHz Crystal

GPU_CLK27M

NO STUFF

R8782 1

10M

5%

1/16W

MF-LF

402

2

GPU_XTALOUT

R8783

0

1 2

5%

1/16W

MF-LF

402

GPU_CLK27M_XTALOUT_R

CRITICAL

Y8780

27MHZ

SM-2

NC

NC

C8780

12pF

1 2

5%

50V

CERM

402

NC_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

77 76


MAKE_BASE=TRUE


MAKE_BASE=TRUE

NC_GPU_MIOB_CTL3

MAKE_BASE=TRUE

77 76

NC_GPU_MIOB_DE

MAKE_BASE=TRUE

76

NC_GPU_MIOB_D<14..0>

MAKE_BASE=TRUE

76

77

NC_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

76

77

NC_GPU_MIOB_HSYNC

MAKE_BASE=TRUE

C8781

12pF

1 2

5%

50V

CERM

402

R8796

1

2.2K

5%

1/16W

MF-LF

402

2


R8797

1

2.2K

5%

1/16W

MF-LF

402

2

R8798

R8799

0

1 2

5%

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CLKIN



NC_GPU_MIOB_CTL3

NC_GPU_MIOB_DE

GPU_MIOB_D<14..0>

NC_GPU_MIOB_VSYNC

NC_GPU_MIOB_HSYNC

Unused Clocks

95 77 76

76

GPU_CLK27M_SS

GPU_XTALOUTBUFF

R8780

1

10K

5%

1/16W

MF-LF

402

2

GPU_SS_INT

R8781

1

10K

5%

1/16W

MF-LF

402

2

77 76


0

1 2

5%

1/16W

1/16W

MF-LF 402

SMC_GFX_OVERTEMP_L

MF-LF 402

SMC_GFX_THROTTLE_L

EG_LCD_PWR_EN

OUT

42

OUT 42

OUT

76 77 84

EG_BKLT_EN

OUT 76 77 84

GPIO7_FBVDD_ALTVO

OUT

76 77 83

FB_VREF_UNTERM

OUT 73 74 75 76 77

G96 GPIOs & Straps

76 77

76 77

76 77

76 77

76 77

76 77

76 77



R8792

1

10K

5%

1/16W

MF-LF

402

2

R8793

1

10K

5%

1/16W

MF-LF

402

2

R8794

1

10K

5%

1/16W

MF-LF

402

2

NO STUFF

R8795

1

10K

5%

1/16W

MF-LF

402

2







Isolation FETs for DP MUX inputs

SIZE

D

DRAWING NUMBER

051-7892

REV.

APPLE INC.

A.0.0

SCALE

NONE

SHT OF

77 97

D

C

B

A

8

7 6 5 4 3 2 1

D

C

B

A

8

Page Notes


- =PP1V8_GPU_IFPX

- =PP3V3_GPU_IFPCD_IOVDD


(NONE)


(NONE)

1

R8855

2

1K

1%

1/16W

MF-LF

402

1

R8850

1K

1%

2

1/16W

MF-LF

402

1

R8851

1K

1%

2

1/16W

MF-LF

402

8

7

Sum of peak currents: 240mA

70 8

PP1V8_GPUIFPX

GPU_IFPEF_RSET

GPU_IFPCD_RSET

GPU_IFPAB_RSET

78

78

78

83 76 73 71 8

PP1V1_S0GPU_REG

1

R8856

10K

5%

1/16W

2

MF-LF

402

1

R8857

10K

5%

1/16W

2

MF-LF

402

PP1V1_GPU_IFPEF_IOVDD_F

78

PP1V8_GPU_IFPEF_PLLVDD_F

78

Power inputs must be pulled down if not used

7

6 5 4 3 2 1

6

1

L8800

FERR-220-OHM

2

0402

C8800

4.7UF

20%

6.3V

CERM

603

1

2

?mA peak per diff pair

?mA peak for all pairs

C8801

0.1UF

20%

10V

CERM

402

1

2

C8803

0.1UF

20%

10V

CERM

402

1

2

Place at AG9 Place at AG10

GPU_DACB_VDD

GPU_DACC_VDD

1

R8852

10K

5%

2

1/16W

MF-LF

402

1

R8853

10K

5%

2

1/16W

MF-LF

402

1

R8854

10K

5%

2

1/16W

MF-LF

402

PP1V8_GPU_IFPAB_IOVDD_F



VOLTAGE=1.8V

1

L8805

FERR-220-OHM

2

0402

C8805

4.7UF

20%

6.3V

CERM

603

1

2

80mA peak

C8806

0.1UF

20%

10V

CERM

402

1

2

PP1V8_GPU_IFPAB_PLLVDD_F



VOLTAGE=1.8V

78

PP1V1_GPU_IFPCD_IOVDD_F

78

PP1V1_GPU_IFPEF_IOVDD_F

78

GPU_IFPAB_RSET

78

PP1V8_GPU_IFPCD_PLLVDD_F

78

GPU_IFPCD_RSET

78

PP1V8_GPU_IFPEF_PLLVDD_F

78

GPU_IFPEF_RSET

1

L8810

FERR-220-OHM

2

0402

C8810

4.7UF

20%

6.3V

CERM

603

1

2

?mA peak per diff pair

?mA peak for all pairs

C8811

0.1UF

20%

10V

CERM

402

1

2

C8813

0.1UF

20%

10V

CERM

402

1

2

PP1V1_GPU_IFPCD_IOVDD_F



VOLTAGE=1.1V

81 77

BI

78

LVDS_EG_DDC_CLK

81 77

BI

LVDS_EG_DDC_DATA

Place at AJ8 Place at AK8

I2CS must be pulled up if not used

I2CS addr fixed at 0x9E,0x9F

1

L8815

FERR-220-OHM

2

0402

C8815

4.7UF

20%

6.3V

CERM

603

1

2

160mA peak

C8816

0.1UF

20%

10V

CERM

402

1

2

77 BI

77

BI

PP1V8_GPU_IFPCD_PLLVDD_F



VOLTAGE=1.8V

78

94 53 48 45 42

BI

94 53 48 45 42 BI

NC_GPU_I2CC_SCL

NC_GPU_I2CC_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

I2CS must be pulled up if not used.

I2CS addr fixed at 0x9E,0x9F

77

BI

77 BI

NC_GPU_I2CH_SDA

NC_GPU_I2CH_SCL

81 77 BI

81 77 BI

DP_EG_DDC_CLK

DP_EG_DDC_DATA

77

BI

77 BI

NC_GPU_I2CD_SCL

NC_GPU_I2CD_SDA

77 BI

77

BI

NC_GPU_I2CE_SCL

NC_GPU_I2CE_SDA

GPU_DACA_VDD

AG9

AG10

AJ8

AK8

AE7

AD7

AK9

AJ11

AJ9

AK7

AJ6

AL1

G1

G4

E3

E4

E2

E1

F6

G6

G3

G2

F4

G5

D5

E5

OMIT

U8000

NB9P-GS

BGA

SYMBOL 5 OF 9

IFPA_IOVDD IFPA_TXC

IFPB_IOVDD

IFPC_IOVDD

IFPA_TXC*

IFPA_TXD0

IFPD_IOVDD

IFPE_IOVDD

IFPF_IOVDD

IFPA_TXD0*

IFPA_TXD1

IFPA_TXD1*

IFPAB_PLLVDD

IFPAB_RSET

IFPCD_PLLVDD

IFPCD_RSET

IFPA_TXD2

IFPA_TXD2*

IFPA_TXD3

IFPA_TXD3*

IFPEF_PLLVDD

IFPEF_RSET

IFPB_TXC

IFPB_TXC*

I2CA_SCL

I2CA_SDA

IFPB_TXD4

IFPB_TXD4*

IFPB_TXD5

IFPB_TXD5*

IFPB_TXD6

IFPB_TXD6*

IFPB_TXD7

IFPB_TXD7*

AM11

AM12

AP13

AN13

AN8

AP8

AP10

AN10

AR11

AR10

AN11

AP11

AM8

AL8

AM10

AM9

AK10

AL10

AK11

AL11

AP2

AN3

I2CC_SCL

I2CC_SDA

I2CS_SCL

I2CS_SDA

IFPC_AUX

IFPC_AUX*

IFPC_L0

IFPC_L0*

IFPC_L1

IFPC_L1*

IFPC_L2

IFPC_L2*

IFPC_L3

IFPC_L3*

AM7

AM6

AL5

AM5

AM3

AM4

AP1

AR2

I2CH_SCL

I2CH_SDA

I2CB_SCL

I2CB_SDA

I2CD_SCL

I2CD_SDA

I2CE_SCL

I2CE_SDA

IFPD_AUX

IFPD_AUX*

IFPD_L0

IFPD_L0*

IFPD_L1

IFPD_L1*

IFPD_L2

IFPD_L2*

IFPD_L3

IFPD_L3*

IFPE_AUX

IFPE_AUX*

IFPE_L0

IFPE_L0*

IFPE_L1

IFPE_L1*

IFPE_L2

IFPE_L2*

IFPE_L3

IFPE_L3*

IFPF_AUX

IFPF_AUX*

IFPF_L0

IFPF_L0*

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L2*

IFPF_L3

IFPF_L3*

AP4

AN4

NC

NC

AR8

AR7

NC

AP7

NC

AN7

NC

AN5

NC

AP5

NC

AR5

NC

AR4

NC

NC

AE4

AD4

NC

NC

AH6

AH5

NC

AH4

NC

AG4

NC

AF4

NC

AF5

NC

AE6

NC

AE5

NC

NC

AF3

AF2

NC

NC

AL2

AL3

NC

AJ3

NC

AJ2

NC

AJ1

NC

AH1

NC

AH2

NC

AH3

NC

NC

AJ12

DACA_VDD

AK12

NC

AK13

NC

DACA_VREF

DACA_RSET

AC6

DACB_VDD

NC

AC5

NC

AB6

AG7

DACB_VREF

DACB_RSET

DACC_VDD

NC

AK6

NC

AH7

DACC_VREF

DACC_RSET

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

AM15

NC

AM14

NC

AL14

NC

AM13

NC

AL13

NC

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_CSYNC

DACC_RED

DACC_GREEN

DACC_BLUE

DACC_HSYNC

DACC_VSYNC

AA4

NC

AB4

NC

Y4

NC

AB5

NC

AK4

NC

AL4

NC

AJ4

NC

AM1

AM2

NC

NC

LVDS_EG_A_CLK_P

LVDS_EG_A_CLK_N

OUT

OUT

84 95

84 95

LVDS_EG_A_DATA_P<0>

OUT

LVDS_EG_A_DATA_N<0>

OUT

LVDS_EG_A_DATA_P<1>

OUT

LVDS_EG_A_DATA_N<1>

OUT

LVDS_EG_A_DATA_P<2>

OUT

LVDS_EG_A_DATA_N<2>

OUT


OUT


OUT

84 95

84 95

84 95

84 95

84 95

84 95

77

77

TP_LVDS_EG_B_CLK_P

TP_LVDS_EG_B_CLK_N

LVDS_EG_B_DATA_P<0>

OUT

LVDS_EG_B_DATA_N<0>

OUT

LVDS_EG_B_DATA_P<1>

OUT

LVDS_EG_B_DATA_N<1>

OUT

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<2>

OUT


OUT


OUT

OUT

84 95

84 95

84 95

84 95

84 95

84 95

77

77

DP_EG_AUX_CH_P

DP_EG_AUX_CH_N

OUT

OUT

77

77

DP_EG_ML_P<0>

DP_EG_ML_N<0>

DP_EG_ML_P<1>

DP_EG_ML_N<1>

DP_EG_ML_P<2>

DP_EG_ML_N<2>

DP_EG_ML_P<3>

DP_EG_ML_N<3>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

81 95

81 95

81 95

81 95

81 95

81 95

81 95

81 95

5 4 3

1

R8861

1K

5%

1/16W

2

MF-LF

402

NO STUFF

1

R8860

1K

5%

1/16W

2

MF-LF

402

OUT

OUT

81 95

81 95

D

C

B

NV G96 Video Interfaces



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

78

OF

97

2 1

8 7 6 5 4 3

GPU VCore Regulator

D

70 65

51 43

9 8

41

7

40 39 31

64 55 53

PP5V_S3

R8911

1

1 2

5%

1/16W

MF-LF

402

R8904

10

1 2

1%

1/16W

MF-LF

402

PP5V_S5_GFXIMVP6_PVCC



VOLTAGE=5V

C8902

4.7UF

20%

6.3V

X5R-CERM

402

1

2

31

1

2

C8903

0.01uF

10%

16V

CERM

402

CRITICAL

C8931

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

1

2

PP5V_S5_GFXIMVP6_VDD



VOLTAGE=5V

C8901

1UF

10%

10V

X5R

402-1

VDD PVCC

R8905

150K

1 2

1%

1/16W

MF-LF

402

C8904

0.033UF

2 1

10%

16V

X5R

402

GFXIMVP6_RBIAS



1 RBIAS

GFXIMVP6_SOFT

2



SOFT

CRITICAL

U8900

QFN

VIN

ISL6263C UGATE

BOOT

GFXIMVP6_IMON

28 IMON

47

14

18

17

83 67 66 65 64 62 61 46 37 8 7

PPBUS_G3H

86

CRITICAL

C8930

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

1

2

GFXIMVP6_VIN



GFXIMVP6_UGATE



DIDT=TRUE

GFXIMVP6_BOOT



C8932

1UF

10%

25V

C8933

X5R

603-1

1UF

10%

25V

X5R

603-1

C8956

0.22UF

10%

16V

X7R

603

1

2

1

2

23

24

25

26

27

29

30

32

PGOOD

VID0

VID1

VID2

VID3

VID4

VR_ON

AF_EN

FDE

PHASE

LGATE

19

21

GFXIMVP6_PHASE



SWITCH_NODE=TRUE

DIDT=TRUE

GFXIMVP6_LGATE



DIDT=TRUE

69

GPUVCORE_PGOOD

OUT

76 70 69

81

8 6

79 77

C

PP3V3_S0GPU

79 72 46 8

PPVCORE_GPU

R8907 1

10K

5%

1/16W

MF-LF

402

2

1 R8910

10K

5%

1/16W

MF-LF

2

402

84 69

79

79

79

79

79

GFXIMVP6_VID0

GFXIMVP6_VID1

GFXIMVP6_VID2

GFXIMVP6_VID3

GFXIMVP6_VID4

R8924 1

100

1%

1/16W

MF-LF

402 2

IN

GPUVCORE_EN

GFXIMVP6_AF_EN

GFXIMVP6_FDE



71

GPU_VDD_SENSE



VOLTAGE=1.25V

R8920

20

1

5%

1/16W

MF-LF

402

2

1

2

C8920

0.001UF

10%

50V

CERM

402

GFXIMVP6_COMP_RC



1

R8950

374K

1%

1/16W

2

MF-LF

402

5%

50V

CERM

402

96

GFXIMVP6_VSEN_P

71

GPU_GND_SENSE



VOLTAGE=0V

R8925

100

1%

1/16W

MF-LF

402

R8908

20

1

5%

1/16W

MF-LF

402

2

PLACEMENT_NOTE=Place R8920 at U8900

PLACEMENT_NOTE=Place R8908 at U8900

C8950

180PF

2 1

R8909

7.15K

1

1%

1/16W

MF-LF

402

2

1

2

96

GFXIMVP6_VSEN_N



1

2

1

2

C8923

0.001UF

10%

50V

CERM

402

C8921

0.001UF

10%

50V

CERM 2

402

1

(GFXIMVP6_AGND)

GFXIMVP6_VW



C8922

0.001UF

10%

50V

X7R

402

GFXIMVP6_COMP



C8952

68PF

5%

50V

CERM

402-1

B

1 R8951

4.99K

1%

1/16W

MF-LF

402

2

GFXIMVP6_VDIFF_RC



C8951

560PF

1 2

10%

50V

CERM

402

GFXIMVP6_FB



1

R8953

2

2.21K

1%

1/16W

MF-LF

402

GFXIMVP6_VDIFF



8

9

4

5

6

7

VSEN

RTN

VW

COMP

FB

VDIFF

PGND VSS THRM_PAD

XW8900

SM

1 2

VO

OCSET

ISP

ISN

ICOMP

12

3

13

11

10

1

2

C8953

680pF

10%

50V

CERM

402

GFXIMVP6_VO



GFXIMVP6_OCSET



GFXIMVP6_VSUM



GFXIMVP6_DFB



R8900

1

8.66K

2

1%

1/16W

MF-LF

402

1

2

C8934

0.001UF

10%

50V

X7R

402

R8930 1

1K

5%

1/16W

MF-LF

402

2

R8902

9.76K

1%

1/16W

MF-LF

402

2

1

GFXIMVP6_DROOP



C8971

68PF

1 2

5%

50V

CERM

402-1

1

R8901

5.11K

2

1%

1/16W

MF-LF

402

C8972

0.1uF

10%

16V

X5R

402

1

2

GND_GFXIMVP6_AGND



VOLTAGE=0V

4

4

G

G

5

1

R8903 1

1K

1%

1/16W

MF-LF

402

2

C8906

330PF

5%

50V

COG

402

1

2

D

S

5

D

S

1 2 3

CRITICAL

L8920

0.6UH-30A-1.5MOHM

2 3

CRITICAL

Q8950

CSD58856Q5A

MLP5X6-LFPAK-Q5A

1

MPL104-SM

CRITICAL

Q8951

CSD58857Q5

MLP5X6-LFPAK-Q5

2 PPVCORE_GPU_REG_R



GFXIMVP6_PHASE_VSUM



(PPVCORE_GPU_REG)

CRITICAL

R8940

0.001

1%

1W

MF-1

0612

1 2

3 4

GPU VCore Setpoints

C8969

0.001UF

10%

50V

X7R

402

1

2

VID3 VID2 VID1 VID0 Voltage Max Batt Balanced Max perf

A

77 76

IN

77 76

IN

77 76 IN

81 79 77 76 70 69 8 6

PP3V3_S0GPU

GPU_VCORE_VID0

R8986

0

2 1

GPU_VCORE_VID1

5%

1/16W

MF-LF

402

R8990

0

1 2

5%

1/16W

MF-LF

402

GPU_VCORE_VID2

R8994

0

1 2

5%

1/16W

MF-LF

402

GPUVID0_1

R8987

2.2K

1

5%

1/16W

MF-LF

402

2

GPUVID1_1

R8984

2.2K

5%

1/16W

MF-LF

402

GPUVID1_0

R8985

2.2K

5%

1/16W

MF-LF

402

GPUVID2_1

R8982

2.2K

1

5%

1/16W

MF-LF

402

2

GPUVID2_0

R8983

2.2K

5%

1/16W

MF-LF

402

R8980

0

5%

1/16W

MF-LF

402

GFXIMVP6_VID0

GFXIMVP6_VID1

GFXIMVP6_VID2

79

79

79

GFXIMVP6_VID3

GFXIMVP6_VID4

79

79

1 R8988

0

5%

1/16W

MF-LF

2

402

K19 Default Vcore Setpoints

BOM GROUP

GPUVID_0P90V

GPUVID_1P00V

1

1

1

1

1

0

1

1

1

1

0

1

0.90125V

0.92700V

1.00425V

K19

-

-

K19

-

Other VID states may not be valid

BOM OPTIONS

GPUVID2_1,GPUVID1_1,GPUVID0_1

GPUVID2_0,GPUVID1_1,GPUVID0_1

-

-

K19

C8968

10UF

20%

6.3V

X5R

603

1

2

1

2

C8967

4.7UF

10%

6.3V

X5R-CERM

603

8

7 6 5 4 3

2 1

C8966

10UF

20%

6.3V

X5R 2

603

1

1

2

C8965

10UF

20%

6.3V

X5R

603

Vout = 0.90V - 1.00V

PPVCORE_GPU

8 46 72 79

CRITICAL

C8942

330UF

20%

2.0V

POLY-TANT

D2T-SM2

1

2

CRITICAL

1

3 2

C8943

330UF

20%

2.0V

POLY-TANT

D2T-SM2

3

30A max output

(L8920 limit)

D

C

B

GPU (G96) CORE SUPPLY



A

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

79

OF

97

2 1

D

C

B

8 7 6 5 4 3

84 IN

LCD_PWR_EN

R9094

1

10K

5%

1/16W

MF-LF

402 2

81 80

28 25

77

24

70

22

69 68

21 19

63

18

60

13 8

55 51 49 48 47 45 43

96

39

59

7 6

37

85 84

PP3V3_S0

29

82

LCD (LVDS) INTERFACE

1

2

C9009

0.1UF

10%

16V

X5R

402

1

CRITICAL

U9000

ON

FPF1009

MFET-2X2

2 VIN_1

3

VIN_2

VOUT_1 4

GND

6

VOUT_2 5

THRM

PAD

7

1

2

C9011

0.1UF

10%

16V

X5R

402

100K pull-ups are for

Panel has 2K pull-ups

95 81

LVDS_CONN_A_CLK_N

95 81

LVDS_CONN_A_CLK_P 1 2

Place close to the connector

95 81

LVDS_CONN_B_CLK_N

81 7

81 7

1

2

C9012

10UF

20%

6.3V

X5R

603

81 80

28 25

77

24

70

22

69 68

21 19

63

18

60 59

13 8 7 6

55 51 49 48 47 45 43

96

39

85

37 29

84 82

PP3V3_S0 no-panel case (development).

LVDS_DDC_CLK

LVDS_DDC_DATA

CRITICAL

L9010

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

CRITICAL

L9011

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

95 81

LVDS_CONN_B_CLK_P 1 2

Place close to the connector

PP3V3_SW_LCD_UF



VOLTAGE=3.3V

C9001

0.1UF

10%

16V

X5R

402

1

2

CRITICAL

L9000

FERR-250-OHM

1 2

SM

C9002

0.001UF

10%

50V

X7R

402

1

2

R9010 1

100K

5%

1/16W

MF-LF

402

2

1 R9011

100K

5%

1/16W

MF-LF

2

402

C9010

0.001UF

10%

50V

X7R

402

1

2

CRITICAL

J9000

20474-040E-11

F-RT-SM

41

42

95

95

7

PP3V3_SW_LCD



VOLTAGE=3.3V

95 81 7


95 81 7


95 81 7


95 81 7


95 81 7


95 81 7


7

LVDS_CONN_A_CLK_F_N

7

LVDS_CONN_A_CLK_F_P

95 81 7


95 81 7


95 81 7


95 81 7


95 81 7


95 81 7


85 7

85 7

95 7

LVDS_CONN_B_CLK_F_N

95 7

LVDS_CONN_B_CLK_F_P

LED_RETURN_6

LED_RETURN_5

85 7

85 7

85 7

LED_RETURN_4

LED_RETURN_3

LED_RETURN_2

85 7

LED_RETURN_1

85 53 7

PPVOUT_S0_LCDBKLT

NC

NC

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

8

9

10

11

5

6

7

1

2

3

4

12

13

14

15

16

17

43

44

518S0651

A

2

8

7 6 5 4 3

1

D

C

B

LVDS Display Connector



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

80

OF

97

2 1

D

C

B

A

8 7 6 5 4 3 2 1

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

(All 24 resistors)

95 84 IN

LVDS_A_CLK_P

OMIT

R9320

270

1 2

1%

1/16W

MF-LF

402

LVDS_CONN_A_CLK_P

OUT 80 95

95 84 IN

95 84

IN

95 84

IN

95 84

IN

LVDS_A_CLK_N

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<1>

OMIT

R9322

270

1 2

1%

1/16W

MF-LF

402

OMIT

R9330

270

1 2

1%

1/16W

MF-LF

402

R9321

133

1%

1/16W

MF-LF

2

402

SIGNAL_MODEL=EMPTY

LVDS_CONN_A_CLK_N

OMIT

R9325

270

1 2

1%

1/16W

MF-LF

402

1

OMIT

R9327

270

1%

1/16W

MF-LF

402

2

OUT 80 95


OUT

7 80 95

GMUX_2V5

1 R9326

133

SIGNAL_MODEL=EMPTY

2

1%

1/16W

MF-LF

402


OUT

7 80 95


OUT

7 80 95

95 84

IN

95 84

IN

95 84

IN

95 84

IN

95 84 IN

LVDS_A_DATA_N<1>

LVDS_A_DATA_P<2>

LVDS_A_DATA_N<2>

LVDS_B_CLK_P

LVDS_B_CLK_N

OMIT

R9332

270

1 2

1%

1/16W

MF-LF

402

OMIT

R9340

270

1 2

1%

1/16W

MF-LF

402

OMIT

R9342

270

1 2

1%

1/16W

MF-LF

402

R9331

133

SIGNAL_MODEL=EMPTY

2

1%

1/16W

MF-LF

402


OUT

7 80 95

OMIT

R9335

270

1 2

1%

1/16W

MF-LF

402


OUT

7 80 95

1

OMIT

R9337

270

1%

1/16W

MF-LF

402

2

R9336

2

133

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY


OUT

7 80 95

LVDS_CONN_B_CLK_P

OUT

80 95

R9341

2

133

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY

LVDS_CONN_B_CLK_N

OUT 80 95

95 84 IN

LVDS_B_DATA_P<0>

OMIT

R9345

270

1 2

1%

1/16W

MF-LF

402


OUT 7 80 95

95 84 IN

95 84 IN

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<1>

OMIT

R9350

270

1 2

1%

1/16W

MF-LF

402

OMIT

R9347

270

1 2

1%

1/16W

MF-LF

402

R9346

2

133

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY


OUT 7 80 95


OUT 7 80 95

95 84

IN

95 84

IN

95 84 IN

LVDS_B_DATA_N<1>

LVDS_B_DATA_P<2>

LVDS_B_DATA_N<2>

OMIT

R9352

270

1 2

1%

1/16W

MF-LF

402

R9351

2

133

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY


OUT

7 80 95

OMIT

R9355

270

1 2

1%

1/16W

MF-LF

402


OUT

7 80 95

1

OMIT

R9357

270

1%

1/16W

MF-LF

402

2

R9356

2

133

1%

1/16W

MF-LF

402

SIGNAL_MODEL=EMPTY


OUT 7 80 95

PART#

114S0517

QTY

16

DESCRIPTION

114S0174 16

REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

GMUX_2V5

GMUX_1V8

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

DisplayPort Mux

82 81 80

28 25

77 70

24 22

69

21 19

68 63

18 13

60

8 7

59

6

55 51 49 48 47 45 43 39 37 29

96 85 84

PP3V3_S0

1

2

MUXGFX

C9320

0.1UF

20%

10V

CERM

402

90 18 BI

18 9

OUT

77 76 OUT

DP_IG_AUX_CH_N

DP_IG_HPD

R9304 1

100K

5%

1/16W

MF-LF

402

2

DP_EG_HPD

R9306 1

1K

5%

1/16W

MF-LF

402

2

R9305 1

100K

5%

1/16W

MF-LF

402

2

80

25

77 70

24 22

69 68

21 19

63

18

60 59

13 8

55

7 6

51 49 48 47 45 43 39 37 29

96 85 84 82

28

81

PP3V3_S0

DPMUX_EN_S0&DPMUX_EN_PLD

R9302 1

DPMUX_EN_PLD

10K

1%

1/16W

MF-LF

402

2

DP_MUX_EN

R9303

0

1 2

84 IN

5%

1/16W

MF-LF

402

90 9

90 9

IN

IN

90 9

90 9

IN

IN

90 9

90 9

IN

IN

90 9 IN

90 9

IN

90 18 BI

77 18 9

IN

77 18 9 BI

95 78

95 78

IN

IN

95 78 IN

95 78

IN

95 78

95 78

IN

IN

95 78

95 78

IN

IN

95 78

BI

95 78

BI

78 77 IN

78 77

BI

DP_IG_ML_P<0>

DP_IG_ML_N<0>

DP_IG_ML_P<1>

DP_IG_ML_N<1>

DP_IG_ML_P<2>

DP_IG_ML_N<2>

DP_IG_ML_P<3>

DP_IG_ML_N<3>

DP_IG_AUX_CH_P

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_EG_ML_P<0>

DP_EG_ML_N<0>

DP_EG_ML_P<1>

DP_EG_ML_N<1>

DP_EG_ML_P<2>

DP_EG_ML_N<2>

DP_EG_ML_P<3>

DP_EG_ML_N<3>

DP_EG_AUX_CH_P

DP_EG_AUX_CH_N

DP_EG_DDC_CLK

DP_EG_DDC_DATA

C9330

0.1uF

C9331

1

0.1uF

C9335

0.1uF

C9336

1

1

1

0.1uF

DP_MUX_SEL_EG

84

IN

84 82 81 OUT

81 77

84

18

82

OUT

DP_MUX_XSD_L

DPMUX_EN_HPD

R9301

10K

1

1%

1/16W

MF-LF

402

2

DP_HOTPLUG_DET

MAKE_BASE=TRUE

DP_CA_DET

2

96

DP_IG_AUX_CH_C_P

10% 16V X5R 402

2

96

DP_IG_AUX_CH_C_N

10% 16V X5R 402

2

95

DP_EG_AUX_CH_C_P

10% 16V X5R 402

2

10%

95

DP_EG_AUX_CH_C_N

16V X5R 402

1

2

DPMUX_EN_HPD

C9301

1UF

10%

6.3V

CERM-X5R

402

B7

B4

A4

B5

A5

B6

A6

A8

A9

DIN1_0+

DIN1_0-

VDD

MUXGFX

DIN1_1+

DIN1_1-

U9320

CBTL06141EE

BGA

CRITICAL DIN1_2+

DIN1_2-

SIGNAL_MODEL=DPMUX

DIN1_3+

DIN1_3-

DOUT_0+

DOUT_0-

H9

J9

DAUX1+

DAUX1-

H8

J8

DDC_CLK1

DDC_DAT1

J2

HPD_1

DOUT_1+

DOUT_1-

DOUT_2+

DOUT_2-

B8

B9

DIN2_0+

DIN2_0-

D8

D9

DIN2_1+

DIN2_1-

DOUT_3+

DOUT_3-

E8

E9

DIN2_2+

DIN2_2AUX+

AUX-

F8

F9

DIN2_3+

DIN2_3-

H6

J6

DAUX2+

DAUX2-

H5

J5

DDC_CLK2

DDC_DAT2

B2

B1

D2

D1

E2

E1

F2

F1

H2

H1

HPDIN

J1

H3

A1

HPD_2

LO=PORT1

HI=PORT2

GPU_SEL

XSD*

LO=AUX_CH

HI=DDC

DDC_AUX_SEL

TST0

G2

GND

C2

1

2

MUXGFX

C9321

0.1UF

20%

10V

CERM

402

DP_ML_P<0>

DP_ML_N<0>

DP_ML_P<1>

DP_ML_N<1>

DP_ML_P<2>

DP_ML_N<2>

DP_ML_P<3>

DP_ML_N<3>

DP_CA_DET

MAKE_BASE=TRUE

OUT

OUT

82 95

82 95

OUT

OUT

82 95

82 95

OUT

OUT

82 95

82 95

OUT

OUT

82 95

82 95

DP_AUX_CH_C_P

DP_AUX_CH_C_N

BI

BI

82 95

82 95

PLACEMENT_NOTE=Place at U9320

MUXGFX

DP_HPD_R

R9307

1K

1 2

5%

1/16W

MF-LF

402

IN

18 77 81 82 84

82

28

81

25

80 77

24 22

70

21

69 68

19 18

63

13

60

8

59

7 6

55 51 49 48 47 45 43 39

96

37

85

29

84

PP3V3_S0

84

IN

LVDS_DDC_SEL_EG

C9370

0.1UF

20%

10V

CERM

402

1

2

84

IN

LVDS_DDC_SEL_IG

LVDS DDC MUX

79 77 76 70 69 8 6

PP3V3_S0GPU

13

14

VCC

U9370

QFN1

C1 A1

R9372 1

20K

5%

1/16W

MF-LF

402

2

1

2

B1

5

6

12

C2

C3

4

A2

B2

3

A3

B3

8

9

C4 A4

B4

GND THRM

11

10

7 15

R9370 1

20K

5%

1/16W

MF-LF

402

2

1 R9373

20K

5%

2

1/16W

MF-LF

402

1 R9371

2

20K

5%

1/16W

MF-LF

402

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK

LVDS_DDC_CLK

LVDS_EG_DDC_DATA

IN

OUT

18

7 80

BI

77 78

LVDS_IG_DDC_DATA

LVDS_DDC_DATA

IN

77 78

BI

BI

18

7 80

81 82 84

D

C

B

Muxed Graphics Support



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

81

OF

97

8

7 6 5 4 3 2 1

8 7 6 5 4 3 2 1

D

96

34

87

30

70

26

69

24 22

68 64

20 18

54 44

8 7

38 37

PP3V3_S5

PM_SLP_S3_L

84 69 42 37 34 21 7 IN

Port Power Switch

CRITICAL

5

IN

U9480

TPS2051B

SOT23

OUT

1

4

EN OC*

3

GND

2

C9480

10UF

20%

6.3V

X5R

603

1

2

1

2

C9481

0.1UF

20%

10V

CERM

402

PP3V3_S0_DPILIM


TP_DPPWR_OC_L

C9485

0.1UF

20%

10V

CERM

402

1

2

CRITICAL

1

2

C9486

22UF

20%

6.3V

X5R-CERM

603

R9420

100K

1

5%

1/16W

MF-LF

402

2

HDMI_CEC

C

B

R9403

R9413

1 R9425

1M

5%

1/16W

2

MF-LF

402

95 81

IN

95 81 IN

DP_ML_P<3>

DP_ML_N<3>

C9414

1

0.1uF

C9415

1

0.1uF

DP_AUX_CH_C_P

2 DP_ML_C_P<3>

10% 16V X5R 402

2

95

DP_ML_C_N<3>

10% 16V X5R 402

95 81

BI

95 81 BI

96

68

24

63 60

22 21

59 55 51 49

19 18 13 8

48

7 6

47 45 43 39 37 29 28

85 84 82 81 80 77 70

25

69

PP3V3_S0

DP_AUX_CH_C_N

84 81 77 18 OUT

DP_CA_DET

R9443

1

100K

5%

1/16W

MF-LF

402

2

R9442 1

100K

5%

1/16W

MF-LF

402

2

Q9440

2N7002DW-X-G

SOT-363

6

D

S

1

G

2 DP_CA_DET_L_Q

Q9440

2N7002DW-X-G

SOT-363

3

D

S G 5

4

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

0

0

NO STUFF

1 2

NO STUFF

1/16W

1 2

5% 1/16W

MF-LF 402

MF-LF 402

FL9403

12-OHM-100MA

4

TCM1210-4SM

SYM_VER-2

1

3 2

R9421 1

100K

5%

1/16W

MF-LF

402

2

95

DP_ML_CONN_P<3>

95

DP_ML_CONN_N<3>

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

2 IO

9 NC

3

IO 1

NC 10

DP_CA_DET_Q

R9422

1

1M

5%

1/16W

MF-LF

402

2

DP to DVI/HDMI

Cable Adapter

(CA) has 100k pull-up to DP_PWR.

A

96

59 55 51

85 84 82 81

49 48 47 45

22 21 19 18 13 8 7 6

43

80

39 37

77 70

29 28 25 24

69 68 63 60

PP3V3_S0

84 81

OUT

DP_HOTPLUG_DET

R9445 1

10K

5%

1/16W

MF-LF

402

2

R9444 1

10K

5%

1/16W

MF-LF

402

2

Q9441

2N7002DW-X-G

SOT-363

6

D

S

1

G 2 DP_HPD_L_Q

3

Q9441

2N7002DW-X-G

SOT-363

D

S

4

G

5 DP_HPD_Q

R9423

100K

1

5%

1/16W

MF-LF

402

2

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

L9400

FERR-120-OHM-3A

2 1

1

2

0603

C9400

0.01UF

20%

50V

CERM

603

PP3V3_S0_DPPWR



VOLTAGE=3.3V

8

7 6 5 4

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

5 IO

6 NC

IO 4

NC 7

3

3

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

2 IO

9 NC

IO 1

NC 10

3

DisplayPort Connector



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

82

OF

97

2 1

D

CRITICAL

J9400

DSPLYPRT-M97-1

F-RT-THSM

2

4

6

8

10

12

14

16

18

20

BOT ROW

TH PINS

TOP ROW

SM PINS

HOT_PLUG_DETECT

CONFIG1

GND

ML_LANE0P

CONFIG2

GND

ML_LANE3P

ML_LANE0N

GND

ML_LANE1P

ML_LANE3N ML_LANE1N

GND

AUX_CHP

AUX_CHN

DP_PWR

GND

ML_LANE2P

ML_LANE2N

RETURN

1

3

5

7

9

11

13

15

17

19

SHIELD PINS

22 21

R9401

R9431

0

0

95

DP_ML_CONN_N<1> 2

NO STUFF

1 2

NO STUFF

5% 1/16W

1 2

5% 1/16W

R9430

MF-LF 402

MF-LF 402

0

95

95

DP_ML_CONN_P<0>

DP_ML_CONN_N<0>

95

DP_ML_CONN_P<1>

FL9401

12-OHM-100MA

1

TCM1210-4SM

SYM_VER-2

4

95

DP_ML_CONN_P<2>

95

DP_ML_CONN_N<2>

3

FL9402

12-OHM-100MA

1

TCM1210-4SM

SYM_VER-2

4

2

R9400

0

3

FL9400

12-OHM-100MA

1

TCM1210-4SM

SYM_VER-2

4

2

NO STUFF

1 2

NO STUFF

5% 1/16W

1 2

5% 1/16W

MF-LF 402

MF-LF 402

3

95 7

DP_ML_C_P<0>

95

DP_ML_C_N<0>

95 7

DP_ML_C_P<1>

95

DP_ML_C_N<1>

95 7

DP_ML_C_P<2>

95

DP_ML_C_N<2>

C9410

1

0.1uF

C9411

1

0.1uF

C9412

1

0.1uF

C9413

1

0.1uF

C9416

1

0.1uF

C9417 1

0.1uF

2 DP_ML_P<0>

10% 16V X5R 402

2 DP_ML_N<0>

10% 16V X5R 402

2 DP_ML_P<1>

10% 16V X5R 402

2 DP_ML_N<1>

10% 16V X5R 402

2 DP_ML_P<2>

10% 16V X5R 402

2 DP_ML_N<2>

10% 16V X5R 402

IN 81 95

IN

81 95

IN

81 95

IN 81 95

IN

81 95

IN 81 95

R9402

R9432

0

0

NO STUFF

1 2

NO STUFF

5% 1/16W

1 2

5% 1/16W

MF-LF 402

MF-LF 402

DP_ESD

CRITICAL

D9400

RCLAMP0504F

SC70-6-1

6

1

2 5

4

3

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

5 IO

6 NC

3

IO 4

NC 7

C

B

8 7 6 5 4 3 2 1

D

D

C

B

67 66 65 64 62 61 46 37 8 7

86 79

PPBUS_G3H

CRITICAL

C9540

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

73 71 8

78 76

PP1V1_S0GPU_REG

Vout = 1.103V

6A max output


XW9515

SM

1 2

C9515

<Rb>

10UF

20%

6.3V

X5R

603

<Ra>

2

1 R9520

5.76K

1%

1/16W

MF-LF

402

1

R9521

2

10K

1%

1/16W

MF-LF

402

1

2

P1V1S0_VSNS

1

2

C9520

100PF

5%

50V

CERM

402

CRITICAL

C9510

330UF

20%

2.0V

POLY-TANT

B2-SM

NO STUFF

1

2

CRITICAL

L9510

3.3UH-3.5A

1

PCMB053T

2

1

2

C9545

1UF

10%

25V

X5R

603-1

Q9510

CRITICAL

SI7904BDN

PWRPK-1212-8

D

Vout = 0.7V * (1 + Ra / Rb)

(Rb should be between 10K and 100K)

Q9510

CRITICAL

SI7904BDN

PWRPK-1212-8

D

PLACEMENT_NOTE=Place XW9515 next to C7615

S

S

G 4

R9500

4.7

2 1

5%

1/16W

MF-LF

402

P1V1GPU_DRVH



GATE_NODE=TRUE DIDT=TRUE

PVIN_S0GPU_P1V1

CRITICAL

C9590

22UF

20%

25V

POLY-TANT

CASE-D2-SM

1

2

1

2

C9595

1UF

10%

25V

X5R

603-1

G 2 P1V1GPU_DRVL




C9530

0.1UF

10%

50V

X7R

603-1

1

2

P1V1GPU_VBST



P1V1GPU_LL




1

P1V1GPU_VFB

P1V1GPU_TRIP

R9535

280K

2

1%

1/16W

MF-LF

402

PP5V_S0

7 8 39 44 49 51 63 66 67 70 85 C9500

10UF

10%

25V

X5R

805

1

2

C9501

1UF

10%

10V

X5R

402-1

1

2

12

29

4

20

2

6

17

15

16

18

10

14

9

11

VIN

BOOT1

UGATE1

PHASE1

LGATE1

OUT1

EN1

BYP

FB1

ILIM1

SKIP*

EN_LDO

SECFB

TON

PVCC VCC

(Internal 10-ohm path

from PVCC to VCC)

PP5V_S0GPU_P1V1P1V8_VCC



VOLTAGE=5V

PP5V_S0GPU_VREF

VREF3

C9504

1UF

10%

10V

X5R

402-1

1

2

C9503

1UF

10%

10V

X5R

402-1

1

2

LDO

OMIT

U9500

LDOREFIN

BOOT2

UGATE2

PHASE2

ISL6236

LGATE2

QFN

OUT2

THRM_PAD GND

EN2

REFIN2

ILIM2

REF

POK1

POK2

PGND

7

8

24

26

25

23

30

27

32

31

1

13

28

NC

(SGND)

(=PP1V8FB_S0_REG)

GPU_P1V8_REFIN

P1V8FB_TRIP

R9585

1

130K

1%

1/16W

MF-LF

402

2

P1V8FB_VBST



PP2V_S0GPU_P1V8_REF

VOLTAGE=2V

<Ra>

R9563 1

14.0K

1%

1/16W

MF-LF

402

2

1

2

C9580

0.1UF

10%

50V

X7R

603-1

CRITICAL

Q9560

FDMS9600S

P1V8FB_DRVH




P1V8FB_DRVL




P1V8FB_LL




P1V8_GPU_VSNS

1

8

MLP

9 4 3 2

Q1

Q2

7 6 5

10

SW

1

CRITICAL

L9560

2.2UH-14A

MMD06CZ-SM

XW9565

SM

2 1

PLACEMENT_NOTE=Place next to C7665

2

GND_P1V1P1V8_SGND



VOLTAGE=0V

XW9500

1

SM

2

1

2

C9585

0.1UF

20%

10V

CERM

402

<Rb>

R9564

1

127K

1%

1/16W

MF-LF

402

2

1

2

C9561

0.0022UF

10%

50V

CERM

402

1 R9562

78.7K

2

1%

1/16W

MF-LF

402

GPUFB_VID_L

3 D

Q9565

SSM3K15FV

SOD-VESM-HF

2

S G 1

GPIO7_FBVDD_ALTVO

76 77

84 69 IN

69 OUT

84 69 9

OUT

84 70 69

IN

P1V1_GPU_EN

P1V1GPU_PGOOD

PM_ALL_GPU_PGOOD

P1V8_S0GPU_EN

CRITICAL

C9560

220UF

20%

2.5V

POLY-TANT

CASE-B2-SM2

1

2

PP1V8_S0GPU_ISNS_R

Vout = 1.8V

8 47

10.5A max output


1

2

C9565

10UF

20%

6.3V

X5R

603

C

B

PART NUMBER

353S2312

QTY

1

DESCRIPTION

IC,ISL6236,DUAL PWM CTRL,QFN32

REFERENCE DES

U9500

CRITICAL

CRITICAL

BOM OPTION

A

8

7 6 5 4 3

1.1V / 1V8 FB Power Supply



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

83

OF

97

2 1

8 7 6 5 4 3 2 1

D

C

B

96

80 77 70 69

55 51 49 48

37 29 28 25

18 13

24

8

22

7 6

21 19

47 45 43 39

68 63 60 59

85 84 82 81

PP3V3_S0

1

2

C9610

0.1UF

20%

10V

CERM

402

55 25 18 8 7

87 70 69

PP1V8_S0

87 8

PP1V2_S0

R9640 1

10K

1%

1/16W

MF-LF

402

2

1

2

C9621

0.1UF

20%

10V

CERM

402

C9600

4.7UF

20%

4V

X5R

402

1

2

1 R9645

10K

2

1%

1/16W

MF-LF

402

1

2

C9622

0.1UF

20%

10V

CERM

402

1

2

C9611

0.1UF

20%

10V

CERM

402

1

2

C9623

0.1UF

20%

10V

CERM

402

1

2

C9612

0.1UF

20%

10V

CERM

402

1

2

C9604

0.1UF

20%

10V

CERM

402

1

2

C9624

0.1UF

20%

10V

CERM

402

1

2

C9613

0.1UF

20%

10V

CERM

402

1

2

C9605

0.1UF

20%

10V

CERM

402

1

2

C9625

0.1UF

20%

10V

CERM

402

1

2

C9614

0.1UF

20%

10V

CERM

402

1

2

C9606

0.1UF

20%

10V

CERM

402

1

2

C9626

0.1UF

20%

10V

CERM

402

1

2

C9615

0.1UF

20%

10V

CERM

402

1

2

C9607

0.1UF

20%

10V

CERM

402

84 6

19 9 6

IN

17 9 6

OUT

19 9 6 IN

JTAG_GMUX_TCK

JTAG_GMUX_TDI

JTAG_GMUX_TDO

JTAG_GMUX_TMS

GMUX_TOE

GMUX_CFG0

NO STUFF

R9641 1

10K

1%

1/16W

MF-LF

402

2

NO STUFF

1 R9646

10K

2

1%

1/16W

MF-LF

402

86 9

OUT

85 84

84 81

OUT

OUT

84 81

81

OUT

OUT

84 81

84 71 9

OUT

OUT

84

OUT

84

84

OUT

OUT

84

84 9

OUT

OUT

77

80

OUT

OUT

91 44 42 19

BI

91 44 42 19 BI

91 44 42 19 BI

91 44 42 19

BI

91 44 42 19 BI

91 26 19 IN

26

IN

84 18 9 OUT

LCD_BKLT_EN

LCD_BKLT_PWM

LVDS_DDC_SEL_EG

LVDS_DDC_SEL_IG

DP_MUX_EN

DP_MUX_SEL_EG

EG_RESET_L

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

EG_CLKREQ_OUT_L

DP_CA_DET_EG

LCD_PWR_EN

LPC_AD<0>

LPC_AD<1>

LPC_AD<2>

LPC_AD<3>

LPC_FRAME_L

LPC_RESET_L

LPC_CLK33M_GMUX

GMUX_INT

NO STUFF

1

R9647

10K

2

1%

1/16W

MF-LF

402

90 84 18 IN

90 84 18 IN

90 84 18 IN

90 84 18 IN

90 84 18 IN

90 84 18

IN

90 84 18 IN

90 84 18 IN

90 84 18

IN

90 84 18 IN

90 84 18 IN

90 84 18

IN

90 84 18

IN

90 84 18 IN

9

OUT

26 IN

84

IN

83 69 9

IN

84

IN

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<2>

TP_GMUX_PL10A

TP_GMUX_PL10B

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<1>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

TP_LVDS_MUX_SEL_EG

TP_GMUX_PL18B_VSYNC

GMUX_PCIE_RESET_L

GMUX_PM_SLP_S3_L

PM_ALL_GPU_PGOOD

EG_CLKREQ_IN_L

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

1

2

C9628

0.1UF

20%

10V

CERM

402

1

2

C9616

0.1UF

20%

10V

CERM

402

1

2

C9608

0.1UF

20%

10V

CERM

402

K14

L13

K13

L12

K2

TCK

TDI

TDO

TMS

TOE

K1 CFG0

1

2

C9629

0.1UF

20%

10V

CERM

402

1

2

C9617

0.1UF

20%

10V

CERM

402

1

2

C9609

0.1UF

20%

10V

CERM

402

F3

G2

H2

G3

H1

H3

L1

L3

K3

L2

N1

P1

B1

B2

C2

D3

D1

E1

D2

E3

F1

G1

PL14B

PL15A

PL15B

PL16A

PL16B

PL18A

PL18B

PL19A

PL19B

PL32A

PL32B

PL2A

PL2B

PL10A

PL10B

PL11A

PL11B

PL12A

PL12B

PL13A

PL13B

PL14A

PB19A

PB19B

PB20A

PB20B

PB30A

PB30B

PB31A

PB31B

PB32A

PB32B

PB2A

PB2B

PB14A

PB14B

PB15A

(OD)

PB15B

PB16A

PB16B

PB17A

PB17B

PB18A

PB18B

(OD)

M6

P7

M7

N7

N8

P9

N9

P10

M10

P12

P13

N12

P14

P2

N2

P4

N4

N3

M4

P5

M5

P6

VCC

GMUX CPLD

1

2

C9630

0.1UF

20%

10V

CERM

402

VCCAUX

A

42 37 34 21 7

82 69

IN

PM_SLP_S3_L

GND

PM_SLP_S3_L Isolation

82 81 80 77 70 69 68 63 60 59

28 25 24

55 51

22

49

21 19

48 47

18

45

13

43

8 7

39 37

6

29

96 85 84

PP3V3_S0

Q9670

SSM6N15FEAPE

SOT563

1 R9670

10K

2

1%

1/16W

MF-LF

402

GMUX_PM_SLP_S3_L

MAKE_BASE=TRUE

84

GMUX_PM_SLP_S3_L

84

PART#

336S0025

341S2479

QTY DESCRIPTION

1

1

IC,XP2-5,HF,CPLD,BLANK

IC,CPLD,LATTICE,132CSBGA,K19

U9600

XP28

CSBGA-HF

C9631

0.1UF

20%

10V

CERM

402

1

2

OMIT

CRITICAL

L9631

FERR-220-OHM

2



VOLTAGE=3.3V

0402

L9627

FERR-220-OHM

2



0402

VOLTAGE=3.3V

1

2

C9627

0.1UF

20%

10V

CERM

402

VCCJ

G12

G13

H13

H12

H14

J12

L14

M13

N14

N13

A14

B14

D12

D13

D14

E14

E12

F12

F14

G14

PR2A

PR2B

PR10A

PR10B

PR11A

PR11B

PR12A

PR12B

PR13A

PR13B

PR14A

PR14B

PR15A

PR15B

PR16A

PR16B

PR18A

PR18B

PR30A

PR30B

A7

C8

C9

A8

B9

A9

C10

B10

A10

A11

B12

B13

A13

A2

A3

A1

B3

C5

A5

B6

C7

A6

PT2A

PT2B

PT3A

PT3B

PT4A

PT4B

PT14A

PT14B

PT15A

PT15B

PT16A

PT16B

PT17A

PT17B

PT18A

PT18B

PT19A

PT19B

PT20A

PT20B

PT32A

PT32B

84 6

JTAG_GMUX_TCK


U9600

U9600

CRITICAL

CRITICAL

TABLE_5_HEAD

BOM OPTION

TABLE_5_ITEM

GMUX_5K_BLANK

GMUX_PROG

TABLE_5_ITEM

PP3V3_S0

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<1>

LVDS_B_DATA_N<1>

LVDS_B_DATA_P<2>

LVDS_B_DATA_N<2>

GMUX_PM_SLP_S3_L

GMUX_DEBUG_RESET_L

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<1>

LVDS_A_DATA_N<1>

LVDS_A_DATA_P<2>

LVDS_A_DATA_N<2>

TP_GMUX_PT20A

TP_GMUX_PT20B

TP_GMUX_PT32A

TP_GMUX_PT32B

DP_CA_DET

DP_HOTPLUG_DET

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_N<2>

LVDS_EG_B_DATA_P<0>

LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<2>

LVDS_EG_A_CLK_P

LVDS_EG_A_CLK_N

LVDS_IG_PANEL_PWR

EG_LCD_PWR_EN

LVDS_IG_BKL_ON

EG_BKLT_EN

OUT

OUT

OUT

81 95

81 95

81 95

OUT

OUT

OUT

IN

81 95

81 95

81 95

84

IN

OUT

OUT

84

81 95

81 95

OUT

OUT

OUT

OUT

81 95

81 95

81 95

81 95

OUT

OUT

OUT

81 95

81 95

81 95

OUT

81 95

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

18 77 81 82

81 82

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

9 18

76 77

9 18

76 77

GMUX_JTAG_TCK Inversion

3 D

4

S

Q9670

SSM6N15FEAPE

SOT563

G 5

LVDS Receiver Termination

59 60 63 68 69 70 77 80 81 82

6 7 8 13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

84 85 96

90 84 18

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0>

90 84 18

90 84 18

90 84 18

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

90 84 18

90 84 18

90 84 18

95 84 78

95 84 78

95 84 78

95 84 78

95 84 78

95 84 78

95 84 78

84

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<2>

GMUX_DEBUG_RESET_L

R9650

R9651

R9652

R9653

R9654

R9655

R9656

100

100

100

100

100

100

100

1

1

1

1

1

1

1

2

2

2

2

2

2

2

1%

1%

1%

1%

1%

1%

1/16W

1/16W

1/16W

1/16W

1/16W

1/16W

MF-LF

MF-LF

MF-LF

MF-LF

MF-LF

MF-LF

(All 14 resistors)

402

402

402

402

402

402

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2>

1 2

1/16W 402

LVDS_EG_A_CLK_P

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_P<2>

LVDS_EG_B_DATA_P<0>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_P<2>

R9660

R9661

R9662

R9663

R9664

R9665

R9666

100

100

100

100

100

100

1 2 100

1

1

1

1

1

1

2

2

2

2

2

2

1%

1%

1%

1%

1%

1%

1%

1/16W MF-LF 402

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_N<0>

1/16W MF-LF 402

LVDS_EG_A_DATA_N<1>

1/16W MF-LF 402

LVDS_EG_A_DATA_N<2>

1/16W MF-LF 402

LVDS_EG_B_DATA_N<0>

1/16W MF-LF 402

LVDS_EG_B_DATA_N<1>

1/16W MF-LF 402

LVDS_EG_B_DATA_N<2>

1/16W MF-LF 402

81 80 77 70 69

96

68

85

63

84 82

60 59

55

28

51 49 48 47 45 43 39

25 24 22 21 19 18 13

37 29

8 7 6

PP3V3_S0

Required Pullups

R9680 1K

1%

5% 1/16W

MF-LF

MF-LF 402

JTAG_GMUX_TCK

R9690

2

84 6

4.7K

1

5% 1/16W MF-LF 402

18 84 90

18 84 90

18 84 90

18 84 90

18 84 90

18 84 90

18 84 90

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

78 84 95

84 9

EG_CLKREQ_OUT_L

SILK_PART=GMUX_RST

NO STUFF

R9679 1

10K

1%

1/16W

MF-LF

402

2

R9695

10K

1 2

5% 1/16W MF-LF 402

PLACEMENT_NOTE=Place on top side at U9200

84 81

DP_MUX_SEL_EG

84 81

LVDS_DDC_SEL_IG

84 71 9

EG_RESET_L

84 18 9

GMUX_INT

85 84

LCD_BKLT_PWM

84

EG_CLKREQ_IN_L

84

EG_RAIL1_EN

84

EG_RAIL2_EN

84

EG_RAIL3_EN

84

EG_RAIL4_EN

GMUX_JTAG_TCK_L

IN

17

Required Pulldowns

R9681

R9682

R9691

R9692

R9693

10K

1

10K

1

20K

1

100K

1

2

5%

2

5%

84 81

LVDS_DDC_SEL_EG

R9683 10K

1

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

2

5%

100K

NO STUFF

1 2

5%

2

5%

2

5%

NO STUFF

1/16W MF-LF 402

1/16W MF-LF 402

1/16W MF-LF 402

1/16W MF-LF 402

1/16W MF-LF 402

1/16W MF-LF 402

R9694

R9630

100K

1

EG_PWRSEQ_HW

0 1 2

5%

R9631

EG_PWRSEQ_GMUX

0

1 2

5%

R9632

EG_PWRSEQ_GMUX

0

1 2

5%

R9633

EG_PWRSEQ_GMUX

0

1 2

5%

R9634

EG_PWRSEQ_GMUX

0

1 2

5%

2

5%

1/16W

1/16W

1/16W

1/16W

1/16W

1/16W

MF-LF 402

MF-LF 402

MF-LF 402

MF-LF

MF-LF

MF-LF

402

402

402

69

P1V1_GPU_EN

OUT 69 83

P3V3GPU_EN

OUT

GPUVCORE_EN

OUT

The MAKE BASE properties for these signals are on the POWER CONTROL page.

69 70

69 79

69 70 83

1

2

C9691

0.1UF

20%

10V

CERM

402

1

2

1

2

NO STUFF

C9693

0.1UF

20%

10V

CERM

402

NO STUFF

C9692

0.1UF

20%

10V

CERM

402

1

2

NO STUFF

C9694

0.1UF

20%

10V

CERM

402

Graphics MUX (GMUX)

D

C

B



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

84

OF

97

8

7 6 5 4 3 2 1

D

C

B

A

8

8

7 6 5 4 3

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

6

BKL_VLDO_EN_L

3

CRITICAL

Q9701

NTZD3155C

SOT-563-HF

P-CHN

D

5 G

S

4

D

S

G 2

1

N-CHN

R9735

100K

1 2

1%

1/16W

MF-LF

402



BKLT_EN_R

R9701

0

1 2

5%

1/16W

MF-LF

402

PP5V_S0

BKLT_EN

7 8 39 44 49 51 63 66 67 70 83

85

2 1

D

91 60 45 21

91 60 45 21

86 85

PPBUS_S0_LCDBKLT_PWR

96 53

OUT

96 53 OUT

2

XW9721

SM

XW9720

SM

1 2

1

2

XW9722

SM

CRITICAL

1

2

C9712

10UF

10%

25V

X5R

805

1

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

81 80 77 70

28

69 68 63

25 24 22 21

55 51 49 48

60 59

19 18 13

47 45 43 39

96

8 7 6

PP3V3_S0

37 29

84 82

R9716 1

100K

5%

1/16W

MF-LF

402

2

86 85


84

IN

0

1

NO STUFF

1 R9714

IF_SEL=1 FOR SMBUS

2

5% 1/16W MF-LF 402

0

1 2

5% 1/16W MF-LF 402

R9731

2

1%

1/16W

MF-LF

402

1

2

NO STUFF

C9723

0.1UF

10%

25V

X5R

402

R9715

100K

1%

1/16W

MF-LF

402

100K

5%

1/16W

MF-LF

402

2

1

2



VOLTAGE=5V

C9713

0.1UF

10%

25V

X5R

402

7

BKL_VLDO

LCD_BKLT_PWM

R9704

0

1 2

5%

1/16W

MF-LF

402

R9704 SHOULD BE 47K IF RC FILTER IS USED

NO STUFF

1

2

C9704

33PF

5%

50V

CERM

402

BKL_SGND

PLACE XW9700 CLOSE TO C9712 AND C9713

1 R9702

0

5%

1/16W

2

MF-LF

402

1

2

C9714

0.01UF

10%

16V

CERM

402

1

2

C9710

1UF

10%

25V

X5R

603-1

BKL_IF_SEL

BKL_SCL

BKL_SDA

LVDS_BKL_PWM_RC

TP_BKL_FAULT

85

BKLT_EN

1

2

C9711

0.1UF

10%

16V

X5R

402

VDDIO VLDO

U9701

LLP

CRITICAL

VIN

NC

6

ALSO

5

ALSI

20

ADR

SW

24

FB

21

OUT1

12

7

BKL_ISEN1

3

IF_SEL

10

SCLK

11

SDA

2

PWM

OUT2

13

OUT3

14

OMIT

OUT4

16

OUT5

17

7

BKL_ISEN2

7

BKL_ISEN3

7

BKL_ISEN4

7

BKL_ISEN5

7

FAULT

4

EN

OUT6

18

7

BKL_ISEN6

OUT7

19

NC

THRM

PAD

PPVIN_BKL 1 2



VOLTAGE=6V

IHLP2525CZ-SM

R9703

0

5%

1/16W

2

MF-LF

402

XW9710

1

SM

2

CRITICAL

L9701

22UH-2.5A

CRITICAL

D9701

SOD-123

PPBUS_S0_LCDBKLT_PWR_SW



VOLTAGE=50V

1 2

RB160M-60G

SWITCH_NODE=TRUE



R9717

10.2

1 2

0.1%

1/16W

TF

402











R9718

10.2

1 2

0.1%

1/16W

TF

402

R9719

10.2

1 2

0.1%

1/16W

TF

402

R9720

10.2

1 2

0.1%

1/16W

TF

402

R9721

10.2

1 2

0.1%

1/16W

TF

402

R9722

10.2

1 2

0.1%

1/16W

TF

402

1

2

C9796

220PF

10%

50V

X7R-CERM

402

1

2

C9799

2.2UF

10%

100V

X7R

1210

1

2

PPVOUT_S0_LCDBKLT

7 53 80



VOLTAGE=50V

C9797

2.2UF

10%

100V

X7R

1210

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

OUT



7 80

OUT



7 80

OUT



7 80

OUT



7 80

OUT



7 80

OUT



7 80

PART#

353S2670

QTY DESCRIPTION

1 IC,LP8543,WHT LED BKLT,PROD


U9701 CRITICAL

BOM OPTION

7 6

TABLE_5_HEAD

TABLE_5_ITEM

5 4 3

C

B

LCD BACKLIGHT DRIVER



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

85

OF

97

2 1

D

C

8

67 66 65 64 62 61 46 37 8 7

83 79

IN

PPBUS_G3H

86 84 9

IN

LCD_BKLT_EN

26 IN

BKLT_PLT_RST_L

7 6 5 4

1

CRITICAL

F9800

2AMP-32V

2

0402-HF

CRITICAL

Q9806

FDC638APZ_SBMS001

SSOT6-HF

PPBUS_S0_LCDBKLT_FUSED



VOLTAGE=12.6V

R9808

301K

2

1%

1/16W

MF-LF

402

1

2

C9802

0.1UF

10%

16V

X5R

402

PPBUS_S0_LCDBKLT_EN_DIV

Q9807

SSM6N15FEAPE

SOT563

D 3

1 R9809

147K

1%

1/16W

MF-LF

2

402

PPBUS_S0_LCDBKLT_EN_L

5 G S

4

BKLT_EN_L

Q9807

SSM6N15FEAPE

SOT563

D 6

2 G S

1

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

RDS(ON)

LOADING

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.4 A (EDP)

3


OUT



VOLTAGE=12.6V

85

2 1

D

C

B

A

8

1 R9840

4.7K

2

5%

1/16W

MF-LF

402

LCD_BKLT_EN

9 84 86

7 6 5 4 3

B

LCD Backlight Support

SYNC_MASTER=YITE_M98_MLB SYNC_DATE=07/02/2008


A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

86

OF

97

2 1

.

D

C

8 7 6 5 4

1.8V/1.2V S0 SWITCHER

3

37 34

96

30

82

26

70

24 22

69 68

20

64

18 8 7

54 44 38

PP3V3_S5

C9900

10UF

20%

6.3V

X5R

603

1

2

69 IN

P1V2R1V8S0_EN 2

3

5

VIN

U9900

LTC3419

DFN

RUN1 RUN2

MODE

CRITICAL

7

4

SW1

1

VFB1

SW2

6

VFB2

8

THRM

PAD

9

P1V2S0_SW



SWITCH_NODE=TRUE

DIDT=TRUE

P1V2S0_VFB

CRITICAL

L9980

2.2UH-1.2A

1

PCAA031B-SM

2

C9982

10PF

5%

50V

CERM

402

1

2

P1V8S0_SW



SWITCH_NODE=TRUE

DIDT=TRUE

CRITICAL

L9900

2.2UH-1.2A

1 2

PCAA031B-SM

C9901 1

10PF

5%

50V

CERM 2

402

P2V5S0_VFB

<Ra>

1 R9982

280K

1%

1/16W

MF-LF

2

402

<Rb>

1 R9983

280K

2

1%

1/16W

MF-LF

402

PP1V2_S0

8 84

Vout = 1.2V

0.6A max output

(Switcher limit)

1

2 f = 2.25 MHz

C9985

10UF

20%

6.3V

X5R

603

<Ra>

1 R9900

475K

2

1%

1/16W

MF-LF

402

<Rb>

1 R9901

237K

1%

1/16W

2

MF-LF

402

PP1V8_S0

7 8 18 25 55 69 70 84

Vout = 1.8V

0.6A max output

(Switcher limit) f = 2.25 MHz

1

2

C9905

10UF

20%

6.3V

X5R

603

Vout = 0.6V * (1 + Ra/Rb)

B

2 1

D

C

B

A

8

7 6 5 4 3

Misc Power Supplies



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

87

OF

97

2 1

8 7 6

FSB (Front-Side Bus) Constraints

PHYSICAL_RULE_SET

FSB_50S

LAYER

*

ALLOW ROUTE

ON LAYER?

=50_OHM_SE

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM NECK WIDTH

=50_OHM_SE

FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE

MAXIMUM NECK LENGTH

=50_OHM_SE

=50_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD

=1:1_DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP

=STANDARD

TABLE_PHYSICAL_RULE_ITEM


=1:1_DIFFPAIR

D

C

SPACING_RULE_SET

FSB_DATA

FSB_DSTB

FSB_ADDR

FSB_ADSTB

LAYER

*

*

*

*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

=3x_DIELECTRIC

=STANDARD

=2x_DIELECTRIC

TABLE_SPACING_RULE_HEAD

WEIGHT

?

TABLE_SPACING_RULE_ITEM


?

?



?

?


SPACING_RULE_SET

FSB_DATA

FSB_DSTB

FSB_ADDR

FSB_ADSTB

FSB_1X * =STANDARD FSB_1X

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM


=4x_DIELECTRIC

=5x_DIELECTRIC

=3x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 2X signals / groups shown in signal table on right.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

Design Guide recommends each strobe/signal group is routed on the same layer.

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3


WEIGHT

?



?


?

?


?


CPU Signal Constraints

PHYSICAL_RULE_SET

CPU_50S

LAYER

*

ALLOW ROUTE

ON LAYER?

=50_OHM_SE

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM NECK WIDTH MAXIMUM NECK LENGTH

=50_OHM_SE

=27P4_OHM_SE

=50_OHM_SE

=27P4_OHM_SE


=STANDARD

7 MIL


DIFFPAIR NECK GAP

=STANDARD



7 MIL CPU_27P4S *

=27P4_OHM_SE

=27P4_OHM_SE

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SPACING_RULE_SET

CPU_AGTL

CPU_8MIL

CPU_COMP

CPU_GTLREF

CPU_ITP

CPU_VCCSENSE

LAYER

*

*

*

*

*

*


=STANDARD

8 MIL

25 MIL

25 MIL

=2:1_SPACING

25 MIL


WEIGHT

?


?


?


?


?


?


SPACING_RULE_SET

CPU_AGTL

LAYER

TOP,BOTTOM


=2x_DIELECTRIC

SR DG recommends at least 25 mils, >50 mils preferred


WEIGHT

?


Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

PHYSICAL_RULE_SET LAYER

ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

MCP_50S * =50_OHM_SE =50_OHM_SE


=50_OHM_SE =50_OHM_SE


=STANDARD


DIFFPAIR NECK GAP

=STANDARD


B

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING


WEIGHT

?


MCP_FSB_COMP * 8 MIL

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

FSB Clock Constraints


ALLOW ROUTE

ON LAYER?

CLK_FSB_100D *

=100_OHM_DIFF

MINIMUM LINE WIDTH

=100_OHM_DIFF


=100_OHM_DIFF =100_OHM_DIFF


=100_OHM_DIFF


DIFFPAIR NECK GAP


=100_OHM_DIFF



WEIGHT

?


CLK_FSB * =3x_DIELECTRIC


SPACING_RULE_SET

CLK_FSB

LAYER

TOP,BOTTOM


=4x_DIELECTRIC


WEIGHT

?


5

A

8

7 6 5

4 3

FSB_1X

FSB_BREQ0_L

FSB_BREQ1_L

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_CPURST_L

FSB_1X

FSB_1X

CPU_ASYNC

CPU_BSEL

CPU_FERR_L

CPU_ASYNC

CPU_INIT_L

CPU_ASYNC_R

CPU_ASYNC_R

CPU_PROCHOT_L

CPU_PWRGD

CPU_ASYNC

CPU_ASYNC

PM_THRMTRIP_L

FSB_CPUSLP_L

CPU_FROM_SB

CPU_DPRSTP_L

CPU_ASYNC

MCP_CPU_COMP

MCP_CPU_COMP

MCP_CPU_COMP

MCP_CPU_COMP

FSB_CLK_CPU

FSB_CLK_CPU

FSB_CLK_ITP

FSB_CLK_ITP

FSB_CLK_MCP

FSB_CLK_MCP

CPU_IERR_L

CPU / FSB Net Properties

NET_TYPE

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

FSB_DATA_GROUP0

FSB_DATA_GROUP0

FSB_DSTB0

FSB_DSTB0

FSB_DATA_GROUP1

FSB_DATA_GROUP1

FSB_DSTB1

FSB_DSTB1

FSB_DATA_GROUP2

FSB_DATA_GROUP2

FSB_DSTB2

FSB_DSTB2

FSB_DATA_GROUP3

FSB_DATA_GROUP3

FSB_DSTB3

FSB_DSTB3

FSB_ADDR_GROUP0

FSB_ADDR_GROUP0

FSB_ADSTB0

FSB_ADDR_GROUP1

FSB_ADSTB1

PM_DPRSLPVR

(See above)

CPU_GTLREF

CPU_COMP

CPU_COMP

CPU_COMP

CPU_COMP

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TCK

XDP_TRST_L

XDP_BPM_L

XDP_BPM_L5

(FSB_CPURST_L)

CPU_VCCSENSE

CPU_VCCSENSE

(CPU_VCCSENSE)

(CPU_VCCSENSE)

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_27P4S

CPU_50S

CPU_27P4S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_27P4S

CPU_27P4S

CPU_27P4S

CPU_27P4S

FSB_50S

FSB_50S

FSB_DATA

FSB_DATA

FSB_DSTB_50S FSB_DSTB


FSB_50S FSB_DATA

FSB_50S FSB_DATA



FSB_50S

FSB_50S

FSB_DATA

FSB_DATA



FSB_50S FSB_DATA

FSB_50S FSB_DATA



FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_ADDR

FSB_ADDR

FSB_ADSTB

FSB_ADDR

FSB_ADSTB

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

MCP_50S

MCP_50S

MCP_50S

MCP_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

CLK_FSB_100D CLK_FSB






CPU_50S

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

CPU_AGTL

CPU_AGTL

CPU_8MIL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_8MIL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

MCP_FSB_COMP

MCP_FSB_COMP

MCP_FSB_COMP

MCP_FSB_COMP

FSB_D_L<15..0>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_D_L<31..16>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_D_L<47..32>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<63..48>

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_A_L<16..3>

FSB_REQ_L<4..0>

FSB_ADSTB_L<0>

FSB_A_L<35..17>

FSB_ADSTB_L<1>

FSB_ADS_L

FSB_BREQ0_L

FSB_BREQ1_L

FSB_BNR_L

FSB_BPRI_L

FSB_DBSY_L

FSB_DEFER_L

FSB_DRDY_L

FSB_HIT_L

FSB_HITM_L

FSB_LOCK_L

FSB_CPURST_L

FSB_RS_L<2..0>

FSB_TRDY_L

CPU_A20M_L

CPU_BSEL<2..0>

CPU_FERR_L

CPU_IGNNE_L

CPU_INIT_L

CPU_INTR

CPU_NMI

CPU_PROCHOT_L

CPU_PWRGD

CPU_SMI_L

CPU_STPCLK_L

PM_THRMTRIP_L

FSB_CPUSLP_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DPWR_L

MCP_BCLK_VML_COMP_VDD

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

MCP_CPU_COMP_GND

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_CLK_ITP_N

FSB_CLK_MCP_P

FSB_CLK_MCP_N

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

7 10 14

10 14

7 10 14

7 10 14

7 10 14

7 10 14

9 10 14

14

10 14

10 14

10 14

10 14

10 14

7 10 14

7 10 14

7 10 14

9 10 13 14

10 14

10 14

10 14

9 10

10 14

10 14

10 14

9 10 14

9 10 14

10 14 43 63

10 13 14

10 14

10 14

10 14 43

10 14

10 14

9 10 14 63

10 14

14

14

14

14

10 14

10 14

13 14

13 14

14

14

10

CPU_AGTL

CPU_AGTL

CPU_GTLREF

CPU_COMP

CPU_COMP

CPU_COMP

CPU_COMP

CPU_ITP

CPU_ITP

CPU_ITP

CPU_ITP

CPU_ITP

CPU_ITP

CPU_ITP

CPU_ITP

CPU_8MIL

CPU_8MIL

CPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSE

CPU_IERR_L

PM_DPRSLPVR

IMVP_DPRSLPVR

CPU_GTLREF

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TCK

XDP_TRST_L

XDP_BPM_L<4..0>

XDP_BPM_L<5>

XDP_CPURST_L

CPU_VID<6..0>

IMVP6_VID<6..0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VSEN_P

IMVP6_VSEN_N

21 63

63

10 27

10

10

10

10

6 10 13

6 10

6 10 13

6 10 13

6 10 13

10 13

10 13

13

9 11

9 63

11 63

11 63

63

63

2

4 3

1

D

C

B

CPU/FSB Constraints



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

88

OF

97

2 1

8 7 6

Memory Bus Constraints

PHYSICAL_RULE_SET

MEM_40S

LAYER

*

ALLOW ROUTE

ON LAYER?

=40_OHM_SE

MINIMUM LINE WIDTH

=40_OHM_SE

MEM_40S_VDD * =40_OHM_SE =40_OHM_SE

MEM_70D

MEM_70D_VDD

*

*

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF


=40_OHM_SE

=40_OHM_SE

=70_OHM_DIFF

=70_OHM_DIFF

=40_OHM_SE

=40_OHM_SE

=70_OHM_DIFF

=70_OHM_DIFF


=STANDARD

=STANDARD

=70_OHM_DIFF

=70_OHM_DIFF


DIFFPAIR NECK GAP

=STANDARD


=STANDARD



=70_OHM_DIFF


=70_OHM_DIFF

D

C

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD

MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM

MEM_DQS2MEM

MEM_2OTHER

LAYER

*

*

*

*

*

*

*

*

*


=4:1_SPACING

=2:1_SPACING

=2.5:1_SPACING

=1.5:1_SPACING

=3:1_SPACING

=1.5:1_SPACING

=3:1_SPACING

=3:1_SPACING

25 MIL


WEIGHT

?



?

?



?

?


?


?


?



?

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1

MEM_CLK

MEM_CLK

MEM_CLK

MEM_CLK

MEM_CLK

NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

AREA_TYPE

*

*

*

*

*

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK2MEM


MEM_CLK2MEM


MEM_CLK2MEM


MEM_CLK2MEM


MEM_CLK2MEM

NET_SPACING_TYPE1

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

AREA_TYPE

*

*

*

*

*


SPACING_RULE_SET


MEM_CMD2MEM


MEM_CMD2MEM


MEM_CMD2CMD


MEM_CMD2MEM


MEM_CMD2MEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

AREA_TYPE

*

*

*

*

*


SPACING_RULE_SET


MEM_CTRL2MEM


MEM_CTRL2CTRL


MEM_CTRL2MEM


MEM_CTRL2MEM


MEM_CTRL2MEM

NET_SPACING_TYPE1

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

AREA_TYPE

*

*

*

*

*


SPACING_RULE_SET


MEM_DATA2MEM


MEM_DATA2MEM


MEM_DATA2MEM


MEM_DATA2DATA


MEM_DATA2MEM

B

NET_SPACING_TYPE1

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

AREA_TYPE

*

*

*

*

*


SPACING_RULE_SET


MEM_DQS2MEM


MEM_DQS2MEM


MEM_DQS2MEM


MEM_DQS2MEM


MEM_DQS2MEM

NET_SPACING_TYPE1

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

NET_SPACING_TYPE2

*

*

*

*

*

AREA_TYPE

*

*

*

*

*

Need to support MEM_*-style wildcards!

DDR2:

DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.

All DQS pairs should be matched within 100 ps of clocks.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.

A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DDR3:

DQ signals should be matched within 5 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps

No DQS to clock matching requirement.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

A/BA/cmd signals should be matched within 5 ps of CLK pairs.

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

MCP MEM COMP Signal Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

MCP_MEM_COMP * Y 7 MIL


SPACING_RULE_SET


MEM_2OTHER


MEM_2OTHER


MEM_2OTHER


MEM_2OTHER


MEM_2OTHER


7 MIL =STANDARD


=STANDARD


DIFFPAIR NECK GAP

=STANDARD




WEIGHT

?


MCP_MEM_COMP * 8 MIL

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

A

5

8

7 6 5

4 3

MEM_A_CNTL

MEM_A_CNTL

MEM_A_CNTL

MEM_A_CMD

MEM_A_CMD

MEM_A_CMD

MEM_A_CMD

MEM_A_CMD

MEM_A_DQS0

MEM_A_DQS0

MEM_A_DQS1

MEM_A_DQS1

MEM_A_DQS2

MEM_A_DQS2

MEM_A_DQS3

MEM_A_DQS3

MEM_A_DQS4

MEM_A_DQS4

MEM_A_DQS5

MEM_A_DQS5

MEM_A_DQS6

MEM_A_DQS6

MEM_A_DQS7

MEM_A_DQS7

MEM_A_DQ_BYTE0

MEM_A_DQ_BYTE1

MEM_A_DQ_BYTE2

MEM_A_DQ_BYTE3

MEM_A_DQ_BYTE4

MEM_A_DQ_BYTE5

MEM_A_DQ_BYTE6

MEM_A_DQ_BYTE7

MEM_A_DQ_BYTE0

MEM_A_DQ_BYTE1

MEM_A_DQ_BYTE2

MEM_A_DQ_BYTE3

MEM_A_DQ_BYTE4

MEM_A_DQ_BYTE5

MEM_A_DQ_BYTE6

MEM_A_DQ_BYTE7

MEM_B_CLK

MEM_B_CLK

MEM_B_CNTL

MEM_B_CNTL

MEM_B_CNTL

MEM_B_CMD

MEM_B_CMD

MEM_B_CMD

MEM_B_CMD

MEM_B_CMD

MEM_B_DQ_BYTE0

MEM_B_DQ_BYTE1

MEM_B_DQ_BYTE2

MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE4

MEM_B_DQ_BYTE5

MEM_B_DQ_BYTE6

MEM_B_DQ_BYTE7

MEM_B_DQ_BYTE0

MEM_B_DQ_BYTE1

MEM_B_DQ_BYTE2

MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE4

MEM_B_DQ_BYTE5

MEM_B_DQ_BYTE6

MEM_B_DQ_BYTE7

MEM_B_DQS0

MEM_B_DQS0

MEM_B_DQS1

MEM_B_DQS1

MEM_B_DQS2

MEM_B_DQS2

MEM_B_DQS3

MEM_B_DQS3

MEM_B_DQS4

MEM_B_DQS4

MEM_B_DQS5

MEM_B_DQS5

MEM_B_DQS6

MEM_B_DQS6

MEM_B_DQS7

MEM_B_DQS7

MCP_MEM_COMP

MCP_MEM_COMP

Memory Net Properties

NET_TYPE


MEM_A_CLK

MEM_A_CLK

MEM_70D_VDD

MEM_70D_VDD

MEM_CLK

MEM_CLK

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D_VDD

MEM_70D_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_70D

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MCP_MEM_COMP MCP_MEM_COMP

MCP_MEM_COMP MCP_MEM_COMP

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_CLK

MEM_CLK

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_A_CLK_P<5..0>

MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0>

MEM_A_CS_L<3..0>

MEM_A_ODT<3..0>

MEM_A_A<14..0>

MEM_A_BA<2..0>

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_DQ<7..0>

MEM_A_DQ<15..8>

MEM_A_DQ<23..16>

MEM_A_DQ<31..24>

MEM_A_DQ<39..32>

MEM_A_DQ<47..40>

MEM_A_DQ<55..48>

MEM_A_DQ<63..56>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0>

MEM_B_CLK_N<5..0>

MEM_B_CKE<3..0>

MEM_B_CS_L<3..0>

MEM_B_ODT<3..0>

MEM_B_A<14..0>

MEM_B_BA<2..0>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_DQ<7..0>

MEM_B_DQ<15..8>

MEM_B_DQ<23..16>

MEM_B_DQ<31..24>

MEM_B_DQ<39..32>

MEM_B_DQ<47..40>

MEM_B_DQ<55..48>

MEM_B_DQ<63..56>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MCP_MEM_COMP_VDD

MCP_MEM_COMP_GND

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 29

16

16

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 28

15 29

15 29

15 29

15 29

15 29

4 3

2 1

D

C

B

Memory Constraints



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

89

OF

97

2 1

8

PCI-Express


PCIE_90D

CLK_PCIE_100D

*

*

7 6

ALLOW ROUTE

ON LAYER?

=90_OHM_DIFF

MINIMUM LINE WIDTH

=100_OHM_DIFF

=90_OHM_DIFF

=100_OHM_DIFF


=90_OHM_DIFF

=100_OHM_DIFF

13.1 MM

=100_OHM_DIFF


=90_OHM_DIFF

=100_OHM_DIFF


DIFFPAIR NECK GAP


=90_OHM_DIFF


=100_OHM_DIFF

D

SPACING_RULE_SET

PCIE

CLK_PCIE

LAYER

*

*


=3X_DIELECTRIC

20 MIL


WEIGHT


?

?


?


MCP_PEX_COMP * 8 MIL

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

Analog Video Signal Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

CRT_50S * =50_OHM_SE =50_OHM_SE

SPACING_RULE_SET

PCIE

LAYER

TOP,BOTTOM


=4X_DIELECTRIC


WEIGHT

?





=STANDARD


DIFFPAIR NECK GAP

=STANDARD


C

SPACING_RULE_SET

CRT

CRT_2CRT

CRT_2CLK

CRT_2SWITCHER

CRT_SYNC

MCP_DAC_COMP

LAYER

*

*

*

*

*

*


=4:1_SPACING

=STANDARD

50 MIL

250 MIL

16 MIL

=2:1_SPACING


WEIGHT

?



?

?



?


?

?


NET_SPACING_TYPE1

CRT

CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible).

R/G/B signals should be matched as close as possible and < 10 inches.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

NET_SPACING_TYPE2

CRT

AREA_TYPE

*


SPACING_RULE_SET


CRT_2CRT

Digital Video Signal Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

DP_100D * =100_OHM_DIFF

=100_OHM_DIFF

MINIMUM NECK WIDTH

=100_OHM_DIFF

LVDS_100D

MCP_DV_COMP

*

*

=100_OHM_DIFF

Y

=100_OHM_DIFF

20 MIL

=100_OHM_DIFF

20 MIL

MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF

=STANDARD


=100_OHM_DIFF

=100_OHM_DIFF

=STANDARD


DIFFPAIR NECK GAP


=100_OHM_DIFF


=100_OHM_DIFF

=STANDARD


B

SPACING_RULE_SET

DISPLAYPORT

LVDS

LAYER

*

*


=3x_DIELECTRIC

=3x_DIELECTRIC


WEIGHT

?



?

SPACING_RULE_SET

DISPLAYPORT

LVDS

LAYER

TOP,BOTTOM

TOP,BOTTOM


=4x_DIELECTRIC

=4x_DIELECTRIC

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.


SATA Interface Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

SATA_100D * =100_OHM_DIFF

=100_OHM_DIFF


WEIGHT

?



?




=100_OHM_DIFF


DIFFPAIR NECK GAP


=100_OHM_DIFF

SPACING_RULE_SET

SATA

SATA_TERMP

LAYER

*

*


=4x_DIELECTRIC

8 MIL


WEIGHT

?


?


SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SPACING_RULE_SET

SATA

LAYER

TOP,BOTTOM


=3x_DIELECTRIC


WEIGHT

?


5

A

8

7 6 5

4 3

MCP_PEX_CLK_COMP

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_SYNC

CRT_SYNC

MCP_DAC_RSET

MCP_DAC_VREF

TMDS_IG_TXC

TMDS_IG_TXC

TMDS_IG_TXD

TMDS_IG_TXD

DP_ML

DP_ML

DP_AUX_CH

DP_AUX_CH

MCP_HDMI_RSET

MCP_HDMI_VPROBE

LVDS_IG_A_CLK

LVDS_IG_A_CLK

LVDS_IG_A_DATA

LVDS_IG_A_DATA

LVDS_IG_A_DATA3

LVDS_IG_A_DATA3

LVDS_IG_B_CLK

LVDS_IG_B_CLK

LVDS_IG_B_DATA

LVDS_IG_B_DATA

LVDS_IG_B_DATA3

LVDS_IG_B_DATA3

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

SATA_HDD_R2D

ELECTRICAL_CONSTRAINT_SET

PEG_R2D

PEG_D2R

PHYSICAL

NET_TYPE

SPACING

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE_MINI_R2D

PCIE_MINI_D2R

PCIE_FW_R2D

PCIE_FW_D2R

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE_EXCARD_R2D

PCIE_EXCARD_D2R

MCP_PE0_REFCLK

MCP_PE1_REFCLK

MCP_PE2_REFCLK

MCP_PE3_REFCLK

DP_100D

DP_100D

DP_100D

DP_100D

MCP_DV_COMP

MCP_DV_COMP

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

MCP_DV_COMP

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

CLK_PCIE_100D CLK_PCIE








MCP_PEX_COMP

CRT_50S

CRT_50S

CRT_50S

CRT_50S

CRT_50S

DP_100D

DP_100D

DP_100D

DP_100D

CRT

CRT

CRT

CRT_SYNC

CRT_SYNC

MCP_DAC_COMP

MCP_DAC_COMP

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

SATA_HDD_D2R

SATA_ODD_R2D

SATA_ODD_D2R

MCP_SATA_TERMP

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA_TERMP

PEG_R2D_P<15..0>

PEG_R2D_N<15..0>

PEG_R2D_C_P<15..0>

PEG_R2D_C_N<15..0>

PEG_D2R_P<15..0>

PEG_D2R_N<15..0>

PEG_D2R_C_P<15..0>

PEG_D2R_C_N<15..0>

PCIE_MINI_R2D_P

PCIE_MINI_R2D_N

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

PCIE_FW_R2D_P

PCIE_FW_R2D_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_D2R_C_P

PCIE_FW_D2R_C_N

71

71

9 71

9 71

9 71

9 71

71

71

7 31 96

7 31 96

17 31

17 31

7 17 31

7 17 31

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_N





96

96

9 17

9 17

9 17

9 17

PEG_CLK100M_P

PEG_CLK100M_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

17 71

17 71

17 31

17 31

17 36

PCIE_CLK100M_FW_N



MCP_PEX_CLK_COMP

17 36

9 17

9 17

17

36

36

17 36

17 36

17 36

17 36

36

36

NC_CRT_IG_R_C_PR

NC_CRT_IG_G_Y_Y

NC_CRT_IG_B_COMP_PB

NC_CRT_IG_HSYNC

NC_CRT_IG_VSYNC

NC_MCP_TV_DAC_RSET

NC_MCP_TV_DAC_VREF

TMDS_IG_TXC_P

TMDS_IG_TXC_N

TMDS_IG_TXD_P<2..0>

TMDS_IG_TXD_N<2..0>

DP_IG_ML_P<3..0>

DP_IG_ML_N<3..0>

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

18 25

18 25

18 25

18 25

18 25

18 25

18 25

9 81

9 81

18 81

18 81

MCP_HDMI_RSET

MCP_HDMI_VPROBE

18 25

18 25

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_A_DATA_N<2..0>



NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_B_DATA_N<2..0>



18 84

18 84

18 84

18 84

9 18

9 18

9 18

9 18

18 84

18 84

9 18

9 18

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_P

SATA_HDD_R2D_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_P

SATA_ODD_R2D_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

MCP_SATA_TERMP

18 25

18 25

20

7 39

20 39

20 39

7 39

7 39

20 39

20 39

7 39

7 39

20 39

20 39

7 39

7 39

20 39

20 39

7 39

2

4 3

1

D

C

B

MCP Constraints 1



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

90

OF

97

2 1

8 7 6

PCI Bus Constraints

PHYSICAL_RULE_SET

PCI_55S

LAYER

*

ALLOW ROUTE

ON LAYER?

=55_OHM_SE

CLK_PCI_55S * =55_OHM_SE

MINIMUM LINE WIDTH

=55_OHM_SE

=55_OHM_SE


=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE


=STANDARD

=STANDARD


DIFFPAIR NECK GAP

=STANDARD


=STANDARD


SPACING_RULE_SET

PCI

CLK_PCI

LAYER

*

*


=STANDARD

8 MIL


WEIGHT

?



?

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

LPC Bus Constraints


ALLOW ROUTE

ON LAYER?

LPC_55S * =55_OHM_SE

CLK_LPC_55S * =55_OHM_SE

MINIMUM LINE WIDTH

=55_OHM_SE

=55_OHM_SE


=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE


=STANDARD

=STANDARD


DIFFPAIR NECK GAP

=STANDARD


=STANDARD


SPACING_RULE_SET

LPC

CLK_LPC

LAYER

*

*


6 MIL

8 MIL


WEIGHT

?


?



USB 2.0 Interface Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

MCP_USB_RBIAS * =STANDARD 8 MIL

USB_90D * =90_OHM_DIFF

=90_OHM_DIFF


8 MIL

=90_OHM_DIFF

=STANDARD

=90_OHM_DIFF


=STANDARD

=90_OHM_DIFF


DIFFPAIR NECK GAP

=STANDARD



=90_OHM_DIFF

SPACING_RULE_SET

USB

LAYER

*


=2x_DIELECTRIC


WEIGHT


?

SPACING_RULE_SET

USB

LAYER

TOP,BOTTOM


=4x_DIELECTRIC


WEIGHT


?

C


SMBus Interface Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

SMB_55S * =55_OHM_SE =55_OHM_SE




=STANDARD


DIFFPAIR NECK GAP

=STANDARD


SPACING_RULE_SET

SMB

LAYER

*


=2x_DIELECTRIC


WEIGHT

?



HD Audio Interface Constraints

PHYSICAL_RULE_SET

HDA_55S

LAYER

*

ALLOW ROUTE

ON LAYER?

=55_OHM_SE

MINIMUM LINE WIDTH

=55_OHM_SE




=STANDARD


DIFFPAIR NECK GAP

=STANDARD


SPACING_RULE_SET

HDA

MCP_HDA_COMP

LAYER

*

*


=2x_DIELECTRIC

8 MIL


WEIGHT

?


?


B


SIO Signal Constraints


ALLOW ROUTE

ON LAYER?

CLK_SLOW_55S * =55_OHM_SE

MINIMUM LINE WIDTH

=55_OHM_SE




=STANDARD


DIFFPAIR NECK GAP

=STANDARD


SPACING_RULE_SET

CLK_SLOW

LAYER

*


8 MIL


WEIGHT

?



SPI Interface Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

SPI_55S * =55_OHM_SE =55_OHM_SE




=STANDARD


DIFFPAIR NECK GAP

=STANDARD


SPACING_RULE_SET

SPI

LAYER

*


8 MIL


WEIGHT


?


A

5

8

7 6 5

4 3


MCP_DEBUG

PCI_AD

PCI_AD24

PCI_AD

PCI_AD

PCI_C_BE_L

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_REQ0_L

PCI_GNT0_L

PCI_REQ1_L

PCI_GNT1_L

PCI_INTW_L

PCI_INTX_L

PCI_INTY_L

PCI_INTZ_L

PHYSICAL

NET_TYPE

SPACING

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

MCP_PCI_CLK2

LPC_AD

LPC_FRAME_L

LPC_RESET_L

MCP_LPC_CLK0

CLK_PCI_55S

CLK_PCI_55S

LPC_55S

LPC_55S

LPC_55S

CLK_PCI

CLK_PCI

LPC

LPC

LPC

USB_EXTA

USB_MINI

USB_EXTD

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

USB_EXTB

USB_EXCARD

USB_EXTC

CLK_LPC_55S

CLK_LPC_55S

CLK_LPC_55S

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

CLK_LPC

CLK_LPC

CLK_LPC

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

MCP_USB_RBIAS

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

MCP_HDA_PULLDN_COMP

MCP_SUS_CLK

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS0

MCP_USB_RBIAS

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB

SMB

SMB

SMB

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA

HDA

HDA

HDA

HDA

HDA

HDA

HDA

HDA

HDA

MCP_HDA_COMP

CLK_SLOW_55S CLK_SLOW

CLK_SLOW_55S CLK_SLOW

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI

SPI

SPI

SPI

SPI

SPI

SPI

SPI

MCP_DEBUG<7..0>

PCI_AD<23..8>

PCI_AD<24>

PCI_AD<31..25>

PCI_PAR

PCI_C_BE_L<3..0>

PCI_IRDY_L

PCI_DEVSEL_L

PCI_PERR_L

PCI_SERR_L

PCI_STOP_L

PCI_TRDY_L

PCI_FRAME_L

PCI_REQ0_L

PCI_GNT0_L

PCI_REQ1_L

PCI_GNT1_L

PCI_INTW_L

PCI_INTX_L

PCI_INTY_L

PCI_INTZ_L

PCI_CLK33M_MCP_R

PCI_CLK33M_MCP

LPC_AD<3..0>

LPC_FRAME_L

LPC_RESET_L

LPC_CLK33M_SMC_R

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

USB_EXTA_P

USB_EXTA_N

USB_EXTA_MUXED_P

USB_EXTA_MUXED_N

NC_USB_MINIP

NC_USB_MININ

NC_USB_EXTDP

NC_USB_EXTDN

USB_CAMERA_P

USB_CAMERA_N

USB_BT_P

USB_BT_N

USB_TPAD_P

USB_TPAD_N

USB_IR_P

USB_IR_N

USB_EXTB_P

USB_EXTB_N

NC_USB_EXCARDP

NC_USB_EXCARDN

NC_USB_EXTCP

NC_USB_EXTCN

MCP_USB_RBIAS_GND

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

HDA_BIT_CLK

HDA_BIT_CLK_R

HDA_SYNC

HDA_SYNC_R

HDA_RST_R_L

HDA_RST_L

HDA_SDIN0

HDA_SDIN_CODEC

HDA_SDOUT

HDA_SDOUT_R

MCP_HDA_PULLDN_COMP

PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK

SPI_CLK_R

SPI_CLK

SPI_MOSI_R

SPI_MOSI

SPI_MISO

SPI_MISO_R

SPI_CS0_R_L

SPI_CS0_L

13 19

19

19

21 55

21

21

21 26

26 42

21 44

54

21 44

54

21 44

54

21 44

19

19

19 42 44 84

19 42 44 84

19 26 84

19 26

26 42

26 44

20 40

20 40

9 20

9 20

9 20

9 20

7 20 31

7 20 31

7 20 31

7 20 31

20 50

20 50

20 41

20 41

20 40

20 40

9 20

9 20

9 20

9 20

20

13 21 28 29 45

13 21 28 29 45

21 45 60 85

21 45 60 85

21 55

21

21 55

21

21

21 55

21 55

2

4 3

1

D

C

B

MCP Constraints 2



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

91

OF

97

2 1

8 7 6

MCP RGMII (Ethernet) Constraints

PHYSICAL_RULE_SET

MCP_MII_COMP

LAYER

*

ALLOW ROUTE

ON LAYER?

=STANDARD

MINIMUM LINE WIDTH

7.5 MIL

MINIMUM NECK WIDTH

7.5 MIL

ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

=55_OHM_SE


=STANDARD

=STANDARD


DIFFPAIR NECK GAP

=STANDARD


=STANDARD


SPACING_RULE_SET

MCP_BUF0_CLK

ENET_MII

LAYER

*

*


=3:1_SPACING

12 MIL


WEIGHT

?



?

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH MINIMUM NECK WIDTH

ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

MAXIMUM NECK LENGTH

=100_OHM_DIFF


=100_OHM_DIFF


DIFFPAIR NECK GAP


=100_OHM_DIFF

SPACING_RULE_SET

ENET_MDI

LAYER

*


25 MIL


WEIGHT

?



5 4 3


MCP_MII_COMP

MCP_MII_COMP

PHYSICAL

NET_TYPE

SPACING

MCP_MII_COMP

MCP_MII_COMP

MCP_CLK25M_BUF0 ENET_MII_55S

ENET_MII_55S

MCP_BUF0_CLK

MCP_BUF0_CLK

ENET_INTR_L

ENET_MDIO

ENET_MDC

ENET_PWRDWN_L

ENET_RXCLK

ENET_RXD

ENET_RXD_STRAP

ENET_RXD

ENET_TXCLK

ENET_TXD0

ENET_TXD

ENET_TXD

ENET_MDI

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII_55S ENET_MII

ENET_MDI_100D ENET_MDI

ENET_MDI_100D ENET_MDI

MCP_MII_COMP_VDD

MCP_MII_COMP_GND

18

18

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

18 34

33 34

ENET_INTR_L

ENET_MDIO

ENET_MDC

ENET_PWRDWN_L

18 33

18 33

ENET_CLK125M_RXCLK_R

ENET_CLK125M_RXCLK

ENET_RXD_R<3..0>

ENET_RXD<0>

ENET_RXD<3..1>

ENET_RX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<0>

ENET_TXD<3..1>

ENET_TX_CTRL

ENET_RESET_L

ENET_MDI_P<3..0>

ENET_MDI_N<3..0>

33

18 33

33

18 33

18 33

18 33

18 33

18 33

18 33

18 33

18 33

33 35

33 35

2

C

1

D

C

B B

A

8

7 6 5 4 3

Ethernet Constraints



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

92

OF

97

2 1

D

8 7 6

FireWire Interface Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

FW_110D * =110_OHM_DIFF

=110_OHM_DIFF




=110_OHM_DIFF


DIFFPAIR NECK GAP


=110_OHM_DIFF

SPACING_RULE_SET

FW_TP

LAYER

*


=3:1_SPACING


WEIGHT

?


SD CARD INTERFACE CONSTRAINTS


ALLOW ROUTE

ON LAYER?

SD_55S *

=55_OHM_SE

MINIMUM LINE WIDTH

=55_OHM_SE

MINIMUM NECK WIDTH

=55_OHM_SE

MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP

=55_OHM_SE =STANDARD


DIFFPAIR NECK GAP


=STANDARD

SPACING_RULE_SET

SD_INTERFACE

LAYER

*


=3X_DIELECTRIC


WEIGHT

?


5

C

4

FireWire Net Properties

NET_TYPE


FW_P0_TPA

FW_P0_TPA

FW_P0_TPB

FW_P0_TPB

FW_P1_TPA

FW_P1_TPA

FW_P1_TPB

FW_P1_TPB

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

Port 2 Not Used

3

NC_FW0_TPAP

NC_FW0_TPAN

NC_FW0_TPBP

NC_FW0_TPBN

FW_PORT1_TPA_P

FW_PORT1_TPA_N

FW_PORT1_TPB_P

FW_PORT1_TPB_N

SD CARD NET PROPERTIES

I32

I31

I30

I29

I28

I27

I26

I25


SD_DATA

SD_DATA

SD_DATA

SD_DATA

SD_DATA

SD_DATA

SD_DATA

SD_DATA

I23

I24

SD_CLK

SD_CMD

PHYSICAL

SD_55S

SD_55S

SD_55S

SD_55S

SD_55S

SD_55S

SD_55S

SD_55S

NET_TYPE

SPACING

SD_INTERFACE

SD_INTERFACE

SD_INTERFACE

SD_INTERFACE

SD_INTERFACE

SD_INTERFACE

SD_INTERFACE

SD_INTERFACE

SD_55S

SD_55S

SD_INTERFACE

SD_INTERFACE

SD_D<0>

SD_D<1>

SD_D<2>

SD_D<3>

SD_D<4>

SD_D<5>

SD_D<6>

SD_D<7>

SD_CLK

SD_CMD

36 38

36 38

36 38

36 38

36 38

36 38

36 38

36 38

7 32

7 32

7 32

7 32

7 32

7 32

7 32

7 32

7 32

7 32

2 1

D

C

B B

A

8

7 6 5 4 3

FireWire Constraints



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

93

OF

97

2 1

D

8 7 6

PHYSICAL_RULE_SET

1TO1_DIFFPAIR

LAYER

*

ALLOW ROUTE

ON LAYER?

=STANDARD

MINIMUM LINE WIDTH

=STANDARD


=STANDARD =STANDARD


0.1 MM


DIFFPAIR NECK GAP


0.1 MM

5 4

SMC SMBus Net Properties

NET_TYPE


SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SMB

3

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

SMBus Charger Net Properties

NET_TYPE


PHYSICAL SPACING

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

CHGR_CSI_P

CHGR_CSI_N

CHGR_CSO_P

CHGR_CSO_N

62

62

62

62

7 31 42 45 51

7 31 42 45 51

42 45 48

42 45 48

42 45 48 53 78

42 45 48 53 78

7 42 45 61 62

7 42 45 61 62

27 39 42 45

27 39 42 45

2

C

1

D

C

B B

A

8

7 6 5 4 3

SMC Constraints



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

94

OF

97

2 1

D

C

B

A

8

GDDR3 Frame Buffer Signal Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

GDDR3_40R55SE * =55_OHM_SE =40_OHM_SE

GDDR3_40SE * =40_OHM_SE

GDDR3_80D *

=40_OHM_SE


7 6


0.095 MM

0.095 MM

0.095 MM

12.7 MM

=40_OHM_SE

=80_OHM_DIFF


=STANDARD

=STANDARD

=80_OHM_DIFF


DIFFPAIR NECK GAP


=STANDARD


=STANDARD

=80_OHM_DIFF


SPACING_RULE_SET

GDDR3_CLK

GDDR3_CMD

GDDR3_DATA

GDDR3_DQS

LAYER

*

*

*

*


=2.5:1_SPACING

=2.5:1_SPACING

=2.5:1_SPACING

=2.5:1_SPACING


WEIGHT


?


?

?



?

From T18 MXM:

Digital Video Signal Constraints


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

DP_100D * =100_OHM_DIFF

=100_OHM_DIFF

MINIMUM NECK WIDTH

=100_OHM_DIFF

LVDS_100D *

=100_OHM_DIFF


MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF


=100_OHM_DIFF

=100_OHM_DIFF


DIFFPAIR NECK GAP


=100_OHM_DIFF


=100_OHM_DIFF

SPACING_RULE_SET

DISPLAYPORT

LAYER

*


=3x_DIELECTRIC


WEIGHT

?


?


SPACING_RULE_SET

DISPLAYPORT

LAYER

TOP,BOTTOM


=4x_DIELECTRIC

LVDS * =3x_DIELECTRIC LVDS TOP,BOTTOM =4x_DIELECTRIC

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.



WEIGHT

?


?


MUXGFX Net Properties


I148

I149

LVDS_A_CLK

LVDS_A_CLK

PHYSICAL

LVDS_100D

LVDS_100D

NET_TYPE

SPACING

LVDS

LVDS

I199

I198

LVDS_A_DATA

LVDS_A_DATA

LVDS_100D

LVDS_100D

LVDS

LVDS

I152

I153

LVDS_B_CLK

LVDS_B_CLK

I201

I200

I191

I192

I193

I194

I195

I196

I197

I183

I182

I184

I185

I190

LVDS_B_DATA

LVDS_B_DATA

I161

I160

I155

I157

I202

I203

DP_ML

DP_ML

DP_ML

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_A_DATA_P<2..0>

LVDS_A_DATA_N<2..0>

81 84

81 84

81 84

81 84

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

LVDS

LVDS

LVDS_B_CLK_P

LVDS_B_CLK_N

81 84

81 84

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS_B_DATA_P<2..0>

LVDS_B_DATA_N<2..0>

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DP_ML_C_P<3..0>

DP_ML_C_N<3..0>

DP_ML_CONN_P<3..0>

DP_ML_CONN_N<3..0>

81 84

81 84

LVDS_CONN_A_CLK_F_P

LVDS_CONN_A_CLK_F_N

LVDS_CONN_B_CLK_F_P

LVDS_CONN_B_CLK_F_N

LVDS_CONN_A_CLK_P

7 80

7 80

7 80

7 80

80 81

LVDS_CONN_A_CLK_N

80 81

LVDS_CONN_A_DATA_P<2..0>

LVDS_CONN_A_DATA_N<2..0>

7 80 81

7 80 81

LVDS_CONN_B_CLK_P

80 81

LVDS_CONN_B_CLK_N

80 81

LVDS_CONN_B_DATA_P<2..0>

7 80 81

LVDS_CONN_B_DATA_N<2..0>

7 80 81

7 82

82

81 82

81 82

82

82

I159

I158

DP_AUX_CH

DP_AUX_CH

DP_100D

DP_100D

DISPLAYPORT

DISPLAYPORT

DP_AUX_CH_C_P

DP_AUX_CH_C_N

81 82

81 82

5 4

GDDR3 FB A/B Net Properties

NET_TYPE


FB_A_CLK_P

I205

FB_B_CLK_P

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD_PD

FB_AB_CMD_PD

FB_AB_CS0

FB_AB_CMD_PD

PHYSICAL SPACING

GDDR3_80D

GDDR3_80D

GDDR3_80D

GDDR3_80D

GDDR3_CLK

GDDR3_CLK

GDDR3_CLK

GDDR3_CLK

GDDR3_40R55SE GDDR3_CMD




GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD


GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_CMD

GDDR3_CMD

FB_A_CMD

FB_B_CMD

FB_A_WDQS0

FB_A_WDQS1

FB_A_WDQS2

FB_A_WDQS3

FB_A_RDQS0

FB_A_RDQS1

FB_A_RDQS2

FB_A_RDQS3

FB_A_DQ_BYTE0

FB_A_DQ_BYTE1

FB_A_DQ_BYTE2

FB_A_DQ_BYTE3

FB_A_DQM0

FB_A_DQM1

FB_A_DQM2

FB_A_DQM3

FB_B_WDQS0

FB_B_WDQS1

FB_B_WDQS2

FB_B_WDQS3

FB_B_RDQS0

FB_B_RDQS1

FB_B_RDQS2

FB_B_RDQS3

FB_B_DQ_BYTE0

FB_B_DQ_BYTE1

FB_B_DQ_BYTE2

FB_B_DQ_BYTE3

FB_B_DQM0

FB_B_DQM1

FB_B_DQM2

FB_B_DQM3

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_CMD

GDDR3_CMD

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

FB_A_CLK_P<0>

FB_A_CLK_N<0>

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_MA<1..0>

FB_A_MA<12..6>

FB_A_BA<2..0>

FB_A_RAS_L

FB_A_CAS_L

FB_A_WE_L

FB_A_UCKE

FB_A_LCKE

FB_A_LCS0_L

FB_A_DRAM_RST

FB_A_LMA<5..2>

FB_A_UMA<5..2>

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_RDQS<0>

FB_A_RDQS<1>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_DQ<7..0>

FB_A_DQ<15..8>

FB_A_DQ<23..16>

FB_A_DQ<31..24>

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<7>

FB_A_RDQS<4>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<7>

FB_A_DQ<39..32>

FB_A_DQ<47..40>

FB_A_DQ<55..48>

FB_A_DQ<63..56>

FB_A_DQM_L<4>

FB_A_DQM_L<5>

FB_A_DQM_L<6>

FB_A_DQM_L<7>

G96 Net Properties


(CK505_DOT96)

CK505_CLK27MSS

LVDS_EG_A_CLK

LVDS_EG_A_CLK

LVDS_EG_A_DATA

LVDS_EG_A_DATA

NET_TYPE

PHYSICAL

CLK_SLOW_55S

CLK_SLOW_55S

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

SPACING

CLK_SLOW

CLK_SLOW

LVDS

LVDS

LVDS

LVDS

GPU_CLK27M

GPU_CLK27M_SS

LVDS_EG_A_CLK_P

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<2..0>

LVDS_EG_A_DATA_N<2..0>

76 77

76 77

78 84

78 84

78 84

78 84

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

LVDS_EG_B_DATA

LVDS_EG_B_DATA

LVDS_100D

LVDS_100D

LVDS

LVDS

LVDS_EG_B_DATA_P<2..0>

LVDS_EG_B_DATA_N<2..0>

78 84

78 84

I142

I144

I145

I143

I139

I138

DP_ML

DP_ML

DP_AUX_CH

DP_AUX_CH

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DP_EG_ML_P<3..0>

DP_EG_ML_N<3..0>

DP_EG_AUX_CH_P

DP_EG_AUX_CH_N

DP_EG_AUX_CH_C_P

DP_EG_AUX_CH_C_N

78 81

78 81

78 81

78 81

81

81

8

7 6 5 4

3 2

FB_C_CMD

FB_D_CMD

FB_C_WDQS0

FB_C_WDQS1

FB_C_WDQS2

FB_C_WDQS3

FB_C_RDQS0

FB_C_RDQS1

FB_C_RDQS2

FB_C_RDQS3

FB_C_DQ_BYTE0

FB_C_DQ_BYTE1

FB_C_DQ_BYTE2

FB_C_DQ_BYTE3

FB_C_DQM0

FB_C_DQM1

FB_C_DQM2

FB_C_DQM3

FB_D_WDQS0

FB_D_WDQS1

FB_D_WDQS2

FB_D_WDQS3

FB_D_RDQS0

FB_D_RDQS1

FB_D_RDQS2

FB_D_RDQS3

FB_D_DQ_BYTE0

FB_D_DQ_BYTE1

FB_D_DQ_BYTE2

FB_D_DQ_BYTE3

FB_D_DQM0

FB_D_DQM1

FB_D_DQM2

FB_D_DQM3

GDDR3 FB C/D Net Properties

NET_TYPE


FB_C_CLK_P

I204

FB_D_CLK_P

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD_PD

FB_CD_CMD_PD

FB_CD_CS0

FB_CD_CMD_PD

PHYSICAL SPACING

GDDR3_80D

GDDR3_80D

GDDR3_80D

GDDR3_80D

GDDR3_CLK

GDDR3_CLK

GDDR3_CLK

GDDR3_CLK









GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_CMD

GDDR3_CMD

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_CMD

GDDR3_CMD

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

FB_B_CLK_P<0>

FB_B_CLK_N<0>

FB_B_CLK_P<1>

FB_B_CLK_N<1>

FB_B_MA<1..0>

FB_B_MA<12..6>

FB_B_BA<2..0>

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_UCKE

FB_B_LCKE

FB_B_LCS0_L

FB_B_DRAM_RST

FB_B_LMA<5..2>

FB_B_UMA<5..2>

FB_B_WDQS<0>

FB_B_WDQS<1>

FB_B_WDQS<2>

FB_B_WDQS<3>

FB_B_RDQS<0>

FB_B_RDQS<1>

FB_B_RDQS<2>

FB_B_RDQS<3>

FB_B_DQ<7..0>

FB_B_DQ<15..8>

FB_B_DQ<23..16>

FB_B_DQ<31..24>

FB_B_DQM_L<0>

FB_B_DQM_L<1>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_RDQS<4>

FB_B_RDQS<5>

FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_DQ<39..32>

FB_B_DQ<47..40>

FB_B_DQ<55..48>

FB_B_DQ<63..56>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

1

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

3

D

C

B

GPU (G96) CONSTRAINTS



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

95

OF

97

2 1

8 7 6 5 4 3 2 1

D

PHYSICAL_RULE_SET

SENSE_1TO1_55S

THERM_1TO1_55S

DIFFPAIR

SPACING_RULE_SET

SENSE

THERM

AUDIO

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND

PP1V8_MEM

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

LAYER

*

*

*

LAYER

*

*

*

LAYER

*

LAYER

*

*

LAYER

*

*

ALLOW ROUTE

ON LAYER?

=1:1_DIFFPAIR

MINIMUM LINE WIDTH

=55_OHM_SE

=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR


=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=1:1_DIFFPAIR


=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR


DIFFPAIR NECK GAP

=1:1_DIFFPAIR


=1:1_DIFFPAIR


=1:1_DIFFPAIR



=2:1_SPACING

=2:1_SPACING

=2:1_SPACING


25 MILS


=STANDARD

=STANDARD


0.20 MM

0.20 MM


WEIGHT


?


?

?



WEIGHT


?


WEIGHT


?

?



WEIGHT


1000


1000

I146

I145

I144

I142

I143

I140

I141

I139

K19 Specific Net Properties


SENSE_DIFFPAIR

NET_TYPE

PHYSICAL

ENET_MDI_100D

ENET_MDI_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SENSE_1TO1_55S

SPACING

ENETCONN

ENETCONN

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SENSE

SENSE_1TO1_55S SENSE

I124

I125

I127

I126

I128

I130

I129

CPUTHMSNS_D2_DP

CPU_THERMD_DP

GPUTHMSNS_D_DP

GPU_THERMD_DP

I138

I137

I135

I136

I156

I157

MCPTHMSNS_D_DP

MCP_THERMD_DP

SENSE_DIFFPAIR

THERM_1TO1_55S THERM

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM

THERM

THERM







THERM_1TO1_55S

THERM_1TO1_55S

SENSE_1TO1_55S

THERM

THERM

SENSE


ENETCONN_P<3..0>

ENETCONN_N<3..0>

SATA_ODD_R2D_UF_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_UF_P

SATA_HDD_R2D_UF_N

GFXIMVP6_VSEN_P

GFXIMVP6_VSEN_N

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

CPU_THERMD_P

CPU_THERMD_N

GPUTHMSNS_D_P

GPUTHMSNS_D_N

GPU_TDIODE_P

GPU_TDIODE_N

MCPTHMSNS_D_P

MCPTHMSNS_D_N

MCP_THMDIODE_P

MCP_THMDIODE_N

CPUVTTISNS_R_P

CPUVTTISNS_R_N

35

35

39

39

7 39

7 39

39

39

39

39

79

79

48

48

10 48

10 48

48

48

48 76 77

48 76 77

48

48

21 48

21 48

47

47

I168

I166

I167

I165

I182

I181

I179

I180

I177

I164

I162

I163

I161

I160

I159

I178

I176

I175

I174

I172

I173

I171

I169

I170

I183

I184

K19 Specific Net Properties


(PCIE_EXCARD)

(PCIE_EXCARD)

(PCIE_MINI)

(PCIE_MINI)

(USB_EXTA)

(USB_EXTA)

(USB_EXTA)

(USB_EXTA)

(USB_EXTD)

(USB_EXTD)

(USB_CAMERA)

(USB_CAMERA)

USB_CARDREADER

NET_TYPE

PHYSICAL SPACING

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

CLK_PCIE_100D

PCIE

PCIE

PCIE

PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE_100D

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB

USB

USB

USB

USB

USB

USB

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

DP_100D

DP_100D

USB

USB

USB

USB

USB

USB

USB

DISPLAYPORT

DISPLAYPORT

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_N

PCIE_MINI_R2D_P

PCIE_MINI_R2D_N



CHGR_CSI_R_P

CHGR_CSI_R_N

CHGR_CSO_R_P

CHGR_CSO_R_N

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

62

62

90

90

7 31 90

7 31 90

7 31

7 31

46 62

46 62

40

40

USB2_LT1_P

USB2_LT1_N

USB_TPAD_R_P

USB_TPAD_R_N

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

CONN_USB2_BT_P

CONN_USB2_BT_N

USB_LT2_P

USB_LT2_N

40

40

50

50

7 31

7 31

7 31

7 31

40

40

USB_CARDREADER_P

USB_CARDREADER_N

DP_IG_AUX_CH_C_P

DP_IG_AUX_CH_C_N

9 20 32

9 20 32

81

81

C

B

A


MEM_CLK GND

MEM_CMD

MEM_CTRL

MEM_DATA

MEM_DQS

GND

GND

GND

GND


CLK_PCIE GND


LVDS GND

AREA_TYPE

*

*

*

*

*

AREA_TYPE

*

AREA_TYPE

*


SPACING_RULE_SET

GND_P2MM


GND_P2MM


GND_P2MM


GND_P2MM


GND_P2MM



SPACING_RULE_SET

GND_P2MM


GND_P2MM


GND_P2MM


GND_P2MM


PWR_P2MM


PWR_P2MM


PWR_P2MM


NET_SPACING_TYPE1

CLK_FSB

NET_SPACING_TYPE1

ENET_MDI

NET_SPACING_TYPE2

GND

NET_SPACING_TYPE2

GND

AREA_TYPE

*

AREA_TYPE

*

I153

I152

I151

I150

I158

I147

I186

I185

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

SENSE



SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

SENSE

SB_POWER

SB_POWER

GPUISENS_P

GPUISENS_N

CPUVTT_ISNS_P

CPUVTT_ISNS_N

P1V8GPU_P

P1V8GPU_N

ISNS_CPU_P

ISNS_CPU_N

PP3V3_S5

PP3V3_S0

47

47

47 67

47 67

47

47

46

46

82 87

37 38 44 54 64 68 69 70

7 8 18 20 22 24 26 30 34

48 49 51 55 59 60 63 68

6 7 8 13 18 19 21 22 24

25 28 29 37 39 43 45 47

69 70 77 80 81 82 84 85

I199

I202

I206

I207

I204

I205

I208

I198

I197

I201

I200

I203

I223

I224

I226

I225

I221

I222

I227

I228

SPK_OUT

SPK_OUT

SPK_OUT

PCIE

SATA

USB

CLK_PCIE

SATA

USB

GND

GND

GND

SB_POWER

SB_POWER

SB_POWER

*

*

*

*

*

*


SPACING_RULE_SET

GND_P2MM


Memory Constraint Relaxations

CPU_COMP

CPU_GTLREF

CPU_VCCSENSE

FSB_DSTB

GND

GND

GND

FSB_DSTB

*

*

*

*


SPACING_RULE_SET


GND_P2MM

GND_P2MM


GND_P2MM


GND_P2MM


GND_P2MM



SPACING_RULE_SET

GND_P2MM


I134

I133

I214

I209

I215

I216

I218

I217

I210

I211

I212

I213

I219

I220

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

SENSE




SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

SENSE

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

SENSE

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

P1V8GPUISNS_R_P

P1V8GPUISNS_R_N

ISNS_AIRPORT_P

ISNS_AIRPORT_N

ISNS_AIRPORT_R_P

ISNS_AIRPORT_R_N

ISNS_1V5_S3_R_P

ISNS_1V5_S3_R_N

ISNS_1V5_S3_P

ISNS_1V5_S3_N

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

ISNS_LCDBKLT_R_P

ISNS_LCDBKLT_R_N

47

47

31 53

31 53

53

53

53

53

53 65

53 65

53 85

53 85

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.


ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

MEM_70D BOTTOM

MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP


DIFFPAIR NECK GAP


0.127 MM 6.35 MM

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE

LVDS_100D

DP_100D

SATA_100D

FSB_DATA

FSB_DSTB

FSB_ADDR

FSB_ADSTB

FSB_1X

CPU_AGTL

CPU_8MIL

AREA_TYPE

BGA

BGA

BGA

*

*

*

*

*

*

*

TABLE_PHYSICAL_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

100_DIFF_BGA


100_DIFF_BGA


100_DIFF_BGA

PGA CONSTRAINT RELAXATIONS

PHYSICAL_RULE_SET

PGA_50SE

NET_PHYSICAL_TYPE

FSB_50S

FSB_DSTB_50S

CPU_50S

LAYER

*

ALLOW ROUTE

ON LAYER?

AREA_TYPE

PGA

PGA

PGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

PGA_50SE


PGA_50SE


PGA_50SE



Y

PGA

PGA

PGA

PGA

PGA

PGA

PGA

MINIMUM LINE WIDTH

AREA_TYPE

=50_OHM_SE


SPACING_RULE_SET


PGA_CPU


PGA_CPU


PGA_CPU


PGA_CPU

PGA_CPU



PGA_CPU

PGA_CPU



0.073 MM =50_OHM_SE


=1:1_DIFFPAIR


DIFFPAIR NECK GAP


0.073 MM

PHYSICAL_RULE_SET

MEM_40S

OVERRIDE

MEM_40S_VDD

OVERRIDE

MEM_70D

OVERRIDE

MEM_70D_VDD

OVERRIDE

PCIE_90D

OVERRIDE

USB_90D

OVERRIDE

MCP_DV_COMP

OVERRIDE

MCP_MEM_COMP

OVERRIDE

MCP_MII_COMP

OVERRIDE

MCP_USB_RBIAS

OVERRIDE

MCP_DV_COMP

OVERRIDE

CPU_27P4S

OVERRIDE

PHYSICAL_RULE_SET

LAYER

*

OVERRIDE

*

OVERRIDE

*

OVERRIDE

*

OVERRIDE

*

OVERRIDE

*

OVERRIDE

TOP

OVERRIDE

TOP

OVERRIDE

TOP

OVERRIDE

TOP

OVERRIDE

*

OVERRIDE

BOTTOM

OVERRIDE

LAYER

ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

ALLOW ROUTE

ON LAYER?

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.09 MM

OVERRIDE

0.09 MM

OVERRIDE

0.09 MM

OVERRIDE

0.09 MM

OVERRIDE

0.09 MM

OVERRIDE

0.09 MM

OVERRIDE

0.1 MM

OVERRIDE

0.1 MM

OVERRIDE

0.1 MM

OVERRIDE

0.1 MM

OVERRIDE

0.25 MM

OVERRIDE

0.23 MM

OVERRIDE



DIFFPAIR NECK GAP


5.8 MM

OVERRIDE

5.8 MM

OVERRIDE

5.8 MM

OVERRIDE

100 MIL

OVERRIDE

100 MIL

OVERRIDE

500 MIL

OVERRIDE

500 MIL

OVERRIDE

500 MIL

OVERRIDE

500 MIL

OVERRIDE

500 MIL

OVERRIDE

250 MIL

OVERRIDE

100 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE













MEM_40S

OVERRIDE

MEM_40S_VDD

OVERRIDE

ISL4,ISL9

OVERRIDE

ISL3,ISL10

OVERRIDE

OVERRIDE

N

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

MEM_70D

OVERRIDE

MEM_70D_VDD

OVERRIDE

ISL4,ISL9

OVERRIDE

ISL3,ISL10

OVERRIDE

OVERRIDE

N

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.

Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).


DIFFPAIR NECK GAP


OVERRIDE


OVERRIDE


OVERRIDE


OVERRIDE

8

7 6 5 4 3

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55S

AUDIO

SENSE

SENSE




SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE

SENSE

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

GND

Project Specific Constraints

D

C

B



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

96

OF

97

2

SPKRCONN_L_OUT_P

SPKRCONN_L_OUT_N

SPKRCONN_S_OUT_P

SPKRCONN_S_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

SPKRAMP_L_OUT_P

SPKRAMP_L_OUT_N

SPKRAMP_R_OUT_P

SPKRAMP_R_OUT_N

SPKRAMP_S_OUT_P

SPKRAMP_S_OUT_N

ISNS_ODD_P

ISNS_ODD_N

ISNS_ODD_R_P

ISNS_ODD_R_N

ISNS_HDD_P

ISNS_HDD_N

ISNS_HDD_R_P

ISNS_HDD_R_N

53

53

7 58 59

7 58 59

7 58 59

7 58 59

7 58 59

7 58 59

58

58

58

58

58

58

39 53

39 53

53

53

39 53

39 53

GND

1

8 7 6

D

K19 Board-Specific Spacing & Physical Constraints

PHYSICAL_RULE_SET

DEFAULT

STANDARD

PHYSICAL_RULE_SET

55_OHM_SE

55_OHM_SE

LAYER

*

*

LAYER

TOP,BOTTOM

*

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

BOARD AREAS

NO_TYPE,BGA,PGA

BOARD UNITS

(MIL or MM)

MM

TABLE_BOARD_INFO

ALLEGRO

VERSION

15.5.1

ALLOW ROUTE

ON LAYER?

Y

MINIMUM LINE WIDTH

=50_OHM_SE

Y =DEFAULT


=50_OHM_SE

=DEFAULT

33.6 MM

10 MM


0 MM

=DEFAULT


DIFFPAIR NECK GAP


0 MM


=DEFAULT

ALLOW ROUTE

ON LAYER?

Y

MINIMUM LINE WIDTH

0.090 MM

Y 0.076 MM



DIFFPAIR NECK GAP


0.090 MM

0.076 MM =STANDARD =STANDARD =STANDARD


SPACING_RULE_SET

DEFAULT

STANDARD

BGA_P1MM

BGA_P2MM

BGA_P3MM

PGA_CPU

5

LAYER

*

*

*

*

*

*

PHYSICAL_RULE_SET

50_OHM_SE

50_OHM_SE

LAYER

TOP,BOTTOM

*

ALLOW ROUTE

ON LAYER?

Y

MINIMUM LINE WIDTH

0.110 MM

Y 0.090 MM



DIFFPAIR NECK GAP


0.095 MM



SPACING_RULE_SET

1.5:1_SPACING

1.8:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

LAYER

*

*

*

*

*

*

4 3


0.1 MM

=DEFAULT

=DEFAULT

=DEFAULT

=DEFAULT

0.073 MM


0.15 MM

0.18 MM

0.2 MM

0.25 MM

0.3 MM

0.4 MM


WEIGHT


?


?


?


?


?

?


NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE

* * BGA

MEM_CLK

CLK_FSB

CLK_PCIE

CLK_SLOW

FSB_DSTB

*

*

*

*

FSB_DSTB

BGA

BGA

BGA

BGA

BGA


SPACING_RULE_SET

BGA_P1MM


BGA_P2MM


BGA_P2MM


BGA_P2MM


BGA_P2MM


BGA_P3MM



WEIGHT


?

?



?


?

?



?

NOTE:From T18 MLB, changed to reflect M99 stackup.

SPACING_RULE_SET

2X_DIELECTRIC

3X_DIELECTRIC

4X_DIELECTRIC

5X_DIELECTRIC

LAYER

*

*

*

*


0.140 MM

0.210 MM

0.280 MM

0.350 MM


WEIGHT


?


?


?


?

PHYSICAL_RULE_SET

40_OHM_SE

40_OHM_SE

C

PHYSICAL_RULE_SET

27P4_OHM_SE

27P4_OHM_SE

LAYER

TOP,BOTTOM

*

LAYER

TOP,BOTTOM

*

PHYSICAL_RULE_SET

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

PHYSICAL_RULE_SET

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE

ON LAYER?

Y

MINIMUM LINE WIDTH

0.165 MM

Y 0.135 MM

ALLOW ROUTE

ON LAYER?

Y

Y

MINIMUM LINE WIDTH

0.310 MM

0.250 MM



DIFFPAIR NECK GAP


0.095 MM





DIFFPAIR NECK GAP


0.095 MM



ALLOW ROUTE

ON LAYER?

N

MINIMUM LINE WIDTH

=STANDARD

Y 0.160 MM

Y

Y

Y

0.160 MM

0.170 MM

0.170 MM


=STANDARD

0.160 MM

0.160 MM

0.170 MM

0.095 MM

=STANDARD


=STANDARD

0.175 MM

0.175 MM

0.150 MM

0.150 MM


DIFFPAIR NECK GAP


=STANDARD


0.175 MM


0.175 MM


0.150 MM


0.150 MM

ALLOW ROUTE

ON LAYER?

N

MINIMUM LINE WIDTH

=STANDARD

Y

Y

Y

Y

0.125 MM

0.125 MM

0.140 MM

0.140 MM


=STANDARD

0.125 MM

0.125 MM

0.140 MM

0.095 MM

=STANDARD


=STANDARD

0.180 MM

0.180 MM

0.190 MM

0.190 MM


DIFFPAIR NECK GAP


=STANDARD


0.180 MM


0.180 MM


0.190 MM


0.190 MM

PHYSICAL_RULE_SET

1:1_DIFFPAIR

B

LAYER

*

ALLOW ROUTE

ON LAYER?

Y

MINIMUM LINE WIDTH

=STANDARD

MINIMUM NECK WIDTH

=STANDARD


=STANDARD 0.1 MM


DIFFPAIR NECK GAP


0.1 MM

A

PHYSICAL_RULE_SET

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

PHYSICAL_RULE_SET

100_OHM_DIFF

100_OHM_DIFF

100_OHM_DIFF

100_OHM_DIFF

100_OHM_DIFF

PHYSICAL_RULE_SET

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE

ON LAYER?

N

MINIMUM LINE WIDTH

=STANDARD

Y

Y

Y

Y

0.102 MM

0.102 MM

0.115 MM

0.115 MM


=STANDARD

0.102 MM

0.102 MM

0.115 MM

0.095 MM

=STANDARD


=STANDARD

0.220 MM

0.220 MM

0.230 MM

0.230 MM


DIFFPAIR NECK GAP


=STANDARD


0.220 MM


0.220 MM


0.230 MM


0.230 MM

ALLOW ROUTE

ON LAYER?

N

MINIMUM LINE WIDTH

=STANDARD

Y

Y

Y

Y

0.080 MM

0.080 MM

0.089 MM

0.089 MM


=STANDARD

0.080 MM

0.080 MM

0.089 MM

0.089 MM

=STANDARD


=STANDARD

0.200 MM

0.200 MM

0.220 MM

0.220 MM


DIFFPAIR NECK GAP


=STANDARD


0.200 MM


0.200 MM


0.220 MM


0.220 MM

PHYSICAL_RULE_SET

100_DIFF_BGA

100_DIFF_BGA

100_DIFF_BGA

LAYER

*

ISL3,ISL4

ISL9,ISL10

ALLOW ROUTE

ON LAYER?

=100_OHM_DIFF

Y

Y

MINIMUM LINE WIDTH

=100_OHM_DIFF

0.075 MM

0.075 MM

MINIMUM NECK WIDTH

=100_OHM_DIFF

0.075 MM

0.075 MM

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.



0.125 MM

0.125 MM


DIFFPAIR NECK GAP

=100_OHM_DIFF



0.125 MM


0.125 MM

ALLOW ROUTE

ON LAYER?

N

MINIMUM LINE WIDTH

=STANDARD

Y

Y

Y

Y

0.077 MM

0.077 MM

0.077 MM

0.077 MM


=STANDARD

0.077 MM

0.077 MM

0.077 MM

0.077 MM

=STANDARD


=STANDARD

0.330 MM

0.330 MM

0.330 MM

0.330 MM


DIFFPAIR NECK GAP


=STANDARD


0.330 MM


0.330 MM


0.330 MM


0.330 MM

8

7 6 5 4 3

2 1

D

C

B

PCB Rule Definitions



A







SIZE

D

DRAWING NUMBER

051-7892

REV.

A.0.0

APPLE INC.

SCALE

NONE

SHT

97

OF

97

2 1

Apple Macbook Pro A1386 (MBP 15MLB)

Page

Contents

Sync

Page

Contents

Sync

SCHEM,CORNHOLE,K19

PVT 04/24/2009

Page

Contents

Sync

ALIASES RESOLVED

Functional Test Points

HDA Output Caps

DDR3 RESET Support

AIRPORT

ALS

CAMERA

BLUETOOTH

Page Notes

ODD Power Control

SATA ODD Port

SATA HDD Port

IR SUPPORT

Alternate SPI ROM Support

LPC+SPI Connector

GPU 27MHz Crystal

Isolation FETs for DP MUX inputs

LVDS Transmitter Termination

DisplayPort Mux

LVDS DDC MUX

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