NXP LPC11U00 Scalable Entry Level 32-bit Microcontroller (MCU) based on Arm® Cortex®-M0 and Cortex®-M0 Cores Data Sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB
SRAM; USB device; USART
Rev. 2.2 — 11 March 2014 Product data sheet
The LPC11U1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures.
The LPC11U1x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full Speed USB 2.0 device controller, the
LPC11U1x brings unparalleled design flexibility and seamless integration to today’s demanding connectivity solutions.
The peripheral complement of the LPC11U1x includes up to 32 kB of flash memory, 6 kB of SRAM data memory, one Fast-mode Plus I 2 C-bus interface, one RS-485/EIA-485
USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 40 general purpose I/O pins.
For additional documentation related to the LPC11U1x parts, see Section 15
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Total of 6 kB SRAM data memory (4 kB main SRAM and 2 kB USB SRAM).
16 kB boot ROM includes
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
ROM-based 32-bit integer division routines.
Debug options:
Standard JTAG test interface for BSDL.
Serial Wire Debug.
Digital peripherals:
NXP Semiconductors
LPC11U1X
Product data sheet
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Up to 40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, input inverter, and open-drain mode. Eight pins support a programmable glitch filter.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin (P0_7).
High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
Four general purpose counter/timers with a total of up to 5 capture inputs and 13 match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USB 2.0 full-speed device controller.
USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I 2 C-bus interface supporting the full I 2 C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.
A second, dedicated PLL is provided for USB.
Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.
Power control:
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
Power profiles residing in boot ROM allow optimized performance and minimized power consumption for any given application through one simple function call.
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
Processor wake-up from Deep power-down mode using one special function pin.
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
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Rev. 2.2 — 11 March 2014
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Temperature range
40 C to +85 C.
Available as LQFP48, TFBGA48, and HVQFN33 packages.
Pin compatible to the LPC134x series.
3. Applications
Consumer peripherals
Medical
Industrial control
Handheld scanners
USB audio devices
Table 1.
Ordering information
Type number Package
Name
LPC11U12FHN33/201 HVQFN33
LPC11U12FBD48/201 LQFP48
LPC11U13FBD48/201 LQFP48
LPC11U14FHN33/201 HVQFN33
LPC11U14FHI33/201 HVQFN33
LPC11U14FBD48/201 LQFP48
LPC11U14FET48/201 TFBGA48
Description Version plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7
7 0.85 mm n/a plastic low profile quad flat package; 48 leads; body 7
7 1.4 mm
SOT313-2 plastic low profile quad flat package; 48 leads; body 7
7 1.4 mm
SOT313-2 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7
7 0.85 mm n/a plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5
5 0.85 mm n/a plastic low profile quad flat package; 48 leads; body 7
7 1.4 mm
SOT313-2 plastic thin fine-pitch ball grid array package; 48 balls; body
4.5
4.5 0.7 mm
SOT1155-2
4.1 Ordering options
Table 2.
Ordering options
Type number Flash SRAM
LPC11U12FHN33/201
LPC11U12FBD48/201
LPC11U13FBD48/201
LPC11U14FHN33/201
LPC11U14FHI33/201
LPC11U14FBD48/201
LPC11U14FET48/201
CPU
16 kB 4 kB
16 kB 4 kB
24 kB 4 kB
32 kB 4 kB
32 kB 4 kB
32 kB 4 kB
32 kB 4 kB
USB
2 kB
2 kB
2 kB
2 kB
2 kB
2 kB
2 kB
Total
6 kB 1
6 kB 1
6 kB 1
6 kB 1
6 kB 1
6 kB 1
6 kB 1
USART I 2 C-bus
FM+
SSP USB device
ADC channels
GPIO pins
1
1
1
1
1
1
1
2
2
2
2
2
2
2
1
1
1
1
1
1
1
8
8
8
8
8
8
8
26
26
40
40
26
40
40
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
SWD, JTAG
XTALIN XTALOUT RESET
GPIO ports 0/1
RXD
TXD
DCD, DSR
(1)
, RI
(1)
CTS, RTS, DTR
SCLK
CT16B0_MAT[1:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
CT32B0_MAT[3:0]
CT32B0_CAP[1:0]
(1)
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
(2)
LPC11U12/13/14
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
SYSTEM OSCILLATOR
IRC, WDO
BOD
POR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
PLL0 USB PLL system bus
HIGH-SPEED
GPIO slave
FLASH
16/24/32 kB slave slave
SRAM
6 kB
AHB-LITE BUS slave
ROM
16 kB master slave
USB DEVICE
CONTROLLER slave
AHB TO APB
BRIDGE
USART/
SMARTCARD INTERFACE
10-bit ADC
I
2
C-BUS
16-bit COUNTER/TIMER 0
SSP0
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
SSP1
IOCON
32-bit COUNTER/TIMER 1
WINDOWED WATCHDOG
TIMER
SYSTEM CONTROL
PMU
GPIO pins
GPIO pins
GPIO pins
GPIO PIN INTERRUPTS
GPIO GROUP0 INTERRUPT
GPIO GROUP1 INTERRUPT
CLKOUT
USB_DP
USB_DM
USB_VBUS
USB_FTOGGLE,
USB_CONNECT
AD[7:0]
SCL, SDA
SCK0, SSEL0,
MISO0, MOSI0
SCK1, SSEL1,
MISO1, MOSI1
002aaf885
(1) DSR, RI, CT32B0_CAP1 are not available on HVQFN33 packages.
(2) CT32B1_CAP1 is available only on the TFBGA48package.
Fig 1.
Block diagram
LPC11U1X
Product data sheet
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6.1 Pinning
LPC11U1x
32-bit ARM Cortex-M0 microcontroller terminal 1 index area
PIO1_19/DTR/SSEL1
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
XTALIN
XTALOUT
V
DD
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
1
2
3
4
5
6
7
8
LPC11U1x
33 V
SS
24
23
22
21
20
19
18
17
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_8/MISO0/CT16B0_MAT0
002aaf888
Fig 2.
Pin configuration (HVQFN33)
Transparent top view
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
PIO1_25/CT32B0_MAT1
PIO1_19/DTR/SSEL1
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
V
SS
XTALIN
XTALOUT
V
DD
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO1_26/CT32B0_MAT2/RXD
PIO1_27/CT32B0_MAT3/TXD
7
8
5
6
3
4
1
2
9
10
11
12
LPC11U1x
32
31
30
29
36
35
34
33
PIO1_13/DTR/CT16B0_MAT0/TXD
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO1_29/SCK0/CT32B0_CAP1
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
28
27
26
25
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_8/MISO0/CT16B0_MAT0
PIO1_21/DCD/MISO1
PIO1_31
002aaf884
Fig 3.
Pin configuration (LQFP48)
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller ball A1 index area
1 2 3
LPC11U1x
4 5 6 7 8
A
B
C
D
E
F
G
H
Transparent top view
002aag101
Fig 4.
Pin configuration (TFBGA48)
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigned digital or analog functions ordered by GPIO port
number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 4 shows how peripheral functions are assigned to port pins.
Table 3.
Pin description
Symbol Reset state
Type Description
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3/USB_VBUS
LPC11U1X
Product data sheet
2
3 4 C2
I/O
I; PU I/O
8
3
10
C1
F1
9 14 H2
I; PU I
-
O
O
O
I; PU I/O
-
-
I
I/O
I; PU I/O
I
RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin also serves as the debug select input. LOW level selects the JTAG boundary scan. HIGH level selects the ARM SWD debug mode.
In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and
Deep power-down mode is not used.
PIO0_0 — General purpose digital input/output pin.
PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
USB_FTOGGLE — USB 1 ms Start-of-Frame signal.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave select for SSP0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
USB_VBUS — Monitors the presence of USB bus power.
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description …continued
Symbol Reset state
[1]
Type Description
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/USB_CONNECT/
SCK0
PIO0_7/CTS
PIO0_8/MISO0/
CT16B0_MAT0
PIO0_9/MOSI0/
CT16B0_MAT1
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2
TDI/PIO0_11/AD0/
CT32B0_MAT3
LPC11U1X
Product data sheet
10 15 G3
I; IA I/O
I/O
11
15
16
17
18
19
21
16
22
23
27
28
29
32
H3
H6
G7
F8
F7
E7
D8
I; IA I/O
I/O
I; PU I/O
O
I/O
I; PU I/O
I
I; PU I/O
-
I/O
O
I; PU I/O
-
-
I; PU I
I/O
O
I/O
-
O
O
-
I; PU I
I/O
-
I
O
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I 2 C-bus clock input/output (open-drain).
High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I 2 C-bus data input/output (open-drain).
High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.
PIO0_6 — General purpose digital input/output pin.
USB_CONNECT — Signal used to switch an external 1.5 k
resistor under software control.
Used with the SoftConnect USB feature.
SCK0 — Serial clock for SSP0.
PIO0_7 — General purpose digital input/output pin (high-current output driver).
CTS — Clear To Send input for USART.
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SSP0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9 — General purpose digital input/output pin.
MOSI0 — Master Out Slave In for SSP0.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK — Serial wire clock and test clock TCK for JTAG interface.
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SSP0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
TDI — Test Data In for JTAG interface.
PIO0_11 — General purpose digital input/output pin.
AD0 — A/D converter, input 0.
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description …continued
Symbol Reset state
[1]
Type Description
TMS/PIO0_12/AD1/
CT32B1_CAP0
TDO/PIO0_13/AD2/
CT32B1_MAT0
TRST/PIO0_14/AD3/
CT32B1_MAT1
SWDIO/PIO0_15/AD4/
CT32B1_MAT2
PIO0_16/AD5/
CT32B1_MAT3/WAKEUP
PIO0_17/RTS/
CT32B0_CAP0/SCLK
LPC11U1X
Product data sheet
22
23
24
25
26
30
33
34
35
39
40
45
C7
C8
B7
B6
A6
A3
-
-
-
-
-
-
I; PU I
I/O
I
I
-
I; PU O
I/O
-
I
O
-
I; PU I
I/O
-
I
O
-
I; PU I/O
I/O
-
I
O
I; PU I/O
-
-
I
I
O
I; PU I/O
I
O
I/O
TMS — Test Mode Select for JTAG interface.
PIO_12 — General purpose digital input/output pin.
AD1 — A/D converter, input 1.
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
TDO — Test Data Out for JTAG interface.
PIO0_13 — General purpose digital input/output pin.
AD2 — A/D converter, input 2.
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
TRST — Test Reset for JTAG interface.
PIO0_14 — General purpose digital input/output pin.
AD3 — A/D converter, input 3.
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO — Serial wire debug input/output.
PIO0_15 — General purpose digital input/output pin.
AD4 — A/D converter, input 4.
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO0_16 — General purpose digital input/output pin.
AD5 — A/D converter, input 5.
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.
PIO0_17 — General purpose digital input/output pin.
RTS — Request To Send output for USART.
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
SCLK — Serial clock input/output for USART in synchronous mode.
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description …continued
Symbol Reset state
[1]
Type Description
PIO0_18/RXD/
CT32B0_MAT0
PIO0_19/TXD/
CT32B0_MAT1
PIO0_20/CT16B1_CAP0
PIO0_21/CT16B1_MAT0/
MOSI1
PIO0_22/AD6/
CT16B1_MAT1/MISO1
PIO0_23/AD7
PIO1_5/CT32B1_CAP1
PIO1_13/DTR/
CT16B0_MAT0/TXD
-
-
31
32
7
B3
B2
F2
12 17 G4
20
27
-
46
47
9
30
42
36
E8
A5
H8
B8
I; PU I/O
I
O
I; PU I/O
O
O
I; PU I/O
I
I; PU I/O
O
I/O
I; PU I/O
-
I
O
I/O
I; PU I/O
I
I; PU I/O
I
I; PU I/O
-
-
-
O
O
O
PIO0_18 — General purpose digital input/output pin.
RXD — Receiver input for USART.Used in
UART ISP mode.
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO0_19 — General purpose digital input/output pin.
TXD — Transmitter output for USART. Used in
UART ISP mode.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO0_20 — General purpose digital input/output pin.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO0_21 — General purpose digital input/output pin.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
MOSI1 — Master Out Slave In for SSP1.
PIO0_22 — General purpose digital input/output pin.
AD6 — A/D converter, input 6.
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
MISO1 — Master In Slave Out for SSP1.
PIO0_23 — General purpose digital input/output pin.
AD7 — A/D converter, input 7.
PIO1_5 — General purpose digital input/output pin.
CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
PIO1_13 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for USART.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
TXD — Transmitter output for USART.
LPC11U1X
Product data sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description …continued
Symbol Reset state
[1]
Type Description
PIO1_14/DSR/
CT16B0_MAT1/RXD
PIO1_15/DCD/
CT16B0_MAT2/SCK1
PIO1_16/RI/
CT16B0_CAP0
PIO1_19/DTR/SSEL1
PIO1_20/DSR/SCK1
PIO1_21/DCD/MISO1
PIO1_22/RI/MOSI1
PIO1_23/CT16B1_MAT1/
SSEL1
-
-
-
-
-
28
1
37
43
48
2
13
A8
A4
A2
B1
H1
26 G8
38
18
A7
H4
I; PU I/O
-
I
O
I
I; PU I/O
-
I
O
I/O
I; PU I/O
-
-
I
I
I; PU I/O
-
O
I/O
I; PU I/O
-
I
I/O
I; PU I/O
-
I
I/O
I; PU I/O
-
I
I/O
I; PU I/O
-
O
I/O
PIO1_14 — General purpose digital input/output pin.
DSR — Data Set Ready input for USART.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
RXD — Receiver input for USART.
PIO1_15 — General purpose digital input/output pin.
DCD — Data Carrier Detect input for USART.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
SCK1 — Serial clock for SSP1.
PIO1_16 — General purpose digital input/output pin.
RI — Ring Indicator input for USART.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO1_19 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for USART.
SSEL1 — Slave select for SSP1.
PIO1_20 — General purpose digital input/output pin.
DSR — Data Set Ready input for USART.
SCK1 — Serial clock for SSP1.
PIO1_21 — General purpose digital input/output pin.
DCD — Data Carrier Detect input for USART.
MISO1 — Master In Slave Out for SSP1.
PIO1_22 — General purpose digital input/output pin.
RI — Ring Indicator input for USART.
MOSI1 — Master Out Slave In for SSP1.
PIO1_23 — General purpose digital input/output pin.
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
SSEL1 — Slave select for SSP1.
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description …continued
Symbol Reset state
[1]
Type Description
PIO1_31
USB_DM
USB_DP
XTALIN
XTALOUT
V
DD
V
SS
PIO1_24/CT32B0_MAT0
PIO1_25/CT32B0_MAT1
PIO1_26/CT32B0_MAT2/
RXD
PIO1_27/CT32B0_MAT3/
TXD
PIO1_28/CT32B0_CAP0/
SCLK
PIO1_29/SCK0/
CT32B0_CAP1
LPC11U1X
Product data sheet
-
-
-
-
-
-
21 G6
1
11
12
A1
G2
G1
I; PU I/O
O
I; PU I/O
O
I; PU I/O
O
I
I; PU I/O
24
31
25 -
H7
D7
13 19 G5
14 20 H5
4 6 D1
O
O
I; PU I/O
I
I/O
I; PU I/O
-
-
-
F
F -
-
-
I
I/O
I; PU I/O
5 7 E1
6;
29
8;
44
B4,
E2
33 5;
41
B5,
D2
-
-
-
-
-
-
PIO1_24 — General purpose digital input/output pin.
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_25 — General purpose digital input/output pin.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_26 — General purpose digital input/output pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
RXD — Receiver input for USART.
PIO1_27 — General purpose digital input/output pin.
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
TXD — Transmitter output for USART.
PIO1_28 — General purpose digital input/output pin.
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
SCLK — Serial clock input/output for USART in synchronous mode.
PIO1_29 — General purpose digital input/output pin.
SCK0 — Serial clock for SSP0.
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0.
PIO1_31 — General purpose digital input/output pin.
USB_DM — USB bidirectional D
line.
USB_DP — USB bidirectional D+ line.
Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.
Output from the oscillator amplifier.
Supply voltage to the internal regulator, the external rail, and the ADC. Also used as the
ADC reference voltage.
Ground.
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[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See
for the reset pad configuration.
[3]
[4] For parts with bootloader version 7.0, both pins (PIO0_1, PIO0_3) must be pulled LOW to enter UART ISP mode.
[5] I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
); includes high-current output driver.
[7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
); includes digital input glitch filter.
[8] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant.
[9] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
To assign a peripheral function to a port, program the FUNC bits in the port pin’s IOCON register with this function. The user must ensure that the assignment of a function to a port pin is unambiguous. Only the debug functions for JTAG and SWD are selected by default in their corresponding IOCON registers. All other functions must be programmed in the
IOCON block before they can be used. For details see the LPC11Uxx user manual.
Table 4.
Multiplexing of peripheral functions
Peripheral Function Type Default Available on ports
HVQFN33/LQFP48/TFBGA48 LQFP48/TFBGA48
USART RXD
TXD
CTS
RTS
I
O
I
O no no no no
PIO0_18
PIO0_19
PIO0_7
PIO0_17 -
-
-
-
-
-
PIO1_14
PIO1_13
-
-
PIO1_26
PIO1_27
-
PIO1_19
SSP0
SSP1
DTR
DSR
DCD
RI
SCLK
SCK0
SSEL0
MISO0
MOSI0
SCK1
SSEL1
MISO1
MOSI1
I/O
I/O
I/O
I/O
I
I
I
O
I/O
I/O
I/O
I/O
I/O no no no no no no no no no no no no no
-
PIO1_13
-
PIO1_15
PIO0_17
PIO0_6
PIO0_2
PIO0_8
PIO0_9
PIO1_15
PIO1_19
PIO0_22
PIO0_21
-
-
-
-
-
-
-
PIO0_10
-
PIO1_14
PIO1_21 -
PIO1_16 PIO1_22
PIO1_28
PIO1_29
-
-
PIO1_20
-
-
-
PIO1_20
-
-
-
-
PIO1_23
PIO1_21
PIO1_22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TFBGA48
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 4.
Multiplexing of peripheral functions …continued
Peripheral Function Type Default Available on ports
HVQFN33/LQFP48/TFBGA48 LQFP48/TFBGA48
CT16B0 CT16B0_CAP0
CT16B0_MAT0
CT16B0_MAT1
I
O
O no no no
PIO0_2
PIO0_8
PIO0_9 -
-
PIO1_16
PIO1_13
PIO1_14 -
-
-
CT16B1
CT32B0
CT16B0_MAT2
CT16B1_CAP0
CT16B1_MAT0
CT16B1_MAT1
CT32B0_CAP0
CT32B0_CAP1
CT32B0_MAT0
CT32B0_MAT1
I
I
I
O
O
O
O
O no no no no no no no no
PIO0_10
PIO0_20
PIO0_21
PIO0_22
PIO0_17
PIO1_29
PIO0_18
PIO0_19
-
-
-
-
-
-
-
-
-
PIO1_15 -
-
-
-
PIO1_23
PIO1_28
PIO1_24
PIO1_25
CT32B1
CT32B0_MAT2
CT32B0_MAT3
CT32B1_CAP0
CT32B1_CAP1
CT32B1_MAT0
CT32B1_MAT1
CT32B1_MAT2
CT32B1_MAT3
O
O
O
O
I
I
O
O no no no no no no no no
PIO0_1
PIO0_11
-
PIO0_12
PIO0_13
PIO0_14
PIO0_15
PIO0_16 -
-
-
-
-
-
PIO1_26
PIO1_27
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC
-
-
-
-
-
-
-
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7 I
I
I
I
I
I
I
I no no no no no no no no
PIO0_11
PIO0_12
PIO0_13
PIO0_14
PIO0_15
PIO0_16
PIO0_22
PIO0_23 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USB
-
-
-
-
-
-
-
-
CLKOUT
JTAG
SWD
USB_VBUS I
USB_FTOGGLE O
USB_CONNECT O
CLKOUT O
TDI
TMS
TDO
TRST
I
I
I
O
TCK
SWCLK
SWDIO
I
I
I/O yes yes yes yes no no no no yes yes yes
PIO0_3
PIO0_1
PIO0_6
PIO0_1
PIO0_11
PIO0_12
PIO0_13
PIO0_14
PIO0_10
PIO0_10
PIO0_15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PIO1_5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TFBGA48
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.1 On-chip flash programming memory
The LPC11U1x contain up to 32 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software.
7.2 SRAM
The LPC11U1x contain a total of 6 kB on-chip static RAM memory.
7.3 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash programming
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
7.4 Memory map
The LPC11U1x incorporates several distinct memory regions, shown in the following
shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
4 GB
LPC11U12/13/14 reserved private peripheral bus
0xFFFF FFFF
0xE010 0000
0xE000 0000 reserved
1 GB
0.5 GB
0 GB
GPIO reserved
USB
APB peripherals reserved
2 kB USB RAM reserved reserved
16 kB boot ROM reserved
0x5000 4000
0x5000 0000
0x4008 4000
0x4008 0000
0x4000 0000
0x2000 4800
0x2000 4000
0x2000 0000
0x1FFF 4000
0x1FFF 0000
4 kB SRAM
0x1000 1000
0x1000 0000 reserved
32 kB on-chip flash (LPC11U14)
24 kB on-chip flash (LPC11U13)
16 kB on-chip flash (LPC11U12)
0x0000 8000
0x0000 6000
0x0000 4000
0x0000 0000
19
18
17
16
15
14
24
23
22
APB peripherals
0x4008 0000
25 - 31 reserved
GPIO GROUP1 interrupt
GPIO GROUP0 interrupt
SSP1
20 - 21 reserved
GPIO pin interrupt system control
IOCON
SSP0 flash controller
PMU
0x4006 4000
0x4006 0000
0x4005 C000
0x4005 8000
0x4004 C000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
6
5
4
3
2
1
0
9
8
7
10 - 13 reserved reserved reserved
ADC
32-bit counter/timer 1
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
USART/SMART CARD
WWDT
I
2
C-bus
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000 active interrupt vectors
0x0000 00C0
0x0000 0000
002aaf891
Fig 5.
LPC11U1x memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11U1x, the NVIC supports 24 vectored interrupts.
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LPC11U1x
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• Four programmable interrupt priority levels, with hardware priority level masking.
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
7.6 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupts being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
7.6.1 Features
• Programmable pull-up, pull-down, or repeater mode.
• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V
DD
= 3.3 V) if their pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable 10-ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned on by default.
• Programmable hysteresis.
• Programmable input inverter.
7.7 General Purpose Input/Output GPIO
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.
LPC11U1x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved.
• Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.
2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO pins.
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7.7.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request.
• Port interrupts can be triggered by any pin or pins in each port.
7.8 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller.
The LPC11U1x USB interface consists of a full-speed device controller with on-chip PHY for device functions.
Remark: Configure the LPC11U1x in default power mode with the power profiles before
using the USB (see Section 7.16.5.1
). Do not use the USB with the part in performance,
efficiency, or low-power mode.
7.8.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled.
7.8.1.1
Features
• Dedicated USB PLL available.
• Fully compliant with USB 2.0 specification (full speed).
• Supports 10 physical (5 logical) endpoints including one control endpoint.
• Single and double buffering supported.
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
• Supports wake-up from Deep-sleep mode and Power-down mode on USB activity and remote wake-up.
• Supports SoftConnect.
7.9 USART
The LPC11U1x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart card interface. The RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.
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The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.9.1 Features
• Maximum USART data bit rate of 3.125 Mbit/s.
• 16-byte receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
• Support for synchronous mode.
• Includes smart card interface.
7.10 SSP serial I/O controller
The SSP controllers are capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.
7.10.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.11 I 2 C-bus serial I/O controller
The LPC11U1x contain one I 2 C-bus controller.
The I 2 C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2 C is a multi-master bus and can be controlled by more than one bus master connected to it.
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7.11.1 Features
• The I 2 C-interface is an I 2 C-bus compliant interface with open-drain pins. The I 2 C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.
• The I 2 C-bus can be used for test and diagnostic purposes.
• The I 2 C-bus controller supports multiple address recognition and a bus monitor mode.
7.12 10-bit ADC
The LPC11U1x contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.
7.12.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to V
DD
.
• 10-bit conversion time
2.44 s (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 General purpose external event counter/timers
The LPC11U1x includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
7.13.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt.
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• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.
7.14 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.15 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window.
7.15.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (T cy(WDCLK)
256 4) to (T cy(WDCLK) multiples of T cy(WDCLK)
4.
2 24 4) in
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). This gives a wide range of potential timing choices of watchdog operation under different power conditions.
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.16 Clocking and power control
7.16.1 Integrated oscillators
The LPC11U1x include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.
Following reset, the LPC11U1x will operate from the internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.
See
Figure 6 for an overview of the LPC11U1x clock generation.
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
SYSTEM CLOCK
DIVIDER system clock
CPU, system control,
PMU n
SYSAHBCLKCTRLn
(AHB clock enable) memories, peripheral clocks
IRC oscillator watchdog oscillator main clock
MAINCLKSEL
(main clock select)
IRC oscillator system oscillator
SYSPLLCLKSEL
(system PLL clock select)
SYSTEM PLL system oscillator
USBPLLCLKSEL
(USB clock select)
USB PLL
SSP0 PERIPHERAL
CLOCK DIVIDER
USART PERIPHERAL
CLOCK DIVIDER
SSP1 PERIPHERAL
CLOCK DIVIDER
SSP0
UART
SSP1
USB 48 MHz CLOCK
DIVIDER
USB
USBUEN
(USB clock update enable)
IRC oscillator system oscillator watchdog oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUTUEN
(CLKOUT update enable)
IRC oscillator watchdog oscillator
WDCLKSEL
(WDT clock select)
CLKOUT pin
WDT
002aaf892
Fig 6.
LPC11U1x clocking generation block diagram
7.16.1.1
Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U1x use the IRC as the clock source. Software may later switch to one of the other available clock sources.
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.16.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U1x, the system oscillator must be used to provide the clock source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.
7.16.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is
40 % (see also
).
7.16.2 System PLL and USB PLL
The LPC11U1x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100
s.
7.16.3 Clock output
The LPC11U1x features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.16.4 Wake-up process
The LPC11U1x begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.
7.16.5 Power control
The LPC11U1x support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control.
7.16.5.1
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the
LPC11U1x for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock.
Remark: When using the USB, configure the LPC11U1x in Default mode.
7.16.5.2
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.
7.16.5.3
Deep-sleep mode
In Deep-sleep mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all clock sources are off with the exception of the IRC. The IRC output is disabled unless the
IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection.
The LPC11U1x can wake up from Deep-sleep mode via reset, selected GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
7.16.5.4
Power-down mode
In Power-down mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all clock sources are off with the exception of watchdog oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the user has the option to keep the BOD circuit running for BOD protection.
The LPC11U1x can wake up from Power-down mode via reset, selected GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity.
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times.
7.16.5.5
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC11U1x can wake up from Deep power-down mode via the
WAKEUP pin.
The LPC11U1x can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block. Locking out Deep power-down mode enables the user to always keep the watchdog timer or the BOD running.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode.
7.16.6 System control
7.16.6.1
Reset
Reset has four sources on the LPC11U1x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is used.
7.16.6.2
Brownout detection
The LPC11U1x includes four levels for monitoring the voltage on the V
DD
pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip.
7.16.6.3
Code security (Code Read Protection - CRP)
This feature of the LPC11U1x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC11U1x user manual.
There are three levels of Code Read Protection:
LPC11U1X
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CAUTION
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the USART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC11U1x user manual.
7.16.6.4
APB interface
The APB peripherals are located on one APB bus.
7.16.6.5
AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the ROM.
7.16.6.6
External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.17 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U1x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250
s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
Parameter supply voltage (core and external rail)
Conditions
V
I
V
IA input voltage analog input voltage
5 V tolerant digital I/O pins;
V
DD
1.8 V
V
DD
= 0 V
5 V tolerant open-drain pins
PIO0_4 and PIO0_5 pin configured as analog input
Min
0.5
0.5
0.5
0.5
Max
+4.6
+5.5
+3.6
+5.5
Unit
V
V
V
I
I
I
T
T
DD
SS latch
P
V stg j(max) tot(pack)
ESD supply current ground current
I/O latch-up current storage temperature maximum junction temperature total power dissipation (per package) electrostatic discharge voltage per supply pin per ground pin
(0.5V
DD
) < V
I
< (1.5V
DD
);
T j
< 125
C non-operating based on package heat transfer, not device power consumption human body model; all pins
0.5 4.6
-
-
-
-
-
-
65
100
100
100
+150
150
1.5
+6500
V mA mA mA
C
C
W
V
[1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 6 .
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 6
) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See
Table 7 for maximum operating voltage.
[4] V
DD
present or not present. Compliant with the I
2
C-bus standard. 5.5 V can be applied to this pin when V
DD
is powered down.
[5] Including voltage on outputs in 3-state mode.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
series resistor.
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics
T amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions
V
DD supply voltage (core and external rail)
I
DD supply current Active mode; V
DD
= 3.3 V;
T amb
= 25
C; code while(1){} executed from flash; system clock = 12 MHz
Min
1.8
3.3
system clock = 50 MHz
I
I
Sleep mode;
V
DD
= 3.3 V; T amb
= 25
C; system clock = 12 MHz
Deep-sleep mode; V
DD
T amb
= 25
C
= 3.3 V;
Power-down mode; V
DD
T amb
= 25
C
= 3.3 V;
Deep power-down mode;
V
DD
= 3.3 V; T amb
= 25
C
Standard port pins, RESET
I
IL
LOW-level input current V
I
= 0 V; on-chip pull-up resistor disabled
I
IH
OZ
V
V
V
V
V
V
V
I
O
IH
IL hys
OH
OL
OH
HIGH-level input current
OFF-state output current input voltage
V
V
I
O
= V
DD disabled
; on-chip pull-down resistor
= 0 V; V
O
= V
DD
; on-chip pull-up/down resistors disabled pin configured to provide a digital function output voltage
HIGH-level input voltage
LOW-level input voltage output active hysteresis voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
2.0 V
V
DD
3.6 V; I
OH
=
4 mA
1.8 V
V
DD
< 2.0 V; I
OH
=
3 mA
2.0 V
V
DD
3.6 V; I
OL
= 4 mA
1.8 V
V
DD
< 2.0 V; I
OL
= 3 mA
V
OH
= V
DD
0.4 V;
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
-
-
-
-
-
-
-
-
-
0
0
0.7V
DD
-
-
-
-
2
7
1
360
2
220
0.5
0.5
0.5
-
-
-
-
-
0.4
V
DD
0.4 -
V
DD
0.4 -
-
-
4
3
Max
3.6
-
-
-
-
-
-
Unit
V
-
10
10
10
5.0
-
V
DD
V
V
-
-
0.3V
DD
-
0.4
-
0.4
V
V
V
V
V
V mA nA nA nA
V mA
A
A nA mA mA mA
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
T amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions
I
OL
I
OHS
LOW-level output current
HIGH-level short-circuit output current
V
OL
= 0.4 V
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
V
OH
= 0 V
I
I
I
I
I
I
OLS
LOW-level short-circuit output current pull-down current
V
OL
= V
DD
I
I pd pu pull-up current
V
I
= 5 V
V
I
= 0 V;
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
V
DD
< V
I
< 5 V
I
High-drive output pin (PIO0_7)
I
IL
IH
LOW-level input current V
HIGH-level input current
I
= 0 V; on-chip pull-up resistor disabled
V
I
= V
DD disabled
; on-chip pull-down resistor
I
OZ
V
I
OFF-state output current input voltage
V
O
= 0 V; V
O
= V
DD
; on-chip pull-up/down resistors disabled pin configured to provide a digital function
V
O
V
IH
V
V
V
V
IL hys
OH
OL
OH
OL
OLS pd pu output voltage
HIGH-level input voltage
LOW-level input voltage output active hysteresis voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
2.5 V
V
DD
3.6 V; I
OH
=
20 mA
1.8 V
V
DD
< 2.5 V; I
OH
=
12 mA
2.0 V
V
DD
3.6 V; I
OL
= 4 mA
1.8 V
V
DD
< 2.0 V; I
OL
= 3 mA
V
OH
= V
DD
2.5 V
V
0.4 V;
DD
3.6 V
1.8 V
V
DD
< 2.5 V
V
OL
= 0.4 V
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
V
OL
= V
DD
LOW-level short-circuit output current pull-down current pull-up current
V
I
= 5 V
V
I
= 0 V
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
V
DD
< V
I
< 5 V
LPC11U1X
Product data sheet
-
3
-
0
0
0.7V
DD
-
3
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Rev. 2.2 — 11 March 2014
-
-
-
Min
4
10
15
10
0
12
4
10
15
10
0
-
-
-
-
-
-
-
-
-
-
-
Typ [1]
50
50
50
0
0.5
0.5
0.5
-
-
0.4
-
V
DD
0.4 -
V
DD
0.4 -
-
-
20 -
-
50
50
50
0
-
-
-
Max
-
45
50
150
85
85
0
10
10
10
5.0
-
V
DD
-
-
0.3V
DD
-
0.4
-
0.4
-
50
150
85
85
0
Unit mA mA mA mA
A
A
A
A nA nA nA
V
V
V mA mA mA mA
A
A
A
A
© NXP Semiconductors N.V. 2014. All rights reserved.
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V
V
V
V
V
V mA
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
T amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter
I 2 C-bus pins (PIO0_4 and PIO0_5)
Conditions
I
I
I
V
V
V
IL hys
OL
OL
LI
IH
HIGH-level input voltage
LOW-level input voltage hysteresis voltage
LOW-level output current
LOW-level output current input leakage current
V
OL
= 0.4 V; I 2 C-bus pins configured as standard mode pins
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
V
OL
= 0.4 V; I 2 C-bus pins configured as Fast-mode Plus pins
2.0 V
V
DD
3.6 V
1.8 V
V
DD
< 2.0 V
V
I
= V
DD
V
I
= 5 V
Oscillator pins
V i(xtal) crystal input voltage
V o(xtal) crystal output voltage
USB pins
I
OZ
V
V
V
V
V
V
C
Z
BUS
DI
CM th(rs)se
OL
OH trans
DRV
OFF-state output current bus supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage
0 V < V
I
< 3.3 V
(D+) (D) includes V
DI
range
LOW-level output voltage
HIGH-level output voltage for low-/full-speed;
R
L
of 1.5 k
to 3.6 V driven; for low-/full-speed;
R
L
of 15 k
to GND transceiver capacitance pin to GND driver output impedance for driver which is not high-speed capable with 33
series resistor; steady state drive
-
16
-
-
-
-
3.5
3
20
-
0.2
0.8
0.8
-
Min
0.7V
DD
0.5
0.5
2.8
-
36
-
-
-
-
-
-
-
-
-
-
-
-
Typ [1]
-
2
10
-
Max Unit
V
-
-
0.05V
DD
-
-
0.3V
DD
V
V mA
1.8
1.8
-
-
-
4
22
1.95
1.95
10
-
5.25
2.5
2.0
0.18
3.5
20
44.1
mA
V
V
A
A
A
V
V
V
V
V
V pF
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
T amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions
Pin capacitance
C io input/output capacitance pins configured for analog function
I 2 C-bus pins (PIO0_4 and PIO0_5) pins configured as GPIO
-
-
-
Min
-
-
-
Typ [1] Max
7.1
2.5
2.8
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
[2] For USB operation 3.0 V
V
DD((3V3)
3.6 V. Guaranteed by design.
[3] IRC enabled; system oscillator disabled; system PLL disabled.
[4] I
DD
measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[5] BOD disabled.
[6] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block.
[7] USB_DP and USB_DM pulled LOW externally.
[8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[9] IRC disabled; system oscillator enabled; system PLL enabled.
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[11] Including voltage on outputs in 3-state mode.
[12] V
DD
supply voltage must be present.
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To V
SS
.
[16] Includes external resistors of 33
1 % on USB_DP and USB_DM.
Unit pF pF pF
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Table 7.
ADC static characteristics
T amb
=
40
C to +85
C unless otherwise specified; ADC frequency 4.5 MHz, V
DD
= 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ
E
O
E
G
E
T
R vsi
V
IA
C ia
E
D
E
L(adj) analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
R i voltage source interface resistance input resistance
-
Max
V
DD
1
1
1.5
3.5
0.6
4
40
2.5
M
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See
[3] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See
[4] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
.
[5] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 7
.
[6] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 7
.
[7] T amb
= 25
C; maximum sampling frequency f s
= 400kSamples/s and analog input capacitance C ia
= 1 pF.
[8] Input resistance R i
depends on the sampling frequency fs: R i
= 1 / (f s
C ia
).
Unit
V pF
LSB
LSB
LSB
%
LSB k
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller offset error
E
O gain error
E
G
1023
1022
1021
1020
1019
1018
(2) code out
7
6
5
2
1
4
3
0
1 offset error
E
O
2
(4)
(5)
(3)
3 4
1 LSB
(ideal)
5 6 7
V
IA
(LSB ideal
)
(1)
1018 1019 1020 1021 1022 1023 1024
1 LSB =
V
DD
−
V
SS
1024
002aaf426
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (E
D
).
(4) Integral non-linearity (E
L(adj)
).
(5) Center of a step of the actual transfer curve.
Fig 7.
ADC characteristics
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9.1 BOD static characteristics
Table 8.
BOD static characteristics
T amb
= 25
C.
Symbol Parameter Conditions
V th threshold voltage interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min Typ
2.22
2.35
2.52
2.66
2.80
2.90
1.46
1.63
2.06
2.15
2.35
2.43
2.63
2.71
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see
LPC11U1x user manual.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11U1x user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
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48 MHz
(2)
002aag749
9
I
DD
(mA)
6
3
36 MHz
(2)
24 MHz
(2)
12 MHz
(1)
0
1.8
2.4
3.0
3.6
V
DD
(V)
Conditions: T amb
= 25
C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and
USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 8.
Typical supply current versus regulator supply voltage V
DD
in active mode
002aag750
I
DD
(mA)
9
6
48 MHz
(2)
36 MHz
(2)
3
24 MHz
(2)
12 MHz
(1)
0
-40 -15 10 35 60 temperature (°C)
85
Conditions: V
DD
= 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 9.
Typical supply current versus temperature in Active mode
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32-bit ARM Cortex-M0 microcontroller
48 MHz
(2)
36 MHz
(2)
24 MHz
(2)
12 MHz
(1)
002aag751
4
I
DD
(mA)
3
2
1
0
-40 -15 10 35 60 temperature (°C)
85
Conditions: V
DD
= 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 10. Typical supply current versus temperature in Sleep mode
002aag745
385
I
DD
(μA)
375
V
DD
= 3.6 V
V
DD
= 3.3 V
365
355
V
DD
= 2.0 V
V
DD
= 1.8 V
345
-40 -15 10 35 60 temperature (°C)
85
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally.
Fig 11. Typical supply current versus temperature in Deep-sleep mode
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32-bit ARM Cortex-M0 microcontroller
20
I
DD
(μA)
15
10
5
V
DD
= 3.6 V, 3.3 V
V
DD
= 2.0 V
V
DD
= 1.8 V
002aag746
0
-40 -15 10 35 60 temperature (°C)
85
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally.
Fig 12. Typical supply current versus temperature in Power-down mode
0.8
I
DD
(μA)
0.6
V
DD
= 3.6 V
V
DD
= 3.3 V
V
DD
= 2.0 V
V
DD
= 1.8 V
002aag747
0.4
0.2
0
-40 -15 10 35 60 temperature (°C)
85
Fig 13. Typical supply current versus temperature in Deep power-down mode
9.3 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T amb
= 25
C. Unless noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
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Table 9.
Power consumption for individual analog and digital blocks
Peripheral Typical supply current in mA
Notes n/a 12 MHz 48 MHz
IRC 0.27
-
-
System oscillator running; PLL off; independent of main clock frequency.
IRC running; PLL off; independent of main clock frequency.
System oscillator at 12 MHz
0.22
0.004
Watchdog oscillator at
500 kHz/2
BOD
Main PLL
ADC
CLKOUT
-
-
-
0.051
-
-
0.21
0.08
0.12
-
-
-
0.29
0.47
-
-
System oscillator running; PLL off; independent of main clock frequency.
Independent of main clock frequency.
Main clock divided by 4 in the CLKOUTDIV register.
CT16B0
CT16B1
CT32B0
CT32B1
GPIO
IOCONFIG -
I2C
ROM
SPI0
SPI1
UART
WWDT
USB -
-
-
-
-
-
-
-
-
-
-
-
-
0.02
0.02
0.02
0.02
0.23
0.03
0.04
0.04
0.12
0.12
0.22
0.02
0.06
0.06
0.07
0.06
0.88
0.10
0.13
0.15
0.45
0.45
0.82
0.06
1.2
-
-
-
-
-
-
-
-
-
-
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register.
-
Main clock selected as clock source for the
WDT.
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9.4 Electrical pin characteristics
3.6
V
OH
(V)
3.2
T = 85 ° C
25 ° C
−
40
°
C
002aae990
2.8
2.4
2
0 10 20 30 40 50
I
OH
(mA)
60
Conditions: V
DD
= 3.3 V; on pin PIO0_7.
Fig 14. High-drive output: Typical HIGH-level output voltage V
OH
versus HIGH-level output current I
OH
.
002aaf019
60
I
OL
(mA)
40
T = 85
°
C
25
°
C
− 40 ° C
20
0
0 0.2
0.4
0.6
V
OL
(V)
Conditions: V
DD
= 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 15. I 2 C-bus pins (high current sink): Typical LOW-level output current I
OL
versus
LOW-level output voltage V
OL
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15
I
OL
(mA)
10
32-bit ARM Cortex-M0 microcontroller
T = 85
°
C
25
°
C
− 40 ° C
LPC11U1x
002aae991
5
0
0 0.2
0.4
0.6
V
OL
(V)
Conditions: V
DD
= 3.3 V; standard port pins and PIO0_7.
Fig 16. Typical LOW-level output current I
OL
versus LOW-level output voltage V
OL
002aae992
3.6
V
OH
(V)
3.2
T = 85
°
C
25 ° C
− 40 ° C
2.8
2.4
2
0 8 16 24
I
OH
(mA)
Conditions: V
DD
= 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage V
OH
versus HIGH-level output source current
I
OH
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002aae988
10
I pu
(
μ
A)
− 10
− 30
− 50
T = 85
°
C
25 ° C
− 40 ° C
− 70
0 1 2 3
Conditions: V
DD
= 3.3 V; standard port pins.
Fig 18. Typical pull-up current I pu
versus input voltage V
I
80
I pd
(
μ
A)
60
T = 85 ° C
25 ° C
− 40 ° C
4
V
I
(V)
5
002aae989
40
20
0
0 1 2 3
Conditions: V
DD
= 3.3 V; standard port pins.
Fig 19. Typical pull-down current I pd
versus input voltage V
I
4
V
I
(V)
5
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10. Dynamic characteristics
10.1 Flash memory
Table 10.
Flash characteristics
T amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions
N endu t ret endurance retention time t er erase time powered unpowered sector or multiple consecutive sectors t prog programming time
Min Typ
10000 100000 -
Max
10 -
20
95
-
100
-
105
0.95
1 1.05
Unit cycles years years ms ms
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
10.2 External clock
Table 11.
Dynamic characteristic: external clock
T amb
=
40
C to +85
C; V
DD
over specified ranges.
Symbol Parameter Conditions f osc
T cy(clk) t
CHCX t
CLCX t
CLCH t
CHCL oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time
Min
-
1
-
40
T cy(clk)
0.4
-
T cy(clk)
0.4
-
-
-
-
-
Typ
5
5
-
-
Max
25
1000
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
ns ns ns ns
Unit
MHz ns t
CHCL t
CLCX
T cy(clk) t
CHCX t
CLCH
002aaa907
Fig 20. External clock timing (with an amplitude of at least V i(RMS)
= 200 mV)
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10.3 Internal oscillators
Table 12.
Dynamic characteristics: IRC
T amb
=
40
C to +85
C; 2.7 V
V
DD
3.6 V
.
Symbol Parameter Conditions f osc(RC) internal RC oscillator frequency
-
Min
11.88
12
Max
12.12
Unit
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
002aaf403
12.15
f
(MHz)
12.05
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
2.4 V
2.0 V
11.95
11.85
− 40 − 15 10 35 60 temperature (
°
C)
85
Conditions: Frequency values are typical values. 12 MHz
1 % accuracy is guaranteed for
2.7 V
V
DD
3.6 V and T amb
=
40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz
1 % accuracy specification for voltages below 2.7 V.
Fig 21. Internal RC oscillator frequency versus temperature
Table 13.
Dynamic characteristics: Watchdog oscillator
Symbol Parameter Conditions f osc(int) internal oscillator frequency
DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register
-
Min Typ
7.8
-
Max Unit kHz
1700 kHz
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2] The typical frequency spread over processing and temperature (T amb
=
40 C to +85 C) is 40 %.
[3] See the LPC11U1x user manual.
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10.4 I/O pins t r t f
Table 14.
Dynamic characteristics: I/O pins
T amb
=
40
C to +85
C; 3.0 V
V
DD
3.6 V.
Symbol Parameter Conditions rise time fall time pin configured as output pin configured as output
[1] Applies to standard port pins and RESET pin.
Min
3.0
2.5
-
-
Typ Max
5.0
5.0
Unit ns ns f
SCL t f t
LOW t
HIGH t
HD;DAT t
SU;DAT
10.5 I 2 C-bus
Table 15.
Dynamic characteristic: I 2
T amb
=
40
C to +85
C.
Symbol Parameter Conditions
SCL clock frequency fall time
LOW period of the
SCL clock
HIGH period of the
SCL clock data hold time data set-up time
Standard-mode
Fast-mode
Fast-mode Plus of both SDA and SCL signals
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
-
-
0
0
Min
0
20 + 0.1
C b
4.7
1.3
0.5
4.0
0.6
0.26
0
0
0
250
100
50
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
400
1
300
300
120
Unit kHz kHz
MHz ns ns ns
s
s
s
s
s
s
s
s
s ns ns ns
[1] See the I
2
C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
IH
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] C b
= total capacitance of one bus line in pF.
[6] The maximum t f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f
is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f
.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing.
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[8] The maximum t
HD;DAT
could be 3.45
s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t
VD;DAT
or t
VD;ACK
by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge.
[10] A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system but the requirement t
SU;DAT
= 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the
Standard-mode I
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
SDA
70 %
30 % t f
SCL
S t f
70 %
30 %
1 / f
SCL
70 %
30 % t
HD;DAT t
SU;DAT
70 %
30 %
70 %
30 % t
LOW t
HIGH
70 %
30 % t
VD;DAT
002aaf425
Fig 22. I 2 C-bus pins clock timing
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10.6 SSP interface
Table 16.
Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter
SPI master (in SPI mode)
Conditions
T cy(clk) clock cycle time full-duplex mode when only transmitting
t
DS data set-up time in SPI mode
2.4 V
V
DD
3.6 V
2.0 V
V
DD
< 2.4 V
1.8 V
V
DD
< 2.0 V in SPI mode t
DH t v(Q) data hold time data output valid time in SPI mode t h(Q) data output hold time in SPI mode
SPI slave (in SPI mode)
PCLK cycle time T cy(PCLK) t
DS t
DH t v(Q) t h(Q) data set-up time data hold time in SPI mode in SPI mode data output valid time in SPI mode data output hold time in SPI mode
-
-
Min
50
40
15
20
24
0
0
20
-
0
3
T cy(PCLK)
+ 4 -
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
Max
10
-
3
T cy(PCLK)
+ 11
2
T cy(PCLK)
+ 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
[1] T cy(clk)
= (SSPCLKDIV
(1 + SCR) CPSDVSR) / f main
. The clock cycle time derived from the SPI bit rate T cy(clk)
is a function of the main clock frequency f main
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] T amb
=
40 C to 85 C.
[3] T cy(clk)
= 12
T cy(PCLK)
.
[4] T amb
= 25
C; for normal voltage supply range: V
DD
= 3.3 V.
LPC11U1X
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32-bit ARM Cortex-M0 microcontroller
T cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO t v(Q)
DATA VALID
DATA VALID
DATA VALID t
DS t
DH
DATA VALID t h(Q)
CPHA = 1
MOSI t v(Q)
DATA VALID
DATA VALID
DATA VALID t
DS t
DH
DATA VALID t h(Q)
MISO
Fig 23. SSP master timing in SPI mode
T cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO
DATA VALID t v(Q)
DATA VALID t
DS t
DH
DATA VALID
DATA VALID
CPHA = 0
002aae829 t h(Q) CPHA = 1
LPC11U1X
Product data sheet
MOSI
MISO
DATA VALID t v(Q)
DATA VALID t
DS t
DH
DATA VALID
DATA VALID t h(Q)
Fig 24. SSP slave timing in SPI mode
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Rev. 2.2 — 11 March 2014
CPHA = 0
002aae830
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
10.7 USB interface
Table 17.
Dynamic characteristics: USB pins (full-speed)
C
L
= 50 pF; R pu
= 1.5 k
on D+ to V
DD
; 3.0 V
V
DD
3.6 V.
Symbol Parameter Conditions t r t f t
FRFM
V
CRS t
FEOPT t
FDEOP t
JR1 t
JR2 t
EOPR rise time fall time differential rise and fall time matching output signal crossover voltage
10 % to 90 %
10 % to 90 %
t r
/ t f source SE0 interval of EOP source jitter for differential transition to SE0 transition see
see
receiver jitter to next transition receiver jitter for paired transitions 10 % to 90 %
EOP width at receiver must accept as
EOP; see
[1] Characterized but not implemented as production test. Guaranteed by design.
-
Min
8.5
7.7
1.3
160
2
18.5
9
82
T
PERIOD crossover point extended crossover point differential data lines
-
-
-
-
-
-
-
-
-
Typ Max
13.8
13.7
109
2.0
175
+5
-
+18.5
+9 ns ns ns
V ns ns
Unit ns ns
% differential data to
SE0/EOP skew n T
PERIOD
+ t
FDEOP source EOP width: t
FEOPT receiver EOP width: t
EOPR aaa-009330
Fig 25. Differential data-to-EOP transition skew and EOP width
LPC11U1X
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
11. Application information
11.1 Suggested USB interface solutions
The USB device can be connected to the USB as self-powered device (see
bus-powered device (see
).
On the LPC11U1x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when V
DD
is applied and at operating voltage level. Therefore, if the USB_VBUS function is connected to the
USB connector and the device is self-powered, the USB_VBUS pin must be protected for situations when V
DD
= 0 V.
If V
DD
is always greater than 0 V while VBUS = 5 V, the USB_VBUS pin can be connected directly to the VBUS pin on the USB connector.
For systems where V
DD
can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum allowable voltage on the USB_VBUS pin in this case.
One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be greater than 0.7V
DD
to indicate a logic HIGH while below the 3.6 V allowable maximum voltage.
For the following operating conditions
VBUS max
= 5.25 V
V
DD
= 3.6 V, the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.
V
DD
USB_CONNECT soft-connect switch
R1
1.5 kΩ
LPC1xxx
R2
R3
USB_VBUS
USB_DP
RS = 33 Ω
USB_DM
RS = 33 Ω
V
SS
USB-B connector
Fig 26. USB interface on a self-powered device where USB_VBUS = 5 V
LPC11U1X
Product data sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
For a bus-powered device, the VBUS signal does not need to be connected to the
USB_VBUS pin (see
). The USB_CONNECT function can additionally be connected as shown in
to prevent the USB from timing out when there is a significant delay between power-up and handling USB traffic.
V
DD
REGULATOR
LPC1xxx
R1
1.5 kΩ
VBUS
USB_DP RS = 33 Ω
USB_DM
RS = 33 Ω
V
SS
USB-B connector aaa-010179
Fig 27. USB interface on a bus-powered device
Remark: When a bus-powered circuit as shown in
Figure 27 is used, configure the
PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block to ensure that the
USB_CONNECT signal can still be controlled by software. For details on the soft-connect feature, see the LPC11U1x user manual (
Remark: When a self-powered circuit is used without connecting VBUS, configure the
PIO0_3/USB_VBUS pin for GPIO (PIO0_3) and provide software that can detect the host presence through some other mechanism before enabling USB_CONNECT and the soft-connect feature. Enabling the soft-connect without host presence will lead to USB compliance failure.
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with
C i
= 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground C g
which attenuates the input voltage by a factor C i
/(C i
+ C g
). In slave mode, a minimum of 200 mV(RMS) is needed.
LPC11U1X
Product data sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
LPC1xxx
XTALIN
Ci
100 pF
Cg
002aae788
Fig 28. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in
and in
Table 18 and Table 19 . Since the feedback resistance is integrated on chip, only a crystal
and the capacitances C
X1
and C
X2
need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, C
L
and
R
S
). Capacitance C
P
in Figure 29 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters F
OSC
, C
L
, R
S
and C
P
are supplied by the crystal manufacturer.
LPC1xxx
XTALIN XTALOUT
XTAL
=
L
CL CP
RS
CX1 CX2
002aaf424
Fig 29. Oscillator modes and models: oscillation mode of operation and external crystal model used for C
X1
/C
X2
evaluation
LPC11U1X
Product data sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Table 18.
Recommended values for C
X1
/C
X2
in oscillation mode (crystal and external components parameters) low frequency mode
Fundamental oscillation frequency F
OSC
1 MHz to 5 MHz
5 MHz to 10 MHz
10 MHz to 15 MHz
15 MHz to 20 MHz
Crystal load capacitance C
10 pF
20 pF
30 pF
10 pF
20 pF
30 pF
10 pF
20 pF
10 pF
L
Maximum crystal series resistance R
S
< 300
< 300
< 300
< 300
< 200
< 100
< 160
< 60
< 80
External load capacitors C
X1
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
, C
X2
Table 19.
Recommended values for C
X1
/C
X2
in oscillation mode (crystal and external components parameters) high frequency mode
Fundamental oscillation frequency F
OSC
15 MHz to 20 MHz
20 MHz to 25 MHz
Crystal load capacitance C
10 pF
20 pF
10 pF
20 pF
L
Maximum crystal series resistance R
S
< 180
< 100
< 160
< 80
External load capacitors C
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
39 pF, 39 pF
X1
, C
X2
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C x1
, C x2
, and C x3
in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C x1
and C x2
should be chosen smaller accordingly to the increase in parasitics of the PCB layout.
LPC11U1X
Product data sheet
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32-bit ARM Cortex-M0 microcontroller
11.4 Standard I/O pad configuration
shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Analog input
V
DD output enable ESD pin configured as digital output driver output PIN
ESD
V
SS pin configured as digital input repeater mode enable pull-up enable pull-down enable
V
DD weak pull-up weak pull-down data input pin configured as analog input analog input
Fig 30. Standard I/O pad configuration select analog input
002aaf304
LPC11U1X
Product data sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
11.5 Reset pad configuration
V
DD
V
DD
Rpu
V
DD
ESD
LPC11U1X
Product data sheet reset
20 ns RC
GLITCH FILTER
PIN
ESD
V
SS
002aaf274
Fig 31. Reset pad configuration
11.6 ADC effective input impedance
A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See
.
ADC Block
Source
ADC
COMPARATOR
Rmux
<2 k Ω
Rsw
<1.3 k Ω
Rs
Cia
Cio
Rin
VEXT
V
SS
002aah615
Fig 32. ADC input channel
The effective input impedance, R in
, seen by the external voltage source, V
EXT
, is the parallel impedance of ((1/f s
x C ia
) + R mux
+ R sw
) and (1/f s
x C io
), and can be calculated
f s
= sampling frequency
C ia
= ADC analog input capacitance
R mux
= analog mux resistance
R sw
= switch resistance
C io
= pin capacitance
R in
=
f s
1
C ia
+ R mux
+ R
sw
f
-----------------s
1
C io
(1)
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Under nominal operating condition V
DD
= 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values:
C ia
= 1 pF (max)
R mux
= 2 k Ω (max)
R sw
= 1.3 k Ω (max)
C io
= 7.1 pF (max)
The effective input impedance with these parameters is R in
= 308 k Ω.
11.7 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in
:
• The ADC input trace must be short and as close as possible to the LPC11U1x chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion.
LPC11U1X
Product data sheet
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12. Package outline
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
D B A terminal 1 index area
E A
A
1
LPC11U1x
32-bit ARM Cortex-M0 microcontroller c detail X
L
8
9 e
E h e
1 b
16 v w
C
C
A B
17 e e
2 y
1
C
C y terminal 1 index area
1
32
33
25
24
X
D h
0 2.5
scale
5 mm
Dimensions
Unit A
(1)
A
1 b c D
(1)
D h
E
(1)
E h e e
1 e
2
L mm max nom min
1.00
0.85
0.80
0.05
0.02
0.00
0.35
0.28
0.23
0.2
7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9
4.85
4.70
4.55
0.65
4.55
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
4.55
Outline version
IEC JEDEC
References
JEITA
0.75
0.60
0.45
v w y
0.1
0.05
0.08
y
1
0.1
European projection
- - -
Fig 33. Package outline HVQFN33 (7 x 7 x 0.85 mm)
LPC11U1X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.2 — 11 March 2014 hvqfn33_po
Issue date
09-03-17
09-03-23
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D B A terminal 1 index area
E
A
A1 c detail X
L
8
9 e e1
1/2 e b
16
17 e v w
C
C
A B y1 C
C y
Eh
1/2 e e2 terminal 1 index area
1
32 25
24
Dh
0 2.5
scale
Dimensions (mm are the original dimensions)
Unit
(1)
A
(1)
A
1 b c D
(1)
D h
E
(1)
E h e e
1 e
2 mm max nom min
0.85
0.05
0.30
0.2
5.1
3.75
5.1
3.75
0.5
3.5
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline version
0.00
0.18
IEC
4.9
3.45
4.9
JEDEC
3.45
References
JEITA
3.5
MO-220
L
0.5
0.3
v
5 mm w y y
1
0.1
0.05
0.05
0.1
European projection
Fig 34. Package outline HVQFN33 (5 x 5 x 0.85 mm)
X
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014 hvqfn33f_po
Issue date
11-10-11
11-10-17
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y
X
37
36 25
24 Z E
A
48 pin 1 index
13
1 e b p
D
H
D w M
12
ZD
B e w
M b p
E H
E v v
M
M
A
B
A
A
2
A
1 detail X
L
L p
θ
0 2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
A max.
A
1
A
2
A
3 b p c mm 1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
D
(1)
7.1
6.9
E
(1)
7.1
6.9
e
0.5
H
D
9.15
8.85
H
E
9.15
8.85
L
1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
L p
0.75
0.45
v
0.2
w y
0.12
0.1
Z
D
(1)
Z
E
(1)
0.95
0.55
0.95
0.55
θ
7 o
0 o
OUTLINE
VERSION
SOT313-2
IEC
136E05
REFERENCES
JEDEC JEITA
MS-026
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 35. Package outline LQFP48 (SOT313-2)
LPC11U1X
Product data sheet
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LPC11U1x
32-bit ARM Cortex-M0 microcontroller
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2
D B A ball A1 index area
E A
A
2
A
1 detail X e e
1
1/2 e b
Ø v
Ø w
C
C
A B ball A1 index area
F
E
H
G
B
A
D
C
1 2 3 4 5 6 7 8 e
1/2 e e
2 solder mask open area not for solder ball y
1
C
C y
X
0
Dimensions mm
Unit A A
1
A
2 max nom min
1.10
0.95
0.85
0.30
0.25
0.20
0.80
0.70
0.65
b
0.35
0.30
0.25
D
4.6
4.5
4.4
E
4.6
4.5
4.4
e
0.5
e
1 e
2 scale v w y y
1
3.5
3.5
0.15
0.05
0.08
0.1
5 mm
Outline version
SOT1155-2
IEC JEDEC
References
JEITA
- - -
Fig 36. Package outline TFBGA48 (SOT1155-2)
European projection
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014 sot1155-2_po
Issue date
13-06-17
13-06-19
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13. Soldering
Footprint information for reflow soldering of HVQFN33 package
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Hx
Gx see detail X
P nSPx
Hy Gy SLy By
Ay nSPy
C
SLx
Bx
Ax
D solder land solder paste occupied area detail X
0.60
0.30
Dimensions in mm
P Ax Ay
0.5
Issue date
5.95
5.95
11-11-15
11-11-20
Bx
4.25
By
4.25
C
0.85
D
0.27
Gx
5.25
Gy
5.25
Fig 37. Reflow soldering for the HVQFN33 (5x5) package
Hx
6.2
LPC11U1X
Product data sheet
Hy
6.2
SLx
3.75
SLy
3.75
nSPx nSPy
3 3
002aag766
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32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA evia = 4.25
0.20 SR chamfer (4×) e = 0.65
W = 0.30 CU
SPD = 1.00 SP
GapD = 0.70 SP evia = 2.40
SDhtot = 2.70 SP
4.55 SR
DHS = 4.85 CU
LbD = 5.80 CU
LaD = 7.95 CU
0.45 DM
B-side
Solder resist covered via
0.30 PH
0.60 SR cover
0.60 CU
(A-side fully covered) number of vias: 20 solder land solder paste deposit occupied area solder land plus solder paste solder resist
Dimensions in mm
Remark:
Stencil thickness: 0.125 mm
Fig 38. Reflow soldering for the HVQFN33 (7x7) package
001aao134
LPC11U1X
Product data sheet
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Footprint information for reflow soldering of LQFP48 package
P2 P1
Hx
Gx
(0.125)
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
SOT313-2
Hy Gy By Ay
C
D2 (8
×
) D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout solder land occupied area
DIMENSIONS in mm
P1 P2 Ax Ay Bx By
0.500
0.560
10.350
10.350
7.350
7.350
C
1.500
D1 D2 Gx Gy Hx Hy
0.280
0.500
7.500
7.500
10.650 10.650
Fig 39. Reflow soldering for the LQFP48 package
LPC11U1X
Product data sheet
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Footprint information for reflow soldering of TFBGA48 package
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
SOT1155-2
Hx
P
P
Hy see detail X solder land solder paste deposit solder land plus solder paste occupied area solder resist
DIMENSIONS in mm
P
0.50
SL SP SR
0.225
0.275
0.325
Hx
4.75
Hy
4.75
Fig 40. Reflow soldering for the TFBGA48 package
LPC11U1X
Product data sheet
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Rev. 2.2 — 11 March 2014
SL
SP
SR detail X sot1155-2_fr
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14. Abbreviations
Table 20.
Abbreviations
Acronym
A/D
Description
Analog-to-Digital
ADC
AHB
APB
BOD
Analog-to-Digital Converter
Advanced High-performance Bus
Advanced Peripheral Bus
BrownOut Detection
GPIO
JTAG
PLL
RC
SPI
SSI
SSP
TAP
USART
General Purpose Input/Output
Joint Test Action Group
Phase-Locked Loop
Resistor-Capacitor
Serial Peripheral Interface
Serial Synchronous Interface
Synchronous Serial Port
Test Access Port
Universal Synchronous Asynchronous Receiver/Transmitter
15. References
[1] LPC11U1x User manual UM10462: http://www.nxp.com/documents/user_manual/UM10462.pdf
[2] LPC11U1x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U1X.pdf
LPC11U1X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.2 — 11 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
67 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
16. Revision history
Table 21.
Revision history
Document ID
LPC11U1X v.2.2
Modifications:
LPC11U1X v.2.1
Modifications:
LPC11U1X v.2
Modifications:
LPC11U1X v.1
Release date Data sheet status Change notice Supersedes
20140311 Product data sheet LPC11U1X v.2.1
•
Updated
Section 11.1 “Suggested USB interface solutions” for clarity.
•
Open-drain I2C-bus and RESET pin descriptions updated for clarity. See
.
20130924 Product data sheet -
•
Number of CT16B0 match outputs corrected in Figure 1.
•
Table 3:
LPC11U1X v.2
– Added Table note 2 “5 V tolerant pad” to RESET/PIO0_0.
– Added Table note 4 “For parts with bootloader version 7.0...” .
•
Table 8: Removed BOD interrupt level 0.
•
Added Section 11.6 “ADC effective input impedance”.
•
Programmable glitch filter is enabled by default. See Section 7.6.1.
•
Table 6 “Static characteristics” added Pin capacitance section.
•
Updated Section 11.1 “Suggested USB interface solutions”.
•
Table 5 “Limiting values”:
– Updated V
DD
min and max.
– Updated V
I
conditions.
•
Changed title of Figure 28 from “USB interface on a self-powered device” to “USB interface with soft-connect”.
•
Section 10.7 “USB interface” added. Parameter t
EOPR1
and t
EOPR2 renamed to t
EOPR
.
20120111 Product data sheet LPC11U1X v.1
•
Number of physical and logical endpoints corrected in Section 7.8.1.
•
Use of JTAG updated in Section 2 (for BSDL only).
•
Sampling frequency corrected in Table note 7 of Table 7.
•
Conditions for parameter T stg
updated in Table 5.
•
Part LPC11U14FHI33/201 added.
•
Editorial updates.
•
ROM-based integer division routines added (Section 2).
•
Use of USB with power profiles specified (Section 7.8).
•
Power consumption data added in Section 9.2.
•
SSP dynamic characteristics added (Table 16).
•
IRC dynamic characteristics added (Table 12).
•
Data sheet status changed to Product data sheet.
•
Section 13 added.
•
Description of pin PIO0_3 updated in Table 3: this pin is not used by the boot loader.
20110411 Objective data sheet -
LPC11U1X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.2 — 11 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
68 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
17. Legal information
Document status
Objective [short] data sheet
Development
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com
.
17.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
LPC11U1X
Product data sheet
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2.2 — 11 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
69 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
I 2 C-bus — logo is a trademark of NXP Semiconductors N.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LPC11U1X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.2 — 11 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
70 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
19. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . 16
On-chip flash programming memory . . . . . . . 16
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nested Vectored Interrupt Controller (NVIC) . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USB interface . . . . . . . . . . . . . . . . . . . . . . . . 19
7.8.1 Full-speed USB device controller . . . . . . . . . . 19
7.8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.10 SSP serial I/O controller . . . . . . . . . . . . . . . . . 20
7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
C-bus serial I/O controller . . . . . . . . . . . . . . 20
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.12 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.14 System tick timer . . . . . . . . . . . . . . . . . . . . . . 22
7.15 Windowed WatchDog Timer (WWDT) . . . . . . 22
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.16 Clocking and power control . . . . . . . . . . . . . . 23
7.16.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 23
7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24
7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 25
7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 25
7.16.2 System PLL and USB PLL . . . . . . . . . . . . . . . 25
7.16.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.16.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 25
7.16.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.16.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 27
7.16.6 System control . . . . . . . . . . . . . . . . . . . . . . . . 27
7.16.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.16.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 27
7.16.6.3 Code security (Code Read Protection - CRP) 27
7.16.6.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.16.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Emulation and debugging . . . . . . . . . . . . . . . 29
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 30
Static characteristics . . . . . . . . . . . . . . . . . . . 31
BOD static characteristics . . . . . . . . . . . . . . . 37
Power consumption . . . . . . . . . . . . . . . . . . . 37
Peripheral power consumption . . . . . . . . . . . 40
Electrical pin characteristics. . . . . . . . . . . . . . 42
10 Dynamic characteristics. . . . . . . . . . . . . . . . . 45
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 45
External clock. . . . . . . . . . . . . . . . . . . . . . . . . 45
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 46
10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 49
USB interface . . . . . . . . . . . . . . . . . . . . . . . . 51
Application information . . . . . . . . . . . . . . . . . 52
Suggested USB interface solutions . . . . . . . . 52
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Standard I/O pad configuration . . . . . . . . . . . 56
Reset pad configuration . . . . . . . . . . . . . . . . . 57
ADC effective input impedance . . . . . . . . . . . 57
ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 58
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 59
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 67
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision history . . . . . . . . . . . . . . . . . . . . . . . 68
Legal information . . . . . . . . . . . . . . . . . . . . . . 69
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 69
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 70
continued >>
LPC11U1X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.2 — 11 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
71 of 72
NXP Semiconductors
Contact information. . . . . . . . . . . . . . . . . . . . . 70
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 March 2014
Document identifier: LPC11U1X
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