Analog Devices ADF4355 2 frequency synthesizer Application note
विज्ञापन
विज्ञापन
AN-1381
APPLICATION NOTE
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How to Bypass VCO Calibration for the
ADF4355-2
By Robert Brennan
VCO CALIBRATION
Bypass VCO Calibration for Faster Lock Times
For any given output frequency, the ADF4355-2 uses a certain voltage controlled oscillator (VCO) core, band, and bias code.
These three settings are selected automatically during the VCO automatic calibration (AUTOCAL). The settings are read from the ADF4355-2 and stored in a lookup table. Using this lookup table to bypass the AUTOCAL routine dramatically decreases the total lock time when changing the frequency. For example, lock times of less than 30 µs are possible with a 59.7 kHz loop
bandwidth. Figure 1 shows an example of a suitable loop filter.
R2
5.1kΩ
CP V
TUNE
C1
220pF
R1
2.4kΩ
C2
3.3nF
C3
100pF
7. Repeat Step 1 through Step 6 to build a lookup table for all desired frequencies. For Step 1, writing R10, R7, R2, R1, and R0 is only required after the first iteration. R2 and R1 are optional if they have not changed.
CORE AND BAND (R10 DB[28:26] = 1):
LE
CLK
MUXOUT
X X 1 0 0
CORE = A
0 1 0 0 0 1 1 0
BAND = 70
VALUE
001
010
011
100
CORE
B
A
D
C k
VCO
= 15MHz/V f
PFD
= 61.44MHz
I
CP
= 0.9mA
LBW = 59.7kHz
PM = 46.5°
Figure 1. Example Loop Filter with a 59.7 kHz Loop Bandwidth
Because each ADF4355-2 chip is unique, a new lookup table must be generated for every chip.
VCO Readback Procedure
The VCO readback procedure is as follows:
1. Load all registers to lock to the desired frequency. a. Ensure VCO read is set to VCO core and band
(R10, DB[28:26] = 0b001) (see Figure 5).
b. Ensure VCO readback is set to VCO calibration
complete (R7, DB[14:12] = 0b110) (see Figure 4).
c. Ensure MUXOUT is set to VCO readback
(R4, DB[29:27] = 0b111) (see Figure 3).
d. Ensure AUTOCAL is enabled (R0, DB21 = 0b1); see the ADF4355-2 data sheet for the R0 register map.
2. Wait until MUXOUT outputs a logic high (VCO calibration complete).
3. Load R7 with VCO readback set to VCO readback (R7,
DB[14:12] = 0b111).
4. Pulse SPI CLK while LE is kept high. The data outputs on
MUXOUT. Extract the data as shown in Figure 2.
5. Load R10 with VCO read set to VCO bias code (R10,
DB[28:26] = 0b011).
6. Repeat Step 4 for bias data.
BIAS CODE (R10 DB[28:26] = 3):
LE
CLK
MUXOUT
X X X X X X X X X 0 1 1 0
BIAS CODE = 6
NOTES
1. X = DON’T CARE.
2. MUXOUT MUST BE SET TO VCO READBACK (R4, DB[29:27] = 7).
3. VCO READBACK MUST BE SET TO VCO READBACK (R7, DB[14:12] = 7).
4. DATA IS CLOCKED OUT ON THE POSITIVE EDGE OF CLK AND READ ON
THE NEGATIVE EDGE OF CLK. READBACK STARTS ON THE FIRST CLK
EDGE AFTER LE GOES HIGH. LE MUST STAY HIGH DURING A READ.
Figure 2. VCO Readback
Bypass Automatic Calibration (AUTOCAL) to Manually
Select VCO and Lock
If the required VCO core, band, and bias code for a desired frequency is known (for example, in a lookup table), bypass the
VCO calibration routine and set the VCO data manually with the following steps:
1. Load R0 with AUTOCAL disabled (R0, DB21 = 0b0). This step is optional if AUTOCAL is already disabled.
2. Load R10 with VCO write set to VCO core and band (R10,
DB[31:29] = 0b001).
3. Load R11 with the desired VCO core, VCO band, and
VCO bias setting as defined in Figure 6. Note that the VCO
core bits are different for read and write.
4. Load R10 with VCO write set to VCO bias code (R10,
DB[31:29] = 0b011).
5. Reload R11 with the same value as in Step 3.
6. Lock to the desired frequency by programming R2, R1, and
R0, respectively.
Rev. 0 | Page 1 of 4
AN-1381
Expanded
ADF4355-2
Register Maps
Application Note
RESERVED MUXOUT 10-BIT R COUNTER DBR 1
CURRENT
SETTING DBR 1
PD PO
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
CONTROL
BITS
DB2 DB1
0 0 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2
DB0
U1 C4(0) C3(1) C2(0) C1(0)
RD2
0
1
REFERENCE
DOUBLER
DISABLED
ENABLED
D1
0
1
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
DISABLED
ENABLED
R10
1
1
.
1
1
.
.
0
0
RD1 REFERENCE DIVIDE BY 2
0 DISABLED
1 ENABLED
R9
1
1
.
1
1
.
.
0
0
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
1
0
1
0
1
0
1
M1
0
OUTPUT
THREE-STATE OUTPUT
DVDD
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
VCO READBACK
R1
1
0
.
0
1
.
.
1
0
R2
0
1
0
.
1
.
.
0
1
R DIVIDER (R)
.
.
1
2
.
1020
1021
1022
1023
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
CP4
0
0
1
0
0
1
1
1
1
1
1
0
0
1
0
0
CP3
0
1
0
0
1
0
1
1
0
1
1
0
1
0
0
1
CP2
0
0
1
0
0
1
1
1
M3
0
1
0
0
1
0
1
1
M2
0
1 DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 3. Register 4
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
CP1
0
3.0
3.3
3.6
3.9
4.2
4.5
4.8
0.9
1.2
1.5
1.8
ICP (mA)
5.1kΩ
0.3
0.6
2.1
2.4
2.7
U6
0
1
U4
0
1
U5
0
1
REFIN
SINGLE
DIFF
LDP
1.8V
3.3V
PD POLARITY
NEGATIVE
POSITIVE
U3
0
1
U2
0
1
U1
0
1
COUNTER
RESET
DISABLED
ENABLED
CP
THREE-STATE
DISABLED
ENABLED
POWER DOWN
DISABLED
ENABLED
RESERVED RESERVED VCO READBACK
LD
CYCLE
COUNT CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 0 0 LE 0 0 0 0 0 0 0 0 0 0 VR3 VR2 VR1 0 0 LD5 LD4 LOL LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)
LE
0
1
LE SYNCHRONIZATION
DISABLED
LE SYNCED TO REFIN
VR3 VR2 VR1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
VCO READBACK
NORMAL OPERATION
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VCO CALIBRATION COMPLETE
VCO READBACK
LD1
0
1
LOCK DETECT MODE
FRACTIONAL-N
INTEGER-N (2.9ns)
LD3 LD2
1
1
0
0
0
1
0
1
FRACTIONAL-N
LD PRECISION
5.0ns
6.0ns
8.0ns
12.0ns
LOL
0
1
LOSS OF LOCK MODE
DISABLED
ENABLED
0
1
LD5
0
1
1
0
LD4
0
1
LOCK DETECT CYCLE COUNT
1024
2048
4096
8192
Figure 4. Register 7
Rev. 0 | Page 2 of 4
Application Note AN-1381
VCO WRITE VCO READ RESERVED
ADC
CLOCK DIVIDER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VW3 VW2 VW1 VR3 VR2 VR1 0 0 1 1 0 0 0 0 0 0 0 0 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AE1 ADC
0
1
DISABLED
ENABLED
VR3 VR2
0
0
1
0
0
1
1
1
1
1
0
0
0
0
1
1
VR1
0
1
0
0
1
1
0
1
VCO READ
NORMAL OPERATION
VCO CORE AND BAND
RESERVED
VCO BIAS CODE
RESERVED
RESERVED
RESERVED
RESERVED
VW3 VW2 VW1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
VCO WRITE
NORMAL OPERATION
VCO CORE AND BAND
RESERVED
VCO BIAS CODE
RESERVED
RESERVED
RESERVED
RESERVED
Figure 5. Register 10
AD8
.
1
1
.
.
0
0
1
1
AD7
.
1
1
.
.
0
0
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
AD2 AD1 ADC CLK DIV
.
0
0
.
.
0
1
1
1
1
0
.
.
.
0
1
0
1
.
.
.
1
2
252
253
254
255
AE2
0
1
ADC CONVERSION
DISABLED
ENABLED
RESERVED VCO CORE VCO BIAS VCO BAND
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 1 1 0 C4 C3 C2 C1 B4 B3 B2 B1 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA C4(1) C3(0) C2(1) C1(0)
C4 C3 C2 C1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
VCO CORE
RESERVED
CORE D/NORMAL OPERATION
CORE C
CORE B
CORE A
B4 B3 B2 B1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
VCO BIAS
6
7
8
0
1
4
5
2
3/NORMAL OPERATION
Figure 6. Register 11
BA8 BA7
.
.
.
0
0
1
1
1
1
.
.
.
0
0
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
BA2 BA1
.
.
.
0
0
0
0
1
1
.
.
.
0
0
0
1
0
1
VCO BAND
0/NORMAL OPERATION
1
.
.
.
252
253
254
255
Rev. 0 | Page 3 of 4
AN-1381
Read Timing Characteristics
Application Note t
1 t
2 t
3 t
4 t
5
Table 1. Read Timing
Parameter Limit Description
15 ns min LE high to CLK high
15
25
25
10 ns min ns min ns min ns min
CLK high to DATA ready
CLK high duration
CLK low duration
CLK high to LE low (next write)
Read Timing Diagram
t
1 t
3 t
4
CLK t
2
DB2 DB1
MUXOUT X DB11 DB0 t
5
LE
NOTES
1. LE MUST BE KEPT HIGH DURING READBACK.
2. X = DON’T CARE.
Figure 7. Read Timing Diagram
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN13647-0-11/15(0)
Rev. 0 | Page 4 of 4
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