Epson S1C33 Specifications

MF1359-02

CMOS 32-BIT SINGLE CHIP MICROCOMPUTER

S1C33

ASIC DESIGN GUIDE

Embedded Array S1X50000 Series

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

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All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners.

2001 All rights reserved.

The information of the product number change

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales representative.

Configuration of product number

Devices

S1 C 33104 F 0A01 00

Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C 33L01 D1 1 00

Packing specification

Version (1: Version 1

∗

2 )

Tool type (D1: Development Tool

∗

1 )

Corresponding model number (33L01: for S1C33L01)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗

1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗

2: Actual versions are not written in the manuals.

Comparison table between new and previous number

Comparison table between new and previous number of development tools

S1C33 Family processors

Previous No.

E0C33A104

E0C33202

E0C33204

E0C33208

E0C33209

E0C332T01

New No.

S1C33104

S1C33202

S1C33204

S1C33208

S1C33209

S1C33T01

E0C332L01

E0C332L02

E0C332S08

E0C332129

E0C33264

E0C332F128

S1C33L01

S1C33L02

S1C33S01

S1C33221

S1C33222

S1C33240

Previous No.

CC33

CF33

COSIM33

GRAPHIC33

HMM33

JPEG33

MON33

MELODY33

PEN33

ROS33

SOUND33

SMT33

TS33

USB33

VOX33

VRE33

New No.

S5U1C33000C

S5U1C330C1S

S5U1C330C2S

S5U1C330G1S

S5U1C330H1S

S5U1C330J1S

S5U1C330M2S

S5U1C330M1S

S5U1C330P1S

S5U1C330R1S

S5U1C330S1S

S5U1C330S2S

S5U1C330T1S

S5U1C330U1S

S5U1C330V1S

S5U1C330V2S

Development tools for the S1C33 Family

Previous No.

New No.

Previous No.

ICE33

EM33-4M

PRC33001

POD33001

ICD33

DMT33004

DMT33004PD

DMT33005

DMT33005PD

DMT33006LV

DMT33006PDLV

DMT33007

DMT33007PD

DMT33008LV

DMT33008PDLV

DMT332S08LV

DMT332S08PDLV

DMT33209LV

DMT33209PDLV

DMT332F128LV

DMT33MON

DMT33MONLV

DMT33AMP

DMT33AMP2

DMT33AMP3

DMT33AMP4

DMT33CF

DMT33CPLD400KLV

S5U1C33104H

S5U1C33104E

S5U1C33104P1

S5U1C33104P2

S5U1C33000H

S5U1C33104D1

S5U1C33104D2

S5U1C33208D1

S5U1C33208D2

S5U1C33L01D1

S5U1C33L01D2

S5U1C33208D3

S5U1C33208D4

S5U1C33T01D1

S5U1C33T01D2

S5U1C33S01D1

S5U1C33S01D2

S5U1C33209D1

S5U1C33209D2

S5U1C33240D1

S5U1C330M1D1

S5U1C330M2D1

S5U1C330A1D1

S5U1C330A2D1

S5U1C330A3D1

S5U1C330A4D1

S5U1C330C1D1

S5U1C330C2D1

DMT33LIF

DMT33SMT

DMT33LCD26

DMT33LCD37

EPOD33001

EPOD33001LV

EPOD33208

EPOD33208LV

EPOD332L01LV

EPOD332T01

EPOD332T01LV

EPOD33209

EPOD33209LV

EPOD332128

EPOD332128LV

EPOD332S08LV

MEM33201

MEM33201LV

MEM33202

MEM33202LV

MEM33203

MEM33203LV

MEM33DIP42

MEM33TSOP48

EPOD176CABLE

EPOD100CABLE

EPOD33SRAM5V

EPOD33SRAM3V

New No.

S5U1C330L1D1

S5U1C330S1D1

S5U1C330L2D1

S5U1C330L3D1

S5U1C33208E1

S5U1C33208E2

S5U1C33208E3

S5U1C33208E4

S5U1C33L01E1

S5U1C33T01E1

S5U1C33T01E2

S5U1C33209E1

S5U1C33209E2

S5U1C33220E1

S5U1C33220E2

S5U1C33S01E1

S5U1C33001M1

S5U1C33001M2

S5U1C33002M1

S5U1C33002M2

S5U1C33003M1

S5U1C33003M2

S5U1C330D1M1

S5U1C330T1M1

S5U1C33T00E31

S5U1C33S00E31

S5U1C33000S

S5U1C33001S

Contents

Contents

Chapter 1 Product Overview ................................................................ 1

1.1

Introduction ........................................................................... 1

1.2

Interface and Design Process Flowchart .............................. 3

Chapter 2 C33 Macro Specifications .................................................... 7

2.1

Overview ............................................................................... 7

2.2

Block Diagram ...................................................................... 8

2.3

C33 Macro Pins .................................................................. 10

2.4

Special Signals ................................................................... 15

2.5

Clock and Reset Signals .................................................... 15

2.6

Electrical Characteristics .................................................... 17

2.6.1 Absolute Maximum Ratings .................................................. 17

2.6.2 Recommended Operating Conditions ..................................... 18

2.6.3 DC Characteristics .............................................................. 20

2.6.4 Current Consumption ........................................................... 21

2.6.5 A/D Converter Characteristics ............................................... 22

2.6.6 AC Characteristics .............................................................. 24

2.6.6.1

Symbol Description ...................................................... 25

2.6.6.2

AC Characteristics Measurement Condition ...................... 26

2.6.6.3

AC Characteristics Tables (I/O Buffer Pins) ....................... 27

2.6.6.4

AC Characteristics Timing Charts (I/O Buffer Pins)

2.6.6.5

AC Characteristics Tables (User Logic Interface)

............. 37

............... 43

2.6.6.6

AC Characteristics Timing Charts (User Logic Interface) ...... 45

2.6.6.7

Oscillation Characteristics

2.6.6.8

PLL Characteristics

............................................. 49

...................................................... 51

Chapter 3 C33 Test Functions ........................................................... 52

3.1

Test Function Overview ...................................................... 52

3.2

DC/AC Test Mode (TST_DCT Mode) ................................. 53

3.2.1 Procedure to Enter Test Mode

3.2.2 Test Mode

.............................................. 53

........................................................................ 54

3.3

User Circuit Test Mode (TST_USER Mode) ...................... 59

3.3.1 Procedure to Enter Test Mode

3.3.2 Test Mode

.............................................. 59

........................................................................ 60

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY S1X50000 SERIES

EPSON i

Contents

Chapter 4 Special Operations in ASICs that Include C33 Macros ...... 62

4.1

Special Operations ............................................................. 62

4.2

Verifying the C33 Macro Specifications .............................. 62

4.3

Verifying the Constraints on the Pin Arrangement ............. 63

4.3.1 Constraints on PLL, Low-speed, and High-speed Oscillator Circuit

Pins ................................................................................. 63

4.3.2 Constraints on A/D Converter Pins ......................................... 63

4.3.3 Number of Power Supply Pins ............................................... 63

4.3.4 Floorplan .......................................................................... 63

4.4

Connections between User I/O, User Circuits, and C33

Macros ................................................................................ 65

4.4.1 Connections between C33 Macros and User Circuits

4.4.2 Connections between C33 Macros and User I/O

................. 65

....................... 65

4.4.3 Notes on the Use of 5 V Tolerant I/O Cells ............................... 65

4.4.4 Connections between C33 Macros and User I/O ....................... 66

4.5

Test Pattern Creation ......................................................... 67

4.5.1 DC/AC Test Pattern Creation ................................................ 67

4.5.2 C33 Macro/User Circuit Connection Verification Test Pattern

Creation ........................................................................... 67

Chapter 5 Simulation .......................................................................... 68

5.1

Design Flowchart .............................................................................

68

5.2

System Level Simulation .................................................... 70

5.3

Test Pattern Creation ......................................................... 70

5.4

Simulation Environment ...................................................... 71

5.4.1 Operating Environment ........................................................ 71

5.4.2 Installation Procedure .......................................................... 71

5.5

Running a Simulation ......................................................... 72

5.5.1 Preparing for Simulation ...................................................... 72

5.5.2 Sample Simulation Execution ............................................... 72

5.5.3 Simulation Execution Script

5.5.4 Test Bench Structure

.................................................. 73

.......................................................... 74

5.6

Evaluation Program Creation ............................................. 76

5.6.1 asm33 Assembler Prototype ................................................. 76

Chapter 6 Board Development ........................................................... 79

6.1

Development Environment ................................................. 79

6.2

Evaluation Board Design .................................................... 82 ii

Chapter 7 Mounting ............................................................................ 85

7.1

Precautions on Mounting .................................................... 85

7.2

Others ................................................................................. 89

EPSON S1C33 ASIC DESIGN GUIDE


1 Product Overview

Chapter 1 Product Overview

1.1 Introduction

This product, abbreviated here as "C33," is an ASIC macro family that consists of Seiko Epson's independently developed S1C33000 Series 32-bit CPU core and macros for a wide range of peripheral functions. The C33 macros can be integrated on Seiko Epson's 0.35 µm embedded ASIC family

(S1X50000 Series) ICs. SRAM, ROM, and flash memory ASIC memory macros that share the same process technology can be integrated on the same chip. Thus Seiko Epson provides a complete ASIC microcontroller design environment, and makes ASIC products (S1C33ASIC) that include C33 macros available to our customers.

The C33 CPU features a RISC architecture. Despite the small size of this CPU core, it provides an extremely powerful instruction set that allows compilers to generate compact code. The C33 macros provide the following features.

• High speed and high performance:

• Powerful instruction set:

• Instruction execution cycle:

• Multiply and accumulate operation:

• Registers:

• Address space:

• External bus interface:

• Interrupts:

• Reset:

• Low-power modes:

• Harvard architecture:

• User interface:

Operation from DC to 60 MHz. ASICs with on chip

ROM can operate at up to 50 MHz, and ASICs without

ROM can operate at up to 60 MHz.

16-bit fixed length, 105 basic instructions.

Most instructions are executed in a single cycle.

16 bits

×

16 bits + 64 bits. Multiply and accumulate operations are executed in 2 clock cycles, thus achieving 25 MOPS at 50 MHz.

Sixteen 32-bit general-purpose registers and five 32-bit special registers.

256 MB linear address space (28-bit addresses) shared by code, data, and I/O registers.

15 configurable memory areas

Direct connection to external memory.

Reset, NMI, up to 128 external interrupts, 4 software interrupts, and two instruction execution exceptions

Cold reset, hot reset, and boot from area 10.

Sleep mode and halt mode.

Instruction fetch and data load/store operations are executed in parallel.

Allows software controlled insertion of wait cycles

(up to 7 cycles).

Supports #WAIT pin handshake control.

Large memory space for user logic (up to 16M bytes)

BCU registers allow internal software access to areas 4 through 18.

Large numbers of interrupt request signals from the user logic may be connected to the interrupt controller.



EPSON 1

1 Product Overview

• Other features: Little endian (Certain areas can be set up for big endian operation.)

*: In addition to this documents, you will also find the following documents of use when

designing ASICs.

• S1L50000 SERIES ASIC DESIGN GUIDE

• S1L50000 SERIES MSI Cell Library (I/O)

• S1X50000 SERIES MSI Cell Library (Internal cells)

• S1C332XX Series Technical Manual

• S1C33 Family ASIC Macro Manual

• EVALUATION BOARD MANUAL

2 EPSON S1C33 ASIC DESIGN GUIDE


1.2

Interface and Design Process Flowchart

1 Product Overview

Determination of the specifications for the S1C33 ASIC product

IC design

Bulk design

Software development

OS development

Application development

EPOD development

(*)

Evaluation board development

Target board development

User circuit development

FPGA circuit development

Metal design ROM data issued Functional verification in an actual end product

(*)EPOD: ROM emulation board

ES samples

Customer verification

Start of mass production

Figure 1.1 Total Product Development Process Flowchart



EPSON 3

1 Product Overview

Table 1.1 Work Involved in Each Step of S1C33ASIC Development

Development step

Specifications verification

Development environment preparation

User logic design

Combined simulation

Design rule check

Bulk signoff

Pre-simulation

Test design

P&R

Post-simulation

ROM code handling

Work involved

• Selection of C33 macros and modules used

• Fixing the specifications of the user logic

• Verifying the package and pin assignment specifications

• Verifying the test design specifications

• Verifying the EPOD specifications

• Design kit start-up (S1X50000 Series and C33 design kit)

• Schematic capture, functional notation, logic synthesis

• User logic simulation

• Chip level net list creation

• Chip level simulation program creation (C33 assembler code)

• Chip level simulation

• SNRC(*)

• Floorplan creation (macro layout, pin assignment)

Finalizing the bulk size

• Pre-simulation

• ATPG (user logic block)

• Automatic placement and routing, CTS insertion

• Back annotation SDF creation

• Post-simulation

• Finalizing the internal ROM code

• ROM code data conversion

Metal signoff

Test production flow

Sample shipment, evaluation, switchover to mass production

(*) SNRC: Net list rule checker



1 Product Overview

Figure 1.2 Division of Responsibility in the Development Process

(Development Flowchart Organized by Responsibility)

Continued on following page.



EPSON 5

1 Product Overview



2 C33 Macro Specifications

Chapter 2 C33 Macro Specifications

2.1

Overview

The C33 macro model has the structure described below. Seiko Epson provides a combination of these elements as specified by user options.

! C33_CORE

• C33 core macros

• CPU, BCU (bus control unit), ITC (Interrupt controller), DBG (debugging unit), and highspeed oscillator circuit (including PLL circuit) macros

• About 60,000 gates

• Hard macro

! C33_PERI

• C33 digital peripheral function macros

• 4-channel 8-bit timer, 6-channel 16-bit timer, prescaler, 2-channel serial interface, watchdog timer, clock timer, low-speed oscillator circuit (32 kHz), and I/O port macros


• Soft macros

! C33_AD

• C33 analog peripheral function macros

• 8-channel input and 10-bit successive-approximation converters

• Conversion time: 10 µs


• Hard macros

! C33_DMA

• C33 DMA function macros

• 4-channel high-speed DMA and 128-channel intelligent DMA macros


• Hard macros

(*)

• Soft macro: Net list or RTL macro for which the layout is not fixed.

• Hard macro: Net list macro for which the layout is fixed.



EPSON 7


2.2

Block Diagram

DMA

Internal RAM

(area 0)

Internal ROM

(area 10)

(4) User pins

User logic interface

User logic

C33_CORE

PAD_

CORE

(CPU,BCU,ITC,CLG,DBG)

SBUS

PAD_

CORE_

OPTION

C33 CORE BLOCK

(1) Required pins

(2) Optional pins

C33_PERI

(PSC,T8,T16,SIO,PORT)

PAD_

PERI

(3) Peripheral

function pins

8

Terminology

BCU:

ITC:

CLG:

DBG:

C33_CORE:

PAD_CORE:

ADC

Figure 2.1 C33 Macro Block Diagram

Bus control unit

Interrupt controller

Clock generator (oscillator circuit, PLL, and clock divider circuits built in)

Debugging function block (On-chip ICE)

Functional blocks such as CPU, BCU, ITC, CLG, and DBG blocks

I/O pad block for C33_CORE blocks




SBUS:

C33_PERI:

Bus control block that has an address/data bus structure connected to the user logic.

C33 peripheral function blocks. These blocks include prescaler, 8-bit timer

(4 channels), 16-bit timer (6 channels), serial interface (2 channels), port

(input, output, and I/O), and clock timer blocks.

PSC:

T8:

SIO:

PAD_PERI:

Prescaler

8-bit timer

Serial interface

I/O pads for the C33_PERI blocks

Internal ROM (area 10):Basically, area 10 is for user use as an on-chip mask ROM.

[16-bit data bus] ASIC ROM is placed in this area.

(0 to 2 MB)

Internal RAM (area 0): Area 0 is used for on-chip data SRAM. This is high-speed access SRAM

[8-bit data bus] that requires no wait cycle.

(0 to 128 KB)

[Byte write

×

32 bits]

ASIC RAM is allocated to this area.

ADC: A/D converter



EPSON 9


2.3

C33 Macro Pins

(1) C33 Macro - Required pins (pad connections)

(2) C33 Macro - Optional pins (pad connections)

(3) C33 Macro - Peripheral function pins (pad connections)

(4) C33 Macro - User pins (chip internal connections)

(1) C33 Macro - Required pins (pad connections) (57 pins)

These required pins must be connected to IC package pins.

Table 2.3.1 Required Pins

Connection: PAD_CORE

Name I/O

Cell name

(****)

Pull-u/d Function

P_A23 to P_A0

P_D15 to P_D0

P_CE10EX

P_RD_X

P_WRL_X

P_WRH_X

P_BCLK

P_NMI_X

P_RESETX

I/O(*) XHBC1T

I/O XHBC1T

I/O(*) XHBC1T

I/O(*) XHBC1T

I/O(*) XHBC1T

I/O(*) XHBC1T

O XHTB1T

I

I XHIBHP2

XHIBHP2

Pull-up

Pull-up

24-bit address bus. A0 is shared with the #BSL pin function.

16-bit data bus

Area 10 chip enable/test clock

Read strobe

Lower byte write strobe

Upper byte write strobe

Bus clock

Nonmaskable interrupt

Reset signal

P_X2SPDX

P_TST

P_EA10M1

P_EA10M0

P_DSIO

P_OSC4

I

I

I

I

XHIBC

XITST1

XHIBHP2

XHIBC

Double-speed mode (The CPU clock operates at a frequency twice that of the bus clock.)

Pull-down Test mode

Pull-up

I/O XLBH2P2T Pull-up

O XLLOT

Area 10 boot mode specification bit 1 (**)

Area 10 boot mode specification bit 0 (**)

On-chip ICE serial I/O

High-speed oscillator output

P_OSC3 I XLLIN

High-speed oscillator input (oscillator element connection)

PLL mode specification bit 1 (***) P_PLLS1

P_PLLS0

P_PLLC

I

I

O

XHIBC

XHIBC

XLLIN

PLL mode specification bit 0 (***)

PLL capacitor connection

(*) Functions as an input in test mode.

(**) Refer to table 2.3.3 for the setting values.

(***) P_PLLS[1:0] pin settings

00: PLL unused. (The OSC3 input is used as the system clock.)

01: 4

×

mode. fin = 10 to 15 MHz, fout = 40 to 60 MHz

11: 2

×

mode. fin = 10 to 30 MHz, fout = 20 to 60 MHz

(****) The type can be modified as specified by the customer.

Refer to the "S1L50000 SERIES MSI Cell Library" manual for more information on the cell type.




(2) C33 Macro - Optional pins (pad connections) (12 pins)

Name

P_LCAS_X

P_HCAS_X

P_CE10IN

P_CE9_X

P_CE8_X

P_CE7_X

I/O

O

O

O

I/O

I/O

I/O

Cell name

XHTB1T

XHTB1T

XHTB1T

XHBC1T

XHBC1T

XHBC1T

Table 2.3.2 Optional Pins

Pull-u/d

Connection: PAD_CORE_OPTION

Function

DRAM lower byte CAS signal

DRAM upper byte CAS signal

Internal ROM emulation area (area 10) chip enable

Chip enable (area 9 or area 17)

Chip enable (area 8 or area 14) or the area 8 and 14

DRAM strobe

Chip enable (area 7 or area 13) or the area 7 and 13

DRAM strobe

P_CE6_X

P_CE5_X

P_CE4_X

P_CE3_X

I/O

I/O

I/O

O

XHBC1T

XHBC1T

XHBC1T

XHTB1T

Chip enable (area 6)



Chip enable (area 3)

P_EMEMRD

P_EA10M2

(*)

O

I

XHTB1T

XHIBC

Internal ROM emulation area (area 10) read strobe

Area 10 boot mode specification bit 2

Pins P_CE4_X to P_CE9_X function as output pins due to test circuit modifications.

The customer can select whether or not each of the above optional pins is connected to a pad. If the pin is not connected to a pad, it can be used as an internal signal with the same meaning. In that case, the fan-in and fan-out values are equivalent to those for XBF2 from the S1X50000 library.

Table 2.3.3 P_EA10M2, P_EA10M1, and P_EA10M0 Settings

(Area 10 Boot Mode) Function

P_EA10M2 P_EA10M1 P_EA10M0

0 0 0

0

1

0

0

0

1

1

0

1

0

1

0

1

1

1

0

1

1

1

0

1

Function

Internal ROM emulation

Reserved

Internal ROM

External ROM

Reserved

Reserved

Reserved

Internal flash ROM



EPSON 11


(3) C33 Macro - Peripheral function pins (pad connections) (44 pins)

Table 2.3.4 Peripheral Function Pins

Connection: PAD_PERI

Name I/O Cell name Pull-u/d

P_K67

P_K66 I

I XHIBCLIN**

XHIBCLIN**

Function

Input port. When /CFK67(D7/0x402C3) = 0 (default)


P_K65

P_K64

P_K63

P_K62

P_K61

P_K60

I

I

I

I

I

I

XHIBCLIN**

XHIBCLIN**

XHIBCLIN**

XHIBCLIN**

XHIBCLIN**

XHIBCLIN**







P_K54

P_K53

P_K52

P_K51

P_k50

P_P35

P_P34

P_P33

P_P32

P_P31

P_P30

I

I

I XHIBHP2

XHIBHP2

I XHIBHP2

I XHIBHP2

XHIBHP2

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

P_P27

P_P26

P_P25

P_P24

P_P23

P_P22

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

P_P21 I/O XHBH1T

P_P20 I/O XHBH1T

P_P16 I/O XHBH1T

P_P15 * I/O XHBH1T

P_P14 * I/O XLBH2T

P_P13 * I/O XLBH2T

P_P12 * I/O XLBH2T

P_P11 * I/O XLBH2T

P_P10 * I/O XLBH2T

Pull-up Input port. When /CFK54(D4/0x402C0) = 0 (default)





I/O shared function port. When /CFP35(D5/0x402DC) = 0 (default)






I/O shared function port. When /CFP27(D7/0x402D8) = 0 (default)






I/O shared function port. When /CFP21(D1/0x402D8) and

CFEx2(D2/0x40LDF) = 0 (default)





CFEx0(D0/0x402DF) = 0 (default)












Connection: PAD_PERI

Name I/O Cell name Pull-u/d

P_P07

P_P06

P_P05

P_P04

P_P03

P_P02

P_P01

P_P00

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

I/O XHBH1T

Function








CFEx4(D4/0x402LDF) = 0 (default)





P_OSC2

P_OSC1

O

I

XLLOT

XLLIN

Low-speed oscillator (OSC1) output

Low-speed oscillator (OSC1) input (32 kHz oscillator element connection or external clock input)

(*) Pins P_P10 to P_P14 are used as S5U1C33000H interface pins.

(**) Analog input and digital input shared function input buffer

The customer can select whether or not each of the above optional pins is connected to a pad. If the pin is not connected to a pad, it can be used as an internal signal with the same meaning. In that case, the fan-in and fan-out values are equivalent to those for XBF2 from the S1X50000 Series library.

(4) C33 Macro - User logic interface pins (chip internal connections)

When the corresponding area is in on-chip mode due to BCU register settings, the following signals and bus lines will be active when the bus is operational.

The C33 memory area is divided into 19 areas (area 0 through area 18). Basically, areas 4 to 18 are external (off-chip) memory areas, and areas 0 to 3 are internal (on-chip) memory areas. The operating conditions for these areas, such as type of memory used (SRAM, ROM, RAM, DRAM), device size

(8-bit or 16-bit data width), and timing (wait cycles and output disable cycles) are set using the BCU registers. Additionally, it is also possible, using other BCU registers, to set up specific areas in areas

4 to 18 as external areas on the external bus and to have the other areas function as internal areas on the internal bus as described later in this section.

Even in cases where specific areas as set up as on-chip (i.e. on the internal bus) areas, the operating conditions for those areas, such as type of memory used (SRAM, ROM, RAM, DRAM), device size

(8-bit or 16-bit data width), and timing (wait cycles and output disable cycles), can be set in the same way with the BCU registers.



EPSON 13


U_WAIT_X

U_P3_PIN[5:0]

U_P2_PIN[7:0]

U_P1_PIN[6:0]

U_P0_PIN[7:0]

U_K5_PIN[4:0]

U_BUSMD[2:0]

U_BUSSZ[1:0]

U_BCLK

U_OSC1CLK

U_OSC3CLK

U_PLLCLK

U_BCUCLK

U_PERICLK

U_RST_X

TST_USER

TST_TA

TST_TE_X

TST_TS

Pin

U_ADDR[23:0]

U_DOUT[15:0]

U_DIN[15:0]

U_CE10_X

U_CE9_X

U_CE8_X

U_CE7_X

U_CE6_X

U_CE5_X

U_CE4_X

U_WRL_X

U_WRH_X

U_RD_X

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

I

O

O

O

O

O

O

O

O

O

I/O

O

O

O

O

I

XBF4

XBF4

XBF4

XBF4

XBF4

XBF4

XBF4

XBF4

Table 2.3.5 User Logic Interface Pins

Cell name (fanout)

XBF4

XBF4

XAO22V

XBF4

XBF4

Address bus

Output data bus

Input data bus

User logic chip enable




Connection: User logic

Function




Lower byte write strobe

Upper byte write strobe

Read strobe

Wait signal

P3 port input value (Separated test input)

XAO22V

XBF2

XBF2

XBF2

XBF2

XBF2

XBF2

XBF2




K5 port input value (Separated test input)

Bus cycle status signal

Bus size signal

Bus clock

Low-speed oscillator circuit output

XBF4

XBF4

XBF4

XBF4

XCRBF6

XCRBF6

XBF4

XBF2

XBF16

XBF16

XBF16

High-speed oscillator circuit output

PLL circuit output

BCU clock (CTS support)

Peripheral circuit clock (CTS support)

Reset signal

User circuit test mode

I/O cell TA pin connection signal

I/O cell TE pin connection signal

I/O cell TS pin connection signal




2.4

Special Signals

The U_BUSSZ[1:0] and U_BUSMD[2:0] signals indicate the state of the bus cycle currently executing on the chip external bus and the internal bus (the internal bus including the on-chip user logic). First, when U_BUSSZ[1:0] is 11, the bus is in the idle state, and the U_BUSMD[2:0] signals have no meaning. This indicates that the neither the CPU nor the DMA controller is executing a meaningful bus cycle. When U_BUSSZ[1:0] is not 11, U_BUSSZ[1:0] itself indicates the bus operation data cycle at that point and U_BUSMD[2:0] indicates the bus state.

U_BUSMD[2:0]

U_BUSSZ [1:0]

Table 2.4 Bus Cycle States

000

001

010

011

100

101

110

111

00

01

10

11

CPU instruction fetch cycle

CPU vector fetch cycle

CPU data read cycle

CPU data write cycle

CPU stack read cycle

CPU stack write cycle

DMA data read cycle

DMA data write cycle

Byte (8 bits)

Half word (16 bits)

Word (32 bits)

Idle state

2.5

Clock and Reset Signals

There are 6 clock signals that can be connected to the user logic as follows.

U_PLLCLK, U_OSC1CLK, U_OSC3CLK, U_BCLK, U_BCUCLK, U_PERICLK

Figure 2.2 presents an overview of the clock and reset signals. U_OSC3CLK is the output from the high-speed oscillator circuit (OSC3), and U_PLLCLK is the output from the PLL circuit. This means that the frequency of the U_PLLCLK signal is determined by the inputs to pin P_PLLS1 and

P_PLLS0. For example, if the OSC3 oscillator frequency is 20 MHz, P_PLLS1 is 1, and P_PLLS0 is

0, then these clocks will have the following frequencies.

U_PLLCLK=40MHz,

U_OSC3CLK=20MHz

Note that the phases of these clocks do not match the phases of the CPU and BCU internal clocks due to clock tree synthesis. Since both U_OSC3CLK and U_PLLCLK are generated from the OSC3 clock, they will stop when the CPU executes a SLP instruction until sleep mode is cleared. Furthermore, when the OSC3 oscillator starts operating again due to the factor that cleared sleep mode, the

U_OSC3CLK and U_PLLCLK signals will be unstable for a certain period, normally about 10 ms.

U_OSC1CLK is the output from the low-speed oscillator circuit.

U_BCUCLK and U_PERICLK are clocks to which the same clock tree synthesis applied as that for the clocks used by the C33 core.

U_BCLK is the bus clock output from the BCU. Refer to the description of the bus clocks in the

"S1C33 Family ASIC Macro Manual" for more information on the bus clocks.



EPSON 15


The U_RST_X signal outputs the value of the P_RESETX pad pin shown in the figure.

P_OSC1

P_OSC3

C33 MACRO

PLL

OSC1

OSC3

U_PLLCLK

U_OSC1CLK

U_OSC3CLK

CLG

CLOCK TREE CPU

PERIPHERAL

CLOCK TREE U_PERICLK

CLOCK TREE U_BCUCLK

P_X2SPD

P_RESETX

BCU U_BCLK

U_RST_X

Figure 2.2 On-Chip User Circuit Clock and Reset Signals

U_PERICLK

U_BCUCLK

Table 2.5 Clock Operating Modes

Halt mode

RUN

RUN

Halt 2 mode

RUN

STOP

SLP mode Debug mode*

STOP STOP

STOP RUN

(*) Debug mode is the mode used when debugging with the S5U1C33000H.




2.6

Electrical Characteristics

The C33 macro I/O cell library is designed based on the S1L50000 Series. Therefore, the electrical characteristics are basically the same as those of the S1L50000 Series. However, since the C33 macros include function blocks, such as CPU, DMA, PLL, oscillator, and A/D converter blocks, that have unique and special characteristics, this manual stipulates the electrical characteristics for this product.

The C33 macros include I/O buffers, such the data bus and the I/O ports. The default I/O buffer setup is based on that of the S1C33209 general-purpose product. Refer to section 2.3, "C33 Macro Pins" for detailed information.

2.6.1 Absolute Maximum Ratings

1) Single power source

Item

Supply voltage

Input voltage

Output voltage

Output current per pin

Analog power voltage

Analog input voltage

Storage temperature

Symbol

V

DD

V

I

V

O

I

OUT

AV

DD

AV

IN

T

STG

Condition Rated value

-0.3 to +4.0

-0.3 to V

DD

+0.5*

1

-0.3 to V

DD

+0.5*

1

±30

-0.3 to +7.0

-0.3 to AV

DD

+0.3

-65 to +150

*1: Voltages in the range -0.3 to +7.0 V are allowable for n-channel open-drain bidirectional buffers, IDC and IDH system input buffers, and failsafe cells.

(V

SS

=0V)

* mA

V

V

°C

Unit

V

V

V

2) Dual power source

Supply voltage

Input voltage

Output voltage

Item

Output current per pin

Storage temperature

Symbol

HV

DD

LV

DD

HV

I

LV

I

HV

O

LV

O

I

OUT

T

STG

Condition Rated value

-0.3 to +7.0

-0.3 to +4.0

-0.3 to HV

DD

+0.5*

1

-0.3 to V

DD

+0.5*

1

-0.3 to HV

DD

+0.5*

1

-0.3 to LV

DD

+0.5*

1

±30(±50*

2

)

-65 to +150

*1: Voltages in the range -0.3 to +7.5 V are allowable for n-channel open-drain bidirectional buffers, LIDC and LIDH system input buffers, and HIDC and HIDH system input buffers.

*2: Applies to 24 mA output current buffers.

(V

SS

=0V)

*

V

V

V mA

°C

Unit

V

V

V



EPSON 17


2.6.2 Recommended Operating Conditions

1) 3.3V single power source

Item

Supply voltage

Input voltage

CPU oprerating clock frequency

Low-speed oscillation frequency

V

V f

Symbol

DD

I

CPU

Condition

ROM-less model and 3.0±0.3V

ROM model and 3.0±0.3V

Min.

3.00

2.70

V

SS

–

–

Typ.

3.30

3.00

–

–

–

Max.

3.60

3.30

V

DD

*

1

60

50

(V

SS

=0V)

Unit

V

V

V

MHz

MHz

*

Operating temperature f

OSC1

Ta

Input rise time (normal input) tri

Input fall time (normal input) tfi

Input rise time (schmitt input) tri

Input fall time (schmitt input) tfi

Tj=0 to 85°C

Tj=-40 to 125°C

–

0

-40

–

–

–

–

32.768

25

25

–

–

–

–

–

70*

85*

100

100

10

10

2

3

KHz

°C

°C ns ns ms ms

*1: Either 5.25 V or 5.5 V is possible for n-channel open-drain bidirectional buffers and LIDC and LIDH system input buffers.

*2: This temperature range is the recommended ambient temperature assuming a junction temperature of Tj = 0 to 85 °C.

*3: This temperature range is the recommended ambient temperature assuming a junction temperature of Tj = -40 to 125 °C.


Item

Supply voltage

Input voltage

CPU oprerating clock frequency

Low-speed oscillation

frequency

V

DD

V

I f

Symbol

CPU

Condition Min.

1.80

V

SS

–

Typ.

2.00

–

–

Max.

2.20

V

DD

*

1

20

(V

SS

=0V)

* Unit

V

V

MHz

Operating temperature f

OSC1

Ta

Input rise time (normal input) tri

Input fall time (normal input) tfi

Input rise time (schmitt input) tri

Input fall time (schmitt input) tfi

Tj=0 to 85°C

Tj=-40 to 125°C

–

0

-40

–

–

–

–

32.768

25

25

–

–

–

–

–

70*

85*

100

100

10

10

2

3

KHz

°C

°C ns ns ms ms







3) 3.3 V/5.0 V dual power source

(V

SS

=0V)

Input voltage

Item

Supply voltage (high voltge)

Supply voltage (low voltge)

CPU operating clock frequency

Low-speed oscillation frequency

Operating temperature

Input rise time (normal input)

Input fall time (normal input)

Input rise time (schmitt input)

Input fall time (schmitt input)

L f f

Symbol

HV

LV

H

Ta tri tfi tri tfi

DD

VI

VI

DD

CPU

OSC1

Tj=0 to 85°C

Condition

ROM-less model and 3.0±0.3V

ROM model and 3.0±0.3V

Tj=-40 to 125°C

Min.

4.75

4.50

3.00

2.70

V

SS

V

SS

–

–

–

0

-40

–

–

–

–

Typ.

5.00

5.00

3.30

3.00

–

–

–

–

32.768

25

25

–

–

–

–

Max.

5.25

5.50

3.60

3.30

HV

DD

V

SS

60

50

–

70*

2

85*

3

100

100

10

10




ns ns ms ms

MHz

KHz

°C

°C

Unit

V

V

V

V

V

–

MHz

*

1

4) 2.0V/3.3V dual power source

(V

SS

=0V)

Item Symbol

Supply voltage (high voltge)

Supply voltage (low voltge)

Input voltage

HV

DD

LV

DD

H

VI

L

VI

CPU operating clock frequency f

CPU

Low-speed oscillation frequency f

OSC1

Operating temperature Ta

Condition Min.

3.00

1.80

V

SS

V

SS

–

–

0

-40

–

Typ.

3.30

2.20

–

–

–

32.768

25

25

–

–

–

–

Max.

3.60

Unit

V

2.20

HV

DD

*

1

LV

DD

*

1

20

V

V

V

MHz

–

70*

2

85*

3

50

100

50

100

5

10

5

10

KHz

°C

°C ns ns ns ns ms ms ms ms

*

Input rise time (normal input)

Input fall time (normal input)

Input rise time (schmitt input)

Input fall time (schmitt input)

Htri

Ltri

Htri

Ltri

Htri

Ltri

Htri

Ltri

–

–

–

*1: Either 5.25 V or 5.5 V is possible for n-channel open-drain bidirectional buffers and the LIDC and LIDH system or HIDC and HIDH system input buffers.





EPSON 19


2.6.3 DC Characteristics


(Unless otherwise specified: HV

DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to +85°C)

Condition * Item

Input leakage current

Off-state leakage current

High-level output voltage

Symbol

I

LI

I

OZ

V

OH

Low-level output voltage

High-level input voltage

V

OL

V

IH

Low-level input voltage V

IL

Positive trigger input voltage V

T+

Negative trigger input voltage V

T-

Hysteresis voltage V

H

Pull-up resistor

Pull-down registor

R

PU

R

PD

Input pin capacitance

Output pin capacitance

I/O pin capacitance

C

I

C

O

C

IO

I

OH

=-3mA, V

DD

=Min.

I

OL

=3mA, V

DD

=Min.

CMOS level, V

DD

=Max.

CMOS level, V

DD

=Min.

CMOS schmitt

CMOS schmitt

CMOS schmitt

V

I

=0V

V

I

= V

DD

(#ICEMD) f=1MHz, V

DD

=0V f=1MHz, V

DD

=0V f=1MHz, V

DD

=0V

Typ.

–

–

–

3.1

–

288

144

0.4

–

1.0

4.0

10

10

10

–

–

120

60

–

–

–

–

–

–

–

0.8

0.3

60

30

–

3.5

–

2.0

–

–

–

Min.

-1

-1

V

DD

-0.4

Max.

1

1

–

Unit

µA

µA

V

V

V

V

V

V

V

K

Ω

K

Ω pF pF pF


Item






V

OL

V

IH

Low-level input voltage V

IL


T+

Negative trigger input voltage

V

T-


H

Symbol

I

LI

I

OZ

V

OH

I

OH

I

OL

(Unless otherwise specified: V

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to +85°C)

Condition *

=-2mA, V

=2mA , V

DD

DD

CMOS level, V

CMOS level, V

LVTTL schmitt

=Min.

=Min.

DD

DD

=Max.

=Min.

Min.

-1

-1

V

DD

-0.4

–

2.4

–

1.1

Typ.

–

–

–

–

–

–

–

Max.

1

1

–

0.4

–

0.4

2.4

Unit

µA

µA

V

V

V

V

V

LVTTL schmitt

LVTTL schmitt

0.6

– 1.8

V

Pull-up resistor

Pull-down registor



I/O pin capacitance

R

R

C

C

C

PU

PD

I

O

IO

V

V

I

I

=0V

=V

DD

(#ICEMD) f=1MHz, V f=1MHz, V f=1MHz, V

DD

DD

DD

=0V

=0V

=0V

Other than DSIO

DSIO

–

–

–

0.1

80

40

40

–

–

–

–

200

100

100

10

10

10

–

480

240

240

V k

Ω k

Ω k

Ω pF pF pF






DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to +85°C)

* Item Symbol






Low-level input voltage

Pull-down registor

V

IH

V

IL


T+

Negative trigger input voltage V

T-


H

Pull-up resistor R

PU

R

PD


I

LI

I

OZ

V

OH

V

OL


I/O pin capacitance

C

I

C

O

C

IO

Condition

I

OH

=-0.6mA, V

DD

=Min.

I

OL

=0.6mA, V

DD

=Min.

CMO level, V

DD

=Max.

CMO level, V

DD

=Min.

CMO schmitt

CMO schmitt

CMO schmitt

V

I

=0V

V

I

=V

DD

(#ICEMD) f=1MHz, V

DD

=0V f=1MHz, V

DD

=0V f=1MHz, V

DD

=0V

Min.

-1

-1

V

DD

-0.2

–

0

60

30

–

1.6

–

0.4

0.3

–

–

–

–

–

–

–

240

120

–

–

–

–

Typ.

–

–

–

V

V

V

V

V

V

K

Ω

K

Ω

Unit

µA

µA

V pF pF pF

10

10

10

1.4

–

600

300

0.2

–

0.3

1.6

Max.

1

1

–

2.6.4 Current Consumption

The current consumption of C33 ICs is defined as that for the C33 macro block V

DD

system. The current consumption of user circuits and functional blocks other than C33 macros is not included in these ratings.


Item

Operating current

Operating current

Operating current

Operating current

Clock timer operation current

Symbol

I

I

I

I

I

DD1

DD2

DD3

DD4

DDCT


DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to +85°C)

Condition *

When CPU is operating

HALT mode

HALT2 mode, 20MHz

Sleep mode

When clock timer only is operating

OSC1oscillation: 32KHz

20MHz

33MHz

50MHz

20MHz

33MHz

50MHz –

–

–

–

–

Min.

–

–

–

–

12

20

30

1.8

1

Typ.

25

40

65

7

16

26

40

2.5

30

Max.

35

60

85

– mA mA mA mA

µA

Unit mA mA mA

µA



EPSON 21



Item

Operating current

Operating current

Operating current

Operating current

Clock timer operation current


DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to +85°C)

* Symbol

I

DD1

I

DD2

I

DD3

I

DD4

I

DDCT

Condition

When CPU is operating

HALT mode

HALT2 mode, 20MHz

Sleep mode

When clock timer only is operating

OSC1oscillation: 32KHz

20MHz

20MHz

20MHz

Min.

–

–

–

–

–

Typ.

13

6

0.4

1

1.5

Max.

19

9

1.0

30

–

Unit mA mA mA

µA

µA

Item Symbol Condition

AD converter operating current

AI

DD1

AV

DD

=HV

DD

=4.5V to 5.5V

V

DD

=AV

DD

=2.7V to 3.6V

Current consumption measurement condition:

VIH=V

DD

, V

IL

=0V, output pins are open, V

DD

current is not included

Min.

–

–

Typ.

800

500

Max.

1400

800

Unit

µA

*

No.

1

2

3

4

5

6

OSC3

On

On

On

Off

Off

On

OSC1

Off

Off

Off

Off

On

Off

CPU

Normal operation

* 1

HALT mode

HALT2 mode

SLEEP mode

HALT mode

HALT mode

Clock timer

Stop

Stop

Stop

Stop

Run

Stop

Other peripheral circuits

Stop

Stop

Stop

Stop

Stop

A/D converter only operated, conversion clock frequency=2MHz

*1: The values of current consumption while the CPU is operating were measured when a test program that consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction is being executed in the built-in RAM continuously.

2.6.5 A/D Converter Characteristics



DD

=AV

DD

=4.5V to 5.5V, V

SS

=AV

SS

=0V, Ta=-40 to +85°C, ST[1:0]=11)

Resolution

Item Symbol

–

Conversion time

Zero scale error

Full scale error

Integral linearity error t

ADC

E

ZS

E

FS

E

IL

Differential linearity error E

DL

Permissible signal source impedance A

IMP

Analog input capacitance A

CIN

Condition

ST[1:0]=00(Min.), 11(Max.)

Best straight line method

Min.

–

5

0

-2

-3

-3

–

–

–

–

–

–

–

Typ.

10

–

2

* Note 1: Indicates the minimum value when A/D clock = 4MHz (maximum clock frequency in 5V system).

3

5

2

3

45

Max.

–

–

4

LSB

LSB

LSB

K

Ω pF

Unit bit

*

µs 1

LSB

22

3) Analog power current






DD

=AV

DD

=2.7V to 3.6V, V

SS

=AV

SS

=0V, Ta=0 to +70°C, A/D converter clock input f=2MHz, ST[1:0]=11)

Resolution

Conversion time

Item

Zero scale error

Full scale error

Integral linearity error

Differential linearity error

Permissible signal source impedance

Analog input capacitance

Symbol

– t

ADC

E

ZS

E

FS

E

IL

E

DL

Condition

ST[1:0]=00(Min.), 11(Max.)

Best straight line method

A

IMP

-2

-3

-3

Min.

–

10

0

–

–

–

–

Typ.

10

–

2

–

A

CIN

– –

Note 1: Indicates the minimum value when A/D clock = 2MHz (maximum clock frequency in 3V system).

Note 2: • Be sure to use as V

DDE

= AV

DD

.

•

The A/D converter cannot be used when the S1C33209/204/202 is used with a 2V power source.

2

3

3

Max.

–

–

4

5

45

Unit bit

*

µs 1

LSB

LSB

LSB

LSB

K

Ω pF

A/D conversion error

V[000]h = Ideal voltage at zero-scale point (=0.5LSB)

V'[000]h = Actual voltage at zero-scale point

V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB)

V'[3FF]h = Actual voltage at full-scale point

1LSB =

1LSB' =

AV DD - V SS

2 10 - 1

V'[3FF]h - V'[000]h

2 10 - 2

■ Zero scale error

004

Ideal conversion characteristic

003

002

V[000]h

(=0.5LSB)

001

Actual conversion characteristic

Zero scale error E

ZS

=

(V'[000]h - 0.5LSB') - (V[000]h - 0.5LSB)

1LSB

[LSB]

V'[000]h

000

V SS

Analog input

■ Full scale error

V'[3FF]h

3FF

V[3FF]h (=1022.5LSB)

3FE

3FD

Full scale error E

FS

=

(V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB)

1LSB

[LSB]


3FC

3FB


AV DD

Analog input



EPSON 23


■ Integral linearity error

3FF

3FE

V'[3FF]h

3FD Integral linearity error E

L

=

V

N

' - V

N

1LSB'

[LSB]

V

N

V

N

'

003


002


001

V'[000]h

000

V SS

Analog input

■ Differential linearity error

AV DD

N+1

N

N-1

N-2



V'[N]h

V'[N-1]h

Analog input

Differential linearity error E

D

=

V'[N]h - V'[N-1]h

1LSB'

- 1 [LSB]

2.6.6 AC Characteristics

The C33 macro block AC characteristics fall into two major sets.

One is the AC characteristics for the I/O buffer pins built into the C33 macros. These characteristics stipulate the timing conditions for the interface with circuits outside the chip. These AC characteristics are listed in section 2.6.6.3, "AC Characteristics Tables (I/O Buffer Pins)" and the timing charts are shown in section 2.6.6.4, "AC Characteristics Timing Charts (I/O Buffer Pins)."

The other set is the AC characteristics for the signals that connect the C33 macro blocks to the user circuits on the same chip. These AC characteristics are listed in section 2.6.6.5, "AC Characteristics

Tables (User Logic Interface)" and the timing charts are shown in section 2.6.6.6, "AC Characteristics

Timing Charts (User Logic Interface)."

The C33 macro bus interface can connect a wide range of external memory types, from SRAM and

ROM to EDO DRAM and burst ROM. The bus interface with chip internal user logic can only be used as an SRAM type interface.




2.6.6.1

Symbol Description

tCYC: Bus-clock cycle time

• In x1 mode, t

CYC

= 50 nS (20 MHz) when the CPU is operated with a 20-MHz clock t

CYC

= 30 nS (33 MHz) when the CPU is operated with a 33-MHz clock

• In x2 mode, t

CYC


CYC


CYC

= 33 nS (30 MHz) when the CPU is operated with a 60-MHz clock

WC: Number of wait cycles

Up to 7 wait cycles can be specified using the BCU control register. It is also possible to extend the number of wait cycles by inputs (wait request inputs) to the P_P30 (#WAIT) pin or the U_WAIT_X pin when it is necessary.

The minimum number of read cycles with no wait (0) inserted is 1 cycle.

The minimum number of write cycles with no wait cycle (0) inserted is 2 cycles. It does not change even if 1-wait cycle is set. The write cycle is actually extended when 2 or more wait cycles are set.

When inserting wait cycles by controlling the wait request inputs from external circuits, the sampling timing of the wait request input requires careful attention. Read cycles are terminated on the cycle that the negation of the wait request input was sampled. Write cycles are terminated on the cycle following the cycle that the negation of the wait request input was sampled.

C1, C2, C3, Cn: Cycle number

C1 indicates the first cycle when the BCU transfers data from/to an external memory or another device. Similarly, C2 and Cn indicate the second cycle and nth cycle, respectively.

Cw: Wait cycle

Indicates that the cycle is wait cycle inserted.



EPSON 25


2.6.6.2

AC Characteristics Measurement Condition

Signal detection level: Input signal High level V

IH

= V

DD

- 0.4 V

Low level V

IL

= 0.4 V

Output signal High level V

OH

= 1/2 V

DD

Low level V

OL

= 1/2 V

DD

The following applies when OSC3 is external clock input:

Input signal High level V

IH

= 1/2 V

DD

Low level V

IL

= 1/2 V

DD

Input signal waveform: Rise time (10%

→

90% V

DD

) 5 ns (I/O buffer pins)

Fall time (90%

→

10% V

DD

) 5 ns (I/O buffer pins)

Output load capacitance: CL = 50 pF (I/O buffer pins only)

F/O = 1 (User logic interface)




2.6.6.3

AC Characteristics Tables (I/O Buffer Pins)

The tables in this section stipulate the timing of the interface between the C33 macros and circuits external to the chip.

External clock input characteristics

Note: These AC characteristics apply to input signals from outside the IC.



DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Item Symbol Min.

High-speed clock cycle time

P_OSC3 clock input duty

P_OSC3 clock input rise time

P_OSC3 clock input fall time t

C3 t

C3ED t

IF t

IR

P_BCLK high-level output delay time

P_BCLK low-level output delay time t

CD1 t

CD2

Minimum reset pulse width (P_RESETX input) t

RST

Note: The input to the OSC3 pin must be in the range V

SS

to LV

DD

.

30

45

6

× t

CYC

55

5

5

35

35 ns ns ns ns

Unit ns

% ns



DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Item Symbol





C3 t

C3ED t

IF t

IR



CD1 t

CD2


RST


SS

to V

DD

.

6

Min.

30

45

× t

CYC

55

5

5

35

35 ns ns ns ns

Unit ns

% ns



DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Item Symbol





C3 t

C3ED t

IF t

IR



CD1 t

CD2


RST


SS

to V

DD

.

6

Min.

30

45

× t

CYC

55

5

5

60

60 ns ns ns ns

Unit ns

% ns



EPSON 27


BCLK clock output chracteristics

Note: These AC characteristic values are applied only when the high-speed oscillation circuit is used.



DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Item

P_BCLK clock output duty

Symbol t

CBD

Min.

40

Max.

60

Unit

%

*


Item



DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

CBD

Min.

40

Max.

60

Unit

%

*


Item



DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

CBD

Min.

40

Max.

60

Unit

%

*

Common characteristics

1) 3.3/5.0V dual power source


DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

* Item

Address delay time

P_CEx delay time (1)


Wait setup time

Wait hold time

Read signal delay time (1)

Read data setup time

Read data hold time

Write signal delay time (1)

Write data delay time (1)


Write data hold time

Symbol t

AD t

CE1 t

CE2 t

WTS t

WTH t

RDD1 t

RDS t

RDH t

WRD1 t

WDD1 t

WDD2 t

WDH

Min.

–

–

–

15

0

12

0

0

0

–

–

8

Max.

8

8

8

8

10

10 ns ns ns ns

Unit ns ns ns ns ns ns ns ns





Item

Address delay time



Wait setup time

Wait hold time



Read data hold time






DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

* Symbol t

AD t

CE1 t

CE2 t

WTS t

WTH t

RDD1 t

RDS t

RDH t

WRD1 t

WDD1 t

WDD2 t

WDH

Min.

–

–

–

15

0

15

0

0

0

Max.

10

10

10

–

–

10

10

10

10 ns ns ns ns



Item

Address delay time



Wait setup time

Wait hold time



Read data hold time






DD

= 1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

* Symbol t

AD t

CE1 t

CE2 t

WTS t

WTH t

RDD1 t

RDS t

RDH t

WRD1 t

WDD1 t

WDD2 t

WDH

Min.

–

–

–

40

0

40

0

0

0

Max.

20

20

20

–

–

20

20

20

20 ns ns ns ns


SRAM read cycle

1) 3.3/5.0V dual power source


DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Item


Read signal pulse width

Read address access time (1)

Chip enable access time (1)

Read signal access time (1)

Symbol t

RDD2 t

RDW t

ACC1 t

CEAC1 t

RDAC1 t

CYC

Min.

(0.5+WC)-8 t t t

CYC

CYC

CYC

Max.

8

(1+WC)-20

(1+WC)-20

(0.5+WC)-20

Unit ns ns ns ns ns

*



EPSON 29



Item







Item






SRAM write cycle



DDE

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Item


Write signal pulse width

Symbol t

WRD2 t

WRW t

CYC

Min.

(1+WC)-10

Max.

8

Unit ns ns

*



DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

RDD2 t

RDW t

ACC1 t

CEAC1 t

RDAC1 t

CYC

Min.

(0.5+WC)-10 t t t

CYC

CYC

CYC

Max.

10

(1+WC)-60

(1+WC)-60

(0.5+WC)-60

Unit ns ns ns ns ns

*

Item




DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

WRD2 t

WRW t

CYC

Min.

(1+WC)-10

Max.

10

Unit ns ns

*



DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

RDD2 t

RDW t

ACC1 t

CEAC1 t

RDAC1 t

CYC

Min.

(0.5+WC)-10 t t t

CYC

CYC

CYC

Max.

10

(1+WC)-25

(1+WC)-25

(0.5+WC)-25

Unit ns ns ns ns ns

*

Item




DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

WRD2 t

WRW t

CYC

Min.

(1+WC)-20

Max.

20

Unit ns ns

*




DRAM access cycle common characteristics

The #RAS and #CAS symbols in the stipulations for the DRAM interface in the following tables are to be interpreted as follows.

• #RAS refers to that signal any one of the chip enable signals (P_CE

X

signals) set up by the bus controller (BCU) to operate as a RAS signal for the DRAM.

• #CAS refers to the P_HCAS_X or the P_LCAS_X signal.



DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Item

#RAS signal delay time (1)


#RAS signal pulse width

#CAS signal delay time (1)


#CAS signal pulse width


Read signal pulse width (2)


Write signal pulse width (2)

Symbol t

RASD1 t

RASD2 t

RASW t

CASD1 t

CASD2 t

CASW t

RDD3 t

RDW2 t

WRD3 t

WRW2 t t t t

CYC

CYC

CYC

CYC

(2+WC)-10

(0.5+WC)-5

(2+WC)-10

(2+WC)-10

Max.

10

10

10

10

10

10 ns ns ns ns ns ns ns

Unit ns ns ns


Item












DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Symbol t

RASD1 t

RASD2 t

RASW t

CASD1 t

CASD2 t

CASW t

RDD3 t

RDW2 t

WRD3 t

WRW2 t t t t

CYC

CYC

CYC

CYC

(2+WC)-10

(0.5+WC)-10

(2+WC)-10

(2+WC)-10

Max.

10

10

10

10

10


Unit ns ns ns



EPSON 31



Item











(Unless otherwise specified: VDD=1.8V to 2.2V, VSS=0V, Ta=–40 to 85°C)

Min.

Symbol t

RASD1 t

RASD2 t

RASW t

CASD1 t

CASD2 t

CASW t

RDD3 t

RDW2 t

WRD3 t

WRW2 t t t t

CYC

CYC

CYC

CYC

(2+WC)-20

(0.5+WC)-20

(2+WC)-20

(2+WC)-20

Max.

20

20

20

20

20


Unit ns ns ns

*

DRAM random access cycle and DRAM fast-page cycle



DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Item

Column address access time

#RAS access time

#CAS access time

Symbol t

ACCF t

RACF t

CACF

Max.

t

CYC

(1+WC)-25 t

CYC

(1.5+WC)-25 t

CYC

(0.5+WC)-25

Unit ns ns ns


Item


#RAS access time

#CAS access time


Item


#RAS access time

#CAS access time


DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

Symbol t

ACCF t

RACF t

CACF

Max.

t

CYC

(1+WC)-25 t

CYC

(1.5+WC)-25 t

CYC

(0.5+WC)-25

Unit * ns ns ns


DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Symbol t

ACCF t

RACF t

CACF

Max.

t

CYC

(1+WC)-60 t

CYC

(1.5+WC)-60 t

CYC

(0.5+WC)-60

Unit ns ns ns



EDO DRAM random access cycle and EDO DRAM page cycle




DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Item


#RAS access time

#CAS access time


Symbol t

ACCE t

RACE t

CACE t

RDS2

20

Max.

t

CYC

(1.5+WC)-25 t

CYC

(2+WC)-25 t

CYC

(1+WC)-15

Unit ns ns ns ns


Item


#RAS access time

#CAS access time



DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Symbol t

ACCE t

RACE t

CACE t

RDS2

20

Max.

t

CYC

(1.5+WC)-25 t

CYC

(2+WC)-25 t

CYC

(1+WC)-20

Unit ns ns ns ns


Item


#RAS access time

#CAS access time



DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Symbol t

ACCE t

RACE t

CACE t

RDS2

20

Max.

t

CYC

(1.5+WC)-60 t

CYC

(2+WC)-60 t

CYC

(1+WC)-60

Unit ns ns ns ns



EPSON 33


Burst ROM read cycle



DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Item




Burst address access time

Symbol t

ACC2 t

CEAC2 t

RDAC2 t

ACCB

Max.

t

CYC

(1+WC)-20 t

CYC

(1+WC)-20 t

CYC

(0.5+WC)-20 t

CYC

(1+WC)-20

Unit ns ns ns ns


Item






DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Symbol t

ACC2 t

CEAC2 t

RDAC2 t

ACCB

Max.

t

CYC

(1+WC)-25 t

CYC

(1+WC)-25 t

CYC

(0.5+WC)-25 t

CYC

(1+WC)-25

Unit ns ns ns ns


Item






DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Min.

* Symbol t

ACC2 t

CEAC2 t

RDAC2 t

ACCB

Max.

t

CYC

(1+WC)-60 t

CYC

(1+WC)-60 t

CYC

(0.5+WC)-60 t

CYC

(1+WC)-60

Unit ns ns ns ns

External bus master and NMI

The #BUSRE0, #BUSACK, and #NMI symbols in the external bus master and NMI timing stipulations in the following tables are to be interpreted as follows.

#BUSRE0: When the P_34 pin is set up as bus request signal input from an external bus master.

#BUSACK: When the P_35 pin is set up as the bus acknowledge signal output to an external bus master.

#NMI: The P_NMI_X input






DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Max.

Item

#BUSREQ signal setup time

#BUSREQ signal hold time

#BUSACK signal output delay time

High-impedance

→

output delay time

Output

→

high-impedance delay time

#NMI pulse width

Symbol t

BRQS t

BRQH t

BAKD t

Z2E t

B2Z t

NMIW

Min.

15

0

30

10

10

10 ns ns ns

Unit * ns ns ns


Item




High-impedance

→

output delay time

Output

→


#NMI pulse width


DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C )

Symbol t

BRQS t

BRQH t

BAKD t

Z2E t

B2Z t

NMIW

Min.

15

0

30

Max.

10

10

10 ns ns ns

Unit ns ns ns

*


Item




High-impedance

→

output delay time

Output

→


#NMI pulse width


DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Symbol t

BRQS t

BRQH t

BAKD t

Z2E t

B2Z t

NMIW

Min.

40

0

90

20

20

20 ns ns ns

Unit ns ns ns



EPSON 35


Input, Output and I/O port

The tables in this section stipulate the AC characteristics of the P_Pxx and P_Kxx ports.

1) 3.3V/5.0V single power source


DD

=4.5V to 5.5V, LV

DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Max.

Item

Input data setup time

Input data hold time

Output data delay time

P_Kxx-port interrupt SLEEP, HALT2 mode input pulse width Others

Symbol t

INPS t

INPH t

OUTD t

KINW

Min.

20

10

30

2

×

t

CYC

20

Unit * ns ns ns ns ns


Item






DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Symbol t

INPS t

INPH t

OUTD t

KINW

Min.

20

10

30

2

×

t

CYC

20

Unit ns ns ns ns ns


Item






DD

=1.8V to 2.2V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Symbol t

INPS t

INPH t

OUTD t

KINW

Min.

40

20

90

2

×

t

CYC

30

Unit ns ns ns ns ns




2.6.6.4

AC Characteristics Timing Charts (I/O Buffer Pins)

This section presents the timing charts for the interface between the C33 macros and chip-external circuits.

Clock

(1) When an external clock is input (in x1 speed mode): t

C3 t

C3H

P_OSC3

(High-speed clock) t

IF t

CD1 t

CD2 t

C3

P_BCLK

(Clock output) t

IR t

C1 t

C1H

P_OSC1

(Low-speed clock)

(2) When the high-speed oscillation circuit is used for the operating clock: t

C3 t

CBH

P_BCLK

(Clock output) t

C3ED

= t

C3H

/ t

C3 t

C1ED

= t

C1H

/ t

C1 t

CBD

= t

CBH

/ t

C3

SRAM read cycle (basic cycle: 1 cycle) t

C3

P_BCLK t

AD t

AD

P_A[23:0] t

CE1 t

CE2

P_CEx t

RDD1 t

RDD2 t

RDW

P_RD_X t

CEAC1 t

ACC1 t

RDAC1

P_D[15:0] t

RDS t

RDH

*1 t

WTS t

WTH

P_P30

(Wait input)

∗

1 tRDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the

P_A[23:0] signals.



EPSON 37


SRAM read cycle (when a wait cycle is inserted)

C1 Cw (wait cycle) Cn (last cycle)

P_BCLK t

AD t

AD

P_A[23:0] t

CE1 t

CE2

P_CEx t

RDD1 (C1 only) t

RDD2 t

RDW

P_RD_X t

CEAC1 t

ACC1 t

RDAC1

P_D[15:0] t

WTS t

WTH t

WTS t

WTH t

RDS t

RDH

*1

P_P30

(Wait input)

∗

1 tRDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the

P_A[23:0] signals.

SRAM write cycle (basic cycle: 2 cycles)

C1 C2

P_BCLK

P_A[23:0]

P_CEx t

AD t

CE1 t

AD t

CE2

P_WRx_X

P_D[15:0]

P_P30

(Wait input) t

WTS t

WRD1 t

WRW t

WDD1 t

WTH t

WRD2 t

WDH




SRAM write cycle (when wait cycles are inserted)

C1 Cw (wait cycle)

Wait cycle follows

Cw (wait cycle)

Last cycle follows

P_BCLK

P_A[23:0]

P_CEx t

AD t

CE1 t

WRD1 t

WRW

P_WRx_X

P_D[15:0]

P_P30

(Wait input) t

WTS t

WDD1 t

WTH t

WTS t

WTH t

WTS t

WTH

Cn (last cycle) t

WRD2 t

AD t

CE2 t

WDH

DRAM random access cycle (basic cycle)

RAS1

Data transfer #1

CAS1 PRE1 (precharge)

Next data transfer

RAS1' CAS1'

P_BCLK t

AD t

AD t

AD

P_A[23:0] t

RASD1 t

RASD2 t

RASW

P_CEx

(RAS output) t

CASD1 t

CASD2 t

CASW

P_HCAS_X/

P_LCAS_X t

RDD1 t

RDD3 t

RDW2

P_RD_X t

RACF t

ACCF t

RDS t

CACF t

RDH

*1

D[15:0]

(Read) t

WRD1 t

WRD3 t

WRW2

P_WRL_X t

WDD1 t

WDD2

P_D[15:0]

(Write)

∗

1 t RDH is measured with respect to the first signal change (negation) of either the P_RD or the P_A[23:0] signals.



EPSON 39


DRAM fast-page access cycle

RAS1

Data transfer #1

CAS1

Data transfer #2


Next data transfer

RAS1'

P_BCLK t

AD t

AD t

AD

P_A[23:0] t

RASD1 t

RASD2 t

RASW

P_CEx

(RAS output) t

CASD1 t

CASD2 t

CASW

P_HCAS_X/

P_LCAS_X t

RDD1 t

RDD3 t

RDW2

P_RD_X t

RACF t

ACCF t

RDS t

CACF t

ACCF t

*1

RDH t

RDS t

*1

RDH

P_D[15:0]

(Read) t

WRD1 t

WRD3 t

WRW2

P_WRL_X t

WDD1 t

WDD2 t

WDD2

P_D[15:0]

(Write)

∗

1 t RDH is measured with respect to the first signal change (negation) of either the P_RD or the P_A[23:0] signals.

EDO DRAM random access cycle (basic cycle)

RAS1

Data transfer #1


Next data transfer

RAS1' CAS1'

P_BCLK t

AD t

AD t

AD

P_A[23:0] t

RASD1 t

RASD2 t

RASW

P_CEx

(RAS output) t

CASD1 t

CASD2 t

CASW

P_HCAS_X/

P_LCAS_X t

RDD1 t

RDD3 t

RDW2

P_RD_X t

CACE t

RACE t

ACCE t

RDS2 t

RDH

*1

P_D[15:0]

(Read) t

WRD1 t

WRD3 t

WRW2

P_WE t

WDD1 t

WDD2

D[15:0]

∗

1 t RDH is measured with respect to the first signal change (negation) of either the P_RD or the P_RASx signals.




EDO DRAM page access cycle

RAS1

Data transfer #1

CAS1

Data transfer #2


Next data transfer

RAS1'

P_BCLK t

AD t

AD t

AD

P_A[23:0] t

RASD1 t

RASD2 t

RASW

P_CEx

(RAS output) t

CASD1 t

CASD2 t

CASW

P_HCAS_X/

P_LCAS_X t

RDD1 t

RDD3 t

RDW2

P_RD_X t

ACCE t

RACE t

ACCE t

CACE t

RDS t

RDH t

RDS t

RDH

*1

P_D[15:0]

(Read) t

WRD1 t

WRD3 t

WRW2

P_WRL_X t

WDD1 t

WDD2 t

WDD2

D[15:0]

(Write)

∗

1 t RDH is measured with respect to the first signal change from among the P_RD (negation), P_RASx

(negation), or the #CAS (fall) signals.

DRAM CAS-before-RAS refresh cycle

C

CBR1

CBR refresh cycle

C

CBR2 t

RASD1

C

CBR3 t

RASD2

P_BCLK

P_CEx

(RAS output)

P_HCAS_X/

P_LCAS_X

P_WRL_X

DRAM self-refresh cycle t

CASD1 t

CASD2

P_BCLK

P_CEx

(RAS output)

P_HCAS_X/

P_LCAS_X

Self-refresh mode setup t

CASD1

Self-refresh mode Self-refresh mode canceration

6-cycle precharge

(Fixed) t

RASD1 t

RASD2 t

CASD2



EPSON 41


Burst ROM read cycle

SRAM read cycle Burst cycle

P_BCLK t

AD t

AD

P_A[23:2] t

AD t

AD t

AD t

AD t

AD

P_A[1:0] t

CE1 t

CE2

P_CEx t

RDD1 t

RDD2

P_RD_X t

ACC2 t

CEAC t

RDAC2 t

RDS t

ACCB t

RDS t

ACCB t

RDS t

ACCB t

RDS

P_D[15:0] t

RDH t

RDH t

RDH t

RDH

*1

∗

1 t RDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the

P_A[23:0] signals.

External bus master and NMI timing

Burst cycle Burst cycle

P_BCLK t

BRQS t

BRQH

P_P34(#BUSREQ)

Valid input t

BAKD

P_P35(#BUSACK) t

Z2E eBUS_OUT signals *1 t

B2Z eBUS_OUT signals *1 t

NMIW

P_NMI

*1 eBUS_OUT indicates the following pins:

P_A[23:0], P_RD_X, P_WRL_X, P_WRH_X, P_HCAS_X, P_LCAS_X, P_CEx[17:4], P_D[15:0]

Input, output and I/O port timing

P_BCLK

Kxx, Pxx

(input: data read

from the port)

Pxx, Rxx (output)

Kxx

(K-port interrupt input) t

INPS

Valid input t

KINW t

INPH t

OUTD




2.6.6.5

AC Characteristics Tables (User Logic Interface)

The tables in this section stipulate the timing of the interface between the C33 macros and the user logic on the same chip. (Note that these timing values must be verified by simulation at the end of the development process.)

External clock input characteristic

This table stipulates the AC characteristics for V

DD

in the range 3.0 to 3.6 V.

Consult your Seiko Epson representative for details on AC characteristics under other conditions.

Item

Low-speed clock cycle time

U_OSC1CLK clock duty


DD

= 3.0 to 3.6 V, V

SS

= 0 V, Ta = -40 to 85°C)

Symbol t

C1 t

UC1D

Min.

–

45

Max.

–

55

Unit * ns 1

%


U_OSC3CLK clock duty

30

40

–

60 ns

%

U_PLLCLK clock cycle time

U_PLLCLK clock duty

U_PLLCLK clock delay time

U_BCLK clock cycle time

U_BCLK clock duty

U_BCLK clock delay time

U_PERICLK clock cycle time

U_PERICLK clock duty

U_PERICLK clock delay time

U_BCUCLK clock cycle time

U_BCUCLK clock duty

U_BUCLK clock delay time t

CBCLK t

UCBD t

UCDB t

CPSC t

VPD t

UDP t

C3 t

U3D t

UPLL t

UCPD t

UCDP t

CBCU t

UBD t

UDB

16.66

40

–

16.66

40

–

16.66

40

–

16.66

40

–

–

60

10

–

60

10

–

60

13

–

60

5 ns

% ns ns

% ns ns

% ns ns

% ns

Reset assert delay time

Reset deassert delay time

Minimum reset pulse width t

URA t

URD t

URST

6 t

–

– cyc

10

6

– ns ns ns

Note 1: For the OSC1 clock cycle time, the frequency adjustment range is 50 ppm at f

OSC1

= 32.768 MHz. Refer to section

2.6.6.7, "Oscillator Characteristics" for details.

Note 2: The AC characteristics for the clocks shown above assume that the clocks are generated by the OSC1 and OSC3 oscillator circuits.



EPSON 43


Common Characteristics (User Logic Interface)

The V

DD

and V

SS

levels are always used for the interface with user logic.

Item

Address delay time

U_CE

X

delay time (1)

U_CE

X

delay time (2)

Wait setup time

Wait hold time



Read data hold time






DD

=3.0V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

* Symbol t

UAD t

UCE1 t

UCE2 t

UWTS t

UWTH t

URDD1 t

URDS t

URDH t

UWRD1 t

UWDD1 t

UWDD2 t

UWDH

Min.

–

–

–

10

0

13

0

0

0

–

–

7

Max.

7

7

7

7

7

7 ns ns ns ns


SRAM read cycle

Item







DD

=2.7V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

URDD2 t

URDW t

UACC1 t

UCEAC1 t

URDAC1 t

CYC

Min.

(0.5+WC)-7 t t t

CYC

CYC

CYC

Max.

7

(1+WC)-20

(1+WC)-20

(0.5+WC)-20

Unit ns ns ns ns ns

*

SRAM write cycle

Item

Write signal delay time



DD

=3.0V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Symbol t

WRD2 t

WRW t

CYC

Min.

(1+WC)-7

Max.

7

Unit ns ns

*

Input, Output, I/O Ports (User Logic Interface)

Item




K-port interrupt SLEEP, HALT2 mode input pulse width Others


DD

=3.0V to 3.6V, V

SS

=0V, Ta=–40 to 85°C)

Max.

* Symbol t

UINPS t

UINPH t

UOUTD t

UKINW

Min.

10

5

30

2

×

t

CYC

10

Unit ns ns ns ns ns




2.6.6.6

AC Characteristics Timing Charts (User Logic Interface)

This section presents the timing charts for the interface between C33 macros and the user logic on the same chip.

Clock signals t

C1 t

UC1H t

UC1L

U_OSC1CLK t

UC3L t

UC1D= t

UC1H t

C2 t

U3D= t

UC3H t

C3

U_OSC3CLK t

C3 t

UC3H t

UCDP t

UCPH t

UPLL t

UCPL

U_PLLCLK t

UCPD= t

UCPH t

UPLL t

UCDB t

UCBH t

CBCLK t

UCBL t

UCBD= t

UCBH t

CBCLK

U_BCLK

(Default output) t

UDP t

CPSC t

UPH t

UPL t

UPD= t

UPH t

CPSC

U_PERICLK t

UDB t

CBCU t

UBH t

UBL t

UBD= t

CBH t

CBCU

U_BCUCLK



EPSON 45


Reset

P_RESETX

U_BCUCLK

U_RST_X t

URA t

URST t

URD

SRAM read cycle (Basic cycle: 1 cycle) t

C3

U_BCUCLK t

AD t

AD

U_ADDR[23:0] t

CE1 t

CE2

U_CEx t

RDD1 t

RDW t

RDD2

U_RD_

X t

CEAC1 t

ACC1 t

RDAC1

U_DIN[15:0] t

RDS t

RDH

*1 t

WTS t

WTH

U_WAIT_X

∗

1 t RDH is measured with respect to the first signal change (negation) of either the P_RD, P_CEx, or the

P_A[23:0] signals.




SRAM read cycle (when a wait cycle is inserted)

C1 Cw (wait cycle) Cn (last cycle)

U_BCUCLK t

AD t

AD

U_ADDR[23:0] t

CE1 t

CE2

U_CEx t

RDD1 (C1 only) t

RDD2 t

RDW

U_RD_X t

CEAC1 t

ACC1 t

RDAC1

U_DIN[15:0] t

WTS t

WTH t

WTS t

WTH t

RDS t

RDH *1

U_WAIT_X

∗

1 t RDH is measured with respect to the first signal change (negation) of either the P_RD, P_CEx, or the

P_A[23:0] signals.

SRAM write cycle (basic cycle: 2 cycles)

C1

U_BCUCLK

U_ADDR[23:0]

U_CEx

U_WRL_X/

U_WRH_X

U_DOUT[15:0]

U_WAIT_X t

WDD1 t

WTS t

AD t

CE1 t

WRD1 t

WRW t

WTH

C2 t

WRD2 t

AD t

CE2 t

WDH



EPSON 47


SRAM write cycle (when wait cycles are inserted)

C1 Cw (wait cycle)

Wait cycle follows

Cw (wait cycle)

Last cycle follows

U_BCUCLK

U_ADDR[23:0]

U_CEx

U_WRL_X/

U_WRH_X

U_DOUT[15:0]

U_WAIT_X t

AD t

CE1 t

WRD1 t

WDD1 t

WTS t

WTH t

WTS t

WRW t

WTH t

WTS t

WTH

Cn (last cycle) t

WRD2 t

AD t

CE2 t

WDH

Input, output and I/O port timing

U_BCLK

U_Kxx, Pxx

(input: data read

from the port)

U_Pxx (output)

U_Kxx

(K-port interrupt input) t

UINPS t

UINPH

Valid input t

UOUTD t

UKINW




2.6.6.7

Oscillation Characteristics

Oscillation characteristics change depending on conditions (board pattern, components used, etc.).

Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer recommended values for constants such as capacitance and resistance.

OSC1 crystal oscillation

(Unless otherwise specified: crystal=C-002RX

∗

1

, 32.768kHz, Rf

1

=20M

Ω

, C

G1

=C

D1

=15

P

F

∗

2

)

Typ.

* Item

Operating temperature T

Symbol a

Condition

V

DD

=2.7

to 3.6V

V

DD

=1.9

to 2.2V

V

DD

=1.8

to 2.2V

∗

1 Q11C02RX: Crystal resonator made by Seiko Epson

∗

2 "C

G1

=C

D1

=15pF" includes board capacitance.

Min.

-40

-40

0

Max.

85

85

70

Unit

°

C

°

C

°

C


∗

1

, V

DD

=3.3V, V

SS

=0V, crystal=C-002RX

∗

1

C

G1

=C

D1

=1

0

P

F, Rf

1

=20M

Ω

, Ta=25°C)

Min.

Typ.

Item Symbol Condition

Oscillation start time

External gate/drain capacitance

Frequency/IC deviation t

STA1

C

G1

, C

D1 f/IC

Frequency/power voltage deviation f/V

Frequency adjustment range f/C

G

C

G

=15pF

C

G

=5 to 25pF

*1 Q11C02RX: Crystal resonator made by Seiko Epson

*2 "C

G1

=C

D1


5

-10

-10

50

Max.

3

25

10

10

Unit sec pF ppm ppm/V ppm

*


∗

1

, V

DD

=2.0V, V

SS

=0V, crystal=C-002RX

∗

1

C

G1

=C

D1

=10

P

F, Rf

1

=20MW, Ta=25°C)

Min.

Typ.

Item


External gate/drain capacitance

Frequency/IC deviation

Symbol t

STA1

C

G1

, C

D1 f/IC

Condition

Frequency/power voltage deviation

Frequency adjustment range f/V f/C

G

C

G

=15pF

C

G

=5 to 25pF

∗

1 Q11C02RX: Crystal resonator made by Seiko Epson

*2 "C

G1

=C

D1


5

-10

-10

50

Max.

3

25

10

10

Unit sec pF ppm ppm/V ppm

*



EPSON 49


OSC3 crystal oscillation

Note: A "crystal resonator that uses a fundamental" should be used for the OSC3 crystal oscillation circuit.


SS

=0V, crystal=MA-306

∗

1

, 33.8688MHz, Rf

2

=1M

Ω

, C

G1

=C

D1

=15pF

∗

2

, Ta=25°C)

Min.

Typ.

* Item


Symbol t

STA3

V

DD

=3.3V

V

DD

=2.0V

*1 Q22MA306: Crystal resonator made by Seiko Epson

*2 "C

G1

=C

D1


Condition Max.

10

25

Unit ms ms

OSC3 ceramic oscillation

Item


Symbol t

STA3

Condition

10MHz ceramic oscillator






SS

=0V, T a

=25°C)

Min.

Typ.

* Max.

10

10

10

5

5

Unit ms ms ms ms ms

Note: No.

Ceramic oscillator

1 CST10.0MTW

2 CST16.00MXTW0C1

3 CST20.00MXTW0H1

4 CST25.00MXW0H1

5 CST33.00MXZ040

Recommended constants

C

G2

(pF) C

D2

(pF) Rf

2

(ΜΩ)

30 30 1

5

5

5

Open

5

5

5

Open

*1 This oscillator has a tendency to rise to the frequency of 0.3%.

1

1

1

1

Power voltage range (V)

1.8 to 2.2

1.8 to 2.2

1.8 to 2.2

2.7 to 3.6

2.7 to 3.6

Remarks

(Murata Mfg. corporation) *1

(Murata Mfg. corporation)







2.6.6.8

PLL Characteristics

Setting the PLLS0 and PLLS1 pins (recommended operating condition)

V

DD

=2.7V to 3.6V

PLL

1

0

0

PLLS0

1

1

0

Mode

×2

×4

PLL not used

Fin (OSC3 clock)

10 to 25MHz

10 to 12.5MHz

–

Fout

20 to 50MHz

40 to 50MHz

–

V

DD

=2.0V ± 0.2V

PLLSL

1

0

PLLS0

1

0

Mode

×

2

PLL not used

Fin (OSC3 clock)

10MHz

–

Fout

20MHz

–

PLL characteristics


DD

=2.7V to 3.6V, V

SS

=0V, crystal oscillator=SG-8002

∗

1

, R

1

=4.7k

Ω

, C

1

=100pF, C

2

=5pF, T a

=-40 to +85°C)

Item Symbol

Jitter (peak jitter)

Lockup time t pj t pll

∗

1 Q3204DC: Crystal oscillator made by Seiko Epson

Condition Min.

-1

Typ.

Max.

1

1

Unit ns ms

*


DD

=2.0V±0.2V, V

SS

=0V, crystal oscillator=SG-8002

∗

1

, R

1

=4.7k

Ω

, C

1

=100pF, C

2

=5pF, T a

=-40 to +85°C)

Item Symbol

Jitter (peak jitter)

Lockup time t pj t pll

∗

1 Q3204DC: Crystal oscillator made by Seiko Epson

Condition Min.

-2

Typ.

Max.

2

2

Unit ns ms

*



EPSON 51

3 C33 Test Functions

Chapter 3 C33 Test Functions

3.1 Test Function Overview

The C33 macros provide an extensive set of test modes for testing and pre-shipment inspection of the

C33 CPU core, I/O, and user circuits. Of these, the following two test modes are provided for use by the user. Note that the test mode is set up by the four pins P_TST, P_RESETX, P_X2SPD, and

P_EA10M0, which are C33 macro required pins.

(1) DC/AC test mode (TST_DCT mode)

This mode allows the testing of all I/O pins to be controlled from the test input pins, and makes

DC/AC testing easy to perform. The C33 macros include the TCIR test circuit, which is recommended for the S1X50000 Series, and XACPI, which is used for AC path measurement.

DC/AC testing uses the TCIR and XACPI functions. The following 4 DC/AC tests can be performed by using the C33 macro built-in TCIR circuit.

a. DC tests

1. Quiescent current drain measurement

2. Output characteristics (V

OH

/V

OL

) measurement

3. Input logic level validation

b. AC test

1. Special-purpose AC path measurement

(2) User circuit test mode (TST_USER mode)

In this test mode, addresses, data, read, write, chip enable, and data bus direction control functionality can all be controlled directly from pads. This mode allows to access user circuit internal registers.

Note that the C33 system clock stops in this test mode.




3.2 DC/AC Test Mode (TST_DCT mode)

3.2.1 Procedure to Enter Test Mode

Use the following procedure entering test mode.

(1) With P_RESETX = 0 and P_TST = 0, input at least 4 clock cycles from P_OSC3 to stabilize the C33 macro internal state. After that, set P_TST to 1.

(2) With P_RESETX = 0 and P_TST = 1, input 4 rising edges on the P_X2SPDX signal, which is stable signal in normal mode.

(3) Set P_RESETX to 1. At this transition, C33 mode is determined to DC/AC Test Mode, the

C33 internal signal tst_dct will switch from low to high. (The tst_dct signal being at the high level indicates that the IC in DC/AC Test Mode.)

Note that the tst_dct signal can be monitored by AAA.tst_dct.

Note 1: AAA is the instance name of the C33 macro.

Note 2: Since it is possible for the chip to switch to another mode, be sure to hold all input pins that can affect the initial state fixed at either the high or low level.

The following pins must be held fixed: P_NMI_X, P_EA10M0, P_EA10M1,

P_EA10M2, P_DSIO, P_PLLS0, P_PLLS1, and P_OSC1. In particular, the

P_NMI_X and P_DSIO must be held at their inactive state, namely the high level.

P_TST

P_RESETX

P_X2SPDX

AAA.tst_dct

P_OSC3

Input of at least 4 clock cycles

Figure 3.1 Transition to Test Mode

DC/AC

Test mode



EPSON 53


In the DC/AC test mode, the user I/O cells are controlled by the C33 macro user pin internal signals, namely the TST_TA, TST_TE_X, and TST_TS signals. Note that when P_TST is high, the I/O pullup/pull-down resistors are set to the inactive state.

The control and output pins function as follows in this test mode.

External pin

P_X2SPDX

P_EA10M1

P_EA10M0

P_A1

P_BCLK

Table 3.1 DC/AC Test Mode External Pin Functions

I/O

In

In

In

Out

Out

Function

The TCIR IP0 pin

The TCIR IP1 pin

The TCIR IP2 pin

Output pin for the special-purpose AC path measurement mode

Output pin for input logic level verification mode

Table 3.2 Test Mode Signals for DC/AC Test Mode

Macro internal signal tst_dct

I/O

Out

Function

Goes to 1 when the chip enters DC/AC test mode

Measurement Mode Descriptions (The following descriptions are identical to those provided in the

S1L50000 SERIES DESIGN GUIDE.)

1) Quiescent current drain measurement mode

• High-impedance mode: bidirectional pins function as inputs, and 3-state outputs go to the high-impedance state.

P_X2SPDX (IP0) ... Fixed at the high level

P_EA10M1 (IP1) ... Fixed at either high or low (Either can be selected.)

P_EA10M0 (IP2) ... Fixed at the high level

• Output mode: both bidirectional pins and 3-state output pins go to the output state.

P_X2SPDX (IP0 ... Fixed at the high level


P_EA10M0 (IP2) ... Fixed at the low level

2) Output characteristics (V

OH

/V

OL

) measurement mode


P_EA10M1 (IP1) ... High level or low level input

This input state is output to all output cells and bidirectional cells (if

EA10MD0 is low).

P_EA10M0 (IP2) ... Controls the bidirectional pin mode.

High ... High-impedance (input) mode

Low ... Output mode




3) Input logic level verification mode




P_BCLK

Test pins ... High or low level input

... Outputs a high or low level.

4) Special-purpose AC path measurement mode

P_X2SPDX (IP0) ... Fixed at the low level

P_EA10M1 (IP1) ... Data (high or low level) input


P_A1 ... Data (high or low level) output (the state of P_EA10M1)

<APF Format Example>

$RATE

$STROBE

$RESOLUTION

100000

85000

0.001ns

$NODE

P_RESETX

P_X2SPDX

P_TST

P_OSC3

P_EA10M1

IU 0

I 0

ID 0

P 20000 50000

IU 0

P_EA10M0 I

P_BCLK O

P_A1 B

P_D15

P_D14

P_D13

P_D12

P_D11

P_D10

P_D9

P_D8

P_D7

P_D6

P_D5

P_D4

P_D3

P_D2

P_D1

P_D0

BIO1

OUT1

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

0

0

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

75000

0

OUT1

$ENDNODE

0



EPSON 55


$PATTERN

#

#

#

#

#

#

#

#

#

#

#

#

PPPPPPPPPPPPPPPPPPPPPPPPBOO

________________________IUU

RXIOEEBADDDDDDDDDDDDDDDDOTT

E2CSAAC11111119876543210112

SSEC11L 543210

EPM300K

TDD MM

XX 10

IIIPIIOBBBBBBBBBBBBBBBBBBOO

U D U

0 000P00LXXXXXXXXXXXXXXXXXHLX

1 000P00LXXXXXXXXXXXXXXXXXHLH

2 000P00LL0000000000000000HLH

3 000P00LL0000000000000000HLH

4 001P00L000000000000000000ZL

5 001P00L000000000000000000ZL

6 011P00L000000000000000000ZL

7 001P00L000000000000000000ZL

Test mode input sequence

8 011P00L000000000000000000ZL

9 001P00L000000000000000000ZL

10 011P00L000000000000000000ZL

11 001P00L000000000000000000ZL

12 001P00L000000000000000000ZL

14 111P00XLLLLLLLLLLLLLLLLLLLL

15 111P11X000000000000000000ZH

20 111P01X000000000000000000ZH

25 111P10XHHHHHHHHHHHHHHHHHHHH


Quiescent current drain measurement (Bidirectional pins in input mode and 3-state pins in the high-impedance state)

Quiescent current drain measurement (Bidirectional pins and 3-state pins in output mode)


36 111P11X000000000000000000ZH Output characteristics (V

OH

/V

OL

) measurement

40 111P11XHHHHHHHHHHHHHHHHHHZH

41 111P10XHHHHHHHHHHHHHHHHHHHH ⋅⋅⋅⋅⋅⋅ All outputs: high level


46 111P11X000000000000000000ZH

47 111P01X000000000000000000ZH

50 111P01X000000000000000000ZH


⋅⋅⋅⋅⋅⋅ All outputs: low level


57 111P11X000000000000000000ZH

60 111P11X000000000000000000ZH



68 101P01XLHHHHHHHHHHHHHHHHHHH







88 111P11X000000000000000000ZH

Special-purpose AC path measurement

(Used to measure the delay from P_EA10M1 to

P_A1.)

90 111P11X000000000000000000ZH

93 111P11H000000000000000000ZH

95 111P11H000000000000000000ZH

98 111P11L000000000000000000ZH

100 111P11L000000000000000000ZH

103 111P11H000000000000000000ZH

105 111P11H000000000000000000ZH

Input logic level verification (Created by Seiko

Epson.)

Monitors the high/low level inputs to a certain input pin from the P_BCLK pin.

(This cannot be simulated.)




$ENDPATTERN

#

# EOF

108 111P11L000000000000000000ZH

110 111P11L000000000000000000ZH

113 111P01L000000000000000000ZH

115 111P11H000000000000000000ZH

118 111P01H000000000000000000ZH

120 111P01H000000000000000000ZH

123 111P01L000000000000000000ZH

125 111P01L000000000000000000ZH

128 111P01H000000000000000000ZH

130 111P01H000000000000000000ZH

133 111P01L000000000000000000ZH

135 111P01L000000000000000000ZH

140 111P01L000000000000000000ZH

Since this example is the result of simulating forcing high/low data on the XITST1 (P_TST)

LG pin, the high/low state can be verified from the

P_BCLK pin.



EPSON 57


58

Figure 3.2 Sample Pattern Waveforms



3.3 User Circuit Test Mode (TST_USER mode)


3.3.1 Procedure to Enter Test Mode

The following presents the procedure entering test mode.

(1) With P_RESETX = 0 and P_TST = 0, input at least 4 clock cycles from P_OSC3 to stabilize the C33 macro internal state. After that, set P_TST to 1. After that, system clock input is disabled internally in the C33 macros.

(2) With P_RESETX = 0 and P_TST = 1, input 1 rising edge on the P_EA10M0 signal, which is stable signal in normal mode. At this transition, C33 mode is determined to User Circuit

Test Mode, the TST_USER macro pin will switch from low to high.

(The TST_USER signal being at the high level indicates that the IC in User Circuit Test

Mode.)

(3) Set P_RESETX to 1.

Caution: Since it is possible for the chip to switch to another mode, be sure to hold all input pins that can affect the initial state fixed at either the high or low level. The following pins must be held fixed: P_NMI_X, P_X2SPD, P_EA10M1,

P_EA10M2, P_DSIO, P_PLLS0, P_PLLS1, and P_OSC1. In particular, the

P_NMI_X and P_DSIO must be held at their inactive state, namely the high level.

P_TST

P_RESETX

P_EA10M0

TST_USER

P_OSC3

Input of at least 4 clock cycles

TST_USER mode

Furthermore,

C33 system clock input is disabled.

Figure 3.3 Transition to User Circuit Test Mode



EPSON 59


3.3.2 Test Mode

In user circuit test mode, the clock, address, data, read, write, chip enable, and data bus direction control signals can be controlled from external pins. This allows direct control of user circuits without using C33 CPU operation.

The external pins function as follows in this test mode.

Table 3.3 User Circuit Test Mode External Pin Functions

External pin I/O

P_A[17:0] In

Macro pin

U_ADDR[17:0] Address input

Function

P_RD_X

P_WRL_X

P_WRH_X In U_WRH_X

P_X2SPDX In -

P_D[15:0]

In U_RD_X

In U_WRL_X

I/O

Read signal

Low byte write signal

High byte write signal

Data bus direction control: 1: Read (output), 0: Write (input)

U_DOUT[15:0] Data input in write mode

U_DIN[15:0] Data output in read mode

P_CE10EX In U_BCLK Clock input

U_OSC1CLK (In user circuit test mode, all 5 pins function as P_CE10EX input.)

U_OSC3CLK

U_PLLCLK

U_BCUCLK

U_PERICLK

Table 3.4 Test Mode Signals in User Circuit Test Mode

Macro pin

TST_USER

I/O Function

Out Goes to 1 when the IC enters user circuit test mode.

Caution: In user circuit test mode, system clock supply is stopped since the C33 core block is stopped. Therefore, the test clock (P_CE10EX) must be used for clock supply to the user circuit block in user test mode.

MUX

Test clock

(P_CE10EX)

System clock

1

0

S

TST_USER

(Test mode signal)

User clock

U_BCLK

U_OSC1CLK

U_OSC3CLK

U_PLLCLK

U_BCUCLK

U_PERICLK

Figure 3.4 Clock Supply in User Circuit Test Mode




Caution: Provide the chip enable signal to the user circuit as shown below.

U_P3_PIN[5:0]

U_P2_PIN[7:0]

U_P1_PIN[6:0]

U_P0_PIN[7:0]

U_K5_PIN[4:0]

Arbitrary signals

U_CEx_X x: 4,5,6,7,8,9

TST_USER

1

MUX

0

S

To the user circuit

Figure 3.5 Creating the Chip Enable Signal Supplied to the User Circuit



EPSON 61

4 Special Operations in ASICs that Include C33 Macros

Chapter 4 Special Operations in ASICs that Include

C33 Macros

This chapter describes certain special operations that arise when developing ASICs that include C33 macros in the S1X50000 Series. Refer to the S1L50000 SERIES DESIGN GUIDE for information not provided in this chapter.

4.2 Verifying the C33 Macro Specifications

In the verification stage for ASICs that include C33 macros, the customer must verify the following items in advance. Seiko Epson releases the C33 macro library based on these specifications.

1) C33 macro module selection

Refer to section 2.1, "Overview," and inform us of which modules will be used, whether or not internal RAM/ROM is used, and other items.

2) C33 option pad selection

Refer to section 2.3, "C33 Macro Pins," and inform us which, if any, of the C33 optional pins are not required.

3) C33 user pin selection

Refer to section 2.3, "C33 Macro Pins," and inform us which, if any, C33 optional pads must be provided as C33 pins (internal signals) with the same function.

4) C33 macro pin I/O cell type selection

Refer to section 2.3, "C33 Macro Pins," and the "S1L50000 SERIES MSI Cell Library" document, and inform us of the C33 macro pin I/O cell types.




4.3

Verifying the Constraints on the Pin Arrangement

The chip floorplan will differ depending on the chip size and the C33 macro modules selected. The following constraints on the pin arrangement arise due to these variations. Please consult your Seiko

Epson ASIC representative when verifying the pin arrangement.

4.3.1 Constraints on PLL, Low-speed, and High-speed Oscillator

Circuit Pins

The positions of the PLL pin (P_PLLC) and the two high-speed oscillator circuit pins (P_OSC3 and

P_OSC4) depend on the layout of the C33 macros. The positions of the low-speed oscillator circuit pins (P_OSC1 and P_OSC2) depend on the position of the low-speed oscillator circuit. These pins should be flanked by either power supply pins or, at least by input pins whose values do not change.

(Refer to the example shown in figure 4.1.)

4.3.2 Constraints on A/D Converter Pins

The positions of the analog power supply (AV

DD

) and analog input pins (P_K60 to P_K67) depend on the position of the A/D converter macro. While the A/D converter macro can be moved up, down, left, or right on the chip, there are cases where its position is constrained by the size of the chip and the positions of other macros. The power supply (AV

DD

) for the A/D converter macro and the A/D converter I/O cells is isolated from the other power supplies (HV

DD

and LV

DD

). I/O cells for the separate power supply flank the A/D converter I/O cells. This means that pins other than A/D converter pins must not be located in the AV

DD

area. (Refer to the example shown in figure 4.1. Note that only the V

DD

system is a separate power supply and that V

SS

is shared.)

4.3.3 Number of Power Supply Pins

Refer to the S1L50000 SERIES ASIC DESIGN GUIDE for details on the number of power supply pins.

4.3.4 Floorplan

Figure 4.1 presents an example of the floorplan for a device for which all of the blocks (C33_CORE,

C33_DMA, C33_ADC, and C33_PERI) have been selected. Note that this figure is an example of a floorplan, and does not indicate the relationships between the sizes of the blocks and I/O areas. As a result, the actual sizes of the blocks and I/O areas on the chip differ from those shown.



EPSON 63


VSS

P_PLLC

VSS

HVDD

P_OSC3

P_OSC4

VSS

C33_CORE

User circuits

C33_DMA C33_ADC

C33_PERI

VSS

P_OSC1

P_OSC2

HVDD

Figure 4.1 Sample Floorplan and Pin Constraints




4.4 Connections between User I/O, User Circuits, and C33

Macros

4.4.1 Connections between C33 Macros and User Circuits

The connections between C33 macros and user circuits are handled by connecting the required pins as desired from the C33 macro user pins. Since the user pins can be controlled from external pins in user circuit test mode, there is no need to add special test circuits.

4.4.2 Connections between C33 Macros and User I/O

As a basic policy, I/O with built-in test functions is used for user I/O, and the user I/O is connected to the C33 macros as listed in the table below. This connection method allows the DC/AC test mode functions provided by the C33 macros to be used. This means that there is no need to add DC/AC test circuits in the user circuits.

C33 macro pins

TST_USER

TST_TA

TST_TE_X

TST_TS

Usage

Use this signal to set user circuits to the test state.

Connect this signal to the I/O cell TA pin.

Connect this signal to the I/O cell TE pin.

Connect this signal to the I/O cell TS pin.

4.4.3 Notes on the Use of 5 V Tolerant I/O Cells

Note that since there are no I/O cells with built-in test functions in the S1X50000 Series 5 V tolerant

I/O cells, the C33 macro DC/AC test mode cannot be used. If these cells are used, the user must provide the following test patterns for the pins that use the 5 V tolerant I/O cells.

A. Input logic level verification: Test patterns in which all inputs transition from the

0 to 1 state, and patterns in which all inputs transition from the 1 to 0 state.

B. Output characteristics (V

OH

/V

OL

): Test patterns for which all outputs transition from the low to high levels, and patterns in which all outputs transition from the high to low levels.

C. Bidirectional pins: Test patterns which meet both conditions A and B above.



EPSON 65


4.4.4 Connections between C33 Macros and User I/O

Figure 4.2 shows examples of connections between C33 macros and user circuits and user I/O.

User circuit

A

E

TA

TE

TS

A

E

TA

TE

TS

BIO1

OUT1

P_X2SPD

P_EA10M1

P_EA10M0

P_TST

A

TA

TS

XITST1

IP0

TCIR

TA

Test circuit

TST_TA

IP1 TE TST_TE_X

IP2

TST

VTI

TS

ACO

VTO

TST_TS

C33 macro

A

TA

TS

A

E

TA

TE

TS

P_A1

P_BCLK

Figure 4.2 Example of Connection Between C33 Macros and User I/O

OUT2




4.5

Test Pattern Creation

4.5.1 DC/AC Test Pattern Creation

Of the DC/AC test items, the user must create all the test patterns except the input level verification test. Refer to section 3.2, "DC/AC Test Mode," in this document and the S1L50000 SERIES DESIGN

GUIDE for more information on test pattern creation.

4.5.2 C33 Macro/User Circuit Connection Verification Test Pattern

Creation

While the test patterns for verifying user circuit functionality must be created to operate in user circuit test mode, in addition to this functional verification, the user must also create test patterns to verify the connections between the C33 macros and the user circuits. These connection verification test patterns must be created in accordance with the contents of chapter 5, "Simulation," in this document.

These test patterns must include patterns that operate the C33 blocks and access the user circuits, as well as patterns that can observe, from outside the IC, all signals that connect C33 macros to user circuits. Below, we present the flowchart for an example of verifying connection of the address, data, chip enable, read, and write signals that connect to the user circuits.

(1) Set up the areas allocated for user circuits internal access by setting the BCU register.

(Set an arbitrary bit in 0x48132/D[F:8] to 1.)

↓

(2) Write an arbitrary data value to an arbitrary register in the user circuits.

↓

(3) Read out the register written in step (2).

↓

(4) Write the read data to an arbitrary address in an external area that does not exist on the chip.

Verify the following signals during the above sequence.

(2) Verify the address (U_ADDR), data (U_DOUT), chip enable (U_CEx_X), and write

(U_WRL_X/U_WRH_X) connections.

(3) Verify the address (U_ADDR), data (U_IN), chip enable (U_CEx_X), and read (U_RD_X) connections.

(4) The read data is output from P_D[15:0] by writing that read data to an external area. These values are then the expected values for the test pattern.



EPSON 67

5 Simulation

Chapter 5 Simulation

5.1

Design Flowchart

68

Figure 5.1 Design Flowchart


EMBEDDED ARRAY SSL50000 SERIES

5 Simulation

External memory model

(SRAM,DRAM)

Verilog netlist C33 MACRO

C33 ASM code

Test bench creation script

C33 Assembler

LST2ROM

Stimulus

ROM code

Test Bench

Verilog-XL

EPSON Lib

Waveform display file

Trace file

Figure 5.2 Simulation Flowchart

Simulation condition

T0 timing

Forward Annotation

Back Annotation

Table 5.1 Simulation Conditions

C33 hard macros

(CPU core, DMA)

No SDF

Assumed wiring SDF

Post-layout SDF

User logic, C33 soft macros

No SDF

Assumed wiring SDF

Post-layout SDF

Note: Current there is only a gate level simulation model.



EPSON 69

5 Simulation

5.2

System Level Simulation

CC33

Personal computer

C compiler

Assembler

Linker

Workstation

Simple assembler

AS33 An assembler-based evaluation program is loaded into ROM.

C33 custom microcontroller model

ROM RAM

ASIC and other technologies

Verilog simulator

Figure 5.3 System Level Simulation

5.3

Test Pattern Creation

When the logic design is complete, the next step is test pattern creation. Test patterns are not only used in simulation to verify operation of the circuit design, but are also used in product pre-shipment inspection.



5 Simulation

5.4

Simulation Environment

5.4.1 Operating Environment

The standard simulation environment that Seiko Epson supports with the C33 product consists of the following. Contact your Seiko Epson representative for details on using other environments.

Machine : Sun workstation

OS: Solaris 2.5.1 or 2.6

Verilog : Verilog-XL 2.6 or later

5.4.2 Installation Procedure

The C33 simulation environment is provided on CD-ROM.

Create the direct for installation and define "C33" as an environment variable with that directory as its value. Execute the script "c33_install.csh" from the CD-ROM to install the environment.

csh> mkdir {install directory} csh> setenv C33 {install_directory} csh> cd {CD-ROM directory} csh> c33_install.csh

The directory structure will be as follows after the installation.

$C33/bin

$C33/lib

$C33/lib/C33_lib

$C33/lib/Megacell

$C33/lib/Epsonlib

$C33/sim

$C33/sim/asm

$C33/sim/verilog

$C33/sim/verilog/ENV

$C33/sim/verilog/ENV/bin

Tool directory

Library directory

C33 library

Megacell library

Gate array cell library

Simulation directory

C33 assembler program

Verilog simulation

Verilog environment

Verilog startup tool

$C33/sim/verilog/ENV/tb Test bench components (C33)

$C33/sim/verilog/ENV/user_tb Test bench components (user)

$C33/sim/verilog/Sample Sample simulation directory

$C33/sim/verilog/Sample/t0 t0 delay simulation environment

$C33/sim/verilog/Sample/ba Back annotation environment



EPSON 71

5 Simulation

The C33 macro net list consists of the hard macros, the soft macros, and the I/O cells used. The libraries shown above include a sample that forms the S1C33208, which is a general-purpose model in the

C33 Series that uses the C33 macros. Seiko Epson provided hard macros are included in the megacell library.

5.5

Running a Simulation

5.5.1 Preparing for Simulation

The following setup is required prior to executing a simulation.

1) Define the C33 environment variable to point to the install directory.

2) Set up your system so that the verilog command runs the Verilog simulator.

csh> verilog

:

VERILOG-XL 2.8

Valid host command options:

-f <filename> read host command arguments from file

:

:

3) Edit the environment setup file as required.

The file $C33/bin/SETUP performs the settings required in the C33 simulation environment.

5.5.2 Sample Simulation Execution

The following procedure executes the sample simulation.

csh> cd $C33/sim/verilog/Sample/t0 csh> mv trc trc_back csh> ./qa_sample.csh

The results of the simulation will be stored in the following directory. Compare the results here to the backed up results in the trc_back directory.

$C33/sim/verilog/Sample/t0/trc/sample/...

Output directory sample_f10emux1.log: Log file sample_f10emux1.tb: sample_f10emux1.trc:

Test bench file

Trace output file



5 Simulation

5.5.3 Simulation Execution Script

The C33 simulation is executed by the following script.

$C33/sim/verilog/Sample/t0/verilog.boo

$C33/sim/verilog/Sample/t0/qa_sample.csh

$C33/sim/verilog/ENV/bin/c33_sim.csh

The file verilog.boo

is a shell script that sets up the Verilog simulator startup command options and actually starts the Verilog simulator.

The file qa_sample.csh

is a script that prepares to manage the operations associated with running the simulation using the file c33_sim.csh

.

The file c33_sim.csh

executes the following sequence of operations.

• Generates the C33 machine language code that is read into the Verilog ROM model.

• Generates the test bench for the Verilog simulation.

• Starts the Verilog simulator using the verilog.boo

file.

Format of the file c33_sim.csh c33_sim.csh ASM file [option...]

ASM_file: Name of the C33 assembler program file

The following options can be used.

(There must be no spaces around the equal signs ( = ) in the options.) trc=file : Specifies the name of the file to which the trace results are output.

cycle=n tcyc=n tb=file incl=file debug

: Specifies the number of simulation execution cycles.

: Specifies the cycle time for the simulation. (Units: ns)

: Specifies a test bench component file. This option may be used multiple times.

: Specifies a file that lists test bench component files. This option may be used in conjunction with the tb= option. This option may be used multiple times.

: Used to debug the test bench environment. The verilog.boo

file is not run if this option is specified.



EPSON 73

5 Simulation

Example 1) Normal simulation csh> c33_sim.csh sample.asm trc=test1 tcyc=100 cycle=300 tb=abc.tb tb=def.tb

The file sample.asm

is input and executed at 10 MHz (10 ns) for 300 cycles. The files abc.tb

and def.tb

are added to the test bench. The output file is ./trc/sample/ test1.trc

.

A directory with the same name as the ASM_file is created in the trc directory, and the results of the Verilog simulation are stored in a file with the name specified with the trc= option.

Example 2) Debug simulation csh> debug_sample.csh

>>> verilog debug files copied to directory --> ./samplex_f10emux1

>>> edit test bench samplex_f10emux1.tb

>>> run verilog with following command source $C33/bin/SETUP cd samplex_f10emux1 verilog.boo samplex_f10emux1.tb

The debug_sample.csh

file consists of the qa_sample.csh

file with the debug option added. In this case, a directory with the same name as the ASM_file is created, and the files necessary for simulation are set up. To execute a Verilog simulation, execute the Source of the SETUP file, switch to the generated directory, and execute verilog.boo

with the test bench as the argument.

5.5.4 Test Bench Structure

The test bench consists of the assembled test bench component files specified by the "tb=" and

"incl=" options to the c33_sim.csh

script. Directories are searched in the following order to find these files.

(1) The tb directory where the simulation is performed.

(2) The user shared test bench in $C33/sim/verilog/ENV/user_tb

(3) The C33 shared test bench in $C33/sim/verilog/ENV/c33_tb

If multiple files with the same name exist in two or more of the above directories, the first file found by the search procedure will be used.

When c33_sim.csh

generates a test bench, it uses the "//_ _" format (two forward slashes and two underscores) in places where component files are used as test benches.

The locations of the files can be displayed easily by using grep to search for the test bench files.



5 Simulation csh> grep //_ _ samplex_f10emux1.tb

//_ _.../sim/verilog/ENV/tb/header.tb

//_ _.../sim/verilog/ENV/tb/c33_chip.tb

//_ _.../sim/verilog/ENV/tb/pll_00.tb

//_ _.../sim/verilog/ENV/tb/c33_init.tb

//_ _.../sim/verilog/ENV/tb/osc1_5MHz.tb

//_ _.../sim/verilog/ENV/tb/mode_x1spd.tb

//_ _.../sim/verilog/ENV/tb/ea10md_00.tb

//_ _.../sim/verilog/ENV/tb/ea3md_0.tb

//_ _.../sim/verilog/ENV/tb/mode_normal.tb

//_ _.../sim/verilog/ENV/tb/top1.tb

//_ _.../sim/verilog/Sample/t0/tb/cpu_trace.tb

( "..." indicates the actual installation directory.)

The c33_sim.csh

script replaces the character string "TRACE_FILE" in the test bench with the name of the output file name specified by tb = option . Therefore, it is possible to output a trace file or a waveform file with the name of the output file using a common test bench component file.



EPSON 75

5 Simulation

5.6

Evaluation Program Creation

5.6.1 asm33 Assembler Prototype

The procedure for using the asm33 assembler prototype and limitations on its use are described below.

Other issues follow the contents of the S1C33 Family C Compiler Package Manual. Refer to that manual for more information.

(1) Running asm33

After executing $C33/bin/SETUP , enter the following command.

csh > asm33 <source file>

Input file: source file

Output lst file: (

*

.lst)

Example: asm33 test.asm

This creates the file test.lst

.

When this command is executed, the following message is output to standard output, and the

LST file ( *.lst

) is created in the current directory.

Assembler33 Rev1.4 ( Proto )

Copyright (C) SEIKO EPSON CORP. 1995

When the assembly completes without error, the following message will be output to standard output.

Assembler complete.

If an assembly error occurs, the source file, line number, and error information will be output to standard output.

The following message will be output to standard output if the argument is missing or if multiple file names are specified.

Usage: asm33 filename filename:Assembler source file

Output:

Listing file (.lst)

Example: asm33 test.asm



5 Simulation

(2) Limitations on registers, values, and labels

• Character set

There are 3 delimiters: space, tab and comma .

If the first character is:

.

; Pseudoinstruction

0x[0-9a-fA-F]* ; Number a-z,A-Z,_ ; Label instruction

; ; Comment

A single line can hold any one of label definition (label:), instruction, or pseudoinstruction.

Only lower case letters may be used in instruction and register names.

Both upper and lower case may be used in labels.

%rs, %rd, %ra, %rb : General-purpose registers (%r0, %r1, %r2 --

%r15)

%ss, %sd, %sp : Special-purpose registers

%ahr)

(%sp, %psr, %alr, immediate

LABEL@rh

LABEL@rm

LABEL@rl values : 0x0-0xffffffff (hexadecimal only)

: bit22-31[12:3] For jp,call,jrcc instructions

: bit9-21 For jp,call,jrcc instructions

: bit1-8(sign9[8:1] ) For jp,call,jrcc instructions

(3) Allowed pseudoinstructions

.org imm32

.half imm16

: Address specification, only for increasing values of the address

: 16-bit data

(4) Limitations

1) Only a single source file can be assembled.

2) Labels cannot be used with instructions other than jp,call and jrcc .

3) Of the extended instructions, only the 32-bit immediate value load instructions can be used.

Example: xld.w %r0,0xabcd1234

4) Jump instructions that require an immediate value extended instruction must be coded as following order. (A syntax error results if this is not obeyed.) extLABEL@rh extLABEL@rm extLABEL@rm -orjp LABEL@rl jpLABEL@rl



EPSON 77

5 Simulation

5) Jump instructions that require an immediate value extended instruction must be coded successively after the extended instruction. (A syntax error results if this is not obeyed.) ext LABEL@rh ext LABEL@rm jp LABEL@rl

× ext LABEL@rh ext LABEL@rh

[Other instruction] -orext LABEL@rm ext LABEL@rm [Other instruction] jp LABEL@rl jpLABEL@rl

6) The maximum number of lines per source file is 65536 lines.



6 Board Development

Chapter 6 Board Development

6.1

Development Environment

S5U1C33000C

Serial/parallel

EPSON

S5U1C330M1D1

I/F board 33 chip S5U1C330M2S

Serial

4, 10 pins

S5U1C33XXXE

User target board

S5U1C33000H

User target board

Figure 6.1 S1C33 Software Development Environment



EPSON 79

6 Board Development

•

Host computer

• Personal computer running Windows 95, 98, or NT

•

Software tools

• S5U1C33000

- Provides tools from a C compiler to a debugger

•

Hardware and debugging tools

• S5U1C33000H (Minimal pin count ICE)

- Support for C33 model 2 or later

• S5U1C330M2S and S5U1C330M1D1

- Provides a simple debugging environment

• S5U1C33XXXE

- Adapter board used during ASIC design

The following development software is also available.

•

Real-time OS

• S5U1C330R1S

- Conforms to the ITRON 3.0 specifications

•

Middleware

• S5U1C330V2S

- Audio compression and expansion. Supports a variety of compression types, from

ADPCM to original techniques. Conversation speed modification software is also supported.

• S5U1C330V2S

- Voice recognition engine

• S5U1C330J1S

- Supports JPEG compression and expansion

• S5U1C330M1S, S5U1C330S1S

- Supports music performance, from simplified PWM playback to WAVE sound source playback.

•

Demonstration boards and other items

• S5U1C33104D1, S5U1C33208D1, S5U1C33041D1

- Evaluation boards that can evaluate the above set of middleware with the 33A104 and 33209.

• FLS33(provided with the C33 version 2)

- Utility that allows AMD and Intel type flash memory to be erased and written from the debugger



6 Board Development

S1C332XX

EPGA or

Gate Array

Fast SRAM X 16bit

ACC = 15 ns

S1C332XX

Others

Fast SRAM X 8 bit

ACC = 15 ns

During hardware and software development

SRAM Flash

Others

For mass production

User target board

IC With S1C33 macro

PAD Pattern

Figure 6.2 S5U1C33XXE QFP Interface



EPSON 81

6 Board Development

6.2

Evaluation Board Design

ES samples

Determination of the C33 ASIC product package specifications

EPOD design

Circuit design

Manufacturing

Target development

Circuit development

Manufacturing

OR

Evaluation board development

Circuit development

Manufacturing

Functional verification in an actual end product

Issuing as ROM

Figure 6.3 Board Development Flowchart



6 Board Development

(1) Board development process (example 1)

Step 1: Determine the C33 ASIC product package and pin arrangement.

Step 2: Perform performance and user circuit evaluation by creating a target board (mass production version), and, at the same time, creating an EPOD board with an FPGA by using a C33209 (a general-purpose product). Also, start software development.

Step 3: Design and manufacture the C33 ASIC product.

Step 4: Mount the C33 ASIC product in the target board, verify software operation, and perform final evaluation.

Step 5: Release to production.

S5U1C33XXXE that includes an FPGA and provides a QFP interface

Target board (mass production version)

S1C33 CPU, BCU basic peripheral functions, and internal RAM

During board and software development

S1C33209 or else

FPGA

SRAM

Flash

Internal ROM emulation others

QFP I/F

Pad pattern for the IC with internal S1C33 macros

ROM. RAM, flash memory, G/A, and other devices

For mass production

C33 ASIC manufacturing

C33 ASIC product

Figure 6.4 Board Development Structure (Example 1)



EPSON 83

6 Board Development

(2) Board development process (example 2)

Use the following procedure when the package and pin arrangement cannot be determined initially.

Step 1: Create an evaluation board using the C33209 (general-purpose product), FPGA, and the required memory. Evaluate the performance and the FPGA circuit. Also, start software development at this time.

Step 2: Create the target board (mass production version), and at the same time design and manufacture the C33 ASIC.

Step 3: Mount the C33 ASIC on the target board, verify software operation, and perform final evaluation.

Step 4: Release to production.

Target board (evaluation version)

ROM. RAM, flash memory,

G/A, and other devices

Either S1C33209 that includes an FPGA or a circuit block equivalent to that product

Target board (mass production version)

ROM. RAM, flash memory,

G/A, and other devices

S1C33209 pin pattern

During board and software development

S1C33 CPU, BCU basic peripheral functions, and internal RAM

S1C33209 or else

SRAM

Flash

FPGA others

QFP I/F

Internal ROM emulation

Pin pattern for the IC with internal S1C33 macros

C33 ASIC manufacturing

For mass production

C33 ASIC product

Figure 6.5 Board Development Structure (Example 2)



7 Mounting

Chapter 7 Mounting

7.1

Precautions on Mounting

The following shows the precautions when designing the board and mounting the IC.

Oscillation Circuit

• Oscillation characteristics change depending on conditions (board pattern, components used, etc.).

In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance.

• Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this:

(1) Components which are connected to the OSC3 (OSC1), OSC4 (OSC2) and PLLC pins, such as oscillators, resistors and capacitors, should be connected in the shortest line.

(2) As shown in the figure below, make a V

SS

pattern as large as possible at circumscription of the OSC3 (OSC1) and OSC4 (OSC2) pins and the components connected to these pins. The same applies to the PLLC pin.

Furthermore, do not use this V

SS cillation system.

pattern to connect other components than the os-

OSC3, OSC4 PLLC

OSC4

OSC3

V

SS

V

SS

PLLC

V

SS

Figure 7.1 Sample V

SS

Pattern

(3) When supplying an external clock to the OSC3 (OSC1) pin, the clock source should be connected to the OSC3 (OSC1) pin in the shortest line.

Furthermore, do not connect anything else to the OSC4 (OSC2) pin.

• In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 (OSC1) and V

DD

, please keep enough distance between OSC3

(OSC1) and V

DD

or other signals on the board pattern.



EPSON 85

7 Mounting

Reset Circuit

• The power-on reset signal which is input to the P_RESETX pin changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product.

• In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the

P_RESETX pin in the shortest line.

Power Supply Circuit

• Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this:

(1) The power supply should be connected to the V

DD

, V

SS

and AV terns as short and large as possible.

DD

pins with pat-

In particular, the power supply for AV

DD

affects A/D conversion precision.

(2) When connecting between the V

DD

and V

SS should be connected as short as possible.

pins with a bypass capacitor, the pins

V

DD

V

SS

V

DD

V

SS

Figure 7.2 Bypass Capacitor Connection Example



7 Mounting

HSDMA

Serial I/O

A/D input

Timer input/output

Input

I/O

Recommended Circuit

External

Bus

C

2

C

1

Rf

2

C

G2

C

D2

Rf

1

C

G1

C

D1

3.3V

A[23:0]

D[23:0]

#RD

#EMEMRD

#DRD

#GARD

#GAAS

#WRL/#WR#WE

#WRH/BSH

#DWR

#HCAS

#LCAS

#CExx/#RASx

#CE10EX

#CE10IN

#WAIT

#BCLK

#BUSREQ

#BUSACK

#BUSGET

#NMI

S1C33209/204/202

[The potential of the substrate

#DMAREQx

#DMAACKx

#DMAENDx

(back of the chip) is V SS .]

V

DD

V

DDE

AV

DDE

DSIO

TST

EA3MD

EA10MD0

EA10MD1

#X2SPD

PLLC

PLLS0

PLLS1

OSC3

SINx

SOUTx

#SCLKx

#SRDYx

#ADTRG

ADx

OSC4

OSC1

EXCLx

TMx

T8UFx kxx

OSC2

#RESET

Vss

Pxx

*1

R

1

X`tal2 or CR

X`tal1

∗

1: When the PLL is not used,

∗

2: leave the PLLC pin open.

The portion of the circuit enclosed in wide lines must be mounted as close to the device as possible.

Also, power supply should be as short and as wide as possible.

C D2

Rf 2

R 1

C 1

C 2

X'tal1

C G1

C D1

Rf 1

X'tal 2

CR

C G2

Crystal oscillator

Gate capacitor

Drain capacitor

Feedback resistor

Crystal oscillator

Ceramic oscillator

Gate capacitor

Drain capacitor

Feedback resistor

Resistor

Capacitor

Capacitor

32.768 kHz

10 pF

10 pF

10 M

Ω

33 MHz (Max.)

33 MHz (Max.)

10 pF

10 pF

1 M

Ω

4.7 k

Ω

100 pF

5 pF

Note: The above table is simply an example, and is not guaranteed to work.



EPSON 87

7 Mounting

Arrangement of Signal Lines

• In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit.

• When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction.

Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit.

Large current signal line

High-speed signal line

K60 (AD0) OSC4

OSC3

V

SS

Large current signal line

High-speed signal line

Figure 7.3 Prohibited Pattern

Precautions for Visible Radiation (when bare chip is mounted)

• Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this

IC, consider the following precautions to prevent malfunctions caused by visible radiation.

(1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use.

(2) The inspection process of the product needs an environment that shields the IC from visible radiation.

(3) As well as the face of the IC, shield the back and side too.



7 Mounting

7.2

Others

The positions (layout) of the following pins is extremely important to prevent incorrect operation of the end device when the C33 macros are used. In some cases, we may request consultation with the customer concerning these positions, depending on the pin arrangement table created by the customer.

P_OSC4, P_OSC3, P_OSC2, P_OSC1, P_PLLC,

P_K67, P_K66, P_K65, P_K64, P_K63, P_K62, P_K61, P_K60



EPSON 89

International Sales Operations

AMERICA

EPSON ELECTRONICS AMERICA, INC.

- HEADQUARTERS -

150 River Oaks Parkway

San Jose, CA 95134, U.S.A.

Phone: +1-408-922-0200 Fax: +1-408-922-0238

- SALES OFFICES -

West

1960 E. Grand Avenue

EI Segundo, CA 90245, U.S.A.

Phone: +1-310-955-5300 Fax: +1-310-955-5400

Central

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone: +1-815-455-7630 Fax: +1-815-455-7633

Northeast

301 Edgewater Place, Suite 120

Wakefield, MA 01880, U.S.A.

Phone: +1-781-246-3600 Fax: +1-781-246-5443

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone: +1-877-EEA-0020 Fax: +1-770-777-2637

EUROPE

EPSON EUROPE ELECTRONICS GmbH

- HEADQUARTERS -

Riesstrasse 15

80992 Munich, GERMANY

Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110

SALES OFFICE

Altstadtstrasse 176

51379 Leverkusen, GERMANY

Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701

FRENCH BRANCH OFFICE

1 Avenue de l' Atlantique, LP 915 Les Conquerants

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

Avda. Alcalde Barrils num. 64-68

E-08190 Sant Cugat del Vallès, SPAIN

Phone: +34-93-544-2490 Fax: +34-93-544-2491

ASIA

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

Phone: 64106655 Fax: 64107319

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

Phone: 21-6485-5552 Fax: 21-6485-0775

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

Phone: +852-2585-4600 Fax: +852-2827-4346

Telex: 65542 EPSCO HX

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287, Nanking East Road, Sec. 3

Taipei

Phone: 02-2717-7360 Fax: 02-2712-9164

Telex: 24444 EPSONTB

HSINCHU OFFICE

13F-3, No. 295, Kuang-Fu Road, Sec. 2

HsinChu 300

Phone: 03-573-9900 Fax: 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

Millenia Tower, SINGAPORE 039192

Phone: +65-337-7911 Fax: +65-334-2716

SEIKO EPSON CORPORATION KOREA OFFICE

50F, KLI 63 Bldg., 60 Yoido-dong

Youngdeungpo-Ku, Seoul, 150-763, KOREA

Phone: 02-784-6027 Fax: 02-767-3677

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624

ED International Marketing Department Europe & U.S.A.


Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564

ED International Marketing Department Asia


Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110

In pursuit of “Saving” Technology, Epson electronic devices.

Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams.

Epson IS energy savings.

S1C33

ASIC DESIGN GUIDE

ELECTRONIC DEVICES MARKETING DIVISION

EPSON Electronic Devices Website http://www.epson.co.jp/device/

First issue November, 2000

Printed March, 2001 in Japan O A

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