Si537x-EVB User`s Guide

Si537x-EVB User`s Guide
Si 5 3 7 x - EVB
S i537 X -EVB E VALUATION B OARD U SER ’ S G UIDE
Description
Features
The Si5374/75/76 Any Frequency Precision Clocks are
based on Silicon Labs 3rd-generation DSPLL
technology, which provides any-frequency synthesis in
a highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
devices have excellent phase noise and jitter
performance. All of the devices support 350 fs RMS
jitter generation across the 12 kHz to 20 MHz jitter filter
bandwidth. For all devices, the DSPLL loop bandwidth
is digitally programmable, providing jitter performance
optimization at the application level. These devices are
ideal for providing clock multiplication/clock division and
jitter attenuation in mid-range and high-performance
timing applications where printed circuit board real
estate is at a premium.
The Si537x-EVB includes the following:

CD with documentation and EVB software including
the Si537x_DSPLLsim configuration software utility.
 EVB circuit board
 Si537x-EVB User’s Guide (this document)
Functional Block Diagram
Regulator
3.3 V
USB
Serial #
SPI
MCU
EEPROM
I2C
Level
Translate
CPLD
Si530
I2C
Control, monitor
OSC
Ext Ref
A
B
C
D
Si537x
Rev. 0.6 11/12
Copyright © 2012 by Silicon Laboratories
Si537x-EVB
Si537x-EVB
1. Introduction
The Si537x-EVB provides a platform for evaluating Silicon Labs’ Si5374, Si5375, and Si5376 Any Frequency
Precision Clocks. These devices are jitter attenuating quad DSPLLs that are microprocessor controlled using an
I2C interface. The Si5374 and the Si5376 have eight clock inputs and 8 clock outputs, whereas the Si5375 has 4
clock inputs and 4 clock outputs. The Si5374 has the added feature of lower loop BW than the Si5375 and Si5376.
Figure 1. Si537x-EVB
2 kHz–808 MHz
4–525 Hz

4/4
2 kHz–710 MHz
2 kHz–808 MHz
60 Hz–8.4 kHz
8/8
2 kHz–710 MHz
2 kHz–808 MHz
60 Hz–8.4 kHz
Input
Si5374
8/8
Si5375
Si5376
2
Rev. 0.6
Package


Digital Hold
2 kHz–710 MHz
Frequency Range
Free Run
Output
DSPLL Loop
Bandwidth
Range
# Input/
Output
Clocks
VCO Freeze
Device
Hitless Switching
Table 1. Si537x Selection Summary




10x10 mm
80-PBGA
10x10 mm
80-PBGA

10x10 mm
80-PBGA
Si537x-EVB
2. Applications
The Si5374/75/76 Any Frequency Precision Clocks offer a comprehensive feature set, including any frequency
synthesis, jitter attenuation, fully integrated loop filter, multiple clock inputs, multiple clock outputs, alarm and status
outputs, hitless switching between multiple input clocks, programmable output clock format (LVPECL, LVDS, CML,
CMOS), and output phase adjustment between all output clocks. For more details, consult the Silicon Labs timing
products website at www.silabs.com/timing.
The Si537x-EVB has a Silicon Labs MCU (C8051F430) that supports USB communications with a PC host. The
Si5374/75/76 devices are controlled and monitored through the I2C serial port. A CPLD is connected to the MCU
and stores pin configuration data and reads the device status pins. The MCU communicates to the Si537x device
using I2C through a voltage level translator. However, the user has the option of bypassing the MCU and controlling
the devices from an external serial device. On-board termination is included so that the user can evaluate either
single-ended or differential as well as ac or dc coupled clock inputs and outputs. A separate DUT (device under
test) power supply connector is included. LEDs are provided for convenient monitor of key status signals. The user
can select between a number of reference oscillator options, including external sources and various on-board
options.
For more detailed information about the applications of these devices, please see their respective data sheets.
3. Si5374/75/76-EVB Quick Start
For more detailed information about these devices, see their respective data sheets.
Rev. 0.6
3
Si537x-EVB
4. Functional Description
The Si537x-EVB and software allows for a complete and simple evaluation of the functions, features, and
performance of the Si5374/75/76 Any Frequency Precision Clocks. For the following material, refer to the
schematics in section “7. Schematics.”
4.1. Block Diagram
Regulator
3.3 V
USB
Serial #
SPI
MCU
EEPROM
I2C
Level
Translate
CPLD
Si530
I2C
Control, monitor
OSC
Ext Ref
A
B
C
D
Si537x
Figure 2. Si537x-EVB Block Diagram
Figure 2 is a block diagram of the evaluation board and it is helpful to refer to this diagram. The MCU
communicates to the host PC over a USB connection. The MCU controls and monitors the Si537x pins through the
CPLD, which provides level translation between the MCU and the Si537x. I2C level translation is provided
separately. A number of different options are provided for the required Si537x external reference oscillator.
4.2. Si537x Device
To minimize noise and crosstalk, the Si537x device has separate and filtered VDD supplies. Two-pin jumper plugs
(J16, J17, J25, and J33) are provided so that the distinct power supplies can be monitored.
4.3. Input Clocks
The input clocks are all located at the edge of the board. For each clock input pair, each input is ac terminated with
50  to ground. With this configuration, single ended inputs can be implemented by simply leaving the unused
clock input disconnected. If low frequency clock inputs are in use, the reactance of the 100 nf capacitors (C12,
C13, C14, etc.) can become significant and they should be replaced with 0  resistors. In some circumstances, the
ac termination should be removed and replaced. CMOS inputs are typically best terminated by using series source
termination at the output of the CMOS driver and completely removing all of the on-board input termination.
Regardless of the termination scheme in use, a scope should be used to verify that none of the clock input
specifications found in the data sheet are being violated.
4
Rev. 0.6
Si537x-EVB
4.4. Output clocks
The output clocks all use vertical mount SMA connectors and are ac coupled. There may be circumstances (e.g.,
CMOS outputs) for which the 100 nF capacitors should be replaced with 0  resistors. Pads for resistors between
the two halves of the outputs are provided for CMOS outputs so that the outputs can be put in parallel for greater
drive strength.
4.5. OSC Reference Source
The Si537x requires a low-jitter reference on its OSC_P and OSC_N input pins. To provide a clock source, the user
has a number of different options:
1. The factory default configuration is a 121.109 MHz Si530 crystal oscillator (XO). For this configuration
install C78 and C81 (in the silkscreen XO box on the top of the board), remove C97 and C101 (in the INT
silkscreen box on the bottom of the board), and remove C77 and C80 (in the silkscreen box EXT on the top
of the board). J50 should be removed and J60 should select the desired XO supply voltage of 3.3 V by
jumpering J60.2 to J60.3.
2. There are provisions for three different XO oscillator packages in industry standard pinouts: 5x7 mm,
3.2x5 mm, and 3.2x2.5 mm. If any of these are used, be sure to install C78 and C81 (in the silkscreen XO
box on the top of the board), remove C97 and C101 (in the INT silkscreen box on the bottom of the board),
and remove C77 and C80 (in the silkscreen box EXT on the top of the board). J50 should be removed and
J60 should select the desired XO supply voltage of either the Si537x VDD or 3.3 V.
3. An off-board, external reference oscillator may be used instead of the Si530 XO. If this is desired, C98 and
C102 (in the CKIN silkscreen box on the bottom of the board), C101 and C97 (in the INT silkscreen box on
the bottom of the board), and C78 and C81 (in the silkscreen XO box on the top of the board) should all be
removed and C77 and C80 (in the EXT silkscreen box on the top of the board) should be installed. If this
mode is selected, the clock input should be applied to J64 and J66. Both J50 and J60 should be removed
so that the other references sources are not powered and do not add noise.
4. A PCB footprint for a reference Si5326 is included on the EVB. If it is installed, the Si5326 is initialized by
the MCU and EEPROM so that it powers up with an output that is 114.285 MHz based on its crystal, X1.
The output of the Si5326 can be monitored at J65 and J67 and can be changed to most any frequency
using DSPLLsim . Free run at 114.285 MHz is the factory default Si5326 frequency plan. If a reference
OSC frequency in the
37–41 MHz band is to be used, be sure to set the RATE register (reg 2) for all of the DSPLLs to 0101.
For options 2 and 4 above, an external OSC reference XO in the 37–41 MHz frequency band can also be used.
With this approach, the output jitter will be higher by an amount that is illustrated in “AN591: Crystal Selection for
the Si5315 and Si5317,” Figures 3 and 4. It will also be necessary to create an Si537xDSPLLsim frequency plan
with the appropriate RATE_REG (at addr 2) setting of 0001.
It is also possible to have the reference Si5326 lock onto an external clock source instead of locking to its
114.285 MHz crystal in free run mode. If this mode is desired, install C98 and C102 (in the CKIN silkscreen box on
the bottom of the board) and then load the appropriate frequency plan into the reference Si5326 using DSPLLsim.
The external clock source is connected to J64 and J66. If the Si5326 is being used, J50 should be installed and
J60 should be removed.
Though they will result in slightly lower performance, single ended reference clock inputs can be connected to J66,
with the unused J64 connected to ground. In all cases, when a single ended reference oscillator is in use, C53
(located close to the Si537x) should be installed.
Rev. 0.6
5
Si537x-EVB
4.6. CPLD
The CPLD provides various functions including level translation and the buffering of monitor/control of signals for
the Si537x DUT and the Si5326 reference source. Examples are the LOL, IRQ, and CS_CA signals from the
Si537x as well as the SPI port connection to the reference Si5326.
4.7. MCU
The MCU is the intermediary between the PC host and the Si537x DUT. The host’s USB port provides power for
the MCU and the LEDs through a 3.3 V regulator (U17). U6 provides I2C level translation to the DUT VDD voltage
level. U2 is an EEPROM that is used to initialize the reference Si5326. J51 is an I2C serial port connector by which
an external I2C master can control the on-board Si537x or by which the on-board MCU can control an Si537x that
resides on a external target board.
4.8. Power and LEDs
J4 is the main Si537x power connector. Remote sensing for the power supply is provided by J3. DUT current can
be monitored by removing R1 and connecting to J7. U10 and U11 are buffers that are used to drive the LEDs. The
status outputs are available at J44/45.
6
Rev. 0.6
Si537x-EVB
5. Connectors and LEDs
U1
J44, J45, status
J51, ext I2C
XO caps
J50, Ref pwr
EXT caps
Top
J60, XO pwr
INT caps
Bottom
CKIN caps
Figure 3. Connectors, Top, and Bottom Views
J51 can be used as an attachment point for controlling the Si537x DUT from an external I2C master or to use the
MCU to control an Si537x DUT that resides on an external target board.
To control the on-board Si537x from an external I2C master, disconnect the cable from the USB connector (J61),
thereby depriving the EVB of its 5 V power source. A lack of 3.3 V power will disable the U6 level translator (by
virtue of U6.8) so that the MCU will be isolated from the external I2C bus that should be applied to J51.
To control an external Si537x from the on-board MCU, the on-board Si537x must be held in reset so that it does not
assert either of the two I2C bus signals. This can be done by opening the Si537x Register Programmer and going
to the Options pull down menu on the top toolbar and selecting "Switch to External Control Mode.”
Rev. 0.6
7
Si537x-EVB
Table 2. External I2C
J51
Name
Comment
J51.1
SDA
serial data
J51.3
SCL
serial clock
J51.9
DUT_RST_L
DUT reset
J45 is used to make external connections to status signals:
Table 3. Status
8
J45
Name
Comment
J45.27
DUT_PWR
+2.5 or 1.8 V
J45.25
REF_LOL
J45.23
IRQ_D
J45.21
IRQ_C
J45.19
IRQ_B
J45.17
IRQ_A
J45.15
CS_CA_D
J45.13
CS_CA_C
J45.11
CS_CA_B
J45.9
CS_CA_A
J45.7
LOL_D
J45.5
LOL_C
J45.3
LOL_B
J45.1
LOL_A
Rev. 0.6
Si537x-EVB
The LEDs are used to quickly determine the board status:
Table 4. LED Descriptions
LED
Color
Label
D17
yellow
CS_CA_D
D16
yellow
CS_CA_C
D15
yellow
CS_CA_B
D14
yellow
CS_CA_A
D13
red
LOL_D
D12
red
LOL_C
D11
red
LOL_B
D10
red
LOL_A
D9
red
IRQ_D
D8
red
IRQ_C
D7
red
IRQ_B
D6
red
IRQ_A
D5
green
MCU_2
D4
green
MCU_1
D3
red
REF_LOL
D2
green
3.3 V
D1
green
DUT_PWR
Rev. 0.6
9
Si537x-EVB
6. EVB Software Installation
The release notes and the procedure for installing the EVB software can be found on the release CD included with
the EVB. These items can also be downloaded from the Silabs web site: www.silabs.com/timing. Follow the links
for 4-PLL Jitter attenuators, and look under the Tools tab.
Program
Description
Si537x_DSPLLsim
Provides the high level control of the Si537x device. It has the frequency planning wizard
as well as control of the pins in an organized, intuitive manner. Register maps and other
configuration files can be saved and opened.
Setting Utility
This application allows for quick read/write access to each control word of the Si537x
device. It can save and open text files.
Register Prgmr
Provides a low-level, hex register read/write capability on a byte basis (as opposed to
control word). Register map files can be opened and saved in its batch mode.
Register Viewer
Displays the current register map data in a table format sorted by register address. Can
save and print the register map.
10
Rev. 0.6
100N
100N
RSTD_L
CS_CA_D
RSTC_L
CS_CA_C
RSTB_L
CS_CA_B
RSTA_L
CS_CA_A
NOPOP
220UF
+
C116
SCL
SDA
CKIN2N_D
CKIN2P_D
CKIN1N_D
CKIN1P_D
CKIN2N_C
CKIN2P_C
CKIN1N_C
CKIN1P_C
CKIN2N_B
CKIN2P_B
CKIN1N_B
CKIN1P_B
CKIN2N_A
CKIN2P_A
CKIN1N_A
CKIN1P_A
C112
402
C17 100N
10UF_805
C19
1
2
1
2
1
2
C27
NOPOP
220UF
C117
+
10UF_805
C18
1
2
C20
100N
C28
100N
49.9
49.9
49.9
49.9
J16
G5
G6
F4
J4
G4
G3
H4
H3
F6
F9
F7
G7
F8
G8
D6
A6
C6
C7
B6
B7
D4
D1
D3
C3
D2
C2
SCL
SDA
RSTL_D
CS_CA_D
CKIN2N_D
CKIN2P_D
CKIN1N_D
CKIN1P_D
RSTL_C
CS_CA_C
CKIN2N_C
CKIN2P_C
CKIN1N_C
CKIN1P_C
RSTL_B
CS_CA_B
CKIN2N_B
CKIN2P_B
CKIN1N_B
CKIN1P_B
RSTL_A
CS_CA_A
CKIN2N_A
CKIN2P_A
CKIN1N_A
CKIN1P_A
J17
NOPOP
1
2
NOPOP
1
2
R29
R31
R32
R30
100N
C113
402
B
A
VDD_B
D
C
B
A
Si537x
U1
C1
B5
C4
VddA1
VddA2
VddA3
CKOUT1P_A
402
C115
100N
E6
E5
H5
F2
F1
E1
H1
J1
E8
H6
J6
J5
J8
J9
C5
D8
D9
E9
B9
A9
E2
B4
A4
A5
2A
B1
C30
100N
Figure 4. Si537x
OSC_N
OSC_P
LOL_D
IRQ_D
CKOUT2N_D
CKOUT2P_D
CKOUT1N_D
CKOUT1P_D
LOL_C
IRQ_C
CKOUT2N_C
CKOUT2P_C
CKOUT1N_C
CKOUT1P_C
LOL_B
IRQ_B
CKOUT2N_B
CKOUT2P_B
CKOUT1N_B
CKOUT1P_B
LOL_A
IRQ_A
CKOUT2N_A
CKOUT2P_A
CKOUT1N_A
Gnd1
Gnd2
Gnd3
Gnd4
B2
A3
B3
E4
VDD_A
D5
A7
D7
VddB1
VddB2
VddB3
Gnd5
Gnd6
Gnd7
Gnd8
C8
A8
B8
C9
Ferrite
L2
F5
E7
G9
VddC1
VddC2
VddC3
Gnd9
Gnd10
Gnd11
Gnd12
H7
J7
H8
H9
C29
100N
1
10UF_805
C31
C53
100N
402
NOPOP
2
Ferrite
L1
F3
J3
E3
VddD1
VddD2
VddD3
Gnd13
Gnd14
Gnd15
Gnd16
Rev. 0.6
G1
H2
J2
G2
C118
220UF
NOPOP
OSC_N
OSC_P
+
VDD_C
C
J25
CKOUT2N_D
CKOUT2P_D
CKOUT1N_D
CKOUT1P_D
CKOUT2N_C
CKOUT2P_C
CKOUT1N_C
CKOUT1P_C
CKOUT2N_B
CKOUT2P_B
CKOUT1N_B
CKOUT1P_B
CKOUT2N_A
CKOUT2P_A
CKOUT1N_A
CKOUT1P_A
NOPOP
1
2
LOL_D
IRQ_D
LOL_C
IRQ_C
LOL_B
IRQ_B
LOL_A
IRQ_A
C43
10UF_805
402
C114
100N
1
2
C44
100N
L3
Ferrite
C45
100N
+
C119
220UF
NOPOP
VDD_D VDD_D
2
1
1
2
NOPOP
J33
D
L4
Ferrite
DUT_PWR
2
1
DUT_PWR
Si537x-EVB
7. Schematics
11
Si537x-EVB
1
CKIN1P_A
CKIN1_A-
49.9
R14
J18
2
CKIN1N_A
C33
10NF
49.9
CKIN1P_C
J35
SMA_EDGE
CKIN1_C-
100N C15
SMA_EDGE
100N C52
49.9
C35
10NF
R15
J31
CKIN1N_C
100N C42
C34
10NF
SMA_EDGE
49.9
1
CKIN2P_A
100N C3
49.9
R6
R16
1
CKIN2_C+
2
C21
10NF
3
J5
SMA_EDGE
3
2
CKIN2_A+
R17
1
2
3
2
1
1
CKIN1_C+
C32
10NF
3
100N C9
3
J13
SMA_EDGE
3
2
CKIN1_A+
J56
CKIN2P_C
100N C69
49.9
R21
C46
10NF
SMA_EDGE
J1
CKIN2N_A
100N C1
CKIN2_C-
C22
10NF
SMA_EDGE
49.9
R7
1
3
3
2
1
2
CKIN2_A-
J48
CKIN2N_C
100N C60
C39
10NF
SMA_EDGE
49.9
SMA_EDGE
49.9
1
CKIN2P_B
J23
SMA_EDGE
100N C16
3
2
CKIN2_B+
CKIN2_B-
49.9
C26
10NF
3
2
3
3
J55
CKIN1N_D
100N C65
C57
10NF
49.9
R28
1
CKIN2P_D
J26
100N C36
SMA_EDGE
CKIN2_D-
CKIN2N_B
C25
10NF
49.9
R27
49.9
R25
C54
10NF
100N C14
SMA_EDGE
49.9
C56
10NF
SMA_EDGE
CKIN2_D+
R11
1
J14
Do not populate
for Si5375-EVB
R8
100N C59
1
2
C23
10NF
CKIN1P_D
J46
SMA_EDGE
CKIN1_D-
CKIN1N_B
100N C2
1
2
3
2
1
J2
2
C24
10NF
2
CKIN1_B-
1
CKIN1_D+
R9
3
49.9
3
2
CKIN1P_B
J6
100N C4
SMA_EDGE
3
1
CKIN1_B+
R19
J34
CKIN2N_D
100N C47
C55
10NF
49.9
R26
SMA_EDGE
R10
Figure 5. Clock Inputs
C10
C40
J19
100N
SMA_VERT
R2
0 ohm
CKOUT1_C+
R20
0 ohm
J9
J30
100N
100N
CKOUT1_A-
1
CKOUT1N_A
J29
SMA_VERT
NOPOP
CKOUT1_C-
1
C41
2
3
4
5
C5
CKOUT1N_C
SMA_VERT
2
3
4
5
NOPOP
1
CKOUT1P_C
2
3
4
5
100N
2
3
4
5
CKOUT1_A+
1
CKOUT1P_A
SMA_VERT
C11
C50
J20
100N
SMA_VERT
R23
0 ohm
J10
100N
J39
100N
CKOUT2_A-
1
CKOUT2N_A
CKOUT2_C+
SMA_VERT
NOPOP
R3
0 ohm
J38
C51
2
3
4
5
C6
CKOUT2_C-
1
CKOUT2N_C
SMA_VERT
2
3
4
5
NOPOP
1
CKOUT2P_C
CKOUT2_A+
2
3
4
5
100N
2
3
4
5
1
CKOUT2P_A
SMA_VERT
Do not populate
for Si5375-EVB
C12
C49
J21
100N
SMA_VERT
R4
0 ohm
R22
0 ohm
J11
100N
CKOUT1_B-
C48
2
3
4
5
C7
SMA_VERT
SMA_VERT
C13
C38
J22
100N
SMA_VERT
R5
0 ohm
NOPOP
J28
SMA_VERT
R18
0 ohm
J12
100N
J27
100N
CKOUT2_B-
C8
C37
SMA_VERT
SMA_VERT
Figure 6. Clock Outputs
Rev. 0.6
CKOUT2_D-
1
CKOUT2N_D
2
3
4
5
1
CKOUT2N_B
CKOUT2_D+
1
CKOUT2P_D
CKOUT2_B+
2
3
4
5
100N
2
3
4
5
1
CKOUT2P_B
12
CKOUT1_D-
1
CKOUT1N_D
2
3
4
5
1
NOPOP
CKOUT1_D+
J36
100N
CKOUT1N_B
J37
SMA_VERT
NOPOP
2
3
4
5
NOPOP
1
CKOUT1P_D
2
3
4
5
100N
2
3
4
5
CKOUT1_B+
1
CKOUT1P_B
5()B/2/
5()B567B/
026,
5()B66B/
0,62
6&/.
EXT_REF-
1)
&
1)
&
5
5
12323
&
1
5
-
60$B('*(
5
N
5()B&.,1B3
5()B&.,1B1
CKIN
12323
&
1
5
N
73
;
73
8
567
&02'(
)547%/
6',B)546(/
$B66B)546(/
$B)546(/
$B)546(/
,17B&%
&%
6)287
6)287
&.287
&.287
&.287
&.287
/2/
&.6(/&.B$&79
12323
Si532x
6'$B6'2B%:6(/
6&/B6&/.B%:6(/
'%/B%<
$8726(/
,1&
'(&
&.,1B
&.,1B
&.,1
&.,1
;$
;%
&
1
/
/
&
8)
)HUULWH
&
8)
-
RKP
&
1
'87B3:5
73
5
INT
&
1
12323
&
&
-
60$B('*(
12323 1
12323 1
REF_PWR
& 1
93
EXT
1 &
)HUULWH
26&B'87B3:5
-
XO_PWR
5()B&.287B3
5()B&.287B1
&
1
93
&
1
Figure 7. Reference Oscillators
0+]
5()B9''
5()B1
5()B3
5DWH
5DWH
-
60$B('*(
REF_OUT-
REF_OUT+
&
1
12323
9GG
&/.
9''
12323
287
9''
;2E\P
8
*1'
2(
6L
*1' &/.
1&
2(
8
&ON
6L
*QG
2( 8 &ON
1&
121.109 MHz
;2B3:5
-
60$B('*(
9''
9''
9''
Rev. 0.6
*1'
*1'
*1'
GND
EXT_REF+
&
1
5
RKP
5
5
N
12323
5
XO
&
1
26&B1
26&B3
Si537x-EVB
13
RSTA_L
RSTB_L
RSTC_L
RSTD_L
CPLD_DUT_PWR
R57
1
2
3
4
Rev. 0.6
C99
1UF
10 R80
LOL_A
LOL_B
LOL_C
LOL_D
10
NOPOP
R62
0 ohm
+
J53
J54
NOPOP
R61
0 ohm
0 ohm
R90
C70
33UF
R81
2
3
1
LOL
NOPOP
NOPOP
NOPOP
R60
0 ohm
4
5
66.5
R89
TPS76201
FB
Vreg
Out
R10x4
R50
5
6
7
8
R10Kx4
R58
0 ohm
Gnd
EN
In
U3
4
3
2
1
install exactly one resistor:
code
E
Si5374: install R58
D
Si5375: install R60
B
Si5376: install R61
V3P3
R36
0 ohm
1
2
3
4
1
2
3
4
14
8
7
6
5
DUT_PWR
LS
MS
2
1
2
C66
1UF
+
C73
100N
C71
33UF
C63
10NF
C96
1UF
1.8V
FN12_M11
FN12_M13
FN12_M14
FN12_M15
FN11_M11
FN11_M12
FN11_M13
FN11_M14
FN10_M1
FN10_M2
FN10_M3
FN10_M4
FN10_M5
FN10_M6
FN10_M12
FN9_M1
FN9_M2
FN9_M4
FN9_M6
FN9_M12
FN4_M1
FN4_M2
FN4_M3
FN4_M5
FN4_M6
FN4_M13
FN3_M5
FN3_M12
FN3_M14
FN3_M16
FN2_M1_GTS2
FN2_M3_GTS3
FN2_M5_GTS0
FN2_M12_GTS1
FN2_M14
FN2_M15
FN5_M4_GCK1
FN5_M6_GCK0
Bank 1
C85
1UF
C72
10NF
100N
C74
43
42
41
40
39
58
59
60
61
63
64
52
50
49
46
44
53
54
55
56
32
33
34
35
36
37
C83
100N
C75
10NF
RST_L
C82
10NF
88
98
20
38
51
26
57
XC2C128
VCCIO2-1
VCCIO2-2
VCCIO1-1
VCCIO1-2
VCCIO1-3
VCC1
VCC2
U12A
Figure 8. CPLD
C62
10NF
C61
10NF
XC2C128
FN16_M5
FN16_M6
FN16_M11
FN16_M12
FN16_M13
FN15_M11
FN15_M12
FN15_M13
FN15_M14
FN15_M15
FN15_M16
FN14_M1
FN14_M3
FN14_M5
FN14_M14
FN14_M15
FN13_M2
FN13_M4
FN13_M6
FN13_M13
FN8_M6
FN8_M11
FN8_M12
FN8_M13
FN8_M14
FN8_M15
FN7_M5
FN7_M6
FN7_M11
FN7_M12
FN7_M13
FN7_M14
19
18
17
16
15
14
24
27
28
29
30
23
22
+3.3V
FN6_M2_CDRST
FN6_M4_GCK2
FN6_M12_DGE
FN6_M14
FN6_M16
U12C
FN1_M3_GSR
FN1_M6
FN1_M12
FN1_M13
FN1_M14
Bank 2
V1P8
68
67
66
65
85
86
87
89
77
76
74
73
72
71
70
78
79
80
81
82
8
9
10
11
12
13
93
92
91
90
1
2
3
4
6
7
1
2
99
97
96
95
94
1
R79
113
IRQ_A
IRQ_B
IRQ_C
IRQ_D
CS_CA_A
CS_CA_B
CS_CA_C
CS_CA_D
TP1
TP3
TP4
DUT_PWR
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
SMT
J63
21
25
31
62
69
75
84
100
1
2
3
4
5
6
VCCAUX
TMS
TDI
TDO
TCK
J52
NOPOP
JTAG
1
2
3
4
5
6
NOPOP
CLK
Trig1
R49
REG_ADR0
REG_ADR1
REG_ADR2
REG_ADR3
REG_ADR4
SS_L
MOSI
SCLK
MISO
REF_RST_L
5
83
47
48
45
V3P3
LED_CS_CA_A
LED_CS_CA_B
LED_CS_CA_C
LED_CS_CA_D
REF_LOL
LED_LOL_A
LED_LOL_B
LED_LOL_C
LED_LOL_D
LED_IRQ_A
LED_IRQ_B
LED_IRQ_C
LED_IRQ_D
NOPOP
U12B
10
10
R47
R44
XC2C128
VCCAUX
TDO
TMS
TCK
TDI
Trig3
Trig2
J47
NOPOP
J49
0 ohm
J43
1
2
3
4
1
2
3
4
5
6
1
2
3
R74
100
76
CPLD_RST_L
REF_SS_L
10
1
75
CPLD
CMND_DONE
DUT_PWR_L
25
51
26
50
Si537x-EVB
I2C
10
8
6
4
2
J51
9
7
5
3
1
2
C64
100N
I2C
CS
49.9
R43
Vref2
SDA2
SCL2
R85
0 ohm
NOPOP
SDA1
SCL1
7
3
MCU_SCLK
MCU_MISO
EEPROM_WE
EEPROM_CS
4
3
U6
PCA9306
2 Vref1
C104
100N
1
R45
10k
R41
10k
R83
1.5K
1
2
disable
I2C
Xcvr
J68
MCU_MOSI
R48
49.9
R46
10k
R93
1.5K
A
K
NOPOP
1
2
1
5
6
M95040
HOLD
EEPROM W
Q
D
Clk
U2
SCL
SDA
R77
0 ohm
D20
2
NOPOP
BAT54S
D19
4
3
3
BAT54S
6
I2C pullup
BUS1
BUS2
NOPOP
LTC4311
10_M_Header_SMT
V3P3
SDA
SCL
EN
DUT_RST_L
C105
100N
3
GND1
1
GND2 VCC
U5
3
1
Q3
BSS138
1
Q2
3
MCU_SDA
5
NOPOP
R92
MCU_SCL
R82
4.99K
2
6
7
C100
100N
BSS138
0 ohm
2
2
DUT_PWR
C87
1UF
R91
4.99K
10k
10k
S
G
+
46
45
44
43
42
41
40
39
6
5
4
3
2
1
48
47
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
U14
V5V
U17
49.9
49.9
R54
R52
SCLK
MOSI
SS_L
MISO
Figure 9. MCU
49.9
49.9
1
2
3
23
24
25
26
27
28
29
30
15
16
17
18
19
20
21
22
SPI
to
Si5326
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
LM1117
GND
VOUT1
VIN
3
4 2
1
Vreg
VOUT2
C8051F340
4
R55
R53
Si8051F340
C89
33UF
V3P3
MCU_SS_L
C88
100N
R84
FET
D
R78
TP8
2
48
37
1
36
2
1
+
MCU
12
13
24
C90
33UF
25
CMND_DONE
TP5
J62
R24
1K
NOPOP
MCU_EVB_SER_NUM
R33
1K
10_M_Header_SMT
2
1
4
3
6
5
8
7
10
9
MCU
USB Clamp
49.9
V3P3
NO
USB Clamp
D+
D-
J61
Gnd
V
USB
4
1
R39
10k
1
2
3
SN65220
SW1
4
3
RESET
Ser No.
I/O
DS2411
2
R65
1K
serial number
EVB_SER_NUM
MCU_LED1
1
2
1
2
J59
NOPOP
5V
CPLD_RST_L
NC1
NC2
NC3
U9
3
4
5
C109
100N
MCU depends on USB for power
3
USB
U15
R40
2
U16
SN65220
C67
100N
10
D18
3
BAT54S
D_P
MCU_LED2
REG_ADR4
REG_ADR3
REG_ADR2
REG_ADR1
REG_ADR0
C68
1UF
1K
C58
100N
R76
1K
D_N
R64
VBUS
R42
R38
0 ohm
V3P3
1
NC1
A
6
5
8
2
R34
8
EN
GND
1
3
NC2
B
0 ohm
GND
7
Vcc
Vss
4
10
11
Vdd
REGIN
13
14
RST/C2CK
C2D
12
8
9
VBUS
D+
D-
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
38
37
36
35
34
33
32
31
1
6
Gnd1
Gnd2
2
6
4
1
NC1
A
S2
5
3
NC2
B
4
Gnd1
Gnd2
5
S1
5
6
Vcc
GND
Rev. 0.6
1
MCU_DUT_PWR
Si537x-EVB
15
1
R67
10k
DUT_PWR
DUT_PWR_L
LED_LOL_A
LED_LOL_B
LED_LOL_C
LED_LOL_D
LED_CS_CA_A
LED_CS_CA_B
LED_CS_CA_C
LED_CS_CA_D
1
R69
10k
BSS138
C94
100N
Phoenix_2_screw
GND
2
OE1
OE2
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
R96
+
Grn
C
18
17
16
15
14
13
12
11
A
D1
C91
220UF
1
+
DUT_PWR
2
10k
O0
O1
O2
Q3
O4
O5
O6
O7
Buffer
2
74LCX541
V3P3
1612
L6
Q1
1
19
2
3
4
5
6
7
8
9
U10
1
20
Vcc
GND
150
C92
33UF
R73
LOL_D
LOL_C
LOL_B
LOL_A
CS_CA_D
CS_CA_C
CS_CA_B
CS_CA_A
V3P3
C93
100N
1
1
1
1
2
2
2
2
NOPOP
Yel
Yel
D17
Yel
D15
D16
Yel
D14
Red
D13
Red
D12
Red
D11
Red
D10
2
2
2
2
1
1
1
1
#4
H4
-S
#4
#4
H5
J3
1
2
3
SENSE
+S
H1
mounting holes
#4
H3
R150x4
R68
8
7
6
5
1
LED_IRQ_A
LED_IRQ_B
LED_IRQ_C
LED_IRQ_D
REF_LOL
MCU_LED1
MCU_LED2
0 ohm
R13
OE1
OE2
J58
1
J32
J57
J15
1
1
J41
1
J40
J8
1
1
J24
1
J42
18
17
16
15
14
13
12
11
1
1
O0
O1
O2
Q3
O4
O5
O6
O7
Buffer
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
74LCX541
ground
pins
R75
10k
1
19
2
3
4
5
6
7
8
9
U11
10k
R70
V3P3
Place resistors
next to U1
0 ohm R12
Figure 10. Power and LEDs
#4
H2
1
2
3
4
4
3
2
1
R66
R150x4
5
6
7
8
DUT_PWR
measure DUT
voltage, currrent
J7
0 ohm R1
2
1
1
*
*
1
R35
20
Vcc
GND
J4
A
A
C
C
A
DUT_PWR
1
100
C95
100N
3.3V
MCU_2
MCU_1
REF_LOL
IRQ_D
IRQ_C
IRQ_B
IRQ_A
14_M_Header
J44
J45
14_M_Header
14
13
12
11
10
9
8
7
6
5
4
3
2
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Status
1
1
1
2
2
2
2
2
D3
D9
D8
D7
D6
D4
D5
D2
Red
Red
Red
Red
Red
Grn
Grn
Grn
2
2
2
1
1
1
1
1
REF_LOL
LED_IRQ_D
LED_IRQ_C
LED_IRQ_B
LED_IRQ_A
LED_CS_CA_D
LED_CS_CA_C
LED_CS_CA_B
LED_CS_CA_A
LED_LOL_D
LED_LOL_C
LED_LOL_B
LED_LOL_A
1
2
3
4
4
3
2
1
R150x4
R72
8
7
6
5
R71
R150x4
5
6
7
8
3M unshrouded header:
2380-6121TG
Digikey: 2380-6121TG-ND
A
DUT_PWR
C
A
C
A
Ferrite
C
A
C
A
3
C
A
C
A
Rev. 0.6
2
C
A
C
A
A
C
C
10
C
A
1
C
A
10
C
A
16
C
DUT Power
Si537x-EVB
Si537x-EVB
8. Bill of Materials
Table 5. Si537x-EVB Bill of Materials
Item Qty
Reference
Part
Mfgr
Mfr Part Num
BOM
Digikey
Footprint
1
62
C1,C2,C3,C4,
C5,C6,C7,C8,
C9,C10,C11,
C12,C13,C14,
C15,C16,C19,
C20,C27,C28,
C29,C30,C36,
C37,C38,C40,
C41,C42,C44,
C45,C47,C48,
C49,C50,C51,
C52,C58,C59,
C60,C64,C65,
C67,C69,C73,
C74,C83,C86,
C88,C93,C94,
C95,C97,C100,
C101,C103,
C104,C105,
C106,C107,
C109,C110,C111
100N
Venkel
C0603X7R160-104KNE
603
2
4
C17,C18,C31,C43
10UF_805
Venkel
C0805Y5V6R3106ZN
805
3
24
C21,C22,C23,C24,
C25,C26,C32,C33,
C34,C35,C39,C46,
C54,C55,C56,C57,
C61,C62,C63,C72,
C75,C76,C82,C84
10NF
Venkel
C0603X7R160-103KNE
603
5
8
C66,C68,C79,C85,
C87,C96,C99,C108
1UF
Venkel
C0603X7R6R3-105KNE
603
6
3
C70,C89,C90
33UF
Venkel
TA006TCM336MBR
3528
7
2
C71,C92
33UF
Venkel
TA0006TCM336MBR
3528
9
1
C91
220UF
Kemet
T494B227M004AT
399-4631-1-ND
SM_C_3528_21
10
4
D1,D2,D4,D5
Grn
Panasonic
LN1371G
P491CT-ND
LED_gull
11
9
D3,D6,D7,D8,D9,
D10,D11,
Red
Lumex
LN1271RAL
P493CT-ND
LED_gull
D12,D13
12
4
D14,D15,D16,D17
Yel
Panasonic
LN1471YTR
P11125CT-ND
LED_gull
13
1
D18
BAT54S
Fairchild
BAT54S
BAT54SFSCTND
SOT23
Rev. 0.6
17
Si537x-EVB
Table 5. Si537x-EVB Bill of Materials (Continued)
Item Qty
Reference
Part
16
20
J1,J2,J5,J6,J13,J14 SMA_EDGE
,J18,J23,J26,J31,J
34,J35,J46,J48,J55
,J56,J64,J65,J66,J
67
17
2
J3,J60
Jmpr_3pin
18
1
J4
Phoenix_2_
screw
20
9
J8,J15,J24,J32,J40
,
J41,J42,J57,J58
Jmpr_1pin
21
16
J9,J10,J11,J12,J19, SMA_VERT
J20,J21,J22,J27,J2
8,J29,J30,J36,J37,
J38,J39
23
2
J44,J45
unshrouded
_Header
26
1
J50
Jmpr_2pin
27
2
J51,J62
28
1
29
Mfgr
Mfr Part Num
Johnson
142-0701-801
BOM
Digikey
Footprint
J502-ND
SMA_EDGE_
p062
3pin_p1pitch
Phoenix
MKDSN 1.5/2-5.08
277-1247-ND
Phoenix2pinM_
p2pitch
1pin_p1pitch
Johnson
142-0701-211
J494-ND
SMA_VERT
3M
2380-6121TG
2380-6121TG-ND
28pin thru hole
header
10_M_Head
er_SMT
Samtec
HTST-105-01-lm-dv-a
J61
USB
FCI
61729-0010BLF
609-1039-ND
USB_typeB
1
J63
SMT
Sullins
GZC36SABN-M30
S1033-36-ND
6pin_m_smt
30
6
L1,L2,L3,L4,L5,L7
Ferrite
Venkel
FBC1206-471H
1206
31
1
L6
Ferrite
Steward
HI1612X560R-10
1612
32
3
Q1,Q2,Q3
BSS138
On Semi
BSS138LT1G
33
14
R1,R12,R13,R29,
R30,R31,R32,R34,
R36,R37,R38,R49,
R61,R77,R87, R90,
R23,R62,R85,R92
0
Venkel
CR0603-16W-000T
603
35
25
R6,R7,R8,R9,R10,
R11,R14,R15,R16,
R17,R19,R21,R25,
R26,R27,R28,R43,
R48,R51,R52,R53,
R54,R55,R56,R64
49.9
Venkel
CR0603-16W-49R9FT
603
37
4
R33,R42,R65,R76
1K
Venkel
CR0603-16W-1001FT
603
38
1
R35, R86, R94
100
Venkel
CR0603-16W-1000FT
603
18
Rev. 0.6
10pinMdualHea
der_p1pitch_smt
BSS138LT10SCT
-ND
SOT23
Si537x-EVB
Table 5. Si537x-EVB Bill of Materials (Continued)
Item Qty
Reference
Part
Mfgr
Mfr Part Num
BOM
Digikey
Footprint
39
13
R39,R41,R45,R46,
R57,R59,R67,R69,
R70,R75,R78,R84,
R88
10k
Venkel
CR603-16W-1002FT
603
40
7
R40,R44,R47,R63,
R74,R80,R81
10
Venkel
CR0603-16W-10R0FT
603
41
1
R50
R10x4
Panasonic
EXB-38V100JV
Y9100CT-ND
1206x4
42
4
R66,R68,R71,R72
R150x4
Panasonic
EXB-38V151JV
Y9151CT-ND
1206x4
43
1
R73
150
Venkel
CR0603-16W-1500FT
603
44
1
R79
113
Venkel
CR0603-16W-1130FT
603
45
2
R82,R91
4.99K
Venkel
CR0603-16W-4991FT
603
46
2
R83,R93
1.5K
Venkel
CR0603-16W-1501FT
603
48
1
R89
66.5
Venkel
CR0603-16W-66R5FT
603
49
1
SW1
NO
Mountain
Switch
101-0161-EV
51
1
U1
Si537x
Silicon
Labs
Si537x
10x10 mm BGA
52
1
U2
M95040
ST Micro
M95040-WMN6P
SOIC-8
53
1
U3
TPS76201
TI
TPS76201DBVT
296-11013-1-ND
SOT23-5
56
1
U6
PCA9306
TI
PCA9306DCTR-ND
296-18509-1-ND
SM8
57
1
U7
Si530_2.5V
PECL
Silicon
Labs
530EB121M109DG
5x7 mm
59
1
U9
DS2411
Maxim/
Dallas
DS2411P
TSOC-6
60
2
U10,U11
74LCX541
Fairchild
74LCX541MTC_NL
61
1
U12
XC2C128
Xilinx
XC2C128-7VQG100I
VQG100
63
1
U14
Si8051F340
Silicon
Labs
C8051F340-GQ
TQFP-48
64
2
U15,U16
SN65220
TI
SN65220DBVT
296-9694-1-ND
SOT23-6
65
1
U17
FAN1540B
Fairchild
FAN1540BPMX
FAN1540BMPXC
T-ND
MLP6
66
1
X1
114.285 MH
z
TXC
7MA1400014
4
spacer
SPC Technology
2397
4
screw
Richco
NSS-4-4-01
1010161(mouser)
TC74LCX541FTF
CT-ND
4pin Switch
TSSOP-20
xtal_3p2by2p5
4
1
C53
10NF
Venkel
C0603X7R160-103KNE
NOPOP
603
8
6
C77,C78,C80,C81,
C98,C102
100N
Venkel
C0603X7R160-104KNE
NOPOP
603
Rev. 0.6
19
Si537x-EVB
Table 5. Si537x-EVB Bill of Materials (Continued)
Item Qty
Reference
Part
Mfgr
Mfr Part Num
BOM
Digikey
Footprint
Fairchild
BAT54S
NOPOP
BAT54SFSCTND
SOT23
14
2
D19,D20
BAT54S
19
5
J7,J16,J17,J25,J33
Jmpr_2pin
NOPOP
22
3
J43,J53,J54
Jmpr_4pin
NOPOP
4pin_p1pitch
24
2
J47,J52
Jmpr_6pin
NOPOP
6pin_p1pitch
25
2
J49,J59
Jmpr_3pin
NOPOP
3pin_p1pitch
34
14
R2,R3,R4,R5,R18,
R20,R22,
0 ohm
Venkel
CR0603-16W-000T
Note: install R58 for
Si5374-EVB, install R60
for Si5375-EVB
NOPOP
603
36
1
R24
1K
Venkel
CR0603-16W-1001FT
NOPOP
603
50
8
TP1,TP2,TP3,TP4,
TP5,TP6,
test_points
none
none
NOPOP
Silicon
Labs
Si5326C-C-GM
NOPOP
TP7,TP8
54
1
U4
Si5326
55
1
U5
LTC4311
58
1
U8
Si500
Silicon
Labs
62
1
U13
XO, 3.2 by
2.5
Pericom
67
1
—
heatsink
Aavid
Thermalloy
20
LinearTech LTC4311ISC6#TRMPBF
NOPOP LTC4311CSC6#T
RMPBFCT-ND
QFN-36
SC70
NOPOP
3x5 mm_6pin
FKB420001
NOPOP
3x2 mm
375324B00035G
NOPOP
10x10 mm
Rev. 0.6
Si537x-EVB
9. Layout
Contact Silicon Labs to obtain the Allegro Board file.
Rev. 0.6
21
Si537x-EVB
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3

Various changes to accommodate 1.8 V operation.
Revision 0.3 to Revision 0.4

Removed software installation instructions and
directed reader to refer to release CD or download
from Silicon Labs web site.
Revision 0.4 to Revision 0.5

Changed U7 to LVPECL, part number
Si530EB121M109G.
 Installed 100  resistors at R94 and R86.
Revision 0.5 to Revision 0.6

Added Si5376.
 Updated " Description" on page 1.
22
Rev. 0.6
Si537x-EVB
NOTES:
Rev. 0.6
23
Si537x-EVB
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
24
Rev. 0.6
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement