datasheet for CY29948AXI by Cypress Semiconductor

CY29948

2.5 V or 3.3 V, 200-MHz,

1:12 Clock Distribution Buffer

2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer

Features

■

2.5 V or 3.3 V operation

■

200-MHz clock support

■

LVPECL or LVCMOS/LVTTL clock input

■

LVCMOS-/LVTTL-compatible inputs

■

12 clock outputs: drive up to 24 clock lines

■

Synchronous Output Enable

■

Output three-state control

■

150 ps typical output-to-output skew

■

Pin compatible with MPC948, MPC948L, MPC9448

■

Available in Commercial and Industrial temp. range

■

32-pin TQFP package

Block Diagram

VDD

PECL_CLK

PECL_CLK#

TCLK

TCLK_SEL

SYNC_OE

TS#

0

1

Description

The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a

LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 12 outputs are LVCMOS or LVTTL compatible and can drive 50

series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of

1:24. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.

The CY29948 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated.

VDDC

12

Q0-Q11

Pin Configuration

TCLK_SEL

TCLK

PECL_CLK

PECL_CLK#

SYNC_OE

TS#

VDD

VSS

1

6

7

8

4

5

2

3

CY29948

24

23

22

21

20

19

18

17

VSS

Q4

VDDC

Q5

VSS

Q6

VDDC

Q7

Cypress Semiconductor Corporation

• 198 Champion Court

Document Number: 38-07288 Rev. *E

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised May 2, 2011

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CY29948

Pin Description

[1]

Pin

3

4

2

9, 11, 13, 15,

17, 19, 21, 23,

25, 27, 29, 31

1

Name

PECL_CLK

PECL_CLK#

TCLK

Q(11:0)

TCLK_SEL

PWR

–

–

–

VDDC

I/O

I, PU PECL Input Clock

Description

I, PD PECL Input Clock

I, PU External Reference/Test Clock Input

O

Clock Outputs

5

6

SYNC_OE

TS#

–

–

–

I, PU Clock Select Input. When LOW, PECL clock is selected. When HIGH

TCLK is selected.

I, PU Output Enable Input. When asserted HIGH, the outputs are enabled.

When set LOW the outputs are disabled in a LOW state.

I, PU Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled.

–

2.5 V or 3.3 V Power Supply for Output Clock Buffers

10, 14, 18, 22,

26, 30

7

8, 12, 16, 20,

24, 28, 32

VDDC

VDD

VSS

–

–

–

– 2.5 V or 3.3 V Power Supply

–

Common Ground

Output Enable/Disable

The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When

SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown

in Figure 1 .

Figure 1. SYNC_OE Timing Diagram

TCLK

SYNC_OE

Q

Note

1. PD = Internal pull-down, PU = Internal pull-up.

Document Number: 38-07288 Rev. *E Page 2 of 10

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CY29948

Maximum Ratings

[2]

Maximum Input Voltage Relative to V

SS

............. V

SS

– 0.3 V

Maximum Input Voltage Relative to V

DD

............. V

DD

+ 0.3 V

Storage Temperature ............................... –65 °C to + 150 °C

Operating Temperature............................... –40 °C to +85 °C

Maximum ESD protection............................................... 2 kV

Maximum Power Supply................................................ 5.5 V

Maximum Input Current ............................................. ±20 mA

DC Parameters

This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, V in

and V out

should be constrained to the range:

V

SS

< (V in

or V out

) < V

DD

Unused inputs must always be tied to an appropriate logic voltage level (either V

SS

or V

DD

).

V

DD

= V

DDC

= 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range.

V

Parameter

IL

Description

Input Low Voltage

Conditions

V

DD

= 3.3 V, PECL_CLK single ended

V

DD

= 2.5 V, PECL_CLK single ended

All other inputs

V

IH

I

I

I

I

Z

IL

IH

V

V

V

V

PP

DDQ

DD

C

CMR

OL

OH out in

Input High Voltage V

DD

= 3.3 V, PECL_CLK single ended

V

DD

= 2.5 V, PECL_CLK single ended

All other inputs

Input Low Current

[3]

Input High Current

[3]

Peak-to-Peak Input Voltage

PECL_CLK

Common Mode Range

PECL_CLK

Output Low Voltage

Output High Voltage

[5]

[5]

[4]

V

DD

= 3.3 V

V

DD

= 2.5 V

I

OL

= 20 mA

I

OH

= –20 mA, V

DD

= 3.3 V

Quiescent Supply Current

I

OH

= –20 mA, V

DD

= 2.5 V

Dynamic Supply Current

Output Impedance

V

DD

C

L

= 3.3 V, Outputs @ 100 MHz,

= 30 pF

V

DD

C

L

= 3.3 V, Outputs @ 160 MHz,

= 30 pF

V

DD

C

L

= 2.5 V, Outputs @ 100 MHz,

= 30 pF

V

DD

C

L

= 2.5 V, Outputs @ 160 MHz,

= 30 pF

V

DD

= 3.3 V

V

DD

= 2.5 V

Input Capacitance

Min

1.49

1.10

V

SS

2.135

1.75

2.0

–

–

300

V

DD

– 2.0

V

DD

– 1.2

–

2.5

1.8

–

–

–

–

–

12

14

–

–

5

180

–

–

–

–

–

–

–

–

Typ

–

–

–

–

–

270

125

190

15

18

4

Max

1.825

1.45

0.8

2.42

2.0

V

DD

–100

100

1000

V

DD

– 0.6

V

DD

– 0.6

0.4

–

–

7

–

–

–

–

18

22

–

Unit

V

V

µA mV

V

V

V mA mA

 pF

Notes

2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.

3. Inputs have pull-up/pull-down resistors that effect input current.

4. The V

CMR

is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V

CMR

range and the input lies within the V

PP

specification.

5. Driving series or parallel terminated 50

 (or 50  to V

DD

/2) transmission lines.

Document Number: 38-07288 Rev. *E Page 3 of 10

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CY29948

AC Parameters

[6]

V

DD

= V

DDC

= 3.3 V ± 10% or 2.5 V ± 5%, over the specified operating range.

F

T

Parameter

max pd

Description

Input Frequency

[7]

V

DD

= 3.3 V

V

DD

= 2.5 V

V

DD

= 3.3 V

Conditions

F outDC t pZL

, t pZH t pLZ

, t pHZ

T skew

T skew(pp)

PECL_CLK to Q Delay

[7]

TCLK to Q Delay

[7]

PECL_CLK to Q Delay

[7]

TCLK to Q Delay

[7]

Output Duty Cycle

[7, 8, 9]

Output Enable Time (all outputs)

V

DD

= 2.5 V

Measured at V

DD

/2

T

T

T s h r

/T f

Output Disable Time (all outputs)

Output-to-Output Skew

[7, 9]

Part-to-Part Skew

[10]

PECL_CLK to Q

TCLK to Q

Set-up Time

[7, 11]

SYNC_OE to PECL_CLK

SYNC_OE to TCLK

Hold Time

[7, 11]

PECL_CLK to SYNC_OE

TCLK to SYNC_OE

Output Clocks Rise/Fall Time

[9]

0.8 V to 2.0 V, V

DD

= 3.3 V

0.6 V to 1.8 V, V

DD

= 2.5 V

Figure 2. LVCMOS_CLK CY29948 Test Reference for V

CC

= 3.3 V and V

CC

= 2.5 V

Zo = 50 ohm

CY29948 DUT

Zo = 50 ohm

Pulse

Generator

Z = 50 ohm

R

T

= 50 ohm

R

T

= 50 ohm

VTT VTT

–

–

1.0

0.0

45

2

2

–

0.0

1.0

0.20

0.20

Min

–

–

4.0

4.4

6.0

6.4

–

–

–

–

–

–

–

150

–

–

–

–

–

–

–

–

Typ

–

–

1.5

2.0

–

–

55

10

10

250

–

–

1.0

1.3

Max

200

170

8.0

8.9

10.0

10.9

Unit

MHz ns ns ns ns

% ns ns ps ns

Notes

6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.

7. Outputs driving 50

 transmission lines.

8. 50% input duty cycle.

9. See

Figure 2

and

Figure 3 on page 5

.

10. Part-to-Part skew at a given temperature and voltage.

11. Setup and hold times are relative to the falling edge of the input clock.

Document Number: 38-07288 Rev. *E Page 4 of 10

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Figure 3. PECL_CLK CY29948 Test Reference for V

CC

= 3.3 V and V

CC

= 2.5 V

CY29948 DUT

Zo = 50 ohm

Differential

Pulse

Generator

Z = 50 ohm

Zo = 50 ohm

Zo = 50 ohm

R

T

= 50 ohm

VTT

R

T

= 50 ohm

VTT

Figure 4. Propagation Delay (t

PD

) Test Reference

P E C L _ C L K

P E C L _ C L K

V

P P

V

C M R

Q

t

P D

V C C

V C C /2

G N D

Figure 5. LVCMOS Propagation Delay (t

PD

) Test Reference

LVCMOS_CLK

Q t

PD

VCC

VCC /2

GND

VCC

VCC /2

GND

Figure 6. Output Duty Cycle (F outDC

) t

P

VCC

VCC /2

GND

T0

DC = tP / T0 x 100%

CY29948

Document Number: 38-07288 Rev. *E Page 5 of 10

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Figure 7. Output-to-Output Skew tsk(0)

VCC

VCC /2

GND

VCC

VCC /2

GND t

SK(0)

Ordering Information

Part Number

CY29948AC

CY29948ACT

Pb-free

CY29948AXC

CY29948AXCT

CY29948AXI

CY29948AXIT

Package Type

32-pin TQFP

32-pin TQFP - Tape and Reel

Production Flow

Commercial, 0 °C to +70 °C

Commercial, 0 °C to +70 °C

32-pin TQFP

32-pin TQFP - Tape and Reel

32-pin TQFP

32-pin TQFP - Tape and Reel

Commercial, 0 °C to +70 °C

Commercial, 0 °C to +70 °C

Industrial, –40 °C to +85 °C

Industrial, –40 °C to +85 °C

Ordering Code Definitions

CY 29948 A X X T

T = Tape and Reel; blank = Tube

Temperature: X = C or I

C = Commercial; I = Industrial

X = Pb-free

Package: A = 32-pin TQFP

Device part number

Company ID: CY = Cypress

CY29948

Document Number: 38-07288 Rev. *E Page 6 of 10

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Package Drawing and Dimensions

CY29948

51-85063 *C

Document Number: 38-07288 Rev. *E Page 7 of 10

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Acronyms

Acronym

CMOS

ESD

I/O

LVCMOS

LVPECL

LVTTL

PLL

TQFP

Description

complementary metal oxide semiconductor electrostatic Discharge input/output low voltage complementary metal oxide semiconductor low voltage positive emitter coupled logic low voltage transistor-transistor logic phase locked loop thin quad flat pack

Document Conventions

Units of Measure

pF ps

V

µA mA mm mV ns



%

Symbol

°C kV

MHz degree Celsius kilo Volts

Mega Hertz micro Amperes milli Amperes milli meter milli Volts nano seconds ohms percent pico Farad pico seconds

Volts

Unit of Measure

CY29948

Document Number: 38-07288 Rev. *E Page 8 of 10

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CY29948

Document Revision History

Document Title: CY29948, 2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer

Document Number: 38-07288

Rev.

ECN No.

Submission

Date

Orig. of

Change

Description of Change

**

*A

*B

*C

*D

*E

111099

116782

122880

428221

2904731

3246222

02/13/02

08/14/02

12/22/02

See ECN

04/05/10

05/02/2011

BRK

RBI

RGL

New datasheet

HWT Added Commercial Temperature Range

Added power up requirements to Maximum Ratings

Added Lead-free devices

CXQ Removed inactive part numbers - CY29948AI and CY29948AIT. Updated package diagram.

CXQ

Added Ordering Code Definitions

.

Added Acronyms and Units of Measure .

Updated in new template.

Document Number: 38-07288 Rev. *E Page 9 of 10

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CY29948

Sales, Solutions, and Legal Information

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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .

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© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-07288 Rev. *E Revised May 2, 2011

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