Infineon CY8C4024FNI-S412T Microcontroller Data Sheet

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PSoC 4: PSoC 4000S Datasheet

Programmable System-on-Chip (PSoC)

General Description

PSoC

Arm

®

®

4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.

The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4000S products are upward compatible with members of the PSoC 4 platform for new applications and design needs.

Features

32-bit MCU Subsystem

■ 48-MHz Arm Cortex-M0+ CPU with single-cycle multiply

■ Up to 32 KB of flash with Read Accelerator

■ Up to 4 KB of SRAM

Programmable Analog

■ Single-slope 10-bit ADC function provided by Capacitance sensing block

■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

■ Two low-power comparators that operate in Deep Sleep low-power mode

Programmable Digital

Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs

Low-Power 1.71-V to 5.5-V Operation

■ Deep Sleep mode with operational analog and 2.5 µA digital system current

Capacitive Sensing

■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance

■ Cypress-supplied software component makes capacitive sensing design easy

■ Automatic hardware tuning (SmartSense™)

LCD Drive Capability

LCD segment drive capability on GPIOs

Serial Communication

■ Two independent run-time reconfigurable Serial

Communication Blocks (SCBs) with re-configurable I or UART functionality

2

C, SPI,

Timing and Pulse-Width Modulation

■ Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks

■ Center-aligned, Edge, and Pseudo-random modes

■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

Up to 36 Programmable GPIO Pins

■ 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin

TQFP, and 25-ball WLCSP packages

■ Any GPIO pin can be CapSense, analog, or digital

■ Drive modes, strengths, and slew rates are programmable

Clock Sources

■ 32-kHz Watch Crystal Oscillator (WCO)

■ ±2% Internal Main Oscillator (IMO)

■ 32-kHz Internal Low-power Oscillator (ILO)

ModusToolbox™ Software

■ Comprehensive collection of multi-platform tools and software libraries

■ Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CapSense

PSoC Creator Design Environment

■ Integrated development environment (IDE) provides schematic design entry and build, with analog and digital automatic routing

■ Application programming interface (API) Components for all fixed-function and programmable peripherals

Industry-Standard Tool Compatibility

■ After schematic entry, development can be done with

Arm-based industry-standard development tools

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 002-00123 Rev. *N

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised December 23, 2020


Development Ecosystem

PSoC 4 MCU Resources

Cypress provides a wealth of data at www.cypress.com

to help you select the right PSoC device and quickly and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 4 MCU:

■ Overview: PSoC Portfolio , PSoC Roadmap

■ Product Selectors: PSoC 4 MCU

■

❐

❐

❐

❐

❐

❐

❐

Application Notes cover a broad range of topics, from basic to advanced level, and include the following:

❐ AN79953 : Getting Started With PSoC 4. This application note has a convenient flow chart to help decide which IDE to use:

ModusToolbox™ Software

or

PSoC Creator .

AN91184 : PSoC 4 BLE - Designing BLE Applications

AN88619: PSoC 4 Hardware Design Considerations

AN73854 : Introduction To Bootloaders

AN89610: Arm Cortex Code Optimization

AN86233 : PSoC 4 MCU Power Reduction Techniques

AN57821: Mixed Signal Circuit Board Layout

AN85951 : PSoC 4, PSoC 6 CapSense Design Guide

■ Code Examples demonstrate product features and usage, and are also available on Cypress GitHub repositories .

■ Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC 4 MCU architecture and registers.

■ PSoC 4 MCU Programming Specification provides the information necessary to program PSoC 4 MCU nonvolatile memory.

■ Development Tools

❐

❐

❐

❐

❐

ModusToolbox™ Software

enables cross platform code development with a robust suite of tools and software libraries.

PSoC Creator

is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC 3, PSoC

4, PSoC 5LP, and PSoC 6 MCU based systems. Applications are created using schematic capture and over 150 pre-verified, production-ready peripheral Components.

CY8CKIT-145-40XX PSoC 4000S CapSense Prototyping

Kit, is a low-cost and easy-to-use evaluation platform. This kit provides easy access to all the device I/Os in a breadboard-compatible format.

MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.

PSoC 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also available.

■ Training Videos are available on a wide range of topics including the PSoC 4 MCU 101 series .

■ Cypress Developer Community enables connection with fellow PSoC developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC 4 MCU Community .

Document Number: 002-00123 Rev. *N Page 2 of 42


ModusToolbox™ Software

ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is:

■

Comprehensive - it has the resources you need

■

Flexible - you can use the resources in your own workflow

■

Atomic - you can get just the resources you want

Cypress provides a large collection of code repositories on GitHub , including:

■

Board Support Packages (BSPs) aligned with Cypress kits

■

Low-level resources, including a peripheral driver library (PDL)

■

Middleware enabling industry-leading features such as CapSense

■

An extensive set of thoroughly tested code example applications

ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox, as

Figure 1 shows. For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and

AN79953: Getting Started with PSoC 4 .

Figure 1. ModusToolbox Software Tools



PSoC Creator

PSoC Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concurrently, based on

PSoC 4 MCU. As Figure 2 shows, with PSoC Creator you can:

1. Drag and drop Component icons to build your hardware system design in the main design workspace

2. Co-design your application firmware with the PSoC hardware, using the PSoC Creator IDE C compiler

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

6. Prototype your solution with the PSoC 4 Pioneer kits. If a design change is needed, PSoC Creator and Components enable you to make changes on-the-fly without the need for hardware revisions.

Figure 2. Multiple-Sensor Example Project in PSoC Creator

1

2

3

4

5



Logic Block Diagram

PSoC 4000S

Architecture

32-bit

AHB- Lite

System Resources

Lite

Power

Sleep Control

WIC

POR REF

PWRSYS

Clock

Clock Control

WDT

ILO IMO

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

Analog DFT

CPU Subsystem

SWD/TC

Cortex

M0+

48 MHz

FAST MUL

NVIC, IRQMUX

SPCIF

FLASH

32 KB

Read Accelerator

SRAM

4 KB

SRAM Controller

Peripherals

PCLK

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

ROM

8 KB

ROM Controller

High Speed I/ O Matrix & 2x Programmable I/O

Power Modes

Active/ Sleep

DeepSleep

I/O Subsystem

PSoC 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.

The Arm Serial-Wire Debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.

The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4100S devices. The SWD interface is fully compatible with industry-standard third-party tools. The PSoC 4000S provides a level of security not possible with multi-chip application solutions or with microcontrollers.

It has the following advantages:

■ Allows disabling of debug features

■ Robust flash protection

■ Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

36x GPIOs, LCD

The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore,

PSoC 4000S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC 4000S allows the customer to make.



Functional Description

PSoC 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.

The ARM Serial-Wire Debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.

The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4000S devices. The SWD interface is fully compatible with industry-standard third-party tools. The PSoC 4000S family provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following advantages:

■

Allows disabling of debug features

■

Robust flash protection

■

Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore,

PSoC 4000S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC 4000S allows the customer to make.



Contents

Functional Definition ........................................................ 8

CPU and Memory Subsystem ..................................... 8

System Resources ...................................................... 8

Analog Blocks .............................................................. 9

Programmable Digital Blocks ...................................... 9

Fixed Function Digital .................................................. 9

GPIO ......................................................................... 10

Special Function Peripherals ..................................... 10

Pinouts ............................................................................ 11

Alternate Pin Functions ............................................. 12

Power ............................................................................... 14

Mode 1: 1.8 V to 5.5 V External Supply .................... 14

Mode 2: 1.8 V ±5% External Supply .......................... 14

Electrical Specifications ................................................ 15

Absolute Maximum Ratings ....................................... 15

Device Level Specifications ....................................... 16

Analog Peripherals .................................................... 19

Digital Peripherals ..................................................... 23

Memory ..................................................................... 26

System Resources .................................................... 26

Ordering Information ...................................................... 29

Packaging ........................................................................ 31

Package Diagrams .................................................... 32

Acronyms ........................................................................ 36

Document Conventions ................................................. 38

Units of Measure ....................................................... 38

Document History Page ................................................. 39

Sales, Solutions, and Legal Information ...................... 42

Worldwide Sales and Design Support ....................... 42

Products .................................................................... 42

PSoC® Solutions ...................................................... 42

Cypress Developer Community ................................. 42

Technical Support ..................................................... 42



Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0+ CPU in the PSoC 4000S is part of the 32-bit

MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of the Thumb-2 instruction set.

It includes a nested vectored interrupt controller (NVIC) block with eight interrupt inputs and also includes a Wakeup Interrupt

Controller (WIC). The WIC can wake the processor from Deep

Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4000S has four breakpoint

(address) comparators and two watchpoint (data) comparators.

Flash

The PSoC 4000S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS) access time at 48 MHz.

The flash accelerator delivers 85% of single-cycle SRAM access performance on average.

SRAM

Four KB of SRAM are provided with zero wait-state access at

48 MHz.

SROM

A supervisory ROM that contains boot and configuration routines is provided.

System Resources

Power System

The power system is described in detail in the section Power on page 14

. It provides assurance that voltage levels are as required for each respective mode and either delays mode entry

(for example, on power-on reset (POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection). The PSoC 4000S operates with a single external supply over the range of either 1.8 V ±5%

(externally regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are managed by the power system. The PSoC 4000S provides

Active, Sleep, and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes 35 µs.

Clock System

The PSoC 4000S clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that there are no metastable conditions.

The clock system for the PSoC 4000S consists of the internal main oscillator (IMO), internal low-frequency oscillator (ILO), a

32 kHz Watch Crystal Oscillator (WCO) and provision for an external clock. Clock dividers are provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to enable clocking of higher data rates for UARTs.

The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals. There are eight clock dividers for the PSoC 4000S, two of those are fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, and is fully supported in

PSoC Creator.

Figure 3. PSoC 4000S MCU Clocking Architecture

IMO HFCLK

Divide By

2,4,8

External Clock

HFCLK

ILO

Prescaler

Integer

Dividers

Fractional

Dividers

6X 16-bit

2X 16.5-bit

SYSCLK

LFCLK

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4000S. It is trimmed during testing to achieve the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance with Cypress-provided calibration settings is ±2%.

ILO Clock Source

The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy.

Cypress provides a software component, which does the calibration.

Watch Crystal Oscillator (WCO)

The PSoC 4000S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can be used for precision timing applications. The WCO block allows locking the IMO to the 32-kHz oscillator. The WCO on PSoC 4000S series devices does not connect to the LFCLK or WDT. Due to this, RTC functionality is not supported.



Watchdog Timer

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause register, which is firmware readable.

Reset

The PSoC 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.

Voltage Reference

The PSoC 4000S reference system generates all internally required references. A 1.2-V voltage reference is provided for the comparator. The IDACs are based on a ±5% reference.

Analog Blocks

Low-power Comparators (LPC)

The PSoC 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event. The LPC outputs can be routed to pins.

Current DACs

The PSoC 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges.

Analog Multiplexed Buses

The PSoC 4000S has two concentric independent buses that go around the periphery of the chip. These buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources (IDACs, comparator) to connect to any pin on the I/O Ports.

Programmable Digital Blocks

The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs.

Fixed Function Digital

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC 4000S.

Serial Communication Block (SCB)

The PSoC 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART functionality.

I

2

C Mode : The hardware I

2

C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a mailbox address range in the memory of the PSoC 4000S and effectively reduces I

2

C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the

CPU not having read data on time.

The I

2

C peripheral is compatible with the I and user manual (UM10204). The I with GPIO in open-drain modes.

2

2

C Standard-mode and

Fast-mode devices as defined in the NXP I

2

C-bus specification

C bus I/O is implemented

The PSoC 4000S is not completely compliant with the I

2 in the following respect:

C spec

■

I

GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the

2

C system.

UART Mode : This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.

SPI Mode : The SPI mode supports full Motorola SPI, TI SSP

(adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.



GPIO

The PSoC 4000S has up to 36 GPIOs. The GPIO block implements the following:

■

■

❐

❐

❐

❐

❐

❐

❐

❐

Eight drive modes:

Analog input mode (input and output buffers disabled)

Input only

Weak pull-up with strong pull-down

Strong pull-up with weak pull-down

Open drain with strong pull-down

Open drain with strong pull-up

Strong pull-up with strong pull-down

Weak pull-up with weak pull-down

Input threshold select (CMOS or LVTTL).

■

Individual control of input and output buffer enabling/disabling in addition to the drive strength modes

■

Selectable slew rates for dV/dt related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 2 and 3). During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4000S).

Special Function Peripherals

CapSense

CapSense is supported in the PSoC 4000S through a CapSense

Sigma-Delta (CSD) block that can be connected to any pins through an analog multiplex bus via analog switches. CapSense function can thus be provided on any available pin or group of pins in a system under software control. A PSoC Creator component is provided for the CapSense block to make it easy for the user.

Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented.

The CapSense block has two IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available).

The CapSense block also provides a 10-bit Slope ADC function, which can be used in conjunction with the CapSense function.

The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise.

LCD Segment Drive

The PSoC 4000S has an LCD controller, which can drive up to

8 commons and up to 28 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal

LCD voltages. The two methods used are referred to as Digital

Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN

(cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays.



Pinouts

The following table provides the pin list for PSoC 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the 48-TQFP.

Table 1. PSoC 4000S Pin List

48-pin TQFP

Pin

28

29

30

31

32

7

8

5

6

3

4

1

2

45

46

47

48

41

42

43

44

9

10

12

13

14

16

37

38

39

40

33

34

35

36

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P2.7

VSSD

P3.0

P3.1

P3.2

P3.3

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDDD

VDDA

18

19

20

21

32-pin QFN

Pin

17

Name

P0.0

22

23

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

24

25

26

27

27

28

29

30

31

32

1

2

3

4

5

6

7

8

9

10

11

12

P1.7

P2.0

P2.1

P2.2

P2.3

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

XRES

VCCD

VSSD

VDD

VDD

VSSA

P1.0

P1.1

P1.2

P1.3

21

21

22

18

19

20

1

2

3

15

16

17

24-pin QFN

Pin

13

14

Name

P0.0

P0.1

4

5

23

24

6

7

8

P0.4

P0.5

P0.6

XRES

VCCD

VSSD

VDD

VDD

VSSA

P1.2

P1.3

P1.7

P2.0

P2.1

P2.6

P2.7

P3.0

P3.2

P3.3

B2

B3

A1

A2

C2

C1

B1

A3

A3

A2

A4

B4

E5

D4

E4

D3

D5

C4

A2

25-ball CSP

Pin

D1

C3

Name

P0.0

P0.1

A5

B5

C5

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSS

VDD

VDD

VSS

P1.2

P1.3

P1.7

P2.0

P2.1

P2.6

P2.7

VSS

P3.0

P3.1

P3.2

P3.3

P2.7

VSSD

P3.0

P3.1

P3.2

P3.3

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

8

9

10

11

12

13

6

7

4

5

2

3

40

1

36

37

38

39

32

33

34

35

27

28

29

30

31

23

24

25

26

40-pin QFN

Pin

22

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VDDD

VDDA

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

27

27

28

29

24

25

26

30

31

32

9

10

11

12

6

7

8

3

4

1

2

5

18

19

20

21

32-pin TQFP

Pin

17

Name

P0.0

22

23

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

XRES

VCCD

VSSD

VDD

VDD

VSSA

P1.0

P1.1

P1.2

P1.3

P1.7

P2.0

P2.1

P2.2

P2.3

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3



Table 1. PSoC 4000S Pin List (continued)

48-pin TQFP

Pin

21

22

23

24

25

17

18

19

20

Name

P3.4

P3.5

P3.6

P3.7

VDDD

P4.0

P4.1

P4.2

P4.3

32-pin QFN

Pin Name

13

14

15

16

P4.0

P4.1

P4.2

P4.3

24-pin QFN

Pin Name

9

10

11

12

P4.0

P4.1

P4.2

P4.3

25-ball CSP

Pin Name

E3

D2

E2

E1

P4.0

P4.1

P4.2

P4.3

18

19

20

21

40-pin QFN

Pin Name

14

15

16

17

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

32-pin TQFP

Pin Name

13

14

15

16

P4.0

P4.1

P4.2

P4.3

Note: Pins 11, 15, 26, and 27 are No connects (NC) on the 48-pin TQFP.

Descriptions of the pin functions are as follows:

VDDD : Power supply for the digital section.

VDDA : Power supply for the analog section.

VSSD, VSSA : Ground pins for the digital and analog sections respectively.

VCCD : Regulated digital supply (1.8 V ±5%)

VDD: Power supply to all sections of the chip

VSS: Ground for all sections of the chip

Alternate Pin Functions

Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin assignments are shown in the following table.

Table 2. Pin Assignments

Port/

Pin

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

Analog lpcomp.in_p[0] lpcomp.in_n[0] lpcomp.in_p[1] lpcomp.in_n[1] wco.wco_in

wco.wco_out

Smart I/O

P1.1

P1.2

P1.3

P1.4

Alternate Function 1 Alternate Function 2 Alternate Function 3 tcpwm.tr_in[0] tcpwm.tr_in[1]

Deep Sleep 1 Deep Sleep 2 scb[0].spi_select1:0 scb[0].spi_select2:0 scb[0].spi_select3:0 srss.ext_clk

tcpwm.line[2]:1 scb[1].uart_rx:0 scb[1].uart_tx:0 scb[1].uart_cts:0 scb[1].uart_rts:0 scb[0].uart_rx:1 tcpwm.line_compl[2]:1 scb[0].uart_tx:1 scb[1].i2c_scl:0 scb[1].i2c_sda:0 scb[0].i2c_scl:0 scb[0].i2c_sda:0 scb[1].spi_mosi:1 scb[1].spi_miso:1 scb[1].spi_clk:1 scb[1].spi_select0:1 scb[0].spi_mosi:1 scb[0].spi_miso:1 tcpwm.line[3]:1 tcpwm.line_compl[3]:1 scb[0].uart_cts:1 scb[0].uart_rts:1 tcpwm.tr_in[2] tcpwm.tr_in[3] scb[0].spi_clk:1 scb[0].spi_select0:1 scb[0].spi_select1:1



Table 2. Pin Assignments (continued)

Port/

Pin

P1.5

Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2 scb[0].spi_select2:1

P1.6

scb[0].spi_select3:1

P1.7

P2.0

prgio[0].io[0] tcpwm.line[4]:0 csd.comp

tcpwm.tr_in[4] scb[1].i2c_scl:1 scb[1].spi_mosi:2

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

csd.vref_ext

csd.cshieldpads

csd.cmodpad

P4.3

csd.csh_tank

prgio[0].io[1] prgio[0].io[2] prgio[0].io[3] prgio[0].io[4] prgio[0].io[5] prgio[0].io[6] prgio[0].io[7] prgio[1].io[0] prgio[1].io[1] tcpwm.line_compl[4]:0 tcpwm.line[0]:1 tcpwm.line_compl[0]:1 tcpwm.line[1]:1 tcpwm.line_compl[1]:1 tcpwm.line[0]:0 tcpwm.line_compl[0]:0 scb[1].uart_rx:1 scb[1].uart_tx:1 prgio[1].io[2] prgio[1].io[3] prgio[1].io[4] prgio[1].io[5] prgio[1].io[6] prgio[1].io[7] tcpwm.line[1]:0 tcpwm.line_compl[1]:0 tcpwm.line[2]:0 tcpwm.line_compl[2]:0 tcpwm.line[3]:0 tcpwm.line_compl[3]:0 scb[1].uart_cts:1 scb[1].uart_rts:1 scb[0].uart_rx:0 scb[0].uart_tx:0 scb[0].uart_cts:0 scb[0].uart_rts:0 tcpwm.tr_in[5] scb[1].i2c_sda:1 scb[1].spi_miso:2 scb[1].spi_clk:2 scb[1].spi_select0:2 scb[1].spi_select1:1 scb[1].spi_select2:1 scb[1].spi_select3:1 lpcomp.comp[0]:1 scb[1].i2c_scl:2 scb[1].i2c_sda:2 scb[1].spi_mosi:0 scb[1].spi_miso:0 tcpwm.tr_in[6] tcpwm.tr_in[7] tcpwm.tr_in[8] tcpwm.tr_in[9] tcpwm.tr_in[10] tcpwm.tr_in[11] cpuss.swd_data

cpuss.swd_clk

scb[1].spi_clk:0 scb[1].spi_select0:0 scb[1].spi_select1:0 scb[1].spi_select2:0 scb[1].spi_select3:0 lpcomp.comp[1]:1 scb[0].i2c_scl:1 scb[0].i2c_sda:1 lpcomp.comp[0]:0 scb[0].spi_mosi:0 scb[0].spi_miso:0 scb[0].spi_clk:0 lpcomp.comp[1]:0 scb[0].spi_select0:0



Power

The following power system diagram shows the set of power supply pins as implemented for the PSoC 4000S. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the V

DD input.

Figure 4. Power Supply Connections

Mode 1: 1.8 V to 5.5 V External Supply

In this mode, the PSoC 4000S is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC 4000S supplies the internal logic and its output is connected to the V

CCD

pin. The VCCD pin must be bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.

VDDA

VDDA

VSSA

Analog

Domain

Digital

Domain

1.8 Volt

Regulator

VDDD

VSSD

VCCD

VDDD

Mode 2: 1.8 V ±5% External Supply

In this mode, the PSoC 4000S is powered by an external power supply that must be within the range of 1.71 to 1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins are shorted together and bypassed. The internal regulator can be disabled in the firmware.

Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.

An example of a bypass scheme is shown in the following diagram.

There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Figure 5. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Power supply bypass connections example

1.8V to 5.5V

0.1

 F

V

DD

PSoC 4000S

V

DDA

 F

1.8V to 5.5V

0.1

 F

V

CCD

0.1

 F

V

SS



Electrical Specifications

Absolute Maximum Ratings

Table 3. Absolute Maximum Ratings

[1]

Spec ID# Parameter

SID1

SID2

SID3

SID4

SID5

BID44

BID45

BID46

V

V

DDD_ABS

CCD_ABS

Description

Digital supply relative to V

SS

Direct digital core voltage input relative to V

SS

GPIO voltage V

GPIO_ABS

I

GPIO_ABS

Maximum current per GPIO

I

GPIO_injection

GPIO injection current, Max for

V

IH

> V

DDD

, and Min for V

IL

< V

SS

ESD_HBM Electrostatic discharge human body model

ESD_CDM Electrostatic discharge charged device model

LU Pin current for latch-up

Min

–0.5

–0.5

–0.5

–25

–0.5

2200

500

–140

–

–

–

Typ

–

–

–

–

–

Max

6

1.95

V

DD

+ 0.5

25

0.5

Units Details/Conditions

V –

–

– mA –

Current injected per pin

–

–

140

V

–

– mA –

Note

1. Usage above the absolute maximum conditions listed in Table 3

may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.



Device Level Specifications

All specifications are valid for –40 °C  T except where noted.

A

 105 °C and T

J

 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

Table 4. DC Specifications

Typical values measured at V

DD

= 3.3 V and 25 °C.


SID53 V

DD

Description

Power supply input voltage

Min

1.8

Typ

–

Max

5.5

SID255 V

DD

Power supply input voltage

(V

CCD

= V

DD

= V

DDA

)

Output voltage (for core logic)

1.71

– 1.89

SID54

SID55

SID56

V

CCD

C

EFC

C

EXC

External regulator voltage bypass

Power supply bypass capacitor

–

–

–

1.8

0.1

1

–

–

–

Active Mode, V

DD

= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

SID10 I

DD5

Execute from flash;

CPU at 6 MHz

– 1.2

2.0

SID16 I

DD8

– 2.4

4.0

SID19 I

DD11

Execute from flash;

CPU at 24 MHz

Execute from flash;

CPU at 48 MHz

– 4.6

5.9

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

SID22 I

DD17

I

2

C wakeup WDT, and

Comparators on

SID25 I

DD20

I

2

C wakeup, WDT, and

Comparators on

Sleep Mode, V

DDD

= 1.71 V to 1.89 V (Regulator bypassed)

SID28 I

DD23

I

2

C wakeup, WDT, and

Comparators on

SID28A I

DD23A

I

2

C wakeup, WDT, and

Comparators on

–

–

–

–

Deep Sleep Mode, V

DD

= 1.8 V to 3.6 V (Regulator on)

SID31 I

DD26

I

2

C wakeup and WDT on


DD

= 3.6 V to 5.5 V (Regulator on)

SID34 I

DD29

I

2

C wakeup and WDT on

–

–


DD

= V

CCD

= 1.71 V to 1.89 V (Regulator bypassed)

SID37 I

DD32

I

2

C wakeup and WDT on –

XRES Current

1.1

1.4

0.7

0.9

2.5

2.5

2.5

1.6

1.9

0.9

1.1

60

60

60

SID307 I

DD_XR

Supply current while XRES asserted

– 2 5


V Internally regulated supply

Internally unregulated supply

–

µF X5R ceramic or better

X5R ceramic or better mA – mA 6 MHz mA 6 MHz mA 12 MHz

µA –

µA –

µA – mA

–

–

12 MHz

–

Table 5. AC Specifications

Spec ID#

SID48

SID49

[2]

SID50

[2]

Parameter

F

CPU

T

SLEEP

T

DEEPSLEEP

Description

CPU frequency

Wakeup from Sleep mode

Wakeup from Deep Sleep mode

Min

DC

–

–

Typ

–

0

35

Max

48

–

–


MHz 1.71  V

DD

 5.5

µs –

–

Note

2. Guaranteed by characterization.



GPIO

Table 6. GPIO DC Specifications

Spec ID#

SID57

SID58

SID241

SID242

SID243

SID244

SID59

Parameter

V

IH

[3]

V

IL

V

IH

[3]

V

IL

V

IH

[3]

V

IL

V

OH

Description

Input voltage high threshold

Input voltage low threshold

LVTTL input, V

DDD

< 2.7 V

LVTTL input, V

DDD

< 2.7 V

LVTTL input, V

DDD

 2.7 V

LVTTL input, V

DDD

 2.7 V

Output voltage high level

SID60 Output voltage high level

SID61

V

OH

V

OL

Output voltage low level

SID62

SID62A

SID63

SID64

SID65

SID66

SID67

[4]

SID68

[4]

SID68A

[4]

SID69

[4]

SID69A

[4]

Min

0.7 



V

DDD

–

0.7 



V

DDD

–

2.0

–

V

DDD

– 0.6

V

DDD

–

– 0.5

V

OL

V

OL



–

–

I

I

R

R

IL

PULLUP

PULLDOWN

C

IN

V

HYSTTL

V

HYSCMOS

V

HYSCMOS5V5

I

DIODE

TOT_GPIO

Pull-up resistor

Pull-down resistor

Input leakage current (absolute value)

Input capacitance

3.5

3.5

–

–

Input hysteresis LVTTL

Input hysteresis CMOS

Input hysteresis CMOS

Current through protection diode to V

DD

/V

SS

Maximum total source or sink chip current

25

0.05 × V

DDD

200

–

–

–

–

–

40

–

5.6

5.6

–

–

–

–

–

–

–

–

–

–

Typ

–

–

–

Max

–

0.3 



V

DDD

–

0.3 



V

DDD

–

0.8

–

–

0.6

0.6

0.4

8.5

8.5

2


V CMOS Input

CMOS Input

–

–

–

–

I

OH

= 4 mA at 3 V V

DDD

I

OH

= 1 mA at 3 V V

DDD

I

OL

= 4 mA at 1.8 V V

DDD

I

OL

= 10 mA at 3 V V

DDD

I

OL

= 3 mA at 3 V V

DDD kΩ –

– nA 25 °C, V

DDD

= 3.0 V

7

–

–

–

100 pF – mV V

DDD

 2.7 V

V

DD

< 4.5 V

V

DD

> 4.5 V

µA –

200 mA –

Notes

3. V

IH

must not exceed V

DDD

+ 0.2 V.




Table 7. GPIO AC Specifications

(Guaranteed by Characterization)


SID70 T

RISEF

Description

Rise time in fast strong mode

SID71 Fall time in fast strong mode

SID72

T

FALLF

T

RISES

Rise time in slow strong mode

Min

2

2

10

SID73 T

FALLS

Fall time in slow strong mode 10

SID74

SID75

SID76

SID245

SID246

F

F

F

F

F

GPIOUT1

GPIOUT2

GPIOUT3

GPIOUT4

GPIOIN

GPIO F

OUT

; 3.3 V  V

DDD

 5.5 V

Fast strong mode

GPIO F

OUT

; 1.71 V

Fast strong mode

 V

DDD

 3.3 V

GPIO F

OUT

; 3.3 V  V

DDD

 5.5 V

Slow strong mode

GPIO F

OUT

; 1.71 V  V

3.3 V

Slow strong mode.

DDD



GPIO input operating frequency;

1.71 V  V

DDD

 5.5 V

XRES

Table 8. XRES DC Specifications


SID77

SID78

SID79

SID80

SID81

[5]

V

IH

V

IL

R

PULLUP

C

IN

V

HYSXRES

Description

Input voltage high threshold

Input voltage low threshold

Pull-up resistor

Input capacitance

Input voltage hysteresis

–

–

–

–

–

Min

0.7 × V

DDD

–

–

–

–

SID82 I

DIODE

Current through protection diode to V

DD

/V

SS

–

Table 9. XRES AC Specifications

Spec ID#

SID83

[5]

BID194

[5]

Parameter

T

RESETWIDTH

T

RESETWAKE

Description

Reset pulse width

Wake-up time from reset release

Min

1

–

–

–

–

–

–

Typ

–

–

–

–

60

33

16.7

7

3.5

Max

12

12

60

48

Units Details/Conditions ns 3.3 V V

DDD

,

Cload = 25 pF

3.3 V V

DDD

,

Cload = 25 pF

– 3.3 V V

DDD

,

Cload = 25 pF

– 3.3 V V

DDD

,

Cload = 25 pF

MHz 90/10%, 25 pF load,

60/40 duty cycle

90/10%, 25 pF load,

60/40 duty cycle

90/10%, 25 pF load,

60/40 duty cycle

90/10%, 25 pF load,

60/40 duty cycle

90/10% V

IO

Typ

–

–

60

–

100

–

Max

–

0.3  V

DDD

–

7

–

100


V CMOS Input kΩ pF

–

– mV Typical hysteresis is

200 mV for V

DD

> 4.5 V

µA –

Typ

–

–

Max

–

2.7


µs – ms –

Note




Analog Peripherals

Comparator

Table 10. Comparator DC Specifications


SID84

SID85

SID86

SID87

V

OFFSET1

V

OFFSET2

V

HYST

V

ICM1

SID247

SID247A

SID88

SID88A

SID89

SID248

SID259

SID90

I

I

I

V

V

C

C

MRR

MRR

CMP1

CMP2

CMP3

Z

ICM2

ICM3

CMP

Description

Input offset voltage, Factory trim

Input offset voltage, Custom trim

Hysteresis when enabled

Input common mode voltage in normal mode

Input common mode voltage in low power mode

Input common mode voltage in ultra low power mode

Common mode rejection ratio

Common mode rejection ratio

Block current, normal mode

Block current, low power mode

Block current in ultra low-power mode

DC Input impedance of comparator

Table 11. Comparator AC Specifications


SID91 TRESP1

SID258

SID92

TRESP2

TRESP3

Description

Response time, normal mode,

50 mV overdrive

Response time, low power mode,

50 mV overdrive

Response time, ultra-low power mode, 200 mV overdrive

Min

–

–

–

0

0

Min

–

–

–

0

–

–

50

42

–

35

Typ

38

70

2.3

Typ

–

–

10

–

–

–

–

–

–

–

6

–

Max

±10

±4

35

V

DDD

– 0.1

Units Details/Conditions mV –

–

–

V Modes 1 and 2

V

DDD

V

DDD

– 1.15

–

–

400

100

28

–

–

V

DDD

≥ 2.2 V at

–40 °C dB V

DDD

≥ 2.7V

V

DDD

≤ 2.7V

µA –

–

V

DDD

≥ 2.2 V at

–40 °C

MΩ –

Max

110

200

15

Units Details/Conditions ns –

–

µs V

DDD

≥ 2.2 V at

–40 °C



CSD and IDAC

Table 12. CSD and IDAC Specifications

SPEC ID#

SYS.PER#3

SYS.PER#16

Parameter

VDD_RIPPLE

VDD_RIPPLE_1.8

SID.CSD.BLK ICSD

SID.CSD#15 V

REF

SID.CSD#15A V

REF_EXT

SID.CSD#16 IDAC1IDD

SID.CSD#17 IDAC2IDD

SID308 VCSD

SID308A

SID309

SID310

SID311

SID312

SID313

SID314

SID314A

SID314B

SID314C

SID314D

SID314E

SID315

V

COMPIDAC

IDAC1DNL

IDAC1INL

IDAC2DNL

IDAC2INL

SNR

IDAC1CRT1

IDAC1CRT2

IDAC1CRT3

IDAC1CRT12

IDAC1CRT22

IDAC1CRT32

IDAC2CRT1

Description

Max allowed ripple on power supply, DC to 10 MHz

Max allowed ripple on power supply, DC to 10 MHz

Maximum block current

Voltage reference for CSD and

Comparator

External Voltage reference for

CSD and Comparator

IDAC1 (7-bits) block current

IDAC2 (7-bits) block current

Voltage range of operation

Voltage compliance range of

IDAC

DNL

INL

DNL

INL

Ratio of counts of finger to noise.

Guaranteed by characterization

0.6

–1

–2

–1

–2

5

0.6

0.6

–

–

1.71

Output current of IDAC1 (7 bits) in low range

Output current of IDAC1(7 bits) in medium range

Output current of IDAC1(7 bits) in high range

Output current of IDAC1 (7 bits) in low range, 2X mode

Output current of IDAC1(7 bits) in medium range, 2X mode

Output current of IDAC1(7 bits) in high range, 2X mode

Output current of IDAC2 (7 bits) in low range

Min

–

–

–

4.2

34

275

8

69

540

4.2

–

–

–

–

Typ

–

Max

±50

– ±25 mV V

DD

> 1.75V (with ripple), 25 °C T

P

) < 20 pF,

A

,

Parasitic Capacitance

(C

Sensitivity ≥ 0.4 pF

– 4000 µA Maximum block current for both

IDACs in dynamic

(switching) mode including comparators, buffer, and reference generator.

1.2

V

DDA

- 0.6 V V

DDA

– 0.6 or 4.4, whichever is lower

– V

DDA

- 0.6

V V

DDA


– 1750 µA –

–

–

1750

5.5

Units Details/Conditions mV V

DD

> 2 V (with ripple), 25 °C T

A

,

Sensitivity = 0.1 pF

–

–

–

–

–

–

–

V

DDA

0.6

1

2

1

2

–

5.4

–

µA –

V 1.8 V ±5% or 1.8 V to

5.5 V

V V

DDA


LSB –

LSB INL is ±5.5 LSB for

V

DDA

< 2 V

LSB –

LSB INL is ±5.5 LSB for

V

DDA

< 2 V

Ratio Capacitance range of

5 to 35 pF, 0.1-pF sensitivity. All use cases. V

DDA

> 2 V.

µA LSB = 37.5-nA typ.

–

–

41

330

µA

µA

LSB = 300-nA typ.

LSB = 2.4-µA typ.

10.5

82

660

5.4

µA

µA

µA

µA

LSB = 75-nA typ.

LSB = 600-nA typ.

LSB = 4.8-µA typ.

LSB = 37.5-nA typ.



SID321

SID322

SID322A

SID322B

SID323

SID324

SID325

Table 12. CSD and IDAC Specifications (continued)

SPEC ID#

SID315A

SID315B

SID315C

SID315D

SID315E

SID315F

SID315G

SID315H

SID320

Parameter

IDAC2CRT2

IDAC2CRT3

IDAC2CRT12

IDAC2CRT22

IDAC2CRT32

IDAC3CRT13

IDAC3CRT23

IDAC3CRT33

IDACOFFSET

Description

Output current of IDAC2 (7 bits) in medium range

Output current of IDAC2 (7 bits) in high range

Output current of IDAC2 (7 bits) in low range, 2X mode

Output current of IDAC2(7 bits) in medium range, 2X mode

Output current of IDAC2(7 bits) in high range, 2X mode

Output current of IDAC in 8-bit mode in low range

Output current of IDAC in 8-bit mode in medium range

Output current of IDAC in 8-bit mode in high range

All zeroes input

69

540

8

69

Min

34

275

8

540

–

IDACGAIN Full-scale error less offset

IDACMISMATCH1 Mismatch between IDAC1 and

IDAC2 in Low mode


IDAC2 in Medium mode


IDAC2 in High mode

IDACSET8 Settling time to 0.5 LSB for 8-bit

IDAC

IDACSET7

CMOD

Settling time to 0.5 LSB for 7-bit

IDAC

External modulator capacitor.

–

–

–

–

–

–

–

–

–

2.2

–

–

–

–

–

–

–

–

Typ

–

–

–

–

–

10

10

–

±10

9.2

5.6

6.8

82

660

10.5

82

Max

41

330

10.5

660

1


µA LSB = 300-nA typ.

µA LSB = 2.4-µA typ.




µA LSB = 37.5-nA typ.



LSB Polarity set by Source or Sink. Offset is 2

LSBs for 37.5 nA/LSB mode

% –

LSB LSB = 37.5-nA typ.

LSB LSB = 300-nA typ.

LSB LSB = 2.4-µA typ.

µs Full-scale transition.

No external load.

µs Full-scale transition.

No external load.

nF 5-V rating, X7R or

NP0 cap.



10-bit CapSense ADC

Table 13. 10-bit CapSense ADC Specifications

Spec ID#

SIDA94

Parameter

A_RES Resolution

Description

SIDA95

SIDA97

SIDA98

A_CHNLS_S Number of channels - single ended

A-MONO Monotonicity

A_GAINERR Gain error

SIDA99 A_OFFSET Input offset voltage

SIDA100

SIDA101

SIDA103

SIDA104

SIDA106

A_ISAR

A_VINS

A_INRES

A_INCAP

A_PSRR

SIDA110

SIDA111

SIDA112

A_BW

A_INL

A_DNL

Current consumption

Input voltage range - single ended

Input resistance

Input capacitance

Power supply rejection ratio

SIDA107

SIDA108

A_TACQ

A_CONV8

SIDA108A A_CONV10

SIDA109 A_SND

Sample acquisition time

Conversion time for 8-bit resolution at conversion rate =

Fhclk/(2^(N+2)). Clock frequency

= 48 MHz.

Conversion time for 10-bit resolution at conversion rate =

Fhclk/(2^(N+2)). Clock frequency

= 48 MHz.

Signal-to-noise and Distortion ratio (SINAD)

–

–

–

–

Input bandwidth without aliasing

Integral Non Linearity. 1 ksps

Differential Non Linearity. 1 ksps

–

V

SSA

–

–

–

–

–

–

Min

–

–

–

–

–

Typ

–

–

–

–

–

–

–

2.2

20

60

1

–

–

61

–

–

–

Max

10

16

–

±2

3

0.25

V

DDA

–

–

–

–

21.3

85.3

–

22.4

2

1

Units Details/Conditions bits Auto-zeroing is required every millisecond

Defined by AMUX

Bus.

Yes –

% In V

REF

(2.4 V) mode with V

DDA

bypass capacitance of 10 µF mV In V

REF

(2.4 V) mode with V

DDA

bypass capacitance of 10 µF mA –

V –

KΩ – pF – dB In V

REF

(2.4 V) mode with V

DDA

bypass capacitance of 10 µF

µs –

µs Does not include acquisition time.

Equivalent to

44.8 ksps including acquisition time.

µs Does not include acquisition time.

Equivalent to

11.6 ksps including acquisition time.

dB With 10-Hz input sine wave, external 2.4-V reference, V

REF

(2.4 V) mode kHz 8-bit resolution

LSB V

REF

= 2.4 V or greater

LSB –



Digital Peripherals

Timer Counter Pulse-Width Modulator (TCPWM)

Table 14. TCPWM Specifications

Spec ID

SID.TCPWM.1

Parameter

ITCPWM1

SID.TCPWM.2

SID.TCPWM.2A ITCPWM3

SID.TCPWM.3

ITCPWM2

TCPWM

FREQ

Description

Block current consumption at

3 MHz


12 MHz


48 MHz

Operating frequency

SID.TCPWM.4

Input trigger pulse width

SID.TCPWM.5

TPWM

ENEXT

TPWM

EXT

Output trigger pulse widths

SID.TCPWM.5A TC

RES

SID.TCPWM.5B PWM

RES

SID.TCPWM.5C Q

RES

Resolution of counter

PWM resolution

Quadrature inputs resolution

Min

–

–

–

–

2/Fc

2/Fc

Typ

–

–

–

–

–

–

1/Fc

1/Fc

1/Fc

–

–

–

Max

45

155

650

Fc

–

–

–

–

–


µA All modes (TCPWM)

All modes (TCPWM)

All modes (TCPWM)

MHz Fc max = CLK_SYS

Maximum = 48 MHz ns For all trigger events

[6]

Minimum possible width of Overflow,

Underflow, and CC

(Counter equals

Compare value) outputs

Minimum time between successive counts

Minimum pulse width of PWM Output

Minimum pulse width between Quadrature phase inputs

Note

6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.



I

2

C

Table 15. Fixed I

2

C DC Specifications

[7]

Spec ID

SID149

SID150

SID151

SID152 I

I

I

Parameter

I

I2C1

I2C2

I2C3

I2C4

Description


100 kHz


400 kHz


1 Mbps

I

2

C enabled in Deep Sleep mode

Table 16. Fixed I

2

C AC Specifications

[7]

Spec ID

SID153 F

Parameter

I2C1

Bit rate

Description

SPI

Table 17. SPI DC Specifications

[7]

Spec ID

SID163

SID164

SID165

Parameter

ISPI1

ISPI2

ISPI3

Description


1 Mbps


4 Mbps


8 Mbps

Table 18. SPI AC Specifications

[7]

Spec ID

SID166

Parameter

FSPI

Description

SPI operating frequency (Master;

6X Oversampling)

Fixed SPI Master Mode AC Specifications

SID167 TDMO MOSI Valid after SClock driving edge

SID168 TDSI

SID169 THMO

MISO Valid before SClock capturing edge

Previous MOSI data hold time

Fixed SPI Slave Mode AC Specifications

SID170 TDMI MOSI Valid before Sclock

Capturing edge

SID171

SID171A

SID172

SID172A

TDSO

TDSO_EXT

MISO Valid after Sclock driving edge

MISO Valid after Sclock driving edge in Ext. Clk mode

Previous MISO data hold time THSO

TSSELSSCK SSEL Valid to first SCK Valid edge

Min

–

–

–

–

Min

–

Min

–

–

–

Min

–

–

20

0

40

–

–

0

100

Typ

–

Typ

–

Typ

–

–

–

–

Typ

–

–

–

Max

50

135

310

1.4

Max

1

Max

360

560

600

Max

8


µA –

Units

Msps –

Units

µA

–

–

–

–

–

–

Details/Conditions



MHz –

–

–

–

15

–

– ns –

Full clock, late MISO sampling

Referred to Slave capturing edge

–

–

–

–

–

–

42 + (3 × Tcpu)

48

–

– ns –

– ns –

T

CPU

= 1/F

CPU

–

Note




UART

Table 19. UART DC Specifications

[8]

Spec ID

SID160

SID161 I

Parameter

I

UART1

UART2

Description


100 Kbps


1000 Kbps

Table 20. UART AC Specifications

[8]

Spec ID

SID162 F

Parameter

UART

Bit rate

Description

LCD Direct Drive

Table 21. LCD Direct Drive DC Specifications

[8]

Spec ID

SID154

SID155

SID156

SID157

SID158

I

I

Parameter

I

LCDLOW

C

LCDCAP

LCD

OFFSET

LCDOP1

LCDOP2

Description

Operating current in low power mode

LCD capacitance per segment/common driver

Long-term segment offset

LCD system operating current

Vbias = 5 V

LCD system operating current

Vbias = 3.3 V

Table 22. LCD Direct Drive AC Specifications

[8]

Spec ID

SID159 F

Parameter

LCD

Description

LCD frame rate

Min

–

–

Min

–

–

–

–

Min

–

–

Min

10

Typ

–

–

Typ

–

Max

55

312


µA –

µA –

20

2

2

Typ

5

500

–

–

–

Max

–

5000


µA 16  4 small segment disp. at 50 Hz pF – mV – mA 32  4 segments.

50 Hz. 25 °C

32  4 segments.

50 Hz. 25 °C

Typ

50

Max

1

Max

150


Mbps –


Hz –

Note




Memory

Flash

Table 23. Flash DC Specifications

Spec ID

SID173 V

Parameter

PE

Description

Erase and program voltage

Min

1.71

Typ

–

Max

5.5


V –

Table 24. Flash AC Specifications

Spec ID

SID174

SID175

SID176

SID178

SID180

[10]

SID181

[10]

SID182

[10]

SID182A

SID182B

SID256

[10]

[10]

Parameter

T

ROWWRITE

[9]

T

T

T

T

ROWERASE

[9]

ROWPROGRAM

[9]

BULKERASE

[9]

DEVPROG

[9]

F

END

F

RET

–

F

RETQ

TWS48

Description

Row (block) write time

(erase and program)

Row erase time

Row program time after erase

Bulk erase time (32 KB)

Total device program time

Flash endurance

Flash retention.

T

A

 55 °C, 100 K P/E cycles.

Flash retention.

T

A

 85 °C, 10 K P/E cycles.

Flash retention.

T

A

≤ 105 °C, 10 K P/E cycles,

≤ three years at T

A

≥ 85 °C.

Number of Wait states at 48 MHz

SID257 TWS24 Number of Wait states at 24 MHz

Min

–

–

–

–

–

100 K

20

10

10

2

1

Typ

–

–

–

–

–

–

–

–

–

–

–

System Resources

Power-on Reset (POR)

Table 25. Power On Reset (PRES)

Spec ID Parameter Description

SID.CLK#6 SR_POWER_UP Power supply slew rate

SID185

[10]

SID186

[10]

V

RISEIPOR

V

FALLIPOR

Rising trip voltage

Falling trip voltage

Min

1

0.80

0.70

Typ

–

–

–

Max

20

16

4

35

7

–

–

–

20

–

–

Max

67

1.5

1.4

Units Details/Conditions ms Row (block) =

128 bytes

–

–

–

Seconds –

Cycles –

Years –

–

Guaranteed by

Characterization

CPU execution from

Flash

CPU execution from

Flash


V/ms At power-up and power-down

V –

–

Table 26. Brown-out Detect (BOD) for V

CCD

Spec ID

SID190

[10]

SID192

[10]

V

V

Parameter

FALLPPOR

FALLDPSLP

Description

BOD trip voltage in active and sleep modes

BOD trip voltage in Deep Sleep

Min

1.48

1.11

Typ

–

–

Max

1.62

1.5


V –

–

Notes

9. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.




SWD Interface

Table 27. SWD Interface Specifications

Spec ID

SID213

Parameter

F_SWDCLK1

Description

3.3 V  V

DD

 5.5 V

SID214 F_SWDCLK2 1.71 V  V

DD

 3.3 V

SID215

[11]

SID216

[11]

SID217

[11]

SID217A

[11]

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

Internal Main Oscillator (IMO)

Table 28. IMO DC Specifications

(Guaranteed by Design)

Spec ID

SID218

SID219

Parameter

I

IMO1

I

IMO2

Description

IMO operating current at 48 MHz

IMO operating current at 24 MHz

Min

–

–

Min

–

–

0.25 × T

0.25 × T

–

1

Typ

–

–

Typ

–

–

–

–

–

–

Table 29. IMO AC Specifications

Spec ID

SID223

SID223A

SID226

SID228

Parameter

F

IMOTOL1

T

T

STARTIMO

JITRMSIMO2

Description

Frequency variation at 24, 32, and 48 MHz (trimmed)

IMO startup time

RMS jitter at 24 MHz

Internal Low-Speed Oscillator (ILO)

Table 30. ILO DC Specifications

(Guaranteed by Design)

Spec ID

SID231

[11]

Parameter

I

ILO1

Description

ILO operating current

Table 31. ILO AC Specifications

Spec ID

SID234

[11]

SID236

[11]

SID237

Parameter

T

STARTILO1

T

ILODUTY

F

ILOTRIM1

Description

ILO startup time

ILO duty cycle

ILO frequency range

Min

–

–

–

–

Min

–

Min

–

40

20

Typ

–

–

–

145

Typ

0.3

Typ

–

50

40

Max

14

7

–

–

0.5 × T

–


MHz SWDCLK ≤ 1/3 CPU clock frequency ns –

–

SWDCLK ≤ 1/3 CPU clock frequency

–

–

Max

250

180

Max

±2

±2.5

7

–

Max

1.05

Max

2

60

80


µA –

µA –


% –

% 105 °C

µs – ps –


µA –

Units Details/Conditions ms –

% – kHz –

Note




Watch Crystal Oscillator (WCO)

Table 32. Watch Crystal Oscillator (WCO) Specifications


SID398 FWCO

SID399

SID400

FTOL

ESR

SID401

SID402

SID403

SID404

SID405

PD

TSTART

CL

C0

IWCO1

SID406 IWCO2

Description

Crystal Frequency

Frequency tolerance

Equivalent series resistance

Drive Level

Startup time

Crystal Load Capacitance

Crystal Shunt Capacitance

Operating Current (high power mode)

Operating Current (low power mode)

External Clock

Table 33. External Clock Specifications

Spec ID

SID305

[12]

SID306

[12]

Parameter

ExtClkFreq

ExtClkDuty

Description

External clock input frequency

Duty cycle; measured at V

DD/2

Clock

Table 34. Clock Specs

Spec ID

SID262

[12]

T

Parameter

CLKSWITCH

Description

System clock source switching time

Min

0

45

Min

3

Smart I/O Pass-through Time

Table 35. Smart I/O Pass-through Time (Delay in Bypass Mode)

Spec ID#

SID252

Parameter Description

PRG_BYPASS Max delay added by Smart I/O in bypass mode

Min

–

6

–

–

–

–

Min

–

–

–

–

Typ

32.768

50

50

–

–

–

1.35

–

–

Typ

–

–

Typ

–

Typ

–

Max

–

250

–

1

500

12.5

–

8

1

Max

48

55


MHz –

% –

Max

4

Max

1.6

Units Details/Conditions kHz – ppm With 20-ppm crystal kΩ –

µW – ms – pF – pF –

µA –

µA

Units

–

Periods –


Units Details/Conditions ns –

Note



Ordering Information

The PSoC 4000S part numbers and features are listed in the following table.

Table 36. PSoC 4000S Ordering Information

Features

Category MPN


Package

4024

4025

4045

CY8C4024FNI-S402 24 16

CY8C4024LQI-S401 24 16

CY8C4024LQI-S402 24 16

CY8C4024AXI-S402 24 16

CY8C4024LQI-S403 24 16

CY8C4024AZI-S403 24 16

CY8C4024FNI-S412 24 16

CY8C4024LQI-S411 24 16

CY8C4024LQI-S412 24 16

CY8C4024AXI-S412 24 16

CY8C4024LQI-S413 24 16

CY8C4024AZI-S413 24 16

CY8C4024AZQ-S413 24 16

CY8C4025FNI-S402 24 32

CY8C4025LQI-S401 24 32

CY8C4025LQI-S402 24 32

CY8C4025AXI-S402 24 32

CY8C4025LQI-S403 24 32

CY8C4025AZI-S403 24 32

CY8C4025AZQ-S403 24 32

CY8C4025FNI-S412 24 32

CY8C4025LQI-S411 24 32

CY8C4025LQI-S412 24 32

CY8C4025AXI-S412 24 32

CY8C4025LQI-S413 24 32

CY8C4025AZI-S413 24 32

CY8C4025AZQ-S413 24 32

CY8C4045FNI-S412 48 32

CY8C4045LQI-S411 48 32

CY8C4045LQI-S412 48 32

CY8C4045AXI-S412 48 32

CY8C4045LQI-S413 48 32

CY8C4045AZI-S413 48 32

CY8C4045AZQ-S413 48 32

4

4

4

4

4

4

4

4

2

4

2

2

2

2

2

2

2

2

2

2

2

2

4

4

4

4

4

4

4

4

4

4

4

4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

2

2

8 21 ✔

8 19

2 16 27

2 16 27

2

2

2 16 34

2 16 36

8 21 ✔

8 19

2 16 27

2 16 27

2 16 34

2 16 36

2 16 36

2

2

8 21

8 19

✔

2 16 27

2 16 27

2 16 34

2

2

2 16 36

2 16 36

8 21 ✔

8 19

2 16 27

2 16 27

2 16 34

2 16 36

2 16 36

2

2

8 21 ✔

8 19

2 16 27

2 16 27

2 16 34

2 16 36

2 16 36

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

✔

–40 to 85 °C

✔

✔ –40 to 105 °C

–40 to 85 °C

✔

✔ –40 to 105 °C

–40 to 85 °C

✔

✔ –40 to 105 °C

–40 to 85 °C

✔

✔ –40 to 105 °C



The nomenclature used in the preceding table is based on the following part numbering convention:

Table 37. Nomenclature

Field

CY8C

4

A

B

C

DE

F

S

XYZ

Description

Cypress Prefix

Architecture

Family

CPU Speed

Flash Capacity

Package Code

Temperature Range

Series Designator

Attributes Code

Values

4

0

2

PV

FN

I

Q

S

M

L

BL

000-999

7

AX

AZ

LQ

5

6

4

4

Meaning

PSoC 4

4000 Family

24 MHz

48 MHz

16 KB

32 KB

64 KB

128 KB

TQFP (0.8-mm pitch)

TQFP (0.5-mm pitch)

QFN

SSOP

CSP

Industrial

Extended Industrial

PSoC 4 S-Series

PSoC 4 M-Series

PSoC 4 L-Series

PSoC 4 BLE-Series

Code of feature set in the specific family

The following is an example of a part number:

CY8C 4 A B C DE F – S XYZ Example

4: PSoC 4

4: 48 MHz

5: 32 KB

I: Industrial

Cypress Prefix

Architecture

Family within Architecture

CPU Speed

Flash Capacity

Package Code

Temperature Range

Silicon Family

Attributes Code



Packaging

The PSoC 4000S is offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages.

Package dimensions and Cypress drawing numbers are in the following table.

Table 38. Package List

Spec ID#

BID20

BID27

BID34A

BID34

BID34G

BID34F

Package

48-pin TQFP

40-pin QFN

32-pin QFN

Description

7 × 7 × 1.4 mm height with 0.5-mm pitch



24-pin QFN

32-pin TQFP



25-ball WLCSP 2.02 × 1.93 × 0.48 mm height with 0.35-mm pitch

Package Dwg

51-85135

001-80659

001-42168

001-13937

51-85088

002-09957

Table 39. Package Thermal Characteristics

T

JC

T

JA

T

JC

T

JA

T

JC

Parameter

T

A

T

J

T

JA

T

T

T

T

T

T

JA

JC

JA

JC

JA

JC

Package θ

JA

Package θ

JC

Package θ

JA

Package θ

JC

Package θ

JA

Package θ

JC

Description

Operating ambient temperature

Operating junction temperature

Package θ

JA

Package θ

JC

Package θ

JA

Package θ

JC

Package θ

JA

Package θ

JC

–

–

Package

48-pin TQFP

48-pin TQFP

40-pin QFN

40-pin QFN

32-pin QFN

32-pin QFN

24-pin QFN

24-pin QFN

32-pin TQFP

32-pin TQFP

25-ball WLCSP

25-ball WLCSP

Table 40. Solder Reflow Peak Temperature

Package

All

Maximum Peak

Temperature

260 °C

Maximum Time at Peak Temperature

30 seconds

–

–

–

–

–

–

–

–

–

–

–

Min

–40

–40

–

–

–

–

–

–

–

–

–

–

–

–

Max

105

125

–

21.7

5.6

29.4

3.5

40

0.5

Typ

25

–

73.5

33.5

17.8

2.8

20.8

5.9

Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020

Package

All except WLCSP

25-ball WLCSP

MSL

MSL 3

MSL 1

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

Units

°C

°C

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W



Package Diagrams

Figure 6. 48-pin TQFP (7 × 7 × 1.4 mm) Package Outline, 51-85135

51-85135 *C

Figure 7. 40-pin QFN (6 × 6 × 0.6 mm) Package Outline, 001-80659


001-80659 *A

Page 32 of 42


Figure 8. 32-pin QFN ((5.0 × 5.0 × 0.55 mm) 3.5 × 3.5 mm E-Pad (Sawn)) Package Outline, 001-42168

SEE NOTE 1

TOP VIEW

BOTTOM VIEW

SIDE VIEW

DIMENSIONS

D2

E

E2

L

A

A1

A2

D b e

SYMBOL

MIN.

NOM.

MAX.

0.50

-

0.55

0.020

0.60

0.045

4.90

0.15 BSC

5.00

5.10

3.40

4.90

3.50

5.00

3.60

5.10

3.40

0.30

3.50

0.40

3.60

0.50

0.18

0.25

0.50 TYP

0.30

NOTES:

1. HATCH AREA IS SOLDERABLE EXPOSED PAD

2. BASED ON REF JEDEC # MO-248

3. PACKAGE WEIGHT: 0.0388g

4. DIMENSIONS ARE IN MILLIMETERS

001-42168 *F



Figure 9. 24-pin QFN ((4 × 4 × 0.60 mm) 2.65 × 2.65 E-Pad (Sawn)) Package Outline, 001-13937

001-13937 *H

The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.

If not connected to ground, it should be electrically floating and not connected to any other signal.

Figure 10. 32-pin TQFP (7 × 7 × 1.4 mm) Package Outline, 51-85088


51-85088 *E

Page 34 of 42


Figure 11. 25-ball WLCSP (2.02 × 1.93 × 0.48 mm) Package Outline, 002-09957

002-09957 **



Acronyms

Table 42. Acronyms Used in this Document

Acronym abus

ADC

AG

AHB

Description analog local bus analog-to-digital converter analog global

AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus

ALU arithmetic logic unit

AMUXBUS analog multiplexer bus

API

APSR

ARM

®

ATM application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode

BW

CAN

CMRR

CPU

CRC bandwidth

Controller Area Network, a communications protocol common-mode rejection ratio central processing unit

DAC

DFB

DIO cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO.

EMI

EMIF

EOC

EOF

EPSR

ESD

DMIPS

DMA

DNL

DNU

DR

DSI

DWT

ECC

Dhrystone million instructions per second direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers digital system interconnect data watchpoint and trace error correcting code

ECO external crystal oscillator

EEPROM electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame execution program status register electrostatic discharge


Table 42. Acronyms Used in this Document (continued)

MISO

NC

NMI

NRZ

NVIC

NVL opamp

PAL

PC

PCB

LR

LUT

LVD

LVI

LVTTL

MAC

MCU

IIR

ILO

IMO

INL

I/O

IPOR

IPSR

IRQ

Acronym

ETM

FIR

Description embedded trace macrocell finite impulse response, see also IIR

FPB

FS

GPIO flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin high-voltage interrupt, see also LVI, LVD HVI

IC

IDAC integrated circuit current DAC, see also DAC, VDAC

IDE integrated development environment

I

2

C, or IIC Inter-Integrated Circuit, a communications protocol

ITM

LCD

LIN infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell liquid crystal display

Local Interconnect Network, a communications protocol.

link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter printed circuit board

Page 36 of 42


SAR

SC/CT

SCL

SDA

S/H

SINAD

SIO

PWM

RAM

RISC

RMS

RTC

RTL

RTR

RX

PLL

PMDD

POR

PRES

PRS

PS

PSoC

®

PSRR

Acronym

PGA

PHUB

PHY

PICU

PLA

PLD


SOC

SOF

SPI

SR

SRAM

SRES

SWD

SWV

TD

Description programmable gain amplifier peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration datasheet power-on reset precise power-on reset pseudo random sequence port read data register

Programmable System-on-Chip™ power supply rejection ratio pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time

I

2

C serial clock

I

2

C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO.

start of conversion start of frame

Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA



Acronym

THD

TIA

TRM

TTL

TX

UART

UDB

USB

USBIO

VDAC

WDT

WOL

WRES

XRES

XTAL

Description total harmonic distortion transimpedance amplifier technical reference manual transistor-transistor logic transmit

Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block

Universal Serial Bus

USB input/output, PSoC pins used to connect to a

USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal

Page 37 of 42

Document Conventions

Units of Measure

Table 43. Units of Measure

µV

µW mA ms

µA

µF

µH

µs mV nA ns nV

 pF kHz k  ksps

LSB

Mbps

MHz

M 

Msps

°C

Symbol dB fF

Hz

KB kbps

Khr ppm ps s sps sqrtHz

V degrees Celsius

Unit of Measure decibel femto farad hertz

1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt



Page 38 of 42


Document History Page

Description Title: PSoC 4: PSoC 4000S Datasheet, Programmable System-on-Chip (PSoC)

Document Number: 002-00123

Revision

**

*A

ECN

Submission

Date

4883809 08/28/2015 New data sheet.

Description of Change

4992376 10/30/2015 Removed 20-ball WLCSP package related information in all instances across the document.

Added 25-ball WLCSP package related information in all instances across the document.

Updated

Pinouts :

Updated

Table 1

.

Updated

Electrical Specifications

:

Updated

Analog Peripherals :

Updated

Comparator

:

Updated Table 10

(Updated details in “Details/Conditions” column corresponding to V

ICM3

,

I

CMP3

parameters (Added V

TRESP3 parameter (Added V

Updated

CSD and IDAC :

Updated

Table 13 .

Updated

Ordering Information :

Updated part numbers.

DDD

≥ 2.2V at –40 °C)).

Updated

Table 11 (Updated details in “Details/Conditions” column corresponding to

DDD

≥ 2.2V at –40 °C)).

*B

*C

*D

*E

5037826 12/08/2015 Changed status from Advance to Preliminary.

5104369 01/27/2016 Updated

Packaging :

Updated

Table 39 (Replaced TBD with values for Theta J

A

and Theta J

C

parameters).

Updated

Package Diagrams :

Replaced TBD with spec 002-09957 **.

Added Errata.

5139206 02/16/2016 Updated to new template.

*F

5173961 03/15/2016 Updated

Pinouts :

Updated

Table 1

.

Updated


:

Updated

Device Level Specifications :

Updated

XRES :

Updated

Table 8

(Updated all values corresponding to R

PULLUP

parameter).

parameter).

Updated

Table 9

(Updated all values corresponding to T

RESETWAKE

Updated


Updated

CSD and IDAC :

Updated

Table 12 .

Updated

10-bit CapSense ADC :

Updated

Table 13 .

Updated

Memory :

Updated

Flash :

Updated

Table 24 (Updated all values corresponding to T

parameters).

ROWERASE

, T

ROWPROGRAM

5268662 05/12/2016 Updated

Pinouts :

Updated

Alternate Pin Functions

:

Updated

Table 2

.

Updated


:

Updated


Updated

CSD and IDAC :

Updated

Table 12 (Updated all values corresponding to IDAC1INL, IDAC2INL, SNR,

IDAC1CRT1, IDAC1CRT12, IDAC1CRT22, IDAC1CRT32, IDAC2CRT1, IDAC2CRT12,

IDAC2CRT22, IDAC2CRT32, IDACMISMATCH2, IDACMISMATCH3 parameters).

Updated

10-bit CapSense ADC :

Updated

Table 13 (Updated all values corresponding to A_SND parameter).

Removed Errata.

Updated to new template.




(continued)



Revision ECN

Submission

Date


*G

*H

*I

5330930 07/27/2016 Changed status from Preliminary to Final.

Updated

Functional Definition

:

Updated

Special Function Peripherals

:

Updated

LCD Segment Drive :

Updated description.

Updated


:

Updated


Updated

Table 4

I

DD23A

, I

DD26

(Updated details corresponding to I

, I

DD29

, I

DD32

, I

DD_XR

parameters).

DD5

, I

DD8

, I

DD11

, I

DD17

, I

DD20

, I

DD23

Updated

GPIO :

Updated

Table 6

(Updated details in “Details/Conditions” column corresponding to V

OH

, parameter and spec ID SID60).

Updated

Packaging :

Updated

Table 38 (Updated details in “Description” column corresponding to 25-Ball

WLCSP package (Updated package dimensions)).

Updated

Table 41 (Added 25-Ball WLCSP package and its corresponding details).

Completing Sunset Review.

5415365 09/14/2016 Added 40-pin QFN package related information in all instances across the document.

Updated


:

Updated


Updated

Table 4

(Updated details corresponding to I

DD5

, I

DD8

, I

DD11

, I

DD17

, I

DD20

, I

DD23

,

I

DD23A

, I

DD26

, I

DD29

, I

Updated

Packaging :

DD32

, I

DD_XR

Updated

Package Diagrams :

Added spec 001-80659 *A.

parameters).

5561833 01/09/2017 Updated


:

Replaced PRGIO with Smart I/O in all instances.

*J

*K

*L

5704046 04/26/2017 Updated the Cypress Logo and Copyright.

5969745 11/17/2017 Updated Document Title to read as “PSoC

®

4: PSoC 4000S Datasheet Programmable

System-on-Chip (PSoC

®

)”.

Added 32-pin TQFP Package related information in all instance across the document.

Updated



Updated

Packaging :

Updated

Package Diagrams :

spec 001-42168 – Changed revision from *E to *F.

Added spec 51-85088 *E.

6639191 07/31/2019 Updated

Features

:

Updated

32-bit MCU Subsystem :


Added

Development Ecosystem .

Added

PSoC Creator .

Updated

Functional Definition

:

Updated

System Resources

:

Updated

Power System :


Updated

Watch Crystal Oscillator (WCO) :


Updated

Fixed Function Digital :

Updated

Serial Communication Block (SCB) :


Updated

Special Function Peripherals

:

Updated

LCD Segment Drive :





(continued)



Revision ECN

Submission

Date


*L (cont.) 6639191 07/31/2019 Updated

Pinouts :

Added Note below Table 1 .

Updated


:

Updated


Updated

CSD and IDAC :

Updated

Table 12 (Updated details in “Details/Conditions” column corresponding to V

REF

,

V

REF_EXT

and V

COMPIDAC

parameters).

Updated

Digital Peripherals

:

Updated

SPI :

Updated

Table 18 (Updated all values corresponding to TSSELSSCK parameter).

Updated



Updated

Packaging :

Updated

Package Diagrams :

spec 001-13937 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

*M

*N

7026754

11/20/2020 Added Clock Sources and ModusToolbox™ in Features

.

Updated

Development Ecosystem

.

Updated temperature range in


: Added Q-temp MPNs for the

48-TQFP package.

Updated

Table 25 : Updated SID.CLK#6 Description.

Updated

Table 39 : Updated Typ. value for T

JA

25-ball WLCSP.

Updated

Sales, Solutions, and Legal Information

.

7036861 12/23/2020 Updated

Table 37 : Updated Nomenclature to show “Extended Industrial”.



Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .

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®

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®

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

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