Analog Devices ADuC7122 Precision Analog Microcontroller Preliminary Technical Data

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Precision Analog Microcontroller, 12-Bit

Analog I/O, ARM7TDMI

®

MCU

Preliminary Technical Data

ADuC7122

FEATURES

Analog I/O

13 external channel, 12-bit, 1 MSPS ADC

2 channels with programmable gain

PGA (1 to 5) input range

IOVDD power monitor channel

On-chip temperature monitor

11 general-purpose inputs

Fully differential and single-ended modes

0 V to V

REF

analog input range

12 × 12-bit voltage output DACs

On-chip voltage reference: 1.2 V/2.5 V

Buffered output reference sources for use with external circuits

Microcontroller

ARM7TDMI core, 16-bit/32-bit RISC architecture

JTAG port supports code download and debug

Clocking options

Trimmed on-chip oscillator (±3%)

External watch crystal

External clock source up to 41.78 MHz

41.78 MHz PLL with programmable divider

Memory

126 kB Flash/EE memory, 8 kB SRAM

In-circuit download, JTAG-based debug

FUNCTIONAL BLOCK DIAGRAM

Software-triggered in-circuit reprogrammability

On-chip peripherals

UART, 2 × I 2

C and SPI serial I/O

32-pin GPIO port

4× general-purpose timers

Wake-up and watchdog timers (WDT)

Power supply monitor

Vectored interrupt controller for FIQ and IRQ

8 Priority levels for each interrupt type

Interrupt on edge or level external pin inputs

Power

Specified for 3 V operation

Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz

Packages and temperature range

7 mm × 7mm 108-ball BGA

Fully specified for −10°C to +95°C operation

Tools

Low cost QuickStart™ development system

Full third-party support

APPLICATIONS

Optical networking, industrial control, and automation systems

Smart sensors, precision instrumentation, base station systems

Figure 1

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113 www.analog.com

ADuC7122

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 7

Absolute Maximum Ratings .......................................................... 12

ESD Caution ................................................................................ 12

Pin Configuration and Function Descriptions ........................... 13

Terminology .................................................................................... 17

ADC Specifications .................................................................... 17

DAC Specifications..................................................................... 17

Overview of the ARM7TDMI Core ............................................. 18

Thumb Mode (T) ........................................................................ 18

Long Multiply (M) ...................................................................... 18

EmbeddedICE (I) ....................................................................... 18

Exceptions ................................................................................... 18

ARM Registers ............................................................................ 18

Interrupt Latency ........................................................................ 19

Memory Organization ................................................................... 20

Flash/EE Memory ....................................................................... 20

SRAM ........................................................................................... 20

Memory Mapped Registers ....................................................... 20

Complete MMR Listing ............................................................. 21

ADC Circuit Overview .................................................................. 25

ADC Transfer Function ............................................................. 26

Typical Operation ....................................................................... 27

Temperature Sensor ................................................................... 28

Converter Operation .................................................................. 31

Driving the Analog Inputs ........................................................ 32

Band Gap Reference ................................................................... 33

Power Supply Monitor ............................................................... 33

Nonvolatile Flash/EE Memory ..................................................... 34

Flash/EE Memory Overview ..................................................... 34

Flash/EE Memory ....................................................................... 34

Flash/EE Memory Security ....................................................... 35

Flash/EE Control Interface ........................................................ 35

Execution Time from SRAM and FLASH/EE ........................ 38

Reset and Remap ........................................................................ 39

Other Analog Peripherals .............................................................. 40

Rev. PrA | Page 2 of 92

Preliminary Technical Data

DAC .............................................................................................. 40

LDO (Low Dropout Regulator) ................................................ 42

Oscillator and PLL—Power Control ............................................ 43

External Crystal Selection ......................................................... 43

External Clock Selection ........................................................... 43

Power Control System ............................................................... 44

MMRs and Keys ......................................................................... 45

Digital Peripherals .......................................................................... 46

PWM General Overview ........................................................... 46

PWM Convert Start Control .................................................... 48

General-Purpose I/O ..................................................................... 49

UART Serial Interface .................................................................... 52

Baud Rate Generation ................................................................ 52

UART Register Definition ......................................................... 52

C ..................................................................................................... 57

Serial Clock Generation ............................................................ 57

C Bus Addresses ....................................................................... 57

C Registers ................................................................................ 58

C Common registers ............................................................... 66

Serial Peripheral Interface ............................................................. 67

SPIMISO (Master In, Slave Out) Pin ....................................... 67

SPIMOSI (Master Out, Slave In) Pin ....................................... 67

SPICLk (Serial Clock I/O) Pin ................................................. 67

SPI Chip Select (SPI CS Input) Pin .......................................... 67

Configuring External pins for SPI functionality .................... 67

SPI Registers ................................................................................ 68

Programmable Logic Array (PLA) ............................................... 71

Interrupt System ......................................................................... 73

IRQ ............................................................................................... 74

Fast Interrupt Request (FIQ) .................................................... 74

Timers .......................................................................................... 80

Timer0—Lifetime Timer ........................................................... 80

Timer1—General-Purpose Timer ........................................... 82

Timer2—Wake-Up Timer ......................................................... 84

Timer3—Watchdog Timer ........................................................ 86

Timer4—General-Purpose Timer ........................................... 88

Outline Dimensions ....................................................................... 90

Ordering Guide .......................................................................... 90

Preliminary Technical Data ADuC7122

SPECIFICATIONS

= IOV

= 3.0 V to 3.6 V, ±5%, V

REF

= 2.5 V internal reference, f

CORE

= 41.78 MHz, T

= −10°C to +95°C, unless otherwise noted.

Table 1.

Parameter

ADC CHANNEL SPECIFICATIONS

ADC Power-Up Time

DC Accuracy

1, 2

5 μs

Resolution 12 Bits

Integral Nonlinearity ±0.6 ±2 LSB 2.5 V internal reference, not production tested for PADC0/PADC1 channels

Differential Nonlinearity

3, 4

DC Code Distribution

±0.5

+1..4/−0.99 LSB

LSB

2.5 V internal reference, gauranteed monotonic

ADC input is a dc voltage

ENDPOINT ERRORS

Offset Error

Offset Error Match

Gain Error

±2

±1

±5 LSB

LSB

Eight acquisition clocks and fADC/2

Internally unbuffered channels

±2 ±5 LSB

Gain Error Match

DYNAMIC PERFORMANCE

±1 LSB

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel-to-Channel Crosstalk

−78

−75

−80 dB dB dB dB f

= 10 kHz sine wave, f

SAMPLE

= 1 MSPS internally unbuffered channels

Includes distortion and noise components

Measured on adjacent channels

ANALOG INPUT

Input Voltage Ranges

Differential Mode

Single-Ended Mode

Leakage Current

Input Capacitance

0.15

±0.2

6 ± V

REF

/2 V

0 to V

REF

AVdd-1.5 V

μA pF pF

See Table 35 and Table 36

Buffer enabled

During ADC acquisition buffer bypassed

During ADC acquisition buffer enabled

PADC0 Input

Full Scale Input Range 20 1000 μA

28.3 kΩ resistor, PGA gain = 3

Input Leakage at PADC0P

Resolution

Gain Error

11 Bits 0.1% accuracy, 5 ppm external resistor for I to V

Gain Drift 4 ppm/°C

Offset

Offset Drift

PADC0P Compliant Range 0.1

3 6

AVdd-1.2 nA

PGA offset not included

PADC1 Input

Full Scale Input Range

Input Leakage at PADC1P

Resolution

10.6 700 μA

53.5 kΩ resistor, PGA gain = 3

11 Bits 0.1% accuracy, 5 ppm external resistor for I to V

Gain Error

Gain Drift

Offset

3 6

% ppm/°C nA

Offset Drift 4 30

PGA offset not included

PADC1P Compliant Range

ON-CHIP VOLTAGE REFERENCE

Output Voltage

0.1

Accuracy

Reference Temperature Coefficient

2.5

AVdd-1.2

V ppm/°C

Rev. PrA | Page 3 of 92

0.47 μF from V

REF

to AGND

ADuC7122

Parameter

Power Supply Rejection Ratio

Output Impedance

Internal V

REF

Power-On Time

EXTERNAL REFERENCE INPUT

Input Voltage Range

External reference input Leakage current

DAC CHANNEL SPECIFICATIONS

DC Accuracy

1.2

Preliminary Technical Data

1 dB

Ω ms

= 25°C

TBD μA

= 5 kΩ, C

= 100 pF

Buffered

12 Bits

±2

±0.2 ±1

LSB

LSB Guaranteed monotonic

±2

9 mV mV

2.5 V internal reference

Measured at Code 0

Relative Accuracy

Differential Nonlinearity

Calculated Offset Error

Actual Offset Error

Gain Error

Gain Error Mismatch

PSRR

Settling Time

0.1

μs

% of full scale on DAC0

Buffered

1kHz −57 dB

10 kHz −47 dB

−19 100 kHz

OFFSET DRIFT

GAIN ERROR DRIFT

4 dB

SHORT CIRCUIT CURRENT

ANALOG OUTPUTS

Output Range 0.1

20 mA

REF

/AV

−

0.1

DAC AC CHARACTERISTICS

Slew Rate

Voltage Output Settling Time

Digital-to-Analog Glitch Energy

2.49

±20

V/μs

μs nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously change in the

DACxDAT register)

TEMPERATURE SENSOR

Voltage Output at 25°C

Voltage TC

707

−1.25 mV mV/°C

POWER SUPPLY MONITOR (PSM)

IOV

Trip Point Selection 2.79 V measurement

Two selectable trip points

Power Supply Trip Point Accuracy

POWER-ON RESET

WATCHDOG TIMER (WDT)

Timeout Period

±2.5

2.36

0 512

FLASH/EE MEMORY

Endurance

10,000

Data Retention 12 20

Of the selected nominal trip point voltage sec cycles

DIGITAL INPUTS

Logic 1 Input Current

Logic 0 Input Current

Input Capacitance

±0.2

−40

±1

−60

μA

μA pF

All digital inputs excluding XCLKI and XTALO

= V

or V

= 5 V

= 0 V; except TDI

Rev. PrA | Page 4 of 92

Preliminary Technical Data ADuC7122

Parameter

LOGIC INPUTS 4

INL

, Input Low Voltage

INH

, Input High Voltage

2.0

LOGIC OUTPUTS

, Output High Voltage

, Output Low Voltage

CRYSTAL INPUTS XTALI and XTALO

Logic Inputs, XTALI Only

2.4

All logic inputs excluding XTALI

All digital outputs excluding XTALO

V I

SOURCE

= 1.6 mA

0.4

SINK

= 1.6 mA

INL

, Input Low Voltage

INH

, Input High Voltage

XTALI Input Capacitance

XTALO Output Capacitance

INTERNAL OSCILLATOR

1.1

1.7

32.768

V pF pF kHz

MCU CLOCK RATE

From 32 kHz Internal Oscillator

From 32 kHz External Crystal

Using an External Clock

START-UP TIME

At Power-On

From Pause/Nap Mode

From Sleep Mode

From Stop Mode

326

41.78

0.05

3.06

1.58

1.7

PROGRAMMABLE LOGIC ARRAY (PLA)

Pin Propagation Delay

Element Propagation Delay

2.5

POWER REQUIREMENTS

14, 15

Power Supply Voltage Range

to AGND and IOV

to IOGND 2.7

Analog Power Supply Currents

Current

Digital Power Supply Current

IOV

Current in Normal Mode

200

3.6

30 40

IOV

Current in Pause Mode 4 25

IOV

Current in Sleep Mode

100

Additional Power Supply Currents

ADC

DAC

2.7

0.7

250 kHz

MHz

CD = 7

CD = 0

41.78 MHz T

= 95°C ms

Core clock = 41.78 MHz ns

μs ms ms

CD = 0

CD = 7 ns ns

From input pin to output pin

μA mA mA mA mA mA mA

ADC in idle mode

Code executing from Flash/EE

CD = 7

CD = 3

CD = 0 (41.78 MHz clock)

μA T

= 85°C

At 1 MSPS

At 62.5 kSPS

Rev. PrA | Page 5 of 92

ADuC7122 Preliminary Technical Data

Parameter

ESD TESTS 2.5 V reference, T

= 25°C

HBM Passed Up to 4 kV

FCIDM Passed Up to 0.5 kV

All ADC channel specifications are guaranteed during normal MicroConverter core operation.

Apply to all ADC input channels.

3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN); see the the Calibration section.

4 Not production tested but supported by design and/or characterization data on production release.

Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 22. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC Circuit

Overview).

The input signal can be centered on any dc common-mode voltage (V

) as long as this value is within the ADC voltage input range specified.

REF

calibration and trimming are performed with core operating in normal mode CD = 0, ADC on, and all DACs on. V

REF

accuracy may vary under other operating conditions.

8 DAC linearity is calculated using a reduced code range of 100 to 3995.

DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V

REF

Die temperature.

11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

Retention lifetime equivalent at junction temperature (T

) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

Test carried out with a maximum of eight I/Os set to a low output level.

Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with

3.6 V supply, and sleep mode with 3.6 V supply.

IOV

power supply current decreases typically by 2 mA during a Flash/EE erase cycle.

Rev. PrA | Page 6 of 92

Preliminary Technical Data

TIMING SPECIFICATIONS

Table 2. I

C Timing in Fast Mode (400 kHz)

RSU t

PSU t

BUF t

R t

Parameter Description

SCLOCK low pulse width t

H t

SHD t

DSU t

DHD

SCLOCK high pulse width

Start condition hold time

Data setup time

Data hold time

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Table 3. I

C Timing in Standard Mode (100 kHz)

RSU t

PSU t

BUF t

R t

Parameter Description

SCLOCK low pulse width t

H t

SHD t

DSU t

DHD

SCLOCK high pulse width

Start condition hold time

Data setup time

Data hold time

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

BUF t

SUP

SDATA (I/O)

MSB LSB ACK t

DSU t

DHD t

DSU t

PSU t

SHD t

H t

RSU t

DHD

SCLK (I) 1 2–7 t

8 t

SUP

P S

STOP

CONDITION

START

CONDITION

S(R)

REPEATED

START

100

1.3

200

Slave Master

Unit

1360 ns

100

300

100

1140

740

400 ns ns ns ns

300

800

200 ns ns

μs ns ns

F t

MSB t

4.7

4.0

4.7

Slave

Min Max Unit

4.7 μs

4.0

250

0 3.45 ns

μs ns

μs

300

μs

μs ns

1 t

ADuC7122

Figure 2. I

C-Compatible Interface Timing

Rev. PrA | Page 7 of 92

ADuC7122 Preliminary Technical Data

Table 4. SPI Master Mode Timing (Phase Mode = 1)

Parameter t

SL t

SH t

DAV t

DSU t

DHD t

DF t

DR t

SCLOCK low pulse width

SCLOCK high pulse width

Data output valid after SCLOCK edge

Data input setup time before SCLOCK edge

Data input hold time after SCLOCK edge

Data output fall time

Data output rise time

SCLOCK rise time t

SCLOCK fall time

1 t

UCLK

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

(SPIDIV + 1) × t

UCLK

(SPIDIV + 1) × t

UCLK

1 × t

UCLK

2 × t

UCLK

12.5 ns ns ns ns

12.5

12.5 ns ns ns

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1) t

SH t

SL t

SR t

SF t

DAV

MSB t

DF t

BITS 6 TO 1 MOSI LSB

MISO MSB IN BITS 6 TO 1 t

DSU t

DHD

Figure 3. SPI Master Mode Timing (PHASE Mode = 1)

LSB IN

Rev. PrA | Page 8 of 92

Preliminary Technical Data ADuC7122

Table 5. SPI Master Mode Timing (Phase Mode = 0)

Parameter t

SL t

SH t

DAV t

DOSU t

DSU t

DHD t

DF t

DR t

SCLOCK low pulse width

SCLOCK high pulse width

Data output valid after SCLOCK edge

Data output setup before SCLOCK edge

Data input setup time before SCLOCK edge 1

Data input hold time after SCLOCK edge

Data output fall time

Data output rise time

SCLOCK rise time

1 × t

UCLK

(SPIDIV + 1) × t

UCLK

(SPIDIV + 1) × t

UCLK

75 ns ns ns ns ns

2 × t

UCLK

5 ns

12.5

12.5 ns ns ns t

SCLOCK fall time

UCLK

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

5 12.5 ns

SCLOCK

(POLARITY = 0) t

SH t

SL t

SR t

SCLOCK

(POLARITY = 1) t

DOSU t

DF t

DAV t

BITS 6 TO 1 MOSI MSB LSB

MISO t

DSU

MSB IN BITS 6 TO 1 LSB IN t

DHD

Figure 4. SPI Master Mode Timing (PHASE Mode = 0)

Rev. PrA | Page 9 of 92

ADuC7122 Preliminary Technical Data

Table 6. SPI Slave Mode Timing (Phase Mode = 1)

Parameter t

CS to SCLOCK edge 200 ns t

DF t

DR t

SR t

SF t

SFS t

SL t

SH t

DAV t

DSU t

DHD

SCLOCK low pulse width

SCLOCK high pulse width 1

Data output valid after SCLOCK edge

Data input setup time before SCLOCK edge

Data input hold time after SCLOCK edge

Data output fall time

Data output rise time

SCLOCK rise time

SCLOCK fall time

(SPIDIV + 1) × t

UCLK

(SPIDIV + 1) × t

UCLK

1 × t

UCLK

2 × t

UCLK

25 ns ns ns

12.5

12.5 ns ns ns ns

CS high after SCLOCK edge 0

1 t

UCLK

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. ns

CS t

SFS t

SCLOCK

(POLARITY = 0) t

SH t

SL t

SR t

SCLOCK

(POLARITY = 1) t

DAV

MSB t

DF t

BITS 6 TO 1 MISO LSB

MOSI LSB IN MSB IN BITS 6 TO 1 t

DSU t

DHD

Figure 5. SPI Slave Mode Timing (PHASE Mode = 1)

Rev. PrA | Page 10 of 92

Preliminary Technical Data ADuC7122

Table 7. SPI Slave Mode Timing (Phase Mode = 0)

t t t t t

Parameter Description

CS to SCLOCK edge

SH t

DAV t

DSU t

DHD

SCLOCK low pulse width

SCLOCK high pulse width 1

Data output valid after SCLOCK edge

Data input setup time before SCLOCK edge

Data input hold time after SCLOCK edge 1

DR t

SR t

SF t

DOCS

Data output fall time

Data output rise time

SCLOCK rise time

SCLOCK fall time

Data output valid after CS edge

Min Typ Max Unit

200 ns

(SPIDIV + 1) × t

UCLK

(SPIDIV + 1) × t

UCLK

1 × t

UCLK

2 × t

UCLK

12.5

12.5 t

SFS

CS high after SCLOCK edge

UCLK

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. ns ns ns ns ns ns ns ns ns

CS t

SFS

SCLOCK

(POLARITY = 0) t

SH t

SL t

SR t

SCLOCK

(POLARITY = 1) t

DAV t

DOCS

MISO t

DF t

BITS 6 TO 1 MSB LSB

MOSI MSB IN t

DSU t

DHD

BITS 6 TO 1 LSB IN

Figure 6. SPI Slave Mode Timing (PHASE Mode = 0)

Rev. PrA | Page 11 of 92

ADuC7122

ABSOLUTE MAXIMUM RATINGS

AGND = REFGND = DACGND = GND

REF

, T

= 25°C, unless otherwise noted.

Table 8.

to IOV

AGND to DGND

IOV

to IOGND, AV

to AGND

−0.3 V to +0.3 V

−0.3 V to +6 V

Digital Input Voltage to IOGND

Digital Output Voltage to IOGND

−0.3 V to +5.3 V

−0.3 V to IOV

+ 0.3 V

−0.3 V to AV

+ 0.3 V V

REF

_2.5 and V

REF

_1.2 to AGND

Analog Inputs to AGND

Analog Outputs to AGND

−0.3 V to AV

+ 0.3 V

−0.3 V to AV

+ 0.3 V

Operating Temperature Range, Industrial −40°C to +125°C

Storage Temperature Range

Junction Temperature

Thermal Impedance

108-Ball CSP_BGA

Peak Solder Reflow Temperature

SnPb Assemblies (10 sec to 30 sec)

RoHS-Compliant Assemblies

(20 sec to 40 sec)

–65°C to +150°C

150°C

40°C/W

240°C

260°C

Preliminary Technical Data

Stresses above those listed under Absolute Maximum Ratings rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

Rev. PrA | Page 12 of 92

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADuC7122

11 10 6 5 4 3 2 1 A1 corner n.c.

n.c.

A n.c.

n.c.

AGND AGND n.c.

REG_PWR AGND n.c.

n.c.

P1.6

P1.7

n.c.

/RST P3.1

TDI/

P1.2

P2.7

n.c.

P3.0

P0.2

P1.0

P2.6

P3.6

P3.7

DGND

LVDD

P0.0

P0.1

P2.0

P2.1

TDO/

P1.3

TMS

TCK

P0_7

P2.4

P0.3

P0.4

P0.5

P0.6

P1.1

P3.2

P3.4

P3.5

P3.3

DGND

XTALO LVDD

XTALI IOVDD

IOVDD P2.2

P1.4

IOGND P2.3

P2.5

DAC11 DAC10 DAC9 ADC9 ADC10/

AINCM

BUF_

VREF2

BUF_

VREF1

ADC0 ADC1

P1.5

ADC4

DAC2

DAC1

IOGND

DAC0

AVDD DAC7 DAC8 ADC8 Vref_2.5

PADC1P PADC0P Vref_1.2

ADC3 DAC5 DAC3 AVDD L

AGND DAC6 ADC6 AIN7 PADC1N AVDD AGND PADC0N ADC2 ADC5 DAC4 AGND

Figure 7. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic

C12 RST

Type 1 Description

I Reset Input (Active Low).

D11 P0.0/SCL1/PLAI[5] I/O General-Purpose Input and Output Port 0.0 (P0.0).

I 2 C Interface SCLOCK for I2C0 (SCL1).

Input to PLA Element 5 (PLAI[5]).

E11 P0.1/SDA1/PLAI[4] I/O General-Purpose Input and Output Port 0.1 (P0.1).

C Interface SDATA for I2C0 (SDA1).

Input to PLA Element 4 (PLAI[4]).

C3 P0.2/SPICLK/PLAO[13] I/O

SPI Clock (SPICLK).

Output of PLA Element 13 (PLAO[13]).

SPI Master Input, Slave Output (SPIMISO).

Output of PLA Element 12 (PLAO[12]).

TBD (SYNC).

SPI Master Out Slave Input (SPIMOSI).

Input to PLA Element 11 (PLAI[11]).

TBD (TRIP).

Rev. PrA | Page 13 of 92

F11

ADuC7122

Pin No. Mnemonic

F3 P0.5/SPICS/PLAI[10]/CONVST

G10

G11

P0.6/MRST/PLAI[2]

P0.7/TRST/PLAI[3]

P1.0/SIN/SCL2/PLAI[7]

P1.4/PWM1/PLAI[8]/XCLK

P1.5/PWM2/PLAI[9]

P2.1/IRQ1/PLAI[12]

H11 P2.2/PLAI[1]

J11 P2.3/IRQ2/PLAI[14]

H10 P2.4/PWM5/PLAO[7]

J10 P2.5/PWM6/PLAO[6]

C11

P1.6/PLAO[5]

P1.7/PLAO[4]

P2.0/IRQ0/PLAI[13]

P2.6/IRQ3/PLAI[15]

P2.7/PLAI[0]

P3.0/PLAO[0]

P3.1/PLAO[1]

Preliminary Technical Data

I/O

Type

Description

I/O General-Purpose Input and Output Port 0.5 (P0.5).

SPI Slave Select Input (SPICS).

Input to PLA Element 10 (PLAI[10]).

TBD (CONVST).

I/O General-Purpose Input and Output Port 0.6 (P0.6).

Power-On Reset Output (MRST).

Input to PLA Element 2 (PLAI[2])

I/O General-Purpose Input and Output Port 0.7 (P0.7).

JTAG Test Port Input, Test Reset (TRST). Debug and download access.

Input to PLA Element 3 (PLAI[3]).

I/O General-Purpose Input and Output Port 1.0 (P1.0).

Serial Input, Receive Data (RxD), UART (SIN)

C Interface SCLOCK for I2C1 (SCL2).

Input to PLA Element 7 (PLAI[7]).

I/O

Serial Output, Transmit Data (TxD), UART (SOUT)

C Interface SDATA for I2C1 (SDA2).

Input to PLA Element 6 (PLAI[6]).

General-Purpose Input and Output Port 1.4 (P1.4).

PWM1 Output (PWM1).

Input to PLA Element 8 (PLAI[8]).

General-Purpose Input and Output Port 1.5 (P1.5).

PWM2 Output (PWM2).

Input to PLA Element 9 (PLAI[9]).

General-Purpose Input and Output Port 1.6 (P1.6).

Output of PLA Element 5 (PLAO[5]).

General-Purpose Input and Output Port 1.7 (P1.7).

Output of PLA Element 4 (PLAO[4]).

General-Purpose Input and Output Port 2.0 (P2.0).

External Interrupt Request 0 (IRQ0).

Input to PLA Element 13 (PLAI[13]).

General-Purpose Input and Output Port 2.1 (P2.1).

External Interrupt Request 1 (IRQ0).

Input to PLA Element 12 (PLAI[12]).

General-Purpose Input and Output Port 2.2 (P2.2).

Input to PLA Element 1 (PLAI[1]).

I/O

External Interrupt Request 2 (IRQ2).

Input to PLA Element 14 (PLAI[14]).

General-Purpose Input and Output Port 2.4 (P2.4).

PWM5 Output (PWM5).

Output of PLA Element 7 (PLAO[7]).

PWM6 Output (PWM6).

Output of PLA Element 6 (PLAO[6]).

General-Purpose Input and Output Port 2.6 (P2.6).

External Interrupt Request 3 (IRQ3).

Input to PLA Element 15 (PLAI[15]).

General-Purpose Input and Output Port 2.7 (P2.7).

Input to PLA Element 0 (PLAI[0]).

General-Purpose Input and Output Port 3.0 (P3.0).

Output of PLA Element 0 (PLAO[0]).

General-Purpose Input and Output Port 3.1 (P3.1).

Output of PLA Element 1 (PLAO[1]).

External Interrupt Request 4 (IRQ4).

Rev. PrA | Page 14 of 92

Preliminary Technical Data

Pin No. Mnemonic Type

Description

PWM3 Output (PWM3).

Output of PLA Element 2 (PLAO[2]).

ADuC7122

M11

D12

E12

P3.4/PLAO[8]

P3.5/PLAO[9]

P3.6/PLAO[10]

P3.7/PLAO[11]/BM

I/O

External Interrupt Request 5 (IRQ5).

PWM4 Output (PWM4).

Output of PLA Element 3 (PLAO[3]).

General-Purpose Input and Output Port 3.4 (P3.4).

Output of PLA Element 8 (PLAO[8]).

General-Purpose Input and Output Port 3.5 (P3.5).

Output of PLA Element 9 (PLAO[9]).

General-Purpose Input and Output Port 3.6 (P3.6).

Output of PLA Element 10 (PLAO[10]).

General-Purpose Input and Output Port 3.7 (P3.7).

Output of PLA Element 11 (PLAO[11]).

Boot Mode (BM).

If this pin is low and Address 0x00014 of flash is 0xFFFFFFFF, then the part enters I

C download after the next rest sequence.

L8 V

REF

_2.5 AI/O of a photo diode

L5 V

REF current externally.

B8 NC

K6 BUF_VREF1

BUF_VREF2

PADC0P

Buffered 2.5 V Bias. Maximum load = 1.2 mA.

Buffered 2.5 V. Maximum load = 1.2 mA.

PADC0 Positive Input Channel. PGA-based ADC input channel.

PADC0N

PADC1P

PADC1N

ADC0

ADC1

ADC2

ADC3

M10

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

K8 ADC10/AINCM

L11

L10

K10

K11

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

DAC8

DAC9

DAC10

K12 DAC11

B5 NC

C6 NC

A6 NC

PADC0 Negative Input Channel. PGA-based ADC input channel.

PADC1 Positive Input Channel. PGA-based ADC input channel.

PADC1 Negative Input Channel. PGA-based ADC input channel.

Single-Ended or Differential Analog Input 0/Thermistor Positive Input 0.

Single-Ended or Differential Analog Input 1/Thermistor Ground Input 0

Single-Ended or Differential Analog Input 2/Thermistor Positive Input 1.

Single-Ended or Differential Analog Input 3/Thermistor Ground Input 1.

Single-Ended Analog Input 4/Positive Differential Input 0.

Single-Ended Analog Input 5/Negative Differential Input 0.

Single-Ended Analog Input 6/Positive Differential Input 1.

Single-Ended Analog Input 7/Negative Differential Input 1.

Single-Ended Analog Input 8/Positive Differential Input 2.

Single-Ended Analog Input 9/Negative Differential Input 2.

AI Single-Ended or Differential Analog Input 10 (ADC10).

Common Mode for Pseudo Differential Input (AINCM).

12-Bit DAC Output.

Rev. PrA | Page 15 of 92

ADuC7122 Preliminary Technical Data

Pin No. Mnemonic

A8 NC

A7 NC

C8 NC

A5 NC

C5 NC

B4 NC

A4 NC

A1 NC

A3 NC

A2 NC

B1 NC

A12 NC

A9 NC

A11 NC

A10 NC

B12 NC

B11 NC

B10 AGND

B9 AGND

AGND

M12

AVDD

AGND

L12 AVDD

C7 NC

B7 REG_PWR

Type

Description

Analog Ground.

Analog Supply (3.3 V).

Analog Ground.

Analog Supply (3.3 V).

G1 LVDD

G12 LVDD

S Output of 2.5 V on-chip Regulator. A 470 nF capacitor to DGND must be connected to this pin.

S Output of 2.6 V on-chip LDO regulator. A 470 nF capacitor to DGND must be connected to this pin.

F1 DGND

F12 DGND

H1 IOVDD

Digital ground.

3.3V GPIO Supply.

H12

IOGND

IOVDD

J12 IOGND

G2 XTALO

3.3V GPIO Ground.

3.3V GPIO Supply.

3.3V GPIO Ground.

H2 XTALI

D10

C10

TDO/P1.3/PLAO[14]

TDI/P1.2/PLAO[15]

DO pin can be left unconnected.

DI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator

Circuits. If an external crystal is not being used, this pin should be connected to the

DGND system ground.

JTAG Test Port Output, Test Data Out (TDO). Debug and download access.

General-Purpose Input and Output Port 1.3 (P1.3).

JTAG Test Port Input, Test Data In (TDI). Debug and download access.

General-Purpose Input and Output Port 1.2 (P1.2).

JTAG Test Port Input, Test Clock. Debug and download access. F10 TCK

E10 TMS DI JTAG Test Port Input, Test Mode Select. Debug and download access.

1 I = input, I/O = input/output, AI/O = analog input/output, NC = no connect, AO = analog output, AI = analog input, DI = digital input, DO = digital output, S = supply.

Rev. PrA | Page 16 of 92

Preliminary Technical Data

TERMINOLOGY

ADC SPECIFICATIONS

Integral Nonlinearity (INL)

The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a point

½ LSB below the first code transition, and full scale, a point

½ LSB above the last code transition.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (0000…000) to

(0000…001) from the ideal, that is, ½ LSB.

Gain Error

The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc.

ADuC7122

The ratio is dependent upon the number of quantization levels in the digitization process; the more levels there are, the smaller the quantization noise becomes.

The theoretical signal-to-(noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

The ratio of the rms sum of the harmonics to the fundamental.

DAC SPECIFICATIONS

Relative Accuracy

Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error.

Voltage Output Settling Time

The amount of time it takes the output to settle to within a

1 LSB level for a full-scale input change.

Rev. PrA | Page 17 of 92

ADuC7122 Preliminary Technical Data

OVERVIEW OF THE ARM7TDMI CORE

The ARM7® core is a 32-bit reduced instruction set computer

(RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits.

The ARM7TDMI is an ARM7 core with four additional features:

 T support for the thumb (16-bit) instruction set

 D support for debug

 M support for long multiplications

 I includes the EmbeddedICE module to support embedded system debugging

EXCEPTIONS

ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are:

 Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events.

 Fast interrupt or FIQ. This is provided to service data transfers or communication channels with low latency. FIQ has priority over IRQ.

 Memory abort.

 Attempted execution of an undefined instruction.

 Software interrupt instruction (SWI). This can be used to make a call to an operating system.

THUMB MODE (T)

An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications.

However, the thumb mode has two limitations:

 Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of time-critical code.

 The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling.

See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core.

EmbeddedICE (I)

EmbeddedICE provides integrated on-chip support for the core.

The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes.

These registers are controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor halts and enters a debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE,

SRAM, and memory mapped registers.

Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ.

ARM REGISTERS

ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers.

R10

R11

R12

R13

R14

R15 (PC)

When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and exception handling.

When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in

Figure 8. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process.

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

R13_SVC

R14_SVC

R13_ABT

R14_ABT

USABLE IN USER MODE

SYSTEM MODES ONLY

R13_IRQ

R14_IRQ

R13_UND

R14_UND

CPSR

SPSR_FIQ

SPSR_SVC

SPSR_ABT

SPSR_IRQ

SPSR_UND

USER MODE

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

Figure 8. Register Organization

UNDEFINED

MODE

Rev. PrA | Page 18 of 92

Preliminary Technical Data

More information relative to the programmer’s model and the

ARM7TDMI core architecture can be found in the following materials from ARM:

 DDI 0029G, ARM7TDMI Technical Reference Manual

 DDI 0100, ARM Architecture Reference Manual

INTERRUPT LATENCY

The worst-case latency for a fast interrupt request (FIQ) consists of the following:

 The longest time the request can take to pass through the synchronizer

 The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC

 The time for the data abort entry

 The time for FIQ entry

ADuC7122

At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock.

The maximum interrupt request (IRQ) latency calculation is similar, but must allow for the fact that FIQ has higher priority and can delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode where the time is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode.

Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.

Rev. PrA | Page 19 of 92

ADuC7122

MEMORY ORGANIZATION

The ADuC7122 incorporates three separate blocks of memory:

8 kB of SRAM and two 64 kB of on-chip Flash/EE memory.

There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 9.

Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the

SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP

MMR. This remap function is described in more detail in the

Flash/EE memory chapter.

0xFFFFFFFF

MMRs

0xFFFF0000

RESERVED

0x0009F800

FLASH/EE

0x00080000

RESERVED

0x00041FFF

SRAM

0x00040000

RESERVED

0x0001FFFF

REMAPPABLE MEMORY SPACE

(FLASH/EE OR SRAM)

0x00000000

Figure 9. Physical Memory Map

Memory Access

The ARM7 core sees memory as a linear array of 2

byte location where the different blocks of memory are mapped as outlined in Figure 9.

The ADuC7122 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.

BIT 31 BIT 0

BYTE 3

BYTE 2

BYTE 1

BYTE 0

0xFFFFFFFF

0x00000004

0x00000000

32 BITS

Figure 10. Little Endian Format

Preliminary Technical Data

FLASH/EE MEMORY

The 128 kB of Flash/EE are organized as two banks of 32 k ×

16 bits. In the upper memory block, 31 k × 16 bits are user space and 1 k × 16 bits is reserved for the factory-configured boot page. The page size of this Flash/EE memory is 512 bytes.

The lower 64 kB memory block is organized in a similar manner. It is arranged in 32 k × 16 bits. All of this is available as user space.

The 126 kB of Flash/EE are available to the user as code and non-volatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode

(32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that

Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the

Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and

FLASH/EE section).

SRAM

The 8 kB of SRAM are available to the user, organized as 2 k ×

32 bits, that is, 2 k words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a

32-bit wide memory array (see the Execution Time from SRAM and FLASH/EE section).

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 11 are unoccupied or reserved locations and should not be accessed by user software. Table 10 to Table 26 show a full MMR memory map.

The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the

ADuC7122 are on the APB except the Flash/EE memory and the GPIOs.

Rev. PrA | Page 20 of 92

Preliminary Technical Data

Figure 11. Memory Mapped Registers

COMPLETE MMR LISTING

Note that the Access Type column corresponds to the access time reading or writing an MMR. It depends on the AMBA bus used to access the peripheral. The processor has two AMBA buses: the AHB (advanced high performance bus) used for system modules and the APB (advanced Peripheral bus) used for lower performance peripherals.

ADuC7122

Table 10. IRQ Base Address = 0xFFFF0000

Address Name Byte Access

0x0000 IRQSTA 4 R

0x0004 IRQSIG 4 R

0x0008 IRQEN 4 R/W

0x000C IRQCLR 4 W

0x0010 SWICFG 4 W

0x001C IRQVEC 4 R

0x0020 IRQP0 4 R/W

0x0024 IRQP1 4 R/W

0x0028 IRQP2 4 R/W

0x002C IRQP3 4 R/W

0x0100 FIQSTA 4 R

0x0104 FIQSIG 4 R

0x0108 FIQEN 4 R/W

0x010C FIQCLR 4 W

0x011C FIQVEC 4 R

Table 11. System Control Base Address = 0xFFFF0200

Rev. PrA | Page 21 of 92

ADuC7122

Table 12. Timer Base Address = 0xFFFF0300

0x0300 T0LD 2 R/W

0x030C T0CON 4 R/W

0x0310 T0CLRI 1 W

0x0314 T0CAP 2 R

0x0320 T1LD 4 R/W

0x0324 T1VAL 4 R

0x032C T1CLRI 1 W

0x0330 T1CAP 4 R

0x0340 T2LD 4 R/W

0x0344 T2VAL 4 R

0x034C T2CLRI 1 W

0x0360 T3LD 2 R/W

0x0364 T3VAL 2 R

0x036C T3CLRI 1 W

0x0380 T4LD 4 R/W

0x0384 T4VAL 4 R

0x038C T4CLRI 1 W

0x0390 T4CAP 4 R

Table 13. PLL Base Address = 0xFFFF0400

Address Name Byte Access

0x0408 POWCON 1 R/W

0x040C POWKEY2 2 W

0x0410 PLLKEY1 2 W

0x0414 PLLCON 1 R/W

0x0418 PLLKEY2 2 W

Table 14. PSM Base Address = 0xFFFF0440

Address Name Byte Access

0x0440 PSMCON 2 R/W 2

Table 15. Reference Base Address = 0xFFFF0480

Preliminary Technical Data

Table 16. ADC Base Address = 0xFFFF0500

Address Name Byte Access

0x0504 ADCCP 1 R/W

0x0508 ADCCN 1 R/W

0x050C ADCSTA 1 R

0x0510 ADCDAT 4 R

0x0514 ADCRST 1 W

0x0520 PGA_GN 2 R/W

Table 17. DAC Base Address = 0xFFFF0580

Address Name Byte Access

0x05AC DAC5DAT 4 R/W

Rev. PrA | Page 22 of 92

Preliminary Technical Data ADuC7122

Table 18. UART0 Base Address = 0xFFFF0800

Address Name

0x0800 COM0TX 1 R/W 2

1 2

0x0804 COMIEN0 1 R/W 2

Table 20. I2C1 Base Address = 0xFFFF0900

Address Name

0x0900 I2C1MCTL 2 R/W

0x0904 I2C1MSTA 2 R

0x0908 I2C1MRX 1 R

0x090C I2C1MTX 2 R/W

0x0808 COMIID0 1 R

0x080C COMCON0 1 R/W

0x0810

0x0814

COMCON1

COMSTA0

1 R/W

1 R

0x0818 COMSTA1 1 R

0x081C COMSCR 1 R/W

0x0828 COMADR 1 R/W

0X082C COMDIV2 2 R/W

Table 19. I2C0 Base Address = 0xFFFF0880

Address Name

0x0880 I2C0MCTL 2 R/W

0x0884 I2C0MSTA 2 R

0x0888 I2C0MRX 1 R

0x088C I2C0MTX 2 R/W

0x0898 I2C0ADR1 1 R/W

0x089C I2C0ADR2 1 R/W

0x08A0 I2C0SBYTE 1 R/W

0x08A4 I2C0DIV 2 R/W

0x08A8 I2C0SCTL 2 R/W

0x08AC I2C0SSTA 2 R

0x08B0 I2C0SRX 1 R

0x08B4 I2C0STX 1 R/W

0x08B8 I2C0ALT 1 R/W

0x08BC I2C0ID0 1 R/W

0x08C0 I2C0ID1 1 R/W

0x08C4 I2C0ID2 1 R/W

0x08C8 I2C0ID3 1 R/W

0x08CC I2C0FSTA 1 R/W

0x0918 I2C1ADR0 1 R/W

0x091C I2C1ADR1 1 R/W

0x0920 I2C1SBYTE 1 R/W

0x0924 I2C1DIV 2 R/W

0x0928 I2C1SCTL 2 R/W

0x092C I2C1SSTA 2 R

0x0930 I2C1SRX 1 R

0x0934 I2C1STX 1 R/W

0x0938 I2C1ALT 1 R/W

0x093C I2C1ID0 1 R/W

0x0940 I2C1ID1 1 R/W

0x0944 I2C1ID2 1 R/W

0x0948 I2C1ID3 1 R/W

0x094C I2C1FSTA 1 R/W

Table 21. SPI Base Address = 0xFFFF0A00

Address Name Byte Access

0x0A00 SPISTA 1 R

0x0A04 SPIRX 1 R

0x0A08 SPITX 1 W

0x0A0C SPIDIV 1 R/W

0x0A10 SPICON 2 R/W

Rev. PrA | Page 23 of 92

ADuC7122

Table 22. PLA Base Address = 0xFFFF0B00

Address Name

0x0B0C PLAELM3 2 R/W

0x0B1C PLAELM7 2 R/W

0x0B28 PLAELM10 2 R/W

0x0B2C PLAELM11 2 R/W

0x0B30 PLAELM12 2 R/W

0x0B34 PLAELM13 2 R/W

0x0B38 PLAELM14 2 R/W

0x0B3C PLAELM15 2 R/W

0x0B4C PLADIN 4 R/W

Table 23. GPIO Base Address = 0xFFFF0D00

Address Name Byte Access

0x0D00 GP0CON 4 R/W

0x0D04 GP1CON 4 R/W

0x0D08 GP2CON 4 R/W

0x0D0C GP3CON 4 R/W

0x0D10 GP4CON 4 R/W

0x0D20 GP0DAT 4 R/W

0x0D24 GP0SET 1 W

0x0D28 GP0CLR 1 W

0x0D2C GP0PAR 4 R/W

0x0D30 GP1DAT 4 R/W

0x0D34 GP1SET 1 W

0x0D38 GP1CLR 1 W

0x0D3C GP1PAR 4 R/W

0x0D40 GP2DAT 4 R/W

0x0D44 GP2SET 1 W

0x0D48 GP2CLR 1 W

0x0D50 GP3DAT 4 R/W

0x0D54 GP3SET 1 W

0x0D58 GP3CLR 1 W

0x0D5C GP3PAR 4 R/W

Preliminary Technical Data

Table 24. Flash/EE Block 0 Base Address = 0xFFFF0E00

Address Name Byte Access

0x0E00 FEE0STA 1 R 1

0x0E0C FEE0DAT 2 R/W

0x0E18 FEE0SGN 3 R

0x0E1C FEE0PRO 4 R/W

Table 25. Flash/EE Block 1 Base Address = 0xFFFF0E80

Address Name Byte Access

0x0E80 FEE1STA 1 R 1

0x0E8C FEE1DAT 2 R/W

0x0E98 FEE1SGN 3 R

0x0E9C FEE1PRO 4 R/W

0x0EA0 FEE1HID 4 R/W

Table 26. PWM Base Address= 0xFFFF0F80

Address Name Byte Access Cycle

0x0F80 PWMCON1 2 R/W 2

0x0F84

0x0F88

0x0F8C

0x0F90

0x0F94

0x0F98

0x0F9C

0x0FA0

0x0FA4

0x0FA8

0x0FAC

0x0FB0

0x0FB4

0x0FB8

PWM1COM1

PWM1COM2

PWM1COM3

PWM1LEN

PWM2COM1

PWM2COM2

PWM2COM3

PWM2LEN

PWM3COM1

PWM3COM2

PWM3COM3

PWM3LEN

PWMCON2

PWMICLR

2 R/W

2 W

Rev. PrA | Page 24 of 92

Preliminary Technical Data

ADC CIRCUIT OVERVIEW

The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V supplies and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, differential track-andhold, on-chip reference, and ADC.

The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of the following three modes:

 Fully differential mode, for small and balanced signals

 Single-ended mode, for any single-ended signals

 Pseudo differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input

The converter accepts an analog input range of 0 to V

REF

when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage V

, in the range 0 V to AV

and with maximum amplitude of 2 V

REF

(see Figure 12).

REF

Figure 12. Examples of Balanced Signals for Fully Differential Mode

A high precision, low drift, and factory-calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described in the Band Gap Reference section.

ADuC7122

Single or continuous conversion modes can be initiated in software. An external CONVST pin, an output generated from the on-chip PLA, a Timer0, or a Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions.

If the signal has not been de-asserted by the time the ADC conversion is complete, a second conversion begins automatically.

A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of 3C.

For the ADuC7122 a number of modifications have been made to the ADC input structure that appeared on the ADuC702x family.

The PADC0 and PADC1 inputs connect to a PGA and allow for gain from 1 to 5 with 32 steps. The remaining channels can be configured as single or differential. A buffer is provided before the ADC for measuring internal channels.

Rev. PrA | Page 25 of 92

ADuC7122

ADC TRANSFER FUNCTION

Pseudo Differential and Single-Ended Modes

In pseudo differential or single-ended mode, the input range is

0 to V

REF

. The output coding is straight binary in pseudo differential and single-ended modes with

1 LSB = FS/4096 or

2.5 V/4096 = 0.61 mV or

610 μV when V

REF

= 2.5 V

The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,

FS – 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 13.

1111 1111 1111

1111 1111 1110

1111 1111 1101

1111 1111 1100

1LSB =

4096

0000 0000 0011

0000 0000 0010

0000 0000 0001

0000 0000 0000

0V 1LSB +FS – 1LSB

VOLTAGE INPUT

Figure 13. ADC Transfer Function in Pseudo Differential Mode or

Single-Ended Mode

Fully Differential Mode

The amplitude of the differential signal is the difference between the signals applied to the V

IN+

and V

IN−

inputs (that is,

IN+

− V

IN−

) of the currently enabled differential channel. The maximum amplitude of the differential signal is therefore −V

REF to +V

REF

p-p (2 × V

REF

). This is regardless of the common mode

(CM). The common mode is the average of the two signals

IN+

+ V

IN−

)/2, and is, therefore, the voltage that the two inputs are centered on. This results in the span of each input being CM

± V

REF

/2. This voltage has to be set up externally, and its range varies with V

REF

(see the Driving the Analog Inputs section).

The output coding is twos complement in fully differential mode with 1 LSB = 2 V

REF

/4096 or 2 × 2.5 V/4096 = 1.22 mV when V

REF

= 2.5 V. The output result is ±11 bits, but this is shifted by one to the right. This allows the result in ADCDAT to be declared as a signed integer when writing C code. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,

FS − 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 14.

Preliminary Technical Data

SIGN

BIT

0 1111 1111 1110

0 1111 1111 1100

0 1111 1111 1010

1LSB =

2 × V

REF

4096

0 0000 0000 0001

0 0000 0000 0000

1 1111 1111 1110

1 0000 0000 0100

1 0000 0000 0010

1 0000 0000 0000

–V

REF

+ 1LSB 0LSB +V

REF

VOLTAGE INPUT (V

+ – V

–)

– 1LSB

Figure 14. ADC Transfer Function in Differential Mode

PADC0/PADC1 in Optical Applications

An external precision resistor converts the current to voltage and the PGA then amplifies this voltage signal with gain up to 5 by 32 steps. The intention is to compensate the variation of the detector diode responsitivity and normalize optical power read by ADC. The external resistor is assumed to be 0.1% accuracy,

5 ppm. A 1 nF capacitor is shunted with the resistor to suppress wide band noise. The resistor value should be selected such that the FS voltage developed on the resistor is less than AVDD − 1.2

V, or typically 1.8 V.

The PGA is designed to handle 10 mV minimum input.

To minimize noise, the ADC input buffer should be bypassed.

PADC1 is driven by a buffer to 0.15 V to keep the PGA from saturation when the input current drops to 0. The buffer can be disabled by setting ADCCON[14] so that the PADC1 can be connected to GND as well. This is the same for PADC0.

The ADC needs to be placed in pseudo differential mode and assumes negative input is close to ground.

All the controls are independently set through register bits to give maximum flexibility to the user. Typically, users need to set the following steps (using PADC1 as an example):

1. Select PADC1P as the PGA input, then select PGA output as mux input. Enable the PADC1N buffer and disable the

ADC input buffer.

2. Set the proper gain value for the PGA. Bypass the buffer.

3. Set the ADC to pseudo differential mode and start conversion.

All the controls are independently set through register bits for maximum flexibility to the user. Typically, users must set the following (using PADC0 as an example):

 Select PADC0P as PGA input, select PGA output as MUX input. Enable PADC0N buffer, disable ADC input buffer.

 Set proper gain value for the PGA; bypass the buffer

 ADC: set to pseudo differential mode, start conversion.

 Removing offset and 1/f noise requires performing two conversions on the input signal.

Rev. PrA | Page 26 of 92

Preliminary Technical Data

 Set pga1_chop to 0 for the first conversion and pga1_chop

= 1 for the second. Then calculate the average value.

Thermistor and Other Input Channels

ADuC7122 provides 2 pairs of thermistor inputs and 7 extra differential input pins. These pins can also be configured as differential input pair or single ended input or pseudo differential inputs. The buffer and ADC are configured independently from input channel selection. Note that the input range of ADC input buffer is from 0.15V to AVDD-0.15V, if the input signal range exceeds this range, the input buffer must be bypassed.

The ADuC7122 provide 2 pins for each thermistor input. The negative input is to remove error of ground difference. When selecting the thermistor input, the negative side buffer should always be bypassed to make sure the amplifier is not saturated.

The ADC should be configured to work in positive pseudo differential mode.

Besides these external inputs, ADC can also select internal inputs to monitor the IOVDD power supply.

An on chip diode can also be selected to provide chip temperature monitoring. ADC can also select V

REF

and AGND as input for calibration purpose

PGA and Input Buffer

The PGA is a one stage positive gain amplifier that is be able to accept input from 0.1V to AVDD-1.2V and the output swing should be at least 2.5V. The gain of the PGA is from 1 to 5 with

32 linear steps. PGA cannot be bypassed for the PADC0 and

PADC1 channels.

The PGAs use PMOS input to minimize nonlinearity and noise.

The input level for PGA is limited to AVDD-1.2V ~0.1V to make sure amplifiers are not saturated. The input buffer is railto-rail buffer. It can accept signal from 0.15V to AVDD-0.15V.

Each of input buffers can be bypassed independently.

The PGA can be chopped to remove offset and 1/f noise. The user need to manually chop the PGA for single conversion while it is automatically chopped when chop mode is enabled.

TYPICAL OPERATION

Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register.

The top four bits are the sign bits, and the 12-bit result is placed from Bit 16 to Bit 27, as shown in Figure 15. Again, it should be noted that in fully differential mode, the result is represented in twos complement format, and in pseudo differential and singleended mode, the result is represented in straight binary format.

31 27 16 15 0

SIGN BITS 12-BIT ADC RESULT

Figure

. ADC Result Format

Rev. PrA | Page 27 of 92

ADuC7122

Calibration

By default, the factory-set values written to the ADC offset

(ADCOF) and gain coefficient registers (ADCGN) yield optimum performance in terms of end-point errors and linearity for standalone operation of the part (see the Specifications section). If system calibration is required, it is possible to modify the default offset and gain coefficients to improve end-point errors, but note that any modification to the factory-set ADCOF and ADCGN values can degrade ADC linearity performance.

For system offset error correction, the ADC channel input stage must be tied to AGND. A continuous software ADC conversion loop must be implemented by modifying the value in ADCOF until the ADC result (ADCDAT) reads Code 0 to Code 1. If the ADCDAT value is greater than 1, ADCOF should be decremented until ADCDAT reads Code 0 to Code 1. Offset error correction is performed digitally and has a resolution of 0.25 LSB and a range of ±3.125% of V

REF

For system gain error correction, the ADC channel input stage must be tied to V

REF

. A continuous software ADC conversion loop must be implemented to modify the value in ADCGN until ADCDAT reads Code 4094 to Code 4095. If the ADCDAT value is less than 4094, ADCGN should be incremented until

ADCDAT reads Code 4094 to Code 4095. Similar to the offset calibration, the gain calibration resolution is 0.25 LSB with a range of ±3% of V

REF

Current Consumption

The ADC in standby mode, that is, powered up but not converting, typically consumes 640 μA. The internal reference adds 140 μA. During conversion, the extra current is 0.3 μA, multiplied by the sampling frequency (in kHz).

Timing

Figure 16 gives details of the ADC timing. Users control the

ADC clock speed and the number of acquisition clock in the

ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS.

For conversion on the temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32. When using multiple channels, including the temperature sensor, the timing settings revert back to the userdefined settings after reading the temperature sensor channel.

ADuC7122

ACQ BIT TRIAL WRITE

ADC CLOCK

CONV

START

ADC

BUSY

ADCDAT

DATA

ADCSTA = 0 ADCSTA = 1

Figure 16. ADC Timing

ADC INTERRUPT

Preliminary Technical Data

TEMPERATURE SENSOR

The ADuC7122 provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature.

The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. It is intended for use as an approximate indicator of the temperature of the

ADuC7122 die.

The typical temperature coefficient is −0.707 mV/°C.

ADC MMRs Interface

The ADC is controlled and configured via a number of MMRs

(see Table 27) that are described in detail in the following pages.

ADC Output vs. Temperature

Table 27. ADC MMRs

Name Description

ADCCON ADC control register. Allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC (either single-ended, pseudo differential, or fully differential mode), and to select the conversion type (see Table 28).

ADCCP ADC positive channel selection register.

ADCCN ADC negative channel selection register.

ADCSTA ADC status register. Indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY

(Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADC

Busy

pin. This pin is high during a conversion. When the conversion is finished, ADC

Busy

goes back low.

This information can be available on P0.5 (see the General-Purpose I/O section) if enabled in GP0CON register.

ADCDAT ADC data result register. Holds the 12-bit ADC result, as shown Table 30.

ADCRST ADC reset register. Resets all the ADC registers to their default value.

PGA_GN Gain of PADC0 and PADC1.

Rev. PrA | Page 28 of 92

Preliminary Technical Data

Table 28. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00)

31:16

13:11

000

These bits are reserved.

Positive ADC buffer bypass.

Set to 0 by the user to enable the positive ADC buffer.

Set to 1 by the user to bypass the positive ADC buffer.

Negative ADC buffer bypass.

Set to 0 by the user to enable the negative ADC buffer.

Set to 1 by the user to bypass the negative ADC buffer.

ADC clock speed (fADC = f

CORE

, conversion = 19 ADC clocks + acquisition time). fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.

ADuC7122

10:8 ADC acquisition time (number of ADC clocks).

000 clocks.

001 clocks.

010 8 clocks (default value).

100 32 clocks

7 Enable conversion.

Set by user to 1 to enable conversion mode.

Cleared by user to 0 to disable conversion mode.

Reserved. This bit should be set to 0 by the user.

ADC power control.

Set by user to 1 to place the ADC in normal mode. The ADC must be powered up for at least 5 μs before it converts correctly.

Cleared by user to 0 to place the ADC in power-down mode.

4:3 Conversion

10 Pseudo differential mode.

11 Reserved.

2:0 Conversion

000 Enable CONVST pin as a conversion input.

001

010

011

Enable Timer1 as a conversion input.

Enable Timer0 as a conversion input.

Single software conversion. Automatically set to 000 after conversion.

110 Reserved

Other Reserved.

Rev. PrA | Page 29 of 92

ADuC7122

Table 29. ADCCP MMR Bit Designations

(Address = 0xFFFF0504, Default Value = 0x00)

Bit Value Description

7:5 Reserved

4:0 Positive channel selection bits

00000 PADC0P

00001 PADC1P

00010 ADC0

00011 ADC1

00100 ADC2

00101 ADC3

00110 ADC4

00111 ADC5

01000 ADC6

01001 ADC7

01010 ADC8

01011 ADC9

01100 ADC10/AINCM

01110 Reserved

01111 Reserved

10000 Reserved

10001 Reserved

10010 Reserved

10011 IOVDD_MON

10110

Preliminary Technical Data

Table 30. ADCCN MMR Bit Designations

(Address = 0xFFFF0508, Default Value = 0x00)

Bit Value Description

7:5 Reserved

4:0 Negative channel selection bits

00000 PADC0P

00001 PADC1P

00010 PADC0P

00011 PADC1P

00100 ADC0

00101 ADC1

00110 ADC2

00111 ADC3

01000 ADC4

01001 ADC5

01010 ADC6

01011 ADC7

01100 ADC8

01101 ADC9

01110 ADC10/AINCM

01111 PGND

10000 IOGND

Others Reserved

Table 31. ADCSTA MMR Bit Designations

(Address = 0xFFFF050C, Default Value = 0x00)

0 1 Indicates that an ADC conversion is complete.

It is set automatically once an ADC conversion completes.

0 0 Automatically cleared by reading the ADCDAT

MMR.

Table 32. ADCDAT MMR Bit Designations

(Address = 0xFFFF0510, Default Value = 0x00000000)

27:16 Holds the ADC result (see Figure 15).

Table 33. ADCRST MMR Bit Designations

(Address = 0xFFFF0514, Default Value = 0x00)

0 1 Set to 1 by the user to reset all the ADC registers to their default values.

Table 34. PGA_GN MMR Bit Designations

(Address = 0xFFFF0520, Default Value = 0x00)

11:6

5:0

Gain of PGA for PADC0 (PGA_PADC0_GN)

= 1 + 4 × (PGA_ADC0_GN/32)

Gain of PGA for PADC1 (PGA_PADC1_GN)

= 1 + 4 × (PGA_ADC1_GN/32)

Note that PGA_PADC0_GN and PGA_PADC1_GN must be ≤32.

Rev. PrA | Page 30 of 92

Preliminary Technical Data

CONVERTER OPERATION

The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described for the three different modes of operation: differential mode, pseudo differential mode, and single-ended mode.

Differential Mode

The ADuC7122 contains a successive approximation ADC based on two capacitive DACs. Figure 17 and Figure 18 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs. In Figure 17 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A. The comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

AIN0

AIN11

MUX

CHANNEL+

SW1

CHANNEL–

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 17. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 18), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution

DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the V

IN+

and V

IN−

inputs must be matched; otherwise, the two inputs have different settling times, resulting in errors.

COMPARATOR

CAPACITIVE

DAC

AIN0

AIN11

MUX

CHANNEL+

SW1

CHANNEL–

SW2

REF

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 18. ADC Conversion Phase

ADuC7122

Pseudo Differential Mode

In pseudo differential mode, Channel− is linked to the V

IN− input of the ADuC7122, and SW2 switches between A

(Channel−) and B (V

REF

). The V

IN−

input must be connected to ground or a low voltage. The input signal on V

IN+

can then vary from V

IN−

to V

REF

+ V

IN−

. Note that V

IN−

must be selected so that

REF

+ V

IN−

does not exceed AV

CAPACITIVE

DAC

AIN0

AIN11

VIN–

MUX

CHANNEL+

SW1

SW2

REF

CHANNEL–

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 19. ADC in Pseudo Differential Mode

Single-Ended Mode

In single-ended mode, SW2 is always connected internally to ground. The V

IN−

input can be floating. The input signal range on V

IN+

is 0 V to V

REF

COMPARATOR

CAPACITIVE

DAC

AIN0

AIN11

MUX

CHANNEL+

SW1

CHANNEL–

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 20. ADC in Single-Ended Mode

Analog Input Structure

Figure 21 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than

300 mV. Voltage in excess of 300 mV can cause these diodes to become forward biased and start conducting into the substrate.

These diodes can conduct up to 10 mA without causing irreversible damage to the part.

The C1 capacitors in Figure 21 are typically 4 pF and can be primarily attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The C2 capacitors are the ADC sampling capacitors and have a capacitance of 16 pF typical.

Rev. PrA | Page 31 of 92

ADuC7122

R1 C2

Figure 21. Equivalent Analog Input Circuit Conversion Phase:

Switches Open, Track Phase: Switches Closed

For ac applications, removing high frequency components from the analog input signal is recommended through the use of an

RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source.

Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier.

The choice of the op amp is a function of the particular application.

Figure 22 and Figure 23 give an example of an ADC front end.

ADuC7122

10W

0.01mF

ADC0

Figure 22. Buffering Single-Ended/Pseudo Differential Input

Vref

ADuC7122

ADC0

ADC1

Figure 23. Buffering Differential Inputs

When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and the performance degrades.

Preliminary Technical Data

DRIVING THE ANALOG INPUTS

Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on the common-mode input signal (V

) that are dependent on reference value and supply voltage used to ensure that the signal remains within the supply rails.

Table 35 gives some calculated V

minimum and V

CM maximum values.

Table 35. V

Ranges

AVDD V

REF

3.3 V 2.5 V

Min V

Max Signal Peak-to-Peak

1.25 V 2.05 V 2.5 V

2.048 V 1.024 V 2.276 V 2.048 V

1.25 V 0.75 V 2.55 V 1.25 V

3.0 V 2.5 V 1.25 V 1.75 V 2.5 V

2.048 V 1.024 V 1.976 V 2.048 V

1.25 V 0.75 V 2.25 V 1.25 V

Figure 24. ADC Output vs. Temperature

Rev. PrA | Page 32 of 92

Preliminary Technical Data ADuC7122

BAND GAP REFERENCE

This internal reference also appears on the V

REF

_2.5pin. When using the internal reference, two 0.47 μF capacitors must be connected from the external V

REF

2.5 V and V

REF

1.2 V pins to

AGND to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (V

REF

) and used as a reference for other circuits in the system.

The band gap reference also connects through buffers to the

BUF_VREF1 and the BUF_VREF2 pins. A minimum of 0.1 μF capacitor should be connected to these pins to damp noise.

POWER SUPPLY MONITOR

generated until CMP returns high. The user should ensure that code execution remains within the ISR until CMP returns high.

The ADuC7122 provide an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This 2.5 V reference is generated from a 1.2V reference.

This monitor function allows the user to save working registers to avoid possible data loss due to the low supply or brown-out conditions. It also ensures that normal code execution does not resume until a safe supply level has been established.

When the ADC channel selection bits are configured to

IOVDD_MON, this permits the ADC to convert the voltage available at the input of the power supply monitor comparator.

When measuring an internal channel, the internal buffer should be enabled. The internal buffer should be enabled to isolate the external interference when sampling any of the internal channels. Before measuring this voltage, the following sequence is required.

The band gap reference interface consists of an 8-bit REFCON

MMR, described in Table 36.

The power supply monitor on the ADuC7122 indicates when the IOV

supply pin drops below one of two supply trip points.

The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, the monitor interrupts the core using the PSMI bit in the PSMCON MMR.

This bit is cleared immediately when CMP goes high. Note that if the interrupt generated is exited before CMP goes high

(IOV

is above the trip point), no further interrupts are

1. Measure VREF using the ADC.

2. Set ADCCP = IOVDD_MON channel.

3. Set a typical delay of 60 μs.

4. Perform ADC conversion on the IOVDD_MON channel

(Use anADCCON value of 0x2AA3 for optimum results).

The delay between the ADC mux select switching and the initiation of the conversion is required to allow the voltage on the ADC sampling capacitor to settle to the divided down supply voltage.

Table 36. REFCON MMR Bit Designations (Address = 0xFFFF0480, Default Value = 0x01)

Bit Description

7:1 Reserved.

BUF_VREF is driven from the internal 2.5 V reference when set to 1.

Internal 2.5 V reference output enable.

Set by user to connect the internal 2.5 V reference to the V

REF

_2.5 pin.

Cleared by user to disconnect the reference from the V

REF

_2.5 pin. This pin should also be cleared to connect an external reference source to the V

REF

_2.5 pin.

Internal 1.2 V reference output enable.

Set by user to connect the internal 1.2 V reference to the V

REF

_1.2 pin.

Cleared by user to disconnect the reference from the V

REF

_1.2 pin.

Table 37. PSMCON MMR Bit Designations (Address = 0xFFFF0440, Default Value = 0x08 or 0x00 (Dependent on Device Supply Level)

Bit Name Description

3 CMP Comparator bit. This is a read-only bit that directly reflects the state of the comparator.

Read 1 indicates the IOV

supply is above its selected trip point or the PSM is in power-down mode.

Read 0 indicates the IOV

supply is below its selected trip point. This bit should be set before leaving the interrupt service routine.

2 TP Trip point selection bit.

0 = 2.79 V

1 = 3.07 V

PSMEN Power supply monitor enable bit.

Set to 1 by the user to enable the power supply monitor circuit.

Cleared to 0 by the user to disable the power supply monitor circuit.

0 PSMI Power supply monitor interrupt bit. This bit is set high by the MicroConverter® if CMP is low, indicating low I/O supply.

The PSMI Bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit can be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be cleared immediately once CMP goes high.

Rev. PrA | Page 33 of 92

ADuC7122

NONVOLATILE FLASH/EE MEMORY

FLASH/EE MEMORY OVERVIEW

The ADuC7122 incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space.

Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, Flash memory is often and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer to the ideal memory device that includes no volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7122, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes.

FLASH/EE MEMORY

The ADuC7122 contains two 64 kB arrays of Flash/EE memory.

In the upper block of Flash/EE memory, the bottom 62 Kb are available to the user and the top 2 kB of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download. The 2 Kb of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (band gap references and so on). This 2 kB embedded firmware is hidden from user code. It is not possible for the user to read, write, or erase this page. In the second block, all 64 kB of Flash/EE memory are available to the user.

The 126 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the JTAG mode provided.

Flash/EE Memory Reliability

The Flash/EE memory arrays on the ADuC7122 is fully qualified for two key Flash/EE memory characteristics:

Flash/EE memory cycling endurance and Flash/EE memory data retention.

Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as

1. Initial page erase sequence

2. Read/verify sequence a single Flash/EE

3. Byte program sequence memory

4. Second read/verify sequence endurance cycle

In reliability qualification, three separate page blocks from each

Flash/EE memory block is tested. An entire Flash/EE page at the top, middle, and bottom of each Flash/EE memory block is cycled 10,000 times from 0x0000 to 0xFFFF.

Preliminary Technical Data

As indicated in the Specifications section, the Flash/EE memory endurance qualification is carried out in accordance with JEDEC

Retention Lifetime Specification A117 over the industrial temperature range of –10° to +95°C. The results allow the specification of a minimum endurance figure over a varying supply across the industrial temperature range for 10,000 cycles.

Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention

Lifetime Specification (A117) at a specific junction temperature

= 85°C). As part of this qualification procedure, the

Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized.

This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the

Flash/EE memory is reprogrammed. Note, too, that retention lifetime, based on activation energy of 0.6 eV, derates with

, as shown in Figure 25.

600

450

300

150

30 40 55 70 85 100 125

JUNCTION TEMPERATURE (°C)

135 150

Figure 25. Flash/EE Memory Data Retention

Serial Downloading (In-Circuit Programming)

The ADuC7122 facilitates code download via the I

C serial port. The ADuC7122 enters serial download mode after a reset or power cycle if the BM pin is pulled low through an external

1 kΩ resistor. This is combined with the state of address

0x00014 in the flash. If this address is 0xFFFFFFFF and the BM pin is pulled low the part will enter download mode, if this address contains any other value user code is executed. Once in serial download mode, the user can download code to the full

126 kB of Flash/EE memory while the device is in-circuit in its target application hardware. A PC serial download executable and hardware dongle are provided as part of the development system for serial downloads via the I2C port.

JTAG Access

The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug.

Rev. PrA | Page 34 of 92

Preliminary Technical Data

FLASH/EE MEMORY SECURITY

The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID

MMR protects the 126 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID similarly protect the second

64 kB block. All 32 bits of this are used to protect four pages at a time.

Three Levels of Protection

Protection can be set and removed by writing directly into

FEExHID MMR. This protection does not remain after reset.

Protection can be set by writing into FEExPRO MMR. It takes effect only after a save protection command (0x0C) and a reset.

The FEExPRO MMR is protected by a key to avoid direct access.

The key is saved once and must be entered again to modify

FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code.

The Flash/EE memory can be permanently protected by using the FEEPRO MMR and a particular value of the 0xDEADDEAD key. Entering the key again to modify the FEExPRO register is not allowed.

Sequence to Write the Key

1. Write the bit in FEExPRO corresponding to the page to be protected.

2. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must equal 0).

3. Write a 32-bit key in FEExADR, FEExDAT.

4. Run the write key command 0×0C in FEExCON; wait for the read to be successful by monitoring FEExSTA.

5. Reset the part.

To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value

0xDEADDEAD, then the memory protection cannot be removed.

Only a mass erase unprotects the part; however, it also erases all user code.

ADuC7122

The sequence to write the key is shown in the following example; this protects writing Page 4 to Page 7 of the Flash/EE memory:

FEE0PRO=0xFFFFFFFD; //Protect pages 4 to 7

FEE0MOD=0x48; //Write key enable

FEE0ADR=0x1234; //16 bit key value

FEE0DAT=0x5678;

FEE0CON= 0x0C;

//16 bit key value

// Write key command

The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT =

0xDEADDEAD.

FLASH/EE CONTROL INTERFACE

Table 38. FEE0DAT Register

Name Address Default Value

FEE0DAT 0xFFFF0E0C 0xXXXX

FEE0DAT is a 16-bit data register.

Table 39. FEE0ADR Register

Name Address Default Value

FEE0ADR 0xFFFF0E10 0x0000

FEE0ADR is a 16-bit address register.

Access

R/W

Access

R/W

Table 40. FEE0SGN Register

Name Address Default Value

FEE0SGN 0xFFFF0E18 0xFFFFFF

FEE0SGN is a 24-bit code signature.

Access

Table 41. FEE0PRO Register

Name Address Default Value Access

FEE0PRO 0xFFFF0E1C 0x00000000 R/W

FEE0PRO provides protection following subsequent reset MMR.

It requires a software key (see Table 57). As stated previously, each bit from 30 to 0 of the FEEXPRO register protects a 2 kB block of memory; that is, setting Bit 0 low protects Page 0 to

Page 3 and setting Bit 2 low protects Page 8 to Page 11.

Table 42. FEE0HID Register

Name Address Default Value Access

FEE0HID 0xFFFF0E20 0xFFFFFFFF R/W

FEE0HID provides immediate protection MMR. It does not require any software keys (see Table 57).

Command Sequence for Executing a Mass Erase

FEE0DAT = 0x3CFF;

FEE0ADR = 0xFFC3;

FEE0MOD = FEE0MOD|0x8;

FEE0CON = 0x06;

//Erase key enable

//Mass erase command

Rev. PrA | Page 35 of 92

ADuC7122

Table 43. FEE1DAT Register

Name Address Default Value

FEE1DAT 0xFFFF0E8C 0xXXXX

FEE1DAT is a 16-bit data register.

Access

R/W

Table 44. FEE1ADR Register

Name Address Default Value

FEE1ADR 0xFFFF0E90 0x0000

FEE1ADR is a 16-bit address register.

Table 45. FEE1SGN Register

Name Address Default Value

FEE1SGN 0xFFFF0E98 0xFFFFFF

FEE1SGN is a 24-bit code signature.

Access

R/W

Access

Table 46. FEE1PRO Register

Name Address Default Value Access

FEE1PRO 0xFFFF0E9C 0x00000000 R/W

FEE1PRO provides protection following subsequent reset MMR.

It requires a software key (see Table 58).

Table 47. FEE1HID Register

Name Address Default Value Access

FEE1HID 0xFFFF0EA0 0xFFFFFFFF RW

Preliminary Technical Data

FEE1HID provides immediate protection MMR. It does not require any software keys (see Table 58).

Table 48. FEE0STA Register

Name Address Default Value

FEE0STA 0xFFFF0E00 0x0000

Access

Table 49. FEE1STA Register

Name Address Default Value

FEE1STA 0xFFFF0E80 0x0000

Table 50. FEE0MOD Register

Name Address Default Value

FEE0MOD 0xFFFF0E04 0x80

Table 51. FEE1MOD Register

Name Address Default Value

FEE1MOD 0xFFFF0E84 0x80

Access

Table 52. FEE0CON Register

Name Address Default Value

FEE0CON 0xFFFF0E08 0x0000

Table 53. FEE1CON Register

Name Address Default Value

FEE1CON 0xFFFF0E88 0x0000

Access

Rev. PrA | Page 36 of 92

Preliminary Technical Data ADuC7122

Table 54. FEExSTA MMR Bit Designations

Bit Description

15:6 Reserved.

5 Reserved.

4 Reserved.

Flash/EE interrupt status bit.

Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the

FEExMOD register is set.

Cleared when reading FEExSTA register.

Flash/EE controller busy.

Set automatically when the controller is busy.

Cleared automatically when the controller is not busy.

Set automatically when a command completes unsuccessfully.

Cleared automatically when reading FEExSTA register.

Set by MicroConverter when a command is complete.

Cleared automatically when reading FEExSTA register.

Table 55. FEExMOD MMR Bit Designations

Bit Description

7:5 Reserved.

1:0

Flash/EE interrupt enable.

Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.

Cleared by user to disable the Flash/EE interrupt

Erase/write command protection.

Set by user to enable the erase and write commands.

Cleared to protect the Flash/EE memory against erase/write command.

Reserved. Should always be set to 0 by the user.

Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect.

Table 56. Command Codes in FEExCON

Code Command Description

0x00

Null

0x01 1

0x02 1

Single read

Single write

Load FEExDAT with the 16-bit data indexed by FEExADR.

Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.

0x03 1 Erase/write Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms.

0x04

1 is returned in FEExSTA Bit 1.

0x05

0x06

Single erase Erase the page indexed by FEExADR. execution, a command sequence is required to execute this instruction.

0x07 Reserved Reserved.

0x08 Reserved Reserved.

0x09 Reserved Reserved.

0x0A Reserved Reserved.

0x0B Signature Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.

0x0C Protect This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase

(0x06) or with the key.

0x0D Reserved Reserved.

0x0E Reserved Reserved.

0x0F Ping No operation, interrupt generated.

The FEExCON register always reads 0x07 immediately after execution of any of these commands.

Rev. PrA | Page 37 of 92

ADuC7122 Preliminary Technical Data

Table 57. FEE0PRO and FEE0HID MMR Bit Designations

Bit Description

31 Read Protection.

Cleared by user to protect Block 0.

Set by user to allow reading Block 0.

30:0 Write Protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 0 to Page 3.

Cleared by user to protect the pages in writing.

Set by user to allow writing the pages.

Table 58. FEE1PRO and FEE1HID MMR Bit Designations

Bit Description

31 Read Protection.

Cleared by user to protect Block 1.

Set by user to allow reading Block 1.

31:0

Write Protection for Page 127 to Page 120.

Cleared by user to protect the pages in writing.

Set by user to allow writing the pages.

Write Protection for Page 119 to Page 116 and for Page 0 to Page 3.

Cleared by user to protect the pages in writing.

Set by user to allow writing the pages.

EXECUTION TIME FROM SRAM AND FLASH/EE

This section describes SRAM and Flash/EE access times during execution of applications where execution time is critical.

Execution from SRAM

Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns and a clock cycle is 22 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE), one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, such as a branch instruction, takes one cycle to fetch, but it also takes two cycles to fill the pipeline with the new instructions.

Execution from Flash/EE

Because the Flash/EE width is 16 bits and access time for 16-bit words is 23 ns, execution from Flash/EE cannot be completed in one cycle (contrary to a SRAM fetch, which can be completed in a single cycle when CD bits = 0). Dependent on the instruction, some dead times may be required before accessing data for any value of CD bits.

In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0. In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction.

Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipeline. A data processing instruction involving only core registers doesn’t require any extra clock cycles, but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instructions are more complex and are summarized in Table 59.

Table 59. Execution Cycles in ARM/Thumb Mode

Instructions

Fetch

Cycles

LDM/PUSH 2/1

STR 2/1

STRM/POP 2/1

Dead

Time Data Access

Dead

Time

2 × N

2 × 20 μs

20 1

2 × N × 20 μs N

With 1 < N ≤ 16, N is the number of bytes of data to load or store in the multiple load/store instruction. The SWAP instruction combines an LD and STR instruction with only one fetch, giving a total of eight cycles plus 40 μs.

Rev. PrA | Page 38 of 92

Preliminary Technical Data

RESET AND REMAP

The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 26.

FFFFFFFFh kernel interrupt service routines interrupt service routines

00080000h

0009F800h

Flash/EE

00040000h

00041FFFh

SRAM

Mirror Space

ARM exception vector addresses

0x00000020

0x00000000

00000000h

Figure 26. Remap for Exception Execution

By default and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, facilitating execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, with the exception being executed in ARM mode

(32 bits), and the SRAM being 32 bits wide instead of 16-bit wide Flash/EE memory.

ADuC7122

Remap Operation

When a reset occurs on the ADuC7122, execution starts automatically in factory-programmed internal configuration code. This kernel is hidden and cannot be accessed by user code. If the ADuC7122 is in normal mode (the BM pin is high), it executes the power-on configuration routine of the kernel and then jumps to the reset vector Address 0x00000000 to execute the user’s reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE.

The memory remap from Flash/EE is configured by setting Bit 0 of the REMAP register. Precautions must be taken to execute this command from Flash/EE, above Address 0x00080020, and not from the bottom of the array because this is replaced by the

SRAM.

This operation is reversible: the Flash/EE can be remapped at

Address 0x00000000 by clearing Bit 0 of the REMAP MMR.

Precaution must again be taken to execute the remap function from outside the mirrored area. Any kind of reset remaps the

Flash/EE memory at the bottom of the array.

Reset Operation

There are four types of reset: external reset, power-on reset, watchdog expiration, and software force reset. The RSTSTA register indicates the source of the last reset and RSTCLR clears the RSTSTA register. These registers can be used during a reset exception service routine to identify the source of the reset.

If RSTSTA is null, the reset was external. Note that when clearing RSTSTA, all bits that are currently 1 must be cleared.

Otherwise, a reset event occurs.

Table 60. REMAP MMR Bit Designations (Address = 0xFFFF0220, Default Value = 0x00)

Bit Name Description

0 Remap Remap bit.

Set by user to remap the SRAM to Address 0x00000000.

Cleared automatically after reset to remap the Flash/EE memory to address 0x00000000.

Table 61. RSTSTA MMR Bit Designations (Address = 0xFFFF0230, Default Value = 0x0X)

Bit Description

7:3 Reserved.

2 Software reset.

Set by user to force a software reset.

Cleared by setting the corresponding bit in RSTCLR.

Set automatically when a watchdog timeout occurs.

Cleared by setting the corresponding bit in RSTCLR.

Set automatically when a power-on reset occurs.

Cleared by setting the corresponding bit in RSTCLR.

Rev. PrA | Page 39 of 92

ADuC7122

OTHER ANALOG PERIPHERALS

DAC

The ADuC7122 incorporates 12 buffered 12-bit voltage output string DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF.

Each DAC has three selectable ranges: 0 V to V

REF

(internal band gap 2.5 V reference), 0 V to DAC

REF,

and 0 V to Ext Ref.

Preliminary Technical Data

The signal range is 0 V to AV

. To note that the DAC can also operate in interpolation mode.

MMRs Interface

Each DAC is independently configurable through a control register and a data register. These two registers are identical for the twelve DACs. Only DACxCON and DACxDAT (see

Table 62 to Table 65) are described in detail in this section.

Figure 27. DAC Configuration

Figure 28. DAC User Functionality

Table 62 DACxCON Registers

Name Address

DAC0CON 0xFFFF0580

DAC1CON 0xFFFF0588

DAC2CON 0xFFFF0590

DAC3CON 0xFFFF0598

DAC4CON 0xFFFF05A0

DAC5CON 0xFFFF05A8

DAC6CON 0xFFFF05B0

DAC7CON 0xFFFF05B8

DAC8CON 0xFFFF05C0

DAC9CON 0xFFFF05C8

DAC10CON 0xFFFF05D0

DAC11CON 0xFFFF05D8

Default Value

0x100

Rev. PrA | Page 40 of 92

Access

R/W

Preliminary Technical Data ADuC7122

Table 63. DACxCON MMR Bit Designations

Bit Value Name Description

15:9 0 Reserved.

8 1 DACPD DAC power-down. Set by user to set DACOUTx to tri-state mode.

DACBUF_LP DAC buffer low power mode. Set by user to place DAC_BUFF in a low power mode.

BYP DAC bypass bit. Set this bit to bypass the DAC buffer. Cleared to buffer the DAC output.

5 0 DACCLK DAC update rate. Set by user to update the DAC using Timer1. Cleared by user to update the DAC using

HCLK (core clock).

4 0 DACCLR DAC clear bit. Set by user to enable normal DAC operation. Cleared by user to reset data register of the

DAC to 0.

3 0 MODE Mode bit. Set by user to operate on DAC normal mode and turn off the interpolator clock source. Cleared by user to enable the interpolation mode.

1:0

0 RATE

DACRNx

Rate bit. Set by user to enable the interpolation clock to HCLK/16. Cleared by user to HCLK/32.

DAC range bits.

Int_ref/AGND.

Ext_ref/AGND.

AVDD/AGND.

Table 64. DACxDAT Registers

Name Address Default Value

DAC0DAT 0xFFFF0584 0x00000000

DAC1DAT 0xFFFF058C 0x00000000

DAC2DAT 0xFFFF0594 0x00000000

DAC3DAT 0xFFFF059C 0x00000000

DAC4DAT 0xFFFF05A4 0x00000000

DAC5DAT 0xFFFF05AC 0x00000000

DAC6DAT 0xFFFF05B4 0x00000000

DAC7DAT 0xFFFF05BC 0x00000000

DAC8DAT 0xFFFF05C4 0x00000000

DAC9DAT 0xFFFF05CC 0x00000000

DAC10DAT 0xFFFF05D4 0x00000000

DAC11DAT 0xFFFF05DC 0x00000000

Table 65. DACxDAT MMR Bit Designations

Bit Description

31:28 Reserved.

27:16

15:12

12-bit data for DACx.

Extra bits for Interpolation Mode.

11:0 Reserved.

Access

R/W

Rev. PrA | Page 41 of 92

ADuC7122

Using the DACs

The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier. The functional equivalent is shown in Figure 29.

REF

DAC

REF R

DAC0

– 100mV

Preliminary Technical Data

Figure 29. DAC Structure

As illustrated in Figure 29, the reference source for each DAC is user-selectable in software. It can be either AV

or V

REF

. In 0-to-

mode, the DAC output transfer function spans from 0 V to the voltage at the AV

pin. In 0-to-V

REF

mode, the DAC output transfer function spans from 0 V to the internal 2.5 V reference,

REF

The DAC output buffer amplifier features a true, rail-to-rail output stage implementation. This means that when unloaded, each output is capable of swinging to within less than 5 mV of both AV

and ground. Moreover, the DAC’s linearity specification

(when driving a 5 kΩ resistive load to ground) is guaranteed through the full transfer function except codes 0 to 100, and, in

0-to-AV

mode only, codes 3995 to 4095.

Linearity degradation near ground and V

is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 30.

The dotted line in Figure 30 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 30 represents a transfer function in 0-to-AV

mode only. In 0-to-V

REF

or 0-to-DAC

REF

modes

(with V

REF

< AV

or DAC

REF

< AV

), the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line right to the end (V

REF

in this case, not AV

), showing no signs of endpoint linearity errors.

100mV

0x00000000 0x0FFF0000

Figure 30. Endpoint Nonlinearities Due to Amplifier Saturation

The endpoint nonlinearities conceptually illustrated in

Figure 30 get worse as a function of output loading. The

ADuC7122 data sheet specifications assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 30 become larger. With larger current demands, this can significantly limit output voltage swing.

LDO (LOW DROPOUT REGULATOR)

The ADuC7122 contains an integrated LDO which generates the core supply voltage (LVDD) of approximately 2.6V from the

IOVDD supply. As the LDO is driven from the IOVDD, the

IOVDD supply voltage needs to be greater than 2.7V.

An external compensation capacitor (C

) of 0.47 μF with low equivalent series resistance (ESR) must be placed very close to

LVDD pin. This capacitor also acts as a storage of charge and supplies an instantaneous charge required by the core particularly at positive edge of core clock (HCLK).

The LVDD voltage generated by the LDO is solely for providing a supply for the ADuC7122. Therefore, users should not use

LVDD pin as the power supply pin for any other chip. Also, it is recommended that the IOVDD pin have excellent power supply decoupling, in order to help improve line regulation performance of the LDO.

The LVDD pin has no reverse battery, current limit or thermal shutdown protection; therefore, it is essential that users of the

ADuC7122 do not short this pin to ground at anytime during normal operation or during board manufacture.

Rev. PrA | Page 42 of 92

Preliminary Technical Data

OSCILLATOR AND PLL—POWER CONTROL

The ADuC7122 integrates a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency can be output on the XCLK pin as described in

Figure 31. Note that when the XCLK pin is used to output the core clock, the output signal is not buffered and is not suitable for use as a clock source to an external device without an external buffer.

A power-down mode is available on the ADuC7122.

The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON (see Table 72) and

POWCON (see Table 73). PLLCON controls the operating mode of the clock system, and POWCON controls the core clock frequency and the power-down mode.

Figure 31. Clocking System

EXTERNAL CRYSTAL SELECTION

To switch to an external crystal, users must use the following procedure:

1. Enable the Timer2 interrupt and configure it for a timeout period of >120 μs.

2. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit.

3. Force the part into nap mode by following the correct write sequence to the POWCON register.

4. When the part is interrupted from nap mode by the Timer2 interrupt source, the clock source has switched to the external clock.

ADuC7122

Example Source Code

T2LD = 5;

TCON = 0x480;

while ((T2VAL == t2val_old) || (T2VAL >

3)) //ensures timer value loaded

IRQEN = 0x10;

//enable T2 interrupt

PLLKEY1 = 0xAA;

PLLCON = 0x01;

PLLKEY2 = 0x55;

POWKEY1 = 0x01;

POWCON = 0x27;

// Set Core into Nap mode

POWKEY2 = 0xF4;

In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored.

In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer.

EXTERNAL CLOCK SELECTION

To switch to an external clock on P1.4, configure P1.4 in

Mode 2. The external clock can be up to 41.78 MHz, providing the tolerance is 1%.

Example Source Code

T2LD = 5;

TCON = 0x480;

while ((T2VAL == t2val_old) || (T2VAL >

3)) //ensures timer value loaded

IRQEN = 0x10;

//enable T2 interrupt

PLLKEY1 = 0xAA;

PLLCON = 0x03; //Select external clock

PLLKEY2 = 0x55;

POWKEY1 = 0x01;

POWCON = 0x27; // Set Core into Nap mode

POWKEY2 = 0xF4;

Rev. PrA | Page 43 of 92

ADuC7122 Preliminary Technical Data

POWER CONTROL SYSTEM

A choice of operating modes is available on the ADuC7122.

Table 66 describes which blocks of the ADuC7122 are powered on in the different modes and indicates the power-up time. Table

67 gives some typical values of the total current consumption

Table 66. Operating Modes

Mode Core Peripherals

Active On On

Pause

Nap

Sleep

Stop

(analog + digital supply currents) in the different modes, depending on the clock divider bits when the ADC is turned off.

The ADC is turned off. Note that these values also include current consumption of the regulator and other parts on the test board on which these values were measured.

PLL XTAL/Timer 2/Timer 3 XIRQ

On On On

Start-Up/Power-On Time

130 ms at CD = 0

24 ns at CD = 0; 3.06 μs at CD = 7

Table 67. Typical Current Consumption at 25°C

PC[2-0] Mode CD = 0 CD = 1 CD = 2 CD = 3 CD = 4 CD = 5 CD = 6 CD = 7

010 Nap 3.8 3.8 3.8 3.8 3.8 3.8 3.8 3.8

011 Sleep 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25

100 Stop 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25

Rev. PrA | Page 44 of 92

ADuC7122

MMRS AND KEYS

To prevent accidental programming, a certain sequence must be followed when writing in the PLLCON and POWCON registers

(see Table 72).

Table 68. PLLKEYx Register

Name Address Default Value

PLLKEY1 0xFFFF0410 0x0000

PLLKEY2 0xFFFF0418 0x0000

Table 69. PLLCON Register

Name Address Default Value

PLLCON 0xFFFF0414 0x21

Table 70. POWKEYx Register

Name Address Default Value

POWKEY1 0xFFFF0404 0x0000

POWKEY2 0xFFFF040C 0x0000

Access

R/W

Access

Table 71. POWCON Register

Name Address Default Value

POWCON 0xFFFF0408 0x0003

Access

R/W

Table 72. PLLCON and POWCON Write Sequence

PLLCON POWCON

PLLKEY1 = 0xAA POWKEY1 = 0x01

PLLCON = 0x01

PLLKEY2 = 0x55

POWCON = user value

POWKEY2 = 0xF4

Preliminary Technical Data

Table 73. PLLCON MMR Bit Designations

Bit Value Name Description

7:6 Reserved.

5 OSEL 32 kHz PLL Input Selection.

Set by user to use the internal

32 kHz oscillator.

Set by default.

Cleared by user to use the external 32 kHz crystal.

Reserved. 4:2

1:0

00 Reserved.

01 PLL. default configuration.

10 Reserved.

11 External clock on P1.4 pin.

Table 74. POWCON MMR Bit Designations

Bit Value Name Description

7 Reserved.

6:4 PC Operating

000 Active

001 Pause

010 Nap.

011 Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7122.

100 Stop

Others Reserved.

3 RSVD Reserved.

2:0 CD CPU clock divider bits.

000 41.779200

001 20.889600

010 10.444800

011 5.222400

100 2.611200

101 1.305600

110 654.800

111 326.400

Rev. PrA | Page 45 of 92

ADuC7122

DIGITAL PERIPHERALS

PWM GENERAL OVERVIEW

The ADuC7122 integrates a six channel PWM interface. The

PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power up, the PWM outputs default to H-bridge mode. This ensures that the H-bridge controlled motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins.

Users have control over the period of each pair of outputs and over the duty cycle of each individual output.

HIGH SIDE

(PWM1)

LOW SIDE

(PWM2)

PWM1COM3

PWM1COM2

Preliminary Technical Data

Table 75. PWM MMRs

Name Function

PWM1COM1 Compare Register 1 for PWM Output 1 and Output 2

PWM1COM2 Compare Register 2 for PWM Output 1 and Output 2

PWM1COM3 Compare Register 3 for PWM Output 1 and Output 2

PWM1LEN Frequency Control for PWM Output 1 and Output 2

PWM2COM1 Compare Register 1 for PWM Output 3 and Output 4

PWM2COM2 Compare Register 2 for PWM Output 3 and Output 4

PWM2COM3 Compare Register 3 for PWM Output 3 and Output 4

PWM2LEN Frequency Control for PWM Output 3 and Output 4

PWM3COM1 Compare Register 1 for PWM Output 5 and Output 6

PWM3COM2 Compare Register 2 for PWM Output 5 and Output 6

PWM3COM3 Compare Register 3 for PWM Output 5 and Output 6

PWM3LEN

PWMCON2

PWMICLR

Frequency Control for PWM Output 5 and Output 6

PWM Convert Start Control

PWM Interrupt Clear

In all modes, the PWMxCOMx MMRs controls the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM1 and PWM2) is shown in Figure 32.

PWM1COM1

PWM1LEN

Figure 32. PWM Timing

The PWM clock is selectable via PWMCON1 with one of the following values: UCLK/2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN.

The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents as shown with the

PWM1 and PWM2 waveforms in Figure 32.

The low-side waveform, PWM2, goes high when the timer count reaches PWM1LEN, and it goes low when the timer count reaches the value held in PWM1COM3 or when the high-side waveform PWM1 goes low.

The high-side waveform, PWM1, goes high when the timer count reaches the value held in PWM1COM1, and it goes low when the timer count reaches the value held in PWM1COM2.

In H-bridge mode, HMODE = 1 and Table 76 determine the

PWM outputs.

Table 76. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)

Bit Name Description

15 Reserved This bit is reserved

14 SYNC Enables PWM synchronization.

Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the SYNC pin.

Cleared by user to ignore transitions on the SYNC pin.

13 PWM6INV Set to 1 by the user to invert PWM6.

Cleared by user to use PWM6 in normal mode.

12 PWM4NV Set to 1 by the user to invert PWM4.

Cleared by user to use PWM4 in normal mode.

11 PWM2INV Set to 1 by the user to invert PWM2.

Cleared by user to use PWM2 in normal mode.

10 PWMTRIP Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an interrupt is generated.

Cleared by user to disable the PWMTRIP interrupt.

9 ENA If HOFF = 0 and HMODE = 1.

Set to 1 by the user to enable PWM outputs.

Cleared by user to disable PWM outputs.

If HOFF = 1 and HMODE = 1, see Table 77.

If not in H-Bridge mode, this bit has no effect.

8 PWMCP2 PWM clock prescaler bits.

Rev. PrA | Page 46 of 92

Preliminary Technical Data ADuC7122

Bit Name Description

7 PWMCP1 Sets UCLK divider.

6 PWMCP0

16.

32.

5 POINV

64.

128.

256.

Set to 1 by the user to invert all PWM outputs.

Cleared by user to use PWM outputs as normal.

4 HOFF High-side

Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low.

Cleared by user to use the PWM outputs as normal.

3 LCOMP Load compare registers.

Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the

PWM timer from 0x00 to 0x01.

Cleared by user to use the values previously stored in the internal compare registers.

2 DIR

Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low.

Cleared by user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low.

1 HMODE Enables H-bridge mode.

Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON1.

Cleared by user to operate the PWMs in standard mode.

0 PWMEN Set to 1 by the user to enable all PWM outputs.

Cleared by user to disable all PWM outputs.

Rev. PrA | Page 47 of 92

ADuC7122

Table 77. PWM Output Selection

PWMCOM1 MMR PWM Outputs

ENA HOFF POINV DIR PWM1 PWM2 PWM3 PWM4

0 0 x x 1 1 1 1 x 1 x x 1 0 1 0

1 0 0 0 0 0 HS

1 0 0 1 HS

0 0

1 0 1 0 HS

1 1

1 0 1 1 1 1 HS

1 HS = high side, LS = low side.

On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and

HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 78).

Table 78. Compare Register

Name Address Default Value

PWM1COM1 0xFFFF0F84 0x00

PWM1COM2 0xFFFF0F88 0x00

PWM1COM3 0xFFFF0F8C 0x00

PWM2COM1 0xFFFF0F94 0x00

PWM2COM2 0xFFFF0F98 0x00

PWM2COM3 0xFFFF0F9C 0x00

PWM3COM1 0xFFFF0FA4 0x00

PWM3COM2 0xFFFF0FA8 0x00

PWM3COM3 0xFFFF0FAC 0x00

The PWM trip interrupt can be cleared by writing any value to the PWMICLR MMR. Note that when using the PWM trip interrupt, users should make sure that the PWM interrupt has been cleared before exiting the ISR. This prevents generation of multiple interrupts.

PWM CONVERT START CONTROL

The PWM can be configured to generate an ADC convert start signal after the active low side signal goes high. There is a programmable delay between when the low-side signal goes high and the convert start signal is generated.

This is controlled via the PWMCON2 MMR. If the delay selected is higher than the width of the PWM pulse, the interrupt remains low.

Access

R/W

Preliminary Technical Data

Table 79. PWMCON2 MMR Bit Designations

(Address = 0xFFFF0FB4, Default Value = 0x00)

Bit Value Name Description

7 CSEN Set to 1 by the user to enable the PWM to generate a convert start signal.

Cleared by user to disable the PWM convert start signal.

3:0 CSD3 Convert start delay. Delays the convert start signal by a number of clock pulses.

CSD2

CSD1

CSD0

0000 4 clock pulses.

0001

0010

0011

0100

0101

0110

0111

1000

8 clock pulses.

12 clock pulses.

16 clock pulses.

20 clock pulses.

24 clock pulses.

28 clock pulses.

32 clock pulses.

36 clock pulses.

1001

1010

1011

1100

1101

1110

1111

40 clock pulses.

44 clock pulses.

48 clock pulses.

52 clock pulses.

56 clock pulses.

60 clock pulses.

64 clock pulses.

When calculating the time from the convert start delay to the start of an ADC conversion, the user needs to take account of internal delays. The example below shows the case for a delay of four clocks. One additional clock is required to pass the convert start signal to the ADC logic. Once the ADC logic receives the convert start signal an ADC conversion begins on the next

ADC clock edge (see Figure 33).

UCLOCK

LOW SIDE

COUNT

PWM SIGNAL

TO CONVST

SIGNAL PASSED

TO ADC LOGIC

Figure 33. ADC Conversion

Rev. PrA | Page 48 of 92

Preliminary Technical Data

GENERAL-PURPOSE I/O

The ADuC7122 provides 32 general-purpose, bidirectional I/O

(GPIO) pins. All I/O pins are 5 V tolerant, meaning that the

GPIOs support an input voltage of 5 V. In general, many of the

GPIO pins have multiple functions (see Table 82). By default, the

GPIO pins are configured in GPIO mode.

All GPIO pins have an internal pull-up resistor (of about 100 kΩ) and their drive capability is 1.6 mA. Note that a maximum of 20 GPIO can drive 1.6 mA at the same time. The 32 GPIOs are grouped in four ports: Port 0 to Port 3. Each port is controlled by four or five MMRs, with x representing the port number.

Table 80. GPxCON Register

Name Address Default

GP0CON 0xFFFF0D00 0x00000000 R/W

GP1CON 0xFFFF0D04 0x00000000 R/W

GP2CON 0xFFFF0D08 0x00000000 R/W

GP3CON 0xFFFF0D0C 0x11111111 R/W

The input level of any GPIO can be read at any time in the

GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active.

When the ADuC7122 parts enter a power-saving mode, the

GPIO pins retain their state.

GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 82.

Table 81. GPxCON MMR Bit Designations

Bit Description

31:30 Reserved

29:28 Select function of Px.7 pin

27:26 Reserved

25:24 Select function of Px.6 pin

23:22 Reserved

21:20 Select function of Px.5 pin

19:18 Reserved

17:16 Select function of Px.4 pin

15:14 Reserved

13:12 Select function of Px.3 pin

11:10 Reserved

9:8 Select function of Px.2 pin

7:6 Reserved

5:4 Select function of Px.1 pin

3:2 Reserved

1:0 Select function of Px.0 pin

ADuC7122

Table 82. GPIO Pin Function Designations

Port Pin 00

0 P0.0

Configuration (see GPxCON)

01 10 11

SCL1 N/A

P0.1

GPIO SDA1 disabled

PLAI[5]

PLAI[4]

PLAO[13]

P0.3 GPIO disabled

SPIMISO SYNC PLAO[12]

P0.4 GPIO SPIMOSI TRIP PLAI[11]

CONVST PLAI[10]

GPIO TRST

PLAI[2]

N/A PLAI[3]

1 P1.0 SIN SCL2 PLAI[7]

GPIO SOUT PLAI[1]

GPIO PWM1 PLAI[8]

3 P3.0 N/A N/A

PLAI[9]

PLAO[5]

PLAO[4]

PLAI[13]

PLAI[12]

PLAI[1]

PLAI[14]

PLAO[7]

PLAO[6]

PLAI[15]

PLAI[0]

PLAO[0]

PLAO[1]

PLAO[2]

PLAO[3]

PLAO[8]

PLAO[9]

PLAO[10]

PLAO[11]

1 N/A means no secondary function exists.

Rev. PrA | Page 49 of 92

ADuC7122

Table 83. GPxPAR Register

Name Address Default Value Access

GP0PAR 0xFFFF0D2C 0x20000000 RW

GP1PAR 0xFFFF0D3C 0x00000000 RW

GP2PAR 0xFFFF0D4C 0x00000000 RW

GP3PAR 0xFFFF0D5C 0x00222222 RW

GPxPAR programs the parameters for Port 0, Port 1, Port 2 and

Port 3. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR.

Table 84. GPxPAR MMR Bit Designations

Bit Description

31:29 Reserved

28 Pull-up disable Px.7 pin

27:25 Reserved

24 Pull-up disable Px.6 pin

23:21 Reserved

20 Pull-up disable Px.5 pin

19:17 Reserved

16 Pull-up disable Px.4 pin

15:13 Reserved

12 Pull-up disable Px.3 pin

11:9 Reserved

8 Pull-up disable Px.2 pin

7:5 Reserved

4 Pull-up disable Px.1 pin

3:1 Reserved

0 Pull-up disable Px.0 pin

Table 85. GPxDAT Register

Name Address Default Value Access

GP0DAT 0xFFFF0D20 0x000000XX R/W

GP1DAT 0xFFFF0D30 0x000000XX R/W

GP2DAT 0xFFFF0D40 0x000000XX R/W

GP3DAT 0xFFFF0D50 0x000000XX R/W

GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port x, sets the output value for the pins configured as output, and receives and stores the input value of the pins configured as input.

Table 86. GPxDAT MMR Bit Designations

Bit Description

31:24 Direction of the Data.

Set to 1 by user to configure the GPIO pin as an output.

Cleared to 0 by user to configure the GPIO pin as an input.

23:16

15:8

7:0

Port x Data Output.

Reflect the state of Port x pins at reset (read only).

Port x Data Input (Read Only).

Preliminary Technical Data

Table 87. GPxSET Register

Name Address Default Value Access

GP0SET 0xFFFF0D24 0x000000XX W

GP1SET 0xFFFF0D34 0x000000XX W

GP2SET 0xFFFF0D44 0x000000XX W

GP3SET 0xFFFF0D54 0x000000XX W

GPxSET is a data set Port x register.

Table 88. GPxSET MMR Bit Designations

Bit Description

31: 24 Reserved.

23:16 Data Port x Set Bit.

Set to 1 by user to set bit on Port x; also sets the corresponding bit in the GPxDAT MMR.

Cleared to 0 by user; does not affect the data out.

15: 0 Reserved.

GPxCLR Register

Name Address Default Value Access

GP0CLR 0xFFFF0D28 0x000000XX W

GP1CLR 0xFFFF0D38 0x000000XX W

GP2CLR 0xFFFF0D48 0x000000XX W

GP3CLR 0xFFFF0D58 0x000000XX W

GPxCLR is a data clear Port x register.

Table 89. GPxCLR MMR Bit Designations

Bit Description

31:24 Reserved.

23:16 Data Port x Clear Bit.

Set to 1 by user to clear bit on Port x; also clears the corresponding bit in the GPxDAT MMR.

Cleared to 0 by user; does not affect the data out.

15:0 Reserved.

Rev. PrA | Page 50 of 92

Preliminary Technical Data

Open collector functionality is available on the following GPIO pins: P1.7, P1.6, port 2 and port 3.

Table 90. GPxOCE MMR Bit Designations

Bit Description

31:8 Reserved.

GPIO Px.7 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open collector

GPIO Px.6 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

GPIO Px.5 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

GPIO Px.4 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

GPIO Px.3 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

GPIO Px.2 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

GPIO Px.1 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

GPIO Px.0 open-collector enable

Set to 1 by the user to enable open-collector

Set to 0 by the user to disable open-collector

ADuC7122

Rev. PrA | Page 51 of 92

ADuC7122

UART SERIAL INTERFACE

The ADuC7122 features a 16450-compatible UART.

The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode. The UART functionality is available on the P1.0 and P1.1 pins of the ADuC7122.

The serial communication adopts an asynchronous protocol that supports various word length, stop bits, and parity generation options selectable in the configuration register.

BAUD RATE GENERATION

The ADuC7122 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and

ADuC7122 fractional divider.

Normal 450 UART Baud Rate Generation

The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).

The standard baud rate generator formula is

Baud rate



41 .

78 MHz



Table 91 lists common baud rate values.

Table 91. Baud Rate Using the Standard Baud Rate Generator

Baud Rate DL Actual Baud Rate % Error

ADuC7122 Fractional Divider

The fractional divider combined with the normal baud rate generator allows the generating of a wider range of more accurate baud rates.

CORE

CLOCK

FBEN

/16DL

/(M + N/2048)

Figure 34. Baud Rate Generation Options

UART

Preliminary Technical Data

Calculation of the baud rate using fractional divider is as follows:

Baud Rate





41 .

78 MHz



(



2048

)

(2)



2048



Baud

41 .

78 MHz

Rate



For example, generation of 19,200 baud

 N

2048



41 .

78 MHz

19200



 N

2048



1 .

015 where:

M = 1.

N = 0.015 × 2048 = 30.

Baud Rate





41 .





MHz



2048 where Baud Rate = 19,219 bps.



The UART interface consists of the following ten registers:

COMTX: 8-bit transmit register

COMRX: 8-bit receive register

COMDIV0: divisor latch (low byte)

COMDIV1: divisor latch (high byte)

COMCON0: line control register

COMCON1: line control register

COMSTA0: line status register

COMIEN0: interrupt enable register

COMIID0: interrupt identification register

COMDIV2: 16-bit fractional baud divide register

COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared. COMDIV0 can be accessed when Bit 7 of COMCON0 is set.

Rev. PrA | Page 52 of 92

UART TX Register

Write to this 8-bit register to transmit data using the UART.

Name: COMTX

Address: 0xFFFF0800

UART RX Register

This 8-bit register is read from to receive data transmitted using the UART.

Name: COMRX

Address: 0xFFFF0800

Default Value: 0x00

UART Divisor Latch Register 0

This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates.

Name: COMDIV0

Address: 0xFFFF0800

Default Value: 0x00

Access: Read/write

UART Divisor Latch Register 1

This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates.

Name: COMDIV1

Address: 0xFFFF0804

Default Value: 0x00

Access: Read/write

UART Control Register 0

This 8-bit register controls the operation of the UART in conjunction with COMCON1.

Name: COMCON0

Address: 0xFFFF080C

Default Value: 0x00

Access: Read/write

Rev. PrA | Page 53 of 92

ADuC7122 Preliminary Technical Data

Table 92. COMCON0 MMR Bit Designations

Bit Name Description

7 DLAB Divisor latch access.

Set by user to enable access to COMDIV0 and COMDIV1 registers.

Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX,

COMTX, and COMIEN0.

EPS

PEN

Set by user to force TxD to 0.

Cleared to operate in normal mode.

Stick parity. Set by user to force parity to defined values.

1 if EPS = 1 and PEN = 1.

0 if EPS = 0 and PEN = 1.

Even parity select bit.

Set for even parity.

Cleared for odd parity.

Parity enable bit.

Set by user to transmit and check the parity bit.

Cleared by user for no parity transmission or checking.

1 to 0 WLS

UART Control Register 1

Set by the user to transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected.

Cleared by the user to generate one stop bit in the transmitted data.

Word length select.

00 = 5 bits.

01 = 6 bits.

10 = 7 bits.

11 = 8 bits.

This 8-bit register controls the operation of the UART in conjunction with COMCON0.

Table 93. COMCON1 MMR Bit Designations

Bit Name

7:5

Description

Reserved bits. Not used.

Name: COMCON1

Address: 0xFFFF0810

Default Value: 0x00

Access: Read/write

3:2

1 RTS

DTR mode. In loopback mode, the TxD is forced high.

Reserved bits. Not used.

Request to send.

Set by user to force the RTS output to 0.

Cleared by user to force the RTS output to

Data Terminal Ready.

Set by user to force the DTR output to 0.

Cleared by user to force the DTR output to 1.

Rev. PrA | Page 54 of 92

ADuC7122

UART Status Register 0

Name: COMSTA0

Address: 0xFFFF0714

Default Value: 0x60

Preliminary Technical Data

Function: This 8-bit read-only register reflects the current status on the UART.

Table 94. COMSTA0 MMR Bit Designations

Bit Name Description

7 Reserved.

6 TEMT COMTX and shift register empty status bit.

Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted, that is, no more data is present in the shift register.

Cleared automatically when writing to COMTX.

5 THRE COMTX empty status bit.

Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set, the previous data might not have been transmitted yet and can still be present in the shift register.

Cleared automatically when writing to COMTX.

4 BI Break

Set when SIN is held low for more than the maximum word length.

Cleared

3 FE Framing

Set when the stop bit is invalid.

Cleared

Set when a parity error occurs.

Cleared

Set automatically if data are overwritten before being read.

Cleared

Set automatically when COMRX is full.

Cleared by reading COMRX.

Rev. PrA | Page 55 of 92

ADuC7122

UART Interrupt Enable Register 0

Name: COMIEN0

Address: 0xFFFF0804

Default value: 0x00

Access: Read/write

Function: The 8-bit register enables and disables the individual UART interrupt sources.

Table 95. COMIEN0 MMR Bit Designations

7:4

Reserved. Not used.

EDSSI Modem Status Interrupt Enable Bit.

ELSI

Set by user to enable generation of an interrupt if any of COMSTA0[3:1] are set.

Cleared by user.

RxD Status Interrupt Enable Bit.

Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set.

Cleared by the user.

ETBEI Enable Transmit Buffer Empty Interrupt.

Set by the user to enable an interrupt when the buffer is empty during a transmission, that is, when COMSTA[5] is set.

Cleared by the user.

ERBFI Enable Receive Buffer Full Interrupt.

Set by the user to enable an interrupt when the buffer is full during a reception.

Cleared by the user.

UART Interrupt Identification Register 0

Name: COMIID0

Address: 0xFFFF0808

Default value: 0x01

Function: This 8-bit register reflects the source of the

UART interrupt.

Preliminary Technical Data

Table 96. COMIID0 MMR Bit Designations

Bits[2:1]

Status

Bits

Bit 0

NINT Priority Definition

Clearing

Operation

status interrupt

Read

COMSTA0

Read COMRX buffer full interrupt buffer empty interrupt status interrupt

Write data to

COMTX or read COMIID0

Read

COMSTA1 register

UART Fractional Divider Register

This 16-bit register controls the operation of the fractional divider for the ADuC7122.

Name: COMDIV2

Address: 0xFFFF082C

Default value: 0x0000

Access: Read/write

Table 97. COMDIV2 MMR Bit Designations

Bit Name Description

15 FBEN Fractional Baud Rate Generator Enable Bit.

Set by the user to enable the fractional baud rate generator.

Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator.

14:13 Reserved.

12:11 FBM[1:0] M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using a fractional divider and table 76 for common baud rate values. baud rate using a fractional divider and table 76 for common baud rate values.

Rev. PrA | Page 56 of 92

Preliminary Technical Data

2

The ADuC7122 incorporates two I

C peripherals that can be separately configured as a fully I

C compatible I

C bus Master device or, as a fully I2C bus compatible slave device. Because both peripherals are identical, only one is explained here.

The two pins used for data transfer, SDA and SCL, are configured in a wired-AND format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 kΩ and 10 kΩ.

The I 2 C bus peripheral’s address in the I 2 C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses.

The transfer sequence of an I

C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (Read or /Write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle.

The I

C peripheral can only be configured as a master or slave at any given time. The same I

C channel cannot simultaneously support master and slave modes.

The I

C interface on the ADuC7122 includes the following features:

 Support for Repeated Start Conditions. In Master mode, the ADuC7122 can be programmed to generate a Repeated

Start. In Slave mode, the ADuC7122 recognizes Repeated

Start conditions.

 In Master and Slave mode, the part recognizes both 7-bit and 10-bit bus addresses.

 In I2C Master mode, the ADuC7122 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence.

 Clock stretching is supported in both Master and Slave modes.

 In Slave mode, the ADuC7122 can be programmed to return a “NACK.” This allows the validiation of checksum bytes at the end of I2C transfers.

 Bus arbitration in Master mode is supported.

 Internal and external loopback modes are supported for

I2C hardware testing. In loopback mode.

 The Transmit and receive circuits in both Master and Slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs.

ADuC7122

Configuring External pins for I2C functionality

The I2C pins of the ADuC7122 device are P0.0 and P0.1 for

I2C1, and P1.0 and P1.1 for I2C2.

P0.0 and P1.0 are the I2C clock signals and P0.1 and P1.1 are the I2C data signals. For instance, to configure the I2C1 pins

(SCL1, SDA1), Bit 0 and Bit 4 of the GP0CON register must be set to 1 to enable I

C mode. Alternatively, to configure the I2C2 pins (SCL2, SDA2), Bit 1 and Bit 5 of the GP0CON register must be set to 1 to enable I

C mode.

SERIAL CLOCK GENERATION

The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz).

The bit rate is defined in the I2CxDIV MMR as follows:

SERIAL CLOCK



( 2



DIVH f

UCLK

)



DIVL

) where:

UCLK

= clock before the clock divider.

DIVH = the high period of the clock.

DIVL = the low period of the clock.

Thus, for 100 kHz operation

DIVH = DIVL = 0xCF and for 400 kHz

DIVH = 0x28, DIVL = 0x3C

The I2CxDIV register corresponds to DIVH:DIVL

I

C BUS ADDRESSES

Slave Mode

In slave mode, the registers I2CID0, I2CID1, I2CID2, and

I2CID3 contain the device IDs. The device compares the four

I2CIDx registers to the address byte received from the bus

Master. To be correctly addressed, the 7 MSBs of either ID register must be identical to that of the 7 MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition.

The ADuC7122 also supports 10-bit addressing mode. When

Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in registers

I2CID0 and I2CID1. The 10-bit address is derived as follows:

I2CID0[0] is the read/write bit and is not part of the I

C address.

I2CID0[7:1] = Address Bits[6:0].

I2CID1[2:0] = Address Bits[9:7].

I2CID1[7:3] must be set to 11110b

Rev. PrA | Page 57 of 92

ADuC7122

Master Mode

In master mode, the I2CADR0 register is programmed with the

C address of the device.

In 7-bit address mode, I2CADR0[7:1] are set to the device address. I2CADR0[0] is the read/write bit.

In 10-bit address mode, the 10-bit address is created as follows:

I2CADR0[7:3] must be set to 11110b.

I2CADR0[2:1] = Address Bits[9:8].

I2CADR1[7:0] = Address Bits[7:0].

I2CADR0[0] is the read/write bit.

I

C REGISTERS

The I

C peripheral interfaces consists of a number of MMRs.

These are described in the following section.

Preliminary Technical Data

I

C Master Registers

I

C Master Control Register

Default value: 0x0000, 0x0000

Access: Read/write

Function: This 16-bit MMR configures I

C peripheral in master mode.

Table 98. I2CxMCTL MMR Bit Designations

Bit Name Description

15:9 Reserved. These bits are reserved and should not be written to

I2CMCENI I2C transmission complete Interrupt Enable bit

Set this bit to enable an interrupt on detecting a Stop condition on the I2C bus.

Clear this interrupt source.

I2CNACKENI I2C NACK received Interrupt enable bit.

I2CALENI

I2CMTENI

I2CMRENI

I2CMSEN

Set this bit to enable interrupts when the I2C master receives a NACK.

Clear this interrupt source.

I2C Arbitration lost Interrupt Enable bit..

Set this bit to enable interrupts when the I2C master has lost in trying to gain control of the I2C bus.

Clear this interrupt source.

I2C Transmit Interrupt Enable bit.

Set this bit to enable interrupts when the I2C master has transmitted a byte

Clear this interrupt source.

I2C Receive Interrupt Enable bit.

Set this bit to enable interrupts when the I2C master receives data

Cleared by user to disable interrupts when the I2C master is receiving data

I2C Master SCL stretch Enable bit.

Set this bit to 1 to enable Clock stretching. When SCL is low, setting this bit will force the device to hold SCL low until

I2CMSEN is cleared. If SCL is high, setting this bit will force the device to hold SCL low after the next falling edge.

Clear this bit to disable clock stretching.

I2CILEN

I2CBD

I2CMEN

I2C Internal Loopback Enable

Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their

Respective input signals.

Cleared by user to disable Loopback mode.

I2C Master Backoff Disable bit

Set this bit to allow the device to compete for control of the bus even if another device is currently driving a Start Condition

Clear this bit to back off until the I2C bus becomes free.

I2C Master Enable bit.

Set by user to enable I2C Master mode.

Cleared disable I2C Master mode.

Rev. PrA | Page 58 of 92

Preliminary Technical Data

I

C Master Status Register

Name: I2C0MSTA , I2C1MSTA

ADuC7122

Default value: 0x0000, 0x0000

Access: Read

Function: This 16-bit MMR is I

C status register in master mode.

Table 99 I2CxMSTA MMR Bit Designations

Bit Name Description

15:11 Reserved. These bits are reserved.

10 I2CBBUSY C bus busy status bit.

This bit is set to 1 when a Start condition is detected on the I

C bus.

This bit is cleared when a Stop condition is detected on the bus

I2CMRxFO Master Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit will be cleared in all other conditions.

8 I2CMTC I 2 C transmission complete status bit.

This bit is set to 1 when a transmission is complete between the Master and the Slave it was communicating with.

If the I2CMCENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set.

Clear this interrupt source.

C master NACK data bit

This bit will be set to 1 when a NACK condition is received by the Master in response to a Data write transfer.

If the I2CNACKENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set.

This bit will be cleared in all other conditions.

Set to 1 when the Master is busy processing a transaction.

Cleared if the Master is ready or if another Master device has control of the bus

5 I2CAL I

C arbitration lost status bit..

This bit is set to 1 when the I2C master has lost in trying to gain control of the I2C bus.

If the I2CALENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set.

This bit will be cleared in all other conditions.

C master NACK address bit

This bit will be set to 1 when a NACK condition is received by the Master in response to an Address.

If the I2CNACKENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set.

This bit will be cleared in all other conditions.

This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt will be generated.

This bit will be cleared in all other conditions.

This bit will go high if the Tx FIFO is empty or only contains 1 byte and the master has transmitted an address + write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set.

This bit will be cleared in all other conditions.

00 = I 2 C master Tx FIFO empty

01 = 1 byte in master Tx FIFO

10 = 1 byte in master Tx FIFO

11 = I

C Master Tx FIFO Full.

Rev. PrA | Page 59 of 92

ADuC7122

I

C Master Receive Register

Name: I2C0MRX , I2C1MRX

Preliminary Technical Data

I

C Master Read Count Register

Default Value: 0x00, 0x00

Function: This 8-bit MMR is the I

C master receive register.

I

C Master Transmit Register

Default Value: 0x0000, 0x0000

Access: Read/write

Function: This 16-bit MMR holds the required number of bytes when the master begins a read sequence from a slave device.

I

C Master Current Read Count Register

Name: I2C0MCNT1I2C1MCNT1

Default Value: 0x00, 0x00

Function: This 8-bit MMR is the I register.

2 C master transmit

Default value: 0x00, 0x00

Access: Read

Function: This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device.

Table 100. I2CxMCNT0 MMR Bit Descriptions (Address = 0xFFFF0890, 0xFFFF0910, Default value = 0x0000)

15:9 Reserved.

8 I2CRECNT Set this bit if greater than 256 bytes are required from the slave.

Clear this bit when reading 256 bytes or less. required, these bits should be set to 0.

Rev. PrA | Page 60 of 92

Preliminary Technical Data

I

C Address 0 Register

ADuC7122

I

C Master Clock Control Register

Default value: 0x00, 0x00

Access: Read/write

Function: This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins communicating with a slave.

I

C Address 1 Register

Default Value: 0x1F1F, 0x1F1F

Access: Read/write

Function: This MMR controls the frequency of the I

C clock generated by the master on to the SCL pin. For further details, see I2C initial section.

Address: 0xFFFF089C , 0xFFFF091C

Default value: 0x00, 0x00

Access: Read/write

Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address.

Table 101. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0898, 0xFFFF0918, Default Value = 0x00)

7:1

I2CADR

R/W

These bits contain the 7-bit address of the required slave device.

Bit 0 is the read/write bit.

When this bit = 1, a read sequence is requested.

When this bit = 0, a write sequence is requested.

Table 102. I2CxADR0 MMR in 10-Bit Address Mode

7:3

2:1

These bits must be set to [11110b] in 10-bit address mode.

I2CMADR These bits contain ADDR[9:8] in 10-bit addressing mode.

R/W Read/write bit.

When this bit = 1, a read sequence is requested.

When this bit = 0, a write sequence is requested.

Table 103. I2CxADR1 MMR in 10-Bit Address Mode

7:0 I2CLADR These bits contain ADDR[7:0] in 10-bit addressing mode.

Table 104. I2CxDIV MMR

15:8

7:0

DIVH

DIVL

These bits control the duration of the High period of SCL.

These bits control the duration of the low period of SCL.

Rev. PrA | Page 61 of 92

ADuC7122

I

C Slave Registers

I

C Slave Control Register

Preliminary Technical Data

Default Value: 0x0000, 0x000

Access: Read/write

Function: This 16-bit MMR configures the I

C peripheral in slave mode.

Table 105. I2CxSCTL MMR Bit Designations

Bit Name Description

15:11

10 I2CSTXENI Slave transmit interrupt enable bit.

Set this bit to enable an interrupt after a slave transmits a byte.

Clear this interrupt source.

9 I2CSRXENI Slave receive interrupt enable bit.

Set this bit to enable an interrupt after the Slave receives data.

Clear this interrupt source.

8 I2CSSENI C stop condition detected interrupt enable bit

Set this bit to enable an interrupt on detecting a Stop condition on the I2C bus.

Clear this interrupt source.

Set this bit to NACK the next byte in the transmission sequence.

Clear this bit to let the Hardware control the ACK/NACK sequence.

6 I2CSSEN 2 C slave SCL stretch enable bit.

Set this bit to 1 to enable Clock stretching. When SCL is low, setting this bit will force the device to hold

SCL low until I2CSSEN is cleared. If SCL is high, setting this bit will force the device to hold SCL low after the next falling edge.

Clear this bit to disable clock stretching.

Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit

Transmission.

Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the Read bit

Transmission.

Writing a 1 to this bit will clear the general call status and ID bits in the I2CxSSTA register.

Clear this bit at all other times.

Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC7122 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately.

The LSB of the I2CxALT register should always be written to 1, as per the I

C January 2000 bus specification.

Set this bit and I2CGCEN to enable Hardware General call recognition in Slave mode.

Clear to disable recognition of Hardware General Call commands.

Rev. PrA | Page 62 of 92

Preliminary Technical Data ADuC7122

Bit Name Description

2 I2CGCEN C general call enable.

Set this bit to enable the slave device to acknowledge an I

C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I 2 C interface resets as per the I 2 C January 2000 bus specification. This command can be used to reset an entire I

C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call.

The user must take corrective action by reprogramming the device address.

Set this bit to allow the Slave “ACK” I2C General Call commands.

Clear to disable recognition of General Call commands.

1 Reserved Always set this bit = 0.

0 I2CSEN I

C slave enable bit.

Set by user to enable I 2 C slave mode.

Clear to disable I

Cslave mode.

I

C Slave Status Registers

Default Value: 0x0000, 0x0000

Access: Read/write

Function: This 16-bit MMR is the I

C status register in slave mode.

Table 106. I2CxSSTA MMR Bit Designations

Bit Name Description

I2CSTA

I2CREPS

This bit is set to 1 if:

A start condition followed by a matching address is detected.

It is also set if a start byte (0x01) is received.

If general calls are enabled and a general call code of 0x00 is received.

This bit is cleared on receiving a stop condition

This bit is set to 1 if a repeated start condition is detected.

This bit is cleared on receiving a stop condition

12-11 I2CID[1:0] I2C Address matching register. These bits indicate which I2CxIDx register matches the received address.

00 = received address matches I2CxID0

01 = received address matches I2CxID1

10 = received address matches I2CxID2

11 = received address matches I2CxID3

10 I2CSS I

C stop condition after start detected bit.

This bit is set to 1 when a stop condition is detected after a previous start and matching address.

When the I2CSSENI bit in I2CxSCTL is set, an interrupt is generated.

This bit is cleared by reading this register.

00 = no general call received.

01 = general call reset and program address.

10 = general program address.

11 = general call matching alternative ID

Note that these bits are not cleared by a general call reset command.

Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL.

Rev. PrA | Page 63 of 92

ADuC7122 Preliminary Technical Data

Bit Name Description

7 I2CGC I

C general call status bit

This bit is set to 1 if the slave receives a general call command of any type.

If the command received was a reset command, then all registers will return to their default state.

If the command received was a hardware general call, the Rx FIFO holds the 2 nd

byte of the command and this can be compared with the I2CxALT register.

Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL.

6 I2CSBUSY C slave busy status bit

Set to 1 when the slave receives a start condition

Cleared by hardware if:

The received address does not match any of the I2CxIDx registers

The slave device receives a stop condition.

If a repeated start address does not match any of the I2CxIDx registers

5 I2CSNA I

C slave NACK data bit

This bit is set to 1 when the slave responded to a bus address with a NACK. This bit is asserted under the following conditions:

If NACK was returned because there was no data in the Tx FIFO

If the I2CNACKEN bit was set in the I2CxSCTL register.

This bit is cleared in all other conditions.

I2CSRxFO

I2CSRXQ

Slave Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I2C slave receive request bit

This bit is set to 1 when the slave’s Rx FIFO is not empty.

This bit causes an interrupt to occur if the I2CSRXENI bit in I2CxSCTL is set.

The Rx FIFO must be read or flushed to clear this bit

2 I2CSTXQ I

C slave transmit request bit

This bit is set to 1 when the slave receives a matching address followed by a read.

If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCL during the read bit transmission.

If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the read bit transmission.

This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.

This bit is cleared in all other conditions.

1 I2CSTFE I

C slave FIFO underflow status bit.

This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit.

This bit is cleared in all other conditions.

0 I2CETSTA I

C slave early transmit FIFO status bit

If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high of the slave Tx FIFO is empty.

If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission.

This bit asserts once only for a transfer.

This bit is cleared after being read.

Rev. PrA | Page 64 of 92

Preliminary Technical Data

I

C Slave Receive Registers

Default value: 0x00

Access: Read

Function: This 8-bit MMR is the I

C slave receive register.

I

C Slave Transmit Registers

Name: I2C0STX, I2C1STX

Default value: 0x00

Access: Write

Function: This 8-bit MMR is the I

C slave transmit register.

I

C Hardware General Call Recognition Registers

ADuC7122

I

C Slave Device ID Registers

Addresses: 0xFFFF093C = I2C1ID0

0xFFFF08BC = I2C0ID0

0xFFFF08C0 = I2C0ID1

0xFFFF08C4 = I2C0ID2

0xFFFF08C8 = I2C0ID3

Default value: 0x00

Access: Read/write

Function: These 8-bit MMRs are programmed with I

C bus IDs of the slave. See the I2C Bus Addresses section for further details.

Default value: 0x00

Access: Read/write

Function: This 8-bit MMR is used with hardware general calls when I2CxSCTL bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master.

Rev. PrA | Page 65 of 92

ADuC7122

I

C COMMON REGISTERS

I

C FIFO Status Register

Preliminary Technical Data

Default value: 0x0000

Access: Read/write

Function: These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes.

Table 107. I2CxFSTA MMR Bit Designations

Bit Name

15:10

Description

9 I2CFMTX Set this bit to 1 to flush the master, Tx FIFO.

8 I2CFSTX Set this bit to 1 to flush the slave, Tx FIFO.

7:6 I2CMRXSTA I

C master receive FIFO status bits.

00 = FIFO empty.

01 = byte written to FIFO.

10 = 1 byte in FIFO.

11 = FIFO full.

5:4 I2CMTXSTA I 2 C master transmit FIFO status bits.

3:2 I2CSRXSTA

1:0 I2CSTXSTA

00 = FIFO empty.

01 = byte written to FIFO.

10 = 1 byte in FIFO.

11 = FIFO full.

2 C slave receive FIFO status bits.

00 = FIFO empty

01 = byte written to FIFO

10 = 1 byte in FIFO

11 = FIFO full

C slave transmit FIFO status bits.

00 = FIFO empty.

01 = byte written to FIFO.

10 = 1 byte in FIFO.

11 = FIFO full.

Rev. PrA | Page 66 of 92

Preliminary Technical Data

SERIAL PERIPHERAL INTERFACE

The ADuC7122 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 Mb.

The SPI port can be configured for master or slave operation and typically consists of four pins: SPIMISO, SPIMOSI,

SPICLK, and SPI CS.

SPIMISO (MASTER IN, SLAVE OUT) PIN

The SPIMISO pin is configured as an input line in master mode and an output line in slave mode. The SPIMISO line on the master (data in) should be connected to the SPIMISO line in the slave device (data out). The data is transferred as byte wide

(8-bit) serial data, MSB first.

SPIMOSI (MASTER OUT, SLAVE IN) PIN

The SPIMOSI pin is configured as an output line in master mode and an input line in slave mode. The SPIMOSI line on the master (data out) should be connected to the SPIMOSI line in the slave device (data in). The data is transferred as byte wide

(8-bit) serial data, MSB first.

SPICLK (SERIAL CLOCK I/O) PIN

The master serial clock (SPICLK) synchronizes the data being transmitted and received through the MOSI SPICLK period.

Therefore, a byte is transmitted/received after eight SPICLK periods. The SPICLK pin is configured as an output in master mode and as an input in slave mode.

In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the

SPIDIV register as follows:

SERIAL CLOCK





( 1

UCLK



SPIDIV

)

The maximum speed of the SPI clock is independent on the clock divider bits.

In Slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10 Mb.

In both master and slave modes, data is transmitted on one edge of the SPICLK signal and sampled on the other. Therefore, it is important that the polarity and phase are configured the same for the master and slave devices.

ADuC7122

SPI CHIP SELECT (SPI CS INPUT) PIN

In SPI slave mode, a transfer is initiated by the assertion of SPI

CS, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of SPI CS. In slave mode, SPI CS is always an input.

In SPI master mode, the SPICS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion.

CONFIGURING EXTERNAL PINS FOR SPI

FUNCTIONALITY

The SPI pins of the ADuC7122 device are P0[2..4].

P0.5 is the Slave Chip Select pin. In Slave mode, this pin is an input and must be driven low by the Master. In Master mode, this pin is an output and will go low at the beginning of a transfer and high at the end of a transfer.

P0.2 is the SPICLK pin.

P0.3 is the master in, slave out (SPIMISO) pin.

P0.4 is the master out, slave in (SPIMOSI) pin.

To configure P0[2:4] for SPI mode, see the General-Purpose

I/O section.

Rev. PrA | Page 67 of 92

ADuC7122

SPI REGISTERS

The following MMR registers control the SPI interface: SPISTA,

SPIRX, SPITX, SPIDIV, and SPICON.

Preliminary Technical Data

SPI Status Register

Name: SPISTA

Address: 0xFFFF0A00

Default value: 0x0000

Access: Read/write

Function: This 16-bit MMR contains the status of the SPI interface in both master and slave modes.

Table 108. SPISTA MMR Bit Designations

Bit Name

15:12

Description

11 SPIREX

10:8

3:1

SPIRXFSTA[2:0]

SPIFOF

SPIRXIRQ

SPITXIRQ

SPITXUF

SPITXFSTA[2:0]

SPIISTA

SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the

SPIMDE bits in SPICON

This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIRXMDE.

SPI Rx FIFO status bits.

000 = Rx FIFO is empty

001 = 1 valid byte in the FIFO

010 = 2 valid bytes in the FIFO

011 = 3 valid bytes in the FIFO

100 = 4 valid bytes in the FIFO

Clear this bit to disable clock stretching.

SPI Rx FIFO overflow status bit.

Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON.

Cleared when the SPISTA register is read.

SPI Rx IRQ status bit.

Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes have been received.

Cleared when the SPISTA register is read.

SPI Tx IRQ status bit.

Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes have been transmitted.

Cleared when the SPISTA register is read.

SPI Tx FIFO underflow.

This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON.

Cleared when the SPISTA register is read.

SPI Tx FIFO status bits.

000 = Tx FIFO is empty.

001 = 1 valid byte in the FIFO.

010 = 2 valid bytes in the FIFO.

011 = 3 valid bytes in the FIFO.

100 = 4 valid bytes in the FIFO.

Clear this bit to enable 7-bit address mode

SPI interrupt status bit.

Set to 1 when an SPI-based interrupt occurs.

Cleared after reading SPISTA.

Rev. PrA | Page 68 of 92

ADuC7122

SPIRX Register

Name: SPIRX

Address: 0xFFFF0A04

Default value: 0x00

Access: Read

Function: This 8-bit MMR is the SPI receive register.

SPITX Register

Name: SPITX

Address: 0xFFFF0A08

Default value: 0x00

Access: Write

Function: This 8-bit MMR is the SPI transmit register.

Preliminary Technical Data

SPIDIV Register

Name: SPIDIV

Address: 0xFFFF0A0C

Default value: 0x1B

Access: Write

Function: This 8-bit MMR is the SPI baud rate selection register.

SPI Control Register

Name: SPICON

Address: 0xFFFF0A10

Default value: 0x0000

Access: Read/write

Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes.

Table 109. SPICON MMR Bit Designations

Bit Name Description

15:14 SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.

00 = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received by the FIFO.

01 = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been received by the FIFO.

10 = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have been received by the FIFO.

11 = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or four bytes present

SPITFLH SPI Tx FIFO flush enable bit.

Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit.

Any writes to the Tx FIFO are ignored while this bit is set.

Clear this bit to disable Tx FIFO flushing.

SPIRFLH SPI Rx FIFO flush enable bit.

Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.

If this bit is set all incoming data is ignored and no interrupts are generated.

If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.

Clear this bit to disable Rx FIFO flushing.

SPICONT Continuous transfer enable.

Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the

Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.

10 SPILP

Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.

Loop back enable bit.

Set by user to connect MISO to MOSI and test software.

Cleared by user to be in normal mode.

Set this bit for MISO to operate as normal.

Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.

Rev. PrA | Page 69 of 92

ADuC7122 Preliminary Technical Data

Bit Name Description

8 SPIROW SPIRX overflow overwrite enable.

Set by user, the valid data in the Rx register is overwritten by the new serial byte received.

Cleared by user, the new serial byte received is discarded.

SPIZEN SPI transmit zeros when Tx FIFO is empty.

Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.

Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.

SPITMDE SPI transfer and interrupt mode.

Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.

Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.

SPILF LSB first transfer enable bit.

Set by user, the LSB is transmitted first

Cleared by user, the MSB is transmitted first.

SPIWOM SPI wired or mode enable bit

Set to 1 to enable open-drain data output enable. External pull-ups required on data out pins.

Clear for normal output levels..

SPICPO Serial clock polarity mode bit.

Set by user, the serial clock idles high

Cleared by user, the serial clock idles low.

SPICPH Serial clock phase mode bit.

Set by user, the serial clock pulses at the beginning of each serial bit transfer.

Cleared by user, the serial clock pulses at the end of each serial bit transfer.

SPIMEN Master mode enable bit

Set by user to enable master mode

Cleared by user to enable slave mode

SPIEN SPI enable bit.

Set by user to enable the SPI.

Cleared by user to disable the SPI.

Rev. PrA | Page 70 of 92

ADuC7122

PROGRAMMABLE LOGIC ARRAY (PLA)

The ADuC7122 integrates a fully programmable logic array

(PLA) that consists of two, independent but interconnected

PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements.

Each PLA element contains a two-input look-up table that can be configured to generate any logic output function based on two inputs and a flip-flop. This is represented in Figure 35.

LOOK-UP

TABLE

Figure 35. PLA Element

In total, 32 GPIO pins are available on each ADuC7122 for the

PLA. These include 16 input pins and 16 output pins, which need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins.

The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the

CONV

START

signal of the ADC, to an MMR, or to any of the 16

PLA output pins.

The two blocks can be interconnected as follows:

 Output of Element 15 (Block 1) can be fed back to Input 0 of

Mux 0 of Element 0 (Block 0)

 Output of Element 7 (Block 0) can be fed back to the Input 0 of Mux 0 of Element 8 (Block 1)

Table 110. Element Input/Output

PLA Block 0 PLA Block 1

Element Input Output Element Input Output

Preliminary Technical Data

Table 111. PLAELMx Registers

Name Address Default Value

PLAELM0 0xFFFF0B00 0x0000

PLAELM1 0xFFFF0B04 0x0000

PLAELM2 0xFFFF0B08 0x0000

PLAELM3 0xFFFF0B0C 0x0000

PLAELM4 0xFFFF0B10 0x0000

PLAELM5 0xFFFF0B14 0x0000

PLAELM6 0xFFFF0B18 0x0000

PLAELM7 0xFFFF0B1C 0x0000

PLAELM8 0xFFFF0B20 0x0000

PLAELM9 0xFFFF0B24 0x0000

PLAELM10 0xFFFF0B28 0x0000

PLAELM11 0xFFFF0B2C 0x0000

PLAELM12 0xFFFF0B30 0x0000

PLAELM13 0xFFFF0B34 0x0000

PLAELM14 0xFFFF0B38 0x0000

PLAELM15 0xFFFF0B3C 0x0000

Access

R/W

PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in the look-up table, and bypass/use the flip-flop. See

Table 112 and Table 117.

Table 112. PLAELMx MMR Bit Descriptions

31:11

10:9

Reserved.

Mux 0 control (see Table 117).

8:7 Mux 1 control (see Table 117).

6 Mux 2 control. Set by user to select the output of Mux 0. Cleared by user to select the bit value from PLADIN.

5 Mux 3 control. Set by user to select the input pin of the particular element. Cleared by user to select the output of Mux 1.

4:1 Look-up table control.

0010 B AND NOT A.

0100 A AND NOT B.

PLA MMRs Interface

The PLA peripheral interface consists of the 21 MMRs described in the following sections.

1011 NOT A OR B.

1101 A OR NOT B.

0 Mux 4 Control. Set by user to bypass the flipflop. Cleared by user to select the flip-flop

(cleared by default).

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ADuC7122

Table 113. PLACLK Register

Name Address Default Value

PLACLK 0xFFFF0B40 0x00

Access

R/W

PLACLK is the clock selection for the flip-flops of Block 0 and

Block 1. Note that the maximum frequency when using the

GPIO pins as the clock input for the PLA blocks is 44 MHz.

Table 114. PLACLK MMR Bit Descriptions

Bit Value Description

7 Reserved.

6:4

000

Block 1 clock source selection.

GPIO clock on P0.5.

001

010

GPIO clock on P0.0.

GPIO clock on P0.7.

011 HCLK.

100 External crystal (OCLK) (32.768 kHz).

101 Timer1

Other Reserved.

3 Reserved.

2:0

000

001

010

Block 0 clock source selection.

GPIO clock on P0.5.

GPIO clock on P0.0.

GPIO clock on P0.7.

011 HCLK.

100 External crystal (OCLK) (32.768 kHz).

101 Timer1

Other Reserved.

8:7

Table 117. Feedback Configuration

Bit

10:9

Value

PLAELM0

Element 15

Element 2

Element 4

Element 6

Element 1

Element 3

Element 5

Element 7

PLAELM1 to PLAELM7

Element 0

Element 2

Element 4

Element 6

Element 1

Element 3

Element 5

Element 7

Preliminary Technical Data

Table 115. PLAIRQ Register

Name Address Default Value Access

PLAIRQ 0xFFFF0B44 0x00000000 R/W

PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ.

Table 116. PLAIRQ MMR Bit Descriptions

15:13 Reserved.

12 PLA IRQ1 enable bit. Set by user to enable

IRQ1 output from PLA. Cleared by user to disable IRQ1 output from PLA.

11:8

0000

PLA IRQ1 source.

PLA Element 0.

0001

1111

PLA Element 1.

PLA Element 15.

7:5 Reserved.

4 PLA IRQ0 enable bit. Set by user to enable

IRQ0 output from PLA. Cleared by user to disable IRQ0 output from PLA.

3:0 PLA IRQ0 source.

0000

0001

1111

PLA Element 0.

PLA Element 1.

PLA Element 15.

PLAELM8

Element 7

Element 10

Element 12

Element 14

Element 9

Element 11

Element 13

Element 15

PLAELM9 to PLAELM15

Element 8

Element 10

Element 12

Element 14

Element 9

Element 11

Element 13

Element 15

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Preliminary Technical Data

PLAADC Register

Name Address Default Value Access

PLAADC 0xFFFF0B48 0x00000000 R/W

PLAADC is the PLA source for the ADC start conversion signal.

Table 118. PLAADC MMR Bit Descriptions

31:5 Reserved.

4 ADC start conversion enable bit. Set by user to enable ADC start conversion from PLA.

Cleared by user to disable ADC start conversion from PLA.

3:0 ADC start conversion source.

0000 PLA Element 0.

0001 PLA Element 1.

1111 PLA Element 15.

PLADIN Register

Name Address Default Value Access

PLADIN 0xFFFF0B4C 0x00000000 R/W

PLADIN is a data input MMR for PLA.

Table 119. PLADIN MMR Bit Descriptions

Bit Description

31:16 Reserved.

15:0 Input bit to Element 15 to Element 0.

PLADOUT Register

Name Address Default Value

PLADOUT 0xFFFF0B50 0x00000000

Access

PLADOUT is a data output MMR for PLA. This register is always updated.

Table 120. PLADOUT MMR Bit Descriptions

Bit Description

31:16 Reserved.

15:0 Output bit from Element 15 to Element 0.

PLALCK Register

Name Address Default Value

PLALCK 0xFFFF0B54 0x00

Access

PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMRs, except

PLADIN. A PLA tool is provided in the development system to easily configure the PLA.

INTERRUPT SYSTEM

There are 27 interrupt sources on the ADuC7122 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI) which is programmable by the user. The

ARM7TDMI CPU core only recognizes interrupts as one of two

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ADuC7122

types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately.

The control and configuration of the interrupt system is managed through a number of interrupt-related registers. The bits in each IRQ and FIQ register represent the same interrupt source as described in Table 121.

The ADuC7122 contains a vectored interrupt controller (VIC) that supports nested interrupts up to eight levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting needs to be enabled by setting the

ENIRQN bit in the IRQCONN register. A number of extra

MMRs are used when the full vectored interrupt controller is enabled.

IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced.

Table 121. IRQ/FIQ MMRs Bit Designations

Bit Description

0 All interrupts OR’ed

(FIQ only)

Comments

This bit is set if any FIQ is active source

2 Timer0

3 Timer1

Timer2 or wake-up timer

Timer3 or watchdog timer

Timer4

7 Reserved

General-Purpose Timer 2 or wake-up timer

General-Purpose Timer 3 or watchdog timer

General-Purpose Timer 4

Reserved

PSM

Undefined

Flash Control 0

Flash Control 1

ADC

UART

SPI

I2C 0 Master IRQ

16 I2C 0 Slave IRQ

17 I2C 1 Master IRQ

18 I2C 1 Slave IRQ I

Power Supply Monitor

This bit is not used

Flash controller for Block 0 interrupt

Flash controller for Block 1 interrupt

ADC interrupt source bit

UART interrupt source bit

SPI interrupt source bit

I 2 C master interrupt source bit

C slave interrupt source bit

C master interrupt source bit

C slave interrupt source bit

19 XIRQ0 (GPIO IRQ0 ) External Interrupt 0

20 XIRQ1 (GPIO IRQ1) External Interrupt 1

21 XIRQ2 (GPIO IRQ2 ) External Interrupt 2

22 XIRQ3 (GPIO IRQ3) External Interrupt 3

23 PWM PWM Trip interrupt source bit

24 XIRQ4 (GPIO IRQ4 ) External Interrupt 4

25 XIRQ5 (GPIO IRQ5) External Interrupt 5

26 PLA IRQ0 PLA block 0 IRQ bit

27 PLA IRQ1 PLA block 1 IRQ bit

ADuC7122

IRQ

The IRQ is the exception signal to enter the IRQ mode of the processor. It services general-purpose interrupt handling of internal and external events.

All 32 bits are logically OR’ed to create a single IRQ signal to the

ARM7TDMI core. The four 32-bit registers dedicated to IRQ follow.

IRQSIG

IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All

IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only.

IRQSIG Register

Name: IRQSIG

Address: 0xFFFF0004

Default value: 0x00000000

Preliminary Technical Data

IRQSTA

IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the

IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.

IRQSIG Register

Name: IRQSTA

Address: 0xFFFF0000

Default value: 0x00000000

IRQEN

IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt.

IRQEN Register

Name: IRQEN

Address: 0xFFFF0008

Default value: 0x00000000

Access: Read/write

IRQCLR

IRQCLR is a write-only register that allows the IRQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and

IRQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write.

IRQCLR Register

Name: IRQCLR

Address: 0xFFFF000C

Default value: 0x00000000

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FAST INTERRUPT REQUEST (FIQ)

The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The

FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.

Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers

(FIQ source).

The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN.

Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both

IRQEN and FIQEN masks.

FIQSIG

FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR.

FIQSIG is read only.

FIQSIG Register

PrA

Name: FIQSIG

Address: 0xFFFF0104

Default value: 0x00000000

Preliminary Technical Data

FIQEN

FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt.

FIQEN Register

Name: FIQEN

Address: 0xFFFF0108

Default value: 0x00000000

Access: Read/write

FIQCLR

FIQCLR is a write-only register that allows the FIQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and

FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write.

FIQCLR Register

Name: FIQCLR

Address: 0xFFFF010C

Default value: 0x00000000

ADuC7122

The 32-bit register dedicated to software interrupt is SWICFG described in Table 122. This MMR allows the control of a programmed source interrupt.

Table 122. SWICFG MMR Bit Designations

Bit Description

31 to 3 Reserved.

Programmed Interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and

FIQSIG.

Programmed Interrupt IRQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of IRQSTA and

IRQSIG.

0 Reserved.

Any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register.

PROGRAMMABLE PRIORITY

PER INTERRUPT (IRQP0/IRQP1/IRQP2)

IRQ_SOURCE

FIQ_SOURCE

INTERNAL

ARBITER

LOGIC

POINTER TO

FUNCTION

(IRQVEC)

FIQSTA

FIQSTA is a read-only register that provides the current enabled

FIQ source status (effectively a logic AND of the FIQSIG and

FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.

FIQSTA Register

Name: FIQSTA

Address: 0xFFFF0100

Default value: 0x00000000

Programmed Interrupts

Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into both

IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time.

INTERRUPT VECTOR

BITS 31-23

UNUSED

BITS 22-7

(IRQBASE)

BITS 6-2

HIGHEST

PRIORITY

ACTIVE IRQ

BITS 1-0

LSBs

Figure 36. Interrupt Structure

Vectored Interrupt Controller (VIC)

The ADUC7122 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources.

The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts:

 Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and

IRQVEC registers.

 IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, then it is possible to have 16 separate interrupt levels.

 Programmable interrupt priorities—using the IRQP0 to

IRQP2 registers, an interrupt source can be assigned an interrupt priority level value between 1 and 8.

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ADuC7122

VIC MMRs

IRQBASE Register

The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines.

Name: IRQBASE

Address: 0xFFFF0014

Default value: 0x00000000

Preliminary Technical Data

Priority Registers

IRQP0 Register

Name: IRQP0

Address: 0xFFFF0020

Default value: 0x00000000

Table 123. IRQBASE MMR Bit Designations

Bit Type Initial Description

31:16 Read only Reserved Always read as 0

15:0 R/W 0 Vector base address

IRQVEC Register

The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register.

Name: IRQVEC

Address: 0xFFFF001C

Default value: 0x00000000

Table 124. IRQVEC MMR Bit Designations

Bit Type

31:23 Read only

Initial value Description

0 Always read as 0.

6:2 Read only

0 Highest priority IRQ source. This is a value between 0 to 19 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer 1, then these bits are [01000].

1:0 Reserved bits.

Table 125. IRQP0 MMR Bit Designations

Bit Name Description

26:24 T4PI

22:20 T3PI

18:16 T2PI

A priority level of 0 to 7 can be set for

Timer 4.

A priority level of 0 to 7 can be set for

Timer 3.

A priority level of 0 to 7 can be set for

Timer 2.

14:12 T1PI A priority level of 0 to 7 can be set for

Timer 1.

10:8 T0PI A priority level of 0 to 7 can be set for

Timer 0.

6:4 SWINTP A priority level of 0 to 7 can be set for the software interrupt source.

3:0 Reserved Interrupt 0 cannot be prioritized.

IRQP1 Register

Name: IRQP1

Address: 0xFFFF0024

Default value: 0x00000000

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Preliminary Technical Data

Table 126. IRQP1 MMR Bit Designations

Bit Name Description

30:28 I2C0MPI A priority level of 0 to 7 can be set for I 2

C0 master.

26:24 SPIPI A priority level of 0 to 7 can be set for SPI.

IRQP3 Register

Name: IRQP3

Address: 0xFFFF002C

Default value: 0x00000000

ADuC7122

22:20 UARTPI A priority level of 0 to 7 can be set for UART.

18:16 ADCPI A priority level of 0 to 7 can be set for the

ADC interrupt source.

14:12 Flash1PI A priority level of 0 to 7 can be set for the

Flash Block 1 controller interrupt source.

Table 128. IRQP3 MMR Bit Designations

Bit Name Description

14:12 PLA1PI A priority level of 0 to 7 can be set for PLA0.

10:8 PLA0PI

6:4 IRQ5PI

A priority level of 0 to 7 can be set for PLA0.

A priority level of 0 to 7 can be set for IRQ5.

10:8 Flash0PI A priority level of 0 to 7 can be set for the

Flash Block 0 controller interrupt source.

2:0 PSMPI A priority level of 0 to 7 can be set for the

Power supply monitor interrupt source.

IRQP2 Register

Name: IRQP2

Address: 0xFFFF0028

Default value: 0x00000000

Table 127. . IRQP2 MMR Bit Designations

Bit Name Description

2:0 IRQ4PI A priority level of 0 to 7 can be set for IRQ4.

IRQCONN Register

The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first to enable nesting and prioritization of IRQ interrupts the other to enable nesting and prioritization of FIQ interrupts.

If these bits are cleared, then FIQs and IRQs may still be used but it is not possible to nest IRQs or FIQs. Neither is it possible to set an interrupt source priority level. In this default state, an

FIQ does have a higher priority than an IRQ.

Name: IRQCONN

Address: 0xFFFF0030

Default value: 0x00000000

30:28 PWMPI

26:24 IRQ3PI

22:20 IRQ2PI

18:16 IRQ1PI

A priority level of 0 to 7 can be set for PWM.

A priority level of 0 to 7 can be set for IRQ3.

A priority level of 0 to 7 can be set for IRQ2.

A priority level of 0 to 7 can be set for IRQ1.

14:12 IRQ0PI A priority level of 0 to 7 can be set for IRQ0.

10:8 I2C1SPI A priority level of 0 to 7 can be set for I 2 C1 slave.

A priority level of 0 to 7 can be set for I

C1 master.

2:0 I2C0SPI A priority level of 0 to 7 can be set for I

C0 slave.

Rev. PrA | Page 77 of 92

Table 129. IRQCONN MMR Bit Designations

Bit Name Description

31:2 Reserved These bits are reserved and should not be written to. interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed.

ADuC7122

IRQSTAN Register

If IRQCONN.0 is asserted and IRQVEC is read then one of these bits is asserted. The bit that asserts depend on the priority of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts, Priority 1 then Bit 1 asserts, and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked.

To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit at a time. For example, if this register is set to 0x09 then writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00.

Name: IRQSTAN

Address: 0xFFFF003C

Default value: 0x00000000

Preliminary Technical Data

FIQSTAN Register

If IRQCONN.1 is asserted and FIQVEC is read then one of these bits assert. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0 then Bit 0 asserts, Priority 1 then Bit 1 asserts, and so forth.

When a bit is set in this register all interrupts of that priority and lower are blocked.

To clear a bit in this register all bits of a higher priority must be cleared first. It is only possible to clear one bit as a time. For example if this register is set to 0x09 then writing 0xFF changes the register to 0x08 and writing 0xFF a second time changes the register to 0x00.

Name: FIQSTAN

Address: 0xFFFF013C

Default value: 0x00000000

Table 130. IRQSTAN MMR Bit Designations

Bit Name Description

31:8 Reserved These bits are reserved and should not be written to.

7:0 Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed.

FIQVEC Register

The FIQ interrupt vector register, FIQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should only be read when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register.

Name: FIQVEC

Address: 0xFFFF011C

Default value: 0x00000000

Table 131. FIQVEC MMR Bit Designations

Bit Type

Initial

Value

31:23 Read only 0

Description

Always read as 0.

22:7 R/W

6:2

0 IRQBASE register value.

0 Highest priority FIQ source. This is a value between 0 to 19 represent the possible interrupt sources. For example, if the highest currently active FIQ is Timer 1, then these bits are 01000.

1:0 Reserved bits.

Table 132. FIQSTAN MMR Bit Designations

Bit Name Description

31:8 Reserved These bits are reserved and should not be written to.

7:0 Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed.

External Interrupts (IRQ0 to IRQ3)

The ADuC7122 provides up to four external interrupt sources.

These external interrupts can be individually configured as level or rising/falling edge triggered.

To enable the external interrupt source, first of all, the appropriate bit must be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured.

To properly clear an edge based external IRQ interrupt, set the appropriate bit in the EDGELEVELCLR register.

IRQCONE Register

Name: IRQCONE

Address: 0xFFFF0034

Default value: 0x00000000

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ADuC7122

Table 133. IRQCONEMMR Bit Designations

Bit Value Name

31:12 Reserved

5:4

3:2

7:6

9:8

11:10

1:0

IRQ5SRC[1:0]

IRQ4SRC[1:0]

IRQ3SRC[1:0]

IRQ2SRC[1:0]

IRQ1SRC[1:0]

IRQ0SRC[1:0]

Preliminary Technical Data

Description

These bits are reserved and should not be written to.

External IRQ5 triggers on falling edge.

External IRQ5 triggers on rising edge.

External IRQ5 triggers on low level.

External IRQ5 triggers on high level.

External IRQ4 triggers on falling edge.

External IRQ4 triggers on rising edge.

External IRQ4 triggers on low level.

External IRQ4 triggers on high level.

External IRQ3 triggers on falling edge.

External IRQ3 triggers on rising edge.

External IRQ3 triggers on low level.

External IRQ3 triggers on high level.

External IRQ2 triggers on falling edge.

External IRQ2 triggers on rising edge.

External IRQ2 triggers on low level.

External IRQ2 triggers on high level.

External IRQ1 triggers on falling edge.

External IRQ1 triggers on rising edge.

External IRQ1 triggers on low level.

External IRQ1 triggers on high level.

External IRQ0 triggers on falling edge.

External IRQ0 triggers on rising edge.

External IRQ0 triggers on low level.

External IRQ0 triggers on high level.

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ADuC7122

IRQCLRE Register

Name: IRQCLRE

Address: 0xFFFF0038

Default value: 0x00000000

Table 134. IRQCLRE MMR Bit Designations

Bit Name Description

31:20 Reserved These bits are reserved and should not be written to. interrupt service routine to clear an edge triggered IRQ3 interrupt. interrupt service routine to clear an edge triggered IRQ2 interrupt.

17:15 Reserved These bits are reserved and should not be written to. interrupt service routine to clear an edge triggered IRQ1 interrupt. interrupt service routine to clear an edge triggered IRQ0 interrupt. written to.

TIMERS

The ADuC7122 has five general purpose timers/counters.

 Timer0

 Timer1

 Timer2 or wake-up timer

 Timer3 or watchdog timer

 Timer4

The five timers in their normal mode of operation can be either free-running or periodic.

In free-running mode, the counter decrements/increments from the maximum/minimum value until zero scale/full scale and starts again at the maximum /minimum value.

In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero scale/full scale and starts again at the value stored in the load register.

The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON).

In normal mode, an IRQ is generated each time the value of the counter reaches zero if counting down, or full scale if counting up. An IRQ can be cleared by writing any value to clear register of the particular timer (TxICLR).

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Preliminary Technical Data

Table 135. Event Selection Numbers

00000 2

00001 3

00010

00011

00100 6

00101 7

00110 8

00111 9

01000 10

01001 11

01010 12

01011 13

01100 14

01101 15

01110 16

01111 17

10000 18

10001 19

RTOS timer (Timer0)

Wake-up timer (Timer2)

Watchdog timer (Timer3)

Reserved

Undefined

Flash Block 0

Flash Block 1

ADC

UART

SPI

TIMER0—LIFETIME TIMER

Timer0 is a general-purpose, 48-bit count up, or a 16-bit count up/down timer with a programmable prescaler. Timer0 is clocked from the core clock, with a prescaler of 1, 16, 256, or

32768. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Timer 0 can also be clocked from the undivided core clock, internal 32kHz oscillator or external 32kHz crystal.

In 48-bit mode, Timer0 counts up from zero. The current counter value can be read from T0VAL0 and T0VAL1.

In 16-bit mode, Timer0 can count up or count down. A 16-bit value can be written to T0LD that is loaded into the counter. The current counter value can be read from T0VAL0. Timer 0 has a capture register (T0CAP) that can be triggered by a selected IRQ’s source initial assertion. Once triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone.

Timer0 reloads the value from T0LD either when TIMER0 overflows or immediately when T0CLRI is written.

Preliminary Technical Data

Timer0 interface consists of six MMRs, shown in Table 136.

Table 136. Timer0 Interface MMRs

Name Description

T0LD

T0CAP

16-bit register that holds the 16-bit value loaded into the counter. Available only in

16-bit mode.

16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode

T0VAL0/T0VAL1 TOVAL0 is a 16 bit register that holds the 16 least significant bits (LSBs).

T0VAL1 is a 32-bit register that holds the 32 most significant bits (MSBs).

T0CLRI 8-bit register. Writing any value to this register clears the interrupt. Available only in 16-bit mode.

Table 137. Timer0 Value Register

Name Address

T0VAL0/T0VAL1 0xFFFF0304,

0xFFFF0308

Default Value

0x00, 0x00

Access

T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold the 16 least significant bits and 32 most significant bits, respectively. T0VAL0 and T0VAL1 are read-only. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit

T0VAL0 and 32-bit T0VAL1 are used.

Timer0 Capture Register

Name Address Default Value Access

T0CAP 0xFFFF0314 R

This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event; only available in 16-bit mode.

ADuC7122

Table 138. Timer0 Control Register

Name Address Default Value Access

T0CON 0xFFFF030C R/W

The 17-bit MMR configures the mode of operation of Timer0.

Table 139. T0CON MMR Bit Designations

31:18

16:12

Reserved.

Event select bit.

Set by user to enable time capture of an event.

Cleared by user to disable time capture of an event.

Event select range, 0 to 16. The events are as described in the introduction to the timers.

11 Reserved.

10:9

00 Internal 32 kHz oscillator.

01 UCLK.

10 External 32kHz crystal.

11 HCLK.

8 Count up. Available only in 16-bit mode.

Set by user for timer 0 to count up.

Cleared by user for timer 0 to count down

(default).

Timer0 enable bit.

Set by user to enable Timer0.

Cleared by user to disable Timer0 (default).

Timer0 mode.

Set by user to operate in periodic mode.

Cleared by user to operate in free-running mode (default).

5 Reserved.

4 Timer0 mode of operation.

0 16-bit operation (default).

3:0

0000

Prescaler.

Source clock/1 (default).

Timer0 Load Registers

Name Address Default Value Access

T0LD is a 16-bit register that holds the 16-bit value that is loaded into the counter; available only in 16-bit mode.

Timer0 Clear Register

Name Address Default Value Access

T0CLRI 0xFFFF0310 W

This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer0.

Rev. PrA | Page 81 of 92

ADuC7122

TIMER1—GENERAL-PURPOSE TIMER

Timer1 is a 32-bit general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be from the 32 kHz internal oscillator, the 32kHz external crystal, the core clock, or from the undivided PLL clock output. This source can be scaled by a factor of 1, 16, 256, or 32768. This gives a minimum resolution of 42 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescaler of 1.

The counter can be formatted as a standard 32-bit value or as

Hours:Minutes:Seconds:Hundredths.

Timer1 has a capture register (T1CAP) that can be triggered by a selected IRQ’s source initial assertion. Once triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy.

Timer1 interface consists of five MMRs as shown in the table below.

Table 140. Timer1 Interface Registers

Register Description

T1LD 32-bit register. Holds 32-bit unsigned integers.

This register is read only.

T1VAL

T1CAP

32-bit register. Holds 32-bit unsigned integers.

32-bit register; Holds 32-bit unsigned integers.

This register is read only.

T1ICLR 8-bit register. Writing any value to this register clears the Timer1 interrupt.

Note that if the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source, then

Timer1 continues to operate.

Preliminary Technical Data

Timer1 reloads the value from T1LD either when Timer1 overflows or immediately when T1ICLR is written.

Table 141. Timer1 Load Registers

Name Address Default Value Access

T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter.

Table 142. Timer1 Clear Register

Name Address Default Value Access

T1ICLR 0xFFFF032C W

This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer1.

Table 143. Timer1 Value Register

Name Address Default Value Access

T1VAL is a 32-bit register that holds the current value of

Timer1.

Table 144. Timer1 Capture Register

Name Address Default Value Access

T1CAP 0xFFFF0330 R

This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event.

Table 145. Timer1 Control Register.

Name Address Default Value Access

This 32-bit MMR configures the mode of operation of Timer1.

Rev. PrA | Page 82 of 92

Preliminary Technical Data

Table 146. T1CON MMR Bit Designations

31:24

22:20

Enable write to postscaler.

Reserved.

Postscaler compare flag.

T1 interrupt generation selection flag.

Event select bit.

Set by user to enable time capture of an event.

Cleared by user to disable time capture of an event.

Event select range, 0 to 16. The events are as described in the introduction to the timers. 16:12

11:9

000 Internal 32 kHz oscillator (default).

010 UCLK.

011 P0.6.

8 Count

Set by user for Timer1 to count up.

Cleared by user for Timer1 to count down (default).

7 Timer1 enable bit.

Set by user to enable Timer1.

Cleared by user to disable Timer1 (default).

6 Timer1 mode.

Set by user to operate in periodic mode.

Cleared by user to operate in free-running mode (default).

5:4 Format.

01 Reserved.

10 Hr:Min:Sec:Hundredths: 23 hours to 0 hours.

11 Hr:Min:Sec:Hundredths: 255 hours to 0 hours.

3:0 Prescaler.

0000 Source clock/1 (default).

ADuC7122

Rev. PrA | Page 83 of 92

ADuC7122

TIMER2—WAKE-UP TIMER

Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from 1 of 4 clock sources, namely, the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the PLL undivided clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via

IRQEN[4].

The counter can be formatted as plain 32-bit value or as

Hours:Minutes:Seconds:Hundredths.

Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2ICLR is written.

The Timer2 interface consists of four MMRs, shown in the table below.

Table 147. Timer2 Interface Registers

Register Description

T2LD 32-bit register. Holds 32-bit unsigned integers.

T2VAL

T2ICLR

32-bit register. Holds 32-bit unsigned integers. This register is read only.

8-bit register. Writing any value to this register clears the Timer2 interrupt.

Preliminary Technical Data

Table 148. Timer2 Load Registers

Name Address Default Value Access

T2LD is a 32-bit register, which holds the 32 bit value that is loaded into the counter.

Table 149. Timer2 Clear Register

Name Address Default Value Access

T2CLRI 0xFFFF034C W

This 8-bit write-only MMR is written (with any value) by user code to refresh (reload) Timer2.

Table 150. Timer2 Value Register

Name Address Default Value Access

T2VAL is a 32-bit register that holds the current value of

Timer2.

Table 151. Timer2 Control Register

Name Address Default Value Access

This 32-bit MMR configures the mode of operation for Timer2.

Rev. PrA | Page 84 of 92

Preliminary Technical Data

Table 152. T2CON MMR Bit Designations

31:11

10:9

Reserved.

Internal 32.768 kHz oscillator (default).

10 External 32.768 kHz watch crystal.

11 UCLK.

Count up.

Set by user for Timer2 to count up.

Cleared by user for Timer2 to count down (default).

Timer2 enable bit.

Set by user to enable Timer2.

Cleared by user to disable Timer2 (default).

6 Timer2 mode.

Set by user to operate in periodic mode.

Cleared by user to operate in free-running mode (default).

5:4 Format.

01 Reserved.

10 Hr:Min:Sec:Hundredths. 23 hours to 0 hours.

11 Hr:Min:Sec:Hundredths. 255 hours to 0 hours.

3:0 Prescaler.

0000 Source clock/1 (default).

1000 Source clock/256. (This setting should be used in conjunction with Timer2 Format 10 and Format 11.)

ADuC7122

Rev. PrA | Page 85 of 92

ADuC7122

TIMER3—WATCHDOG TIMER

16-BIT LOAD

LOW POWER

32.768kHz

PRESCALER

1, 16, OR 256

16-BIT

UP/DOWN

COUNTER

WATCHDOG

RESET

TIMER3IRQ

TIMER3 VALUE

Figure 37. Timer3 Block Diagram

Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a reset of the processor.

Timer3 reloads the value from T3LD either when Timer3 overflows or immediately when T3ICLR is written.

Normal Mode

The Timer3 in normal mode is identical to Timer0 in 16-bit mode of operation, except for the clock source. The clock source is the 32.768 kHz oscillator and can be scaled by a factor of 1,

16, or 256. Timer3 also features a capture facility that allows capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5].

Watchdog Mode

Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in the T3LD register until

0. The maximum timeout is 512 seconds, using the maximum prescalar/256 and full scale in T3LD.

User software should only configure a minimum timeout period of 30 milliseconds. This is to avoid any conflict with

Flash/EE memory page erase cycles, requiring 20 ms to complete a single page erase cycle and kernel execution.

If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period.

Once watchdog mode is entered, T3LD and T3CON are write protected. These two registers cannot be modified until a power-on reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. The watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets.

Preliminary Technical Data

Timer3 is automatically halted during JTAG debug access and only recommences counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This can be disabled by setting Bit 0 in T3CON. It is recommended that the default value is used, that is, the watchdog timer continues to count during power-down.

Timer3 Interface

Timer3 interface consists of four MMRS as shown in the table below.

Table 153. Timer3 Interface Registers

Register Description

T3CON The configuration MMR.

T3LD 6-bit registers (Bit 0 to Bit15); holds 16-bit unsigned integers.

T3VAL 6-bit registers (Bit 0 to Bit 15); holds 16-bit unsigned integers. This register is read only.

T3ICLR 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode.

Table 154. Timer3 Load Register

Name Address Default Value Access

This 16-bit MMR holds the Timer3 reload value.

Table 155. Timer3 Value Register

Name Address Default Value Access

This 16-bit, read-only MMR holds the currentTimer3 count value.

Table 156. Timer3 Clear Register

Name Address Default Value Access

T3CLRI 0xFFFF036C W

This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload), Timer3 in watchdog mode to prevent a watchdog timer reset event.

Table 157. Timer3 Control Register

Name Address Default Value Access

T3CON 0xFFFF0368

R/W once only

The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 158.

Rev. PrA | Page 86 of 92

Preliminary Technical Data ADuC7122

Table 158. T3CON MMR Bit Designations

Bit Value Description

16:9 These bits are reserved and should be written as 0s by user code.

Count up/down enable.

Set by user code to configure Timer3 to count up.

Cleared by user code to configure Timer3 to count down.

Timer3 enable.

Set by user code to enable Timer3.

Cleared by user code to disable Timer3.

Timer3 operating mode.

Set by user code to configure Timer3 to operate in periodic mode.

Cleared by user to configure Timer3 to operate in free-running mode.

Watchdog timer mode enable.

Set by user code to enable watchdog mode.

Cleared by user code to disable watchdog mode.

3:2

Secure clear bit.

Set by user to use the secure clear option.

Cleared by user to disable the secure clear option by default.

Timer3 clock(32.768 kHz) prescaler.

Source clock/1 (default).

01 Reserved.

10 Reserved.

11 Reserved.

1 Watchdog timer IRQ enable.

Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.

Cleared by user code to disable the IRQ option.

0 PD_OFF.

Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.

Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.

Secure Clear Bit (Watchdog Mode Only)

The secure clear bit is provided for a higher level of protection.

When set, a specific sequential value must be written to T3ICLR to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8

+ X6 + X5 + X + 1.

CLOCK

D Q

Figure 38. 8-Bit LFSR

The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to

T3ICLR must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens.

If it fails to match the expected state, reset is immediately generated, even if the count has not yet expired.

The value 0×00 should not be used as an initial seed due to the properties of the polynomial. The value 0×00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software.

Example of a sequence:

1. Enter initial seed, 0×AA, in T3ICLR before starting Timer3 in watchdog mode.

2. Enter 0×AA in T3ICLR; Timer3 is reloaded.

3. Enter 0×37 in T3ICLR; Timer3 is reloaded.

4. Enter 0×6E in T3ICLR; Timer3 is reloaded.

5. Enter 0×66. 0×DC was expected; the watchdog resets the chip.

Rev. PrA | Page 87 of 92

ADuC7122

TIMER4—GENERAL-PURPOSE TIMER

Timer4 is a 32-bit general-purpose timer, count down or count up, with a programmable prescalar. The prescalar source can be the 32kHz oscillator, the core clock or PLL undivided output. This source can be scaled by a factor of 1, 16, 256, or 32768. This gives a minimum resolution of 42 ns when operating at

CD zero, the core is operating at 41.78 MHz, and with a prescalar of 1 ( ignoring external GPIO).

The counter can be formatted as a standard 32-bit value or as

Hours:Minutes:Seconds:Hundreths.

Timer4 has a capture register (T4CAP), which can be triggered by a selected IRQ’s source initial assertion. Once triggered, the current timer value is copied to T4CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy.

Timer4 interface consists of five MMRS.



T4LD, T4VAL and T4CAP are 32-bit registers and hold

32-bit unsigned integers. T4VAL and T4CAP are read only.



T4ICLR is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.



T4CON is the configuration MMR.

Note that if the part is in a low power mode, and Timer 4 is clocked from the GPIO or oscillator source then, Timer 4 continues to operate.

Timer4 reloads the value from T4LD either when Timer 4 overflows, or immediately when T4ICLR is written.

Preliminary Technical Data

Table 159. Timer4 Load Registers

Name Address Default Value Access

T4LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter.

Table 160. Timer4 Clear Register

Name Address Default Value Access

T4CLRI 0xFFFF038C W

This 8-bit, write only MMR is written (with any value) by user code to refresh (reload) Timer4.

Table 161. Timer4Value Register

Name Address Default Value Access

T4VAL is a 32-bit register that holds the current value of Timer4.

Table 162. Timer4 Capture Register

Name Address Default Value Access

T4CAP 0xFFFF0390 R

This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event.

Table 163. Timer4 Control Register

Name Address Default Value Access

This 32-bit MMR configures the mode of operation of Timer4.

Rev. PrA | Page 88 of 92

Preliminary Technical Data

Table 164. T4CON MMR Bit Designations

Bit

31:18

Value Description

Reserved. Set by user to 0.

17 Event select bit.

Set by user to enable time capture of an event.

Cleared by user to disable time capture of an event.

Event Select Range, 0 to 31. The events are as described in the introduction to the timers. 16:12

11:9

000 32.768 kHz oscillator.

010 UCLK.

011 UCLK.

Set by user for Timer4 to count up.

Cleared by user for Timer4 to count down (default).

Timer4 enable bit.

Set by user to enable Timer4.

Cleared by user to disable Timer4 (default).

6 Timer4 mode.

Set by user to operate in periodic mode.

Cleared by user to operate in free-running mode (default).

5:4 Format.

01 Reserved.

10 Hr:Min:Sec:Hundredths: 23 hours to 0 hours.

11 Hr:Min:Sec:Hundredths: 255 hours to 0 hours.

3:0 Prescaler.

0000 Source clock/1 (default).

ADuC7122

Rev. PrA | Page 89 of 92

ADuC7122

OUTLINE DIMENSIONS

Preliminary Technical Data

BALL A1

PAD CORNER

*1.40 MAX

ORDERING GUIDE

−10°C to +95°C ADuC7122

7.10

7.00 SQ

6.90

5.50

BSC SQ

0.50

BSC

A1 BALL

CORNER

8 7 6

5 4 3 2 1

BOTTOM VIEW

TOP VIEW

DETAIL A

*1.11 MAX

DETAIL A

0.15 MIN

0.35

0.30

0.25

BALL DIAMETER

SEATING

PLANE

COPLANARITY

0.08

*COMPLIANT WITH JEDEC STANDARDS MO-195-BD WITH

EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.

Figure 39. 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-108-4

Dimensions shown in millimiters

108-Ball BGA package

Rev. PrA | Page 90 of 92

Preliminary Technical Data

NOTES

ADuC7122

Rev. PrA | Page 91 of 92

ADuC7122 Preliminary Technical Data

NOTES

C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

PR08755-0-1/10(PrA)

Rev. PrA | Page 92 of 92

வணக்கம்! Analog Devices ADuC7122 Precision Analog Microcontroller Preliminary Technical Data உடன் உங்களுக்கு உதவ சிறப்பாகப் பயிற்றுவிக்கப்பட்ட AI சாட்போட் நான். நான் ஆவணத்தை முழுமையாக மதிப்பாய்வு செய்துள்ளேன், மேலும் உங்களுக்குத் தேவையான சரியான தகவலைக் கண்டறிய அல்லது உள்ளடக்கத்தை தெளிவான மற்றும் எளிமையான சொற்களில் விளக்க உதவ முடியும். குறிப்பிட்ட அம்சங்கள், சரிசெய்தல் படிகள் அல்லது பொதுவான பயன்பாடு குறித்த வழிகாட்டுதலை நீங்கள் தேடுகிறீர்களானால், உங்கள் கேள்விகளைக் கேட்க தயங்கவும். உங்கள் கவலைகள் அல்லது தேவைகள் பற்றி நீங்கள் எவ்வளவு அதிகமாக விவரங்களை வழங்குகிறீர்களோ, அவ்வளவு துல்லியமாகவும் эффективноவும் நான் உங்களுக்கு உதவ முடியும்!

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