Analog Devices ADuC842/843 MicroConverter Quick Reference Guide

Instruction Set

Data Transfer Operations

MOV A,Rn

MOV A,@Ri

MOV A,direct

MOV A,#data

MOV Rn,A

MOV Rn,direct

MOV Rn,#data

MOV direct,A

MOV direct,Rn move

MOV direct,@Ri

MOV direct,direct

MOV direct,#data

MOV @Ri,A

MOV @Ri,direct

MOV @Ri,#data

MOV DPTR,#data16

MOVC A,@A+DPTR move from

MOVC A,@A+PC

MOVX A,@Ri

MOVX A,@DPTR

MOVX @Ri,A

MOVX @DPTR,A

PUSH direct

POP direct

XCH A,Rn

XCH A,@Ri

XCH A,direct

XCHD A,@Ri code memory move to/from data memory

1 push onto stack 2 pop from stack

3

1

2

2

3

1

2

3

2

1

1

1

1

1 exchange bytes 1

2 exchg low digits 1

1

2

2

2

2

2

1

1

2

Boolean Variable Manipulation

CLR C

CLR bit

MOV C,bit

MOV bit,C clear bit to zero

SETB C

SETB bit

CPL C

CPL bit set bit to one complement bit

ANL C,bit AND bit with C 2

ANL C,/bit AND (NOTbit) with C 2

ORL C,bit OR bit with C

ORL C,/bit OR (NOTbit) with C

2

2

1

2

1

2 move bit to bit

1

2

2

2

Program Branching

ACALL addr11

LCALL addr16

RET

RETI

AJMP addr11

LJMP addr16

SJMP rel

JMP @A+DPTR

JC rel

JNC rel

JB bit,rel

JNB bit,rel

JBC bit,rel

JZ rel

JNZ rel

CJNE A,direct,rel

CJNE A,#data,rel

CJNE Rn,#data,rel

CJNE @Ri,#data,rel

DJNZ Rn,rel

DJNZ direct, rel

NOP call subroutine return from sub. 1 return from int.

1

2

3 jump jump if C set 2 jmp if C not set 2 jump if bit set 3 jmp if bit not set 3

2

1

2

3 jmp&clear if set 3 jump if A = 0 2 jump if A not 0 2 compare and jump if not equal

3

3

3

3 decrement and 2 jump if not zero 3 no operation 1

2

2

2

2

1

2

1

2

1

2

2

2

2

1

4

2

4

4

4

4

2

2

2

3

4

2

2

3

2

2

3

1

2

2

2

2

2

1

2

2

4

3

4

4

3

4

4

3

4

1

4

4

3

3

3

3

3

4

4

4

3

4

Instructions That Affect Flags

ADD A,x C = carry out of bit 7

AC = carry out of bit 3

OV = carry out of bit 6, but not 7

ADDC A,x C = carry out of bit 7

AC = carry out of bit 3

OV = carry out of bit 6, but not 7

SUBB A,x C = borrow into bit 7

AC = borrow into bit 3

OV = borrow into bit 6, but not 7

MUL AB C = 0

DIV AB

OV = (result>255)

C = 0

OV = divide by zero

Arithmetic Operations

ADD A,Rn

ADD A,@Ri

ADD A,direct

ADD A,#data

ADDC A,Rn

ADDC A,@Ri

ADDC A,direct

ADDC A,#data

SUBB A,Rn

SUBB A,@Ri

SUBB A,direct

SUBB A,#data

INC

INC

INC

INC

INC

A

Rn

@Ri direct

DPTR *

DEC A

DEC Rn

DEC @Ri

DEC direct

MUL AB

DIV

DA

AB

A add source to A add with carry subtract from A 1 with borrow 2

2 increment 1

2

1

1

1 decrement multiply A by B 1 divide A by B decimal adjust

1

1

1

2

1

1

1

2

1

1

2

2

1

1

2

*

INC DPTR increments the 24bit value DPP/DPH/DPL

Logical Operations

ANL A,Rn

ANL A,@Ri

ANL A,direct

ANL A,#data

ANL direct,A

ANL direct,#data

ORL A,Rn

ORL A,@Ri

ORL A,direct

ORL A,#data

ORL direct,A

ORL direct,#data

XRL A,Rn

XRL A,@Ri

XRL A,direct

XRL A,#data

XRL direct,A

XRL direct,#data

CLR A

CPL A

RL A

RLC A

RR A

RRC A

SWAP A logical AND logical OR logical XOR clear A to zero complement A rotate A left

...through C rotate A right

...through C swap nibbles

1

1

3

1

2

2

1

2

1

1

1

1

3

1

2

2

1

2

3

1

2

2

1

1

2

9

9

2

2

2

1

1

2

3

1

2

2

1

2

2

1

2

1

2

2

2

1

2

2

1

1

3

1

2

2

2

2

1

1

1

1

3

1

2

2

2

2

3

1

2

2

1

2

2

Legend

Rn

@Ri direct

#data register addressing using R0-R7 indirect addressing using R0 or R1

8bit internal address (00h-FFh)

8bit constant included in instruction

#data16 16bit constant included in instruction bit rel

8bit direct address of bit signed 8bit offset addr11 11bit address in current 2K page addr16 16bit address x any of: Rn, @Ri, direct, #data

DA A

RRC A

RLC A

SETB C

CLR C

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

C = C or (x>100)

C = ACC.7

C = ACC.0

C = 1

C = 0

C = C and bit

C = C and NOTbit

C = C or bit

C = C or NOTbit

C = bit

CJNE x,y,rel C = (x<y)

Pin Functions

2

3

MQFP CSP

1 56 P1.0 / ADC0 / T2

1

2

P1.1 / ADC1 / T2EX

P1.2 / ADC2

4 3 P1.3 / ADC3

5 4,5 AV

DD

6 6,7,8 AGND

7 9 C

REF

8 10 V

REF

9 11 DAC0

10 12 DAC1

11 13 P1.4 / ADC4

12 14 P1.5 / ADC5 / SS

13 15 P1.6 / ADC6

14 16 P1.7 / ADC7

15 17 RESET

16 18 P3.0 / RxD

17 19 P3.1 / TxD

18 20 P3.2 / INT0

19 21 P3.3/INT1/MISO/PWM1

20 22 DV

DD

21 23 DGND

22 24

23 25 P3.5 / T1 / CONVST

24 26 P3.6 / WR

25 27 P3.7 / RD

26 28 SCLOCK

1

2

3

4

5

6

7

8

9

10

11

12

13

14 pin 1 identifier

ADuC842

56pin CSP

TOP VIEW

(not to scale)

6

7

8

9

10

11

12

13

1

2

3

4

5

33

32

31

30

29

37

36

35

34

42

41

40

39

38

MQFP CSP

27 29 SDATA / MOSI

28 30 P2.0 / A8 / A16

29 31 P2.1 / A9 / A17

30 32 P2.2 / A10 / A18

31 33 P2.3 / A11 / A19

32 34 XTAL1 (in)

33 35 XTAL2 (out)

34 36 DV

DD

35 37,38 DGND

36 39 P2.4 / A12 / A20

37 40 P2.5 / A13 / A21

38 41 P2.6/A14/A22/PWM0

39 42 P2.7/A15/A23/PWM1

Code Memory Space Options

62

FFFFh

F800h

F7FFh

(NOP instructions)

FFFFh

32

(NOP instructions)

8000h

7FFFh internal code space

62K bytes

Flash/EE internal code space

32K bytes

Flash/EE

0000h 0000h pin 1 identifier

ADuC842

52pin MQFP

TOP VIEW

(not to scale)

MQFP CSP

40 43 EA

41 44 PSEN

42 45 ALE

43 46 P0.0 / AD0

44 47 P0.1 / AD1

45 48 P0.2 / AD2

46 49 P0.3 / AD3

47 50 DGND

48 51 DV

DD

49 52 P0.4 / AD4

50 53 P0.5 / AD5

51 54 P0.6 / AD6

52 55 P0.7 / AD7

FFFFh

8

(NOP instructions)

2000h

1FFFh

0000h internal code space

8K bytes

Flash/EE

35

34

33

32

39

38

37

36

31

30

29

28

27

Interrupt Vector Addresses

Interrupt Bit Interrupt Name

PSMCON.5

Power Supply Monitor Interrupt

WDS

IE0

ADCI

TF0

IE1

TF1

ISPI/I2CI

RI/TI

TF2/EXF2

WatchDog Timer Interrupt

External Interrupt 0

End of ADC Conversion Interrupt

Timer0 Overflow Interrupt

External Interrupt 1

Timer1 Overflow Interrupt

SPI/I

2

C Interrupt

UART Interrupt

Timer2 Interrupt

TIMECON.2

Time Interval Counter Interrupt

© 2003 Analog Devices, Inc. All rights reserved.

Trademarks and registered trademarks are the property of their respective companies.

Purchase of licensed I 2 C components of Analog

Devices or one of its sublicensed Associated

Companies conveys a license for the purchaser under the Philips I 2 components in an I

C Patent Rights to use these

C system, provided that the system conforms to the I as defined by Philips.

Printed in the U.S.A.

2 C Standard Specification

G03602-4-12/03(0)

Vector

Address

43h

5Bh

03h

33h

0Bh

13h

1Bh

3Bh

23h

2Bh

53h

Relative

Priority

7

8

5

6

3

4

1

2

9

10

11

REV. 0

ADuC842/843 MicroConverter

Quick Reference Guide

FUNCTIONAL

BLOCK

DIAGRAM

® hardware

CONVST 23

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

11

12

13

14

3

4

1

2

V

REF

8

C

REF

7

AIN

MUX

T/H

TEMP sensor

(-3 mV/ o C)

2.5V

bandgap reference

BUF

POR

ADuC842/ADuC843

DACs on ADuC842 only

DAC0

12bit ADC

ADC control

& calibration

DAC control

DAC1

BUF

BUF

4K x 8 data

Flash/EE

62K x 8 program

Flash/EE baudrate timer downloader debugger asynchronous serial port

( UART )

1-clock

8052

MCU core single-pin emulator

PWM

2K x 8 user “XRAM”

256 x 8 user RAM watchdog timer power supply monitor

16bit counter timers serial interfaces

( synchronous

SPI & I 2 C ) time interval counter

OSC &

PLL

20 34 35 47

9 DAC0

10 DAC1

38 PWM0

39 PWM1

22

23

1

2

T0

T1

T2

T2EX

18

19

INT0

INT1

* pin numbers refer to MQFP package

A Precision Analog Flash MCU

The ADuC842/ADuC843 is:

ADC:

12bit, 5µs, 8channel, self calibrating

0.5LSB INL & 70dB SNR

DAC

(ADuC842 only)

:

dual, 12bit, 15µs, voltage output

<1LSB DNL

Flash/EEPROM:

62K bytes Flash/EE program memory

4K bytes Flash/EE data memory

Microcontroller:

“single-cycle” 8052, up to 16.8MIPS

32 I/O lines, programmable PLL clock

(131KHz to 16.8MHz from 32KHz crystal)

Other on-chip features:

temperature monitor, power supply monitor, watchdog timer, flexible serial interface ports, voltage reference, time interval counter, dual 8/16bit PWM, power-on-reset

Data Memory: RAM, SFRs, user Flash/EE (all read/write)

SFR Map

Lower RAM

7

6

9

8

13

12

11

10

17

16

15

14

21

20

19

18

3

2

5

4

1

0

25

24

23

22

29

28

27

26

33

32

31

30

37

36

35

34

41

40

39

38

45

44

43

42 decimal address

127

...

48

47

46

09h

08h

07h

06h

0Dh

0Ch

0Bh

0Ah

11h

10h

0Fh

0Eh

15h

14h

13h

12h

05h

04h

03h

02h

01h

00h

19h

18h

17h

16h

1Dh

1Ch

1Bh

1Ah

21h

20h

1Fh

1Eh

25h

24h

23h

22h

29h

28h

27h

26h

2Dh

2Ch

2Bh

2Ah

HEX address

7Fh

...

30h

2Fh

2Eh

General Purpose

Area

Bit Addressable

R3

R2

R1

R0

R7

R6

R5

R4

R3

R2

R1

R0

R7

R6

R5

R4

R3

R2

R1

R0

R7

R6

R5

R4

R3

R2

R1

R0

R7

R6

R5

R4

Area

1Eh

16h

0Eh

06h

3Eh

36h

2Eh

26h

5Eh

56h

4Eh

46h

7Eh

76h

6Eh

66h

1Fh

17h

0Fh

07h

3Fh

37h

2Fh

27h

5Fh

57h

4Fh

47h

7Fh

77h

6Fh

67h

Flash/EE

4K bytes data

Flash/EE through

SFRs)

000h ( page 0 )

1Dh

15h

0Dh

05h

3Dh

35h

2Dh

25h

5Dh

55h

4Dh

45h

7Dh

75h

6Dh

65h

(bit addresses)

1Ch

14h

0Ch

04h

3Ch

34h

2Ch

24h

5Ch

54h

4Ch

44h

7Ch

74h

6Ch

64h

1Bh

13h

0Bh

03h

3Bh

33h

2Bh

23h

5Bh

53h

4Bh

43h

7Bh

73h

6Bh

63h

1Ah

12h

0Ah

02h

3Ah

32h

2Ah

22g

5Ah

52h

4Ah

42h

7Ah

72h

6Ah

62h data space

3FFh ( page 1023 )

(1K pages)

(accessible

RAM & SFRs

7FFh

19h

11g

09h

01h

39h

31h

29h

21h

59h

51h

49h

41h

79h

71h

69h

61h

“XRAM”

18h

10h

08h

00h

38h

30h

28h

20h

58h

50h

48h

40h

78h

70h

68h

60h extended RAM space

FFFFFFh

FFh

00h

128 bytes upper RAM

(indirect addressing only)

128 bytes lower RAM

(direct or indirect addressing)

SFRs

(direct addressing only)

000h

CFG842.0=1 internal data memory

2K bytes

CFG842.0=0 external data memory

(16M bytes addressable) lower RAM details

SFR details these bits are contained in this byte mnemonic address reset value

SPR1

F9h 0

SPR0

F8h 0

SPICON

F8h 04h

* calibration coefficients are preconfigured at power-up to factory calibrated values mnemonic reset value address

ADCCON1

ADCCON1.7

ADCCON1.6

ADCCON1.5

ADCCON1.4

ADCCON1.3

ADCCON1.2

ADCCON1.1

ADCCON1.0

ADCCON2

ADC Control register #1

ADC mode (0=off, 1=on) external Vref select bit (0=on-chip Vref) conversion time = 16 / ADCclk

ADCclk = 16,777,216Hz / [32,4,8,2] acquisition time select bits

acq time = [1,2,3,4] / ADCclk

Timer2 convert enable external CONVST enable

ADC Control register #2

ADCI

DMA

CCONV

SCONV

CS3

CS2

CS1

CS0

ADC interrupt flag

DMA mode enable continuous conversion enable bit single conversion start bit input channel select bits:

0 - 7 = ADC0 - ADC7

8 = temperature sensor

9=DAC0, A=DAC1, B=AGND, C=VREF

ADCCON3

ADCCON3.7

ADCCON3.6

ADCCON3.5

ADCCON3.4

ADCCON3.3

ADCCON3.2

ADCCON3.1

ADCCON3.0

ADCDATAH

ADC Control register #3 busy indicator flag (0=ADC not active)

(this bit must contain zero) number of averages selection bits:

[15,1,31,63]

(this bit must contain zero)

(this bit must contain one when calibrating) cal type select (0=offset, 1=gain) start calibration bit, cleared by hardware

ADCDATAL

ADC Data registers

DMAP , DMAH , DMAL DMA address pointer

ADCGAINH

ADCGAINL

ADCOFSH

ADCOFSL

ADC Gain calibration coefficients

ADC Offset calibration coefficients

DACCON

DACCON.7

DACCON.6

DACCON.5

DACCON.4

DACCON.3

DACCON.2

DACCON.1

DACCON.0

DAC1H ,

DAC Control register

ModeSelect (0=12bit, 1=8bit)

DAC1 RangeSelect (0=V

REF

DAC0 RangeSelect (0=V REF

, 1=V

, 1=V

DD

DD

)

)

Clear DAC1 (0=0V, 1=normal operation)

Clear DAC0 (0=0V, 1=normal operation)

SynchronousUpdate (1=asynchronous)

PowerDown DAC1 (0=off, 1=on)

PowerDown DAC0 (0=off, 1=on)

DAC1L

DAC1 data registers

DAC0H , DAC0L DAC0 data registers

PLLCON

PLLCON.7

PLLCON.6

PLLCON.5

PLLCON.4

PLLCON.3

PLLCON.2

PLLCON.1

PLLCON.0

TIMECON

PLL Control register oscillator powerdown control bit (0=XTAL on)

PLL lock indicator flag (0=out of lock)

(this bit must contain zero)

(this bit must contain zero)

“fast interrupt” control bit (0=normal)

3-bit clock divider value, “CD” (default=3):

F

CORE

= 16,777,216Hz / 2 CD

Time Interval Counter Control Register

TIMECON.6 24-hour mode select (0=0..255hour, 1=0..23hour)

TIMECON.5 INTVAL timebase select bits

TIMECON.4 [128th sec, seconds, minutes, hours]

TIMECON.3 single time interval control bit (0=reload&restart)

TIMECON.2 time interval interrupt bit, “TII”

TIMECON.1 time interval enable bit (0=disable&clear)

TIMECON.0 time clock enable bit (0=disable)

INTVAL

HTHSEC

SEC

MIN

HOUR

TIC Interval Register

TIC Elapsed 128th Second Register

TIC Elapsed Seconds Register

TIC Elapsed Minutes Register

TIC Elapsed Hours Register

ECON Data Flash/EE comand register

EADRH

01h READ page

02h PROGRAM page

04h VERIFY page

05h ERASE page

06h ERASE ALL

, EADRL

82h PROGRAM byte

0Fh EXIT ULOAD mode

F0h ENTER ULOAD mode

(all others reserved)

Data Flash/EE address registers

EDATA1 , EDATA2 , EDATA3 , EDATA4

Data Flash/EE data registers

SPICON

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

SPR1

SPR0

SPIDAT

SPI Control register

SPI interrupt (set by hardware at end of SPI transfer) write collision error flag

SPI enable (0=I 2 C enable, 1=SPI enable) master mode select (0=slave) clock polarity select (0=SCLK idles low) clock phase select (0=leading edge latch)

SPI bitrate select bits

bitrate = F

CORE

/ [2,4,8,16] (slave: SPR0=SS)

SPI Data register

I2CCON

I2CSI

I2CGC

I2CID1

I2CID0

I2CM

I2CRS

I2CTX

I2CI

I2CCON

I 2 C Control register (in slave mode) slave mode stop interrupt enable bit (0=disable) slave mode general call status flag slave mode interrupt decode bits

[start, repeated-start, data, stop] master mode select bit (0=slave mode) serial port reset transmission direction status (0=RX,1=TX) serial interface interrupt

I 2 C Control register (in master mode)

MDO

MDE

MCO

MDI

I2CM

I2CADD master mode SDATA output bit master mode SDATA output enable (0=disable) master mode SCLK output bit master mode SDATA input bit master mode select bit (0=slave mode)

I 2 C slave Address register

I2CADD1 , I2CADD2 , I2CADD3

I 2 C secondary slave Address registers

I2CDAT I 2 C Data register

PWMCON

PWM0H ,

PWM Control register

PWMCON.7 disable P2.6/P3.4 PWM output (0=enable)

PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,

PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,

PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]

PWMCON.3 PWM clock divide bits

PWMCON.2 PWM counter = clock / [1,4,16,64]

PWMCON.1 PWM clock source bits [0=F

XTAL

PWMCON.0 2=T0 ext.int.rate, 3=F

VCO

/15, 1=F

XTAL

(16.777MHz)]

,

PWM0L PWM0 data registers

PWM1H , PWM1L

DPCON

DPCON.6

DPCON.5

DPCON.4

DPCON.3

DPCON.2

DPCON.1

DPCON.0

T3CON

T3CON.7

T3CON.2

T3CON.1

T3CON.0

PWM1 data registers

Data Pointer Control register data pointer auto-toggle enable (0=disable) shadow data pointer mode control bits

[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl] main data pointer mode control bits

[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]

(not implemented to allow INC DPCON toggling) data pointer select [0=main, 1=shadow]

Timer 3 Control register

Timer 3 baud rate enable (0=disable) binary divide factor (DIV)

DIV = log[F CORE

(rounded down)

/(16·baudrate)] / log2

T3FD Timer 3 Fractional Divider register

T3FD = (2·F

CORE

) / (baudrate·2 (DIV-1) ) - 64

CHIPID Chip ID Register (AX hex = ADuC842/843)

CFG842/CFG843

CFG842.7

CFG842.6

CFG842.5

CFG842.4

CFG842.3

CFG842.2

CFG842.1

CFG842.0

WDCON

ADuC84x Config. Register extended stack-pointer enable (0=disable)

PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)

DAC output buffer bypass (0=buffer enabled) external clock select (0=internal clock)

(this bit must contain 0)

(this bit must contain 0) select SPI pins (0=default, 1=P3.3/P3.4/P3.5) internal XRAM select (0=external XRAM)

Watchdog Timer control register

PRE3

PRE2

PRE1

PRE0

WDIR

WDS

WDE

WDWR

PSMCON

PSMCON.6

PSMCON.5

PSMCON.4

PSMCON.3

PSMCON.2

PSMCON.1

PSMCON.0

SP watchdog timeout selection bits

0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms

8=0ms (immediate reset)

>8=reserved watchdog interrupt response bit watchdog status flag (1 indicates watchdog timeout) watchdog enable control (0=disabled) watchdog write enable bit (set to enable write)

Power Supply Monitor control register

PSM status bit (1=normal / 0=fault)

PSM interrupt bit trip point select bits

[(reserved), 3.08V, 2.93V, (reserved)]

(this bit must contain zero)

(reserved)

PSM powerdown control (1=on / 0=off)

Stack Pointer

SPH Stack Pointer High byte

IE Interrupt Enable register #1

EA

EADC

ET2

ES

ET1

EX1

ET0

EX0

IEIP2

IEIP2.6

IEIP2.5

IEIP2.4

IEIP2.3

IEIP2.2

IEIP2.1

IEIP2.0

IP

PADC

PT2

PS

PT1

PX1

PT0

PX0

TMOD enable interrupts (0=all interrupts disabled) enable ADCI (ADC interrupt) enable TF2/EXF2 (Timer2 overflow interrupt) enable RI/TI (serial port interrupt) enable TF1 (Timer1 overflow interrupt) enable IE1 (external interrupt 1) enable TF0 (Timer0 overflow interrupt) enable IE0 (external interrupt 0)

Interrupt Enable/Priority register #2 priority of TII interrupt (time interval) priority of PSMI interrupt (power supply monitor) priority of ISPI interrupt (serial interface)

(this bit must contain zero) enable TII interrupt (time interval) enable PSMI (power supply monitor interrupt) enable ISPI interrupt (serial interface)

Interrupt Priority register priority of ADCI (ADC interrupt) priority of TF2/EXF2 (Timer2 overflow interrupt) priority of RI/TI (serial port interrupt) priority of TF1 (Timer1 overflow interrupt) priority of IE1 (external interrupt 1) priority of TF0 (Timer0 overflow interrupt) priority of IE0 (external interrupt 0)

Timer Mode register

TMOD.3/.7

TMOD.2/.6

TMOD.1/.5

TMOD.0/.4

gate control bit (0=ignore INTx) counter/timer select bit (0=timer) timer mode selecton bits

[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]

(upper nibble = Timer1, lower nibble = Timer0)

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TH0,TL0

Timer Control register

Timer1 overflow flag (auto cleared on vector to ISR)

Timer1 run control (0=off, 1=run)

Timer0 overflow flag (auto cleared on vector to ISR)

Timer0 run control (0=off, 1=run) external INT1 flag (auto cleared on vector to ISR)

IE1 type (0=level trig, 1=edge trig) external INT0 flag (auto cleared on vector to ISR)

IE0 type (0=level trig, 1=edge trig)

Timer0 registers

TH1,TL1 Timer1 registers

T2CON

Timer2 Control register

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

CNT2

CAP2

TH2,TL2 overflow flag external flag receive clock enable (0=Timer1 used for RxD clk) transmit clock enable (0=Timer1 used for TxD clk) external enable (0=ignore T2EX, 1=cap/rld on T2EX) run control (0=stop, 1=run) timer/counter select (0=timer, 1=counter) capture/reload select (0=reload, 1=capture)

Timer2 register

RCAP2H,RCAP2L

P0

Timer2 Reload/Capture

Port0 register (also A0-A7 & D0-D7)

P1

T2EX

T2

P2

Port1 register (analog & digital inputs) timer/counter 2 capture/reload trigger timer/counter 2 external input

Port2 register (also A8-A15 & A16-A23)

P3

RD

WR

T1

T0

INT1

INT0

TxD

RxD

SCON

Port3 register external data memory read strobe external data memory write strobe timer/counter 1 external input timer/counter 0 external input external interrupt 1 external interrupt 0 serial port transmit data line serial port receive data line

Serial communications Control register

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SBUF

UART mode control bits baud rate:

00 - 8bit shift register - F CORE /12

01 - 8bit UART

10 - 9bit UART

- variable

- F

CORE receive enable control bit in modes 2&3, 9th bit transmitted in modes 2&3, 9th bit received transmit interrupt flag receive interrupt flag

/64(x2)

11 - 9bit UART - variable in modes 2&3, enables multiprocessor communication

Serial port Buffer register

PCON Power Control register

PCON.7 double baud rate control

PCON.4 ALE disable (0=normal, 1=forces ALE high)

PCON.3 general purpose flag

PCON.2 general purpose flag

PCON.1 power-down control bit (recoverable with hard reset)

PCON.0 idle-mode control (recoverable with enabled interrupt)

PSW Program Status Word

CY

AC

F0

RS1

RS0

OV

F1

P

DPP carry flag auxiliary carry flag general purpose flag 0 register bank select control bits

active register bank = [0,1,2,3] overflow flag general purpose flag 1 parity of ACC

Data Pointer Page

DPH,DPL (DPTR) Data Pointer

ACC

B

Accumulator auxiliary math register