3A SIMPLE SWITCHER Power Module with 4.5V-14.5V Input in QFN Package LMZ31503 ®
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SNVS992 – JULY 2013
3A SIMPLE SWITCHER
®
Power Module with 4.5V-14.5V Input in QFN Package
Check for Samples: LMZ31503
1
FEATURES
2
• Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
• 9mm x 15mm x 2.8mm package
- Pin Compatible with LMZ31506
• Efficiencies Up To 95%
• Wide-Output Voltage Adjust
0.8 V to 5.5 V, with 1% Reference Accuracy
• Optional Split Power Rail Allows
Input Voltage Down to 1.6 V
• Adjustable Switching Frequency
(330 kHz to 780 kHz)
• Synchronizes to an External Clock
• Adjustable Slow-Start
• Output Voltage Sequencing / Tracking
• Power Good Output
• Programmable Undervoltage Lockout (UVLO)
• Overcurrent Protection (Hiccup-Mode)
• Over Temperature Protection
• Pre-bias Output Start-up
• Operating Temperature Range: –40°C to 85°C
• Enhanced Thermal Performance: 13°C/W
• Meets EN55022 Class B Emissions
- Integrated Shielded Inductor
DESCRIPTION
The LMZ31503 SIMPLE SWITCHER® power module is an easy-to-use integrated power solution that combines a 3-A DC/DC converter with power
MOSFETs, a shielded inductor, and passives into a low profile, QFN package. This total power solution allows as few as 3 external components and eliminates the loop compensation and magnetics design process.
The 9×15×2.8 mm QFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design with up to 95% efficiency and excellent power dissipation with a thermal impedance of 13°C/W junction to ambient. The device delivers the full 3-A rated output current at 85°C ambient temperature without airflow.
The LMZ31503 offers the flexibility and the featureset of a discrete point-of-load design and is ideal for powering performance DSPs and FPGAs. Advanced packaging technology afford a robust and reliable power solution compatible with standard QFN mounting and testing techniques.
V
IN
SIMPLIFIED APPLICATION
LMZ31503
PVIN PWRGD
V
OUT
VIN VOUT
APPLICATIONS
• Broadband & Communications Infrastructure
• Automated Test and Medical Equipment
• Compact PCI / PCI Express / PXI Express
• DSP and FPGA Point of Load Applications
• High Density Distributed Power Systems
100
95
90
85
80
75
70
65
60
55
50
45
40
0 0.5
V
IN
= PV
IN
= 5 V, V
OUT
= 3.3V, f
SW
= 630 kHz
V
IN
= PV
IN
= 12 V, V
OUT
= 3.3V, f
SW
= 630 kHz
1 1.5
Output Current (A)
2 2.5
3
G000
C
IN
RT/CLK
SS/TR
STSEL
SENSE+
INH/UVLO
VADJ
PGND AGND
R
SET
C
OUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LMZ31503
SNVS992 – JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating temperature range (unless otherwise noted)
Input Voltage
Output Voltage
VIN
PVIN
INH/UVLO
VADJ
PWRGD
SS/TR
STSEL
RT/CLK
PH
PH 10ns Transient
V
DIFF
(GND to exposed thermal pad)
Source Current
Sink Current
RT/CLK
PH
PH
PVIN
PWRGD
Operating Junction Temperature
Storage Temperature
Mechanical Shock
Mechanical Vibration
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20-2000Hz
VALUE
–0.3 to 16
–0.3 to 16
–0.3 to 6
–0.3 to 3
–0.3 to 6
–0.3 to 3
–0.3 to 3
–0.3 to 6
–1 to 20
–3 to 20
–0.2 to 0.2
±100
Current Limit
Current Limit
Current Limit
–0.1 to 5
–40 to 125
(2)
–65 to 150
1500
20
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the temperature derating curves in the Typical Characteristics section for thermal information.
°C
°C
G
µA
A
A
A mA
V
V
V
V
V
UNIT
V
V
V
V
V
V
2
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SNVS992 – JULY 2013
THERMAL INFORMATION
θ
JA
ψ
JT
ψ
JB
THERMAL METRIC
Junction-to-ambient thermal resistance
(2)
Junction-to-top characterization parameter
(1)
(3)
Junction-to-board characterization parameter
(4)
LMZ31503
RUQ47
47 PINS
13
2.5
5
UNIT
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .
(2) The junction-to-ambient thermal resistance, θ
JA
, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with
1 oz. copper and natural convection cooling. Additional airflow reduces
θ
JA
.
(3) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature, T
J
, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). T
J
=
ψ
JT
* Pdis + T
T
; where Pdis is the power dissipated in the device and T
T the temperature of the top of the device.
(4) The junction-to-board characterization parameter,
ψ
JB
, estimates the junction temperature, T procedure described in JESD51-2A (sections 6 and 7). T
J the temperature of the board 1mm from the device.
= ψ
JB
* Pdis + T
B
J
, of a device in a real system, using a
; where Pdis is the power dissipated in the device and T
B is is
PACKAGE SPECIFICATIONS
LMZ31503
Weight
Flammability Meets UL 94 V-O
MTBF Calculated reliability Per Bellcore TR-332, 50% stress, T
A
= 40°C, ground benign
UNIT
1.26 grams
40.1 MHrs
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ELECTRICAL CHARACTERISTICS
Over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, V
OUT
C
IN1
= 2x 22 µF ceramic, C
IN2
= 68 µF poly-tantalum, C
OUT1
= 1.8 V, I
OUT
= 3A,
= 4x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
I
OUT
VIN
PVIN
UVLO
V
OUT(adj)
V
OUT
η
I
LIM
Output current
Input bias voltage range
T
A
= 85°C, natural convection
Over I
OUT range
Input switching voltage range Over I
OUT range
VIN = increasing
VIN Undervoltage lockout
VIN = decreasing
Output voltage adjust range
Set-point voltage tolerance
Over I
OUT range
T
A
= 25°C, I
OUT
= 0A
Temperature variation
Line regulation
-40°C ≤ T
A
≤ +85°C, I
OUT
= 0A
Over PVIN range, T
A
= 25°C, I
OUT
= 0A
Load regulation Over I
OUT range, T
A
= 25°C
Total output voltage variation Includes set-point, line, load, and temperature variation
Efficiency
I
I
PVIN = VIN = 12 V
O
= 1.5 A
PVIN = VIN = 5 V
O
= 1.5 A
V
OUT
= 5V, f
SW
= 780kHz
V
OUT
= 3.3V, f
SW
= 630kHz
V
OUT
= 2.5V, f
SW
= 480kHz
V
OUT
= 1.8V, f
SW
= 480kHz
V
OUT
= 1.2V, f
SW
= 480kHz
V
OUT
= 0.8V, f
SW
= 330kHz
V
OUT
= 3.3V, f
SW
= 630kHz
V
OUT
= 2.5V, f
SW
= 480kHz
V
OUT
= 1.8V, f
SW
= 480kHz
V
OUT
= 1.2V, f
SW
= 480kHz
V
OUT
= 0.8V, f
SW
= 330kHz
Output voltage ripple
Overcurrent threshold
20 MHz bandwith
Transient response 1.0 A/µs load step from 50 to 100% I
OUT(max)
Recovery time
V
OUT over/undershoot
0
4.5
1.6
(1)
3.5
0.8
4.0
3.85
±0.3%
±0.1%
±0.1%
91.5 %
89.0 %
86.9 %
85.2 %
82.1 %
78.7 %
93.3 %
91.4 %
88.8 %
85.2 %
81.8 %
35
5.8
190
35
V
INH-H
V
INH-L
I
I(stby)
Power
Good
Inhibit Control
INH Input current
INH Hysteresis current
Input standby current
PWRGD Thresholds
Inhibit High Voltage
Inhibit Low Voltage
INH < 1.1 V
INH > 1.26 V
INH pin to AGND
V
OUT rising
V
OUT falling
Good
Fault
Fault
Good
1.30
–0.3
-1.15
-3.4
2
94%
109%
91%
106%
MAX
3
14.5
14.5
4.5
5.5
±1.0%
(2)
±1.5%
(2)
Open
(3)
1.05
4 f
SW f
CLK
V
CLK-H
V
CLK-L
D
CLK
PWRGD Low Voltage
Switching frequency
Synchronization frequency
CLK High-Level Threshold
CLK Low-Level Threshold
CLK Duty cycle
Thermal Shutdown
I(PWRGD) = 2 mA
Over VIN and I
OUT ranges, RT/CLK pin OPEN
CLK Control
Thermal shutdown
Thermal shutdown hysteresis
270
330
2.0
20%
160
330
175
10
0.3
390
780
5.5
0.8
80%
UNIT
A
V
V
V
V
V
μA
μA
µA mV
PP
A
µs mV
V kHz kHz
V
V
°C
°C
(1) The minimum PVIN voltage is 1.6V or (V
OUT
+ 0.7V) , whichever is greater. VIN must be greater than 4.5V.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R
SET resistor.
(3) This control pin has an internal pullup. If this pin is left open circuit, the device operates when input power is applied. A small lowleakage (<300 nA) MOSFET is recommended for control. See the application section for further guidance.
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ELECTRICAL CHARACTERISTICS (continued)
Over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, V
OUT
C
IN1
= 2x 22 µF ceramic, C
IN2
= 68 µF poly-tantalum, C
OUT1
= 1.8 V, I
OUT
= 3A,
= 4x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS
C
IN
External input capacitance
Ceramic
Ceramic
Non-ceramic
MIN
22
(4)
68
(4)
200
(5)
TYP
C
OUT
External output capacitance Non-ceramic
Equivalent series resistance (ESR)
SNVS992 – JULY 2013
MAX
1500
5000
35
UNIT
µF
µF m Ω
(4) A minimum of 68µF of polymer tantalum and/or ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation. Locate the capacitor close to the device. See
for more details. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin to PGND.
(5) The amount of required output capacitance varies depending on the output voltage (see
). The amount of required capacitance must include ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See
and
more details.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
PWRGD
VSENSE+
VADJ
SS/TR
STSEL
RT/CLK
AGND
PWRGD
Logic
Thermal Shutdown
OCP
Shutdown
Logic
VIN
UVLO
VREF
+
+
Comp
Power
Stage and
Control
Logic
OSC w/PLL
INH/UVLO
VIN
PVIN
PH
VOUT
PGND
LMZ31503
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SNVS992 – JULY 2013
NAME
AGND
TERMINAL
NO.
1
2
34
45
8
INH/UVLO
9
DNC
PGND
PH
PWRGD
PVIN
38
10
11
12
13
30
31
32
36
37
33
39
40
41
14
17
46
18
19
20
22
23
15
16
3
4
5
RT/CLK 35
SENSE+ 44
SS/TR
STSEL
VADJ
VIN
6
7
43
42
PIN DESCRIPTIONS
DESCRIPTION www.ti.com
Zero VDC reference for the analog control circuitry. Connect AGND to PGND at a single point. Connect near the output capacitors. See for a recommended layout.
Inhibit and UVLO adjust pin. Use an open drain or open collector output logic to control the INH function. A resistor divider between this pin, AGND and VIN adjusts the UVLO voltage. Tie both pins together when using this control.
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
Common ground connection for the PVIN, VIN, and VOUT power connections. See for a recommended layout.
Phase switch node. These pins should be connected to a small copper island under the device for thermal relief. Do not place any external component on this pin or tie it to a pin of another function.
Power good fault pin. Asserts low if the output voltage is low. A pull-up resistor is required.
Input switching voltage. This pin supplies voltage to the power switches of the converter. See for a recommended layout.
This pin automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device. In CLK mode, the device synchronizes to an external clock.
Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be connected to VOUT at the load, or at the module pins.
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
A voltage applied to this pin allows for tracking and sequencing control.
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor with a SS interval of approximately 1.1 ms. Leave this pin open to enable the TR feature.
Connecting a resistor between this pin and AGND sets the output voltage.
Input bias voltage pin. Supplies the control circuitry of the power converter. See for a recommended layout.
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NAME
VOUT
TERMINAL
NO.
21
24
25
26
27
28
29
47
PIN DESCRIPTIONS (continued)
DESCRIPTION
Output voltage. Connect output capacitors between these pins and PGND.
RUQ PACKAGE
47 PINS
(TOP VIEW)
LMZ31503
SNVS992 – JULY 2013
AGND 1
6
7
8
9
10
11
12
13
14
4
5
2
3
AGND
DNC
DNC
DNC
SS/TR
STSEL
INH/UVLO
INH/UVLO
PH
PH
PH
PH
PH
46
PH
DNC 15
45
AGND
37 PGND
47
VO
VO
VO
VO
VO
DNC
DNC
VO
VO
PGND
RT/CLK
AGND
PWRGD
DNC
28
27
26
25
31
30
29
24
36
35
34
33
32
23 DNC
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SNVS992 – JULY 2013
100
95
90
85
80
75
70
65
60
55
50
45
40
0
www.ti.com
TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V)
(1) (2)
80
70
60
50
V
OUT
= 5.0 V, f
V
OUT
= 3.3 V, f
SW
= 780 kHz
SW
= 630 kHz
V
OUT
= 2.5 V, f
V
OUT
= 1.8 V, f
SW
= 480 kHz
SW
= 480 kHz
V
OUT
= 1.2 V, f
V
OUT
= 0.8 V, f
SW
= 480 kHz
SW
= 330 kHz
V
OUT
= 5.0 V, f
SW
= 780 kHz
V
OUT
= 3.3 V, f
SW
= 630 kHz
V
OUT
= 2.5 V, f
SW
= 480 kHz
V
OUT
= 1.8 V, f
SW
= 480 kHz
V
OUT
= 1.2 V, f
SW
= 480 kHz
V
OUT
= 0.8 V, f
SW
= 330 kHz
0.5
1 1.5
Output Current (A)
2 2.5
Figure 1. Efficiency vs. Output Current
3
G000
40
30
20
10
0 0.5
1 1.5
Output Current (A)
2 2.5
Figure 2. Voltage Ripple vs. Output Current
3
G000
2
1.6
1.2
0.8
0.4
V
OUT
= 5.0 V, f
SW
= 780 kHz
V
OUT
= 3.3 V, f
V
OUT
= 2.5 V, f
SW
= 630 kHz
SW
= 480 kHz
V
OUT
= 1.8 V, f
SW
= 480 kHz
V
OUT
= 1.2 V, f
V
OUT
= 0.8 V, f
SW
= 480 kHz
SW
= 330 kHz
90
80
70
60
50
40
30
20
0
All Output Voltages
0.5
1 1.5
Output Current (A)
2
Natural Convection
2.5
3
G000
0
0 0.5
1 1.5
Output Current (A)
2 2.5
Figure 3. Power Dissipation vs. Output Current
3
G000
Figure 4. Safe Operating Area
40
30
20
10
0
120
90
60
30
0
−10 −30
−20 −60
−30
Gain
Phase
−90
−40
1000 10000 100000
−120
400000
Frequency (Hz)
G000
Figure 5. V
OUT
= 1.8 V, I
OUT
= 3 A, C
OUT1
= 100 µF ceramic, C
OUT2
= 100 µF ceramic, f
SW
= 480 kHz
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to
Figure 1 , Figure 2 , and Figure 3 .
(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to
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TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V)
(1) (2)
60 100
95
90
85
80
75
70
65
60
55
50
45
40
0
V
OUT
= 3.3 V, f
SW
= 630 kHz
V
OUT
= 2.5 V, f
SW
= 480 kHz
V
OUT
= 1.8 V, f
SW
= 480 kHz
V
OUT
= 1.2 V, f
SW
= 480 kHz
V
OUT
= 1.0 V, f
SW
= 330 kHz
V
OUT
= 0.8 V, f
SW
= 330 kHz
0.5
1 1.5
Output Current (A)
2 2.5
Figure 6. Efficiency vs. Output Current
3
G000
50
40
30
20
SNVS992 – JULY 2013
V
OUT
= 3.3 V, f
V
OUT
= 2.5 V, f
SW
= 630 kHz
SW
= 480 kHz
V
OUT
= 1.8 V, f
V
OUT
= 1.2 V, f
SW
= 480 kHz
SW
= 480 kHz
V
OUT
= 0.8 V, f
SW
= 330 kHz
10
0 0.5
1 1.5
Output Current (A)
2 2.5
Figure 7. Voltage Ripple vs. Output Current
3
G000
1.2
0.9
0.6
0.3
V
OUT
= 3.3 V, f
SW
= 630 kHz
V
OUT
= 2.5 V, f
V
OUT
= 1.8 V, f
SW
= 480 kHz
SW
= 480 kHz
V
OUT
= 1.2 V, f
SW
= 480 kHz
V
OUT
= 1.0 V, f
V
OUT
= 0.8 V, f
SW
= 480 kHz
SW
= 330 kHz
90
80
70
60
50
40
30
20
0
All Output Voltages
0.5
1 1.5
Output Current (A)
2
Natural Convection
Figure 9. Safe Operating Area
2.5
3
G000
0
0 0.5
1 1.5
Output Current (A)
2 2.5
Figure 8. Power Dissipation vs. Output Current
3
G000
40
30
20
10
0
120
90
60
30
0
−10 −30
−20 −60
−30
Gain
Phase
−90
−40
1000 10000 100000
−120
400000
Frequency (Hz)
G000
Figure 10. V
OUT
=1.8 V, I
OUT
=3 A, C
OUT1
= 100 µF ceramic, C
OUT2
= 100 µF ceramic, f
SW
= 480 kHz
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to
Figure 6 , Figure 7 , and Figure 8 .
(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to
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TYPICAL CHARACTERISTICS (PVIN = 12 V, VIN = 5 V)
(1) (2)
80 100
95
90
85
80
75
70
65
60
55
50
45
40
0
V
OUT
= 5.0 V, f
SW
= 780 kHz
V
OUT
= 3.3 V, f
SW
= 630 kHz
V
OUT
= 2.5 V, f
SW
= 480 kHz
V
OUT
= 1.8 V, f
SW
= 480 kHz
V
OUT
= 1.2 V, f
SW
= 480 kHz
V
OUT
= 0.8 V, f
SW
= 330 kHz
0.5
1 1.5
Output Current (A)
2 2.5
Figure 11. Efficiency vs. Output Current
3
G000
70
60
50
40
30
20
V
OUT
= 5.0 V, f
V
OUT
= 3.3 V, f
SW
= 780 kHz
SW
= 630 kHz
V
OUT
= 2.5 V, f
V
OUT
= 1.8 V, f
SW
= 480 kHz
SW
= 480 kHz
V
OUT
= 1.2 V, f
V
OUT
= 0.8 V, f
SW
= 480 kHz
SW
= 330 kHz
10
0 0.5
1 1.5
Output Current (A)
2 2.5
Figure 12. Voltage Ripple vs. Output Current
3
G000
2
1.6
1.2
0.8
0.4
V
OUT
= 5.0 V, f
SW
= 780 kHz
V
OUT
= 3.3 V, f
V
OUT
= 2.5 V, f
SW
= 630 kHz
SW
= 480 kHz
V
OUT
= 1.8 V, f
SW
= 480 kHz
V
OUT
= 1.2 V, f
V
OUT
= 0.8 V, f
SW
= 480 kHz
SW
= 330 kHz
0
0 0.5
1 1.5
Output Current (A)
2 2.5
Figure 13. Power Dissipation vs. Output Current
3
G000
90
80
70
60
50
40
30
20
0
All Output Voltages
0.5
1 1.5
Output Current (A)
2
Natural Convection
Figure 14. Safe Operating Area
2.5
3
G000
40
30
20
10
0
120
90
60
30
0
−10 −30
−20 −60
−30
Gain
Phase
−90
−40
1000 10000
Frequency (Hz)
100000
−120
400000
Figure 15. V
C
OUT
=2.5 V, I
OUT
=3 A, C
OUT2
= 100 µF ceramic, f
OUT1
= 100 µF ceramic,
SW
= 480 kHz
G000
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to
,
, and
(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to
.
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2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
1.8
1.9
2.0
2.1
2.2
V
OUT
(V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
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APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE
The VADJ control sets the output voltage of the LMZ31503. The output voltage adjustment range is from 0.8V to
5.5V. The adjustment method requires the addition of R
SET
, which sets the output voltage, the connection of
SENSE+ to VOUT, and in some cases R
RT which sets the switching frequency. The R
SET resistor must be connected directly between the VADJ (pin 43) and AGND (pin 45). The SENSE+ pin (pin 44) must be connected to VOUT either at the load for improved regulation or at VOUT of the module. The R
RT connected directly between the RT/CLK (pin 35) and AGND (pin 34).
resistor must be
gives the standard external R
SET
R
RT resistor for a number of common bus voltages, along with the required resistor for that output voltage. For other output voltages, the value of the required resistor can either be calculated using
, or selected from the values given in
RESISTORS
Table 1. Standard R
SET
Resistor Values for Common Output Voltages
R
SET
(k Ω)
R
RT
(k Ω)
R
SET
=
1.43
æ
ç
è
æ
è
V
OUT
0.8
ö
ø
-
1
ö
÷
ø
0.8
open open
1.0
5.76
open
1.2
2.87
324
OUTPUT VOLTAGE V
OUT
(V)
1.5
1.8
1.62
324
1.13
324
2.5
0.665
324
3.3
0.453
158
5.0
0.267
105
(1)
1.13
1.02
0.953
0.866
0.806
0.750
0.715
0.665
0.634
0.604
0.562
0.536
0.511
0.499
R
SET
(k Ω)
open
11.3
5.76
3.83
2.87
2.26
1.91
1.62
1.43
1.27
480
480
480
530
530
530
530
580
580
480
480
480
480
480
f
SW
(kHz)
330
330
330
330
480
480
480
480
480
480
Table 2. Standard R
SET
Resistor Values
324
324
324
237
237
237
237
191
191
324
324
324
324
324
R
RT
(k Ω)
open open open open
324
324
324
324
324
324
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
4.2
4.3
4.4
4.5
4.6
V
OUT
(V)
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
0.332
0.324
0.316
0.309
0.301
0.294
0.287
0.280
0.267
0.267
0.261
0.255
0.249
0.243
R
SET
(k Ω)
0.475
0.453
0.442
0.422
0.402
0.392
0.374
0.365
0.357
0.348
118
105
105
105
105
105
105
105
105
118
118
118
118
118
R
RT
(k Ω)
191
158
158
158
158
158
137
137
137
137
730
780
780
780
780
780
780
780
780
730
730
730
730
730
f
SW
(kHz)
580
630
630
630
630
630
680
680
680
680
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CAPACITOR RECOMMENDATIONS FOR THE LMZ31503 POWER SUPPLY
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Capacitor Technologies
Electrolytic, Polymer-Electrolytic Capacitors
When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.
Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures are above 0°C.
Ceramic Capacitors
The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output.
Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power applications.
Input Capacitor
The LMZ31503 requires a minimum input capacitance of 68 μF of ceramic and/or polymer-tantalum capacitors.
The ripple current rating of the capacitor must be at least 450 mArms.
includes a preferred list of capacitors by vendor.
Output Capacitor
The required output capacitance is determined by the output voltage of the LMZ31503. See
for the amount of required capacitance. The required output capacitance must be comprised of all ceramic capacitors.
When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in
are required. The required capacitance above the minimum is determined by actual transient deviation requirements. See
for typical transient response values for several output voltage, input voltage and capacitance combinations.
includes a preferred list of capacitors by vendor.
MIN
0.8
1.2
3.0
4.0
Table 3. Required Output Capacitance
V
OUT
RANGE (V)
MINIMUM REQUIRED C
OUT
(µF)
MAX
< 1.2
< 3.0
< 4.0
5.5
6x 47 µF ceramic
4x 47 µF ceramic
2x 47 µF ceramic
47 µF ceramic
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Table 4. Output Voltage Transient Response
C
IN1
= 22 µF CERAMIC, C
IN2
= 68 µF POSCAP, LOAD STEP = 1.5 A, 1 A/µs
V
OUT
(V) PV
IN
(V) C
OUT1
Ceramic C
OUT2
BULK
VOLTAGE
DEVIATION (mV)
0.8
5
12
5
6x 47 µF
6x 47 µF
6x 47 µF
6x 47 µF
6x 47 µF
None
330 µF
None
330 µF
None
25
15
20
15
20
1.0
12
6x 47 µF
6x 47 µF
6x 47 µF
330 µF
None
330 µF
15
20
15
1.2
1.8
5
12
5
4x 47 µF
4x 47 µF
4x 47 µF
4x 47 µF
4x 47 µF
4x 47 µF
4x 47 µF
12
None
220 µF
None
220 µF
None
220 µF
None
30
25
30
25
35
30
35
3.3
5.0
5
12
12
4x 47 µF
2x 47 µF
2x 47 µF
2x 47 µF
2x 47 µF
1x 47 µF
1x 47 µF
220 µF
None
100 µF
None
100 µF
None
100 µF
30
65
55
65
60
100
85
PEAK-PEAK (mV)
55
130
110
130
120
200
170
55
50
65
55
65
30
45
30
55
45
55
30
35
30
40
RECOVERY TIME
(µs)
170
160
180
170
170
180
170
180
180
190
170
180
170
170
170
180
190
190
200
200
210
210
VENDOR
Murata
TDK
Murata
Sanyo
Kemet
Sanyo
Sanyo
Kemet
Kemet
Sanyo
Sanyo
SERIES
X5R
X5R
X5R
POSCAP
T520
POSCAP
POSCAP
T530
T530
POSCAP
POSCAP
Table 5. Recommended Input/Output Capacitors
(1)
PART NUMBER
GRM32ER61E226K
C3225X5R0J476K
GRM32ER60J476M
16TQC68M
T520V107M010ASE025
6TPE100MI
2R5TPE220M7
T530D227M006ATE006
T530D337M006ATE010
2TPF330M6
6TPE330MFL
10
6.3
2.5
6.3
6.3
2.0
6.3
WORKING
VOLTAGE
(V)
16
CAPACITOR CHARACTERISTICS
CAPACITANCE
(µF)
22
ESR
(2)
(m Ω)
2
6.3
6.3
16
47
47
68
2
2
50
100
100
220
220
330
330
330
6
10
6
15
25
25
7
(1)
Capacitor Supplier Verification
Please verify availability of capacitors identified in this table.
RoHS, Lead-free and Material Details
Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process requirements.
(2) Maximum ESR @ 100kHz, 25°C.
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Transient Response
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Figure 16. PVIN = 12V, VOUT = 0.8V, 1.5A Load
Step
Figure 17. PVIN = 5V, VOUT = 0.8V, 1.5A Load Step
Figure 18. PVIN = 12V, VOUT = 1.2V, 1.5A Load
Step
Figure 19. PVIN = 5V, VOUT = 1.2V, 1.5A Load Step
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Figure 20. PVIN = 12V, VOUT = 1.8V, 1.5A Load
Step
Figure 21. PVIN = 5V, VOUT = 1.8V, 1.5A Load Step
Figure 22. PVIN = 12V, VOUT = 3.3V, 1.5A Load
Step
Figure 23. PVIN = 5V, VOUT = 3.3V, 1.5A Load Step
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Application Schematics
V
IN
/ P
VIN
4.5 V to 14.5 V
+
C
IN2
68 F
C
IN1
22 F
R
SET
324 k
R
SET
1.13 k
LMZ31503
VIN
PWRGD
PVIN
INH/UVLO
SENSE+
VOUT
SS/TR
RT/CLK
VADJ
STSEL AGND PGND
V
OUT
1.8 V
C
OUT1
4x 47 F
+
C
OUT2
220 F
Figure 24. Typical Schematic
PVIN = VIN = 4.5 V to 14.5 V, VOUT = 1.8 V
V
IN
/ P
VIN
4.5 V to 14.5 V
+
C
IN2
68 F
C
IN1
22 F
R
RT
158 k
R
SET
453
LMZ31503
VIN
PWRGD
PVIN
INH/UVLO
SENSE+
VOUT
SS/TR
RT/CLK
VADJ
STSEL AGND PGND
V
OUT
3.3 V
C
OUT1
2x 47 F
+
C
OUT2
100 F
Figure 25. Typical Schematic
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PV
IN
3.3 V
+
C
IN2
68 F
V
IN
4.5 V to 14.5 V
C
IN3
4.7 F
C
IN1
22 F
VIN
PVIN
LMZ31503
PWRGD
SENSE+
INH/UVLO VOUT
SS/TR
RT/CLK
R
SET
5.76 k
VADJ
STSEL AGND PGND
V
OUT
1.0 V
C
OUT1
6x 47 F
+
C
OUT2
330 F
LMZ31503
SNVS992 – JULY 2013
Figure 26. Typical Schematic
PVIN = 3.3 V, VIN = 4.5 V to 14.5 V, VOUT = 1.0 V
VIN and PVIN Input Voltage
The LMZ31503 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 14.5 V. If using the
VIN pin separately from the PVIN pin, the VIN pin must be between 4.5 V and 14.5 V, and the PVIN pin can range from as low as 1.6 V to 14.5 V. A voltage divider connected to the INH/UVLO pin can adjust the either input voltage UVLO appropriately. See the
Programmable Undervoltage Lockout (UVLO)
section of this datasheet for more information.
Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 94% and 106% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 k Ω and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once
VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is lower than 91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input
UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.
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Power-Up Characteristics
When configured as shown in the front page schematic, the LMZ31503 produces a regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is recognized.
shows the start-up waveforms for a LMZ31503, operating from a 5-V input (PVIN=VIN) and with the output voltage adjusted to 1.8 V.
shows the start-up waveforms for a LMZ31503 starting up into a pre-biased output voltage. The waveforms were measured with a 2-A constant current load.
Figure 27. Start-Up Waveforms Figure 28. Start-up into Pre-bias
Pre-Biased Start-Up
The LMZ31503 has been designed to prevent discharging a pre-biased output. During monotonic pre-biased startup, the LMZ31503 does not allow current to sink until the SS/TR pin voltage is higher than 1.4 V.
Remote Sense
The SENSE+ pin must be connected to V
OUT at the load, or at the device pins.
Connecting the SENSE+ pin to V
OUT at the load improves the load regulation performance of the device by allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by the high output current flowing through the small amount of pin and trace resistance. This should be limited to a maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear or frequency dependent components that may be placed in series with the converter output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the SENSE+ connection, they are effectively placed inside the regulation control loop, which can adversely affect the stability of the regulator.
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Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state.
The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to interface with the pin.
shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to
VIN potential. An open-collector or open-drain device is recommended to control this input.
Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown in
. A regulated output voltage is produced within 10 ms. The waveforms were measured with a 2-A constant resistance load.
INH
Control
Q1
INH/UVLO
AGND STSEL
Figure 29. Typical Inhibit Control
Figure 30. Inhibit Turn-Off Figure 31. Inhibit Turn-On
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Slow Start (SS/TR)
Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow start interval of approximately 1.1 ms. Adding additional capacitance between the SS pin and AGND increases the slow start time.
shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin connected to AGND. See
below for SS capacitor values and timing interval.
SS/TR
C
SS
(Optional)
AGND STSEL
Figure 32. Slow-Start Capacitor (C
SS
) and STSEL Connection
C
SS
(pF)
SS Time (msec)
Table 6. Slow-Start Capacitor Values and Slow-Start Time open
1.1
2200
1.9
4700
2.8
10000
4.6
15000
6.4
22000
8.8
25000
9.8
Overcurrent Protection
For protection against load faults, the LMZ31503 incorpoates output overcurrent protection. Applying a load that exceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, the output voltage periodically attempts to recover by initiating a soft-start power-up. This is described as a hiccup mode of operation, whereby the module continues in a cycle of successive shutdown and power up until the load fault is removed, as shown in
Figure 33 . During this period, the average current flowing into the fault is
significantly reduced. Once the fault is removed, the module automatically recovers and returns to normal operation, as shown in
.
Figure 33. Overcurrent - Hiccup Mode Figure 34. Removal of Overcurrent Condition
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Synchronization (CLK)
An internal phase locked loop (PLL) has been implemented to allow synchronization between 330 kHz and
780 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in .
Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor (R
RT
). When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to th CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to
100 kHz and may shut-down due to internal protection circuits before returning to the switching frequency set by the RT resistor.
External Clock
330 kHz to 780 kHz
RT/CLK
R
RT
AGND
Figure 35. CLK/RT Configuration
The synchronization frequency must be selected based on the output voltages of the devices being synchronized.
shows the allowable frequencies for a given range of output voltages. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three LMZ31503 devices with output voltages of 1.2 V, 1.8 V and 2.5 V, all powered from
PVIN = 12 V.
shows that all three output voltages can be synchronized to frquencies between 480 kHz to
630 kHz. For best efficiency, choose 480 kHz as the sychronization frequency.
SYNCHRONIZATION
FREQUENCY (kHz)
330
380
430
480
530
580
630
680
730
780
Table 7. Synchronization Frequency vs Output Voltage
R
RT
(k
Ω)
OPEN
1000
499
324
237
191
158
137
118
105
0.8
0.9
1.0
1.1
1.2
PVIN = 12 V
V
OUT
RANGE (V)
MIN MAX
0.8
0.8
1.5
1.7
1.3
1.4
1.5
4.1
4.7
5.5
2.1
2.5
2.9
3.2
3.7
PVIN = 5 V
V
OUT
RANGE (V)
MIN MAX
0.8
4.3
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Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and
PWRGD pins. The sequential method is illustrated in
using two LMZ31503 devices. The PWRGD pin of the first device is coupled to the INH pin of the second device which enables the second power supply once the primary supply reaches regulation.
shows sequential turn-on waveforms of two LMZ31503 devices.
INH/UVLO
STSEL
VOUT
PWRGD
V
OUT1
INH/UVLO
STSEL
VOUT
PWRGD
V
OUT2
Figure 36. Sequencing Schematic Figure 37. Sequencing Waveforms
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in
to the output of the power supply that needs to be tracked or to another voltage reference source.
shows simultaneous turn-on waveforms of two LMZ31503 devices. Use
and
to calculate the values of R1 and R2.
R1 =
(
V
OUT2
´
12.6
)
0.8
(2)
R2 =
0.8
´
R1
(
V
OUT2
0.8
)
(3)
V
OUT1
INH/UVLO
VOUT
STSEL SS/TR
INH/UVLO
VOUT
STSEL SS/TR
V
OUT2
R1
R2
Figure 38. Simultaneous Tracking Schematic
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Figure 39. Simultaneous Tracking Waveforms
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Programmable Undervoltage Lockout (UVLO)
The LMZ31503 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a typical hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, then the UVLO pin can be configured as shown in
or
lists standard values for R
UVLO1 and R
UVLO2 to adjust the VIN UVLO voltage up.
R
UVLO1
INH/UVLO
R
UVLO2
PVIN
VIN
PVIN
VIN
R
UVLO1
R
UVLO2
INH/UVLO
Figure 40. Adjustable VIN UVLO Figure 41. Adjustable VIN and PVIN Undervoltage
Lockout
VIN UVLO (V) 5.0
R
UVLO1
(k Ω)
68.1
R
UVLO2
(k
Ω)
21.5
Hysteresis (mV)
400
Table 8. Standard Resistor values for Adjusting VIN UVLO
5.5
68.1
18.7
415
6.0
68.1
16.9
430
6.5
68.1
15.4
450
7.0
68.1
14.0
465
7.5
68.1
13.0
480
8.0
68.1
12.1
500
8.5
68.1
11.3
515
9.0
68.1
10.5
530
9.5
68.1
9.76
550
10.0
68.1
9.31
565
For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5V.
shows the
PVIN UVLO configuration. Use
to select R
UVLO1 and R
UVLO2 for PVIN. If PVIN UVLO is set for less than
3.0 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V.
> 4.5 V
R
UVLO1
INH/UVLO
R
UVLO2
VIN
PVIN
Figure 42. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V)
Table 9. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V)
PVIN UVLO (V)
R
UVLO1
(k Ω)
R
UVLO2
(k Ω)
Hysteresis (mV)
2.0
68.1
95.3
300
2.5
68.1
60.4
315
3.0
68.1
44.2
335
3.5
68.1
34.8
350
4.0
68.1
28.7
365
4.5
68.1
24.3
385
For higher PVIN UVLO voltages see
Table UV for resistor values
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LMZ31503
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SNVS992 – JULY 2013
www.ti.com
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically.
Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required.
and
show two layers of a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
• Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place a dedicated AGND copper area beneath the LMZ31503.
• Isolate the PH copper area from the VOUT copper area using the AGND copper area.
• Connect the AGND and PGND copper area at one point; near the output capacitors.
• Place R
SET
, R
RT
, and C
SS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
SENSE+
Via
SENSE+
Via
VOUT
C
OUT3
PGND
Plane
C
OUT2
C
OUT1
PGND
R
RT
Vias to
Topside
PGND
Copper
AGND to PGND connection
C
IN1
C
IN2
AGND
Vias to
Topside
AGND
Copper
AGND
Plane
PH
VIN/PVIN
R
SET
SENSE+
Via
C
SS
Figure 43. Typical Top-Layer Recommended
Layout
SENSE+
Via
Figure 44. Typical GND-Layer Recommended
Layout
24
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LMZ31503 www.ti.com
SNVS992 – JULY 2013
EMI
The LMZ31503 is compliant with EN55022 Class B radiated emissions.
and
show typical examples of radiated emissions plots for the LMZ31503 operating from 5V and 12V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions.
Figure 45. Radiated Emissions 5-V Input, 1.2-V
Output, 3-A Load (EN55022 Class B)
Figure 46. Radiated Emissions 12-V Input, 1.2-V
Output, 3-A Load (EN55022 Class B)
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Product Folder Links:
LMZ31503
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2014
PACKAGING INFORMATION
Orderable Device
LMZ31503RUQR
Status
(1)
ACTIVE
Package Type Package
Drawing
Pins Package
Qty
B1QFN RUQ 47 500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
MSL Peak Temp
(3)
Level-3-260C-168 HR
Op Temp (°C)
-40 to 85
Device Marking
(4/5)
(54320 ~ LMZ31503)
LMZ31503RUQT ACTIVE B1QFN RUQ 47 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 (54320 ~ LMZ31503)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
22-Nov-2014 www.ti.com
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
12-Jan-2015
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ
LMZ31503RUQR
LMZ31503RUQT
B1QFN
B1QFN
RUQ
RUQ
47
47
500
250
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
24.4
330.0
24.4
A0
(mm)
9.35
9.35
B0
(mm)
15.35
15.35
K0
(mm)
3.1
3.1
P1
(mm)
16.0
16.0
W
(mm)
24.0
24.0
Pin1
Quadrant
Q1
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
12-Jan-2015
*All dimensions are nominal
Device
LMZ31503RUQR
LMZ31503RUQT
Package Type Package Drawing Pins
B1QFN
B1QFN
RUQ
RUQ
47
47
SPQ
500
250
Length (mm) Width (mm) Height (mm)
383.0
383.0
353.0
353.0
58.0
58.0
Pack Materials-Page 2
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