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RSET CREG[1:4]
High Performance, ISM Band,
FEATURES
Low power, low IF transceiver
Frequency bands
431 MHz to 478 MHz
862 MHz to 956 MHz
Data rates supported
0.15 kbps to 200 kbps, FSK
0.15 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 0.3 dBm steps
Receiver sensitivity
−119 dBm at 1 kbps, FSK
−112 dBm at 9.6 kbps, FSK
−106.5 dBm at 9.6 kbps, ASK
Low power consumption
19 mA in receive mode
26.8 mA in transmit mode (10 dBm output)
−3 dBm IIP3 in high linearity mode
FUNCTIONAL BLOCK DIAGRAM
ADCIN MUXOUT
FSK/ASK Transceiver IC
ADF7020
On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC) compensates for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at
431 MHz to 478 MHz
Digital RSSI
Integrated Tx/Rx switch
Leakage current of <1 µA in power-down mode
APPLICATIONS
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
ADF7020
R
LNA
LDO(1:4) TEMP
SENSOR
TEST MUX
OFFSET
CORRECTION
LNA
RFIN
RFINB
IF FILTER RSSI
MUX
7-BIT ADC
FSK/ASK
DEMODULATOR
DATA
SYNCHRONIZER
GAIN
OFFSET
CORRECTION
FSK MOD
CONTROL
GAUSSIAN
FILTER
-
MODULATOR
AGC
CONTROL
AFC
CONTROL
Tx/Rx
CONTROL
CE
DATA CLK
DATA I/O
INT/LOCK
RFOUT
DIVIDERS/
MUXING
DIV P N/N + 1
VCO
SERIAL
PORT
SLE
SDATA
SREAD
SCLK
CP PFD
DIV R OSC
CLK
DIV
VCOIN CPOUT CLKOUT
OSC1 OSC2
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved.
ADF7020
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Timing Characteristics..................................................................... 8
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Frequency Synthesizer ................................................................... 15
Reference Input........................................................................... 15
Choosing Channels for Best System Performance................. 17
RF Output Stage.......................................................................... 18
Modulation Schemes.................................................................. 18
RF Front End............................................................................... 20
RSSI/AGC.................................................................................... 21
FSK Demodulators on the ADF7020....................................... 21
FSK Correlator/Demodulator................................................... 21
Linear FSK Demodulator .......................................................... 23
Automatic Sync Word Recognition ......................................... 24
Applications Information .............................................................. 25
LNA/PA Matching...................................................................... 25
Image Rejection Calibration ..................................................... 26
Transmit Protocol and Coding Considerations ..................... 27
Device Programming after Initial Power-Up ......................... 27
Interfacing to Microcontroller/DSP ........................................ 27
Power Consumption and battery lifetime calculations......... 28
Serial Interface ................................................................................ 31
Readback Format........................................................................ 31
Register 0—N Register............................................................... 32
Register 1—Oscillator/Filter Register...................................... 33
Register 2—Transmit Modulation Register (ASK/OOK
Mode)........................................................................................... 34
Register 2—Transmit Modulation Register (FSK Mode) ..... 35
Register 2—Transmit Modulation Register (GFSK/GOOK
Mode)........................................................................................... 36
Register 3—Receiver Clock Register ....................................... 37
Register 4—Demodulator Setup Register ............................... 38
Register 5—Sync Byte Register................................................. 39
Register 6—Correlator/Demodulator Register ...................... 40
Register 7—Readback Setup Register...................................... 41
Register 8—Power-Down Test Register .................................. 42
Register 9—AGC Register......................................................... 43
Register 10—AGC 2 Register.................................................... 44
Register 11—AFC Register ....................................................... 44
Register 12—Test Register......................................................... 45
Register 13—Offset Removal and Signal Gain Register ....... 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
Rev. C | Page 2 of 48
REVISION HISTORY
5/11—Rev. B to Rev. C
Added Exposed Pad Notation to Outline Dimensions ..............47
Changes to Ordering Guide...........................................................47
8/07—Rev. A to Rev. B
Changes to Features ..........................................................................1
Changes to General Description .....................................................4
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................8
Changes to Reference Input Section .............................................15
Changes to N Counter Section ......................................................16
Changes to Choosing Channels for Best Performance Section 17
Changes to Table 5 ..........................................................................20
Changes to FSK Correlator Register Settings Section ................22
Added Image Rejection Calibration Section ...............................26
Added Figure 41 ..............................................................................30
Changes to Readback Format Section ..........................................31
Changes to Register 9—AGC Register Comments Section.......43
Added Register 12—Test Register Comments Section ..............45
4/06—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Table 1 ............................................................................5
Changes to Figure 24 ......................................................................17
Changes to the Setting Up the ADF7020 for GFSK Section......19
Changes to Table 6 ..........................................................................21
ADF7020
Changes to Table 9 ..........................................................................23
Changes to External AFC Section.................................................23
Deleted Maximum AFC Range Section .......................................23
Added AFC Performance Section.................................................24
Changes to Internal Rx/Tx Switch Section ..................................25
Changes to Figure 32 ......................................................................25
Changes to Transmit Protocol and Coding Considerations
Section ..............................................................................................26
Added Text Relating to Figure 37 .................................................27
Changes to Figure 41 ......................................................................31
Changes to Register 1—Oscillator/Filter Register
Comments........................................................................................31
Changes to Figure 42 ......................................................................32
Changes to Register 2—Transmit Modulation Register
(FSK Mode) Comments .................................................................33
Changes to Figure 44 ......................................................................34
Changes to Register 2—Transmit Modulation Register
(GFSK/GOOK Mode) Comments................................................34
Changes to Register 4—Demodulator Setup Register
Comments........................................................................................36
Changes to Figure 51 ......................................................................41
Changes to Figure 53 ......................................................................42
Changes to Ordering Guide...........................................................45
6/05—Revision 0: Initial Version
Rev. C | Page 3 of 48
ADF7020
GENERAL DESCRIPTION
The ADF7020 is a low power, highly integrated FSK/ASK/OOK transceiver designed for operation in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed
Japanese RFID band at 950 MHz. A Gaussian data filter option is available to allow either GFSK or G-ASK modulation, which provides a more spectrally efficient modulation. In addition to these modulation options, the ADF7020 can also be used to perform both MSK and GMSK modulation, where MSK is a special case of FSK with a modulation index of 0.5. The modulation index is calculated as twice the deviation divided by the data rate. MSK is spectrally equivalent to O-QPSK modulation with half-sinusoidal Tx baseband shaping, so the ADF7020 can also support this modulation option by setting up the device in
MSK mode.
This device is suitable for circuit applications that meet the
European ETSI-300-220, the North American FCC (Part 15), or the Chinese Short Range Device regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7020 very suitable for price-sensitive and area-sensitive applications.
The transmitter block on the ADF7020 contains a VCO and low noise fractional-N PLL with an output resolution of
<1 ppm. This frequency agile PLL allows the ADF7020 to be used in frequency-hopping spread spectrum (FHSS) systems.
The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency-pulling problems.
The transmitter output power is programmable in 0.3 dB steps from −16 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.
A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application.
The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to track out the frequency error in the incoming signal.
An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.
Rev. C | Page 4 of 48
ADF7020
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical specifications are at VDD = 3 V, T
A
= 25°C.
All measurements are performed using the EVAL-ADF7020DBZx using the PN9 data sequence, unless otherwise noted.
Table 1.
Parameter Min
RF CHARACTERISTICS
Frequency Ranges (Direct Output) 862
902
928
Frequency Ranges (Divide-by-2 Mode) 431
440
Phase Frequency Detector Frequency RF/256
Typ
TRANSMISSION PARAMETERS
Data Rate
FSK/GFSK
OOK/ASK
OOK/ASK
Frequency Shift Keying
GFSK/FSK Frequency Deviation
Deviation Frequency Resolution
Gaussian Filter BT
Amplitude Shift Keying
ASK Modulation Depth
PA Off Feedthrough in OOK Mode
Transmit Power
Transmit Power Variation vs.
Temperature
Transmit Power Variation vs. VDD
Transmit Power Flatness
Programmable Step Size
−20 dBm to +13 dBm
Integer Boundary
0.15
0.15
0.3
1
4.88
100
−20
0.5
−50
±1
±1
±1
0.3125
−55
Max Unit
870
928
956
440
478
24
MHz
MHz
MHz
MHz
MHz
MHz
30
+13
200 kbps
64
100 kbaud
110
620 kHz kHz
Hz dB dBm dBm dB dB dB dB dBc
Test Conditions
VCO adjust = 0, VCO bias = 10
VCO adjust = 3, VCO bias = 10
VCO adjust = 3, VCO bias = 12, VDD = 2.7 V to 3.6 V
VCO adjust = 0, VCO bias = 10
VCO adjust = 3, VCO bias = 12
Using Manchester encoding
PFD = 3.625 MHz
PFD = 20 MHz
PFD = 3.625 MHz
VDD = 3.0 V, T
A
= 25°C
From −40°C to +85°C
From 2.3 V to 3.6 V at 915 MHz, T
A
= 25°C
From 902 MHz to 928 MHz, 3 V, T
A
= 25°C
50 kHz loop BW
Harmonics
Second Harmonic
Third Harmonic
All Other Harmonics
VCO Frequency Pulling, OOK Mode
Optimum PA Load Impedance
RECEIVER PARAMETERS
FSK/GFSK Input Sensitivity
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
Sensitivity at 200 kbps
OOK Input Sensitivity
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
−27
−21
−35
30
39 + j61
48 + j54
54 + j94
−119.2
−112.8
−100
−116
−106.5 dBm dBm dBm dBm dBm
Ω
Ω
Ω dBc dBc dBc kHz rms
Unfiltered conductive
DR = 9.6 kbps
FRF = 915 MHz
FRF = 868 MHz
FRF = 433 MHz
At BER = 1E − 3, FRF = 915 MHz,
LNA and PA matched separately
FDEV = 5 kHz, high sensitivity mode
FDEV = 10 kHz, high sensitivity mode
FDEV = 50 kHz, high sensitivity mode
At BER = 1E − 3, FRF = 915 MHz
High sensitivity mode
High sensitivity mode
Rev. C | Page 5 of 48
ADF7020
Parameter
Enhanced Linearity Mode
Low Current Mode
High Sensitivity Mode
Rx Spurious Emissions
AFC
Pull-In Range at 868 MHz/915 MHz
Min
Pull-In Range at 433 MHz
Response Time
Accuracy
CHANNEL FILTERING
Adjacent Channel Rejection
(Offset = ±1 × IF Filter BW Setting)
Second Adjacent Channel Rejection
(Offset = ±2 × IF Filter BW Setting)
Third Adjacent Channel Rejection
(Offset = ±3 × IF Filter BW Setting)
Image Channel Rejection
(Uncalibrated)
Image Channel Rejection (Calibrated)
CO-CHANNEL REJECTION
Wideband Interference Rejection
BLOCKING
±1 MHz
±5 MHz
±10 MHz
±10 MHz (High Linearity Mode)
Saturation (Maximum Input Level)
LNA Input Impedance
RSSI
Range at Input
Linearity
Absolute Accuracy
Response Time
PHASE-LOCKED LOOP
VCO Gain
Phase Noise (In-Band)
Phase Noise (Out-of-Band)
Residual FM
PLL Settling
Typ
1
−3
−5
−24
±50
±25
48
27
50
55
30
50
−2
70
130
65
−89
−110
128
40
60
68
65
72
12
24 − j60
26 − j63
71 − j128
−110 to
−24
±2
±3
150
65
Max
−57
−47
Unit
dBm dBm dBm dBm dBm kHz kHz
Bits kHz dB dB dB dB dB
μs
MHz/V
MHz/V
MHz/V dBc/Hz dBc/Hz
Hz
μs
Test Conditions
Pin = −20 dBm, 2 CW interferers
FRF = 915 MHz, F1 = FRF + 3 MHz
F2 = FRF + 6 MHz, maximum gain
<1 GHz at antenna input
>1 GHz at antenna input
IF_BW = 200 kHz
IF_BW = 200 kHz
Modulation index = 0.875
Desired signal 3 dB above the input sensitivity level,
CW interferer power level increased until BER = 10 −3 , image channel excluded
IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
IF filter BW settings = 100 kHz, 150 kHz, 200 kHz dB Image at FRF = 400 kHz dB dB dB dB dB dB dB dBm
Ω
Ω
Ω
dBm
Image at FRF = 400 kHz
Swept from 100 MHz to 2 GHz, measured as channel rejection
Desired signal 3 dB above the input sensitivity level,
CW interferer power level increased until BER = 10
−2
FSK mode, BER = 10 −3
FRF = 915 MHz, RFIN to GND
FRF = 868 MHz
FRF = 433 MHz
section
902 MHz to 928 MHz band,
VCO adjust = 0, VCO_BIAS_SETTING = 10
860 MHz to 870 MHz band, VCO adjust = 0
433 MHz, VCO adjust = 0
PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,
FRF = 915 MHz, VCO_BIAS_SETTING = 10
1 MHz offset
From 200 Hz to 20 kHz, FRF = 868 MHz
Measured for a 10 MHz frequency step to within
5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz
Rev. C | Page 6 of 48
ADF7020
Parameter Min Typ Max Unit Test Conditions
REFERENCE INPUT
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
Input Level
ADC PARAMETERS
INL
DNL
TIMING INFORMATION
Chip Enabled to Regulator Ready
Chip Enabled to RSSI Ready
Tx to Rx Turnaround Time
3.625
3.625
33
2.1
1.0
±1
±1
10
3.0
150 μs +
(5 × T
BIT
)
24
24
MHz
MHz pF ms
See crystal manufacturer’s specification sheet
11.0592 MHz crystal, using 33 pF load capacitors
LSB
LSB
μs ms ms Using 16 pF load capacitors
CMOS levels
section
From 2.3 V to 3.6 V, T
A
= 25°C
From 2.3 V to 3.6 V, T
A
= 25°C
C
REG
= 100 nF
See
for more details
Time to synchronized data out, includes AGC settling; see the
AGC Information and Timing section
LOGIC INPUTS
Input High Voltage, V
INH
0.7
VDD
Input Low Voltage, V
INL
V
VDD
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
Control Clock Input
LOGIC OUTPUTS
Output High Voltage, V
OH
DVDD
0.4
Output Low Voltage, V
OL
CLK
OUT
Rise/Fall
CLK
OUT
Load
50
TEMPERATURE RANGE, T
POWER SUPPLIES
−20 dBm
−10 dBm
0 dBm
A
Voltage Supply
VDD
Transmit Current Consumption
−40
2.3
14.8
15.9
19.1
MHz
V I
OH
= 500 μA
5
10
+85 °C
V = 500 μA ns pF
3.6 V mA mA mA
All VDD pins must be tied together
FRF = 915 MHz, VDD = 3.0 V,
PA is matched to 50 Ω
Combined PA and LNA matching network as on
EVAL-ADF7020DBZx boards
VCO_BIAS_SETTING = 12
10 dBm
10 dBm
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
28.5
26.8
19
21 mA mA mA mA
PA matched separately with external antenna switch, VCO_BIAS_SETTING = 12
Low Power Sleep Mode 0.1 1 μA
1
Higher data rates are achievable, depending on local regulations.
2
For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3 For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4 Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5
For matching details, see the LNA/PA Matching section and the AN-764 Application Note.
6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
7 See Table 5 for a description of different receiver modes.
8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. C | Page 7 of 48
ADF7020
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, VGND = 0 V, T
A
= 25°C, unless otherwise noted. Guaranteed by design, not production tested.
Table 2.
Parameter Limit
MAX
Test
t
1
>10 ns SDATA to SCLK setup time t
5 t
6 t
8 t
9 t
2 t
3 t
4 t
10
>10
>25
>25
>10
>20
<25
<25
>10 ns ns ns ns ns ns ns ns
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
SCLK to SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK to SLE disable time, readback
TIMING DIAGRAMS
t
3 t
4
SCLK t
1 t
2
SDATA DB31 (MSB) DB30 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1) t
6
SLE t
5
Figure 2. Serial Interface Timing Diagram
t
1 t
2
SCLK
SDATA
R7_DB0
(CONTROL BIT C1)
SLE t
3
SREAD t
8
X RV16 RV15 t
9
Figure 3. Readback Timing Diagram
RV2 t
10
RV1
Rev. C | Page 8 of 48
±1 × DATA RATE/32 1/DATA RATE
RxCLK
RxDATA
DATA
Figure 4. RxData/RxCLK Timing Diagram
1/DATA RATE
TxCLK
TxDATA
DATA
FETCH SAMPLE
NOTES
1. TxCLK ONLY AVAILABLE IN GFSK MODE.
Figure 5. TxData/TxCLK Timing Diagram
ADF7020
Rev. C | Page 9 of 48
ADF7020
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Table 3.
Parameter Rating
VDD to GND
Analog I/O Voltage to GND
−0.3 V to +5 V
−0.3 V to AVDD + 0.3 V other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V maximum rating conditions for extended periods may affect
Operating Temperature Range device reliability.
Industrial (B Version) −40°C to +85°C
This device is a high performance RF integrated circuit with an
Storage Temperature Range −65°C to +125°C
ESD rating of <2 kV, and is ESD sensitive. Proper precautions
Maximum Junction Temperature 150°C should be taken for handling and assembly.
MLF θ
JA
Thermal Impedance 26°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1 GND = GND1 = RFGND = GND4 = VCO GND = 0 V.
ESD CAUTION
Rev. C | Page 10 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF7020
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
LNA
VDD4
RSET 10
CREG4 11
8
9
GND4 12
5
6
7
3
4
1
2
PIN 1
INDICATOR
ADF7020
TOP VIEW
(Not to Scale)
36 CLKOUT
35 DATA CLK
34 DATA I/O
33 INT/LOCK
32 VDD2
31 CREG2
30 ADCIN
29 GND2
28 SCLK
27
SREAD
26
SDATA
25 SLE
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
Mnemonic
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
LNA
VDD4
RSET
CREG4
12
13 to 18
GND4
MIX_I, MIX_I,
MIX_Q, MIX_Q,
FILT_I, FILT_I
19, 22 GND4
20, 21, 23 FILT_Q, FILT_Q,
TEST_A
24 CE
25
26
SLE
SDATA
Description
The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection.
Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together.
The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The
section.
Ground for Output Stage of Transmitter. All GND pins should be tied together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
Complementary LNA Input. See the LNA/PA Matching section.
External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed once CE is brought high.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the fourteen latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input.
Rev. C | Page 11 of 48
ADF7020
Pin No. Mnemonic Description
27
28
29
30
31
32
33
SREAD
SCLK
GND2
ADCIN
CREG2
VDD2
INT/LOCK
Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The
SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Ground for Digital Section.
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin.
Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin.
Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked,
NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay.
34
35
36
48
DATA I/O
DATA CLK
CLKOUT
Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.
In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data
from the microcontroller into the transmit section at the exact required data rate. See the Gaussian
Frequency Shift Keying (GFSK) section.
A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 markspace ratio.
37 MUXOUT This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator.
38
39
40
OSC2
OSC1
VDD3
The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator.
The reference crystal should be connected between this pin and OSC2.
Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a
0.01 μF capacitor.
41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection.
42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO.
43
44 to 47
VDD
GND, GND1,
VCO GND
Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor.
Grounds for VCO Block.
CVCO A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
Rev. C | Page 12 of 48
TYPICAL PERFORMANCE CHARACTERISTICS
CARRIER POWER –0.28dBm
ATTEN 0.00dB
MKR1
REF –70.00dBc/Hz
10.00
dB/DIV
1
10.0000kHz
–87.80dBc/Hz
REF 10dBm
PEAK log
10dB/DIV
1
ATTEN 20dB
3
4
REF LEVEL
10.00dBm
ADF7020
MKR4 3.482GHz
SWEEP 16.52ms (601pts)
1kHz FREQUENCY OFFSET 10MHz
Figure 7. Phase Noise Response at 868.3 MHz, VDD = 3.0 V, ICP = 1.5 mA
30
40
10
20
PRBS PN9
DR = 7.1kbps
FDEV = 4.88kHz
RBW = 300kHz
FSK
50
60
GFSK
70
913.28
913.30
913.32
FREQUENCY (MHz)
913.36
913.38
Figure 8. Output Spectrum in FSK and GFSK Modulation
0
–5
–10
–15
–20
–25
–30
–35
200kHz FILTER BW
–40
–45
–50
–55
–60
–65
150kHz FILTER BW
100kHz FILTER BW
–70
–400 –300 –200 –100
–350 –250 –150 –50
0
50
100 200 300 400 500
150 250 350 450 550
600
IF FREQ (kHz)
Figure 9. IF Filter Response
START 100MHz
RES BW 3MHz VBW 3MHz
STOP 10.000GHz
SWEEP 16.52ms (601pts)
Figure 10. Harmonic Response, RF
OUT
Matched to 50 Ω, No Filter
ATTEN 30dB
Mkr1 1.834GHz
–62.57dB
NORM log
10dB/DIV
REF 15dBm
1R
LgAv
W1 S2
S3 FC
AA
£(f):
FTun
Swp
MARKER
1.834000000GHz
–62.57dB
1
START 800MHz
#RES BW 30kHz
VBW 30kHz
STOP 5.000GHz
SWEEP 5.627s (601pts)
Figure 11. Harmonic Response, Murata Dielectric Filter
–10
–20
10
0
–30
ASK
OOK
–40
–50
899.60
899.80
GOOK
900.00
900.20
900.40
FREQUENCY (MHz)
900.60
900.80
Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps
Rev. C | Page 13 of 48
ADF7020
20
15
10
5
0
11µA
9µA
5µA
7µA
–5
–10
–15
–20
–25
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61
PA SETTING
Figure 13. PA Output Power vs. Setting
40
30
20
10
0
–10
80
70
60
50
FREQUENCY OF INTERFERER (MHz)
Figure 14. Wideband Interference Rejection; Wanted Signal (880 MHz) at 3 dB above Sensitivity Point
Interferer = FM Jammer (9.76 kbps, 10 kHz Deviation)
–20
–40
–60
–80
–100
20
0
ACTUAL INPUT LEVEL
RSSI READBACK LEVEL
–120
–120 –100 –80 –60 –40
RF INPUT (dB)
–20 0
Figure 15. Digital RSSI Readback Linearity
20
Rev. C | Page 14 of 48
–6
–7
–8
–2
–3
0
–1
–4
–5
3.6V, –40°C
3.0V, +25°C
DATA RATE = 1kbps FSK
IF BW = 100kHz
DEMOD BW = 0.77kHz
2.4V, +85°C
RF INPUT LEVEL (dBm)
Figure 16. BER vs. VDD and Temperature
–5
–6
–7
–8
0
–1
–2
–3
–4
1.002k
DATA RATE
9.760k
DATA RATE
200.8k
DATA RATE
RF INPUT LEVEL (dBm)
Figure 17. BER vs. Data Rate (Combined Matching Network)
Separate LNA and PA Matching Paths Typically
Improve Performance by 2 dB
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
LINEAR AFC OFF
CORRELATOR
AFC ON
CORRELATOR
AFC OFF
LINEAR AFC ON
FREQUENCY ERROR (kHz)
Figure 18. Sensitivity vs. Frequency Error with AFC On/Off
FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 19) can use
an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency
control (see the AFC section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low.
OSC1 OSC2
CP2 CP1
Figure 19. Oscillator Circuit on the ADF7020
Two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 20 pF. PCB track capacitance values might vary from 2 pF to 5 pF, depending on board layout. Thus, CP1 and CP2 can be calculated using:
C
L
=
1
1
CP 1
+
1
CP2
+
C
PCB
Where possible, choose capacitors that have a low temperature coefficient to ensure stable frequency operation over all conditions.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 19, and supplies a divided-
down 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in
R1_DB[8:11]. On power-up, the CLKOUT defaults to divide-by-8.
DV
DD
CLKOUT
ENABLE BIT
OSC1
DIVIDER
1 TO 15
÷2 CLKOUT
Figure 20. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 Ω) can be used to slow the clock edges to reduce these spurs at f
CLK
.
Rev. C | Page 15 of 48
ADF7020
R Counter
The 3-bit R counter divides the reference input frequency by an integer ranging from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector
(PFD). The divide ratio is set in Register 1. Maximizing the
PFD frequency reduces the N value. Every doubling of the PFD gives a 3 dB benefit in phase noise, as well as reducing occurrences of spurious components. The R register defaults to
R = 1 on power-up.
PFD [Hz] = XTAL/R
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB[29:31].
Regulator Ready
Regulator ready is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 μs. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7020 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7020 can begin.
DV
DD
REGULATOR READY
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
PLL TEST MODES
- TEST MODES
MUX CONTROL MUXOUT
DGND
Figure 21. MUXOUT Circuit
Digital Lock Detect
Digital lock detect is active high. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock detect, it is more widely used than analog lock detect.
Analog Lock Detect
This N-channel open-drain lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low going pulses.
ADF7020
Voltage Regulators
The ADF7020 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between
CREGx and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 μA, and erases all values held in the registers. The serial interface operates off a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (CREG4) can be monitored using the regulator ready signal from MUXOUT.
Loop Filter
The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 22.
CHARGE
PUMP OUT
VCO
Figure 22. Typical Loop Filter Configuration
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately one and a half times the data rate.
Widening the LBW excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation.
For ASK systems, a wider LBW is recommended. The sudden large transition between two power levels can result in VCO pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the amount of VCO pulling is reduced, because the loop settles quickly back to the correct frequency. The wider LBW can restrict the output power and data rate of ASK-based systems compared with FSK-based systems.
Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical to obtaining accurate FSK/GFSK modulation.
For GFSK, it is recommended that an LBW of 1.0 to 1.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. The free design tool ADI SRD Design Studio™ can be used to design loop filters for the ADF7020. It can also be used to view the effect of loop filter bandwidth on the spectrum of the transmitted signal for different combinations of modulation type, data rates, and modulation indices.
N Counter
The feedback divider in the ADF7020 PLL consists of an 8-bit integer counter and a 15-bit Σ-Δ fractional-N divider. The integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 31. The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as f
OUT
=
PFD
×
⎝
⎜
⎛
Integer _ N
+
Fractional _ N
2
15 ⎠
⎟
⎞
REFERENCE IN
4÷R
PFD/
CHARGE
PUMP
VCO
4÷N
THIRD-ORDER
- MODULATOR
FRACTIONAL-N INTEGER-N
Figure 23. Fractional-N PLL
The maximum N divide value is the combination of the
Integer_N (maximum = 255) and the Fractional_N (maximum
= 32767/32768) and puts a lower limit on the minimum usable PFD.
PFD
MIN
[Hz] = Maximum Required Output Frequency/(255 + 1)
For example, when operating in the European 868 MHz to
870 MHz band, PFD
MIN
equals 3.4 MHz. In the majority of cases, it is advisable to use as high a value of PFD as possible to obtain best phase noise performance.
Voltage Controlled Oscillator (VCO)
To minimize spurious emissions, the on-chip VCO operates from 1724 MHz to 1912 MHz. The VCO signal is then divided by 2 to give the required frequency for the transmitter and the required LO frequency for the receiver.
The VCO should be recentered, depending on the required frequency of operation, by programming the VCO Adjust Bits
R1_DB[20:21].
The VCO is enabled as part of the PLL by the PLL Enable bit,
R0_DB28.
A further frequency divide-by-2 block is included to allow operation in the lower 433 MHz and 460 MHz bands. To enable operation in these bands, R1_DB13 should be set to 1. The
VCO needs an external 22 nF between the VCO and the regulator to reduce internal noise.
Rev. C | Page 16 of 48
VCO Bias Current
VCO bias current can be adjusted using Bit R1_DB19 to
Bit R1_DB16. To ensure VCO oscillation, the minimum bias current setting under all conditions is 0xA.
VCO BIAS
R1_DB[16:19]
÷2
TO N
DIVIDER
LOOP FILTER
VCO
220µF
CVCO PIN
÷2
MUX TO PA
VCO SELECT BIT
Figure 24. Voltage-Controlled Oscillator (VCO)
ADF7020
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
The fractional-N PLL allows the selection of any channel within
868 MHz to 956 MHz (and 433 MHz using divide-by-2) to a resolution of <300 Hz. This also facilitates frequency-hopping systems.
Careful selection of the XTAL frequency is important to achieve best spurious and blocking performance. The architecture of fractional-N causes some level of the nearest integer channel to couple directly to the RF output. This phenomenon is often referred to as integer boundary spurious. If the desired RF channel and the nearest integer channel are separated by a frequency of less than the PLL loop bandwidth (LBW), the integer boundary spurs are not attenuated by the loop.
Integer boundary spurs can be significantly reduced in amplitude by choosing XTAL values that place the wanted RF channel away from integer multiples of the PFD.
Rev. C | Page 17 of 48
ADF7020
TRANSMITTER
RF OUTPUT STAGE
The PA of the ADF7020 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of
956 MHz.
The PA output current and, consequently, the output power are programmable over a wide range. The PA configurations in
FSK/GFSK and ASK/OOK modulation modes are shown in
Figure 25 and Figure 26, respectively. In FSK/GFSK modulation
mode, the output power is independent of the state of the
DATA I/O pin. In ASK/OOK modulation mode, it is dependent on the state of the DATA I/O pin and Bit R2_DB29, which selects the polarity of the TxData input. For each transmission mode, the output power can be adjusted as follows:
• FSK/GFSK
The output power is set using Bits R2_DB[9:14].
• ASK
The output power for the inactive state of the TxData input is set by Bits R2_DB[15:20]. The output power for the active state of the TxData input is set by Bits R2_DB[9:14].
• OOK
The output power for the active state of the TxData input is set by Bits R2_DB[9:14]. The PA is muted when the TxData input is inactive.
R2_DB[30:31]
2
6
R2_DB[9:14] IDAC
RFOUT
+
R2_DB4
R2_DB5
DIGITAL
LOCK DETECT
RFGND
FROM VCO
Figure 25. PA Configuration in FSK/GFSK Mode
DATA I/O
RFOUT
RFGND
ASK/OOK MODE
R2_DB29
R2_DB[30:31]
+
IDAC
6
6
R2_DB[9:14]
6
R2_DB[15:23]
0
R2_DB4
R2_DB5
DIGITAL
LOCK DETECT
FROM VCO
Figure 26. PA Configuration in ASK/OOK Mode
Rev. C | Page 18 of 48
The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, one can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or mono-
pole antennas. See the LNA/PA Matching section for details.
PA Bias Currents
Control Bits R2_DB[30:31] facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of
7 μA is recommended. The output stage is powered down by resetting Bit R2_DB4. To reduce the level of undesired spurious emissions, the PA can be muted during the PLL lock phase by toggling this bit.
MODULATION SCHEMES
Frequency Shift Keying (FSK)
Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxData line. The deviation from the center frequency is set using
Bits R2_DB[15:23]. The deviation from the center frequency in Hz is
FSK
DEVIATION
[ Hz ]
=
PFD
×
Modulation Number
2
14 where Modulation Number is a number from 1 to 511
(R2_DB[15:23]).
Select FSK using Bits R2_DB[6:8].
4R
PFD/
CHARGE
PUMP
FSK DEVIATION
FREQUENCY
– f
DEV
+ f
DEV
TxDATA
THIRD-ORDER
- MODULATOR
VCO
PA STAGE
÷N
FRACTIONAL-N INTEGER-N
Figure 27. FSK Implementation
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the
TxData. A TxCLK output line is provided from the ADF7020 for synchronization of TxData from the microcontroller.
The TxCLK line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate.
Setting Up the ADF7020 for GFSK
To set up the frequency deviation, set the PFD and the modulation control bits.
GFSK
DEVIATION
[ Hz ]
=
PFD
×
2 m
2
12 where m is GFSK_Mod_Control, set using R2_DB[24:26].
To set up the GFSK data rate,
DR [ bps ]
=
DIVIDER _
PFD
FACTOR
×
INDEX _ COUNTER
The INDEX_COUNTER variable controls the number of intermediate frequency steps between the low and high frequency.
It is usually possible to achieve a given data rate with various combinations of DIVIDER_FACTOR and INDEX_COUNTER.
Choosing a higher INDEX_COUNTER can help in improving the spectral performance.
ADF7020
Amplitude Shift Keying (ASK)
Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2. A 0 TxData bit sends
Bits R2_DB[15:20] to the DAC. A high TxData bit sends
Bits R2_DB[9:14] to the DAC. A maximum modulation depth of 30 dB is possible.
On-Off Keying (OOK)
On-off keying is implemented by switching the output stage to a certain power level for a high TxData bit and switching the output stage off for a zero. For OOK, the transmitted power for a high input is programmed using Bits R2_DB[9:14].
Gaussian On-Off Keying (GOOK)
Gaussian on-off keying represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian filtered transitions, the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired
BW, especially if it is not possible to increase the loop filter
BW > 300 kHz. The GOOK sampling clock samples data at the
data rate (see the Setting Up the ADF7020 for GFSK section).
Rev. C | Page 19 of 48
ADF7020
RECEIVER
RF FRONT END
The ADF7020 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power lineinduced interference problems.
Figure 28 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity, linearity, and current consumption against each other in the way best suitable for their applications. To achieve a high level of resilience against spurious reception, the LNA features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the
LNA/PA Matching section for details on the design of the
matching network.
I (TO FILTER)
Tx/Rx SELECT
(R0_DB27)
RFIN
RFINB
SW2 LNA LO
Q (TO FILTER)
LNA MODE
(R6_DB15)
LNA CURRENT
(R6_DB[16:17])
LNA GAIN
(R9_DB[20:21])
LNA/MIXER ENABLE
(R8_DB6)
Figure 28. ADF7020 RF Front End
MIXER LINEARITY
(R6_DB18)
The LNA is followed by a quadrature down conversion mixer, that converts the RF signal to the IF frequency of 200 kHz.
It is important to consider that the output frequency of the synthesizer must be programmed to a value 200 kHz below the center frequency of the received channel.
The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA_Mode bit, R6_DB15. The mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, R6_DB18.
Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits
LNA_Mode (R6_DB15) and Mixer_Linearity (R6_DB18), as
The gain of the LNA is configured by the LNA_Gain field,
R9_DB[20:21], and can be set by either the user or the automatic gain control (AGC) logic.
IF Filter Settings/Calibration
Out-of-band interference is rejected by means of a fourth-order
Butterworth polyphase IF filter centered around a frequency of
200 kHz. The bandwidth of the IF filter can be programmed between 100 kHz and 200 kHz by using Control Bits R1_DB[22:23] and should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range.
To compensate for manufacturing tolerances, the IF filter should be calibrated once after power-up. The IF filter calibration logic requires that the IF filter divider in Bits R6_DB[20:28] be set as dependent on the crystal frequency. Once initiated by setting Bit R6_DB19, the calibration is performed automatically without any user intervention. The calibration time is 200 μs, during which the ADF7020 should not be accessed. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of IF filter can be set to three levels using the
Filter_Gain field, R9_DB[20:21]. The filter gain is adjusted automatically, if the AGC loop is enabled.
Table 5. LNA/Mixer Modes
Receiver Mode
LNA Mode
(R6_DB15)
High Sensitivity Mode (Default) 0
LNA Gain Value
(R9_DB[20:21])
30
Mixer
Linearity
(R6_DB18)
0
Sensitivity
(DR = 9.6 kbps, f
DEV
= 10 kHz)
−110.5
Rx Current
Consumption
(mA)
21
Input IP3
(dBm)
−24
Low Current Mode
Enhanced Linearity Mode
1
1
3
3
0
1
−94
−88
19
19
−5
−3
Rev. C | Page 20 of 48
RSSI/AGC
The RSSI is implemented as a successive compression log amp following the baseband channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The RSSI itself is used for amplitude shift keying (ASK) demodulation. In ASK mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the baseband offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm.
OFFSET
CORRECTION
FSK
DEMOD
1 A A A LATCH
FWR FWR FWR FWR CLK
ADC
RSSI
ASK
DEMOD
R
NOTES
1. FWR = FULL WAVE RECTIFIER
Figure 29. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD, the gain is increased. A delay (AGC_DELAY) is programmed to allow for settling of the loop. The user programs the two threshold values (recommended defaults of 30 and 70) and the delay (default of 10). The default AGC setup values should be adequate for most applications. The threshold values must be chosen to be more than 30 apart for the AGC to operate correctly.
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits
R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz.
BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) where BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information and Timing
AGC is selected by default, and operates by selecting the appropriate LNA and filter gain settings for the measured RSSI level. It is possible to disable AGC by writing to Register 9 if entering
one of the modes listed in Table 5 is desired, for example. The
time for the AGC circuit to settle and, therefore, the time to take an accurate RSSI measurement is typically 150 μs, although this depends on how many gain settings the AGC circuit has to cycle through. After each gain change, the AGC loop waits for a programmed time to allow transients to settle.
ADF7020
This wait time can be adjusted to speed up this settling by adjusting the appropriate parameters.
AGC _ Wait _ Time
=
AGC _ DELAY
×
SEQ _ CLK
XTAL
AGC Settling = AGC_Wait_Time × Number of Gain Changes
Thus, in the worst case, if the AGC loop has to go through all
5 gain changes, AGC_Delay =10, SEQ_CLK = 200 kHz, AGC
Settling = 10 × 5 μs × 5 = 250 μs. Minimum AGC_Wait_Time needs to be at least 25 μs.
RSSI Formula (Converting to dBm)
Input_Power [dBm] = −120 dBm + (Readback_Code +
Gain_Mode_Correction ) × 0.5 where:
Readback_Code is given by Bit RV7 to Bit RV1 in the readback
register (see the Readback Format section).
Gain_Mode_Correction
is given by the values in Table 6.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained from the readback register.
Table 6. Gain Mode Correction
LNA Gain
(LG2, LG1)
H (1,1)
M (1,0)
M (1,0)
M (1,0)
L (0,1)
EL (0,0)
Filter Gain
(FG2, FG1)
H (1,0)
H (1,0)
M (0,1)
L (0,0)
L (0,0)
L (0,0)
Gain Mode Correction
0
24
45
63
90
105
An additional factor should be introduced to account for losses in the front-end matching network/antenna.
FSK DEMODULATORS ON THE ADF7020
The two FSK demodulators on the ADF7020 are
• FSK correlator/demodulator
• Linear demodulator
Select these using the demodulator select bits, R4_DB[4:5].
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + f
DEV
) and
(IF − f
DEV
). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white Gaussian noise (AWGN).
Rev. C | Page 21 of 48
ADF7020
FREQUENCY CORRELATOR
IF
I
SLICER
RxDATA
LIMITERS
Q
RxCLK
IF – f
DEV
IF + f
DEV
0
R6_DB[4:13] R6_DB[14]
R3_DB[8:15]
Figure 30. FSK Correlator/Demodulator Block Diagram
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator.
The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver’s performance. Typically, the 3 dB bandwidth of this filter is set at approximately 0.75 times the user’s data rate, using Bits R4_DB[6:15].
Bit Slicer
The received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. In the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on 0. Therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in the more traditional FSK demodulators.
Frequency errors are removed by an internal AFC loop that measures the average IF frequency at the limiter output and applies a frequency correction value to the fractional-N synthesizer. This loop should be activated when the frequency errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC section).
Data Synchronizer
An oversampled digital PLL is used to resynchronize the received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the Register 3—Receiver Clock Register Comments section
for a definition of how to program. The clock recovery PLL can accommodate frequency errors of up to ±2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB[5:4] should be set to 01. To achieve best performance, the bandwidth of the
FSK correlator must be optimized for the specific deviation frequency that is used by the FSK transmitter.
The discriminator BW is controlled in Register 6 by
Bit R6_DB[4:13] and is defined as
Discrimina tor _ BW
=
DEMOD _ CLK
800
×
10
3
×
K where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, second comment.
K = Round(200 × 10
3
/FSK Deviation)
To optimize the coefficients of the FSK correlator, two additional bits, R6_DB14 and R6_DB29, must be assigned. The value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 7. When K Is Even
Even Even 0 0
Even Odd 0 1
Table 8. When K Is Odd
K (K + 1)/2 R6_DB14 R6_DB29
Odd Even 1 0
Odd Odd 1 1
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_DB[6:15] and is given by
Postdemod_BW_Setting
=
2
10
×
2 π
× f
CUTOFF
DEMOD _ CLK where f
CUTOFF
is the target 3 dB bandwidth in Hz of the postdemodulator filter. This should typically be set to 0.75 times the data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 5 MHz
DR = 9.6 kbps f
DEV
= 20 kHz
Therefore, f
CUTOFF
= 0.75 × 9.6 × 10
3
Hz
Postdemod_BW_Setting = 2
11
π 7.2 × 10
3
Hz/(5 MHz)
Postdemod_BW_Setting = Round(9.26) = 9 and
K = Round(200 kHz)/20 kHz) = 10
Discriminator_BW = (5 MHz × 10)/(800 × 10
3
) = 62.5 = 63
(rounded to the nearest integer)
Rev. C | Page 22 of 48
Setting Name Register Address
Postdemod_BW_Setting R4_DB[6:15]
1
The latest version of the ADF7020 configuration software can aid in calculating register settings.
LINEAR FSK DEMODULATOR
Figure 31 shows a block diagram of the linear FSK demodulator.
MUX 1 SLICER
ADC RSSI OUTPUT 7
LEVEL
RxDATA
I
IF
LIMITER
Q
FREQUENCY
LINEAR DISCRIMINATOR
FREQUENCY
READBACK
AND
AFC LOOP
R4_DB[6:15]
Figure 31. Block Diagram of Frequency Measurement System and
ASK/OOK/Linear FSK Demodulator
This method of frequency demodulation is useful when very short preamble length is required, and the system protocol cannot support the overhead of the settling time of the internal feedback AFC loop settling.
A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodulated FSK data is recovered by threshold-detecting the output of
PLL for clock synchronization. To enable the linear FSK demodulator, set Bits R4_DB[4:5] to 00.
The 3 dB bandwidth of the postdemodulation filter is set in the same way as the FSK correlator/demodulator, which is set in
R4_DB[6:15] and is defined as
Postdemod _ BW _ Setting
=
2
10
×
2
π × f
CUTOFF
DEMOD _ CLK where f
CUTOFF
is the target 3 dB bandwidth in Hz of the postdemodulator filter. DEMOD_CLK is as defined in the
Register 3—Receiver Clock Register section, second comment.
ADF7020
Value
0x09
ASK/OOK Operation
ASK/OOK demodulation is activated by setting Bits R4_DB[4:5] to 10.
Digital filtering and envelope detecting the digitized RSSI input
via MUX 1, as shown in Figure 31, performs ASK/OOK
demodulation. The bandwidth of the digital filter must be optimized to remove any excess noise without causing ISI in the received ASK/OOK signal.
The 3 dB bandwidth of this filter is typically set at approximately
0.75 times the user data rate and is assigned by R4 _DB[6:15] as
Postdemod _ BW _ Setting
=
2
10
×
2
π × f
CUTOFF
DEMOD _ CLK where f
CUTOFF
is the target 3 dB bandwidth in Hz of the postdemodulator filter.
It is also recommended to adjust the peak response factor to 6 in Register 10 for robust operation over the full input range.
This improves the receiver’s AM immunity performance.
AFC
The ADF7020 supports a real-time AFC loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. This uses the frequency
averaged to remove the FSK frequency modulation, using a combined averaging filter and envelope detector. In FSK mode, the output of the envelope detector provides an estimate of the average IF frequency.
Two methods of AFC, external and internal, are supported on the ADF7020 (in FSK mode only).
External AFC
The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to the fractional-N synthesizer’s N divider.
The frequency information is obtained by reading the 16-bit
signed AFC_READBACK, as described in the Readback Format
section, and applying the following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2 15
Note that while the AFC_READBACK value is a signed number, under normal operating conditions, it is positive. The frequency error can be calculated from
FREQ_Error [Hz] = FREQ_RB (Hz) − 200 kHz
Thus, in the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz.
Rev. C | Page 23 of 48
ADF7020
Internal AFC
The ADF7020 supports a real-time internal automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer N divider using an internal PI control loop.
The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
R11_DB20 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in
Bits R11_DB[4:19] and should be calculated using
AFC_Scaling_Coefficient = (500 × 2
24
)/XTAL
Therefore, using a 10 MHz XTAL yields an AFC scaling coefficient of 839.
AFC Performance
The improved sensitivity performance of the Rx when AFC is enabled and in the presence of frequency errors is shown in
Figure 18. The maximum AFC frequency range is ±50 kHz,
which corresponds to ±58 ppm at 868 MHz. This is the total error tolerance allowed in the link. For example, in a point-topoint system, AFC can compensate for two ±29 ppm crystals or one ±50 ppm crystal and one ±8 ppm TCXO.
AFC settling typically takes 48 bits to settle within ±1 kHz. This can be improved by increasing the postdemodulator bandwidth in Register 4 at the expense of Rx sensitivity.
When AFC errors have been removed using either the internal or external AFC, further improvement in the receiver’s sensitivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB[22:23].
AUTOMATIC SYNC WORD RECOGNITION
The ADF7020 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7020. In receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7020.
This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically deasserted again after nine data clock cycles.
The automatic sync/ID word detection feature is enabled by selecting Demodulator Mode 2 or Demodulator Mode 3 in the demodulator setup register. Do this by setting Bits R4_DB[25:23] =
010 or 011. Bits R5_DB[4:5] are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the
LSB last to ensure proper alignment in the receiver sync byte detection hardware.
For systems using forward error correction (FEC), an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in Bits R5_DB[6:7].
Rev. C | Page 24 of 48
APPLICATIONS INFORMATION
LNA/PA MATCHING
The ADF7020 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its
RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7020 is equipped with an internal Rx/Tx switch that facilitates the use of a simple combined passive PA/LNA matching network.
Alternatively, an external Rx/Tx switch, such as the Analog
Devices ADG919 , can be used. It yields a slightly improved receiver sensitivity and lower transmitter power consumption.
External Rx/Tx Switch
Figure 32 shows a configuration using an external Rx/Tx switch.
This configuration allows an independent optimization of the matching and filter network in the transmit and receive path and is, therefore, more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, while C1 blocks dc current. Both elements, L1 and C1, also form the matching network, which transforms the source impedance into the optimum PA load impedance, Z
OPT
_PA.
V
BAT
ANTENNA
L1
OPTIONAL
LPF
C1
PA_OUT
OPTIONAL
BPF
(SAW)
C
A
Z
OPT
_PA
Z
IN
_RFIN
L
A
RFIN
RFINB
LNA
PA
ADG919
Z
IN
_RFIN
C
B
Rx/Tx – SELECT
ADF7020
Figure 32. ADF7020 with External Rx/Tx Switch
Z
OPT
_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate Z
OPT
_PA helps to minimize the Tx current consumption in the application. Application Note AN-767 contains a number of
Z
OPT
_PA values for representative conditions. Under certain conditions, however, it is recommended that a suitable Z
OPT
_PA value be obtained by means of a load-pull measurement.
Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended-to-differential conversion and a complex conjugate impedance match. The network with the lowest component count that can satisfy these
requirements is the configuration shown in Figure 32, which
consists of two capacitors and one inductor.
ADF7020
A first-order implementation of the matching network can be obtained by understanding the arrangement as two L type matching networks in a back-to-back configuration. Due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established.
The use of appropriate CAD software is strongly recommended for this optimization.
Depending on the antenna configuration, the user may need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC pi or T-stage filter. Dielectric low-pass filter components, such as the LFL18924MTC1A052 (for operation in the
915 MHz and 868 MHz band) by Murata Manufacturing, Co.,
Ltd., represent an attractive alternative to discrete designs.
AN-917 describes how to replace the Murata dielectric filter with an LC filter if desired.
The immunity of the ADF7020 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path.
Apart from discrete designs, SAW or dielectric filter components, such as the SAFCH869MAM0T00 or SAFCH915MAL0N00, both by Murata, are well suited for this purpose. Alternatively, the ADF7020 blocking performance can be improved by
selecting the high linearity mode, as described in Table 5.
Internal Rx/Tx Switch
Figure 33 shows the ADF7020 in a configuration where the
internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the
ADF7020-XDBX evaluation boards. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration.
V
BAT
L1
C1
PA_OUT
PA
ANTENNA
OPTIONAL
BPF OR LPF
C
A
Z
OPT
_PA
Z
IN
_RFIN
RFIN
L
A
LNA
RFINB
Z
IN
_RFIN
C
B
ADF7020
Figure 33. ADF7020 with Internal Rx/Tx Switch
Rev. C | Page 25 of 48
ADF7020
The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7020 is critically dependent on the availability of an accurate electrical model for the PC board. In this context, the use of a suitable
CAD package is strongly recommended. To avoid this effort, however, a small form-factor reference design for the ADF7020 is provided, including matching and harmonic filter components.
Gerber files and schematics are available at www.analog.com
.
IMAGE REJECTION CALIBRATION
The image channel in the ADF7020 is 400 kHz below the desired signal. The polyphase filter rejects this image with an asymmetric frequency response. The image rejection performance of the receiver is dependent on how well matched the I and Q signals are in amplitude, and how well matched the quadrature is between them (that is, how close to 90º apart they are.) The uncalibrated image rejection performance is approximately 30 dB. However, it is possible to improve this performance by as much as 20 dB by finding the optimum I/Q gain and phase adjust settings.
EXTERNAL
SIGNAL
SOURCE
RFIN
MATCHING
RFINB
LNA
Calibration Procedure and Setup
The image rejection calibration works by connecting an external RF signal to the RF input port. The external RF signal should be set at the image frequency and the filter rejection measured by monitoring the digital RSSI readback. As the image rejection is improved by adjusting the I/Q Gain and phase, the RSSI reading reduces.
The magnitude of the phase adjust is set by using the IR_PHASE_
ADJUST bits (R10_DB[24:27]). This correction can be applied to either the I channel or Q channel, by toggling bit (R10_DB28).
The magnitude of the I/Q gain is adjusted by the IR_GAIN_
ADJUST bits (R10_DB[16:20]). This correction can be applied to either the I or Q channel using bit (R10_DB22), while the
GAIN/ATTENUATE bit (R10_DB21) sets whether the gain adjustment defines a gain or attenuation adjust.
The calibration results are valid over changes in the ADF7020 supply voltage. However, there is some variation with temperature.
A typical plot of variation in image rejection over temperature after initial calibrations at +25°C, −40°C, and +85°C is shown in
Figure 35. The internal temperature sensor on the ADF7020 can
be used to determine if a new IR calibration is required.
ADF7020
POLYPHASE
IF FILTER
RSSI/
LOG AMP
7-BIT ADC
PHASE ADJUSTMENT
I
FROM LO
Q
SERIAL
INTERFACE
4
PHASE ADJUST
REGISTER 10
GAIN ADJUST
REGISTER 10
4
RSSI READBACK
MICROCONTROLLER
I/Q GAIN/PHASE ADJUST AND
RSSI MEASUREMENT
ALGORITHM
Figure 34. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller
Rev. C | Page 26 of 48
60
50
CAL AT +25°C
40
CAL AT +85°C
CAL AT –40°C
30
20
10
V
DD
= 3.0V
IF BW = 25kHz
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
0
–60 f
PRBS9
DEV
= 4kHz
LEVEL= –100dBm
–40 –20 0
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
PRBS11 f
DEV
= 4kHz
20 40
TEMPERATURE (°C)
60 80 100
Figure 35. Image Rejection Variation with Temperature after Initial
Calibrations at +25°C, −40°C, and +85°C
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
PREAMBLE
SYNC
WORD
ID
FIELD DATA FIELD CRC
Figure 36. Typical Format of a Transmit Protocol
A dc-free preamble pattern is recommended for FSK/GFSK/
ASK/OOK demodulation. The recommended preamble pattern is a dc-balanced pattern such as a 10101010… sequence.
Preamble patterns with longer run-length constraints such as
11001100… can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver.
The remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7020 can accommodate coding schemes with a run-length of up to several bytes without any performance degradation, for example several bytes of 0x00 or 0xFF. To help minimize bit errors when receiving these long runs of continuous 0s or 1s, it is important to choose a data rate and XTAL combination that minimizes the error between the actual data rate and the on-board
CDR_CLK/32. For example, if a 9.6 kbps data rate is desired, then using an 11.0592 MHz XTAL gives a 0% nominal error between the desired data rate and CDR_CLK/32. AN-915 gives more details on supporting long run lengths on the ADF7020.
The ADF7020 can also support Manchester-encoded data for the entire protocol. Manchester decoding needs to be done on the companion microcontroller, however. In this case, the
ADF7020 should be set up at the Manchester chip or baud rate, which is twice the effective data rate.
ADF7020
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
Table 10 lists the minimum number of writes needed to set up
the ADF7020 in either Tx or Rx mode after CE is brought high.
Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to write only to the N Register to alter the LO by
200 kHz and to toggle the Tx/Rx bit.
Table 10. Minimum Register Writes Required for Tx/Rx Setup
Mode Register
Tx Reg. 0
Rx (OOK) Reg. 0
Rx (G/FSK) Reg. 0
Tx Rx
Reg. 1 Reg. 2
Reg. 1 Reg. 3 Reg. 4 Reg. 6
Reg. 1 Reg. 3 Reg. 4 Reg. 6
Figure 39 and Figure 40 show the recommended programming
sequence and associated timing for power-up from standby mode.
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing the
ADF7020 to the Analog Devices ADuC84x analog microcontrollers, or the Blackfin® ADSP-BF53x DSPs, using the
hardware connections shown in Figure 37 and Figure 38.
ADuC84x
ADF7020
MISO
MOSI
SCLOCK
SS
P3.7
P3.2/INT0
GPIO
P2.4
P2.5
P2.6
P2.7
DATA I/O
DATA CLK
CE
INT/LOCK
SREAD
SLE
SDATA
SCLK
Figure 37. ADuC84x to ADF7020 Connection Diagram
ADSP-BF533
SCK
MOSI
MISO
PF5
RSCLK1
DT1PRI
DR1PRI
RFS1
PF6
V
DDEXT
GND
ADF7020
SCLK
SDATA
SREAD
SLE
DATA CLK
DATA I/O
INT/LOCK
CE
VDD
GND
Figure 38. ADSP-BF533 to ADF7020 Connection Diagram
Rev. C | Page 27 of 48
ADF7020
POWER CONSUMPTION AND BATTERY LIFETIME
CALCULATIONS
Average Power Consumption can be calculated using
Average Power Consumption = (t
ON
× I
AVG_ON
+ t
OFF
×
I
PowerDown
)/(t
ON
+ t
OFF
)
Using a sequenced power-on routine like that illustrated in
AVG_ON
current and, hence, reduce the overall power consumption. When used in conjunction with a large duty-cycle or large t
OFF
, this can result in significantly increased battery life. Analog Devices, Inc.’s free design tool,
ADI SRD Design Studio , can assist in these calculations.
19mA TO
22mA
14mA
XTAL t
0
3.65mA
2.0mA
AFC t
10
REG.
READY t
1
WR0 t
2
WR1 t
3
VCO t
4
WR3 t
5
WR4 t
6
WR6 t
7
AGC/
RSSI t
8
CDR t
9
Rx
DATA t
11
TIME t
ON
Figure 39. Rx Programming Sequence and Timing Diagram
Table 11. Power-Up Sequence Description
Parameter Value Description
t
0
2 on the crystal type and the load capacitance specified. t t
1
10 this time.
2
, t
3 t
6
, t
7
, t
5
, 32 × 1/SPI_CLK Time to write to a single register. Maximum SPI_CLK is 25 MHz. t
4
1
CVCO capacitance value used. A value of 22 nF is recommended as a trade-off between phase noise performance and power-up time. t t
8
150 through and AGC settings programmed. This is described in more detail
in the AGC Information and Timing section.
t
9
5 × Bit_Period
This is the time for the clock and data recovery circuit to settle. This typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. t
10
11
48 × Bit_Period This is the time for the automatic frequency control circuit to settle. This typically requires 48-bit transitions to acquire lock and is usually covered by an appropriate length preamble.
Packet Length Number of bits in payload by the bit period.
t
OFF
Signal to Monitor
CLKOUT pin
MUXOUT pin
CVCO pin
Analog RSSI on TEST_A pin
(Available by writing 0x3800 000C)
Rev. C | Page 28 of 48
ADF7020
15mA TO
30mA
14mA
3.65mA
2.0mA
REG.
READY t
1
WR0 t
2
WR1 t
3
XTAL + VCO t
4
WR2 t
5
TxDATA t
12 t
ON
Figure 40. Tx Programming Sequence and Timing Diagram
t
OFF
TIME
Rev. C | Page 29 of 48
ADF7020
LOOP FILTER
ANTENNA
CONNECTION
T-STAGE LC
FILTER
VDD
XTAL
REFERENCE
CVCO
CAP
VDD
MATCHING
VDD
VDD
7
8
9
5
6
3
4
1
2
10
11
12
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
LNA
VDD4
RSET
CREG4
GND4
PIN 1
INDICATOR
ADF7020
TOP VIEW
(Not to Scale)
CLKOUT
DATA CLK
DATA I/O
INT/LOCK
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
36
31
30
29
28
35
34
33
32
27
26
25
VDD
RLNA
RESISTOR
RSET
RESISTOR
Figure 41. Application Circuit
Rev. C | Page 30 of 48
SERIAL INTERFACE
The serial interface allows the user to program the fourteen
32-bit registers using a 3-wire interface (SCLK, SDATA, and
SLE). Signals should be CMOS compatible. The serial interface is powered by the regulator and, therefore, is inactive when
CE is low.
Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of fourteen latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1).
These are the bottom four LSBs, DB3 to DB0, as shown in the
READBACK FORMAT
The readback operation is initiated by writing a valid control word to the readback register and setting the readback enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin (see Figure 42), starting with the MSB first. The
data appearing at the first clock cycle following the latch operation must be ignored. The last (eighteenth) SCLK edge puts the SREAD pin back in three-state.
AFC Readback
The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer comprising Bit RV1 to Bit RV16 and is scaled according to the following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2
15
In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. Note that, for the AFC readback to yield a valid result, the down-converted input signal must not fall outside the bandwidth of the analog IF filter. At low input signal levels, the variation in the readback value can be improved by averaging.
ADF7020
RSSI Readback
The RSSI readback operation yields valid results in Rx mode with ASK or FSK signals. The format of the readback word is
shown in Figure 42. It comprises the RSSI level information
(Bit RV1 to Bit RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9. With the reception of ASK modulated signals, averaging of the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the
Battery Voltage/ADCIN/Temperature Sensor Readback
These three ADC readback values are valid by just enabling the
ADC in Register 8 without writing to the other registers. The battery voltage is measured at Pin VDD4. The readback information is contained in Bit RV1 to Bit RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery, ADCIN voltage or temperature can be obtained using
V
BATTERY
= (Battery_Voltage_Readback)/21.1
V
ADCIN
= (ADCIN_Voltage_Readback)/42.1
Temperature =
−40°C + (68.4 − Temperature_Sensor_Readback) × 9.32
Silicon Revision Readback
The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bit RV5 to Bit RV16. The revision code (RV) is coded with one quartet extending from Bit RV1 to Bit RV4. The product code for the ADF7020 should read back as PC = 0x200.
The current revision code should read as RV = 0x8.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8 and is for diagnostic purposes only. Using the automatic filter calibration function, accessible through Register 6, is recommended. Before filter calibration is initiated, decimal 32 should be read back as the default value.
READBACK MODE READBACK VALUE
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
AFC READBACK
RSSI READBACK
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9
X X X X X LG2 LG1 FG2
RV8
FG1
X X X X X X X X X
DB6 DB5
RV7
RV7
RV6
RV6
RV7 RV6
DB4
RV5
RV5
DB3
RV4
RV4
RV5 RV4
DB2 DB1
RV3
RV3
RV2
RV2
DB0
RV1
RV1
RV3 RV2 RV1
SILICON REVISION
FILTER CAL READBACK
RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9
0 0 0
RV8
0 0 0 0 0 RV8
Figure 42. Readback Value Table
RV7
RV7
RV6
RV6
RV5
RV5
RV4
RV4
RV3
RV3
RV2
RV2
RV1
RV1
Rev. C | Page 31 of 48
ADF7020
REGISTERS
REGISTER 0—N REGISTER
MUXOUT 8-BIT INTEGER-N 15-BIT FRACTIONAL-N
ADDRESS
BITS
M3
1
1
1
1
0
0
0
0
M2
1
1
0
0
1
1
0
0
M1
0
1
0
1
0
1
0
1
TR1
0
1
TRANSMIT/
RECEIVE
TRANSMIT
RECEIVE
PLE1 PLL ENABLE
0
1
PLL OFF
PLL ON
MUXOUT
REGULATOR READY (DEFAULT)
R DIVIDER OUTPUT
N DIVIDER OUTPUT
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
THREE-STATE
PLL TEST MODES
- TEST MODES
M15
1
1
1
1
0
.
.
.
0
0
M14
1
1
1
1
0
.
.
.
0
0
.
.
.
.
.
.
.
.
.
.
.
M13
1
1
1
1
0
.
.
.
0
0
M3
1
1
1
1
0
.
.
.
0
0
M2
1
1
0
0
1
.
.
.
0
0
M1
0
1
0
1
0
.
.
.
0
1
FRACTIONAL
DIVIDE RATIO
2
.
.
.
0
1
32,764
32,765
32,766
32,767
N8
.
.
0
0
.
1
1
N7
.
.
0
0
.
1
1
N6
.
.
0
1
.
1
1
N5
.
1
.
.
1
0
1
N4
.
1
.
.
1
0
1
N3
.
1
.
.
1
0
1
N2
.
0
.
.
1
0
1
N1
.
1
.
.
1
0
0
N COUNTER
DIVIDE RATIO
.
.
31
32
.
253
254
1 1 1 1 1 1 1 1 255
Figure 43. Register 0—N Register
Register 0—N Register Comments
•
The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and controls the state of the internal Tx/Rx switch.
• f
OUT
=
XTAL
×
( Integer _ N
R
+
Fractional _ N
2
15
)
•
If operating in 433 MHz band, with the VCO Band bit set, the desired frequency, f
OUT
, should be programmed to be twice the desired operating frequency, due to removal of the divide-by-2 stage in the feedback path.
Rev. C | Page 32 of 48
REGISTER 1—OSCILLATOR/FILTER REGISTER
VCO BIAS
CLOCKOUT
DIVIDE
R COUNTER
ADDRESS
BITS
ADF7020
IR2 IR1
0
0
1
1
0
1
0
1
VA2
1
1
0
0
VB4
0
.
0
0
1
VA1
0
1
0
1
FILTER
BANDWIDTH
100kHz
150kHz
200kHz
NOT USED
FREQUENCY
OF OPERATION
850 TO 920
860 TO 930
870 TO 940
880 TO 950
0
.
0
0
1
VB3 VB2
1
.
0
0
1
X1 XTAL OSC
0 OFF
1 ON
V1
0
1
VCO Band
(MHz)
862 TO 956
431 TO 478
VB1
0
.
0
1
1
VCO BIAS
CURRENT
0.125mA
0.375mA
0.625mA
3.875mA
D1
0
1
XTAL
DOUBLER
DISABLE
ENABLED
CP2
0
0
1
1
CP1
0
1
0
1
I
CP
(mA)
0.3
0.9
1.5
2.1
.
1
.
.
0
0
CL4
0
Figure 44. Register 1—Oscillator/Filter Register
.
1
.
.
0
0
CL3
0
.
.
0
.
1
R3 R2 R1
0 0 1
1
.
.
.
1
.
.
0
.
1
.
.
2
.
7
RF R COUNTER
DIVIDE RATIO
1
.
1
.
.
0
1
CL2 CL1
0 0
1
0
.
1
.
.
CLKOUT
DIVIDE RATIO
OFF
.
.
2
4
.
30
Register 1—Oscillator/Filter Register Comments
• The VCO Adjust Bits R1_DB[20:21] should be set to 0 for operation in the 862 MHz to 870 MHz band and set to 3 for operation in the 902 MHz to 928 MHz band.
• The VCO bias setting should be 0xA for operation in the 862 MHz to 870 MHz and 902 MHz to 928 MHz bands. All VCO gain numbers are specified for these VCO Adjust and Bias settings.
Rev. C | Page 33 of 48
ADF7020
REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)
GFSK MOD
CONTROL
PA BIAS MODULATION PARAMETER POWER AMPLIFIER
MODULATION
SCHEME
ADDRESS
BITS
IC2 IC1 MC3 MC2 MC1
X X X X X
DI1
0
1
TxDATA
TxDATA
PA2
1
1
0
0
PA1
0
1
0
1
PA BIAS
5µA
7µA
9µA
11µA
PE1
0
1
POWER AMPLIFIER
OFF
ON
MP1
0
1
MUTE PA UNTIL
LOCK DETECT HIGH
OFF
ON
S3
0
0
1
0
0
S2
1
1
1
0
0
S1
0
1
1
0
1
MODULATION SCHEME
FSK
GFSK
ASK
OOK
GOOK
.
1
0
.
0
0
X
0
POWER AMPLIFIER OUTPUT LOW LEVEL
D6 D5 .
D2 D1
0
.
X
X
0
.
.
1
.
.
.
.
.
.
.
.
.
1
1
.
0
0
X
X
.
1
0
.
0
1
X
X
OOK MODE
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
.
.
1
0
0
0
0
POWER AMPLIFIER OUTPUT HIGH LEVEL
P6 .
.
P2 P1
.
.
1
.
.
.
.
.
.
.
.
.
.
.
.
.
1
0
1
X
0
.
.
1
1
0
X
0
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
Figure 45. Register 2—Transmit Modulation Register (ASK/OOK Mode)
Register 2—Transmit Modulation Register (ASK/OOK Mode) Comments
If maximum power is needed, program this value to 11 μA.
• D7, D8, and D9 are don’t care bits.
Rev. C | Page 34 of 48
REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)
GFSK MOD
CONTROL
PA BIAS MODULATION PARAMETER POWER AMPLIFIER
MODULATION
SCHEME
ADF7020
ADDRESS
BITS
IC2 IC1 MC3 MC2 MC1
X X X X X
PE1
0
1
POWER AMPLIFIER
OFF
ON
DI1
0
1
TxDATA
TxDATA
PA2
1
1
0
0
PA1
0
1
0
1
PA BIAS
5µA
7µA
9µA
11µA
0
0
0
0
.
1
FOR FSK MODE,
D9 .
D3
.
.
.
.
.
.
0
0
0
0
.
1
D2
0
0
1
1
.
1
D1
0
1
0
1
.
1
F DEVIATION
2 ×
3 ×
.
PLL MODE
1 × f
STEP f
STEP f
STEP
511 × f
STEP
MP1
0
1
MUTE PA UNTIL
LOCK DETECT HIGH
OFF
ON
S3
0
0
1
0
0
S2
1
1
1
0
0
S1
0
1
1
0
1
MODULATION SCHEME
FSK
GFSK
ASK
OOK
GOOK
.
1
0
.
0
0
0
POWER AMPLIFIER OUTPUT LEVEL
P6 .
.
P2 P1
.
1
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
.
X
0
0
.
1
0
.
X
0
1
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
Figure 46. Register 2—Transmit Modulation Register (FSK Mode)
Register 2—Transmit Modulation Register (FSK Mode) Comments
• f
STEP
= PFD/2
14
.
• When operating in the 431 MHz to 478 MHz band, f
STEP
= PFD/2
15
.
• PA bias default = 9 μA.
Rev. C | Page 35 of 48
ADF7020
REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)
GFSK MOD
CONTROL
PA BIAS MODULATION PARAMETER POWER AMPLIFIER
MODULATION
SCHEME
ADDRESS
BITS
D7
0
0
0
0
.
1
.
.
.
.
.
.
.
D3
0
0
0
0
.
1
D2
1
1
0
0
.
1
D1
0
1
0
1
.
1
DIVIDER_FACTOR
2
3
INVALID
1
.
127
PE1
0
1
POWER AMPLIFIER
OFF
ON
DI1
0
1
TxDATA
TxDATA
MP1
0
1
MUTE PA UNTIL
LOCK DETECT HIGH
OFF
ON
PA2
1
1
0
0
PA1
0
1
0
1
PA BIAS
5µA
7µA
9µA
11µA
D9
0
0
1
1
D8
0
1
0
1
GAUSSIAN – OOK
MODE
NORMAL MODE
OUTPUT BUFFER ON
BLEED CURRENT ON
BLEED/BUFFER ON
S3
0
0
1
0
0
S2
1
1
1
0
0
S1
0
1
1
0
1
MODULATION SCHEME
FSK
GFSK
ASK
OOK
GOOK
IC2
1
1
0
0
IC1
0
1
0
1
INDEX_COUNTER
16
32
64
128
.
.
1
0
0
0
0
POWER AMPLIFIER OUTPUT LEVEL
P6 .
.
P2 P1
.
.
1
.
.
.
.
.
.
.
.
.
.
.
.
.
1
0
1
X
0
.
.
1
1
0
X
0
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
MC3
.
1
0
0
MC2 MC1
.
1
0
0
.
1
0
1
GFSK_MOD_CONTROL
.
7
0
1
Figure 47. Register 2—Transmit Modulation Register (GFSK/GOOK Mode)
Register 2—Transmit Modulation Register (GFSK/GOOK Mode) Comments
• GFSK_DEVIATION = (2
GFSK_MOD_CONTROL
× PFD)/2
12
.
• When operating in the 431 MHz to 478 MHz band, GFSK_DEVIATION = (2
GFSK_MOD_CONTROL
× PFD)/2
13
.
• Data Rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).
• PA Bias default = 9 μA.
Rev. C | Page 36 of 48
REGISTER 3—RECEIVER CLOCK REGISTER
SEQUENCER CLOCK DIVIDE CDR CLOCK DIVIDE
ADDRESS
BITS
ADF7020
SK8
.
1
0
0
1
SK7
.
1
0
0
1
.
.
.
.
.
.
SK3
.
1
0
0
1
SK2
.
1
1
0
1
SK1
.
0
1
1
0
SEQ_CLK_DIVIDE
1
2
.
254
255
BK2
0
0
1
BK1
0
1 x
BBOS_CLK_DIVIDE
4
8
16
OK2
0
0
1
1
OK1
0
1
0
1
DEMOD_CLK_DIVIDE
4
1
2
3
FS8
.
1
0
0
1
FS7
.
1
0
0
1
.
.
.
.
.
.
FS3
.
1
0
0
1
FS2
.
1
0
1
1
FS1
.
0
1
0
1
CDR_CLK_DIVIDE
1
2
.
254
255
Figure 48. Register 3—Receiver Clock Register
Register 3—Receiver Clock Register Comments
• Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where
BBOS _ CLK
=
XTAL
BBOS _ CLK _ DIVIDE
• The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where
DEMOD _ CLK
=
XTAL
DEMOD _ CLK _ DIVIDE
• Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where
CDR _ CLK
=
DEMOD _ CLK
CDR _ CLK _ DIVIDE
Note that this can affect your choice of XTAL, depending on the desired data rate.
• The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to
40 kHz for ASK.
SEQ _ CLK
=
XTAL
SEQ _ CLK _ DIVIDE
Rev. C | Page 37 of 48
ADF7020
REGISTER 4—DEMODULATOR SETUP REGISTER
DEMODULATOR LOCK SETTING POSTDEMODULATOR BW
ADDRESS
BITS
DS2
0
0
1
1
DS1
0
1
0
1
DEMODULATOR
TYPE
LINEAR DEMODULATOR
CORRELATOR/DEMODULATOR
ASK/OOK
INVALID
DEMOD MODE
2
3
4
5
0
1
LM2
0
0
1
1
0
0
LM1
1
1
0
1
0
0
DL8
0
1
0
1
X
DL8
DEMOD LOCK/SYNC WORD MATCH
SERIAL PORT CONTROL – FREE RUNNING
SERIAL PORT CONTROL – LOCK THRESHOLD
SYNC WORD DETECT – FREE RUNNING
SYNC WORD DETECT – LOCK THRESHOLD
INTERRUPT/LOCK PIN LOCKS THRESHOLD
DEMOD LOCKED AFTER DL8–DL1 BITS
INT/LOCK PIN
–
–
OUTPUT
OUTPUT
INPUT
–
MODE5 ONLY
DL8
0
.
0
0
1
1
DL7
0
.
0
0
1
1
.
.
.
.
.
.
DL3
0
.
0
0
1
1
DL2
1
.
0
0
1
1
DL1
0
.
0
1
0
1
LOCK_THRESHOLD_TIMEOUT
2
.
0
1
254
255
Figure 49. Register 4—Demodulator Setup Register
Register 4—Demodulator Setup Register Comments
• Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints greater than 7, when using the linear demodulator.
• Postdemod_BW =
2
11
× π × f
CUTOFF
DEMOD_CLK where the cutoff frequency (f
CUTOFF
) of the postdemodulator filter should typically be 0.75 times the data rate.
• For Mode 5, Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK
where SEQ_CLK is defined in the Register 3—Receiver Clock Register section.
Rev. C | Page 38 of 48
REGISTER 5—SYNC BYTE REGISTER
SYNC BYTE SEQUENCE
ADF7020
CONTROL
BITS
PL2
0
0
1
1
PL1
0
1
0
1
SYNC BYTE
LENGTH
12 BITS
16 BITS
20 BITS
24 BITS
MT2
1
1
0
0
MT1
0
1
0
1
MATCHING
TOLERANCE
0 ERRORS
1 ERROR
2 ERRORS
3 ERRORS
Figure 50. Register 5—Sync Byte Register
Register 5—Sync Byte Register Comments
• Sync byte detect is enabled by programming Bits R4_DB[25:23] to 010 or 011.
• This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine data bits.
• The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.
• Choose a sync byte pattern that has good autocorrelation properties, for example, 0x123456.
Rev. C | Page 39 of 48
ADF7020
REGISTER 6—CORRELATOR/DEMODULATOR REGISTER
Rx
RESET
IF FILTER DIVIDER DISCRIMINATOR BW
ADDRESS
BITS
0
1
RI1
0
1
RxDATA
INVERT
RxDATA
RxDATA
0
1
RxRESET
NORMAL OPPERATION
DEMOD RESET
RxRESET
NORMAL OPPERATION
CDR RESET
FC9
.
.
0
0
.
.
1
.
.
.
.
.
.
.
.
CA1
0
1
FILTER CAL
NO CAL
CALIBRATE
ML1
0
1
MIXER LINEARITY
DEFAULT
HIGH
FC6
.
.
.
0
0
.
1
FC5
.
.
.
0
0
.
1
FC4
.
.
.
0
0
.
1
LI2
0
FC3
.
.
0
0
.
.
1
LI1
0
LNA BIAS
800µA (DEFAULT)
FC2
.
.
0
1
.
.
1
FC1
.
.
1
0
.
.
1
FILTER CLOCK
DIVIDE RATIO
1
2
.
.
.
.
511
DP1
0
1
DOT PRODUCT
CROSS PRODUCT
DOT PRODUCT
LG1
0
1
LNA MODE
DEFAULT
REDUCED GAIN
Figure 51. Register 6—Correlator/Demodulator Register
Register 6—Correlator/Demodulator Register Comments
• See the FSK Correlator/Demodulator section for an example of how to determine register settings.
• Nonadherence to correlator programming guidelines results in poorer sensitivity.
• The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz.
The formula is XTAL/FILTER_CLOCK_DIVIDE.
• The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high.
• Discriminator_BW = (DEMOD_CLK × K)/(800 × 10
3
). See the FSK Correlator/Demodulator section. Maximum value = 600.
• When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when
linearity is a concern. See Table 5 for details of the different Rx modes.
Rev. C | Page 40 of 48
REGISTER 7—READBACK SETUP REGISTER
READBACK
SELECT
DB8
RB3
ADC
MODE
CONTROL
BITS
DB7
RB2
DB6
RB1
DB5
AD2
DB4
AD1
DB3
C4(0)
DB2
C3(1)
DB1
C2(1)
DB0
C1(1)
ADF7020
RB3
0
1
READBACK
DISABLED
ENABLED
AD2
0
0
1
1
AD1
0
1
0
1
ADC MODE
MEASURE RSSI
BATTERY VOLTAGE
TEMP SENSOR
TO EXTERNAL PIN
RB2
0
0
1
1
RB1
0
1
0
1
READBACK MODE
AFC WORD
ADC OUTPUT
FILTER CAL
SILICON REV
Figure 52. Register 7—Readback Setup Register
Register 7—Readback Setup Register Comments
• Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the voltage at the external pin in Rx mode, AGC function in Register 9 must be disabled. To read back these parameters in Tx mode, the ADC must first be powered up using Register 8 because this is off by default in Tx mode to save power. This is the recommended method of using the battery readback function because most configurations typically require AGC.
• Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.
• See the Readback Format section for more information.
Rev. C | Page 41 of 48
ADF7020
REGISTER 8—POWER-DOWN TEST REGISTER
LOG AMP/
RSSI
CONTROL
BITS
DB13 DB12 DB11
DB10 DB9
PD7 SW1 LR2 LR1 PD6
DB8
PD5
DB7
PD4
DB6
PD3
DB5
PD2
DB4
PD1
DB3 DB2
DB1 DB0
C4(1) C3(0) C2(0) C1(0)
PD7
0
1
PA (Rx MODE)
PA OFF
PA ON
SW1 Tx/Rx SWITCH
0
1
DEFAULT (ON)
OFF
LR2
X
X
LR1
0
1
RSSI MODE
RSSI OFF
RSSI ON
PD6
0
1
DEMOD ENABLE
DEMOD OFF
DEMOD ON
0
0
1
0
0
PLE1
(FROM REG 0) PD2
1
1
0
0
X
PD1
0
1
0
1
X
LOOP
CONDITION
VCO/PLL OFF
PLL ON
VCO ON
PLL/VCO ON
PLL/VCO ON
PD3
0
1
LNA/MIXER ENABLE
LNA/MIXER OFF
LNA/MIXER ON
PD4
0
1
FILTER ENABLE
FILTER OFF
FILTER ON
PD5
0
1
ADC ENABLE
ADC OFF
ADC ON
Figure 53. Register 8—Power-Down Test Register
Register 8—Power-Down Test Register Comments
• For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.
• It is not necessary to write to this register under normal operating conditions.
Rev. C | Page 42 of 48
REGISTER 9—AGC REGISTER
DIGITAL
TEST IQ
FILTER
GAIN
LNA
GAIN
AGC HIGH THRESHOLD AGC LOW THRESHOLD
ADDRESS
BITS
ADF7020
FI1
0
1
FILTER CURRENT
LOW
HIGH
FG2
0
0
1
1
FG1
0
1
0
1
FILTER GAIN
8
24
72
INVALID
GS1
0
1
AGC SEARCH
AUTO AGC
HOLD SETTING
GC1
0
1
GAIN CONTROL
AUTO
USER
GL7
.
1
1
1
.
.
0
0
0
0
GL6
.
0
0
0
.
.
0
0
0
0
GL5
.
0
0
1
.
.
0
0
0
0
GL4
.
1
1
0
.
.
0
0
0
0
GL3
.
1
1
0
.
.
0
0
0
1
GL2
.
1
1
0
.
.
0
1
1
0
GL1
.
0
1
0
.
.
1
0
1
0
AGC LOW
THRESHOLD
3
4
1
2
.
.
.
78
79
80
LG2
0
0
1
1
LG1
0
1
0
1
LNA GAIN
<1
3
10
30
GH7
.
.
1
1
1
0
0
0
0
.
GH6
.
.
0
0
0
0
0
0
0
.
GH5 GH4
.
.
0
0
1
0
0
0
0
.
.
.
1
1
0
0
0
0
0
.
GH3
.
.
.
1
1
0
0
0
0
1
GH2
.
.
1
1
0
0
1
1
0
.
.
.
0
1
0
1
0
1
0
.
GH1
AGC HIGH
THRESHOLD
.
78
79
80
3
4
.
.
1
2
Figure 54. Register 9—AGC Register
Register 9—AGC Register Comments
•
This register does not need to be programmed in normal operation. Default AGC_Low_Threshold = 30, default
AGC_High_Threshold = 70. See the RSSI/AGC section for details. Default register setting = 0xB2 31E9.
•
AGC high and low settings must be more than 30 apart to ensure correct operation.
•
LNA gain of 30 is available only if LNA mode, R6_DB15, is set to 0.
Rev. C | Page 43 of 48
ADF7020
REGISTER 10—AGC 2 REGISTER
I/Q PHASE
ADJUST
I/Q GAIN ADJUST AGC DELAY LEAK FACTOR PEAK RESPONSE
ADDRESS
BITS
SIQ2 SELECT IQ
0
1
PHASE TO I CHANNEL
PHASE TO Q CHANNEL
IF DB21 = 0, THEN GAIN
IS SELECTED.
IF DB21 = 1, THEN
ATTENUATE IS SELECTED
DEFAULT = 0xA
DEFAULT = 0xA
SIQ2 SELECT IQ
0
1
GAIN TO I CHANNEL
GAIN TO Q CHANNEL
Figure 55. Register 10—AGC 2 Register
DEFAULT = 0x2
Register 10—AGC 2 Register Comments
• This register is not used under normal operating conditions.
• For ASK/OOK modulation, the recommended settings for operation over the full input range are peak response = 2, leak factor = 10
(default), and AGC delay =10 (default). Bit DB31 to Bit DB16 should be cleared. For bit-rates below 4kbps the AGC_Wait_time can be increased by setting the AGC_Delay to 15. The SEQ_CLK should also be set at a minimum.
REGISTER 11—AFC REGISTER
AFC SCALING COEFFICIENT
CONTROL
BITS
AE1
0
1
INTERNAL
AFC
OFF
ON
Figure 56. Register 11—AFC Register
Register 11—AFC Register Comments
• See the Internal AFC section to program the AFC scaling coefficient bits.
• The AFC scaling coefficient bits can be programmed using the following formula:
AFC_Scaling_Coefficient = Round((500 × 2
24
)/XTAL)
Rev. C | Page 44 of 48
REGISTER 12—TEST REGISTER
ANALOG TEST
MUX
MANUAL FILTER CAL
DIGITAL
TEST MODES
ADF7020
-
TEST MODES
PLL TEST MODES
ADDRESS
BITS
P
0
1
PRESCALER
4/5 (DEFAULT)
8/9
DEFAULT = 32. INCREASE
NUMBER TO INCREASE BW
IF USER CAL ON
CR1
0
1
COUNTER RESET
DEFAULT
RESET
CS1
0
1
CAL SOURCE
INTERNAL
SERIAL IF BW CAL
Figure 57. Register 12—Test Register
Register 12—Test Register Comments
This register does not need to be written to in normal operation. The default test mode is 0x0000 000C, which puts the part in normal operation.
Using the Test DAC on the ADF7020 to Implement
Analog FM Demodulation and Measuring of SNR
The test DAC allows the output of the postdemodulator filter
for both the linear and correlator/demodulators (see Figure 30
and Figure 31) to be viewed externally. It takes the 16-bit filter
output and converts it to a high frequency, single-bit output using a second-order Σ-Δ converter. The output can be viewed on the CLKOUT pin. This signal, when filtered appropriately, can then be used to
• Monitor the signals at the FSK/ASK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality.
• Provide analog FM demodulation.
While the correlators and filters are clocked by DEMOD_CLK,
CDR_CLK clocks the test DAC. Note that although the test
DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists.
Programming the test register, Register 12, enables the test
DAC. In correlator mode, this can be done by writing to Digital
Test Mode 7 or 0x0001C00C.
To view the test DAC output when using the linear demodulator, the user must remove a fixed offset term from the signal using Register 13. This offset is nominally equal to the IF frequency. The user can determine the value to program by using the frequency error readback to determine the actual IF and then programming half this value into the offset removal field. It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC.
Setting Up the Test DAC
• Digital test modes = 7: enables the test DAC, with no offset removal (0x0001 C00C).
• Digital test modes = 10: enables the test DAC, with offset removal (needed for linear demodulation only, 0x02 800C).
The output of the active demodulator drives the DAC, that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC.
The evaluation boards for the ADF7020 contain land patterns for placement of an RC filter on the CLKOUT line. This is typically designed so that the cut-off frequency of the filter is above the demodulated data rate.
Rev. C | Page 45 of 48
ADF7020
REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER
PULSE
EXTENSION
TEST DAC GAIN TEST DAC OFFSET REMOVAL KI KP
CONTROL
BITS
KI DEFAULT = 3 KP DEFAULT = 2
PE4
0
.
0
0
.
.
1
PE3
0
.
0
0
.
.
1
PE2
1
.
0
0
.
.
1
PE1
0
.
0
1
.
.
1
PULSE EXTENSION
NORMAL PULSE WIDTH
2 × PULSE WIDTH
3 × PULSE WIDTH
.
.
.
16 × PULSE WIDTH
Figure 58. Register 13—Offset Removal and Signal Gain Register
Register 13—Offset Removal and Signal Gain Register Comments
• Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. The offset can be removed, up to a maximum of 1.0, and gained to use the full dynamic range of the DAC:
DAC_Input = (2
Test_DAC_Gain
) × (Signal − Test_DAC_Offset_Removal/4096)
• Ki (default) = 3. Kp (default) = 2.
Rev. C | Page 46 of 48
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
36
37
0.60 MAX
0.30
0.23
0.18
48
1
PIN 1
INDICATOR
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
4.25
4.10 SQ
3.95
0.50
0.40
0.30
25
24 13
12
0.25 MIN
5.50
REF
1.00
0.85
0.80
12° MAX
0.80 MAX
0.65 TYP
0.50 BSC
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADF7020BCPZ
ADF7020BCPZ-RL
EVAL-ADF7020DBZ3
1
Z = RoHS Compliant Part.
Temperature Range
−40°C to +85°C
−40°C to +85°C
EVAL-ADF70xxMBZ
EVAL-ADF70xxMBZ2
EVAL-ADF7020DBZ1
EVAL-ADF7020DBZ2
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
902 MHz to 928 MHz Daughter Board
860 MHz to 870 MHz Daughter Board
430 MHz to 445 MHz Daughter Board
ADF7020
Package Option
CP-48-3
CP-48-3
Rev. C | Page 47 of 48
ADF7020
NOTES
©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05351-0-5/11(C)
Rev. C | Page 48 of 48
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