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OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
36
37
0.60 MAX
0.30
0.23
0.18
48
1
PIN 1
INDICATOR
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
4.25
4.10 SQ
3.95
0.50
0.40
0.30
25
24 13
12
0.25 MIN
5.50
REF
1.00
0.85
0.80
12° MAX
0.80 MAX
0.65 TYP
0.50 BSC
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADF7020BCPZ
ADF7020BCPZ-RL
EVAL-ADF7020DBZ3
1
Z = RoHS Compliant Part.
Temperature Range
−40°C to +85°C
−40°C to +85°C
EVAL-ADF70xxMBZ
EVAL-ADF70xxMBZ2
EVAL-ADF7020DBZ1
EVAL-ADF7020DBZ2
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
902 MHz to 928 MHz Daughter Board
860 MHz to 870 MHz Daughter Board
430 MHz to 445 MHz Daughter Board
ADF7020
Package Option
CP-48-3
CP-48-3
Rev. C | Page 47 of 48
ADF7020
NOTES
©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05351-0-5/11(C)
Rev. C | Page 48 of 48
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Table of contents
- 1 FEATURES
- 1 APPLICATIONS
- 1 FUNCTIONAL BLOCK DIAGRAM
- 2 TABLE OF CONTENTS
- 3 REVISION HISTORY
- 4 GENERAL DESCRIPTION
- 5 SPECIFICATIONS
- 8 TIMING CHARACTERISTICS
- 8 TIMING DIAGRAMS
- 10 ABSOLUTE MAXIMUM RATINGS
- 10 ESD CAUTION
- 11 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- 13 TYPICAL PERFORMANCE CHARACTERISTICS
- 15 FREQUENCY SYNTHESIZER
- 15 REFERENCE INPUT
- 15 CLKOUT Divider and Buffer
- 15 R Counter
- 15 MUXOUT and Lock Detect
- 15 Regulator Ready
- 15 Digital Lock Detect
- 15 Analog Lock Detect
- 16 Voltage Regulators
- 16 Loop Filter
- 16 N Counter
- 16 Voltage Controlled Oscillator (VCO)
- 17 VCO Bias Current
- 17 CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE
- 18 TRANSMITTER
- 18 RF OUTPUT STAGE
- 18 PA Bias Currents
- 18 MODULATION SCHEMES
- 18 Frequency Shift Keying (FSK)
- 19 Gaussian Frequency Shift Keying (GFSK)
- 19 Setting Up the ADF7020 for GFSK
- 19 Amplitude Shift Keying (ASK)
- 19 On-Off Keying (OOK)
- 19 Gaussian On-Off Keying (GOOK)
- 20 RECEIVER
- 20 RF FRONT END
- 20 IF Filter Settings/Calibration
- 21 RSSI/AGC
- 21 RSSI Thresholds
- 21 Offset Correction Clock
- 21 AGC Information and Timing
- 21 RSSI Formula (Converting to dBm)
- 21 FSK DEMODULATORS ON THE ADF7020
- 21 FSK CORRELATOR/DEMODULATOR
- 22 Postdemodulator Filter
- 22 Bit Slicer
- 22 Data Synchronizer
- 22 FSK Correlator Register Settings
- 22 Postdemodulator Bandwidth Register Settings
- 23 LINEAR FSK DEMODULATOR
- 23 ASK/OOK Operation
- 23 AFC
- 23 External AFC
- 24 Internal AFC
- 24 AFC Performance
- 24 AUTOMATIC SYNC WORD RECOGNITION
- 25 APPLICATIONS INFORMATION
- 25 LNA/PA MATCHING
- 25 External Rx/Tx Switch
- 25 Internal Rx/Tx Switch
- 26 IMAGE REJECTION CALIBRATION
- 26 Calibration Procedure and Setup
- 27 TRANSMIT PROTOCOL AND CODING CONSIDERATIONS
- 27 DEVICE PROGRAMMING AFTER INITIALPOWER-UP
- 27 INTERFACING TO MICROCONTROLLER/DSP
- 28 POWER CONSUMPTION AND BATTERY LIFETIME CALCULATIONS
- 31 SERIAL INTERFACE
- 31 READBACK FORMAT
- 31 AFC Readback
- 31 RSSI Readback
- 31 Battery Voltage/ADCIN/Temperature Sensor Readback
- 31 Silicon Revision Readback
- 31 Filter Calibration Readback
- 32 REGISTERS
- 32 REGISTER 0—N REGISTER
- 32 Register 0—N Register Comments
- 33 REGISTER 1—OSCILLATOR/FILTER REGISTER
- 33 Register 1—Oscillator/Filter Register Comments
- 34 REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)
- 34 Register 2—Transmit Modulation Register (ASK/OOK Mode) Comments
- 35 REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)
- 35 Register 2—Transmit Modulation Register (FSK Mode) Comments
- 36 REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)
- 36 Register 2—Transmit Modulation Register (GFSK/GOOK Mode) Comments
- 37 REGISTER 3—RECEIVER CLOCK REGISTER
- 37 Register 3—Receiver Clock Register Comments
- 38 REGISTER 4—DEMODULATOR SETUP REGISTER
- 38 Register 4—Demodulator Setup Register Comments
- 39 REGISTER 5—SYNC BYTE REGISTER
- 39 Register 5—Sync Byte Register Comments
- 40 REGISTER 6—CORRELATOR/DEMODULATOR REGISTER
- 40 Register 6—Correlator/Demodulator Register Comments
- 41 REGISTER 7—READBACK SETUP REGISTER
- 41 Register 7—Readback Setup Register Comments
- 42 REGISTER 8—POWER-DOWN TEST REGISTER
- 42 Register 8—Power-Down Test Register Comments
- 43 REGISTER 9—AGC REGISTER
- 43 Register 9—AGC Register Comments
- 44 REGISTER 10—AGC 2 REGISTER
- 44 Register 10—AGC 2 Register Comments
- 44 REGISTER 11—AFC REGISTER
- 44 Register 11—AFC Register Comments
- 45 REGISTER 12—TEST REGISTER
- 45 Register 12—Test Register Comments
- 45 Using the Test DAC on the ADF7020 to Implement Analog FM Demodulation and Measuring of SNR
- 45 Setting Up the Test DAC
- 46 REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER
- 46 Register 13—Offset Removal and Signal Gain Register Comments
- 47 OUTLINE DIMENSIONS
- 47 ORDERING GUIDE