NXP LPC11C00 Scalable Entry Level 32-bit Microcontroller (MCU) based on Arm® Cortex®-M0 Cores Data Sheet

yes yes

I/O

Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.

I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the flash ISP command handler via UART

(if PIO0_3 is HIGH) or via C_CAN (if PIO0_3 is LOW).

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/SCK0

PIO0_7/CTS

yes yes yes yes yes yes

I/O

I; PU

CLKOUT — Clockout pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2 — General purpose digital input/output pin.

SSEL0 — Slave Select for SPI0.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

I; PU PIO0_3 — General purpose digital input/output pin. This pin is monitored during reset: Together with a LOW level on pin PIO0_1, a

LOW level starts the flash ISP command handler via C_CAN and a

HIGH level starts the flash ISP command handler via UART.

I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

SCL — I 2 C-bus, open-drain clock input/output. High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.

I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

SDA — I 2 C-bus, open-drain data input/output. High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.

I; PU PIO0_6 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver).

CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

yes yes

I/O

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

yes I

I/O

O -

I; PU PIO0_8 — General purpose digital input/output pin.

MISO0 — Master In Slave Out for SPI0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

I; PU PIO0_9 — General purpose digital input/output pin.

MOSI0 — Master Out Slave In for SPI0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

I; PU SWCLK — Serial wire clock.

PIO0_10 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

7 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 3.

LPC11C12/C14 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

yes R/PIO0_11/

AD0/

CT32B0_MAT3

I/O -

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

PIO0_11 — General purpose digital input/output pin.

PIO1_0 to PIO1_11

R/PIO1_0/AD1/

CT32B1_CAP0

yes -

AD0 — A/D converter, input 0.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 — General purpose digital input/output pin.

R/PIO1_1/AD2/

CT32B1_MAT0

I/O

AD1 — A/D converter, input 1.

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

R/PIO1_2/AD3/

CT32B1_MAT1

I/O

PIO1_1 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 — General purpose digital input/output pin.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

no no

I/O

I/O PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

AD3 — A/D converter, input 3.

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

I; PU SWDIO — Serial wire debug input/output.

PIO1_3 — General purpose digital input/output pin.

AD4 — A/D converter, input 4.

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter.

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

no no

I/O

AD5 — A/D converter, input 5.

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

I; PU PIO1_5 — General purpose digital input/output pin.

RTS — Request To Send output for UART.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

I; PU PIO1_6 — General purpose digital input/output pin.

RXD — Receiver input for UART.

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

8 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 3.

LPC11C12/C14 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

PIO1_7/TXD/

CT32B0_MAT1

no I/O I; PU PIO1_7 — General purpose digital input/output pin.

O -

TXD — Transmitter output for UART.

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0

9 [3]

I/O

I; PU PIO1_8 — General purpose digital input/output pin.

CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_9/

CT16B1_MAT0

no I/O

O -

I; PU PIO1_9 — General purpose digital input/output pin.

CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1

I/O

I; PU PIO1_10 — General purpose digital input/output pin.

AD6 — A/D converter, input 6.

PIO1_11/AD7

PIO2_0 to PIO2_11

I/O

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

I; PU PIO1_11 — General purpose digital input/output pin.

AD7 — A/D converter, input 7.

Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block.

PIO2_0/DTR/

SSEL1

PIO2_1/DSR/SCK1

2 [3]

no no

I/O

I; PU PIO2_0 — General purpose digital input/output pin.

DTR — Data Terminal Ready output for UART.

SSEL1 — Slave Select for SPI1.

I; PU PIO2_1 — General purpose digital input/output pin.

PIO2_2/DCD/

MISO1

PIO2_3/RI/MOSI1

no no

I/O

DSR — Data Set Ready input for UART.

SCK1 — Serial clock for SPI1.

I; PU PIO2_2 — General purpose digital input/output pin.

DCD — Data Carrier Detect input for UART.

MISO1 — Master In Slave Out for SPI1.

I; PU PIO2_3 — General purpose digital input/output pin.

RI — Ring Indicator input for UART.

MOSI1 — Master Out Slave In for SPI1.

PIO2_4

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

PIO2_10

PIO2_11/SCK0

PIO3_0 to PIO3_3

no no no no

no no

I/O

I/O -

I; PU

PIO2_4 — General purpose digital input/output pin.

PIO2_5 — General purpose digital input/output pin.

PIO2_6 — General purpose digital input/output pin.

PIO2_7 — General purpose digital input/output pin.

I; PU PIO2_8 — General purpose digital input/output pin.

I; PU PIO2_9 — General purpose digital input/output pin.

I; PU PIO2_10 — General purpose digital input/output pin.

I; PU PIO2_11 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins

PIO3_4 to PIO3_11 are not available.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

9 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 3.

LPC11C12/C14 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

PIO3_0/DTR 36

no I/O I; PU PIO3_0 — General purpose digital input/output pin.

PIO3_1/DSR

PIO3_2/DCD

no no

I/O

I; PU

DTR — Data Terminal Ready output for UART.

PIO3_1 — General purpose digital input/output pin.

DSR — Data Set Ready input for UART.

PIO3_2 — General purpose digital input/output pin.

PIO3_3/RI

CAN_RXD

CAN_TXD

from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 27

[6]

8; 44 no no no

I/O

XTALIN

XTALOUT

[7]

5; 41 -

DCD — Data Carrier Detect input for UART.

I; PU PIO3_3 — General purpose digital input/output pin.

I; IA

RI — Ring Indicator input for UART.

CAN_RXD — C_CAN receive data input.

I; IA CAN_TXD — C_CAN transmit data output.

Supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

level); IA = inactive, no pull-up/down enabled.

[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

for the reset pad configuration.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see

Figure 26

[4] I 2 C-bus pads compliant with the I 2 C-bus specification for I 2 C standard mode and I 2 C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 26

[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

Table 4.

LPC11C22/C24 pin description table

Symbol

PIO0_0 to PIO0_11

Pin Start logic inputs

Type Reset state

[1]

Description

RESET/PIO0_0

3 [2]

yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

I/O PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

10 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 4.

LPC11C22/C24 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

PIO0_1/CLKOUT/

CT32B0_MAT2

4 [3]

yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the flash ISP command handler via UART

(if PIO0_3 is HIGH) or via C_CAN (if PIO0_3 is LOW).

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

yes yes

I/O

I; PU

CLKOUT — Clockout pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2 — General purpose digital input/output pin.

SSEL0 — Slave Select for SPI0.

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/SCK0

PIO0_7/CTS

yes yes yes yes

I/O

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

I; PU PIO0_3 — General purpose digital input/output pin. This pin is monitored during reset: Together with a LOW level on pin PIO0_1, a

LOW level starts the flash ISP command handler via C_CAN and a

HIGH level starts the flash ISP command handler via UART.

I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

SCL — I 2 C-bus, open-drain clock input/output. High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.

I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

SDA — I 2 C-bus, open-drain data input/output. High-current sink only if I 2 C Fast-mode Plus is selected in the I/O configuration register.

I; PU PIO0_6 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver).

CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

yes yes yes

I/O

I; PU PIO0_8 — General purpose digital input/output pin.

MISO0 — Master In Slave Out for SPI0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

I; PU PIO0_9 — General purpose digital input/output pin.

MOSI0 — Master Out Slave In for SPI0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

I; PU SWCLK — Serial wire clock.

PIO0_10 — General purpose digital input/output pin.

yes -

I/O

R/PIO0_11/

AD0/

CT32B0_MAT3

SCK0 — Serial clock for SPI0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 to PIO1_11

I/O

PIO0_11 — General purpose digital input/output pin.

AD0 — A/D converter, input 0.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

11 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 4.

LPC11C22/C24 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

R/PIO1_0/AD1/

CT32B1_CAP0

yes -

I/O -

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 — General purpose digital input/output pin.

R/PIO1_1/AD2/

CT32B1_MAT0

AD1 — A/D converter, input 1.

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

R/PIO1_2/AD3/

CT32B1_MAT1

I/O

PIO1_1 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 — General purpose digital input/output pin.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

no no

I/O

I/O PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

AD3 — A/D converter, input 3.

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

I; PU SWDIO — Serial wire debug input/output.

PIO1_3 — General purpose digital input/output pin.

AD4 — A/D converter, input 4.

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter.

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

no no

O -

AD5 — A/D converter, input 5.

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

I; PU PIO1_5 — General purpose digital input/output pin.

RTS — Request To Send output for UART.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

I; PU PIO1_6 — General purpose digital input/output pin.

PIO1_7/TXD/

CT32B0_MAT1

I/O

PIO1_8/

CT16B1_CAP0

PIO1_10/AD6/

CT16B1_MAT1

9 [3]

no no

I/O

O -

RXD — Receiver input for UART.

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

I; PU PIO1_7 — General purpose digital input/output pin.

TXD — Transmitter output for UART.

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

I; PU PIO1_8 — General purpose digital input/output pin.

CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

I; PU PIO1_10 — General purpose digital input/output pin.

AD6 — A/D converter, input 6.

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

12 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 4.

LPC11C22/C24 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

PIO1_11/AD7

PIO2_0 to PIO2_11

I/O

I; PU PIO1_11 — General purpose digital input/output pin.

AD7 — A/D converter, input 7.

PIO2_0/DTR/

SSEL1

2 [3]

no I/O

I/O -

I; PU PIO2_0 — General purpose digital input/output pin.

DTR — Data Terminal Ready output for UART.

PIO2_1/DSR/SCK1 13

I/O

I/O -

SSEL1 — Slave Select for SPI1.

I; PU PIO2_1 — General purpose digital input/output pin.

DSR — Data Set Ready input for UART.

SCK1 — Serial clock for SPI1.

PIO2_2/DCD/

MISO1

PIO2_3/RI/MOSI1

no no

I/O

I; PU PIO2_2 — General purpose digital input/output pin.

DCD — Data Carrier Detect input for UART.

MISO1 — Master In Slave Out for SPI1.

I; PU PIO2_3 — General purpose digital input/output pin.

PIO2_6

PIO2_7

PIO2_8

PIO2_10

PIO2_11/SCK0

PIO3_0 to PIO3_3

1 [3]

no no no no no

I/O

I; PU

RI — Ring Indicator input for UART.

MOSI1 — Master Out Slave In for SPI1.

PIO2_6 — General purpose digital input/output pin.

PIO2_7 — General purpose digital input/output pin.

PIO2_8 — General purpose digital input/output pin.

PIO2_10 — General purpose digital input/output pin.

PIO2_11 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

PIO3_4 to PIO3_11 are not available.

PIO3_0/DTR 36

PIO3_1/DSR

PIO3_2/DCD

PIO3_3/RI

from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 27

no no no

I/O

I; PU PIO3_0 — General purpose digital input/output pin.

DTR — Data Terminal Ready output for UART.

I; PU PIO3_1 — General purpose digital input/output pin.

DSR — Data Set Ready input for UART.

I; PU PIO3_2 — General purpose digital input/output pin.

DCD — Data Carrier Detect input for UART.

I; PU PIO3_3 — General purpose digital input/output pin.

RI — Ring Indicator input for UART.

CANL

CANH

STB

VDD_CAN

no no no

I/O

LOW-level CAN bus line.

HIGH-level CAN bus line.

Silent mode control input for CAN transceiver (LOW = Normal mode,

HIGH = silent mode).

Supply voltage for I/O level of CAN transceiver.

Supply voltage for CAN transceiver.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

13 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Table 4.

LPC11C22/C24 pin description table

Symbol Pin Start logic inputs

Type Reset state

[1]

Description

GND

8; 44 -

Ground for CAN transceiver.

Supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

XTALIN

6 [7]

I -

XTALOUT

7 [7]

5; 41 -

O -

Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

level); IA = inactive, no pull-up/down enabled.

[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

for the reset pad configuration.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see

Figure 26

[4] I

C-bus pads compliant with the I

C-bus specification for I

C standard mode and I

C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 26

[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

14 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption.

7.2 On-chip flash program memory

The LPC11Cx2/Cx4 contain 32 kB (LPC11C14/C24) or 16 kB (LPC11C12/C22) of on-chip flash program memory.

7.3 On-chip SRAM

The LPC11Cx2/Cx4 contain a total of 8 kB on-chip static RAM data memory.

7.4 Memory map

The LPC11Cx2/Cx4 incorporates several distinct memory regions, shown in the following

figures. Figure 4

shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral.

LPC11CX2_CX4

Product data sheet

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Rev. 3.2 — 4 January 2016

15 of 64

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

4 GB

1 GB

0.5 GB

0 GB

LPC11Cx2/Cx4 reserved private peripheral bus reserved

AHB peripherals reserved

APB peripherals reserved reserved

16 kB boot ROM reserved

8 kB SRAM reserved

0xFFFF FFFF

0xE010 0000

0xE000 0000

0x5020 0000

0x5000 0000

0x4008 0000

0x4000 0000

0x2000 0000

0x1FFF 4000

0x1FFF 0000

0x1000 2000

0x1000 0000

32 kB on-chip flash (LPC11Cx4)

16 kB on-chip flash (LPC11Cx2)

0x0000 8000

0x0000 4000

0x0000 0000

AHB peripherals

0x5020 0000

16 - 127 reserved

12-15

8-11

4-7

0-3

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

APB peripherals

23 - 31 reserved

SPI1 reserved

C_CAN

reserved system control

IOCONFIG

SPI0 flash controller

PMU

10 - 13 reserved reserved reserved

ADC

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

WDT

C-bus

0x5004 0000

0x5003 0000

0x5002 0000

0x5001 0000

0x5000 0000

0x4008 0000

0x4005 C000

0x4005 8000

0x4005 4000

0x4005 0000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000 active interrupt vectors

0x0000 00C0

0x0000 0000

002aaf268

Fig 4.

LPC11Cx2/Cx4 memory map

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

7.5.1 Features

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• Controls system exceptions and peripheral interrupts.

• In the LPC11Cx2/Cx4, the NVIC supports 32 vectored interrupts including 13 inputs to the start logic from individual GPIO pins.

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• Four programmable interrupt priority levels, with hardware priority level masking.

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any GPIO pin (total of 40 pins (LPC11C12/C14) or 36 pins (LPC11C22/C24)) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.

LPC11Cx2/Cx4 use accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of 40 pins (LPC11C12/C14) or 36 pins (LPC11C22/C24)) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in one write operation.

• Direction control of individual bits.

• All GPIO pins default to inputs with pull-ups enabled after reset except for the I 2 C-bus true open-drain pins PIO0_4 and PIO0_5.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin (except PIO0_4 and PIO0_5).

• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V

= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

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7.8 UART

The LPC11Cx2/Cx4 contain one UART.

Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

• Maximum UART data bit rate of 3.125 Mbit/s.

• 16 Byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.

• FIFO control mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

7.9 SPI serial I/O controller

The LPC11Cx2/Cx4 contain two SPI controllers. Both SPI controllers support SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.9.1 Features

• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.10 I 2 C-bus serial I/O controller

The LPC11Cx2/Cx4 contain one I 2 C-bus controller.

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The I 2 C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2 C is a multi-master bus and can be controlled by more than one bus master connected to it.

7.10.1 Features

• The I 2 C-interface is a standard I 2 C-bus compliant interface with open-drain pins. The

I 2 C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.

• The I 2 C-bus can be used for test and diagnostic purposes.

• The I 2 C-bus controller supports multiple address recognition and a bus monitor mode.

7.11 C_CAN controller

Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security.

On-chip C_CAN drivers provide an API for initialization and communication using CAN and CANopen standards.

7.11.1 Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications.

• Provides programmable loop-back mode for self-test operation.

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• The C_CAN API includes the following functions:

– C_CAN set-up and initialization

– C_CAN send and receive messages

– C_CAN status

– CANopen object dictionary

– CANopen SDO expedited communication

– CANopen SDO segmented communication primitives

– CANopen SDO fall-back handler

• Flash ISP programming via C_CAN supported.

7.11.2 On-chip, high-speed CAN transceiver

Remark: The on-chip CAN transceiver is available on parts LPC11C22/C24 only.

Compared to the LPC11C12/C14, the LPC11C22/C24 supports fewer GPIO functions, and in addition, one counter/timer match function is removed to allow interfacing the CAN

high-speed transceiver to the CAN bus. See Table 4 and

Figure 1

7.11.2.1

Features

• Data rates of up to 1 Mbit/s

• Fully ISO 11898-2 compliant

• Undervoltage detection and thermal protection

• Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)

7.11.2.2

Normal mode

A LOW level on pin STB selects Normal mode. In this mode, the transceiver is able to

transmit and receive data via the bus lines CANH and CANL (see Figure 29

). The differential receiver converts the analog data on the bus lines into digital data which are received by the CAN_RXD input of the C_CAN controller.

7.11.2.3

Silent mode

A HIGH level on pin STB selects Silent mode. In Silent mode the transmitter is disabled, releasing the bus pins to recessive state. All other functions, including the receiver, continue to operate as in Normal mode. Silent mode can be used to prevent a faulty

C_CAN controller from disrupting all network communications.

7.11.2.4

Undervoltage protection

Should V

or VDD_CAN drop below their respective undervoltage detection levels

(V uvd(VCC)

and V uvd (VDD_CAN)

; see Table 8 ), the transceiver will switch off and disengage

from the bus (zero load) until V

and VDD_CAN have recovered.

7.11.2.5

Thermal protection

The output drivers are protected against overtemperature conditions. If the virtual junction temperature exceeds the shutdown junction temperature, T j(sd)

(see Table 8 ), the output

drivers will be disabled until the virtual junction temperature falls below T j(sd)

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7.11.2.6

Time-out function

A ‘TXD dominant time-out’ timer is started when the CAN_TXD signal of the C_CAN controller is set LOW. If the LOW state on the CAN_TXD signal persists for longer than t to(dom)TXD

, the transmitter is disabled, releasing the bus lines to recessive state. This function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). The TXD dominant time-out timer is reset when the CAN_TXD signal is set HIGH. The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.

7.12 10-bit ADC

The LPC11Cx2/Cx4 contains one ADC. The ADC is a single 10-bit successive approximation ADC with eight channels.

7.12.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 V to V

• 10-bit conversion time

 2.44 s (up to 400 kSamples/s).

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.13 General purpose external event counter/timers

The LPC11Cx2/Cx4 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.13.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

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• Up to four external outputs corresponding to match registers, with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.14 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time period.

7.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T cy(WDCLK) multiples of T cy(WDCLK)

 4.

 256  4) to (T cy(WDCLK)

 2 24  4) in

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability.

7.16 Clocking and power control

7.16.1 Crystal oscillators

The LPC11Cx2/Cx4 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC11Cx2/Cx4 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

See

Figure 5 for an overview of the LPC11Cx2/Cx4 clock generation.

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AHB clock 0

(system)

SYSTEM CLOCK

DIVIDER system clock

SYSAHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories and peripherals)

IRC oscillator watchdog oscillator main clock

SPI0 PERIPHERAL

CLOCK DIVIDER

UART PERIPHERAL

CLOCK DIVIDER

SPI1 PERIPHERAL

CLOCK DIVIDER

SPI0

UART

SPI1

MAINCLKSEL

(main clock select)

IRC oscillator system oscillator

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM PLL

IRC oscillator

WDT CLOCK

DIVIDER watchdog oscillator

WDTUEN

(WDT clock update enable)

IRC oscillator system oscillator watchdog oscillator

CLKOUT PIN CLOCK

DIVIDER

WDT

CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aae514

Fig 5.

LPC11Cx2/Cx4 clock generation block diagram

7.16.1.1

Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC11Cx2/Cx4 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.16.1.2

System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

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7.16.1.3

Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is

40 % (see

Table 16

7.16.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100

s.

7.16.3 Clock output

The LPC11Cx2/Cx4 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.16.4 Wake-up process

The LPC11Cx2/Cx4 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.

7.16.5 Power control

The LPC11Cx2/Cx4 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control.

7.16.5.1

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core.

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7.16.5.2

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings.

Up to 13 pins total, see

Table 3

, serve as external wake-up pins to a dedicated start logic to wake up the chip from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free.

7.16.5.3

Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC11Cx2/Cx4 can wake up from Deep power-down mode via the

WAKEUP pin.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode.

7.17 System control

7.17.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in

Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC before being used.

7.17.2 Reset

Reset has four sources on the LPC11Cx2/Cx4: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET pin if Deep power-down mode is used.

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CAUTION

7.17.3 Brownout detection

The LPC11Cx2/Cx4 includes four levels for monitoring the voltage on the V

pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip.

7.17.4 Code security (Code Read Protection - CRP)

This feature of the LPC11Cx2/Cx4 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC11Cx user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART.

If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC11Cx user manual.

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7.17.5 Bootloader

The bootloader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.

The bootloader code is executed every time the part is reset or powered up. The loader can either execute the user application code or the ISP command handler via UART or

C_CAN. A LOW level during reset applied to the PIO0_1 pin is considered as an external hardware request to start the ISP command handler. The state of PIO0_3 at reset determines whether the UART (PIO0_3 HIGH) or the C_CAN (PIO0_3 LOW) interface will be used.

The C_CAN ISP command handler uses the CANopen protocol and data organization method. C_CAN ISP commands have the same functionality as UART ISP commands.

7.17.6 APB interface

The APB peripherals are located on one APB bus.

7.17.7 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM.

7.17.8 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see

Section 7.17.1

7.18 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported.

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Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

V x

Parameter supply voltage (core and external rail) input voltage voltage on pin x

Conditions on pins V

5 V tolerant I/O pins; V no time limit; DC value

 1.8 V on pins CANH and CANL

SS latch

V stg j(max) tot(pack)

ESD supply current on pins STB, V

, VDD_CAN per supply pin ground current

I/O latch-up current per ground pin

(0.5V

) < V

< (1.5V

);

T j

< 125

C storage temperature non-operating maximum junction temperature total power dissipation

(per package) based on package heat transfer, not device power consumption electrostatic discharge voltage human body model; all pins except CAN on-chip transceiver pins CANL,

CANH, STB, VDD_CAN, V

, GND on

LPC11C22/C24 pins CANH and CANL on LPC11C22/C24 pins STB, VDD_CAN, V

, GND on

LPC11C22/C24

Min

0.5

0.5

58

0.3

Table 6 ) and below ground that can be applied for a short time

65

Max

4.6

+5.5

+58

100

+150

150

1.5

[6]

6500

+6500

[6]

8000

+8000

4000

+4000

Unit

V mA mA mA

C

[1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise noted.

[2] Maximum/minimum voltage above the maximum operating voltage (see

(<10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Including voltage on outputs in 3-state mode.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

 series resistor.

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V hys

Table 6.

Static characteristics

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions

DD on pins V

DD supply voltage (core and external rail) supply current Active mode; code while(1){} executed from flash system clock = 12 MHz

= 3.3 V system clock = 50 MHz

= 3.3 V

Sleep mode; system clock = 12

MHz

= 3.3 V

Deep-sleep mode;

= 3.3 V

Deep power-down mode; V

= 3.3 V

Standard port pins, RESET

LOW-level input current

HIGH-level input current

OFF-state output current input voltage

= 0 V; on-chip pull-up resistor disabled

= V

; on-chip pull-down resistor disabled

= 0 V; V

= V

; on-chip pull-up/down resistors disabled

 1.8 V

= 0 V output active output voltage

HIGH-level input voltage

LOW-level input voltage hysteresis voltage

HIGH-level output voltage I

2.0 V

 V

 3.6 V;

4 mA

1.8 V

 V

3 mA

< 2.0 V;

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Min

1.8

Typ

[1]

3.3

Max

3.6

Unit

220

0.5

[11]

[12]

0.7V

 0.4 -

0.4

 0.4 -

0.5

mA mA mA

10 nA

5.0

3.6

0.3V

V nA nA

A nA

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V hys

Table 6.

Static characteristics …continued

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter

OHS

LOW-level output voltage

HIGH-level output current

LOW-level output current

Conditions

2.0 V

 V

 3.6 V;

= 4 mA

1.8 V

 V

< 2.0 V;

= 3 mA

= V

 0.4 V;

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

= 0.4 V

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

= 0 V HIGH-level short-circuit output current

OLS

LOW-level short-circuit output current

= V

I pd

I pu pull-down current pull-up current

= 5 V

= 0 V;

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

< V

< 5 V

High-drive output pin (PIO0_7)

LOW-level input current

HIGH-level input current

OFF-state output current input voltage

= 0 V; on-chip pull-up resistor disabled

= V

; on-chip pull-down resistor disabled

= 0 V; V

= V

; on-chip pull-up/down resistors disabled

 1.8 V output voltage

HIGH-level input voltage

LOW-level input voltage hysteresis voltage

HIGH-level output voltage

= 0 V output active

2.5 V

 V

 3.6 V;

20 mA

1.8 V

 V

< 2.5 V;

12 mA

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[13]

Min

4

3

[13]

15

10

0.5

[11]

[12]

0.7V

0.4

 0.4 -

0.5

50

0.5

Typ [1]

45

Max

0.4

150

85

10 mA mA mA mA

Unit

V mA nA nA

5.0

3.6

0.3V

30 of 64 mA

A

A nA

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Table 6.

Static characteristics …continued

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter

OLS

LOW-level output voltage

HIGH-level output current

LOW-level output current

LOW-level short-circuit output current

Conditions

2.0 V

 V

 3.6 V;

= 4 mA

1.8 V

 V

< 2.0 V;

= 3 mA

= V

 0.4 V;

2.5 V

 V

 3.6 V

1.8 V

 V

< 2.5 V

= 0.4 V

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

= V

I pd pu pull-down current pull-up current

= 5 V

= 0 V

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

< V

< 5 V

I 2 C-bus pins (PIO0_4 and PIO0_5)

HIGH-level input voltage

V hys

Oscillator pins hysteresis voltage

LOW-level output current

= 0.4 V; I 2 C-bus pins configured as standard mode pins

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

= 0.4 V; I 2 C-bus pins configured as

Fast-mode Plus pins

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V input leakage current V

= V

= 5 V

V i(xtal)

V o(xtal)

LOW-level input voltage crystal input voltage crystal output voltage

[13]

Min

15

10

0.7V

3.5

[14]

0.5

Typ [1]

50

0.05V

1.8

Max

0.4

150

85

0.3V

1.95

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[2] T amb

= 25

C.

[3] I

measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

Unit

V mA

V mA mA mA mA

A

V mA mA

A

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[5] Pin CAN_RXD pulled LOW externally.

[6] BOD disabled.

[7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[10] WAKEUP pin pulled HIGH externally.

[11] Including voltage on outputs in 3-state mode.

[12] 3-state outputs go into 3-state mode in Deep power-down mode.

[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[14] To V

9.1 ADC characteristics

Table 7.

ADC static characteristics

T amb





C to +85



C unless otherwise specified; ADC frequency 4.5 MHz, V

= 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ

C ia

L(adj)

R vsi

R i analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance input resistance

Max

 1

 1.5

 3.5

0.6

 4

2.5



[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E

) is the difference between the actual step width and the ideal step width. See Figure 6

[3] The integral non-linearity (E

L(adj)

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See

Figure 6 .

[4] The offset error (E

) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 6

[5] The gain error (E

) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 6 .

[6] The absolute error (E

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See

Figure 6

[7] T amb

= 25

C; maximum sampling frequency f s

= 400 kSamples/s and analog input capacitance C ia

= 1 pF.

[8] Input resistance R i

depends on the sampling frequency fs: R i

= 1 / (f s

 C ia

Unit

V pF

LSB

LSB k



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O gain error

1020

1019

1018

1023

1022

1021

(2) code out

1 offset error

(4)

(5)

(3)

3 4

1 LSB

(ideal)

5 6 7

(LSB ideal

)

(1)

1018 1019 1020 1021 1022 1023 1024

1 LSB =

− V

1024

002aaf426

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E

(4) Integral non-linearity (E

L(adj)

(5) Center of a step of the actual transfer curve.

Fig 6.

ADC characteristics

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9.2 C_CAN on-chip, high-speed transceiver characteristics

Table 8.

Static characteristics

T amb

40 C to +85 C; V

= 4.5 V to 5.5 V; R

= 60

; unless otherwise specified; all voltages are defined with respect to

ground; positive currents flow into the IC. Also see Figure 29 .

Symbol Parameter Conditions Min Typ Max Unit

Supply; pin VCC

CC supply voltage supply current

4.5

0.1

5.5

2.5

V mA

V uvd(VCC) undervoltage detection voltage on pin V

I/O level adapter supply; pin VDD_CAN

DD supply voltage supply current

Silent mode

Normal mode recessive dominant; CAN_TXD = LOW on pin VDD_CAN on pin VDD_CAN; Normal and Silent modes

2.5

3.5

2.8

4.5

5.5

mA mA

V uvd(VDD_CAN) undervoltage detection voltage on pin VDD_CAN recessive; CAN_TXD = HIGH dominant; CAN_TXD = LOW

1.3

350

250

500

2.7

A

Mode control input; pin STB

HIGH-level input voltage

LOW-level input voltage

HIGH-level input current

LOW-level input current

Bus lines; pins CANH and CANL

O(dom)

V dom(TX)sym

O(dif)bus

O(rec) th(RX)dif hys(RX)dif

O(dom)

Voltage on pin STB = 0 V dominant output voltage transmitter dominant voltage symmetry pin CANL

V dom(TX)sym

= V

 V

CANH

 V

CANL bus differential output voltage

CAN_TXD = LOW; t < t to(dom)TXD

CAN_TXD = HIGH; recessive; no load recessive output voltage

CAN_TXD = LOW; t < t to(dom)TXD pin CANH differential receiver threshold voltage differential receiver hysteresis voltage dominant output current

Normal and Silent modes;

CAN_TXD = HIGH; no load

Normal and Silent modes

cm(CAN)

12 V to +12 V

Normal and Silent modes

V cm(CAN)

12 V to +12 V

CAN_TXD = LOW; t < t to(dom)TXD

;

= 5 V pin CANH; V

CANH

= 0 V pin CANL; V

CANL

= 5 V/40 V

0.7V

0.3

1

2.75

0.5

400

1.5

50

0.5

120

3.5

1.5

0.5V

0.7

120

70

0.3V

4.5

2.25

+400

+50

0.9

400

40

120

+ 0.3 V

A

V mV

V mV mA mA

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Table 8.

Static characteristics …continued

T amb

40 C to +85 C; V

= 4.5 V to 5.5 V; R

= 60

; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the IC. Also see Figure 29 .

Symbol

O(rec)

Parameter recessive output current

Conditions Min

5

Typ Max

Unit mA

R i

R i

R i(dif)

C i(cm) leakage current input resistance input resistance deviation differential input resistance common-mode input capacitance

Normal and Silent modes;

CAN_TXD = HIGH;

CANH

= V

CANL

27 V to +32 V

= 0 V; V

CANH

= V

CANL

= 5 V between V

CANH and V

CANL

5

3

A k



% k

 pF

10 pF C i(dif) differential input capacitance

Temperature protection

T j(sd) shutdown junction temperature

190 -

C

[1] VDD_CAN must be equal to the VDD of the microcontroller

[2] V cm(CAN)

is the common mode voltage of CANH and CANL.

Table 9.

Dynamic characteristics

T amb

40 C to +85 C; V

= 4.5 V to 5.5 V; R

L ground. Positive currents flow into the IC.

= 60

 unless specified otherwise. All voltages are defined with respect to

Symbol Parameter Conditions Min Typ Max Unit t to(dom)TXD

TXD dominant time-out time CAN_TXD = LOW; Normal mode

0.3

1 12 ms

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9.3 BOD static characteristics

Table 10.

BOD static characteristics [1]

T amb

= 25



Symbol Parameter Conditions

V th threshold voltage interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion

Min Typ

2.22

2.35

2.52

2.66

2.80

2.90

1.46

1.63

2.06

2.15

2.35

2.43

2.63

2.71

Max Unit

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11Cx

user manual.

9.4 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11Cx user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

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002aaf390

(mA)

48 MHz

(2)

36 MHz

(2)

24 MHz

(2)

12 MHz

(1)

1.8

2.4

3.0

3.6

(V)

Conditions: T amb

= 25

C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 7.

Active mode: Typical supply current I

versus supply voltage V

for different system clock frequencies

002aaf391

(mA)

48 MHz

(2)

36 MHz

(2)

24 MHz

(2)

12 MHz

(1)

LPC11CX2_CX4

Product data sheet

− 40 − 15 10 35 60 temperature (

Conditions: V

= 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 8.

Active mode: Typical supply current I

versus temperature for different system clock frequencies

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48 MHz

(2)

36 MHz

(2)

24 MHz

(2)

12 MHz

(1)

002aaf392

(mA)

−

15 10 35 60 temperature ( ° C)

Conditions: V

= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 9.

Sleep mode: Typical supply current I

versus temperature for different system clock frequencies

002aaf394

(

3.6 V

3.3 V

2.0 V

1.8 V

− 40 − 15 10 35 60 temperature (

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF); pin CAN_RXD pulled LOW externally.

Fig 10. Deep-sleep mode: Typical supply current I

versus temperature for different supply voltages V

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VDD = 3.6 V

3.3 V

2.0 V

1.8 V

002aaf457

0.8

( μ A)

0.6

0.4

0.2

−

15 10 35 60 temperature ( ° C)

Fig 11. Deep power-down mode: Typical supply current I

versus temperature for different supply voltages V

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9.5 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T amb

= 25

C. Unless noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 11.

Power consumption for individual analog and digital blocks

Peripheral Typical supply current in mA

Notes

IRC n/a

0.27

12 MHz 48 MHz

System oscillator at 12 MHz

Watchdog oscillator at

500 kHz/2

0.22

0.004

System oscillator running; PLL off; independent of main clock frequency.

IRC running; PLL off; independent of main clock frequency.

System oscillator running; PLL off; independent of main clock frequency.

BOD

Main PLL

ADC

CLKOUT -

0.051

0.21

0.08

0.12

0.29

0.47

Independent of main clock frequency.

Main clock divided by 4 in the CLKOUTDIV register.

CT16B0

CT16B1

CT32B0

CT32B1

GPIO

0.02

0.23

0.06

0.07

0.06

0.88

GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register.

IOCONFIG -

I2C

ROM -

SPI0

SPI1

UART

C_CAN

WDT

0.03

0.04

0.12

0.22

0.03

0.02

0.10

0.13

0.15

0.45

0.82

0.1

0.06

Main clock selected as clock source for the

WDT.

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9.6 Electrical pin characteristics

3.6

(V)

3.2

T = 85

− 40 ° C

002aae990

2.8

2.4

0 10 20 30 40 50

(mA)

Conditions: V

= 3.3 V; on pin PIO0_7.

Fig 12. High-drive output: Typical HIGH-level output voltage V

versus HIGH-level output current I

002aaf019

(mA)

T = 85 ° C

25 ° C

−

0 0.2

0.4

0.6

(V)

Conditions: V

= 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 13. I 2 C-bus pins (high current sink): Typical LOW-level output current I

versus

LOW-level output voltage V

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T = 85 ° C

25 ° C

−

002aae991

0 0.2

0.4

0.6

(V)

Conditions: V

= 3.3 V; standard port pins and PIO0_7.

Fig 14. Typical LOW-level output current I

versus LOW-level output voltage V

002aae992

3.6

(V)

3.2

T = 85 ° C

−

2.8

2.4

0 8 16 24

(mA)

Conditions: V

= 3.3 V; standard port pins.

Fig 15. Typical HIGH-level output voltage V

versus HIGH-level output source current

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002aae988

I pu

( μ A)

−

T = 85 ° C

−

0 1 2 3

Conditions: V

= 3.3 V; standard port pins.

Fig 16. Typical pull-up current I pu

versus input voltage V

I pd

( μ A)

T = 85 ° C

−

(V)

002aae989

0 1 2 3

Conditions: V

= 3.3 V; standard port pins.

Fig 17. Typical pull-down current I pd

versus input voltage V

(V)

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10. Dynamic characteristics

10.1 Power-up ramp conditions

Table 12.

Power-up characteristics

T amb





C to +85



Symbol Parameter rise time

Conditions at t = t

: 0 < V

 400 mV t r t wait

I wait time input voltage at t = t

on pin V

Min Typ Max

[1][2]

0 -

500

Unit ms

s

400 mV

[1]

See Figure 18

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

t r

400 mV

0 t = t

Condition: 0 < V

 400 mV at start of power-up (t = t

)

Fig 18. Power-up ramp t wait

002aag001

LPC11CX2_CX4

Product data sheet

10.2 Flash memory

Table 13.

Flash characteristics

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions

N endu t ret endurance retention time powered unpowered t er erase time sector or multiple consecutive sectors t prog programming time

Min Typ

10000 100000

100

Dynamic characteristic: I/O pins [1]

0.95

Max

105

1.05

Unit cycles years years ms ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

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10.3 External clock

Table 14.

Dynamic characteristic: external clock

T amb





C to +85



C; V

over specified ranges.

[1]

Symbol Parameter Conditions Min f osc

T cy(clk) t

CHCX t

CLCX t

CLCH t

CHCL oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time -

T cy(clk)

 0.4

T cy(clk)

 0.4

Typ [2]

Max

1000

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

Unit

MHz ns ns ns ns ns t

CHCL t

CLCX

T cy(clk) t

CHCX t

CLCH

002aaa907

Fig 19. External clock timing (with an amplitude of at least V i(RMS)

= 200 mV)

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LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

10.4 Internal oscillators

Table 15.

Dynamic characteristic: internal oscillators

T amb





C to +85



C; 2.7 V



3.6 V.

[1]

Symbol Parameter Conditions f osc(RC) internal RC oscillator frequency -

Min

11.88

Typ

[2]

Max

12.12

Unit

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

002aaf403

12.15

(MHz)

12.05

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

11.95

11.85

− 40 − 15 10 35 60 temperature (

Conditions: Frequency values are typical values. 12 MHz

1 % accuracy is guaranteed for

2.7 V

 V

 3.6 V and T amb

40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz

 1 % accuracy specification for voltages below 2.7 V.

Fig 20. Internal RC oscillator frequency versus temperature

Table 16.

Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions f osc(int) internal oscillator frequency

DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register;

[2][3]

DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register

[2][3]

Min

Typ [1]

7.8

1700

Max Unit kHz kHz

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T amb

40 C to +85 C) is 40 %.

[3] See the LPC11Cx user manual.

LPC11CX2_CX4

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NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

10.5 I/O pins

Table 17.

T amb





C to +85



C; 3.0 V



3.6 V.

Symbol Parameter Conditions t r rise time t f fall time pin configured as output pin configured as output

[1] Applies to standard port pins and RESET pin.

Min

3.0

2.5

Typ Max

5.0

Unit ns ns

10.6 I 2 C-bus

Table 18.

Dynamic characteristic: I 2 C-bus pins

[1]

T amb





C to +85



[2]

Symbol Parameter Conditions f

SCL t f t

LOW t

HIGH t

HD;DAT t

SU;DAT

SCL clock frequency fall time

LOW period of the SCL clock

HIGH period of the SCL clock data hold time data set-up time

[4][5][6][7]

[3][4][8]

[9][10]

Standard-mode

Fast-mode

Fast-mode Plus of both SDA and

SCL signals

Standard-mode

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

Standard-mode

Fast-mode

Fast-mode Plus

Min

20 + 0.1

 C b

4.7

1.3

0.5

4.0

0.6

0.26

250

100

Max

100

400

300

120

Unit kHz kHz

MHz ns ns ns

s

s ns ns ns

[1] See the I 2 C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] C b

= total capacitance of one bus line in pF.

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LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[6] The maximum t f

for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f

is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing.

[8] The maximum t

HD;DAT

could be 3.45

s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t

VD;DAT

or t

VD;ACK

by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t

LOW

) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge.

[10] A Fast-mode I 2 C-bus device can be used in a Standard-mode I 2 C-bus system but the requirement t

SU;DAT

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r(max)

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-mode I 2 C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

SDA

70 %

30 % t f

SCL

S t f

70 %

30 %

1 / f

SCL

70 %

30 % t

HD;DAT t

SU;DAT

70 %

30 %

70 %

30 % t

LOW t

HIGH

70 %

30 % t

VD;DAT

002aaf425

Fig 21. I 2 C-bus pins clock timing

10.7 SPI interfaces

Table 19.

Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions

SPI master (in SPI mode)

T cy(clk) clock cycle time full-duplex mode when only transmitting t

DS data set-up time in SPI mode

2.4 V

 V

 3.6 V

2.0 V

 V

< 2.4 V

1.8 V

 V

< 2.0 V in SPI mode t

DH t v(Q) data hold time data output valid time in SPI mode t h(Q) data output hold time in SPI mode

SPI slave (in SPI mode)

T cy(PCLK)

PCLK cycle time