TRF1123 www.ti.com

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

2.1-GHz to 2.7-GHz 1-W Power Amplifier

FEATURES

•

1.5 W P-1 dBm Linear, 30-dB Gain

Transmitter

•

Operates Over the MMDS, MDS, and WCS

Bands (2.1 GHz to 2.7 GHz)

•

Two TTL Controlled, 1-bit, 16-dB Gain Steps

•

Superior Linearity Over the Entire Gain

Range

•

PACNT Signal Enables and Disables PA

•

Internally Matched 50-

Ω

Input and Output

VPOS

VDD

RFO

Power

Supply

Power Amp /

Attenuator

VNEG

Driver

Amplifier

Pre−Amp

PACNT

LP

RFI

DETN

DETP

PAGAIN1

PAGAIN0

DESCRIPTION

The TRF1123 is a highly integrated linear transmitter power amplifier MMIC. The chip has two 16-dB gain steps that provide a total of 32-dB gain control via 1-bit TTL control signals. The chip also integrates a TTL mute function that turns off the amplifiers for power critical or TDD applications. A temperature compensated detector is included for output power monitor or ALC applications. The chip has a typical P1dB of 31.5 dBm and a third order intercept of 52 dBm.

The TRF1123 is designed to function as a part of Texas Instruments complete 2.5-GHz chip set. The TRF1123 is used as the output power amplifier or a driver amplifier for higher power applications. The linear nature of the transmitter makes it ideal for complex modulations schemes such as high order QAM or OFDM.

KEY SPECIFICATIONS

•

OP

1dB

= 31.5 dBm, Typical

•

Output IP3 = 52 dBm, Typical

•

Gain = 30 dB, Typical

•

Gain Flatness Over Transmit Band ±2.5 dB

•

Frequency Range: 2.1 GHz to 2.7 GHz

•

±0.5-dB Detected Output voltage vs Temperature

BLOCK DIAGRAM

The detailed block diagram and the pin-out of the ASIC are shown in

Figure 1

.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2005–2006, Texas Instruments Incorporated

TRF1123

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

KEY SPECIFICATIONS (continued)

www.ti.com

VDD1

VDD2

VDD3A

VDD3B

Power

Supply

Power Amp /

Attenuator

RFO

Switched Attn

Driver Amp

Switched Attn

Pre−Amp

RFI

DETN

DETP

2

Figure 1. Detailed Block Diagram of TRF1123

ELECTROSTATIC DISCHARGE NOTE

The TRF1223 contain Class 1 devices. The following Electrostatic Discharge (ESD) precautions are recommended:

•

Protective outer garments

•

Handling in ESD safeguarded work area

•

Transporting in ESD shielded containers

•

Frequent monitoring and testing all ESD protection equipment

•

Treating the TRF1223 as extremely sensitive to ESD

PINOUT TABLE

PIN #

1

2

3

4

5

6

7

PIN NAME

GND

GND

GND

RFI

GND

VG1

GND

I/O

-

-

-

I

-

I/O

-

TYPE

-

-

-

Analog

-

Analog

-

Table 1. Pinout of TRF1123

DESCRIPTION

Ground

Ground

Ground

RF input to power amplifier, dc blocked internally.

Ground

No connection required for normal operation. May be used to adjust FET1 bias. DO

NOT GROUND THIS PIN.

Ground

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PIN #

8

9

10

11

12

13

21

22

23

24

18

19

20

28

29

30

31

32

25

26

27

14

15

16

17

PIN NAME

VNEG

VPOS

PAGAIN0

VG2

PAGAIN1

VG3

LP

PACNT

GND

VDD3B

GND

GND

GND

RFO

GND

GND

VDD3A

GND

DETP

DETN

VDD2

GND

GND

VDD1

GND

Back

I/O

I

I

-

O

-

-

-

-

-

O

O

I

-

I

I

-

-

-

I

I

I/O

I

I/O

-

I

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

KEY SPECIFICATIONS (continued)

-

-

-

Analog

-

-

Power

Power

Digital

Analog

Digital

Digital

-

Power

-

Analog

Analog

Power

-

-

-

-

Table 1. Pinout of TRF1123 (continued)

TYPE

Power

Digital

DESCRIPTION

Negative power supply –5 V. Used to set gate voltage. This voltage must be sequenced with VDD. See

(1)

.

Positive power supply. Bias is +V. Used to set gate bias and logic input level.

First 16-dB attenuator gain control. Logic high is high gain; logic low is low gain.

No connection required for normal operation. May be used to adjust FET2 bias. DO

NOT GROUND THIS PIN.

Second 16-dB gain control. Logic high is high gain, Logic low is low gain.

No connection required for normal operation. May be used to adjust FET3 bias. DO

NOT GROUND THIS PIN.

Low Power Mode: Active high. Low power mode is lower DC and Pout mode.

Power amplifier enable, high is PA on, logic low is PA off (low current)

Ground

Stage 3 dc drain supply power. This pin is internally dc connected to pin 24 (VDD3A).

Bias must be provided to both pins for optimal performance. The total dc current through these two pins is typically 70% of IDD.

Ground

Ground

Ground

RF output dc block is provided

Ground

Ground

Stage 3 dc drain supply power. This pin is internally dc connected to pin 17 (VDD3B).

Bias must be provided to both pins for optimal performance. The total dc current through these two pins is typically 70% of IDD.

Ground

Detector output, positive. Voltage will be 0.5 V with/without RF output

Detector output, negative. Voltage is 0.5 V with no RF and decreases with increasing

RF output power.

Stage 2 dc drain supply power. The dc current through this pin is typically 25% of IDD.

Ground

Ground

Stage 1 dc drain supply power. The dc current through this pin is typically 5% of IDD.

Ground

Back of package has metal base that must be grounded for thermal and RF performance.

(1) Proper Sequencing: In order to avoid permanent damage to the power amplifier, the supply voltages must be sequenced. The proper power up sequence is VNEG, then VPOS, and then VDD. The proper power down sequence is remove VDD, then VPOS, and then

VNEG.

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TRF1123

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

ABSOLUTE MAXIMUM RATINGS

PARAMETER

V

DD

V

POS

V

NEG

I

DD

P

IN

T

J

P

D

Θ jc

T stg

T op

DC supply voltage

Current consumption

RF input power

Junction temperature

Power dissipation

Digital input pins

Thermal resistance junction to case

(1)

Storage temperature

Operating temperature

TEST CONDITION MIN

0

0

-5.5

-0.3

MAX

+8

5.5

0

700

20

175

5.5

5.5

20

www.ti.com

UNIT

V

Ma dBm

°C

W

°C/W

Maximum case temperature derate for

PCB thermal resistance

40 sec maximum

-40

-40

+105

+85

°C

°C

Lead temperature 220 °C

(1) Thermal resistance is junction to case assuming thermal pad with 25 thermal vias under package metal base. See recommended layout

Figure 11

and application note RA1005 for more detail.

I

POS

V

IH

V

IL

I

IH

I

IL

V

DD

I

DD

V

NEG

I

NEG

V

POS

DC CHARACTERISTICS

PARAMETER

VDD supply voltage

VDD supply current

Negative supply voltage

Negative supply current

Positive supply digital voltage

Positive supply digital current

Input high voltage

Input low voltage

Input high current

Input low current

CONDITIONS

PACNTRL = High, VDD = 7 V, 25°C

MIN

-5.25

4.75

2.5

TYP

7

600

-5

15

5

25

MAX

7.35

700

-4.75

25

5.25

50

5

0.8

300

-50

UNIT

V mA

V mA

V mA

V

V

µA

µA

POWER AMPLIFIER CHARACTERISTICS

V

DD

= 7 V, I stated

DD

= 600 mA, V

POS

= 5 V, V

NEG

= -5 V, PAGAIN0 = 1, PAGAIN1 = 1, PACNT = 1, T = 25°C, unless otherwise

F

G

G

HG

G

NB

OP-1dB

OIP3

V det t

STEP

PARAMETER

Frequency

Gain

Gain flatness full band

Gain flatness / 2 MHz

TEST CONDITIONS

F = 2100 MHz to 2700 MHz

Output power at 1-dB compression

Output third order intercept point

Gain step size 1st step

Gain step size 2nd step

PAGAIN0 = Low, PAGAIN1 = High

PAGAIN0 = Low, PAGAIN1 = Low

Detector voltage output, differential At Pout = 27 ±0.75 dBm, F = 2100

(DETP-DETN) to 2700 MHz at 25°C

Detector accuracy vs temperature F=2500 MHz, -30°C to 75°C

Gain step response time

MIN

2100

26

30

40

15

30

TYP

30

3

31.5

52

16

32

150

±0.75

1

MAX

2700

36

5

0.2

17

34

5

UNIT

MHz dB dBm dB mV dB

µS

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TRF1123 www.ti.com

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

POWER AMPLIFIER CHARACTERISTICS (continued)

V

DD

= 7 V, I stated

DD

= 600 mA, V

POS

= 5 V, V

NEG

= -5 V, PAGAIN0 = 1, PAGAIN1 = 1, PACNT = 1, T = 25°C, unless otherwise

P

ON/OFF

NF

HG

NF

LG

S

12

S

11

S

22

PARAMETER

On to off power ratio

Noise figure, max gain

Noise figure min gain

Reverse isolation

Input return loss

Output return loss

TEST CONDITIONS

Max Gain to gain with PACNT =

Low

PAGAIN0 = High, PAGAIN1 = High

PAGAIN = Low, PAGAIN1 = Low

Z = 50

Ω

Z = 50

Ω

MIN

35

30

-10

TYP

6

-12

-8

MAX

7

20

UNIT

dB

20

15

10

35

T

A

= 5

5

C

30

25

TYPICAL PERFORMANCE

36

V

DD

= 5 V,

V

DD

= 7 V

5

0

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

3 f − Frequency − GHz

Figure 2. Gain vs Frequency

32

28

24

7 V, 32 dB Step

T

A

= 5

5

C

5 V, 32 dB Step

20

7 V, 16 dB Step

16

12

5 V, 16 dB Step

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

3 f − Frequency − GHz

Figure 3. Gain Control

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5

6

TRF1123

20

2.150 2.250 2.350 2.450 2.550 2.650 2.686

f − Frequency − GHz

Figure 4. Output P-1 dB and IP3

−30

PA Notched Test,

V

DD

= 6 V,

1000 Carriers @ 2 kHz Spacing www.ti.com

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

TYPICAL PERFORMANCE (continued)

60

−30

55

IP3, V

DD

= 7 V

22 dBm

50

45

40

IP3, V

DD

= 5 V

−40

20 dBm

21 dBm

35

30

25

P-1dB, V

DD

= 7 V

P-1dB, V

DD

= 5 V

−50

19 dBm

−60

2000

PA Notched Test,

V

DD

= 5 V,

1000 Carriers @ 2 kHz Spacing

2200 2400 f − Frequency − MHz

2600

Figure 5. PA Notched Test (V

DD

= 5 V)

2800

−30

PA Notched Test,

V

DD

= 7 V,

1000 Carriers @ 2 kHz Spacing

−40

22 dBm

−50

21 dBm

20 dBm

19 dBm

−60

2000 2200 2400 f − Frequency − MHz

2600

Figure 6. PA Notched Test (V

DD

= 6 V)

2800

−40

22 dBm

21 dBm

−50

20 dBm

19 dBm

−60

2000 2200 2400 f − Frequency − MHz

2600

Figure 7. PA Notched Test (V

DD

= 7 V)

2800

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TRF1123

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

TYPICAL PERFORMANCE (continued)

Figure 8. Pulse Droop - RF Output With PACNT Pulsed and 20% Duty Cycle

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TRF1123 www.ti.com

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

APPLICATION INFORMATION

Figure 9. Package Drawing

A typical application schematic is shown in

Figure 10

and a mechanical drawing of the package outline (LPCC

Quad 5 mm x 5 mm, 32-pin) is shown in

Figure 9 .

The recommended PCB layout mask is shown in

Figure 11

, along with recommendations on the board material

Table 2

and construction

Figure 12

.

VDD

10

m

F*

1

m

F

0.1

m

F

100 pF

0.1

m

F

100 pF

Vdet

8

32 31 30 29 28 27 26 25

RFI

VNEG

1

m

F

0.1

m

F 100 pF

BASE

1

GND

2

GND

3

GND

4

RFI

5

GND

6

VG1

7

GND

8

VNEG

9 10 11 12 13

VDD3A

24

GND

23

GND

22

RFO

21

GND

20

GND

19

GND

18

VDD3B

17

100 pF

RF_OUT

100 pF

0.1

m

F

0.1

m

F

14 15 16

VPOS

PACNT

PAGAIN1

PAGAIN0

1

m

F

0.1

m

F 100 pF

0.1

m

F

*10 mF May Need to be 100 mF For High

Speed Pulse Applications

Place 100 pF Capacitors Close to Package

Pins and Minimize Parstic Inductance

Figure 10. Recommended TRF1123 Application Schematic

Table 2. PCB Recommendations

Board Material

Board Material Core Thickness

Copper Thickness (starting)

FR4

10 mil

1 oz

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TRF1123

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

Table 2. PCB Recommendations (continued)

Prepreg Thickness

Recommended Number of Layers

Via Plating Thickness

Final Plate

Final Board Thickness

8 mil

4

0.5 oz

White immersion tin

33-37 mil

3.80

0.50 TYP

0.20 TYP

PIN 1

0.75 TYP

3.80

3.50

0.75 TYP

0.60 TYP

DIA 0.38

TYP

0.25 TYP

3.50

SOLDER MASK: NO SOLDERMASK UNDER CHIP, ON LEAD PADS

OR ON GROUND CONNECTIONS.

25 VIA HOLES, EACH 0.38 mm.

DIMENSIONS in mm

Figure 11. Recommended Pad Layout

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TRF1123

SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006

35 Mil

Dia 15 Mil 1 oz Copper + 1/2 oz Copper Plated

Upper and Lower Surfaces

10 Mil Core FR4

8 Mil

Prepreg

1 oz Copper

1 oz Copper

10 Mil Core FR4 www.ti.com

DuPont CB 100 Conductive Via Plug

1/2 oz Copper Plated

Figure 12. PCB Via Cross Section

10

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PACKAGE OPTION ADDENDUM

5-Feb-2007

PACKAGING INFORMATION

Orderable Device

TRF1123IRTMR

TRF1123IRTMRG3

TRF1123IRTMT

TRF1123IRTMTG3

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package

Type

QFN

QFN

QFN

QFN

Package

Drawing

RTM

RTM

RTM

RTM

Eco Plan

(2)

Pins Package

Qty

32 3000 Green (RoHS & no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU SN Level-3-260C-168 HR

32 CU SN Level-3-260C-168 HR

32

3000 Green (RoHS & no Sb/Br)

250 Green (RoHS & no Sb/Br)

CU SN Level-3-260C-168 HR

32 250 Green (RoHS & no Sb/Br)

CU SN Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

19-Mar-2008

*All dimensions are nominal

Device

TRF1123IRTMR

TRF1123IRTMT

Package

Type

Package

Drawing

QFN

QFN

RTM

RTM

Pins

32

32

SPQ

3000

250

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

12.4

330.0

12.4

A0 (mm)

5.3

5.3

B0 (mm)

5.3

5.3

K0 (mm) P1

(mm)

W

(mm)

Pin1

Quadrant

1.5

1.5

8.0

8.0

12.0

12.0

Q2

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

19-Mar-2008

*All dimensions are nominal

Device

TRF1123IRTMR

TRF1123IRTMT

Package Type Package Drawing Pins

QFN

QFN

RTM

RTM

32

32

SPQ

3000

250

Length (mm) Width (mm) Height (mm)

340.5

340.5

333.0

333.0

20.6

20.6

Pack Materials-Page 2

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