STMicroelectronics TS555 Datasheet

TS555
Low-power single CMOS timer
Datasheet - production data
Description
The TS555 is a single CMOS timer with very low
consumption:
(Icc(TYP) TS555 = 110 µA at VCC = +5 V versus
Icc(TYP) NE555(a) = 3 mA),
SO8
(plastic micropackage)
and high frequency:
(ff(max.) TS555 = 2.7 MHz versus
f(max) NE555(a) = 0.1 MHz).
Pin connections
(top view)
*1'
9&&
7ULJJHU
'LVFKDUJH
2XWSXW
7KUHVKROG
5HVHW
&RQWURO
9ROWDJH
Timing remains accurate in both monostable and
astable mode.
The TS555 provides reduced supply current
spikes during output transitions, which enable the
use of lower decoupling capacitors compared to
those required by bipolar NE555(a).
With the high input impedance (1012Ω), timing
capacitors can also be minimized.
Features
• Very low power consumption:
– 110 µA typ at VCC = 5 V
– 90 µa typ at VCC = 3 V
• High maximum astable frequency of 2.7 MHz
• Pin-to-pin functionally-compatible with bipolar
NE555(a)
• Wide voltage range: +2 V to +16 V
• Supply current spikes reduced during output
transitions
• High input impedance: 1012 Ω
• Output compatible with TTL, CMOS and logic
MOS
a. Terminated product
June 2015
This is information on a product in full production.
DocID4077 Rev 4
1/19
www.st.com
Contents
TS555
Contents
1
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
2
Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
4.1
Monostable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Astable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
DocID4077 Rev 4
TS555
1
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
Symbol
Parameter
VCC
Supply voltage
IOUT
Output current
Rthja
Thermal resistance junction to ambient
Rthjc
Thermal resistance junction to case (1)
Tj
Tstg
(1)
Junction temperature
Storage temperature range
+18
V
± 100
mA
125
40
-65 to +150
°C/W
°C
1500
Machine model (MM)(3)
Charged device model (CDM)
Unit
+150
Human body model (HBM)(2)
ESD
Value
V
200
(4)
1000
1. Short-circuits can cause excessive heating. These values are typical and specified for a four layers PCB.
2. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
3. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of
connected pin combinations while the other pins remain floating.
4. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to the ground.
Table 2. Operating conditions
Symbol
Parameter
VCC
Supply voltage
IOUT
Output sink current
Output source current
Toper
Operating free air temperature range
DocID4077 Rev 4
Value
Unit
2 to 16
V
10
50
mA
-40 to +125
°C
3/19
19
5
4/19
5
DocID4077 Rev 4
N 7
5
N 7
5
N 7
5
N 7
5
&RQWURO9ROWDJH
N 7
4
4
4
4
4
7KUHVKROG
4
4 4
5
4
4
4
4
4
4
4
*1'
4
4
5(6(7
4
4
7ULJJHU
4
4
4
4
4
4
4
4
4
4
4
4
4
4
'LVFKDUJH
4
2XWSXW
2
N 7
9 &&
Schematic diagrams
TS555
Schematic diagrams
Figure 1. Schematic diagram
TS555
Schematic diagrams
Figure 2. Block diagram
6##
2ESET
76
5
5
4HRESHOLD #ONTROL
6OLTAG E
4
/UTPUT
$ISCHARGE
5
$
6
5
4RIGGER %
5
'ROUND
Table 3. Functional table
Reset
Trigger
Low
x
Low
High
Note:
High
Threshold
x
Output
Low
High
High
Low
Low
Previous state
Low: level voltage ≤ minimum voltage specified
High: level voltage ≥ maximum voltage specified
x: irrelevant
DocID4077 Rev 4
5/19
19
Electrical characteristics
3
TS555
Electrical characteristics
Table 4. Static electrical characteristics
VCC = +2 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
65
200
200
µA
1.3
1.4
1.5
0.05
0.2
0.25
1
100
0.1
0.3
0.35
ICC
Supply current (no load, high and low states)
Tmin ≤Tamb ≤Tmax
VCL
Control voltage level
Tmin ≤Tamb ≤Tmax
VDIS
Discharge saturation voltage (Idis = 1 mA)
Tmin ≤Tamb ≤Tmax
IDIS
Discharge pin leakage current
VOL
Low level output voltage (Isink = 1 mA)
Tmin ≤Tamb ≤Tmax
VOH
High level output voltage (Isource = -0.3 mA)
Tmin ≤Tamb ≤Tmax
1.5
1.5
1.9
VTRIG
Trigger voltage
Tmin ≤Tamb ≤Tmax
0.4
0.3
0.67
ITRIG
Trigger current
10
Threshold current
10
ITH
6/19
Parameter
VRESET
Reset voltage
Tmin ≤Tamb ≤Tmax
IRESET
Reset current
1.2
1.1
0.4
0.3
1.1
10
DocID4077 Rev 4
V
nA
V
0.95
1.05
pA
1.5
2.0
V
pA
TS555
Electrical characteristics
Table 5. Static electrical characteristics
VCC = +3 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
90
230
230
µA
2
2.2
2.3
0.05
0.2
0.25
1
100
0.1
0.3
0.35
ICC
Supply current (no load, high and low states)
Tmin ≤Tamb ≤Tmax
VCL
Control voltage level
Tmin ≤Tamb ≤Tmax
VDIS
Discharge saturation voltage (Idis = 1 mA)
Tmin ≤Tamb ≤Tmax
IDIS
Discharge pin leakage current
VOL
Low level output voltage (Isink = 1 mA)
Tmin ≤Tamb ≤Tmax
VOH
High level output voltage (Isource = -0.3 mA)
Tmin ≤Tamb ≤Tmax
2.5
2.5
2.9
VTRIG
Trigger voltage
Tmin ≤Tamb ≤Tmax
0.9
0.8
1
ITRIG
Trigger current
10
Threshold current
10
ITH
VRESET
Reset voltage
Tmin ≤Tamb ≤Tmax
IRESET
Reset current
1.8
1.7
0.4
0.3
1.1
10
DocID4077 Rev 4
V
nA
V
1.1
1.2
pA
1.5
2.0
V
pA
7/19
19
Electrical characteristics
TS555
Table 6. Dynamic electrical characteristics
VCC = +3 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Parameter
Min.
Timing accuracy (monostable)(1)
R = 10 kΩ, C = 0.1 µF
VCC = 2 V
VCC = 3 V
fmax
0.5
Timing shift with temperature (1)
Tmin ≤Tamb ≤Tmax
75
Maximum astable frequency (2)
RA = 470 Ω, RB = 200 Ω, C = 200 pF
Timing shift with supply voltage variations
(astable mode) (2)
RA = RB = 1 kΩ to 100 kΩ, C = 0.1 µF,
VCC = 3 to 5 V
—
2
5
0.5
Output rise time (Cload = 10 pF)
25
tF
Output fall time (Cload = 10 pF)
20
Trigger propagation delay
100
Minimum reset pulse width (Vtrig = 3 V)
350
tRPW
1. See Figure 4
2. See Figure 6
DocID4077 Rev 4
Unit
%
%/V
tR
tPD
Max.
1
1
Timing shift with supply voltage variations
(monostable)
R = 10 kΩ, C = 0.1 µF, VCC = 3 V ± 0.3 V (1)
Astable frequency accuracy (2)
RA = RB = 1 kΩ to 100 kΩ, C = 0.1 µF
8/19
Typ.
ppm/°C
MHz
—
%
%/V
ns
TS555
Electrical characteristics
Table 7. Static electrical characteristics
VCC = +5 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
110
250
250
µA
3.3
3.8
3.9
0.2
0.3
0.35
1
100
0.3
0.6
0.8
ICC
Supply current (no load, high and low states)
Tmin ≤Tamb ≤Tmax
VCL
Control voltage level
Tmin ≤Tamb ≤Tmax
VDIS
Discharge saturation voltage (Idis = 10 mA)
Tmin ≤Tamb ≤Tmax
IDIS
Discharge pin leakage current
VOL
Low level output voltage (Isink = 8 mA)
Tmin ≤Tamb ≤Tmax
VOH
High level output voltage (Isource = -2 mA)
Tmin ≤Tamb ≤Tmax
4.4
4.4
4.6
VTRIG
Trigger voltage
Tmin ≤Tamb ≤Tmax
1.36
1.26
1.67
ITRIG
Trigger current
10
Threshold current
10
ITH
VRESET
Reset voltage
Tmin ≤Tamb ≤Tmax
IRESET
Reset current
2.9
2.8
0.4
0.3
1.1
10
DocID4077 Rev 4
V
nA
V
1.96
2.06
pA
1.5
2.0
V
pA
9/19
19
Electrical characteristics
m
TS555
Table 8. Dynamic electrical characteristics
VCC = +5 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Parameter
Min.
Timing accuracy (monostable) (1)
R = 10 kΩ, C = 0.1 µF
75
Maximum astable frequency (2)
RA = 470 Ω, RB = 200 Ω, C = 200 pF
2.7
3
Output rise time (Cload = 10 pF)
25
tF
Output fall time (Cload = 10 pF)
20
Trigger propagation delay
100
Minimum reset pulse width (Vtrig = 5 V)
350
2. See Figure 6
DocID4077 Rev 4
ppm/°C
MHz
—
tR
1. See Figure 4
10/19
—
0.1
tRPW
%
%/V
Timing shift with supply voltage variations
(astable mode) (2)
RA = RB = 10 kΩ, C = 0.1 µF, VCC = 5 to 12 V
tPD
Unit
0.38
Timing shift with temperature (1)
Tmin ≤Tamb ≤Tmax5
Astable frequency accuracy (2)
RA = RB = 1 kΩ to 100 kΩ, C = 0.1 µF
Max.
2
Timing shift with supply voltage variations
(monostable) (1)
R = 10 kΩ, C = 0.1 µF,VCC = 5 V ± 1 V
fmax
Typ.
%
%/V
ns
TS555
Electrical characteristics
Table 9. Static electrical characteristics
VCC = +12 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
170
400
400
µA
8
8.6
8.7
0.09
1.5
2.0
1
100
1.2
2
2.8
ICC
Supply current (no load, high and low states)
Tmin ≤Tamb ≤Tmax
VCL
Control voltage level
Tmin ≤Tamb ≤Tmax
VDIS
Discharge saturation voltage (Idis = 80 mA)
Tmin ≤Tamb ≤Tmax
IDIS
Discharge pin leakage current
VOL
Low level output voltage (Isink = 50 mA)
Tmin ≤Tamb ≤Tmax
VOH
High level output voltage (Isource = -10 mA)
Tmin ≤Tamb ≤Tmax
10.5
10.5
11
VTRIG
Trigger voltage
Tmin ≤Tamb ≤Tmax
3.2
3.1
4
ITRIG
Trigger current
10
Threshold current
10
ITH
VRESET
Reset Voltage
Tmin ≤Tamb ≤Tmax
IRESET
Reset current
7.4
7.3
0.4
0.3
1.1
10
DocID4077 Rev 4
V
nA
V
4.8
4.9
pA
1.5
2.0
V
pA
11/19
19
Electrical characteristics
TS555
Table 10. Dynamic electrical characteristics
VCC = +12 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)
Symbol
Parameter
Min.
Timing accuracy (monostable) (1)
R = 10 kΩ, C = 0.1 µF, VCC = +12 V
Astable frequency accuracy
RA = RB = 1 kΩ to 100 kΩ, C = 0.1 µF,
VCC = +12 V
Timing shift with supply voltage variations
(astable mode)
RA = RB = 1 kΩ to 100 kΩ, C = 0.1 µF,
VCC = 5 to +12 V
3
0.1
2. See Figure 6
Figure 3. Supply current (per timer) versus supply voltage
6833/<&855(17, &&—$
12/19
DocID4077 Rev 4
ppm/°C
—
2.7
1. See Figure 4
6833/<92/7$*(9 &&9
%/V
75
—
Unit
%
0.38
Timing shift with temperature
Tmin ≤Tamb ≤Tmax., VCC = +5 V
Maximum astable frequency (2)
RA = 470 Ω, RB = 200 Ω, C = 200 pF, VCC = +5 V
Max.
4
Timing shift with supply voltage variations
(monostable) (1)
R = 10 kΩ, C = 0.1 µF, VCC = +5 V ±1 V
fmax
Typ.
MHz
%
%/V
TS555
Application information
4
Application information
4.1
Monostable operation
In monostable mode, the timer operates like a one-shot generator. The external capacitor is
initially held discharged by a transistor inside the timer, as shown in Figure 4.
Figure 4. Application schematic
9&&
5HVHW
5
7ULJJHU
76
2XW
&
&RQWURO9ROWDJH
M)
The circuit triggers on a negative-going input signal when the level reaches 1/3 VCC. Once
triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered
again during this interval. The duration of the output HIGH state is given by t = 1.1 R x C.
Since the charge rate and threshold level of the comparator are both directly proportional to
the supply voltage, the timing interval is independent of the supply. Applying a negative
pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2) during the
timing cycle discharges the external capacitor and causes the cycle to start over. The timing
cycle then starts on the positive edge of the reset pulse. While the reset pulse is applied, the
output is driven to the LOW state.
When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short
circuit across the external capacitor and driving the output HIGH. The voltage across the
capacitor increases exponentially with the time constant τ = R x C.
When the voltage across the capacitor equals 2/3 VCC, the comparator resets the flip-flop
which then discharges the capacitor rapidly and drives the output to its LOW state. Figure 5
shows the actual waveforms generated in this mode of operation.
When reset is not used, it should be tied high to avoid any false triggering.
Figure 5. Timing diagram
W PVGL
Y
,1387 9GL
Y
287387
92/7$*( 9GLY
&$3$&,72592/7$*( 9GL
Y
5 NŸ& —)5 / NŸ
DocID4077 Rev 4
13/19
19
Application information
4.2
TS555
Astable operation
When the circuit is connected as shown in Figure 6 (pins 2 and 6 connected) it triggers itself
and runs as a multi-vibrator. The external capacitor charges through RA and RB and
discharges through RB only. Therefore, the duty cycle may be precisely set by the ratio of
these two resistors.
In the astable mode of operation, C charges and discharges between 1/3 VCC and 2/3 VCC.
As in the triggered mode, the charge and discharge times, and therefore frequency, are
independent of the supply voltage.
Figure 6. Application schematic
9&&
5HVHW
5$
2XW
76
5%
&RQWURO
9ROWDJH
M)
&
Figure 7 shows actual waveforms generated in this mode of operation.
The charge time (output HIGH) is given by:
t1 = 0.693 (RA + RB) C
The discharge time (output LOW) by:
t2 = 0.693 x RB x C
Thus the total period T is given by:
T = t1 + t2 = 0.693 (RA + 2RB) C
The frequency of oscillation is then:
1
1.44
f = --- = -------------------------------------T (RA + 2RB )C
The duty cycle is given by:
RB
D = --------------------------RA + 2RB
Figure 7. Timing diagram
W PVGL
Y
28738792/7$*( 9GLY
&$3$&,72592/7$*( 9GL
Y
5$ 5% NŸ& —)5/ NŸ
14/19
DocID4077 Rev 4
TS555
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID4077 Rev 4
15/19
19
Package information
5.1
TS555
SO8 package information
Figure 8. SO8 package outline
Table 11. SO8 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.010
D
4.80
4.90
5.00
0.189
0.193
0.197
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
0.004
0.010
0.049
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
L1
k
ccc
16/19
Inches
1.04
1°
0.040
8°
0.10
DocID4077 Rev 4
1°
8°
0.004
TS555
6
Ordering information
Ordering information
Table 12. Order code table
Order code
Temperature range
Package
Packaging
Marking
TS555IDTTR
-40 °C to 125 °C
SO8
Tape and reel
555I
DocID4077 Rev 4
17/19
19
Revision history
7
TS555
Revision history
Table 13. Document revision history
Date
Revision
01-Feb-2003
1
Initial release.
03-Nov-2008
2
Document reformatted.
Added output current, ESD and thermal resistance values in
Table 1: Absolute maximum ratings.
Added output current values in Table 2: Operating conditions.
29-Aug-2014
3
Section 5: Package information: updated corporate text
Replaced Table 15: Ordering information scheme
4
Features and Description: added footnote to NE555 product to
explain it is terminated.
Removed all references to DIP8 and TSSOP8 packages
Removed all temperature ranges except -40 to 125 °C
Replaced Table 15: Ordering information scheme with Table 12:
Order code table.
24-Jun-2015
18/19
Changes
DocID4077 Rev 4
TS555
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID4077 Rev 4
19/19
19
">