TAS5518 8 Channel Digital Audio PWM Processor Data Manual Literature Number: SLES115
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TAS5518 8 Channel Digital Audio
PWM Processor
Data Manual
Literature Number: SLES115
August 2004
TM
TAS5518
8 Channel Digital Audio PWM Processor
Data Manual
2004 DAV−Digital Audio/Speaker
SLES115
Contents
Section
1 Introduction
1.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAS5518 System Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
1.3
TAS5518 Features
1.2.1
1.2.2
1.2.3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Input/Output
Audio Processing
PWM Processing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.4
General Features
Physical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
1.3.1
1.3.2
Terminal Assignments
Ordering Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3
Terminal Descriptions
TAS5518 Functional Description
1.4.1
1.4.2
1.4.3
1.4.4
I
Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock, PLL, and Serial Data Interface
2
C Serial Control Interface
Device Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
1.7
1.8
1.9
1.5
1.4.5
Digital Audio Processor (DAP)
TAS5518 DAP Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
1.5.2
I
TAS5518 DAP Architecture Diagrams
2
C Coefficient Number Formats
Input Crossbar Mixer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Biquad Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bass and Treble Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Volume, Auto Mute, and Mute
1.9.1
Auto Mute and Mute
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10
Loudness Compensation
1.10.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loudness Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11.2
Compression/Expansion Coefficient Computation Engine Parameters
1.12
Output Mixer
. . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13
PWM
1.13.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Blocking (High Pass Enable/ Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13.2
1.13.3
De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Volume Control (PSVC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13.4
AM Interference Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 TAS5518 Controls and Status
2.1
I
2
C Status Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
2.1.1
2.1.2
General Status Register (0x01)
Error Status Register (0x02)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAS5518 Pin Controls
2.2.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
2.2.3
2.2.4
2.2.5
Power Down (PDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speaker / Headphone Selector (HP_SEL)
Mute (MUTE)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
Page
30
30
31
33
33
26
29
29
30
20
21
21
23
14
18
19
19
35
35
36
36
33
33
33
33
9
11
11
5
8
8
8
9
9
1
2
3
3
3
4
4
5
5
5
July 2004 SLES115
iii
Contents
2.3
2.4
2.5
Device Configuration Controls
2.3.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
2.3.3
Headphone Configuration Registers
Audio System Configurations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4
2.3.5
2.3.6
Recovery from Clock Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Volume Control Enable
Volume and Mute Update Rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.7
2.3.8
Modulation Index Limit
Inter-channel Delay
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Clock and Serial Data Rate Controls
2.4.1
PLL Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Controls
2.5.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
2.5.3
Automatic Bank Selection
Bank Set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
2.5.5
Bank Switch Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Switching Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.6
Bank Switching Example 2
3 Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Performance (At Recommended Operating Conditions at 25°C)
Recommended Operating Conditions (over 0°C to 70°C)
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . .
PWM Operation at Recommended Operating Conditions Over 0°C to 70°C
Switching Characteristics
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
I
Clock Signals Over Recommended Operating Conditions
Serial Audio Port
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Serial Control Port Operation
Reset Timing (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down (PDN) Timing
Backend Error (BKND_ERR)
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
3.6.7
3.6.8
MUTE Timing—MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Headphone Select (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.9
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Audio Interface Control and Timing
3.7.1
I
2
S Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2
Left Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
Right Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 I
2
C Serial Control Interface (Slave Address 0x36)
4.1
General I
2
C Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
4.3
4.4
Single and Multiple Byte Transfers
Single Byte Write
Multiple Byte Write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
4.6
Incremental Multiple Byte Write
Single Byte Read
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Serial Control I
2
C Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
49
49
50
46
46
46
47
45
45
45
46
43
43
44
45
42
42
42
43
40
41
41
42
36
37
38
38
39
39
40
56
57
57
59
55
55
56
56
52
53
54
55
50
51
52
52 iv
SLES115 July 2004
6 Serial Control Interface Register Definitions
6.1
Clock Control Register (0x00)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
6.3
6.4
General Status Register 0 (0x01)
Error Status Register (0x02)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Register 1 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
6.6
6.7
System Control Register 2 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Configuration Control Register (0x05−X0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Headphone Configuration Control Register (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
6.9
Serial Data Interface Control Register (0x0E)
Soft Mute Register (0x0F)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10
Automute Control Register(0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11
Automute PWM Threshold and Backend Reset Period (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12
Modulation Index Limit Register (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13
Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23) . . . . . . . . . .
6.14
Bank Switching Command (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15
Input Mixer Registers (0x41 – 0x48, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16
Bass Management Registers (0x49 – 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17
Biquad Filters Register (0x51 – 0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18
Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . .
6.19
Loudness Registers (0x91 – 0x95)
6.20
DRC1 Control (0x96, Channels 1−7)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21
DRC2 Control (0x97, Channel 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22
DRC1 Data Registers (0x98 – 0x9C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23
DRC2 Data Registers (0x9D – 0xA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24
DRC Bypass Registers (0xA2 – 0xA9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25
8x2 Output Mixer Registers (0xAA – 0xAF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26
8x3 Output Mixer Registers (0xB0 – 0xB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27
Volume Biquad Register (0xCF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28
Volume Treble and Bass Slew Rates (0xD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29
Volume Registers (0xD1 − 0xD9)
6.30
Bass Filter Set Register (0xDA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.31
Bass Filter Index Register (0xDB)
6.32
Treble Filter Set Register (0xDC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.33
Treble Filter Index (0xDD)
6.34
AM Mode Register (0xDE)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.35
PSVC Range Register (0xDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.36
General Control Register (0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.37
Incremental Multiple Write Append Register (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 TAS5518 Example Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
77
78
79
80
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81
83
83
83
84
70
70
71
72
75
75
76
76
77
85
86
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88
88
89
89
91
66
66
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67
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July 2004 SLES115
v
List of Illustrations
List of Illustrations
Figure Title
1−1. TAS5518 Functional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2. Typical TAS5518 Application (DVD Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3. Recommended TAS5518 + TAS5121 Channel Configuration
1−4. TAS5518 DAP Architecture With I
2
C Registers (Fs 3 96 kHz)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5. TAS5518 Architecture With I
2
C Registers (Fs = 176.4 kHz or Fs = 192 kHz) . . . . . . . . . . . . . . . . . . .
1−6. TAS5518 Detailed Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7. 5.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8. Conversion Weighting Factors—5.23 Format to Floating Point
1−9. Alignment of 5.23 Coefficient in 32-Bit I
2
C Word
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−10. 25.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−11. Alignment of 5.23 Coefficient in 32-Bit I
2
C Word
1−12. Alignment of 25.23 Coefficient in Two 32-Bit I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−13. TAS5518 Digital Audio Processing
1−14. Input Crossbar Mixer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−15. Biquad Filter Structure
1−16. Auto Mute Threshold
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−17. Loudness Compensation Functional Block Diagram
1−18. Loudness Example Plots
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−19. DRC Positioning in TAS5518 Processing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−20. Dynamic Range Compression (DRC) Transfer Function Structure . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−21. Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−22. De-emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−23. Power Supply and Digital Gains (Log Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−24. Power Supply and Digital Gains (Linear Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−25. Block Diagrams of Typical Systems Requiring TAS5518 Automatic AM Interference
Avoidance Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1. Slave Mode Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. Start and Stop Conditions Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5. Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6. Error Recovery Timing
3−7. Mute Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8. HP_SEL Timing
3−9. I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
S Format 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10. Left Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11. Right Justified 64 Fs Format
4−1. Typical I
2
C Sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2. Single Byte Write Transfer
4−3. Multiple Byte Write Transfer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4. Single Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5. Multiple Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
15
16
16
17
17
18
19
21
22
23
25
25
29
30
31
31
13
14
15
15
1
2
2
12
51
52
53
54
55
56
56
57
49
49
50
50
32
47
48
48
57 vi
SLES115 July 2004
List of Tables
List of Tables
Table Title
1−1. Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2. TAS5518 Audio Processing Feature Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)
1−4. Bass and Treble Filter Selections
. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5. Linear Gain Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6. Default Loudness Compensation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7. Loudness Function Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8. DRC Recommended Changes From TAS5518 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1. Device Outputs During Reset
2−2. Values Set During Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3. Device Outputs During Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4. Device Outputs During Backend Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5. Description of the Channel Configuration Registers (0x05 to 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6. Recommended TAS5518 Configurations for Texas Instruments Power Stages . . . . . . . . . . . . . . . . .
2−7. Audio System Configuration (General Control Register 0xE0)
2−8. Volume Ramp Rates in ms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9. Inter-Channel Delay Default Values
6−1. Clock Control Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2. General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3. Error Status Register (0X02)
6−4. System Control Register 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−5. System Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6. Channel Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7. Headphone Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−8. Serial Data Interface Control Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−9. Soft Mute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−10. Automute Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−11. Automute PWM Threshold and Backend Reset Period
6−12. Modulation Index Limit Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−13. Interchannel Channel Delay Registers
6−14. Channel Offset Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−15. Bank Switching Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−16. Input Mixer Registers Format (0x41 – 0x48, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−17. Bass Management Registers Format (0x49 – 0x50)
6−18. Biquad Filters Registers Format (0x51 – 0x88)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−19. Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass)
6−20. Bass and Treble Bypass Register Format (0x89−0x90)
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−21. Loudness Registers Format (0x91 – 0x95)
6−22. DCR1 Control (0x96, Channels 1−7)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−23. DRC2 Control (0x97, Channel 8)
6−24. DRC1 Data Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−25. DRC2 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−26. DRC Bypass Registers Format (0xA2−0xA9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−27. Output Mixer Control Register Format (Upper 4 Bytes)
6−28. Output Mixer Control (Lower 4 Bytes)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−29. Output Mixer Control (Upper 4 Bytes)
6−30. Output Mixer Control (Middle 4 Bytes)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
71
72
75
75
69
70
70
70
76
76
67
67
68
68
65
66
66
66
79
80
80
81
76
77
77
78
81
82
37
38
38
40
33
34
35
36
41
65
65
20
22
23
24
9
11
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July 2004 SLES115
vii
List of Tables
6−31. Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−32. Volume Biquad Register Format (Default = All-pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−33. Volume Gain Update Rate (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−34. Treble and Bass Gain Step Size (Slew Rate)
6−35. Volume Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−36. Master and Individual Volume Controls
6−37. Channel 8 Sub Woofer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−38. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and
Left Surround in Eight Channel Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−39. Channel 4 and 3 (Right and Left Rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−40. Channel 7, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−41. Bass Filter Index Register
6−42. Bass Filter Index
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−43. Channel 8 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−44. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right and Left Surround in Eight Channel Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−45. Channel 4 and 3 (Right and Left Rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−46. Channel 7, 2, 1 (Center, Right Front, and Left Front)
6−47. Treble Filter Index Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−48. Treble Filter Index
6−49. AM Mode Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−50. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)
6−51. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
6−52. PSVC Range Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−53. General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
88
88
88
88
89
86
87
87
87
85
85
85
85
86
86
82
83
83
83
83
84
84 viii
SLES115 July 2004
MCLK
XTL_ OUT
XTL_ IN
PLL_FLTM
PLL_FLTP
OSC CAP
SCLK
LRCLK
SDIN1
SDIN2
SDIN3
SDIN4
SDA
SCL
RESET
PDN
MUTE
HP_SEL
BKND_ERR
Introduction
1 Introduction
The TAS5518 is an eight channel digital pulse width a modulator (PWM) that provides superior dynamic range performance and a high level of system integration. The typical dynamic range in a well-designed system is
110 dB and the power supply volume control (PSVC) feature provides up to 24 dB of additional dynamic range at normal listening levels.
The TAS5518 is designed to interface seamlessly with most audio digital signal processors. This device automatically adjusts control configurations in response to clock and data rate changes and idle conditions.
This enables the TAS5518 to provide an easy to use control interface with relaxed timing requirements.
The TAS5518 can drive eight channels of H-bridge power stages. Texas Instruments H-bridge devices
TAS5111, TAS5112, and TAS5182 + FETs are designed to work seamlessly with the TAS5518. The TAS5518 supports both single-ended or bridge-tied load configurations. It also provides a high-performance differential output to drive an external differential input analog headphone amplifier (such as the TPA112).
The TAS5518 uses an AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data.
The 8x over sampling, combined with a 5 th
-order noise shaper, provides a broad flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.
The TAS5518 is a clock slave-only device. It receives MCLK, SCLK, and LRCLK from other system components. It accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs and a 64-Fs bit clock.
Serial
Control
IF
VR_PLL AVDD_PLL AVSS_PLL AVDD_REF VBGAP VRA_PLL VRD_PLL DVDD DVSS AVDD AVSS
Power Supply
Control
8
Digital Audio Processor
0
Det
7
Biquads
Soft
Tone
Soft
Vol
Loud
Comp DRC
0
Det
7
Biquads
Soft
Tone
Soft
Vol
Loud
Comp DRC
0
Det
7
Biquads
Soft
Tone
Soft
Vol
0
Det
7
Biquads
Soft
Tone
Soft
Vol
0
Det
7
Biquads
Soft
Tone
Soft
Vol
0
Det
7
Biquads
Soft
Tone
Soft
Vol
Loud
Comp DRC
Loud
Comp DRC
Loud
Comp DRC
Loud
Comp DRC
0
Det
7
Biquads
Soft
Tone
Soft
Vol
Loud
Comp DRC
0
Det
7
Biquads
Soft
Tone
Soft
Vol
8 4 8
Loud
Comp DRC
2
2
9
Volume
Control
PWM Section
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
DC
Block
De
Emph
Interpo late
SRC NS PWM
8
8
PSVC
Figure 1−1. TAS5518 Functional Structure
PWM_HPP& MR
PWM_HPP & ML
PWM AP& AM1 L Front
PWM AP& AM2 R Front
PWM AP& AM3 L Rear
PWM AP& AM4 R Rear
PWM AP& Am7 Center
PWM AP& AM8 Sub woofer
PWM AP& AM5 L Surround
PWM L Line Out
PWM AP& AM6 R Surround
PWM R Line Out
VALID
PSVC
SLES115 — August 2004 TAS5518
1
Introduction
1.1
TAS5518 System Diagrams
Typical applications for the TAS5518 are 6- to 8-channel audio systems such as DVD receiver or AV receiver.
Figure 1−2 shows the basic system diagram of the DVD receiver.
Power Supply
AM
FM
Tuner
Texas Instruments
Digital Audio Amplifier
TAS5518
DVD Loader
MPEG Decoder
Micro
Front-Panel Controls
Figure 1−2. Typical TAS5518 Application (DVD Receiver)
Figure 1−3 shows the recommended channel configuration when using the TAS5518 with the TAS5121 power
stage. Note that each channel is normally dedicated to a particular function.
RIGHT BACK
SURROUND
+
−
LEFT BACK
SURROUND
+
−
SUBWOOFER
+
−
CENTER
+
−
RIGHT
−
LEFT
−
+
RIGHT
−
+
LEFT
−
TAS5121 TAS5121 TAS5121 TAS5121 TAS5121 TAS5121 TAS5121 TAS5121
Lineout Right
Lineout Left
PWM to Analog
(Line Level)
TAS5518
PWM to Analog
(Headphone Level)
Headphone
Out Right
Headphone
Out Left
SDIN1,2,3,4 (8 chan. PCM)
Figure 1−3. Recommended TAS5518 + TAS5121 Channel Configuration
2
TAS5518 SLES115 — August 2004
Introduction
1.2
TAS5518 Features
1.2.1 Audio Input / Output
• Automatic Master Clock Rate and Data Sample Rate Detection
• Eight Serial Audio Input Channels
• Eight PWM Audio Output Channels Configurable as Six Channels With Stereo Line Out or Eight Channels
• Line Output is a PWM Output to Drive an External Differential Input Operational Amplifier
• Headphone PWM Output to Drive an External Differential Amplifier Like the TPA112
• PWM Outputs Support Single Ended and Bridge Tied Loads
•
32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Sampling Rates
• Data Formats: 16-, 20-, or 24-bit input Data Left, Right and I
2
S,
• 64 x Fs Bit Clock Rate
• 128, 192, 256, 384, 512, and 768 x Fs Master Clock Rates (Up to a Maximum of 50 MHz)
1.2.2 Audio Processing
•
48-Bit Processing Architecture With 76 bits of Precision for Most Audio Processing Features
• Volume Control Range +36 dB to – 127 dB
− Master Volume Control Range of +18 dB to –100 dB
− Eight Individual Channel Volume Control Range of +18-dB to −127-dB
• Programmable Soft Volume and Mute Update Rates
•
Four Bass and Treble Tone Controls with ±18-dB Range, Selectable Corner Frequencies, and 2 nd
Slopes
Order
− L, R, and C
− LS, RS
− LR, RR
− Sub
• Configurable Loudness Compensation
• Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Slopes
•
Seven Bi-quads Per Channel
• Full 8x8 Input Crossbar Mixer. Each Signal Processing Channel Input Can Be Any Ratio of the Eight Input
Channels
• 8x2 Output Mixer – Channels 1−6. Each Output Can Be Any Ratio of Any Two Signal Processed Channels
• 8x3 Output mixer – Channels 7 and 8. Each Output can be Any Ratio of Any Three Signal Processed
Channels
• Three Coefficient Sets Stored on the Device Can be Selected Manually or Automatically (Based on
Specific Data Rates)
•
DC Blocking Filters
• Able to Support a Variety of Bass Management Algorithms
SLES115 — August 2004 TAS5518
3
Introduction
1.2.3 PWM Processing
• 32-Bit Processing PWM Architecture With 40 Bits of Precision
• 8x Oversampling With 5 th
Order Noise Shaping at 32 – 48 kHz, 4x Oversampling at 88.2 kHz, and 96 kHz and 2x Oversampling at 176.4 kHz and 192 kHz
• >110-dB Dynamic Range
• THD+N < 0.1%
• 20 – 20-kHz Flat Noise Floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Rates
• Digital De-emphasis for 32-, 44.1-, and 48-kHz Data Rates
• Flexible Automute Logic With Programmable Threshold and Duration for Noise Free Operation
•
Intelligent AM Interference Avoidance System Provides Clear AM Reception
•
Power Supply Volume Control (PSVC) Support for Enhanced Dynamic Range in High Performance
Applications
• Adjustable Modulation Limit
1.2.4 General Features
• Automated Operation With an Easy to Use Control Interface
• I
2
C Serial Control Slave Interface
• Integrated AM Interference Avoidance Circuitry
• Single 3.3-V Power Supply
• 64-Pin TQFP Package
• 5-V Tolerant Inputs
4
TAS5518 SLES115 — August 2004
1.3
Physical Characteristics
1.3.1 Terminal Assignments
TQFP PACKAGE
(TOP VIEW)
VRA_PLL
PLL_FLT_RET
PLL_FLTM
PLL_FLTP
AVSS
AVSS
VRD_PLL
AVSS_PLL
AVDD_PLL
VBGAP
RESET
HP_SEL
PDN
MUTE
DVDD
DVSS
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17
38
37
36
35
34
42
41
40
39
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33
48
47
46
45
44
43
VR_PWM
PWM_P_4
PWM_M_4
PWM_P_3
PWM_M_3
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VALID
DVSS
BKND_ERR
DVDD
DVSS
DVSS
VR_DIG
Introduction
1.3.2 Ordering Information
TA PLASTIC 64-PIN PQFP (PN)
0°C to 70°C TAS5518PAG
1.3.3 Terminal Descriptions
TERMINAL
NO.
NAME
TOLERANT
1 VRA_PLL
ATION
2 PLL_FLT_RET
3 PLL_FLTM
4 PLL_FLTP
5 AVSS
6 AVSS
AO
AO
AI
P
P
Voltage reference for PLL analog supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices.
PLL external filter return
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL positive input. Connected to PLL_FLT_RTN via an RC network
Analog ground
Analog ground
SLES115 — August 2004 TAS5518
5
Introduction
NO.
TERMINAL
NAME
7 VRD_PLL
6
8
9
10
11
12
13
14
15 DVDD
16 DVSS
17 VR_DPLL
18
19
20
AVSS_PLL
AVDD_PLL
VBGAP
RESET
HP_SEL
PDN
MUTE
OSC_CAP
XTL_OUT
XTL_IN
TAS5518
P
P
P
P
DI
DI
DI
DI
P
P
P
AO
AO
AI
21 RESERVED
22 RESERVED
23 RESERVED
24 SDA
25 SCL
26 LRCLK
27 SCLK
DIO
DI
DI
DI
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices.
Analog ground for PLL. This terminal should reference the same ground as power terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be minimized. The availability of the AVSS terminal allows a designer to use optimizing techniques such as star ground connections, separate ground planes, or other quiet ground distribution techniques to achieve a quiet ground reference at this terminal.
3.3-V analog power supply for PLL This terminal can be connected to the same power source used to drive power terminal DVDD, but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor.
Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference.
Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This terminal must not be used to power external devices.
Pull up System reset input, active low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the
TAS5518 to its default conditions, sets the valid output low, and places the PWM in the hard mute (M) state. Master volume is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a 4−5 ms. device initialization and set the volume at mute.
Pull up Headphone in/out selector. When a logic low is applied, the headphone is selected
(speakers are off). When a logic high is applied, speakers are selected – headphone is off.
Pull up Power down, active low. PDN powers down all logic and stops all clocks whenever a logic low is applied. The internal parameters are preserved through a power down cycle, as long as a RESET is not active. The duration for system recovery from power down is 100 ms.
Pull up Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a logic high) The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
Digital power 3.3-V supply for digital core and most of I/O buffers
Digital ground for digital core and most of I/O buffers
Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital PLL logic. A 0.1−µF low ESR capacitor should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices.
Oscillator capacitor
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5518 via use of an external fundamental mode
crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the
recommended crystal type.
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5518 via use of an external fundamental mode
crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4 for the
recommended crystal type.
Connect to digital ground
Connect to digital ground
Connect to digital ground
I
2
C serial control data interface input / output
I
2
C serial control clock input output
Serial audio data left / right clock (sampling rate clock)
Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data bit clock that is supplied to the serial bit clock to other I
2
S bus.
SLES115 — August 2004
Introduction
NO.
TERMINAL
NAME
28 SDIN4
29
30
31
32 PSVC
33 VR_DIG
34
SDIN3
SDIN2
SDIN1
DVSS
35 DVSS
36 DVDD
37 BKND_ERR
38 DVSS
39 VALID
40 PWM_M_1
41 PWM_P_1
42 PWM_M_2
43 PWM_P_2
44 PWM_M_3
45 PWM_P_3
46 PWM_M_4
47 PWM_P_4
48 VR_PWM
DI
P
P
P
DI
P
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
49 PWM_M_7
50 PWM_P_7
51 PWM_M_8
52 PWM_P_8
53 DVSS_PWM
54 DVDD_PWM
55 PWM_M_5
56 PWM_P_5
57 PWM_M_6
58 PWM_P_6
59 PWM_HPML
60 PWM_HPPL
61 PWM_HPMR
62 PWM_HPPR
P
P
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DI
O
P
DI
DI
5 V
5 V
5 V
5 V
Pulldown Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Pulldown Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Pulldown Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Pulldown Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Power supply volume control PWM output
Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be connected between this terminal and DVSS. This terminal must not be used to power external devices
Digital ground
Digital ground
3.3-V digital power supply
Pull up Active low. A backend error sequence is generated by applying logic low to this terminal. The BKND_ERR results in all system parameters unaffected, while all
H-bridge drive signals going to a hard mute (M) state.
Digital ground
Output indicating validity of PWM outputs active high
PWM 1 output (differential −)
PWM 1 output (differential +)
PWM 2 output (differential −)
PWM 2 output (differential +)
PWM 3 output (differential −)
PWM 3 output (differential +)
PWM 4 output (differential −)
PWM 4 output (differential +)
Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor should be connected between this terminal and DVSS_PWM. This terminal must not be used to power external devices.
PWM 7 (Line out L) output (differential −)
PWM 7 (Line out L) output (differential +)
PWM 8 (Line out R) output (differential −)
PWM 8 (Line out R) output (differential +)
Digital ground for PWM
3.3-V digital power supply for PWM
PWM 5 output (differential −)
PWM 5 output (differential +)
PWM 6 output (differential −)
PWM 6 output (differential +)
PWM left channel headphone (differential −)
PWM left channel headphone (differential +)
PWM right channel headphone (differential −)
PWM right channel headphone (differential +)
SLES115 — August 2004 TAS5518
7
Introduction
NO.
TERMINAL
NAME
63 MCLK DI 5 V Pulldown MCLK is a 3.3-V clock master clock input. The input frequency of this clock can range from 4 MHz to 50 MHz.
64 RESERVED Connect to digital ground
NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output
2. All pullups are 200-µA weak pullups and all pulldowns are 200-µA weak pull downs. The pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive inputs with pull ups must be able to sink 200 µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must be able to source 200 µA, while maintaining a logic ‘1’ drive level.
3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values.
4. 13.5-MHz crystal (HCM49)
1.4
TAS5518 Functional Description
Figure 1−4 shows the TAS5518 functional structure. The next sections describe the TAS5518 functional
blocks:
• Power Supply
• Clock, PLL, and Serial Data Interface
•
Serial Control Interface
•
Device Control
•
Digital Audio Processor (DAP)
• Pulse Width Modulation (PWM) Processor
1.4.1 Power Supply
The power supply section contains supply regulators that provide analog and digital regulated power for various sections of the TAS5518. The analog supply supports the analog PLL, while digital supplies support the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control
(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.
1.4.2 Clock, PLL, and Serial Data Interface
The TAS5518 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts
MCLK, SCLK, and LRCLK as inputs only.
The TAS5518 uses the external crystal to provide a time base for:
• Continuous data and clock error detection and management
• Automatic data rate detection and configuration
• Automatic MCLK rate detection and configuration (automatic bank switching)
• Supporting I
2
C operation/ communication while MCLK is absent
The TAS5518 automatically handles clock errors, data rate changes, and master clock frequency changes without requiring intervention from an external system controller. This feature significantly reduces system complexity and design.
8
TAS5518 SLES115 — August 2004
Introduction
1.4.2.1
Serial Audio Interface
The TAS5518 operates as a slave only / receive only serial data interface in all modes. The TAS5518 has four
PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2,
SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two’s complement format.
The serial data input interface of the TAS5518 can be configured in right justified, I
2
The serial data interface format is specified using the I
2
and word lengths are shown in Table 1−1.
S, or left-justified modes.
C data interface control register. The supported formats
Table 1−1. Serial Data Formats
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
Right justified
Right justified
Right justified
I2S
I2S
I2S
Left Justified
Left Justified
Left Justified
16
20
24
16
20
24
16
20
24
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5518 accepts 32-, 38-, 44.1-, 48-, 88.2-,
96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I
2
S serial data formats using a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz).
The parameters of this clock and serial data interface are I
2
C configurable.
1.4.3 I
2
C Serial Control Interface
The TAS5518 has an I
2
C serial control slave interface (address 0x36) to receive commands from a system controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait states. Since the TAS5518 has a crystal time base, this interface operates even when
MCLK is absent.
The serial control interface supports both single byte and multi-byte read / write operations for status registers and the general control registers associated with the PWM. However, for the DAP data processing registers, the serial control interface also supports multiple byte (4 byte) write operations.
The I
2
C supports a special mode which permits I
2
C write operations to be broken up into multiple data write operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data.
This permits the system to incrementally write large register values without blocking other I
2
C transactions.
In order to use this feature, the first chunk of data is written to the target I
2
C address and each subsequent chunk of data is written to a special append register (0xFE) until all the data is written and a stop bit is sent.
An incremental read operation is not supported.
1.4.4 Device Control
The TAS5518 control section provides the control and sequencing for the TAS5518. The device control provides both high and low level control for the serial control interface, clock and serial data interfaces, digital audio processor, and pulse width modulator sections.
1.4.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio processing functions – soft volume, loudness compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing.
Figure 1−6 shows the TAS5518 DAP architecture.
SLES115 — August 2004 TAS5518
9
Introduction
The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section.
The DAP supports two configurations, one for 32-kHz – 96-kHz data and one for 176.4-kHz to 192-kHz data.
1.4.5.1
TAS5518 Audio Processing Configurations
The 32 − 96 kHz configuration supports eight channels of data processing that can be configured as eight channels or six channels with two channels for separate stereo line outputs.
The 176.4 − 192 kHz configuration supports three channels of signal processing with five channels passed though (or derived from the three processed channels).
To efficiently support the processing requirements of both multi-channel 32 – 96-kHz data and the two channel
176.4 and 192-kHz data, the TAS5518 supports separate audio processing features for 32 –96-kHz data rates and for 176.4 and 192 kHz. See Table 2 for a summary of TAS5518 processing feature sets.
1.4.5.2
TAS5518 Audio Signal Processing Functions
The DAP provides 10 primary signal processing functions.
1. The data processing input has a full 8x8 input crossbar mixer. This enables each input to be any ratio of the eight input channels.
2. Two I
2
C programmable threshold detectors in each channel support auto mute.
3. Seven biquads per channel
4. Four soft bass and treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes. In 8-channel mode, bass and treble controls are normally configured as follows:
− Bass and Treble 1: Channel 1 (Left), Channel 2 (Right), and Channel 7 (Center)
− Bass and Treble 2: Channel 3 (Left Surround) and Channel 4 (Right Surround)
− Bass and Treble 3: Channel 5 (Left Back Surround) and Channel 6 (Right Back Surround)
− Bass and Treble 4: Channel 8 (Subwoofer)
5. Individual channel and master volume controls. Each control provides an adjustment range of +18 dB to
–127 dB. This permits a total volume device control range of +36 dB to –127 dB plus mute. The master volume control can be configured to control six or eight channels. The DAP soft volume and mute update interval is I
2
C programmable. The update is performed at a fixed rate regardless of the sample rate.
6. Programmable loudness compensation that is controlled via the combination of the master and individual volume settings.
7. Two dual-threshold dual-rate dynamic range compressors (DRCs). The volume gain values are provided used as input parameters using the maximum RMS (master volume x individual channel volume).
8. 8x2 output mixer (channels 1−6). Each output can be any ratio of any two signal processed channels.
9. 8x3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal processed channels.
10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample rate dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These can be set to be automatically selected for one or more data sample rates or can be manually selected under I
2
C program control. This feature enables coefficients for different sample rates to be stored in the TAS5518 and then select when needed.
10
TAS5518 SLES115 — August 2004
Introduction
FEATURE
Table 1−2. TAS5518 Audio Processing Feature Sets
32 − 96 kHz
8 CHANNEL FEATURE SET
32 − 96 kHz
6 + 2 LINE OUT FEATURE SET
176.4- AND 192-kHz
FEATURE SET
Signal processing channels
Pass through channels
Master volume
Individual channel volume controls
8
1 for eight channels
N/A
8
6 + 2
1 for six channels
3
5
1 for three channels
3
Bass and treble tone controls
Four Bass and Treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes
L, R and C (Ch 1, 2, and 7)
LS, RS (Ch 3 and 4)
LBS, RBS (Ch 5 and 6)
Sub (Ch 8)
Four Bass and Treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes
L, R and C (Ch 1, 2, and 7)
LS, RS (Ch 3 and 4)
Sub, (Ch 8)
Line L and R (Ch 5 and 6)
DRC1 for seven satellites and DRC2 for sub
56
DRC1 for five satellites and DRC2 for sub (Ch 5 and 6 Uncompressed)
Two Bass and Treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd order slopes
L and R (Ch 1 and 2)
Sub (Ch 8)
Biquads
Dynamic range compressors
Input output mapping/mixing
Each of the eight signal-processing channels input can be any ratio of the eight input channels.
Each of the eight outputs can be any ratio of any two processed channels.
21
DRC1 for two satellites and DRC2 for sub
Each of the three signal-processing channels or the five pass-though channels inputs can be any ratio of the eight input channels.
Each of the eight outputs can be any ratio of any of the three processed or five bypass channels.
DC blocking filters
(Implemented in PWM
Section)
Digital de-emphasis
(Implemented in PWM
Section)
Loudness
Number of Coefficient sets Stored
Eight channels for 32 kHz, 44.1 kHz, and 48 kHz
Eight channels
Six channels for 32 kHz, 44.1 kHz, and 48 kHz
Three additional coefficient sets can be stored in memory
1.5
TAS5518 DAP Architecture
1.5.1 TAS5518 DAP Architecture Diagrams
Eight channels
Six channels
N/A
Three channels
Figure 1−4 shows the TAS5518 DAP architecture for Fs = 96 kHz. Note the TAS5518 bass management
architecture shown in channels 1, 2, 7, and 8. Note that the I configure the TAS5518.
2
C registers are shown to help the designer
2, and 8 contain all the features. Channels 3−7 are pass-through except for master volume control.
for channels 7 and 8.
SLES115 — August 2004 TAS5518
11
Introduction
Default input is BOLD
SDIN1−L(L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
B
E
F
G
H
A
B
C
D
G
H
E
F
C
D
IP Mixer 1
(I2C 0x41)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 2
(I2C 0x42)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 3
(I2C 0x43)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R(RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 4
(I2C 0x44)
7 DAP1
BQ
(0x51−
0x57)
Bass &
Treble 1
(0xDA−
0xDD)
7 DAP2
BQ
(0x58−
0x5E)
Master Vol
(0xD9)
Max Vol
DAP1
Volume
(0xD1)
Master Vol
(0xD9)
Loud− ness
(0x91−
0x95)
Max Vol
Bass &
Treble 1
(0xDA−
0xDD)
DAP2
Volume
(0xD2)
Master Vol
(0xD9)
Loud− ness
(0x91−
0x95)
Max Vol
7 DAP3
BQ
(0x5F−
0x65)
Bass &
Treble 2
(0xDA−
0xDD)
DAP3
Volume
(0xD3)
Loud− ness
(0x91−
0x95)
Master Vol
(0xD9)
Max Vol
7 DAP4
BQ
(0x66−
0x6C)
Bass &
Treble 2
(0xDA−
0xDD)
DAP4
Volume
(0xD4)
Loud− ness
(0x91−
0x95)
Master Vol
(0xD9)
Max Vol
7 DAP5
BQ
(0x6D−
0x73)
Bass &
Treble 3
(0xDA−
0xDD)
7 DAP6
BQ
(0x74−
0x7A)
Bass &
Treble 3
(0xDA−
0xDD)
DAP5
Volume
(0xD5)
Loud− ness
(0x91−
0x95)
Master Vol
(0xD9)
Max Vol
DAP6
Volume
(0xD6)
Loud− ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
OP Mixer 1
(I2C 0xAA)
8X2 Output
Mixer
L to
PWM1
DRC1
(0x96−
0x9C)
OP Mixer 2
(I2C 0xAB)
8X2 Output
Mixer
R to
PWM2
DRC1
(0x96−
0x9C)
OP Mixer 3
(I2C 0xAC)
8X2 Output
Mixer
LS to
PWM3
DRC1
(0x96−
0x9C)
OP Mixer 4
(I2C 0xAD)
8X2 Output
Mixer
RS to
PWM4
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L(LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 5
(I2C 0x45)
A
B
E
F
G
H
A
B
C
D
G
H
E
F
C
D
IP Mixer 6
(I2C 0x46)
Coeff = 0 (lin)
(I2C 0x4E)
DRC1
(0x96−
0x9C)
OP Mixer 5
(I2C 0xAE)
8X2 Output
Mixer
LBS to
PWM5
DRC1
(0x96−
0x9C)
OP Mixer 6
(I2C 0xAF)
8X2 Output
Mixer
RBS to
PWM6
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L(C)
SDIN4−R (LFE)
A
B
E
F
G
H
A
B
C
D
G
H
E
F
C
D
IP Mixer 7
(I2C 0x47)
2 DAP7
BQ
(0x7B−
0x7C)
Coeff = 0 (lin)
(I2C 0x4B)
Coeff = 1 (lin)
(I2C 0x4D)
5 DAP7
BQ
(0x7D−
0x81)
Bass &
Treble 1
(0xDA−
0xDD)
Master Vol
(0xD9)
Max Vol
DAP7
Volume
(0xD7)
Loud− ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
OP Mixer 7
(I2C 0xB0)
8X3 Output
Mixer
C to
PWM7
Coeff = 0 (lin)
(I2C 0x4C)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L (C)
SDIN4−R(LFE)
Coeff = 0 (lin)
(I2C 0x49)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 8
(I2C 0x48)
2 DAP8
BQ
(0x82−
0x83)
(I2C 0x50)
Coeff = 1 (lin)
Coeff = 0 (lin)
(I2C 0x4A)
5 DAP8
BQ
(0x84−
0x88)
Bass &
Treble 4
(0xDA−
0xDD)
Master Vol
(0xD9)
Max Vol
DAP8
Volume
(0xD8)
Loud− ness
(0x91−
0x95)
DRC2
(0x9D−
0xA1)
OP Mixer 8
(I2C 0xB1)
8X3 Output
Mixer
Sub to
PWM8
Coeff = 0 (lin)
(I2C 0x4F)
Figure 1−4. TAS5518 DAP Architecture With I
2
C Registers (Fs ≤ 96 kHz)
12
TAS5518 SLES115 — August 2004
Introduction
Default input is BOLD
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
B
E
F
G
H
C
D
A
B
G
H
E
F
C
D
IP Mixer 1
(I2C 0x41)
8 X 8
Crossbar
Input Mixer
G
H
A
B
E
F
G
H
C
D
A
B
C
D
E
F
IP Mixer 2
(I2C 0x42)
8 X 8
Crossbar
Input Mixer
7 DAP1
BQ
(0x51−
0x57)
7 DAP2
BQ
(0x58−
0x5E)
Bass &
Treble 1
(0xDA−
0xDD)
Bass &
Treble 1
(0xDA−
0xDD)
Master Vol
(0xD9)
DAP1
Volume
(0xD1)
Master Vol
(0xD9)
DAP2
Volume
(0xD2)
Max Vol
Loud− ness
(0x91−
0x95)
Max Vol
Loud− ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
DRC1
(0x96−
0x9C)
OP Mixer 1
(I2C 0xAA)
8X2 Output
Mixer
OP Mixer 2
(I2C 0xAB)
8X2 Output
Mixer
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 3
(I2C 0x43)
8 X 8
Crossbar
Input Mixer
Master Vol
(0xD9)
OP Mixer 3
(I2C 0xAC)
8X2 Output
Mixer
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 4
(I2C 0x44)
8 X 8
Crossbar
Input Mixer
Master Vol
(0xD9)
OP Mixer 4
(I2C 0xAD)
8X2 Output
Mixer
Master Vol
(0xD9)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 5
(I2C 0x45)
8 X 8
Crossbar
Input Mixer
OP Mixer 5
(I2C 0xAE)
8X2 Output
Mixer
Master Vol
(0xD9)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS
SDIN4−L (C)
SDIN4−R (LFE)
)
G
H
A
B
E
F
G
H
A
B
C
D
E
F
C
D
IP Mixer 6
(I2C 0x46)
8 X 8
Crossbar
Input Mixer
OP Mixer 6
(I2C 0xAF)
8X2 Output
Mixer
Master Vol
(0xD9)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
B
E
F
G
H
A
B
C
D
G
H
E
F
C
D
IP Mixer 7
(I2C 0x47)
8 X 8
Crossbar
Input Mixer
G
H
A
B
E
F
G
H
A
B
C
D
C
D
E
F
IP Mixer 8
(I2C 0x48)
8 X 8
Crossbar
Input Mixer
2 DAP8
BQ
(0x82−
0x83)
5 DAP8
BQ
(0x84−
0x88)
Bass &
Treble 4
(0xDA−
0xDD)
Master Vol
(0xD9)
DAP8
Volume
(0xD8)
Max Vol
Loud− ness
(0x91−
0x95)
DRC2
(0x9D−
0xA1)
OP Mixer 7
(I2C 0xB0)
8X3 Output
Mixer
OP Mixer 8
(I2C 0xB1)
8X3 Output
Mixer
Figure 1−5. TAS5518 Architecture With I
2
C Registers (Fs = 176.4 kHz or Fs = 192 kHz)
L to
PWM1
R to
PWM2
LS to
PWM3
RS to
PWM4
LBS to
PWM5
RBS to
PWM6
C to
PWM7
Sub to
PWM8
SLES115 — August 2004 TAS5518
13
Introduction
Left
SDIN1
Right
A
B
A_to_ipmix
Left
SDIN2
Right
C
D
D_to_ipmix
E_to_ipmix
Left
SDIN3
E
F
Right
F_to_ipmix
G_to_ipmix
Left
SDIN4
G
H
Right
H_to_ipmix
Input Mixer
7 Biquads in Series
Master
Volume
Channel
Volume
Bass and Treble
Bypass
Bass and
Treble
Bass and Treble
In-Line
Pre-
Volume
DRC
Max
Volume
Loudness
Post-
Volume
DRC
Bypass
Output
Gain
Output Mixer Sums
Any Two Channels
DRC
In-Line
1 Other
Channel Output
From 7 Available
32−Bit
Trunc
PWM
Proc
Volume
PWM
Output
Figure 1−6. TAS5518 Detailed Channel Processing
1.5.2 I
2
C Coefficient Number Formats
The architecture of the TAS5518 is contained in ROM resources within the TAS5518 and cannot be altered.
However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I
2
C bus interface, provide a user with the flexibility to set the TAS5518 to a configuration that achieves the system level goals.
The firmware is executed in a 48-bit signed fixed-point arithmetic machine. The most significant bit of the 48-bit data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented by multiplying a 48-bit signed data value by a 28-bit signed gain coefficient. The 76-bit signed output product is then truncated to a signed 48-bit number. Level offset operations are implemented by adding a 48-bit signed offset coefficient to a 48-bit signed data value. In most cases, if the addition results in overflowing the 48-bit signed number format, saturation logic is used. This means that if the summation results in a positive number that is greater than 0x7FFF_FFFF_FFFF (the spaces are used to ease the reading of the hexadecimal number), the number is set to 0x7FFF_FFFF_FFFF. If the summation results in a negative number that is less than
0x8000_0000_0000 0000, the number is set to 0x8000_0000_0000 0000.
14
TAS5518 SLES115 — August 2004
Introduction
1.5.2.1
28-Bit 5.23 Number Format
All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23
numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in the Figure 1−7.
2
−23
Bit
2
−4
Bit
2
−1
Bit
2
0
Bit
2
3
Bit
Sign Bit
S_xxxx.xxxx_xxxx_xxxx_xxxx_xxx
Figure 1−7. 5.23 Format
the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
magnitude of the negative number.
2
3
Bit 2
2
Bit 2
0
Bit 2
−1
Bit 2
−4
Bit 2
−23
Bit
(1 or 0) x 2
3
+ (1 or 0) x 2
2
+ … + (1 or 0) x 2
0
+ (1 or 0) x 2
−1
+ … + (1 or 0) x 2
−4
+ … + (1 or 0) x 2
−23
Figure 1−8. Conversion Weighting Factors—5.23 Format to Floating Point
Gain coefficients, entered via the I
2
C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 1−9.
Sign
Bit
Fraction
Digit 6
Integer
Digit 1
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
0 u u u u S x x x x. x x x x x x x x x x x x x x x x x x x x x x x
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1 u = unused or don’t care bits
Digit = hexadecimal digit
Figure 1−9. Alignment of 5.23 Coefficient in 32-Bit I
2
C Word
hex value of the fractional part of the gain coefficient to form the 32-bit I
2
C coefficient. The reason is that the
28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower
3 bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the zero-valued most significant hex digit).
SLES115 — August 2004 TAS5518
15
Introduction
1.5.2.2
48-Bit 25.23 Number Format
All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. Numbers formatted as 25.23 numbers means that there are 25 bits to the left of the decimal point and 23 bits to the right
of the decimal point. This is shown in Figure 1−10.
2
−23
Bit
2
−10
Bit
2
−1
Bit
2
0
Bit
2
16
Bit
2
22
Bit
2
23
Bit
Sign Bit
S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
Figure 1−10. 25.23 Format
Figure 1−11 shows the derivation of the decimal value of a 48-bit 25.23 format number.
2
23
Bit 2
22
Bit 2
0
Bit 2
−1
Bit 2
−23
Bit
(1 or 0) x 2
23
+ (1 or 0) x 2
22
+ … + (1 or 0) x 2
0
+ (1 or 0) x 2
−1
+ … + (1 or 0) x 2
−23
Figure 1−11. Alignment of 5.23 Coefficient in 32-Bit I
2
C Word
Two 32-bit words must be sent over the I
The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I
2
C bus to download a level or threshold coefficient into the TAS5518.
2
C word is shown in
16
TAS5518 SLES115 — August 2004
Introduction
u u u u u u u u u u u u
Sign
Bit
Integer
Digit 4
(Bits 2
3
− 2
1
) u u u u
Integer
Digit 1
S x x x
Integer
Digit 2 x x x x
Integer
Digit 3 x x x x x x x x
Word 1
(Most
Significant
Word)
Coefficient
Digit 16
Coefficient
Digit 15
Coefficient
Digit 14
Coefficient
Digit 13
Coefficient
Digit 12
Coefficient
Digit 11
Coefficient
Digit 10
Coefficient
Digit 9
Integer
Digit 4
(Bit 2
0
)
Fraction
Digit 6 x
Integer
Digit 5 x x x
Integer
Digit 6 x x x x
Fraction
Digit 1 x. x x x
Fraction
Digit 2 x x x x
Fraction
Digit 3 x x x x
Fraction
Digit 4 x x x x
Fraction
Digit 5 x x x x
0 x x x x
Word 2
(Least
Significant
Word)
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1 u = unused or don’t care bits
Digit = hexadecimal digit
Figure 1−12. Alignment of 25.23 Coefficient in Two 32-Bit I
2
C Words
1.5.2.3
TAS5518 Audio Processing
The TAS5518 digital audio processing is designed such that noise produced by filter operations is maintained
increasing the precision of the signal representation substantially above the number of bits that are absolutely necessary to represent the input signal.
Ideal Input Possible Outputs Desired Output
Maximum Signal
Amplitude
Overflow
Values retained by overflow bits
Signal bits input
Filter
Operation
Reduced
SNR signal output
Signal bits output
Noise Floor with no additional precision
Figure 1−13. TAS5518 Digital Audio Processing
Noise Floor as a result of additional precision
SLES115 — August 2004 TAS5518
17
Introduction
Similarly, the TAS5518 carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5518 advanced digital audio processor achieves both of these important performance capabilities by using a high performance digital audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator.
1.6
Input Crossbar Mixer
The TAS5518 has a full 8x8 input crossbar mixer. This mixer permits each signal processing channel input to be any ratio of any of the eight input channels. The control parameters for the input crossbar mixer are programmable via the I
2
C interface. See the Input Mixer Register (0x41−0x48, channels 1−8) section.
Gain Coefficient
28
Input 1
48
Gain Coefficient
28
48
Input 2
SUM
48 48
Gain Coefficient
28
48
Input 8
48
Figure 1−14. Input Crossbar Mixer
18
TAS5518 SLES115 — August 2004
Introduction
1.7
Biquad Filters
For 32-kHz to 96-kHz data, the TAS5518 provides 56 biquads across the eight channels (seven per channel)
For 176.4-kHz and 192-kHz data, the TAS5518 has 21 biquads across the three channels (seven per channel). All of the biquad filters are second order direct form I structure.
The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number) and a signed 28-bit coefficient (5.23 format number). The 76-bit ALU in the TAS5518 allows the 76-bit resolution to be retained when summing the mixer outputs (filter products).
The five 28-bit coefficients for the each of the 56 biquads are programmable via the I
2
C interface. See
Magnitude
Truncation
Z −1
Z −1
Figure 1−15. Biquad Filter Structure
All five coefficients for one biquad filter structure are written to one I
2
C register containing 20 bytes (or five
32-bit words). The structure is the same for all biquads in the TAS5518. Registers 0x51 – 0x88 show all the biquads in the TAS5518. Note that u(31:28) bits are unused and default to 0x0.
Table 1−3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)
DESCRIPTION REGISTER FIELD CONTENTS
b o
Coefficient b
1
Coefficient b
2
Coefficient a
1
Coefficient a
2
Coefficient u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0) u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0) u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0) u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)
1.8
Bass and Treble Controls
INITIALIZATION GAIN COEFFICIENT VALUE
DECIMAL HEX
1.0
0.0
0.0
0.0
0.0
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
From 32-kHz to 96-kHz data, the TAS5518 has four Bass and Treble tone controls. Each control has a ±18-dB control range with selectable corner frequencies and 2nd order slopes. These controls operate four channel groups:
•
L, R & C (Channels 1, 2, and 7)
• LS, RS (Channels 3 and 4)
• LBS, RBS (or alternately called L and R Lineout.) (Channels 5 and 6)
• Sub (Channel 8)
SLES115 — August 2004 TAS5518
19
Introduction
For 176.4 kHz and 192 kHz data, the TAS5518 has two Bass and Treble tone controls. Each control has a
±18-dB I
2
C control range with selectable corner frequencies and 2nd order slopes. These controls operate two channel groups:
• L & R
•
Sub
The bass and treble filters utilize a soft update rate that does not produce artifacts during adjustment.
Table 1−4. Bass and Treble Filter Selections
FS
(kHz)
3-dB CORNER FREQUENCIES
32
38
44.1
48
88.2
96
176.4
192
FILTER
SET 1
BASS
63
115
125
42
49
57
230
250
FILTER
SET 1
TREBLE
917
1088
1263
1375
2527
2750
5053
5500
FILTER
SET 2
BASS
83
99
115
125
230
250
459
500
FILTER
SET 2
TREBLE
1833
2177
2527
2750
5053
5500
10106
11000
FILTER
SET 3
BASS
125
148
172
188
345
375
689
750
FILTER
SET 3
TREBLE
3000
3562
4134
4500
8269
9000
16538
18000
The I
2
C registers that control Bass and Treble are:
• Bass and Treble By-Pass Register (0x89 – 0x90, channels 1−8)
• Bass and Treble Slew Rates (0xD0)
• Bass Filter Sets 1−5 (0xDA)
• Bass Filter Index (0xDB)
• Treble Filter Sets 1−5 (0xDC)
• Treble Filter Index (0xDD)
FILTER
SET 4
BASS
146
173
201
219
402
438
804
875
FILTER
SET 4
TREBLE
3667
4354
5053
5500
10106
11000
20213
22000
FILTER
SET 5
BASS
167
198
230
250
459
500
919
1000
FILTER
SET 5
TREBLE
4333
5146
5972
6500
11944
13000
23888
26000
1.9
Volume, Auto Mute, and Mute
The TAS5518 provides individual channel and master volume controls. Each control provides an adjustment range of +18.0618 dB to –100 dB in 0.25 dB increments. This permits a total volume device control range of
+36 dB to –100 dB plus mute. The master volume control can be configured to control six or eight channels.
The TAS5518 has a master soft mute control that can be enabled by a terminal or I
2 also has individual channel soft mute controls that can are enabled via I
2
C.
C command. The device
The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft gain linear update with an I
2
C programmable linear step size at a fixed temporal rate. The linear soft gain step size can be varied from 0.5 to 0.003906.
Table 1−5. Linear Gain Step Size
STEP SIZE (GAIN)
Time to go from 36.124 db to −127 dB in ms
Time to go from 18.062 db to −127 dB in ms
Time to go from 0 db to −127 dB in ms
0.5
0.25
10.67
21.33
1.33
0.17
2.67
0.33
0.125
42.67
5.33
0.67
0.0625
85.34
10.67
1.33
0.03125
0.015625
0.007813
0.003906
170.67
341.35
682.70
1365.4
21.33
2.67
42.67
5.33
85.33
10.67
170.67
21.33
20
TAS5518 SLES115 — August 2004
Introduction
1.9.1 Auto Mute and Mute
The TAS5518 has individual channel automute controls that are enabled via the I
2 separate detectors used to trigger the automute:
C interface. There are two
• Input Auto Mute: All channels are muted when all 8 inputs to the TAS5518 are less in magnitude than the input threshold value for a programmable amount of time.
• Output Auto Mute: A single channel is muted when the output of the DAP section is less in magnitude than the input threshold value for a programmable amount of time.
The detection period and thresholds for these two detectors are the same.
This time interval is selectable via I value is mask programmable.
2
C to be from 1 ms. to 110 ms. The increments of time are 1, 2, 3, 4, 5, 10,
20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default
The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is adjustable via I
2
C. The range of the input threshold adjustment is from below the LSB (bit position 0) to below bit position
12 in a 24 bit input data word (bit positions 8 to 20 in the DSPE). This provides an input threshold that can be adjusted for 12 to 24 bits of data. The default value is mask programmable.
DVD Data Range
CD Data Range
24-Bit Input
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32-Bit in DSPE
Representation
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Threshold Range
Figure 1−16. Auto Mute Threshold
The auto mute state is exited when the TAS5518 receives one sample that is greater that the output threshold.
The output threshold can be one of two values:
• Equal to the input threshold
• 6 dB (one bit position) greater than the input threshold
The value for the output threshold is selectable via I
2
C. The default value is mask programmable.
The system latency enables the data value that is above the threshold to be preserved and output.
A mute command initiated by automute, master mute, individual I
2
C mute, the AM interference mute sequence, or the bank switch mute sequence overrides an unmute command or a volume command. While a mute command is activated, the commanded channels transition to the mute state. When a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel.
1.10 Loudness Compensation
The loudness compensation function compensates for the Fletcher-Munson loudness curves. The TAS5518 loudness implementation tracks the volume control setting to provide spectral compensation for weak low or high frequency response at low volume levels. For the volume tracking function both linear and log control laws can be implemented. Any biquad filter response can be used to provide the desired loudness curve. The control parameters for the loudness control are programmable via the I
2
C interface.
SLES115 — August 2004 TAS5518
21
Introduction
The TAS5518 has a single set of loudness controls for the eight channels. In 6-channel mode loudness is available to the six speaker outputs and also the line outputs. The loudness control input uses the Maximum individual master volume (V) to control the loudness that is applied to all channels. In 192-kHz and 176.4-kHz modes, the loudness function is active only for channels 1, 2, and 8.
V
Audio In
+ x
Audio Out
Loudness
Biquad
H(Z)
x x
Loudness Function = f (V)
V
Figure 1−17. Loudness Compensation Functional Block Diagram
Loudness Function = f (V) = G x [2
[(Log V) x LG + LO]
] + O or alternatively,
Loudness Function = f (V) = G x [V
LG
x 2
LO
] + O
For example, for the default values LG = −0.5, LO = 0.0, G = 1.0, and O = 0.0 then:
Loudness Function = 1 / SQRT (V) which is the recommended transfer function for loudness. So,
Audio Out = (Audio In) x V + H (Z) x SQRT (V). Other transfer functions are possible.
Table 1−6. Default Loudness Compensation Parameters
I
2
C
DEFAULT
TERM FORMAT
V
Log V
H (Z)
LG
LO
G
O
Max volume
Log
2
(max volume)
Loudness biquad
Gain (log space)
Offset (log space)
Gain
Offset
Gains audio
Loudness function
Controls shape of
Loudness curves
Loudness function
Loudness function
Switch to enable
Loudness (ON = 1,
OFF = 0)
Provides offset
5.23
5.23
5.23
5.23
25.23
5.23
25.23
RESS
NA
NA
0x95
0x91
0x92
0x93
0x94
HEX
NA
00000000 b0 = 0000D513 b1 = 00000000 b2 = 0FFF2AED a1 = 00FE5045 a2 = 0F81AA27
FFC00000
00000000
00000000
00000000
FLOAT
NA
0.0
b0 = 0.006503
b1 = 0 b2 = −0.006503
a1 = 1.986825
a2 = −0.986995
−0.5
0
0
0
22
TAS5518 SLES115 — August 2004
Introduction
1.10.1
Loudness Example
Problem: Due to the Fletcher-Munson phenomena, we want to compensate for low frequency attenuation near
60 Hz. The TAS5518 provides a loudness transfer function with EQ gain = 6, EQ center frequency = 60 Hz, and EQ bandwidth = 60 Hz.
TERM
H (Z)
LG
LO
G
O
Solution: Using Texas Instruments ALE TAS5518 DSP tool, Matlab, or other signal-processing tool, develop a loudness function with following parameters:
Table 1−7. Loudness Function Parameters
Loudness Biquad
Loudness Gain
Loudness Offset
Gain
Offset
Controls shape of loudness curves
Loudness function
Loudness function
Switch to Enable
Loudness (ON = 1,
OFF = 0)
Offset
FORMAT
5.23
5.23
25.23
5.23
25.23
I
2
C
SUBADDRESS
0x95
0x91
0x92
0x93
0x94
EXAMPLE VALUES
HEX FLOAT
b0 = 00008ACE b1 = 00000000 b2 = FFFF7532 a1 = FF011951 a2 = 007EE914
FFC00000
00000000
00800000 b0 = 0.004236
b1 = 0 b2 = −0.004236
a1 = −1.991415
a2 = 0.991488
−0.5
0
1
00000000 0
See Figure 1−18 for the resulting loudness function at different gains.
SLES115 — August 2004
Figure 1−18. Loudness Example Plots
TAS5518
23
Introduction
1.11 Dynamic Range Control (DRC)
The DRC provides both compression and expansion capabilities over three separate and definable regions of audio signal levels. Programmable threshold levels set the boundaries of the three regions. Within each of the three regions a distinct compression or expansion transfer function can be established and the slope of each transfer function is determined by programmable parameters. The offset (boost or cut) at the two boundaries defining the three regions can also be set by programmable offset coefficients. The DRC implements the composite transfer function by computing a 5.23 format gain coefficient from each sample output from the rms estimator. This gain coefficient is then applied to a mixer element, whose other input is the audio data stream. The mixer output is the DRC-adjusted audio data.
There are two distinct DRC blocks in the TAS5518. DRC1 services channels 1−7 in the 8-channel mode and channels 1−4, and 7 in the 6-channel mode. This DRC computes rms estimates of the audio data streams on all channels that it controls. The estimates are then compared on a sample-by-sample basis and the larger of the estimates is used to compute the compression/expansion gain coefficient. The gain coefficient is then applied to appropriate channels audio stream. DRC2 services only channel 8. This DRC also computes an rms estimate of the signal level on channel 8 and this estimate is used to compute the compression/expansion gain coefficient applied to the channel 8 audio stream.
shows the recommended time constants and their HEX values. If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It will then output the TAS5518 hex coefficients for download to the TAS5518.
I
2
C
SUBADDRESS
0x98
0x9C
0x9D
0xA1
Table 1−8. DRC Recommended Changes From TAS5518 Defaults
REGISTER FIELDS
DRC1 energy
DRC1 (1 – energy)
DRC1 attack
DRC1 (1 – attack)
DRC1 decay
DRC1 (1 – decay)
DRC2 energy
DRC2 (1 – energy)
DRC2 attack
DRC2 (1 – attack)
DRC2 decay
DRC2 (1 – decay)
RECOMMENDED TIME
CONSTANT (MS)
5
5
2
5
5
2
RECOMMENDED
HEX VALUE
0000883F
007F77C0
0000883F
007F77C0
0001538F
007EAC70
0000883F
007F77C0
0000883F
007F77C0
0001538F
007EAC70
DEFAULT HEX
0000883F
007F77C0
0000883F
007F77C0
000000AE
007FFF51
0000883F
007F77C0
0000883F
007F77C0
000000AE
007FFF51
Recommended DRC set-up flow if the defaults are used:
• After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See
• Enable either the pre-volume or post-volume DRC
Recommended DRC set-up flow if the DRC design uses values different from the defaults:
• After power up, load all DRC coefficients per the DRC design.
•
Enable either the pre-volume or post-volume DRC
can come from either before or after soft volume control and loudness processing.
24
TAS5518 SLES115 — August 2004
Introduction
Master
Volume
Channel
Volume
Bass & Treble
By-Pass
Max
Volume
DRC
By-Pass
From Input Mixer
7 Biquads in Series
Bass and
Treble
Bass & Treble
In-Line
Pre-
Volume
Post-
Volume
DRC
In-Line
DRC
Figure 1−19. DRC Positioning in TAS5518 Processing Flow
Figure 1−20 illustrates a typical DRC transfer function.
Region
0
Region
1
Region
2 k2 k1
Loudness
To Output
Mixer
1:1 Transfer Function
Implemented Transfer Fucntion k0
O2
O1
T1 T2
DRC Input Level
Figure 1−20. Dynamic Range Compression (DRC) Transfer Function Structure
The three regions shown in Figure 1−20 are defined by three sets of programmable coefficients:
•
Thresholds T1 and T2—define region boundaries.
• Offsets O1 and O2—define the DRC gain coefficient settings at thresholds T1 and T2 respectively.
• Slopes k0, k1, and k2—define whether compression or expansion is to be performed within a given region.
The magnitudes of the slopes define the degree of compression or expansion to be performed.
The three sets of parameters are all defined in logarithmic space and adhere to the following rules:
•
The maximum input sample into the DRC is referenced at 0 dB. All values below this maximum value then have negative values in logarithmic (dB) space.
• The samples input into the DRC are 32-bit words and consist of the upper 32 bits of the 48-bit word format used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial data received at the serial audio receive port by adding 8 bits of headroom above the 32-bit word and 8 bits of computational precision below the 32-bit word. If the audio processing steps between the SAP input and the DRC input result in no accumulative boost or cut, the DRC would operate on the 8 bits of headroom and the 24 MSBs of the audio sample. Under these conditions, a 0-dB (maximum value) audio sample
(0x7FFFFFFF) is seen at the DRC input as a –48-dB sample (8 bits x −6.02 dB/bit = −48 dB).
SLES115 — August 2004 TAS5518
25
Introduction
•
Thresholds T1 and T2 define, in dB, the boundaries of the three regions of the DRC, as referenced to the rms value of the data into the DRC. Zero valued threshold settings reference the maximum valued rms input into the DRC and negative valued thresholds reference all other rms input levels. Positive valued thresholds have no physical meaning and are not allowed. In addition, zero valued threshold settings are not allowed.
Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of the
DAP. The 32-bit samples input into the DRC are placed in the upper 32 bits of this 48-bit word space. This means that the threshold settings must be programmed as 48-bit (25.23 format) numbers.
CAUTION: Zero valued and positive valued threshold settings are not allowed and cause unpredictable behavior if used.
• Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain coefficient at the threshold points T1 and T2 respectively. Positive offsets are defined as cuts, and thus boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23 format) numbers.
• Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23 format) numbers.
1.11.1 DRC Implementation
The three elements comprising the DRC: (1) an rms estimator, (2) a compression/expansion coefficient computation engine, and (3) an attack/decay controller.
• RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into the DRC. For the DRC block shared by CH1 and CH2, two estimates are computed—an estimate of the
CH1 audio data stream into the DRC, and an estimate of the CH2 audio data stream into the DRC. The outputs of the two estimators are then compared, sample-by-sample, and the larger valued sample is forwarded to the compression/expansion coefficient computation engine.
Two programmable parameters, ae and (1 – ae), set the effective time window over which the rms estimate is made. For the DRC block shared by CH1 and CH2, the programmable parameters apply to both rms estimators. The time window over which the rms estimation is computed can be determined by: twindow +
* 1
FS ȏn(1 * ae)
• Compression/expansion coefficient computation—This DRC element converts the output of the rms estimator to a logarithmic number, determines the region that the input resides, and then computes and outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters—T1,
T2, O1, O2, k0, k1, and k2—define the three compression/expansion regions implemented by this element.
• Attack/decay control—This DRC element controls the transition time of changes in the coefficient computed in the compression/expansion coefficient computation element. Four programmable parameters define the operation of this element. Parameters ad and 1 − ad set the decay or release time constant to be used for volume boost (expansion). Parameters aa and 1 − aa set the attack time constant to be used for volume cuts. The transition time constants can be determined by: ta +
* 1
FS ȏn(1 * aa) td +
* 1
FS ȏn(1 * ad)
1.11.2
Compression/Expansion Coefficient Computation Engine Parameters
There are seven programmable parameters assigned to each DRC block: two threshold parameters - T1 and
T2, two offset parameters - O1 and O2, and three slope parameters - k0, k1, and k2. The threshold parameters establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by establishing known gain settings at the threshold levels, and the slope parameters define whether a given region is a compression or an expansion region.
26
TAS5518 SLES115 — August 2004
Introduction
The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers. These mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the audio data in the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input and the DRC. The selection of threshold values must take the gain (attenuation) of these mixers into account. The DRC implementation examples that follow illustrate the effect these mixers have on establishing the threshold settings.
T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes the boundary between the mid-volume region and the low-volume region. Both thresholds are set in logarithmic space, and which region is active for any given rms estimator output sample is determined by the logarithmic value of the sample.
Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If O2 = 0 dB, the value of the derived gain coefficient is 1.0 (0x00, 80, 00, 00 in 5.23 format). k2 is the slope of the DRC transfer function for rms input levels above T2 and k1 is the slope of the DRC transfer function for rms input levels below
T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that there cannot be a discontinuity in the transfer function at T2. The user can, however, set the DRC parameters to realize a discontinuity in the transfer function at the boundary defined by T1. If no discontinuity is desired at T1, the value for the offset term
O1 must obey the following equation.
O1No Discontinuity + |T1 * T2| k1 ) O2 For ( |T1| w |T2| )
T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If the user chooses to select a value of O1 that does not obey the above equation, a discontinuity at T1 is realized.
Going down in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this input level, the offset of the transfer function curve from the 1:1 transfer curve does not equal O1, there is a discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at the input level
T1 is offset from the 1:1 transfer curve by the value O1. The examples that follow illustrate both continuous and discontinuous transfer curves at T1.
Going down in volume from T1, starting at the offset level O1, the slope k0 defines the compression/expansion activity in the lower region of the DRC transfer curve.
1.11.2.1 Threshold Parameter Computation
For thresholds,
T dB
= −6.0206T
INPUT
= −6.0206T
SUB_ADDRESS_ENTRY
If, for example, it is desired to set T1 = -64 dB, then the subaddressaddress entry required to set T1 to -64 dB is:
T1SUB_ADDRESS_ENTRY +
*64
*6.0206 +
10.63
T1 is entered as a 48-bit number in 25.23 format. Therefore:
T1 = 10.63 = 0_1010.1010_0001_0100_0111_1010_111
= 0x00000550A3D7 in 25.23 format
SLES115 — August 2004 TAS5518
27
Introduction
1.11.2.2 Offset Parameter Computation
The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An equivalent statement is that offsets represent the departure of the actual transfer function from a 1:1 transfer at the threshold point. Offsets are 25.23 formatted 48-bit logarithmic numbers. They are computed by the following equation.
OINPUT +
ODESIRED ) 24.0824 dB
6.0206
Gains or boosts are represented as negative numbers; cuts or attenuation are represented as positive numbers. For example, to achieve a boost of 21 dB at threshold T1, the I must be:
2
C coefficient value entered for O1
O1INPUT +
–21 dB ) 24.0824 dB
6.0206
+ 0.51197555
+ 0.1000_0011_0001_1101_0100
+ 0x00000041886A in 25.23 format
More examples of offset computations are included in the following examples.
1.11.2.3 Slope Parameter Computation
In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within a given region of the DRC, the following convention is adopted.
DRC Transfer = Input Increase : Output Increase
If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the DRC, a 1:n expansion is being performed. If the DRC realizes a 1 dB increase in output level for every n dB increase in the rms value of the audio into the DRC, a n:1 compression is being performed.
For 1:n expansion, the slope k can be found by: k = n − 1
For n:1 compression, the slope k can be found by: k + 1n–1
In both expansion (1:n) and compression (n:1), n is implied to be greater than 1. Thus, for expansion: k = n −1 means k > 0 for n > 1. Likewise, for compression, k + 1n–1 means −1 < k < 0 for n > 1. Thus, it appears that k must always lie in the range k > −1.
The DRC imposes no such restriction and k can be programmed to values as negative as −15.999. To determine what results when such values of k are entered, it is first helpful to note that the compression and expansion equations for k are actually the same equation. For example, a 1:2 expansion is also a 0.5:1 compression.
–1 + 1
1 : 2 Expansion å k + 2–1 + 1
As can be seen, the same value for k is obtained either way. The ability to choose values of k less than −1 allows the DRC to implement negative slope transfer curves within a given region. Negative slope transfer curves are usually not associated with compression and expansion operations, but the definition of these operations can be expanded to include negative slope transfer functions. For example, if k = −4
Compression Equation : k + *4 + 1n *1 å n + –
1
3 å *
0.3333 : 1 compression
Expansion Equation : k + *4 + n–1 å n + –3 å 1 : *3 expansion
With k = −4, the output decreases 3 dB for every 1 dB increase in the rms value of the audio into the DRC.
As the input increases in volume, the output decreases in volume.
28
TAS5518 SLES115 — August 2004
Introduction
1.12 Output Mixer
The TAS5518 provides an 8x2 output mixer for channels 1, 2, 3, 4, 5, and 6. For channels 7 and 8 the TAS5518 provides an 8x3 output mixer. These mixers allow each output to be any ratio of any two (three) signal processed channels. The control parameters for the output crossbar mixer are programmable via the I
2 interface.
C
Gain Coefficient
28
Select
Output
N
48
Gain Coefficient
28
48
Select
Output
N
48 48
Output
1, 2, 3, 4, 7 or 8
Gain Coefficient
28
Select
Output
N
48
Gain Coefficient
28
48
Select
Output
N
Output
5 or 6
48 48
Gain Coefficient
28
48
Select
Output
N
48
Figure 1−21. Output Mixers
1.13 PWM
The TAS5518 has eight channels of high performance digital PWM Modulators that are designed to drive switching output stages (backends) in both single-ended (SE) and H-bridge (bridge tied load) configuration.
The TAS5518 device uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5518 uses an AD1 PWM modulation combined with a 5 th
order noise shaper to provide a 110-dB SNR from 20 to 20 kHz.
The PWM section accepts 32-bit PCM data from the DAP and outputs eight PWM audio output channels configurable as either:
• Six channels to drive power stages + two channels to drive a differential input active filter to provide a separately controllable stereo line out
• Eight channels to drive power stages
The TAS5518 PWM section output supports both single-ended and bridge-tied loads.
The PWM section provides a headphone PWM output to drive an external differential amplifier like the
TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone will not operate while the six or eight backend drive channels are operating. The headphone will be enabled via a headphone select terminal or I
2
C command.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz.
The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled and disabled.
The PWM section also contains the power supply volume control (PSVC) PWM.
SLES115 — August 2004 TAS5518
29
Introduction
The interpolator, noise shaper, and PWM sections provide a PWM output with the following features:
• Up to 8x over sampling.
− 8x at F
S
= 44.1 kHz, 48 kHz, 32 kHz, 38 kHz
− 4x at F
S
= 88.2 kHz, 96 kHz
− 2x at F
S
= 176.4 kHz, 192 kHz
• 5 th
order noise shaping
• 110-dB dynamic range 0 – 20 kHz (TAS5518 + TAS5182 system measured at speaker terminals)
• THD < 0.01%
• Adjustable maximum modulation limit of 93.8% to 99.2%
•
3.3-V digital signal
1.13.1
DC Blocking (High Pass Enable/ Disable)
Each input channel incorporates a first order digital high-pass filter to block potential dc components. The filter
–3 dB point is approximately 0.89-Hz at 44.1-kHz sampling rate. The high-pass filter can be enabled and disabled via the I
2
C interface.
1.13.2
De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50 µs/15 µs de-emphasis filter is provided to
filtering characteristics. De-emphasis is set using two bits in the system control register.
0
−10
3.18 (50 µs)
Frequency − kHz
10.6 (15 µs)
Figure 1−22. De-emphasis Filter Characteristics
1.13.3
Power Supply Volume Control (PSVC)
The TAS5518 supports volume control by both conventional digital gain / attenuation and by a combination of digital and analog gain / attenuation. Varying the H-bridge power supply voltage performs the analog volume control function. The benefits of using powers supply volume control (PSVC) are reduced idle channel noise, improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions at reduced power levels. The power supply volume control (PSVC) is enabled via I
2
C. When enabled the
PSCV provides a PWM output that is filtered to provide a reference voltage for the power supply. The power supply adjustment range can be set for −12.04, −18.06, or −24.08 dB, to accommodate a range of variable power supply designs.
Figure 1−23 and Figure 1−24 show how power supply and digital gains can be used together.
The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to match the PSVC volume transfer function.
30
TAS5518 SLES115 — August 2004
Introduction
Power Supply Volume Control
0
−10
−20
−30
−40
−50
−60
30
20
10
Digital Gain
Power Supply Gain
Desired Gain − dB
Figure 1−23. Power Supply and Digital Gains (Log Space)
Power Supply Volume Control
100
0.1
0.01
10
1
Digital Gain
Power Supply Gain
0.001
0.0001
0.00001
0.0001
0.001
0.01
0.1
Desired Gain (Linear)
1 10
Figure 1−24. Power Supply and Digital Gains (Linear Space)
100
1.13.4
AM Interference Avoidance
Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments patented AM interference avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5518 adjusts the radiated emissions to provide an emission clear zone for the tuned AM frequency. The inputs to the TAS5518 for this operation are the tuned AM frequency, the IF frequency, and the sample rate. The sample rate is automatically detected.
SLES115 — August 2004 TAS5518
31
Introduction
Analog
Receiver
ADC
PCM1802
Audio
DSP
TAS5518
Audio DSP provides the master and bit clocks
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
Digital
Receiver
Audio
DSP
TAS5518
The Digital Receiver or the Audio
DSP provides the Master and Bit clocks
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
Figure 1−25. Block Diagrams of Typical Systems Requiring TAS5518 Automatic AM Interference
Avoidance Circuit
32
TAS5518 SLES115 — August 2004
TAS5518 Controls and Status
2 TAS5518 Controls and Status
The TAS5518 provides control and status information from both the I
2
C registers and device pins.
This section describes some of these controls and status functions. The I
2 descriptions are contained in sections at the end of this document.
C summary and detailed register
2.1
I
2
C Status Registers
The TAS5518 has two status registers that provide general device information. These are the General Status
Register 0 (0x01) and the Error Status Register (0x02).
2.1.1 General Status Register (0x01)
• Device identification code
• Clip indicator – The TAS5518 has a clipping indicator. Writing to the register clears the indicator.
•
Bank switching is busy
2.1.2 Error Status Register (0x02)
• No internal errors (the valid signal is high)
• A clock error has occurred – These are sticky bits that are cleared by writing to the register.
− LRCLK error – When the number of MCLKs per LRCLK is incorrect
− SCLK error – When the number of SCLKS per LRCLK is incorrect
− Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
− PLL phase-lock error
•
This error status register is normally used for system development only.
2.2
TAS5518 Pin Controls
The TAS5518 provide a number of terminal controls to manage the device operation. These controls are:
• RESET
• PDN
• BKND_ERR
•
HP_SEL
• MUTE
2.2.1 Reset (RESET)
The TAS5518 is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry when power is applied.
I
RESET is an asynchronous control signal that restores the TAS5518 to the hard mute state (M). Master volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all
2
C and serial data bus operations are ignored.
Table 2−1 shows the device output signals while RESET is active.
Table 2−1. Device Outputs During Reset
SIGNAL
Valid
PWM P-outputs
PWM M-outputs
SDA
SIGNAL STATE
Low
Low (M-State)
Low (M-State)
Signal Input (not driven)
SLES115 — August 2004 TAS5518
33
TAS5518 Controls and Status
Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational state is performed using a quiet start up sequence to minimize noise. This control uses the PWM reset and unmute sequence to shut down and start up the PWM. A detailed description of these sequences is contained in the PWM section. If a completely quiet reset or power down sequence is desired, MUTE should be applied before applying RESET.
The rising edge of the reset pulse begins device initialization before the transition to the operational mode.
settings following a reset.
Table 2−2. Values Set During Reset
CONTROL
Clock register
High pass
Unmute from clock error
PSVC high Z
Post DAP detection automute
Eight Ch PreDAP detection automute
De−emphasis
Channel configuration control
Headphone configuration control
Serial data interface format
Individual channel mute
Automute delay
Automute threshold 1
Automute threshold 2
Modulation limit
Six (or eight – low) channel configuration
Slew rate limit
Interchannel delay
Shutdown PWM on error
Volume and mute update rate
Treble and bass slew rate
Bank switching
Auto bank switching map
Biquad coefficients (5508)
Input mixer coefficients
Output mixer coefficients
Subwoofer sum into Ch1 and 2 (5508)
Ch1 and 2 sum in subwoofer (5508)
Bass and treble bypass
Bass and treble Inline
DRC bypass (5508)
DRC inline (5508)
DRC (5508)
Master volume
Individual channel volumes
All bass and treble Indexes
Treble filter sets
SETTING
Not valid
Disabled
Hard unmute
Disabled
Enabled
Enabled
De-emphasis disabled
Configured for the default setting
Configured for the default setting
I
2
S 24 bit
No channels are muted
5 ms
< 8 bits
Same as automute threshold 1
Maximum modulation limit of 97.7%
Eight channels
Disengaged for all channels
−32, 0, –16, 16, –24, 8, –8, −24
Enabled
Volume ramp 85 ms
Update every 1.31 ms
Manual bank selection is enabled
All channels use Bank 1
Set to All pass
Input N −> Channel N, no attenuation
Channel N −> Output N, no attenuation
Gain of 0
Gain of 0
Gain of 1
Gain of 0
Gain of 1
Gain of 0
DRC disabled, default values
Mute
0 dB
0x12 neutral
Filter Set 3
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TAS5518 SLES115 — August 2004
TAS5518 Controls and Status
CONTROL
Bass filter sets
Loudness (5508)
AM interference enable
AM interference IF
AM interference select sequence
Tuned freq and mode
Subwoofer PSVC control
PSVC and PSVC range
SETTING
Filter Set 3
Loudness disabled, default values
Disabled
455
1
0000 , BCD
Enabled
Disabled / 0 dB
After the initialization time, the TAS5518 starts the transition to the operational state with the Master volume set at mute.
Since the TAS5518 has an external crystal time base, following the release of RESET, the TAS5518 sets the
MCLK and data rates and perform the initialization sequences. The PWM outputs are held at a mute state until the master volume is set to a value other than mute via I
2
C.
2.2.2 Power Down (PDN)
TheTAS5518 can be placed into the power down mode by holding the PDN terminal low. When power down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation
(there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition to the hard mute state (M). A detailed description of the PWM mute sequence is contained in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power down state. To initiate the power-up sequence requires MCLK to be operational and the TAS5518 to receive 5 MCLKs prior to the release of PDN.
As long as the PDN terminal is held low the device is in the power down state with the PWM outputs in a hard mute (M) state. During power down, all I
2
C and serial data bus operations are ignored. Table 2−3 shows the
device output signals while PDN is active.
Table 2−3. Device Outputs During Power Down
SIGNAL
Valid
PWM P-outputs
PWM M-outputs
SDA
PSVC
SIGNAL STATE
Low
M-state = low
M-state = low
Signal input
M-state = low
Following the application of PDN, the TAS5518 does not perform a quiet shutdown to prevent clicks and pops produced during the application (the leading edge) of this command. The application of PDN immediately performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and the
I
2
C register settings.
The crystal time base allows the TAS5518 to determine the CLK rates. Once these rates are determined, the
TAS5518 unmutes the audio.
2.2.3 Backend Error (BKND_ERR)
Backend error is used to provide error management for backend error conditions. Backend error is a level sensitive signal. Backend error can be initiated by bringing the BKND_ERR terminal low for a minimum 5
MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM backend error state. This state is described in the PWM section. Once the backend error sequence is initiated, a delay of 5 ms is performed before the system starts the output re−initialization sequence. After the initialization time, the TAS5518 begins normal operation. Backend error does not affect other PWM modulator operations
SLES115 — August 2004 TAS5518
35
TAS5518 Controls and Status
The number of channels that are affected by the BKND_ERR signal is dependent upon the 6-channel configuration signal. If the I
2
C setting 6-channel configuration is false, the TAS5518 places all eight PWM outputs in the PWM backend error state, while not affecting any other internal settings or operations. If the
I
2
C setting six configuration is true, the TAS5518 brings the PWM outputs 1−6 to a backend error state, while
backend error.
Table 2−4. Device Outputs During Backend Error
SIGNAL
Valid
PWM P-outputs
PWM M-outputs
HPPWM P-outputs
HPPWM M-outputs
SDA
2.2.4 Speaker / Headphone Selector (HP_SEL)
SIGNAL STATE
Low
M-State − low
M-State − low
M-State − low
M-State − low
Signal Input (not driven)
The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives the processed data output from DAP and PWM channels 1 and 2.
In 6-channel configuration this feature does not affect the two lineout channels.
When low, the headphone output is enabled. In this mode the speaker outputs are disabled. When high, the speaker outputs are enabled and the headphone is disabled.
Changes in the pin logic level results in a state change sequence using soft mute to the hard mute (M) state for both speaker and headphone followed by a soft unmute.
When HP_SEL is low, the configuration of channels 1 and 2 are defined by the headphone configuration register. When HP_SEL is high, the channel 1 and 2 configuration registers define the configuration of channels 1 and 2.
2.2.5 Mute (MUTE)
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. The TAS55508 has both a master and individual channel mute commands. A terminal is also provided for the master MUTE. The low active master Mute I
2
C register and the MUTE terminal are logically Or’ed together. If either is set to low, a mute on all channels is performed. The master mute command operates on all channels regardless on whether the system is in six or eight channel configuration.
When MUTE is invoked, the PWM output stops switching and then goes to an idle state.
The master Mute terminal is used to support a variety of other operations in the TAS5518, such as setting the inter-channel delay, the biquad coefficients, the serial interface format, and the clock rates. A mute command by the master mute terminal, individual I
2
C mute, the AM interference mute sequence, the bank switch mute sequence, or automute overrides an unmute command or a volume command. While a mute is active, the commanded channels will be placed in a mute state. When a channel is unmuted, it goes to the last commanded volume setting that has been received for that channel.
2.3
Device Configuration Controls
The TAS5518 provides a number of system configuration controls that are set at initialization and following a reset.
• Channel Configuration
• Headphone Configuration
• Audio System Configurations
36
TAS5518 SLES115 — August 2004
TAS5518 Controls and Status
•
Recovery from Clock Error
• Power Supply Volume Control Enable
• Volume and Mute Update Rate
• Modulation Index Limit
• Inter-channel Delay
• Master Clock and Data Rate Controls
• Bank Controls
2.3.1 Channel Configuration Registers
In order for the TAS5518 to have full control of the power stages, registers 0x05 to 0x0C must be programmed to reflect the proper power stage and how each one should be controlled. Channel configuration registers consist of eight registers, one for each channel.
BIT
D7
D6
D5
D4
D3
D2
D1
D0
The primary reason for using these registers is that different power stages require different handling during start up, mute/unmute, shutdown, and error recovery. The TAS5518 must select the sequence that gives the best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up.
This sequence depends on which power stage is present at the TAS5518 output.
Table 2−5. Description of the Channel Configuration Registers (0x05 to 0x0C)
DESCRIPTION
Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is to follow the error recovery sequence or to continue with no interruption.
Determines if the power stage needs the TAS5518 VALID pin to go low to reset the power stage. Some power stages can be reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power stages. This provides better control of each power stage.
Determines if the power stage needs the TAS5518 VALID pin to go low to mute the power stage. Some power stages can be muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power stages. This provides better control of each power stage.
Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5518 PWM pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted.
The power stage TAS5182 has a special PWM input. To ensure that the TAS5518 has full control in all occasions, the PWM output must be remapped.
Can be used to handle click and pop for some applications.
This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
Not used
SLES115 — August 2004 TAS5518
37
TAS5518 Controls and Status
in all configurations except the TAS5182 SE/BTL configuration.
Table 2−6. Recommended TAS5518 Configurations for Texas Instruments Power Stages
DEVICE
Default
ERROR RECOVERY
RES
CONFIGURATION
BTL
SE
BTL
SE
BTL
SE
BTL
SE
BTL
SE
BTL
AUT: The power stage can auto recover from a shutdown.
BTL: Bridge tied load configuration
SE: Single-ended configuration
D7
1
0
1
1
0
1
0
0
1
1
1
D5
1
0
1
0
0
1
1
1
1
1
0
D6
1
1
1
1
1
1
1
1
1
1
1
D4
0
0
0
0
0
0
0
0
0
0
0
RES: The output stage requires VALID to go low to recover from a shutdown.
D3
0
0
1
0
0
1
0
0
0
0
0
D2
0
0
0
0
0
0
0
0
0
0
0
D1
0
0
0
0
0
0
0
0
0
0
0
D0
0
0
0
0
0
0
0
0
0
0
0
2.3.2 Headphone Configuration Registers
The headphone configuration controls are identical to the speaker configuration controls. The headphone configuration control settings are used in place of the speaker configuration control settings for channels 1 and 2 when the headphones are selected. In reality however, there is only one used configuration setting for headphones and that is the default setting.
2.3.3 Audio System Configurations
The TAS5518 can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system and 8-channel system.
The audio system configuration is set in the General Control Register (0xE0). Bits D31 – D4 must be zero and
D0 is don’t care.
D3
D2
D1
Determines if SUB is to be controlled by PSVC (D3 is a write-only bit)
Enable/Disable power supply volume control
Sets number of speakers in the system, including possible line outputs
D3−D1 must be configured as the following according to the audio system in the application:
Table 2−7. Audio System Configuration (General Control Register 0xE0)
AUDIO SYSTEM
DEFAULT
6 channel or 5.1 NOT using PSVC
6 channel using PSVC
5.1 system using PSVC
8 channel or 7.1 NOT using PSVC
8 channel using PSVC
7.1 system using PSVC
D31−D4
0
0
0
0
0
0
0
D3
0
0
0
1
0
0
1
D2
0
0
1
1
0
1
1
D1
0
1
1
1
0
0
0
D0
X
X
X
X
X
X
X
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TAS5518 SLES115 — August 2004
TAS5518 Controls and Status
2.3.3.1
Using Line Outputs in 6-Channel Configurations
The audio system can be configured for a 6-channel configuration (with 2 line outs) by writing a 1 to bit D1 of register 0xE0 (General Control Register). In this configuration, channel 5 and 6 processing are exactly the same as the other channels, except that Master Volume has no effect.
Note that in 6-channel configuration, channels 5 and 6 are unaffected by backend error (BKND_ERR goes low).
To use channels 5 and 6 as dry unprocessed line outs, the following setup should be done:
•
Channel 5 volume and channel 6 volume should be set for a constant output such as 0 dB.
•
Bass and Treble for channels 5 and 6 can be used if desired.
• DRC1 should be by-passed for channels 5 and 6.
• If enabled, the loudness function shapes the response of channels 5 and 6. However, the amplitude of
5 and 6 are not used in determining the loudness response.
• If a down mix is desired on the channel 5 and 6 as line out, the down mixing can be performed using the channel 5 and channel 6 input mixers.
• The operation of the channel 5 and 6 biquads is unaffected by the 6/8 channel configuration setting.
2.3.4 Recovery from Clock Error
The TAS5518 can be set to either perform a volume ramp up during the recovery sequence of a clock error or to simply come up in the last state (or desired state if a volume or tone update was in progress). This feature is enabled via I
2
C system control register 0x03.
2.3.5 Power Supply Volume Control Enable
The power supply volume control (PSVC) can be enabled and disabled via I
2
C register 0xE0. The subwoofer
PWM output can configured to be controlled by the PSVC or digitally attenuated when PSVC is enabled (for powered subwoofer configurations). Note that PSVC cannot be simultaneously enabled along with unmute outputs after clock error feature.
SLES115 — August 2004 TAS5518
39
TAS5518 Controls and Status
2.3.6 Volume and Mute Update Rate
The TAS5518 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute ramp rates are adjustable by programming the I
2
C register 0xD0 for the appropriate number of steps to be
512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.
• In normal speed, the update rate is 1 step every 4 / Fs seconds.
• In double speed, the update is 1 step every 8 / Fs seconds.
• In quad speed, the update is 1 step every 16 / Fs seconds.
Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However, the variance of the total time to go from +18 dB to mute is less than 25%.
Table 2−8. Volume Ramp Rates in ms
512
1024
2048
SAMPLE RATE (KHZ)
44.1, 88.2, 176.4
32, 48, 96, 192
46.44 ms
92.88 ms
185.76 ms
42.67 ms
85.33 ms
170.67 ms
2.3.7 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is
50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For negative signals, the PWM modulations fall below 50% towards 0%.
However, there is a limit to the maximum modulation possible. During the off-time period, the power stage connected to the TAS5518 output needs to get ready for he next on-time period. The maximum possible modulation is then set by the power stage requirements. All Texas Instruments power stages needs maximum modulation to be 97.7%. This is also the default setting of the TAS5518. Default settings can be changed in the Modulation Index Register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
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TAS5518 SLES115 — August 2004
TAS5518 Controls and Status
2.3.8 Inter-channel Delay
An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
The default values are shown in Table 2−9.
Table 2−9. Inter-Channel Delay Default Values
I
2
C SUB-ADDRESS
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
CHANNEL
1
5
6
7
2
3
4
8
INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)
−24
0
−16
+16
−24
+8
−8
+24
This delay is generated in the PWM and can be changed at any time through the serial control interface I
2
C registers 0x1B – 0x22. The absolute offset for channel 1 is set in I
2
C sub-address 0x23.
NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a pure path digital amplifier system. The setting is based upon the type of backend power device that is used and the layout. These values are set during initialization using the I 2 C serial
interface. Unless otherwise noted, use the default values given in Table 2−9.
2.4
Master Clock and Serial Data Rate Controls
The TAS5518 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal allows the TAS5518 to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5518 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5518 accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5518 performs a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
• MCLK Ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) − I
2
C parameter
• Data Rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz − I
2
C parameter
• AM Mode Enable / Disable − I
2
C parameter
During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:
•
Tuned AM Frequency (for AM interference avoidance) (550 − 1750 kHz) − I
2
C parameter
• Frequency Set Select (1−4) − I
2
C parameter
• Sample Rate − I
2
C parameter or auto detected
SLES115 — August 2004 TAS5518
41
TAS5518 Controls and Status
2.4.1 PLL Operation
The TAS5518 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL
(DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital
PLL provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal provides the input reference clock for the digital PLL. The crystal provides a time base to support a number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5518 can receive and store I
2
C commands and provide status.
2.5
Bank Controls
The TAS5518 permits the user to specify and assign sample rate dependent parameters for Biquad,
Loudness, DRC, and Tone in one of three banks that can be manually selected or selected automatically based upon the data sample rate. Each bank can be enabled for one or more specific sample rates via I
2
C bank control register 0x40. Each bank set holds the following values:
• Coefficients for Seven Biquads (7X5 = 35 coefficients) for Each of the Eight Channels (Registers 0X51
– 0x88)
• Coefficients for One Loudness Biquad (Register 0x95)
•
DRC1 Energy and (1 – Energy) Values (Register 0x98)
• DRC1 Attack, (1 − Attack), Decay, (1 – Decay) Values (Register 0x9C)
• DRC2 Energy and (1 – Energy) Values (Register 0x9D)
•
DRC2 Attack, (1 − Attack), Decay, (1 – Decay) Values (Register 0xA1)
• Five Bass Filter-Set Selections (Register 0xDA)
• Five Treble Filter-Set Selections (Register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used,
Bank 2 and Bank 3 must be programmed on power−up since the default values are all zeroes. If bank switching is used and Bank 2 and Bank 3 are not programmed correctly, then the output of the TAS5518 could be muted when switching to those banks.
2.5.1 Manual Bank Selection
The three bank selection bits of the bank control register allow the appropriate bank to be manually selected
(000 = Bank 1, 001 = Bank 2, 010 = Bank 3). In the manual mode, when a write occurs to the Biquad, DRC, or Loudness coefficients, the current selected bank is updated. If audio data is streaming to the TAS5518, during a manual bank selection, the TAS5518 first performs a mute sequence, then performs the bank switch, and finally restores the volume using an un−mute sequence.
A mute command initiated by the bank switch mute sequence overrides an un−mute command or a volume command. While a mute is active, the commanded channels are muted. When a channel is unmated, the volume level goes to the last commanded volume setting that has been received for that channel.
If MCLK or SCLK is stopped, the TAS5518 performs a bank switch operation. If the clocks should start up once the manual bank switch command has been received, the bank switch operation is performed during the 5−ms silent start sequence.
2.5.2 Automatic Bank Selection
To enable automatic bank selection, a value of 3 is written into in the bank selection bits of the bank control register. Banks are associated with one or more sample rates by writing values into the Bank 1 or Bank 2 data rate selection registers. The automatic base selection is performed when a frequency change is detected according to the following scheme:
42
TAS5518 SLES115 — August 2004
TAS5518 Controls and Status
1. The system scans Bank 1 data rate associations to see if the Bank 1 is assigned for that data rate.
2. If Bank 1 is assigned, then the Bank 1 coefficients will be loaded.
3. If it is not then, the system scans the bank 2 to see if Bank 1 is assigned for that data rate.
4. If Bank 2 is assigned, then the Bank 2 coefficients will be loaded.
5. If it is not then, the system loads the Bank 3 coefficients.
The default is that all frequencies are enabled for Bank 1. This default is expressed as a value of all 1s in the
Bank 1 auto-selection byte and all 0s in the bank 2 auto−section byte.
2.5.2.1
Coefficients Write Operations While Automatic Bank Switch Is Enabled
In automatic mode if a write occurs to the Tone, EQ, DRC, or Loudness coefficients, the bank that is written to is the current bank.
2.5.3 Bank Set
Bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic switching modes without causing a bank switch to occur. Bank set mode does not alter the current bank register mapping. It simply enables any bank’s coefficients to be updated while inhibiting any bank switches from taking place. In manual mode, this enables the coefficients to be set without switching banks. In automatic mode this prevents a clock error or data rate change from corrupting a bank coefficient write.
To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the bank control register. This enables the Tone, EQ, DRC, and Loudness coefficient values of bank 1, 2, or 3 to be respectively updated.
Once the coefficients of the bank have been updated, the bank selection bits are then returned to the desired manual or automatic bank selection mode.
2.5.4 Bank Switch Timeline
After a bank switch is initiated (manual or automatic), no I
2
C writes to the TAS5518 should occur before a minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate.
2.5.5 Bank Switching Example 1
Problem: The audio unit containing a TAS5518 needs to handle different audio formats with different sample rates. Format #1 requires Fs = 32 kHz, Format #2 requires Fs = 44.1 kHz, and Format #3 requires Fs = 48 kHz. The sample-rate dependent parameters in the TAS5518 require different coefficients and data depending on the sample rate.
Strategy: Use the TAS5518 bank switching feature to allow for managing and switching three banks associated with the three sample rates, 32 kHz (Bank 1), 44.1 kHz (Bank 2), and 48 kHz (Bank 3).
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
• Generate bank-related coefficients (see above) for sample rates 32 kHz, 44.1 kHz, and 48 kHz and include the same in the micro-based TAS5518 I
2
C firmware.
•
On TAS5518 power up or reset, the micro runs the following TAS5518 Initialization code:
− Update Bank 1 (Write 0x00048040 to register 0x40).
− Write bank-related I
2
C registers with appropriate values for Bank 1.
− Write Bank 2 (Write 0x00058040 to register 0x40).
− Load bank-related I
2
C registers with appropriate values for Bank 2.
− Write Bank 3 (Write 0x00068040 to register 0x40).
− Load bank-related I
2
C registers with appropriate values for Bank 3.
− Select automatic bank switching (write 0x00038040 to register 0x40)
SLES115 — August 2004 TAS5518
43
TAS5518 Controls and Status
•
Now when the audio media changes, the TAS5518 automatically detects the incoming sample rate and automatically switches to the appropriate bank.
In this example any sample rates other then 32 kHz and 44.1 kHz will use Bank 3. If other sample rates are used, then the banks need to be set−up differently.
2.5.6 Bank Switching Example 2
Problem: The audio system uses all of the sample rates supported by the TAS5518. How can the automatic bank switching be set up to handle this situation?
Strategy: Use the TAS5518 bank switching feature to allow for managing and switching three banks associated with sample rates as follows:
• Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz
• Bank 2: Coefficients for 88.2kHz and 96 kHz
• Bank 3: Coefficients for 176.4 kHz and 192 kHz
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
•
Generate bank-related coefficients for sample rates 48 kHz (Bank 1), 96 kHz (Bank 2), and 192 kHz (Bank
3) and include the same in the micro-based TAS5518 I
2
C firmware.
•
On TAS5518 power−up or reset, the micro runs the following TAS5518 Initialization code:
− Update Bank 1 (Write 0x0004F00C to register 0x40).
− Write bank-related I
2
C registers with appropriate values for Bank 1.
− Write Bank 2 (Write 0x0005F00C to register 0x40).
− Load bank-related I
2
C registers with appropriate values for Bank 2.
− Write Bank 3 (Write 0x0006F00C to register 0x40).
− Load bank-related I
2
C registers with appropriate values for Bank 3.
− Select automatic bank switching (Write 0x0003F00C to register 0x40)
• Now when the audio media changes, the TAS5518 automatically detects the incoming sample rate and automatically switches to the appropriate bank.
44
TAS5518 SLES115 — August 2004
PACKAGE
PAG
Electrical Specifications
3 Electrical Specifications
3.1
Absolute Maximum Ratings
{
Supply voltage, DVDD and DVD_PWM
Supply voltage, AVDD_PLL
3.3-V digital input
Input voltage
5 V tolerant
digital input
1.8 V LVCMOS
Input clamp current, I
IK
(V
I
< 0 or V
I
> 1.8 V
Output clamp current, I
OK
(V
O
< 0 or V
O
> 1.8 V)
Operating free air temperature
Storage temperature range, T stg
UNITS
−0.3 V to 3.6 V
−0.3 V to 3.6 V
−0.5 V to DVDD + 0.5 V
−0.5 V to 6 V
−0.5 V to VREF
+ 0.5 V
±20 mA
±20 mA
0°C to 70°C
−65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. VREF is a 1.8-V supply derived from regulators internal to the TAS5518 chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL,
VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source power to external devices.
2. 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
3. VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM
DISSIPATION RATING TABLE (High-k Board, 1055C Junction)
T
A
≤ 255C
POWER RATING
1869 mW
DERATING FACTOR
ABOVE T
A
= 255C
23.36 mW/°C
T
A
= 705C
POWER RATING
818 mW
3.2
Dynamic Performance (At Recommended Operating Conditions at 255C)
PARAMETER TEST CONDITIONS MIN NOM MAX UNITS
Dynamic range dB TAS5518 + TAS5182 EVM A-weighted (F
S
= 48 kHz)
TAS5182 A at 1 W
TAS5518 ouput
32-kHz to 96-kHz sample rates
176.4, 192-kHz sample rates
110
0.1%
0.01%
±0.1
±0.2
3.3
Recommended Operating Conditions (over 05C to 705C)
Digital supply voltage, DVDD and DVDD_PWM
MIN NOM MAX UNITS
3 3.3
3.6
V
Analog supply voltage, AVDD_PLL
3.3 V
5-V tolerant
1.8-V LVCMOS (XTL_IN)
2
1.26
3
2
3.3
3.6
V
3.3 V
5-V tolerant
1.8-V (XTL_IN)
0.8
0.8
0.54
Operating ambient air temperature range, T
A
−20 25 70 °C
Operating junction temperature range, T
J
−20 105
NOTE 4: 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
°C
SLES115 — August 2004 TAS5518
45
Electrical Specifications
3.4
Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
V
OH
PARAMETER
3.3 V TTL and 5 V
tolerant
1.8-V LVCMOS (XTL_OUT)
3.3-V TTL and 5 V
tolerant
TEST CONDITIONS MIN TYP MAX UNITS
0.5
V
OL
I
OH
= −4 mA
I
OH
= − 0.55 mA
I
OL
= 4 mA
I
OL
= 0.75 mA
2.4
1.44
I I
I I
I
OZ
1.8-V LVCMOS (XTL_OUT)
High-impedance output current 3.3-V TTL
3.3-V TTL
1.8-V LVCMOS (XTL_IN)
5 V tolerant
3.3-V TTL
1.8-V LVCMOS (XTL_IN)
5 V tolerant
V
I
= V
IL
V
I
= V
IL
V
I
= 0 V DVDD = 3 V
V
I
= V
IH
V
I
= V
IH
V
I
= 5.5 V DVDD = 3 V
Fs = 48 kHz
Fs = 96 kHz
Fs = 192kHz
0.5
±20
±1
±1
±1
±1
±1
±1
µA
I I
DD
140
150
155
Power down
Normal
Power down
8
6
1
NOTES: 5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
6. 5-V tolerant outputs are SCL and SDA
3.5
PWM Operation at Recommended Operating Conditions Over 05C to 705C
PARAMETER TEST CONDITIONS MODE VALUE UNITS
32-kHz data rate ±4%
44.1-, 88.2-, 176.4-kHz data rate ±4%
48, 96, 192 kHz data rate ±4%
12 x sample rate
8, 4, and 2 x sample rate
8, 4, and 2 x sample rate
384
352.8
384 kHz kHz kHz
3.6
Switching Characteristics
3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise
Noted)
3.6.1.1
PLL Input Parameters and External Filter Components
{
PARAMETER TEST CONDITIONS
f
XTALI f
MCLKI
Frequency, XTAL IN
Frequency, MCLK (1 / t cyc2
)
MCLK duty cycle duty cycle
Only use 13.5-MHz crystal ≤1000 ppm
MCLK minimum high time
MCLK minimum low time
≥2-V MCLK = 49.152 MHz, Within the min and max duty cycle constraints
≤0.8-V MCLK = 49.152 MHz,
Within the min and max duty cycle constraints
LRCLK allowable drift before LRCLK reset
External PLL filter cap C1
External PLL filter cap C2
External PLL filter resistor R
External VRA_PLL decoupling
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
SMD, Y5V
See the TAS5518 Example Application Schematic section.
MIN TYP
13.5
2
40% 50%
5
5
100
10
200
100
MAX UNITS
MHz
50 MHz
60% ns ns
10 MCLKs nF nF
Ω nF
46
TAS5518 SLES115 — August 2004
Electrical Specifications
3.6.2 Serial Audio Port
3.6.2.1
Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
f
SCLKIN t su1 t h1 t su2 t h2
Frequency, SCLK 64 x fs
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
SCLK duty cycle
LRCLK duty cycle
SCLK rising edges between LRCLK rising edges
LRCLK clock edge with respect to the falling edge of SCLK
C
L
= 30 pF 2.048
10
10
10
10
32 48
40% 50%
40% 50%
64
−1/4
12.288
MHz ns ns ns ns kHz 192
60%
60%
64
SCLK edges
1/4
SCLK period
SCLK
(Input) t h1 t su1
LRCLK
(Input) t su2 t h2
SDIN1
SDIN2
SDIN3
Figure 3−1. Slave Mode Serial Data Interface Timing
SLES115 — August 2004 TAS5518
47
Electrical Specifications
3.6.3 I
2
C Serial Control Port Operation
3.6.3.1
Timing Characteristics for I
2
C Interface Signals Over Recommended Operating
Conditions (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN MAX UNITS
t
(buf) t su2 t h2 t su3
C
L f
SCL t w(H) t w(L) t r t f t su1 t h1
Frequency, SCL
Pulse duration, SCL high
Pulse duration, SCL low
Rise time, SCL and SDA
Fall time, SCL and SDA
Setup time, SDA to SCL
Hold time, SCL to SDA
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Load capacitance for each bus line
No wait states
0.6
1.3
100
0
1.3
0.6
0.6
0.6
400 kHz
µs
300
300
µs ns ns ns
400 ns
µs
µs
µs
µs pF
t w(H) t w(L) t r t f
SCL
SDA t su1
Figure 3−2. SCL and SDA Timing t h1
SCL t su2 t h2 t
(buf) t su3
SDA
Start Condition
Stop Condition
Figure 3−3. Start and Stop Conditions Timing
48
TAS5518 SLES115 — August 2004
Electrical Specifications
3.6.4 Reset Timing (RESET)
3.6.4.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER MIN TYP
t r(DMSTATE) t w(RESET) t r(I2C_ready) t r(run)
Time to M-STATE low
Pulse duration, RESET active
Time to enable I
2
C
Device startup time
400
10
3
MAX UNITS
370 ns
None ns ms ms
RESET
Earliest time that M-State could be exited t w(RESET)
M-State t r(DMSTATE)
= ~ < 300 ns t r(I2C_ready)
Determine SCLK rate and MCLK ratio Enable I
2
C t r(run)
Start system
Figure 3−4. Reset Timing
Since a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock ratio is determined, the system outputs audio if a master volume command is issued.
3.6.5 Power-Down (PDN) Timing
3.6.5.1
Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise
Noted)
t p(DMSTATE) t su
PARAMETER
Time to M-STATE low
Number of MCLKs preceding the release of PDN
Device startup time
MIN TYP
5
120
MAX UNITS
300 µs ms
PDN
M-State t p(DMSTATE)
= ~ < 300 µs
t su
Figure 3−5. Power-Down Timing
SLES115 — August 2004 TAS5518
49
Electrical Specifications
3.6.6 Backend Error (BKND_ERR)
3.6.6.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER MIN TYP MAX
t w(ER) t p(valid_low) t p(valid_high)
Pulse duration, BKND_ERR active
I
2
C programmable to be between 1 to 10 ms
350
−25
None
UNITS
ns
<100 µs
25 % of interval
t w(ER)
ERR_RCVRY
M-State
Normal
Operation t p(valid_high) t p(valid_low)
Figure 3−6. Error Recovery Timing
Normal
Operation
3.6.7 MUTE Timing—MUTE
3.6.7.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
t d(VOL
Volume ramp time
NOTE 1: See the Volume Treble and Base Slew Rate Register (0xD0) section.
MIN TYP MAX UNITS
Defined by rate setting
ms
MUTE
VOLUME
M-State
Normal
Operation
Normal
Operation t d(VOL)
Figure 3−7. Mute Timing t d(VOL)
50
TAS5518 SLES115 — August 2004
Electrical Specifications
3.6.8 Headphone Select (HP_SEL)
3.6.8.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
t w(HP_SEL) t d(VOL)
Pulse duration, HP_SEL active
Soft volume update time t
(SW)
Switch-over time
NOTE 2: See the Volume Treble and Base Slew Rate Register (0xD0) section.
MIN
350 None
Defined by rate setting
0.2
MAX UNITS
1 ms ns ms ms
HP_SEL
Spkr Volume
HP Volume t d(VOL) t d(VOL) t
(SW)
M-State
(Internal Device State)
HP_SEL
HP Volume
Spkr Volume t d(VOL) t d(VOL) t
(SW)
M-State
Figure 3−8. HP_SEL Timing
SLES115 — August 2004 TAS5518
51
Serial Audio Interface Control and Timing
3.6.9 Volume Control
3.6.9.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER TEST CONDITIONS MIN MAX
Maximum attenuation before mute
Maximum gain
Maximum volume before the onset of clipping
PSVC range
PSVC rate
PSVC modulation
PSVC quantization
PSVC PWM modulation limits
Individual volume, master volume or a combination of both
Individual volume, master volume
0-dB input, any modulation limit
PSVC enabled
PSVC Rangel = 24 dB
12, 18, or 24
Fs
Single Sided
2048
6% (120 :
2048)
−127
18
0
95% 1944 :
2048
UNITS
dB dB dB dB
Steps dB
3.7
Serial Audio Interface Control and Timing
3.7.1 I
2
S Timing
I
2
S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5518 masks unused trailing data bit positions.
2-Channel I
2
S (Philips Format) Stereo Input
32 Clks 32 Clks
LRCLK (Note Reversed Phase) Left Channel
Right Channel
SCLK SCLK
MSB
24-Bit Mode
23 22 9 8
20-Bit Mode
19 18 5 4
16-Bit Mode
15 14 1 0
5 4
1 0
1 0
LSB MSB
23 22
19 18
9 8
5 4
15 14 1 0
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−9. I
2
S Format 64 Fs Format
5 4 1 0
1 0
LSB
52
TAS5518 SLES115 — August 2004
Serial Audio Interface Control and Timing
3.7.2 Left Justified
Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5518 masks unused trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks 32 Clks
LRCLK LRCLK
Left Channel
Right Channel
SCLK
LSB MSB
24-Bit Mode
23 22 9 8
20-Bit Mode
19 18 5 4
16-Bit Mode
15 14 1 0
5 4
1 0
1 0
LSB MSB
23 22 9 8
19 18 5 4
15 14 1 0
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−10. Left Justified 64 Fs Format
5 4
1 0
1 0
SLES115 — August 2004 TAS5518
53
Serial Audio Interface Control and Timing
3.7.3 Right Justified
Right justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5518 masks unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks 32 Clks
LRCLK
Left Channel
Right Channel
SCLK
MSB
24-Bit Mode
23 22 19 18 15 14
LSB MSB
1 0 23 22 19 18 15 14
20-Bit Mode
19 18 15 14 1 0
16-Bit Mode
15 14 1 0
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−11. Right Justified 64 Fs Format
19 18 15 14
15 14
LSB
1 0
1 0
1 0
54
TAS5518 SLES115 — August 2004
I
2
C Serial Control Interface (Slave Address 0x36)
4 I
2
C Serial Control Interface (Slave Address 0x36)
The TAS5518 has a bidirectional I
2
C interface that compatible with the I
2
C (Inter IC) bus protocol and supports both 100 Kbps and 400 Kbps data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multi-master bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5518 supports the standard-mode I
2
C bus operation (100 kHz maximum) and the fast I
2
C bus operation (400 kHz maximum). The TAS5518 performs all I
2
C operations without I
2
C wait cycles.
4.1
General I
2
C Operation
The I
2
C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
with another device and then wait for an acknowledge condition. The TAS5518 holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
SDA
7 Bit Slave Address
R/
W
A 8 Bit Register Address (N) A
8 Bit Register Data For
Address (N)
A
8 Bit Register Data For
Address (N)
A
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SCL
Start Stop
Figure 4−1. Typical I
2
C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence
The 7-bit address for the TAS5518 is 0011011.
4.2
Single and Multiple Byte Transfers
The serial control interface supports both single-byte and multiple-byte read / write operations for status registers and the general control registers associated with the PWM. However, for the DAP data processing registers, the serial control interface supports only multiple byte (4 byte) read / write operations.
During multiple byte read operations, the TAS5518 responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple byte write operations, the TAS5518 compares the number of bytes transmitted to the number of bytes that are required for each specific sub address. If a write command is received for a biquad subaddress, the TAS5518 expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded.
Similarly, if a write command is received for a mixer coefficient, the TAS5518 expects to receive one 32-bit word.
SLES115 — August 2004 TAS5518
55
I
2
C Serial Control Interface (Slave Address 0x36)
Supplying a subaddress for each subaddress transaction is referred to as random I
2
C addressing. The
TAS5518 also supports sequential I
2
C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the fifteen subaddresses that follow, a sequential I
2
C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5518. For I
2
C sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data is discarded.
4.3
Single Byte Write
condition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I
2
C device address and the read/write bit, the TAS5518 device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5518 internal memory address being accessed.
After receiving the address byte, the TAS5518 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5518 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single byte data write transfer.
Start
Condition Acknowledge Acknowledge Acknowledge
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I
2
C Device Address and
Read/Write Bit
Sub-Address
Figure 4−2. Single Byte Write Transfer
Data Byte
Stop
Condition
4.4
Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes
TAS5518 responds with an acknowledge bit.
Start
Condition
Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A3 A1 A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
I
2
C Device Address and
Read/Write Bit
Sub-Address First Data Byte
Figure 4−3. Multiple Byte Write Transfer
Other Data Bytes
Last Data Byte
Stop
Condition
4.5
Incremental Multiple Byte Write
The I
2
C supports a special mode which permits I
2 operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data. This permits the system to incrementally write large register values without blocking other I
2
C transactions.
C write operations to be broken up into multiple data write operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte, ... etc., write
This feature is enabled by the append subaddress function in the TAS5518. This function enables the
TAS5518 to append 4 bytes of data to a register that was opened by a previous I
2
C register write operation but has not received its complete number of data bytes. Since the length of the long registers is a multiple of
4 bytes, using 4-byte transfers will have only an integer number of append operations.
56
TAS5518 SLES115 — August 2004
I
2
C Serial Control Interface (Slave Address 0x36)
When the correct number of bytes has been received, the TAS5518 starts processing the data.
The procedure to perform an incremental multi-byte write operation is as follows:
1. Start a normal I
2
C write operation by sending the device address, write bit, register subaddress, and the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point, the register has been opened and accepts the remaining data that is sent by writing 4-byte blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the remaining number of bytes in sequential order to complete the register write operation. Each of these append operations will be composed of the device address, write bit, append subaddress (0xFE), and four bytes of data followed by a stop condition.
3. The operation will be terminated due to an error condition and the data will be flushed: a. If a new subaddress is written to the TAS5518 before the correct number of bytes have been written.
b. If more or less than 4 bytes are data written at the beginning or during any of the append operations.
c. If a read bit is sent.
4.6
Single Byte Read
condition followed by the I
2
C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit will be a 0. After receiving the TAS5518 address and the read/write bit, the TAS5518 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5518 address and the read/write bit again. This time the read/write bit will be a 1, indicating a read transfer. After receiving the TAS5518 and the read/write bit the TAS5518 again responds with an acknowledge bit. Next, the
TAS5518 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Start
Condition Acknowledge
Repeat Start
Condition
Acknowledge Acknowledge
Not
Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 D1 D0 ACK
I
2
C Device Address and
Read/Write Bit
Sub-Address I
2
C Device Address and
Read/Write Bit
Figure 4−4. Single Byte Read Transfer
Data Byte
Stop
Condition
4.7
Multiple Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes
the master device responds with an acknowledge bit after receiving each data byte.
Start
Condition Acknowledge
Repeat Start
Condition
Acknowledge Acknowledge Acknowledge Acknowledge
Not
Acknowledge
A6 A0 R/W ACK
A7 A6 A5
A0 ACK A6 A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
I
2
C Device Address and
Read/Write Bit
Sub-Address I
2
C Device Address and
Read/Write Bit
First Data Byte
Figure 4−5. Multiple Byte Read Transfer
Other Data Bytes Last Data Byte
Stop
Condition
SLES115 — August 2004 TAS5518
57
I
2
C Serial Control Interface (Slave Address 0x36)
58
TAS5518 SLES115 — August 2004
Serial Control I
2
C Register Summary
5 Serial Control I
2
C Register Summary
The TAS5518 slave address is 0x36. See the Serial Control I
2
bit definitions.
C Register Bit Definitions chapter for complete
Note that u indicates unused bits.
I
2
C
SUBADDRESS
0x00
0x01
0x02
0x03
0x04
0x05 – 0x0C
0x0D
0x0E
0x0F
0x10 – 0x13
0x14
0x15
0x16
TOTAL
BYTES
1
1
1
1
1
1
1
1
1
1
1
1
REGISTER FIELDS
Clock control register
DESCRIPTION OF CONTENTS
Set data rate and MCLK frequency
DEFAULT STATE
1. Fs = 48 kHz
2. MCLK = 256 Fs = 12.288 MHz
0x01 General status register
Error status register
Clip indicator and ID code for the
TAS5518
PLL, SCLK, LRCLK, and frame slip errors
No errors
System control register 1
System control register 2
Channel configuration registers
Headphone configuration register
Serial data interface register
Soft mute register
Automute control
Automute PWM threshold and backend reset period
Modulation limit register
PWM high pass, clock set, un-mute select, PSVC select
Automute and de-emphasis control
Configure channels 1, 2, 3, 4, 5, 6, 7, and 8
Configure headphone output
1. PWM high pass disabled
2. Auto clock set
3. Hard un-mute on clock error recovery
4. PSVC HIZ disable
1. Automute timeout disable
2. Post-DAP detection automute enabled
3. 8-Ch device input detection automute enabled
4. Un-mute threshold 6 dB over input
5. No de-emphasis
1. Enable backend reset
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Don’t remap the output for the
TAS5182
6. Don’t go low-low in mute
7. Don’t remap Hi-Z state to low-low state
1. Disable backend reset sequence
2 Valid does not have to be low for reset
3. Valid does not have to be low for mute
4. Normal BEPolarity
5. Don’t remap output to comply with 5182
6. Don’t go low-low in mute
7. Don’t remap Hi−Z state to low-low state
24-bit I2S Set serial data interface to right justified, I2S, or left justified
Soft mute for channels 1, 2, 3, 4, 5, 6,
7, and 8
RESERVED
Set auto-mute delay and threshold
Set PWM auto-mute threshold, set backend reset period
Set modulation index
Un-mute all channels
1. Set auto-mute delay = 5 ms
2. Set auto-mute threshold less than bit 8
1. Set the PWM threshold the same as the TAS5518 input threshold
2. Set backend reset period = 5 ms
97.7%
SLES115 — August 2004 TAS5518
59
Serial Control I
2
C Register Summary
I
2
C
SUBADDRESS
0x17−0x1A
0x1B–0x22
0x23
0x24−0x3F
0x40
0x41–0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51–0x88
0x89–0x90
0x91
0x92
0x93
0x94
0x96
0x97
TOTAL
BYTES
1/Reg.
1
4
32/Reg
4
4
4
4
4
4
4
4
REGISTER FIELDS
Inter-channel delay registers
Inter-channel offset
Bank switching command register
See the Input Mixer Registers
(0x41 – 0x48, Channels 1 – 8)
section
20/Reg. See the next section
8
4
8
4
8
4
4 ipmix_1_to_ch8 ipmix_2_to_ch8 ipmix_7_to_ch2
Ch7_bp_bq2
Ch7_bq2 ipmix_8_to_ch12
Ch8_bp_bq2
Ch8_bq2
Bass and Treble Bypass
Ch 1 − 8
Loudness Log2 LG
Loudness Log2 LO
Loudness G
Loudness O
DRC1 control channels 1, 2, 3,
4, 5, 6, and 7
DRC2 Ch 8 Control
DESCRIPTION OF CONTENTS DEFAULT STATE
RESERVED
Set inter-channel delay
Channel 1 delay = −23 DCLK periods
Channel 2 delay = 0 DCLK periods
Channel 3 delay = −16 DCLK periods
Channel 4 delay = +16 DCLK periods
Channel 5 delay = −24 DCLK periods
Channel 6 delay = 8 DCLK periods
Channel 7 delay = −8 DCLK periods
Channel 8 delay = 24 DCLK periods
Minimum absolute default = 0
DCLK periods
Absolute delay offset for channel 1
(0 – 255)
RESERVED
Set up DAP coefficients bank switching for banks 1, 2, and 3
Manual selection – Bank 1
8X8 input crossbar mixer setup
SDIN1−Left to input mixer 1
SDIN1−Right to input mixer 2
SDIN2−Left to input mixer 3
SDIN2−Right to input mixer 4
SDIN3−Left to input mixer 5
SDIN3−Right to input mixer 6
SDIN4−Left to input mixer 7
SDIN4−Right to input mixer 8
Input mixer 1 to Ch 8 mixer coefficient 0.0
Input mixer 1 to Ch 8 mixer coefficient 0.0
Input mixer 7 to Ch 2 mixer coefficient 0.0
Bypass Ch 7 biquad 2 coefficient 0.0
Ch 7 biquad 2 coefficient
Ch 8 biquad 2 output to Ch1 mixer and Ch2 mixer coefficient
1.0
0.0
Bypass Ch 8 biquad 2 coefficient 0
Ch 8 biquad 2 coefficient
Channels 1, 2, 3, 4, 5, 6, 7, and 8 biquad filter coefficients
Bypass bass and treble for channels 1−8
Loudness Log2 LG
Loudness Log2 LO
Loudness G
Loudness O
Loudness biquad coefficient b0
Loudness biquad coefficient b1
Loudness biquad coefficient b2
Loudness biquad coefficient a0
Loudness biquad coefficient a1
DRC1 control channels 1, 2, 3, 4, 5, 6, and 7
DRC1 control channel 8
0.0
1.0
All biquads = All pass for all channels
Bass and treble bypassed for all channels
0.5
0.0
0.0
0.0
0x00, 0x00, 0xD5, 0x13
0x00, 0x00, 0x00, 0x00
0x0F, 0xFF, 0x2A, 0xED
0x00, 0xFE, 0x50, 0x45
0x0F, 0x81, 0xAA, 0x27
DRC1 disabled in channels 1, 2, 3,
4, 5, 6, and 7
DRC2 disabled (channel 8)
60
TAS5518 SLES115 — August 2004
Serial Control I
2
C Register Summary
I
2
C
SUBADDRESS
TOTAL
BYTES
0x9A 12
REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE
Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 energy
Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 (1− energy)
DRC1 energy
DRC1 (1 energy)
0.0041579
0.9958421
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 threshold (T1) – upper 4 bytes 0x00, 0x00, 0x00, 0x00
DRC1 threshold T1
DRC1 threshold (T1) – lower 4 bytes 0x0B, 0x20, 0xE2, 0xB2
Channels 1, 2, 3, 4, 5, 6, and 7 DRC1 threshold (T2) – upper 4 bytes 0x00, 0x00, 0x00, 0x00
DRC1 thresholdT2
DRC1 threshold (T2) – lower 4 bytes 0x06, 0xF9, 0xDE, 0x58
DRC1 slope (k0) 0x0F, 0xC0, 0x00, 0x00 Channels 1, 2, 3, 4, 5, 6, and 7
, DRC1 slope k0
Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 slope k1
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 slope k2
DRC1 slope (k1)
DRC1 slope (k2)
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
Channels 1, 2, 3, 4, 5, 6, and 7 DRC1 offset 1 (O1) – upper 4 bytes
DRC1 offset 1
DRC1 offset 1 (O1) – lower 4 bytes
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 offset 2 (O2) – upper 4 bytes
DRC1 offset 2
DRC1 offset 2 (O2) – lower 4 bytes
DRC1 attack Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 attack
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Attack)
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 Delay
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Delay)
DRC1 (1 – Attack)
DRC1 delay
DRC1 (1 – Delay)
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
Ch 8 DRC2 energy
Ch 8 DRC2 (1− Energy)
Ch 8 DRC2 slope k0
Ch 8 DRC2 slope k1
Ch 8 DRC2 slope k2
Ch 8 DRC2 attack
Ch 8 DRC2 (1− Attack)
Ch 8 DRC2 Delay
Ch 8 DRC2 (1− Delay)
DRC bypass 1
DRC inline 1
DRC bypass 2
DRC inline 2
DRC2 energy
DRC2 (1 – Energy)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
DRC2 threshold (T1) – upper 4 bytes 0x00, 0x00, 0x00, 0x00
DRC2 threshold (T1) – lower 4 bytes 0x0B, 0x20, 0xE2, 0xB2
DRC2 threshold (T2) – upper 4 bytes 0x00, 0x00, 0x00, 0x00
DRC2 threshold (T2) – lower 4 bytes 0x06, 0xF9, 0xDE, 0x58
DRC2 slope (k0)
DRC2 slope (k1)
DRC2 slope (k2)
DRC2 offset (O1) – upper 4 bytes
DRC2 offset (O1) – lower 4 bytes
DRC2 offset (O2) – upper 4 bytes
DRC2 offset (O2) – lower 4 bytes
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
DRC 2 attack
DRC2 (1 – Attack)
DRC2 delay
DRC2 (1 – Delay)
Channel 1 DRC1 bypass coefficient
Channel 1 DRC1 inline coefficient
Channel 2 DRC1 bypass coefficient
Channel 2 DRC1 inline coefficient
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
1.0
0.0
1.0
0.0
SLES115 — August 2004 TAS5518
61
Serial Control I
2
C Register Summary
I
2
C
SUBADDRESS
TOTAL
BYTES
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2–0xCE
0xCF
0xD0
0xD7
0xD8
0xD9
OXDA
0xDB
0xDC
0xDD
0xDE
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
8
8
8
8
8
8
12
12
20
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
REGISTER FIELDS
DRC bypass 3
DRC inline 3
DRC bypass 4
DRC inline 4
DRC bypass 5
DRC inline 5
DRC bypass 6
DRC inline 6
DRC bypass 7
DRC inline 7
DRC bypass 8
DRC inline 8 sel op1−8 and mix to S sel op1−8 and mix to T sel op1−8 and mix to U sel op1−8 and mix to V sel op1−8 and mix to W sel op1−8 and mix to X sel op1−8 and mix to Y sel op1−8 and mix to Z
Volume biquad
Vol, T and B slew rates
Ch1 volume
Ch2 volume
Ch3 volume
Ch4 volume
Ch5 volume
Ch6 volume
Ch7 volume
Ch8 volume
Master volume
Bass filter set (1−5)
Bass filter index
Treble filter set (1−5)
Treble filter index
AM mode and tuned frequency register
DESCRIPTION OF CONTENTS
Channel 3 DRC1 bypass coefficient
Channel 3 DRC1 inline coefficient
Channel 4 DRC1 bypass coefficient
Channel 4 DRC1 inline coefficient
Channel 5 DRC1 bypass coefficient
Channel 5 DRC1 inline coefficient
Channel 6 DRC1 bypass coefficient
Channel 6 DRC1 inline coefficient
Channel 7 DRC1 bypass coefficient
Channel 7 DRC1 inline coefficient
Channel 8 DRC2 bypass coefficient
Channel 8 DRC2 inline coefficient
Select 0 to 2 of eight channels to output mixer S
Select 0 to 2 of eight channels to output mixer T
Select 0 to 2 of eight channels to output mixer U
Select 0 to 2 of eight channels to output mixer V
Select 0 to 2 of eight channels to output mixer W
Select 0 to 2 of eight channels to output mixer X
Select 0 to 3 of eight channels to output mixer Y
Select 0 to 3 of eight channels to output mixer Z
RESERVED
Volume biquad
U (31:24), U (23:16), U (15:12)
VSR(11:8), TBSR(7:0)
Channel 1 volume
Channel 2 volume
Channel 3 volume
Channel 4 volume
Channel 5 volume
Channel 6 volume
Channel 7 volume
Channel 8 volume
Master volume
Bass filter set (all channels)
Bass filter level (all channels)
Treble filter set (all channels)
Treble filter level (all channels)
Set-up AM mode for AM-interference reduction
DEFAULT STATE
1.0
0.0
1.0
0.0
1.0
0.0
1.0
0.0
1.0
0.0
1.0
0.0
Select channel 1 to PWM 1
Select channel 2 to PWM 2
Select channel 3 to PWM 3
Select channel 4 to PWM 4
Select channel 5 to PWM 5
Select channel 6 to PWM 6
Select channel 7 to PWM 7
Select channel 8 to PWM 8
All pass
0x00, 0x00, 0x01, 0x3F
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
Mute
Filter set 3
0 dB
Filter set 3
0 dB
AM mode disabled
Select sequence 1
IF frequency = 455 kHz
Use BCD-tuned frequency
62
TAS5518 SLES115 — August 2004
I
2
C
SUBADDRESS
0xDF
0xE0
TOTAL
BYTES
4
4
REGISTER FIELDS
PSVC control range
General control register
0xE1–0xFD
0xFE
0xFF
4 (min) Multiple byte write append register
Serial Control I
2
C Register Summary
DESCRIPTION OF CONTENTS
Set PSVC control range
Six or eight channel configuration,
PSVC enable
RESERVED
Special register
RESERVED
DEFAULT STATE
12-dB control range
Eight channel configuration Power supply volume control disabled
N/A
SLES115 — August 2004 TAS5518
63
Serial Control I
2
C Register Summary
64
TAS5518 SLES115 — August 2004
−
−
−
−
−
−
−
−
−
1
1
1
1
−
D7
0
0
0
0
Serial Control Interface Register Definitions
6 Serial Control Interface Register Definitions
Unless otherwise noted, the I
2
C register default values are in bold font.
Note that u indicates unused bits.
6.1
Clock Control Register (0x00)
Bit D1 is Don’t Care.
1
−
−
0
1
0
0
1
0
−
−
−
−
1
D2
−
−
−
−
1
−
−
0
0
1
0
0
1
−
−
−
−
1
D3
−
−
−
−
1
−
−
1
1
1
0
0
0
−
−
−
−
0
D4
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
0
0
−
D6
0
0
1
1
−
−
−
−
−
−
−
−
−
0
1
0
1
−
D5
0
1
0
1
Table 6−1. Clock Control Register
D1 D0
−
−
−
−
32-kHz data rate
38-kHz data rate
44.1-kHz data rate
48-kHz data rate
1
0
−
−
−
−
FUNCTION
88.2-kHz data rate
96-kHz data rate
176.4-kHz data rate
192-kHz data rate
MCLK frequency = 64
MCLK frequency = 128
MCLK frequency = 192
MCLK frequency = 256
MCLK frequency = 384
MCLK frequency = 512
MCLK frequency = 768
Reserved
Clock register is valid (read only)
Clock register is not valid (read only)
6.2
General Status Register 0 (0x01)
D7
1
−
−
D6
−
1
−
D5
−
−
0
D4
−
−
0
D3
−
−
0
D2
−
−
0
Table 6−2. General Status Register (0x01)
D1
−
−
0
D0
−
−
1
Clip indicator
Bank switching busy
Identification code for TAS5518
FUNCTION
D7
−
−
1
−
−
0
6.3
Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must clear the register (write zeroes) and than read them to determine if there are any persistent errors.
D6
−
−
−
1
−
0
D5
1
−
−
−
−
0
D4
−
1
−
−
−
0
D3
−
−
−
−
1
0
D2
−
−
−
−
−
0
Table 6−3. Error Status Register (0X02)
D1 D0 FUNCTION
−
−
−
−
−
0
−
−
−
−
−
0
PLL phase lock error
PLL auto lock error
SCLK error
LRCLK error
Frame slip
No errors
SLES115 — August 2004 TAS5518
65
Serial Control Interface Register Definitions
D7
0
1
−
−
−
−
6.4
System Control Register 1 (0x03)
Bit D5, D2, D1, and D0 are Don’t Care.
D6
−
−
−
−
−
−
D5 D4
−
−
0
1
−
−
D3
−
−
1
0
D2
Table 6−4. System Control Register 1
D1 D0 FUNCTION
PWM high pass disabled
PWM high pass enabled
Soft unmute on recovery from clock error
Hard unmute on recovery from clock error
PSVC Hi-Z enable
PSVC Hi-Z disable
−
−
−
−
−
−
−
6.5
System Control Register 2 (0x04)
D7
0
−
−
Bit D3 and D2 are Don’t Care.
−
−
−
−
−
−
−
D6
−
0
1
D5
−
−
−
0
1
−
−
−
−
−
−
D4
−
−
−
−
−
0
−
−
1
−
−
D3 D2
Table 6−5. System Control Register 2
D1
−
−
−
−
−
−
0
1
−
0
1
D0
− Reserved
FUNCTION
− PWM automute detection enabled
− PWM automute detection disabled
− 8 Ch device input detection automute enabled
− 8 Ch device input detection automute disabled
− Unmute threshold 6 dB over input threshold
− Unmute threshold equal to input threshold
0 No de-emphasis
1 De-emphasis for Fs = 32 kHz
0 De-emphasis for Fs = 44.1 kHz
1 De-emphasis for Fs = 48 kHz
−
−
−
−
−
−
−
−
−
−
D7
0
1
−
−
6.6
Channel Configuration Control Register (0x05−X0C)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into x05, x06, x07, x08, x09, x0A, x0B, and x0C.
Bit D0 is Don’t Care.
−
−
−
−
−
−
−
−
−
−
D6
−
−
0
1
−
−
0
1
−
−
−
−
−
−
D5
−
−
−
−
0
1
−
−
−
−
−
−
−
−
D4
−
−
−
−
Table 6−6. Channel Configuration Control Registers
−
−
−
−
0
1
−
−
−
−
D3
−
−
−
−
−
−
−
−
−
−
−
−
0
1
D1
−
−
−
−
−
−
−
−
−
−
0
1
−
−
D2
−
−
−
−
D0 FUNCTION
Disable backend reset sequence for a channel − BEErrorRecEn
Enable backend reset sequence for a channel
Valid does not have to be low for this channel to be reset BEValidRst
Valid must be low for this channel to be reset
Valid does not have to be low for this channel to be muted BEValidMute
Valid must be low for this channel to be muted
Normal BEPolarity
Switches PWM+ and PWM− and invert audio signal
Do not remap output to comply with 5182 interface
Remap output to comply with 5182 interface
Do not go to low low in mute − BELowMute
Go to low-low in Mute
Do not remap Hi-Z state to low-low state − BE5111BsMute
Remap Hi-Z state to low-low state
66
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
−
−
−
−
−
−
−
D7
0
−
−
1
−
−
−
6.7
Headphone Configuration Control Register (0x0D)
Bit D0 is Don’t Care.
−
−
−
−
−
−
−
D6
−
1
−
−
0
−
−
−
−
−
−
−
−
−
D5
−
−
0
−
−
1
−
−
−
1
−
−
−
−
D4
−
−
−
−
−
−
0
1
−
−
0
−
−
−
D3
−
−
−
−
−
−
−
Table 6−7. Headphone Configuration Control Register
−
−
−
−
−
0
1
D1
−
−
−
−
−
−
−
−
0
−
−
1
−
−
D2
−
−
−
−
−
−
−
D0 FUNCTION
Disable backend reset sequence for a channel − BEErrorRecEn
Enable backend reset sequence for a channel
Valid does not have to be low for this channel to be reset BEValidRst
Valid must be low for this channel to be reset
Valid does not have to be low for this channel to be muted BEValidMute
Valid must be low for this channel to be muted
Normal BEPolarity
Switches PWM+ and PWM− and invert audio signal
Do not remap output to comply with 5182 interface
Remap output to comply with 5182 interface
Do not go to low low in mute − BELowMute
Go to low-low in Mute
Do not remap Hi-Z state to low-low state − BE5111BsMute
Remap Hi-Z state to low-low state
6.8
Serial Data Interface Control Register (0x0E)
Nine serial modes can be programmed I
2
C.
Table 6−8. Serial Data Interface Control Register Format
RECEIVE SERIAL DATA
INTERFACE FORMAT
Right justified
Right justified
Right justified
I
2
S
I
2
S
I
2
S
Left justified
Left justified
Left justified
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
WORD LENGTHS
16
20
24
16
20
24
16
20
24
D7−D4
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
D3 D2 D1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
SLES115 — August 2004 TAS5518
67
Serial Control Interface Register Definitions
6.9
Soft Mute Register (0x0F)
−
−
0
−
1
−
−
D5
−
−
1
−
0
−
−
−
−
D6
−
−
−
1
0
−
−
−
−
D7
−
−
−
−
0
1
−
−
−
D4
−
−
Table 6−9. Soft Mute Register
−
−
0
−
−
−
−
D0
1
−
−
−
0
−
−
−
−
D1
−
1
−
−
0
−
−
1
−
D2
−
−
−
−
0
−
−
−
1
D3
−
−
Function
Soft Mute Channel 1
Soft Mute Channel 2
Soft Mute Channel 3
Soft Mute Channel 4
Soft Mute Channel 5
Soft Mute Channel 6
Soft Mute Channel 7
Soft Mute Channel 8
Unmute All Channels
6.10 Automute Control Register(0x14)
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
−
−
−
−
−
−
−
−
−
−
−
D7
−
−
−
−
−
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
−
−
−
−
−
−
−
−
−
−
−
D6
−
−
−
−
−
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
−
−
−
−
−
−
−
−
−
−
−
D5
−
−
−
−
−
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
−
−
−
−
−
−
−
−
−
−
−
D4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
1
1
1
0
0
0
D3
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
0
1
1
0
0
0
1
1
1
D2
0
0
0
0
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
0
0
0
0
1
0
1
1
D1
0
0
1
1
0
Table 6−10. Automute Control Register
D0 FUNCTION
0 Set input automute and PWM automute delay to 1 ms
1 Set input automute and PWM automute delay to 2 ms
0 Set input automute and PWM automute delay to 3 ms
1 Set input automute and PWM automute delay to 4 ms
0 Set input automute and PWM automute delay to 5 ms
1 Set input automute and PWM automute delay to 10 ms
0 Set input automute and PWM automute delay to 20 ms
1 Set input automute and PWM automute delay to 30 ms
0 Set input automute and PWM automute delay to 40 ms
1 Set input automute and PWM automute delay to 50 ms
0 Set input automute and PWM automute delay to 60 ms
1 Set input automute and PWM automute delay to 70ms
0 Set input automute and PWM automute delay to 80 ms
1 Set input automute and PWM automute delay to 90 ms
0 Set input automute and PWM automute delay to 100 ms
1 Set input automute and PWM automute delay to 110 ms
−
Set input automute threshold less than Bit 1 (zero input signal), lowest automute threshold.
− Set input automute threshold less than Bit 2
− Set input automute threshold less than Bit 3
− Set input automute threshold less than Bit 4
− Set input automute threshold less than Bit 5
− Set input automute threshold less than Bit 6
− Set input automute threshold less than Bit 7
− Set input automute threshold less than Bit 8
− Set input automute threshold less than Bit 9
− Set input automute threshold less than Bit 10
− Set input automute threshold less than Bit 11
− Set input automute threshold less than Bit 12
− Set input automute threshold less than Bit 13
− Set input automute threshold less than Bit 14
− Set input automute threshold less than Bit 15
68
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
D7
−
−
−
−
−
1
1
−
−
1
1
1
1
1
−
−
−
−
−
−
0
0
1
0
0
0
0
0
0
D6
−
−
−
−
−
1
1
−
−
0
0
0
1
1
−
−
−
−
−
−
1
1
0
0
1
1
0
0
0
D5
−
−
−
−
−
1
1
−
−
0
1
1
0
0
−
−
−
−
−
−
1
1
0
1
0
0
0
0
1
6.11 Automute PWM Threshold and Backend Reset Period (0x15)
D4
Table 6−11. Automute PWM Threshold and Backend Reset Period
D3 D2 D1 D0 FUNCTION
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
0
0
0
1
0
1
1
0
1
X
0
0
1
0
0
1
1
0
0
1
0
0
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
1
−
−
1
0
1
0
1
−
−
−
−
−
−
0
1
0
1
0
1
0
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
− Set PWM automute threshold equals input automute threshold
− Set PWM automute threshold 1 bit more than input automute threshold
− Set PWM automute threshold 2 bits more than input automute threshold
− Set PWM automute threshold 3 bits more than input automute threshold
− Set PWM automute threshold 4 bits more than input automute threshold
− Set PWM automute threshold 5 bits more than input automute threshold
− Set PWM automute threshold 6 bits more than input automute threshold
− Set PWM automute threshold 7 bits more than input automute threshold
− Set PWM automute threshold equals input automute threshold
− Set PWM automute threshold 1 bit less than input automute threshold
− Set PWM automute threshold 2 bits less than input automute threshold
− Set PWM automute threshold 3 bits less than input automute threshold
− Set PWM automute threshold 4 bits less than input automute threshold
Set PWM automute threshold 5 bits less than input automute threshold
Set PWM automute threshold 6 bits less than input automute threshold
Set PWM automute threshold 7 bits less than input automute threshold
0 Set backend reset period < 1 ms
1 Set backend reset period 1 ms
0 Set backend reset period 2 ms
1 Set backend reset period 3 ms
0 Set backend reset period 4 ms
1 Set backend reset period 5 ms
0 Set backend reset period 6 ms
1 Set backend reset period 7 ms
0 Set backend reset period 8 ms
1 Set backend reset period 9 ms
0 Set backend reset period 10 ms
1 Set backend reset period 10 ms
X Set backend reset period 10 ms
SLES115 — August 2004 TAS5518
69
Serial Control Interface Register Definitions
6.12 Modulation Index Limit Register (0x16)
D7 D6 D5 D4
Table 6−12. Modulation Index Limit Register
D3 D2 D1 D0
LIMIT
[DCLKS]
MIN WIDTH
[DCLKS]
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
4
5
6
7
8
1
2
3
8
10
12
14
16
2
4
6
MODULATION INDEX
99.2%
98.4%
97.7%
96.9%
96.1%
95.3%
94.5%
93.8%
D7
1
0
1
0
0
1
0
1
0
1
0
6.13 Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into (0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22).
Bits D1 and D0 are Don’t Care.
D6
0
0
1
0
1
0
1
0
0
1
1
D5
0
0
0
0
1
0
0
1
1
1
1
D3
0
0
0
0
1
0
0
0
0
0
0
D4
0
0
0
0
1
0
0
0
0
0
0
Table 6−13. Interchannel Channel Delay Registers
D2 D1 D0 FUNCTION
0
0
0
0
0
0
0
0
0
1
0
Minimum absolute delay, 0 DCLK cycles, default for channel 1
Maximum positive delay, 31 x 4 DCLK cycles
Maximum negative delay, −32 x 4 DCLK cycles
Default value for Channel 1 −32
Default value for Channel 2 0
Default value for Channel 3 −16
Default value for Channel 4 16
Default value for Channel 5 −24
Default value for Channel 6 8
Default value for Channel 7 −8
Default value for Channel 8 24
D7
0
1
The offset register is mapped into 0x23.
D6
0
1
D5
0
1
D4
0
1
D3
0
1
D2
0
1
Table 6−14. Channel Offset Register
D1 D0 FUNCTION
0
1
0
1
Minimum absolute offset, 0 DCLK cycles default for channel 1
Maximum absolute delay, 255 DCLK cycles
70
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
6.14 Bank Switching Command (0x40)
Bits D31−D24, D22−D19 are Don’t Care.
Table 6−15. Bank Switching Command
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
Unused bits
D23 D22 D21 D20 D19 D18 D17 D16
− 0 0 0
FUNCTION
Manual selection Bank 1
−
−
−
−
0
0
−
−
0
0
0
1
1
1
1 x
0
1
1
0
0
1
1 x
1 Manual selection Bank 2
0 Manual selection Bank 3
1 Automatic bank selection
0 Update the values in Bank 1
1
0
1 x
Update the values in Bank 2
Update the values in Bank 3
Update only the bank map
Update the bank map using values in
D15−D0
1 x x x Do not update the bank map using values in D15−D0
−
−
1
−
−
−
D15 D14 D13 D12 D11 D10 D9
1
−
−
−
1
−
−
−
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
1
1
−
−
−
−
1
−
1
−
−
−
1
−
−
1
−
−
1
1
−
1
−
−
−
D8 FUNCTION
− 32-kHz data rate – Use Bank 1
− 38-kHz data rate – Use Bank 1
− 44.1-kHz data rate – Use Bank 1
− 48-kHz data rate – Use Bank 1
− 88.2-kHz data rate – Use Bank 1
− 96-kHz data rate – Use Bank 1
− 176.4-kHz data rate – Use Bank 1
1 192-kHz data rate – Use Bank 1
1 Default
D7
1
−
−
−
−
1
−
−
−
D6
−
−
−
−
−
1
1
−
−
D5
−
−
−
−
−
1
−
1
−
D4
−
−
−
−
−
1
−
−
1
D3
−
1
−
−
−
1
−
−
−
D2
−
−
1
−
−
1
−
−
−
D1
−
−
−
1
−
1
−
−
−
D0 FUNCTION
− 32-kHz data rate – Use Bank 2
− 38-kHz data rate – Use Bank 2
− 44.1-kHz data rate – Use Bank 2
− 48-kHz data rate – Use Bank 2
− 88.2-kHz data rate – Use Bank 2
− 96-kHz data rate – Use Bank 2
− 176.4-kHz data rate – Use Bank 2
1 192-kHz data rate – Use Bank 2
1 Default
SLES115 — August 2004 TAS5518
71
Serial Control Interface Register Definitions
6.15 Input Mixer Registers (0x41 – 0x48, Channels 1 − 8)
Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and
0x48.
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper 4 bits not used. For 8-gain coefficients, the total is 32 bytes.
Bold indicates the one channel that is passed through the mixer.
I
2
C
SUBADDRESS
Table 6−16. Input Mixer Registers Format (0x41 – 0x48, Channels 1 − 8)
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS DEFAULT STATE
A_to_ipmix[1]
B_to_ipmix[1]
C_to_ipmix[1]
D_to_ipmix[1]
E_to_ipmix[1]
F_to_ipmix[1]
G_to_ipmix[1]
H_to_ipmix[1]
A_to_ipmix[2]
B_to_ipmix[2]
C_to_ipmix[2]
D_to_ipmix[2]
E_to_ipmix[2]
F_to_ipmix[2]
G_to_ipmix[2]
H_to_ipmix[2]
SDIN1−Left (Ch 1) A to Input Mixer 1 coefficient (default = 1)
U (31:28), A_1 (27:24), A_1 (23:16), A_1 (15:8), A_1 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 1 coefficient (default = 0)
U (31:28), B_1 (27:24), B_1 (23:16), B_1 (15:8), B_1 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 1 coefficient (default = 0)
U (31:28), C_1 (27:24), C_1 (23:16), C_1 (15:8), C_1 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 1 coefficient (default = 0)
U (31:28), D_1 (27:24), D_1 (23:16), D_1 (15:8), D_1 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 1 coefficient (default = 0)
U (31:28), E_1 (27:24), E_1 (23:16), E_1 (15:8), E_1 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 1 coefficient (default = 0)
U (31:28), F_1 (27:24), F_1 (23:16), F_1 (15:8), F_1 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 1 coefficient (default = 0)
U (31:28), G_1 (27:24), G_1 (23:16), G_1 (15:8), G_1 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 1 coefficient (default = 0)
U (31:28), H_1 (27:24), H_1 (23:16), H_1 (15:8), H_1 (7:0)
SDIN1−Left (Ch 1) A to Input Mixer 2 coefficient (default = 0)
U (31:28), A_2 (27:24), A_2 (23:16), A_2 (15:8), A_2 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 2 coefficient (default = 1)
U (31:28), B_2 (27:24), B_2 (23:16), B_2 (15:8), B_2 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 2 coefficient (default = 0)
U (31:28), C_2(27:24), C_2(23:16), C_2(15:8), C_2(7:0)
SDIN2−Right (Ch 4) D to Input Mixer 2 coefficient (default = 0)
U (31:28), D_2 (27:24), D_2 (23:16), D_2 (15:8), D_2 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 2 coefficient (default = 0)
U (31:28), E_2 (27:24), E_2 (23:16), E_2 (15:8), E_2 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 2 coefficient (default = 0)
U (31:28), F_2 (27:24), F_2 (23:16), F_2 (15:8), F_2 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 2 coefficient (default = 0)
U (31:28), G_2 (27:24), G_2 (23:16), G_2 (15:8), G_2 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 2 coefficient (default = 0)
U (31:28), H_2 (27:24), H_2 (23:16), H_2 (15:8), H_2 (7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
72
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
I
2
C
SUBADDRESS
TOTAL
BYTES
REGISTER
FIELDS
A_to_ipmix[3]
B_to_ipmix[3]
C_to_ipmix[3]
D_to_ipmix[3]
E_to_ipmix[3]
F_to_ipmix[3]
G_to_ipmix[3]
H_to_ipmix[3]
A_to_ipmix[4]
B_to_ipmix[4]
C_to_ipmix[4]
D_to_ipmix[4]
E_to_ipmix[4]
F_to_ipmix[4]
G_to_ipmix[4]
H_to_ipmix[4]
A_to_ipmix[5]
B_to_ipmix[5]
C_to_ipmix[5]
D_to_ipmix[5]
E_to_ipmix[5]
F_to_ipmix[5]
G_to_ipmix[5]
H_to_ipmix[5]
DESCRIPTION OF CONTENTS
SDIN1−Left (Ch 1) A to Input Mixer 3 coefficient (default = 0)
U (31:28), A_3 (27:24), A_3 (23:16), A_3 (15:8), A_3 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 3 coefficient (default = 0)
U (31:28), B_3 (27:24), B_3 (23:16), B_3 (15:8), B_3 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 3 coefficient (default = 1)
U (31:28), C_3 (27:24), C_3 (23:16), C_3 (15:8), C_3 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 3 coefficient (default = 0)
U (31:28), D_3 (27:24), D_3 (23:16), D_3 (15:8), D_3 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 3 coefficient (default = 0)
U (31:28), E_3 (27:24), E_3 (23:16), E_3 (15:8), E_3 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 3 coefficient (default = 0)
U (31:28), F_3 (27:24), F_3 (23:16), F_3 (15:8), F_3 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 3 coefficient (default = 0)
U (31:28), G_3 (27:24), G_3 (23:16), G_3 (15:8), G_3 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 3 coefficient (default = 0)
U (31:28), H_3 (27:24), H_3 (23:16), H_3 (15:8), H_3 (7:0)
SDIN1−Left (Ch 1) A to Input Mixer 4 coefficient (default = 0)
U (31:28), A_4 (27:24), A_4 (23:16), A_4 (15:8), A_4 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 4 coefficient (default = 0)
U (31:28), B_4 (27:24), B_4 (23:16), B_4 (15:8), B_4 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 4 coefficient (default = 0)
U (31:28), C_4 (27:24), C_4 (23:16), C_4 (15:8), C_4 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 4 coefficient (default = 1)
U (31:28), D_4 (27:24), D_4 (23:16), D_4 (15:8), D_4 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 4 coefficient (default = 0)
U (31:28), E_4 (27:24), E_4 (23:16), E_4 (15:8), E_4 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 4 coefficient (default = 0)
U (31:28), F_4 (27:24), F_4 (23:16), F_4 (15:8), F_4 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 4 coefficient (default = 0)
U (31:28), G_4 (27:24), G_4 (23:16), G_4 (15:8), G_4 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 4 coefficient (default = 0)
U (31:28), H_4 (27:24), H_4 (23:16), H_4 (15:8), H_4 (7:0)
SDIN1−Left (Ch 1) A to Input Mixer 5 coefficient (default = 0)
U (31:28), A_5 (27:24), A_5 (23:16), A_5 (15:8), A_5 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 5 coefficient (default = 0)
U (31:28), B_5 (27:24), B_5 (23:16), B_5 (15:8), B_5 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 5 coefficient (default = 0)
U (31:28), C_5 (27:24), C_5 (23:16), C_5 (15:8), C_5 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 5 coefficient (default = 0)
U (31:28), D_5 (27:24), D_5 (23:16), D_5 (15:8), D_5 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 5 coefficient (default = 1)
U (31:28), E_5 (27:24), E_5 (23:16), E_5 (15:8), E_5 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 5 coefficient (default = 0)
U (31:28), F_5 (27:24), F_5 (23:16), F_5 (15:8), F_5 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 5 coefficient (default = 0)
U (31:28), G_5 (27:24), G_5 (23:16), G_5 (15:8), G_5 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 5 coefficient (default = 0)
U (31:28), H_5 (27:24), H_5 (23:16), H_5 (15:8), H_5 (7:0)
DEFAULT STATE
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
SLES115 — August 2004 TAS5518
73
Serial Control Interface Register Definitions
I
2
C
SUBADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
A_to_ipmix[6]
B_to_ipmix[6]
C_to_ipmix[6]
D_to_ipmix[6]
E_to_ipmix[6]
F_to_ipmix[6]
G_to_ipmix[6]
H_to_ipmix[6]
A_to_ipmix[7]
B_to_ipmix[7]
C_to_ipmix[7]
D_to_ipmix[7]
E_to_ipmix[7]
F_to_ipmix[7]
G_to_ipmix[7]
H_to_ipmix[7]
A_to_ipmix[8]
B_to_ipmix[8]
C_to_ipmix[8]
D_to_ipmix[8]
E_to_ipmix[8]
F_to_ipmix[8]
G_to_ipmix[8]
H_to_ipmix[8]
SDIN1−Left (Ch 1) A to Input Mixer 6 coefficient (default = 0)
U (31:28), A_6 (27:24), A_6 (23:16), A_6 (15:8), A_6 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 6 coefficient (default = 0)
U (31:28), B_6 (27:24), B_6 (23:16), B_6 (15:8), B_6 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 6 coefficient (default = 0)
U (31:28), C_6 (27:24), C_6 (23:16), C_6 (15:8), C_6 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 6 coefficient (default = 0)
U (31:28), D_6 (27:24), D_6 (23:16), D_6 (15:8), D_6 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 6 coefficient (default = 0)
U (31:28), E_6 (27:24), E_6 (23:16), E_6 (15:8), E_6 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 6 coefficient (default = 1)
U (31:28), F_6 (27:24), F_6 (23:16), F_6 (15:8), F_6 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 6 coefficient (default = 0)
U (31:28), G_6 (27:24), G_6 (23:16), G_6 (15:8), G_6 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 6 coefficient (default = 0)
U (31:28), H_6 (27:24), H_6 (23:16), H_6 (15:8), H_6 (7:0)
SDIN1−Left (Ch 1) A to Input Mixer 7 coefficient (default = 0)
U (31:28), A_7 (27:24), A_7 (23:16), A_7 (15:8), A_7 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 7 coefficient (default = 0)
U (31:28), B_7 (27:24), B_7 (23:16), B_7 (15:8), B_7 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 7 coefficient (default = 0)
U (31:28), C_7 (27:24), C_7 (23:16), C_7 (15:8), C_7 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 7 coefficient (default = 0)
U (31:28), D_7 (27:24), D_7 (23:16), D_7 (15:8), D_7 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 7 coefficient (default = 0)
U (31:28), E_7 (27:24), E_7 (23:16), E_7 (15:8), E_7 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 7 coefficient (default = 0)
U (31:28), F_7 (27:24), F_7 (23:16), F_7 (15:8), F_7 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 7 coefficient (default = 1)
U (31:28), G_7 (27:24), G_7 (23:16), G_7 (15:8), G_7 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 7 coefficient (default = 0)
U (31:28), H_7 (27:24), H_7 (23:16), H_7 (15:8), H_7 (7:0)
SDIN1−Left (Ch 1) A to Input Mixer 8 coefficient (default = 0)
U (31:28), A_8 (27:24), A_8 (23:16), A_8 (15:8), A_8 (7:0)
SDIN1−Right (Ch 2) B to Input Mixer 8 coefficient (default = 0)
U (31:28), B_8 (27:24), B_8 (23:16), B_8 (15:8), B_8 (7:0)
SDIN2−Left (Ch 3) C to Input Mixer 8 coefficient (default = 0)
U (31:28), C_8 (27:24), C_8 (23:16), C_8 (15:8), C_8 (7:0)
SDIN2−Right (Ch 4) D to Input Mixer 8 coefficient (default = 0)
U (31:28), D_8 (27:24), D_8 (23:16), D_8 (15:8), D_8 (7:0)
SDIN3−Left (Ch 5) E to Input Mixer 8 coefficient (default = 0)
U (31:28), E_8 (27:24), E_8 (23:16), E_8 (15:8), E_8 (7:0)
SDIN3−Right (Ch 6) F to Input Mixer 8 coefficient (default = 0)
U (31:28), F_8 (27:24), F_8 (23:16), F_8 (15:8), F_8 (7:0)
SDIN4−Left (Ch 7) G to Input Mixer 8 coefficient (default = 0)
U (31:28), G_8 (27:24), G_8 (23:16), G_8 (15:8), G_8 (7:0)
SDIN4−Right (Ch 8) H to Input Mixer 8 coefficient (default = 1)
U (31:28), H_8 (27:24), H_8 (23:16), H_8 (15:8), H_8 (7:0)
DEFAULT STATE
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
74
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
6.16 Bass Management Registers (0x49 – 0x50)
Registers 0x49 – 0x50 provide configuration control for bass mangement.
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.
SUBADDRESS
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
TOTAL
BYTES
4
4
4
4
4
4
4
4
Table 6−17. Bass Management Registers Format (0x49 – 0x50)
REGISTER
NAME
DESCRIPTION OF CONTENTS
ipmix_1_to_ch8 Input Mixer 1 to Ch 8 Mixer coefficient (default = 0)
U (31:28), ipmix18 (27:24), ipmix18 (23:16), ipmix18 (15:8), ipmix18 (7:0) ipmix_2_to_ch8 Input Mixer 1 to Ch 8 Mixer coefficient (default = 0)
U (31:28), ipmix28 (27:24), ipmix28 (23:16), ipmix28 (15:8), ipmix28 (7:0) ipmix_7_to_ch12 Input Mixer 7 to Ch 1 and Ch 2 Mixer coefficient (default = 0)
U (31:28), ipmix72 (27:24), ipmix72 (23:16), ipmix72 (15:8), ipmix72 (7:0)
Ch7_bp_bq2 Ch 7 Biquad-2 By-pass coefficient (default = 0)
U (31:28), ch7_bp_bq2 (27:24), ch7_bp_bq2 (23:16), ch7_bp_bq2 (15:8), ch7_bp_bq2 (7:0)
Ch7_bq2 Ch 7 Biquad-2 Inline coefficient (default = 1)
U (31:28), ch6_bq2 (27:24), ch6_bq2 (23:16), ch6_bq2 (15:8), ch6_bq2 (7:0) ipmix_8_to_ch12 Ch 8 Biquad-2 Output to Ch1 Mixer and Ch2 Mixer coefficient
(default = 0)
U (31:28), ipmix8_12 (27:24), ipmix8_12 (23:16), ipmix8_12
(15:8), ipmix8_12 (7:0)
Ch8_bp_bq2 Ch 8 Biquad-2 By-pass coefficient (default = 0)
0U (31:28), ch8_bp_bq2 (27:24), ch8_bp_bq2 (23:16), ch8_bp_bq2 (15:8), ch8_bp_bq2 (7:0)
Ch8_bq2 Ch 8 Biquad-2 Inline coefficient (default = 1)
U (31:28), ch7_bq2 (27:24), ch7_bq2 (23:16), ch7_bq2 (15:8), ch7_bq2 (7:0)
DEFAULT STATE
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
6.17 Biquad Filters Register (0x51 – 0x88)
Table 6−18. Biquad Filters Registers Format (0x51 – 0x88)
I
2
C
SUBADDRESS
0x51 – 0x57
0x58 – 0x5E
0x5F – 0x65
0x66 – 0x6C
0x6D – 0x73
0x74 – 0x7A
0x7B – 0x81
0x82 – 0x88
TOTAL
BYTES
20/Reg.
20/Reg.
20/Reg.
20/Reg.
20/Reg.
20/Reg.
20/Reg.
20/Reg.
REGISTER NAME
Ch1_bq[1] – [7]
Ch2_bq[1] – [7]
Ch3_bq[1] – [7]
Ch4_bq[1] − [7]
Ch5_bq[1] − [7]
Ch6_bq[1] − [7]
Ch7_bq[1] − [7]
Ch8_bq[1] − [7]
DESCRIPTION OF CONTENTS
Ch 1 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 2 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 3 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 4 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 5 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 6 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 7 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 8 Biquads 1 – 7. See Table 6−19 for bit definition.
DEFAULT
STATE
SLES115 — August 2004 TAS5518
75
Serial Control Interface Register Definitions
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.
Table 6−19. Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass)
b
0
Coefficient b
1
Coefficient b
2
Coefficient a
1
Coefficient a
2
Coefficient
U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)
U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)
U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)
U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)
U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)
DEFAULT GAIN COEFFICIENT VALUES
DECIMAL HEX
1.0
0.0
0.0
0.0
0.0
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
6.18 Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 − 8)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C,0x8D, 0x8E, 0x8F, and
0x90. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.
Table 6−20. Bass and Treble Bypass Register Format (0x89−0x90)
REGISTER NAME TOTAL BYTES
Channel bass and treble bypass
Channel bass and treble inline
CONTENTS INITIALIZATION VALUE
U 31:28), Bypass (27:24), Bypass (23:16), Bypass (15:8), Bypass (7:0) 0x00, 0x80, 0x00, 0x00
U (31:28), Inline (27:24), Inline (23:16), Inline (15:8), Inline (7:0) 0x00, 0x00, 0x00, 0x00
6.19 Loudness Registers (0x91 – 0x95)
Table 6−21. Loudness Registers Format (0x91 – 0x95)
I
2
C
SUBADDRESS
0x91
0x93
TOTAL
BYTES
4
4
REGISTER NAME DESCRIPTION OF CONTENTS DEFAULT STATE
Loudness Log2 Gain (LG) U (31:28), LG (27:24), LG (23:16), LG (15:8), LG
(7:0)
Loudness Log2 Offset
(LO)
U (31:24), U (23:16), LO (15:8), LO (7:0)
Loudness Log2 LO
Loudness Gain (G)
LO (31:24), LO (23:16), LO (15:8), LO (7:0)
U (31:28), G (27:24), G (23:16), G (15:8), G (7:0)
U (31:24), U (23:16), O (15:8), O (7:0) Loudness Offset Upper 16 bits (O)
Loudness O Offset Lower
32 bits (O)
O (31:24), O (23:16), O (15:8), O (7:0)
Loudness Biquad (b0)
Loudness Biquad (b1)
Loudness Biquad (b2)
Loudness Biquad (a1)
Loudness Biquad (a2)
0xFF, 0xC0, 0x00, 0x00
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0) 0x00, 0x00, 0xD5, 0x13,
U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0) 0x00, 0x00, 0x00, 0x00,
U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0) 0x0F, 0xFF, 0x2A, 0xED,
U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0) 0x00, 0xFE, 0x50, 0x45,
U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0) 0x0F, 0x81, 0xAA, 0x27
76
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
6.20 DRC1 Control (0x96, Channels 1−7)
Bits D31 – D14 are Don’t Care.
Table 6−22. DCR1 Control (0x96, Channels 1−7)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
Unused bits
D23 D22 D21 D20 D19 D18 D17 D16
Unused bits
D15 D14 D13
1
−
−
−
−
−
0
0
1
−
−
−
D12
0
1
0
1
−
−
−
−
−
−
−
−
D11
−
−
−
−
0
0
1
1
−
−
−
−
D10
−
−
−
−
0
1
0
1
−
−
−
−
D9
−
−
−
−
−
0
−
−
−
0
1
1
FUNCTION
D8
−
−
−
−
−
0
−
−
−
1
0
1
FUNCTION
Channel 1 (node j): No DRC
Channel 1 (node j): Pre-volume DRC
Channel 1 (node j): Post-volume DRC
Channel 1 (node j): No DRC
Channel 2 (node I): No DRC
Channel 2 (node I): Pre-volume DRC
Channel 2 (node I): Post-volume DRC
Channel 2 (node i): No DRC
Channel 3 (node m): No DRC
Channel 3 (node m): Pre-volume DRC
Channel 3 (node m): Post-volume DRC
Channel 3 (node m): No DRC
D7
0
−
−
−
−
−
−
−
−
−
0
1
1
−
−
−
D6
0
−
−
−
−
−
−
−
−
−
1
0
1
−
−
−
D5
−
1
−
−
−
−
−
0
0
1
−
−
−
−
−
−
D4
−
1
−
−
−
−
−
0
1
0
−
−
−
−
−
−
D3
−
−
0
0
1
1
−
−
−
−
−
−
−
−
−
−
D2
−
−
0
1
0
1
−
−
−
−
−
−
−
−
−
−
D1
−
−
−
−
−
−
0
−
−
−
−
−
−
0
1
1
D0
−
−
−
−
−
−
0
−
−
−
−
−
−
1
0
1
FUNCTION
Channel 4 (node n): No DRC
Channel 4 (node n): Pre-volume DRC
Channel 4 (node n): Post-volume DRC
Channel 4 (node n): No DRC
Channel 5 (node o): No DRC
Channel 5 (node o): Pre-volume DRC
Channel 5 (node o): Post-volume DRC
Channel 5 (node o): No DRC
Channel 6 (node p): No DRC
Channel 6 (node p): Pre-volume DRC
Channel 6 (node p): Post-volume DRC
Channel 6 (node p): No DRC
Channel 7 (node q): No DRC
Channel 7 (node q): Pre-volume DRC
Channel 7 (node q): Post-volume DRC
Channel 7 (node q): No DRC
6.21 DRC2 Control (0x97, Channel 8)
0
0
0
0
D31 – D2
0
0
0
0
D1
0
0
1
1
D0
0
1
0
1
Table 6−23. DRC2 Control (0x97, Channel 8)
FUNCTION
Channel 8 (node r): No DRC
Channel 8 (node r): Pre-volume DRC
Channel 8 (node r): Post-volume DRC
Channel 8 (node r): No DRC
SLES115 — August 2004 TAS5518
77
Serial Control Interface Register Definitions
6.22 DRC1 Data Registers (0x98 – 0x9C)
DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7.
Table 6−24. DRC1 Data Registers
I
2
C
SUBADDRESS
0x9A
TOTAL
BYTES
12
REGISTER NAME
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Energy
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Energy)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold Upper 16 bits
(T1)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold Lower 32 bits
(T1)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold
Upper 16 bits (T2)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold
Lower 32 bits (T2)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k0)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k1)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k2)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 1 Upper 16 bits
(O1)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 1 Lower 32 bits
(O1)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 2 Upper 16 bits
(O2)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 2 Lower 32 bits
(O2)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Attack
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Attack)
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Decay
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Decay)
DESCRIPTION OF CONTENTS DEFAULT STATE
U (31:28), E (27:24), E (23:16), E (15:8), E (7:0) 0x00, 0x00, 0x88, 0x3F
U (31:28), 1−E (27:24), 1−E (23:16), 1−E (15:8),
1−E (7:0)
U (31:24), U (23:16), T1 (15:8), T1 (7:0)
T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)
U (31:24), U (23:16), T2 (15:8), T2 (7:0)
T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)
U (31:28), k0 (27:24), k0 (23:16), k0 (15:8), k0 (7:0)
U (31:28), k1 (27:24), k1 (23:16), k1 (15:8), k1 (7:0)
U (31:28), k2 (27:24), k2 (23:16), k2 (15:8), k2 (7:0)
U (31:24), U (23:16), O1 (15:8), O1 (7:0)
O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)
U (31:24), U (23:16), O2 (15:8), O2 (7:0)
O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0)
U (31:28), A (27:24), A (23:16), A (15:8), A (7:0) 0x00, 0x00, 0x88, 0x3F
U (31:28), 1−A (27:24), 1−A (23:16), 1−A (15:8),
1−A (7:0)
0x00, 0x7F, 0x77, 0xC0
U (31:28), D (27:24), D (23:16), D (15:8), D (7:0) 0x00, 0x00, 0x00, 0xAE
U (31:28), 1−D (27:24), 1−D (23:16), 1−D (15:8),
1−D (7:0)
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x7F, 0xFF, 0x51
78
TAS5518 SLES115 — August 2004
6.23 DRC2 Data Registers (0x9D – 0xA1)
DRC2 applies to channel 8.
Table 6−25. DRC2 Data Registers
Serial Control Interface Register Definitions
I
2
C
SUBADDRESS
TOTAL
BYTES
0x9D 8
REGISTER NAME
Channel 8 DRC2 Energy
Channel 8 DRC2 (1− Energy)
Channel 8 DRC2 Threshold
Upper 16 bits (T1)
Channel 8 DRC2 Threshold
Lower 32 bits (T1)
Channel 8 DRC2 Threshold
Upper 16 bits (T2)
Channel 8 DRC2 Threshold
Lower 32 bits (T2)
Channel 8 DRC2 slope (k0)
0x9F 12
Channel 8 DRC2 slope (k1)
Channel 8 DRC2 slope (k2)
Channel 8 DRC2 Offset 1
Upper 16 bits (O1)
Channel 8 DRC2 Offset 1
Lower 32 bits (O1)
Channel 8 DRC2 Offset 2
Upper 16 bits (O2)
Channel 8 DRC2 Offset 2
Lower 32 bits (O2)
Channel 8 DRC2 Attack
Channel 8 DRC2 (1− Attack)
Channel 8 DRC2 Decay
Channel 8 DRC2 (1− Decay)
DESCRIPTION OF CONTENTS
U (31:28), E (27:24), E (23:16), E (15:8), E (7:0)
U (31:28), 1−E (27:24), 1−E (23:16), 1−E (15:8),
1−E (7:0)
U (31:24), U (23:16), T1 (15:8), T1 (7:0)
T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)
U (31:24), U (23:16), T2 (15:8), T2 (7:0)
T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)
U (31:28), k0 (27:24), k0 (23:16), k0 (15:8), k0 (7:0)
U (31:28), k1 (27:24), k1 (23:16), k1 (15:8), k1 (7:0)
U (31:28), k2 (27:24), k2 (23:16), k2 (15:8), k2 (7:0)
U (31:24), U (23:16), O1 (15:8), O1 (7:0)
O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)
U (31:24), U (23:16), O2 (15:8), O2 (7:0)
DEFAULT STATE
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF,
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0) 0x01, 0x95, 0xB2, 0xC0
U (31:28), A (27:24), A (23:16), A (15:8), A (7:0)
U (31:28), 1−A (27:24), 1−A (23:16), 1−A (15:8),
1−A (7:0)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
U (31:28), D (27:24), D (23:16), D (15:8), D (7:0) 0x00, 0x00, 0x00, 0xAE
U (31:28), 1−D (27:24), 1−D (23:16), 1−D (15:8),
1−D (7:0)
0x00, 0x7F, 0xFF, 0x51
SLES115 — August 2004 TAS5518
79
Serial Control Interface Register Definitions
6.24 DRC Bypass Registers (0xA2 – 0xA9)
DRC bypass/inline for channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xA2, 0xA3, 0xA4,
0xA5,0xA6, 0xA7, 0xA8, and 0xA9. 8−bytes are written for each channel. Each gain coefficient is in 28-bit
(5.23) format so 0x00800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper 4 bits not used.
To enable DRC for a given channel (with unity gain), bypass = 0x00000000 and inline = 0x00800000.
To disable DRC for a given channel, bypass = 0x00800000 and inline = 0x00000000.
REGISTER NAME
Channel bass DRC bypass
Channel DRC inline
Table 6−26. DRC Bypass Registers Format (0xA2−0xA9)
TOTAL
BYTES
CONTENTS INITIALIZATION
VALUE
U (31:28), bypass (27:24), bypass (23:16), bypass (15:8), bypass (7:0) 0x00, 0x80, 0x00, 0x00
U (31:28), inline (27:24), inline (23:16), inline (15:8), inline (7:0) 0x00, 0x00, 0x00, 0x00
6.25 8x2 Output Mixer Registers (0xAA – 0xAF)
Output mixers for channels 1–6 map to registers 0xAA – 0xAF.
Total data per register is 8 bytes.
Table 6−27. Output Mixer Control Register Format (Upper 4 Bytes)
0
0
0
0
0
0
D31 D30 D29 D28 D27 D26 D25 D24
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
Select channel 5 to output mixer
Select channel 6 to output mixer
Select channel 7 to output mixer
Select channel 8 to output mixer
FUNCTION
G27 G26 G25 G24 Selected channel gain (upper 4 bits)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued)
D15 D14 D13 D12 D11 D10 D9
G15 G14 G13 G12 G11 G10 G9
D7
G7
D6
G6
D5
G5
D4
G4
D3
G3
D2
G2
D1
G1
D8 FUNCTION
G8 Selected channel gain (continued)
D0 FUNCTION
G0 Selected channel gain (lower 8 bits)
80
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
Table 6−28. Output Mixer Control (Lower 4 Bytes)
D31 D30 D29 D28 D27 D26 D25 D24
0 0 0 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
Select channel 5 to output mixer
Select channel 6 to output mixer
Select channel 7 to output mixer
FUNCTION
Select channel 8 to output mixer
G27 G26 G25 G24 Selected channel gain (upper 4 bits)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued)
D15 D14 D13 D12 D11 D10 D9
G15 G14 G13 G12 G11 G10 G9
D8 FUNCTION
G8 Selected channel gain (continued)
D7
G7
D6
G6
D5
G5
D4
G4
D3
G3
D2
G2
D1
G1
D0 FUNCTION
G0 Selected channel gain (lower 8 bits)
6.26 8x3 Output Mixer Registers (0xB0 – 0xB1)
Output mixers for channels 7 and 8 map to registers 0xB0 and 0xB1.
Total data per register is 12 bytes.
Table 6−29. Output Mixer Control (Upper 4 Bytes)
D31 D30 D29 D28 D27 D26 D25 D24
0 0 0 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
Select channel 5 to output mixer
Select channel 6 to output mixer
Select channel 7 to output mixer
FUNCTION
Select channel 8 to output mixer
G27 G26 G25 G24 Selected channel gain (upper 4 bits)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued)
D15 D14 D13 D12 D11 D10 D9
G15 G14 G13 G12 G11 G10 G9
D8 FUNCTION
G8 Selected channel gain (continued)
D7
G7
D6
G6
D5
G5
D4
G4
D3
G3
D2
G2
D1
G1
D0 FUNCTION
G0 Selected channel gain (lower 8 bits)
SLES115 — August 2004 TAS5518
81
Serial Control Interface Register Definitions
Table 6−30. Output Mixer Control (Middle 4 Bytes)
D31 D30 D29 D28 D27 D26 D25 D24
0 0 0 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
Select channel 5 to output mixer
Select channel 6 to output mixer
Select channel 7 to output mixer
FUNCTION
Select channel 8 to output mixer
G27 G26 G25 G24 Selected channel gain (upper 4 bits)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued)
D15 D14 D13 D12 D11 D10 D9
G15 G14 G13 G12 G11 G10 G9
D8 FUNCTION
G8 Selected channel gain (continued)
D7
G7
D6
G6
D5
G5
D4
G4
D3
G3
D2
G2
D1
G1
D0 FUNCTION
G0 Selected channel gain (lower 8 bits)
Table 6−31. Output Mixer Control (Lower 4 Bytes)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
Select channel 5 to output mixer
Select channel 6 to output mixer
Select channel 7 to output mixer
Select channel 8 to output mixer
G27 G26 G25 G24 Selected channel gain (upper 4 bits)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued)
D15 D14 D13 D12 D11 D10 D9
G15 G14 G13 G12 G11 G10 G9
D7
G7
D6
G6
D5
G5
D4
G4
D3
G3
D2
G2
D1
G1
D8
G8
D0
G0
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (lower 8 bits)
82
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
6.27 Volume Biquad Register (0xCF)
D7
0
0
0
0
0
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.
b o
Coefficient b
1
Coefficient b
2
Coefficient a
1
Coefficient a
2
Coefficient
Table 6−32. Volume Biquad Register Format (Default = All-pass)
DEFAULT GAIN COEFFICIENT VALUES
DECIMAL HEX
0U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)
U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)
U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)
0U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)
U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)
1.0
0.0
0.0
0.0
0.0
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
6.28 Volume Treble and Bass Slew Rates (0xD0)
D31−D10
0
0
0
0
D9
0
0
1
1
D8
0
1
0
1
Table 6−33. Volume Gain Update Rate (Slew Rate)
FUNCTION
512 step update at 4 Fs, 42.6 ms at 48 kHz
1024 step update at 4 Fs, 85.3 ms at 48 kHz
2048 step update at 4 Fs, 170 ms at 48 kHz
2048 step update at 4 Fs, 170 ms at 48 kHz
1
D6
0
0
0
0
0
1
D5
0
0
0
1
1
1
D4
0
0
0
0
1
1
Table 6−34. Treble and Bass Gain Step Size (Slew Rate)
D3
0
0
0
0
1
D2
0
0
1
0
1
D1
0
1
0
0
1
D0
0
1
0
0
1
No operation
FUNCTION
Minimum rate – Updates every 0.083 ms (every LRCLK at 48 kHz)
Update ever 0.67 ms (32 LRCLKs at 48 kHz)
Default rate − Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the maximum constant time that can be set for all sample rates.
1 1 1 1 Minimum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz)
6.29 Volume Registers (0xD1 − 0xD9)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, and
0xD8.
Master volume is mapped into register 0xD9.
Bits D31 − D12 are Don’t Care.
Table 6−35. Volume Registers
D31 D30 D29 D28 D27 D26 D25 D24
Unused bits
FUNCTION
D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11
V11
D10
V10
D9
V9
Unused bits
D8
V8
Volume
D7
V7
D6
V6
D5
V5
D4
V4
D3
V3
D2
V2
D1
V1
D0
V0
Volume
FUNCTION
FUNCTION
FUNCTION
SLES115 — August 2004 TAS5518
83
Serial Control Interface Register Definitions
Table 6−36. Master and Individual Volume Controls
VOLUME INDEX (H)
001
002
003
004
005
006
007
00E
00F
010
044
045
046
008
009
00A
00B
00C
00D
240
241
242
243
244
245
047
048
049
04A
04B
04C
3FF
14.55
14.3
14.05
1
0.75
0.5
16.05
15.8
15.55
15.3
15.05
14.8
EXPECTED
17.81
17.56
17.31
17.06
16.81
16.56
16.31
0.25
0
−0.25
−0.5
−0.75
−1
−126.43
−126.68
−126.93
−127.19
−127.44
Mute
GAIN/INDEX
17.75
17.5
17.25
17
16.75
16.5
16.25
14.5
14.25
14
1
0.75
0.5
16
15.75
15.5
15.25
15
14.75
0.25
0
−0.25
−0.5
−0.75
−1
−126
−126.25
−126.5
−126.75
−127
Mute
TO
Mute Mute
14.55
14.3
14.05
1
0.75
0.5
16.05
15.8
15.55
15.3
15.05
14.8
ACTUAL
17.81
17.56
17.31
17.06
16.81
16.56
16.31
0.25
0
−0.25
−0.5
−0.75
−1
−126.43
−126.99
−126.99
−127.59
−127.59
Mute
Mute
6.30 Bass Filter Set Register (0xDA)
Bits D31−D27, D23−D19, D15−D11, and D7−D3 are Don’t Care.
Table 6−37. Channel 8 Sub Woofer
D31 D30 D29 D28 D27 D26 D25 D24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
No change
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Illegal
Illegal
FUNCTION
84
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
Table 6−38. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and
Left Surround in Eight Channel Configuration)
FUNCTION
0
0
0
0
D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
No change
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Illegal
Illegal
Table 6−39. Channel 4 and 3 (Right and Left Rear)
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
No change
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Illegal
Illegal
D7
0
0
0
0
0
0
0
0
D6
0
0
0
0
0
0
0
0
D5
0
0
0
0
0
0
0
0
D4
0
0
0
0
0
0
0
0
Table 6−40. Channel 7, 2, 1 (Center, Right Front, and Left Front)
D3
0
0
0
0
0
0
0
0
D2
0
0
0
1
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
No change
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Illegal
Illegal
FUNCTION
6.31 Bass Filter Index Register (0xDB)
Index values above 0x24 are invalid.
Table 6−41. Bass Filter Index Register
I
2
C SUBADDRESS TOTAL BYTES REGISTER NAME DESCRIPTION OF CONTENTS
0xDB Bass filter index
(BFI)
4 Ch8_BFI (31:24), Ch65_BFI (23:16), Ch43_BFI
(15:8), Ch721_BFI (7:0)
DEFAULT STATE
0x12, 0x12, 0x12, 0x12,
SLES115 — August 2004 TAS5518
85
Serial Control Interface Register Definitions
TREBLE INDEX
VALUE
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
ADJUSTMENT
(DB)
+5
+4
+3
+8
+7
+6
+2
+1
0
+14
+13
+12
+11
+10
+9
+18
+17
+16
+15
Table 6−42. Bass Filter Index Table
TREBLE INDEX
VALUE
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
ADJUSTMENT
(DB)
−5
−6
−7
−8
−9
−10
−1
−2
−3
−4
−11
−12
−13
−14
−15
−16
−17
−18
6.32 Treble Filter Set Register (0xDC)
Bits D31−D27 are Don’t Care.
Table 6−43. Channel 8 Sub Woofer
D31 D30 D29 D28 D27 D26 D25 D24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
No change
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Illegal
Illegal
FUNCTION
0
0
0
0
0
0
0
0
Table 6−44. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right and Left Surround in Eight Channel Configuration)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
No change
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Illegal
Illegal
86
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
D7
0
0
0
0
0
0
0
0
Table 6−45. Channel 4 and 3 (Right and Left Rear)
0
0
0
0
D15 D14 D13 D12 D11 D10
0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
D9
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
No change
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Illegal
Illegal
FUNCTION
D6
0
0
0
0
0
0
0
0
D5
0
0
0
0
0
0
0
0
0
0
0
0
D4
0
0
0
0
Table 6−46. Channel 7, 2, 1 (Center, Right Front, and Left Front)
D3
0
0
0
0
D2
0
0
0
1
D1
0
0
1
1
D0
0
1
0
1
No change
Treble filter set 1
Treble filter set 2
Treble filter set 3
FUNCTION
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Treble filter set 4
Treble filter set 5
Illegal
Illegal
6.33 Treble Filter Index (0xDD)
Index values above 0x24 are invalid.
I
2
C
SUBADDRESS
0xDD
TOTAL BYTES
Treble filter index (TFI)
Table 6−47. Treble Filter Index Register
REGISTER
NAME
DESCRIPTION OF CONTENTS
4 Ch8_TFI (31:24), Ch65_TFI (23:16), Ch43_TFI (15:8),
Ch721_TFI (7:0)
TREBLE INDEX VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x\06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
DEFAULT STATE
0x12,0x12,0x12,0x12
Table 6−48. Treble Filter Index
ADJUSTMENT (DB)
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+5
+4
+3
+2
+8
+7
+6
+1
0
TREBLE INDEX VALUE ADJUSTMENT (DB)
0x13
0x14
0x15
−1
−2
−3
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
−4
−5
−6
−7
−8
−9
−10
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
−11
−12
−13
−14
−15
−16
−17
−18
SLES115 — August 2004 TAS5518
87
Serial Control Interface Register Definitions
6.34 AM Mode Register (0xDE)
Bits D31−D21 are Don’t Care.
Table 6−49. AM Mode Register
D31 D30 D29 D28 D27 D26 D25 D24
Unused bits
D23 D22 D21 D20 D19 D18 D17 D16
0 − − − −
−
−
−
−
−
−
−
1
−
−
0
0
1
1
−
−
−
−
−
0
1
0
1
−
−
−
−
−
−
−
−
−
0
1
−
−
−
0
−
−
1
−
−
−
−
AM mode disabled
AM mode enabled
Select sequence 1
Select sequence 2
Select sequence 3
Select sequence 4
IF frequency 455
IF frequency 262.5
Use BCD tuned frequency
Use binary tuned frequency
FUNCTION
FUNCTION
Table 6−50. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)
D15 D14 D13 D12 D11 D10
0 0 0 B0 − −
−
0
−
0
−
0
−
0
B3
0
B2
0
D9
−
B1
0
D8
− BCD frequency (1000s kHz)
B0 BCD frequency (100s kHz)
0 Default value
FUNCTION
D7
B3
−
0
D6
B2
−
0
D5
B1
−
0
D4
B0
−
0
D3
−
B3
0
D2
−
B2
0
D1
−
B1
0
D0
− BCD frequency (10s kHz)
B0 BCD frequency (1s kHz)
0 Default value
FUNCTION
Table 6−51. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)
D15 D14 D13 D12 D11 D10
0
0
0
0
0
0
0
0
0
0
B10
0
D9
B9
0
D8
B8 Binary frequency (upper 3 bits)
0 Default value
FUNCTION
D7
B7
0
D6
B6
0
D5
B5
0
D4
B4
0
D3
B3
0
D2
B2
0
D1
B1
0
D0
B0 Binary frequency (lower 8 bits)
0 Default value
FUNCTION
6.35 PSVC Range Register (0xDF)
Bits D31−D2 are zero.
D31 – D2 D1
0 0
0
0
0
0
1
1
D0
0
1
0
1
Table 6−52. PSVC Range Register
FUNCTION
12.04-dB control range for PSVC
18.06-dB control range for PSVC
24.08-dB control range for PSVC
Ignore − retain last value
88
TAS5518 SLES115 — August 2004
Serial Control Interface Register Definitions
6.36 General Control Register (0xE0)
Bits D31−D4 are zero. Bit D0 is Don’t Care.
D31 – D4 D3
0
0
0
0
0
0
0
1
D2
−
1
−
−
0
−
D1
0
−
−
1
−
−
D0
Table 6−53. General Control Register
FUNCTION
8 channel configuration
6 channel configuration
Power supply volume control disable
Power supply volume control enable
Subwoofer part of PSVC (D3 is a write-only bit)
Subwoofer separate from PSVC
6.37 Incremental Multiple Write Append Register (0xFE)
This is a special register used to append data to a previously opened register.
SLES115 — August 2004 TAS5518
89
Serial Control Interface Register Definitions
90
TAS5518 SLES115 — August 2004
TAS5518 Example Application Schematic
7 TAS5518 Example Application Schematic
The following page contains an example application schematic for the TAS5518.
SLES115 — August 2004 TAS5518
91
D
C
B
A
PSVC_MCPU
PSVC
CONF_SEL
/VALID
/VALID_CH5+CH6
/LINE_OUT_ENABLE
5 4
/LINE_OUT_ENABLE
LINE OUTPUT
Phono socket
J950
Phono socket
J951
4
3
2
1
4
3
2
1
GND
HEADPHONE OUTPUT
J900
4
3
2
1
Mini-Jack (3.5mm)
+3.3V
+5.0V
Left + Right Line Out
+5.0V
+3.3V
/OE
OUT_R
PWM_P_R
PWM_M_R
PWM_M_L
PWM_P_L
OUT_L
2 Channel Line Out (TLV272)
+5.0V
Left + Right Headphone
+5.0V
OUT_R
OUT_GND
OUT_L
PWM_HPM_L
PWM_HPP_L
PWM_HPM_R
PWM_HPP_R
2 Channel Headphone Design (TPA112)
MCLK
3
V-HBRIDGE GVDD +5.0V +3.3V
PSVC_MCPU
PSVC
CONF_SEL
/VALID
/VALID_CH5+CH6
/LINE_OUT_ENABLE
PSU and Interface Logic
5
/RESET
/RESET_5518
/BKND_ERR
/BKND_ERR
/SD1_TAS5121
/SD1
/SD2_TAS5121
/SD2
/OTW_TAS5121
/OTW
C10
10nF
R10
200R
C11
100nF
R11
200R
C13
10nF
C12
100nF
C14
100nF
GND
C15
100nF
C16
10uF
R13
3.30R
+3.3V
1
R12
2R
2
C17
100nF
C18
1nF
/RESET_5518
/HP_SEL
/PDN
/MUTE
R14
1R
C19
10uF
+3.3V
C20
100nF
3
4
1
2
VRA_PLL
PLL_FLT_RET
PLL_FLTM
PLL_FLTP
7
8
5
6
AVSS
AVSS
VRD_PLL
AVSS_PLL
9
10
11
12
AVDD_PLL
VBGAP
RESET
HP_SEL
13
14
PDN
MUTE
15
16
DVDD
DVSS
C21
100nF
GND
/RESET
/RESET_5518
/BKND_ERR
/BKND_ERR
/SD1_TAS5121
/SD1
/SD2_TAS5121
/SD2
/OTW_TAS5121
/OTW
X10
13.5MHz
2
C27
15pF
R21
1M
1
C28
15pF
GND
U1
TAS5518
4 3
C25
220nF
C26
10uF
1
R20
22.0R
+3.3V
2
GND
C29
100nF
VR_PWM
PWM_P_4
PWM_M_4
PWM_P_3
PWM_M_3
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VAILD
DVSS
BKND_ERR
DVDD
DVSS
36
35
DVSS
VR_DIG
34
33
40
39
38
37
44
43
42
41
48
47
46
45
/VALID
/BKND_ERR
R18
1R
+3.3V
C22
470nF
C23
10uF
C24
100nF
PSVC
SDIN1
SDIN2
SDIN3
SDIN4
SCLK
LRCLK
SCL
SDA
GND
2
/SD2_TAS5121
/OTW_TAS5121
/VALID_CH5+CH6
/SD2_TAS5121
/OTW_TAS5121
/VALID_CH5+CH6
/SD2_TAS5121
/OTW_TAS5121
/VALID
/SD1_TAS5121
/OTW_TAS5121
/VALID
/SD2_TAS5121
/OTW_TAS5121
/VALID
/SD2_TAS5121
/OTW_TAS5121
/VALID
/SD1_TAS5121
/OTW_TAS5121
/VALID
/SD1_TAS5121
/OTW_TAS5121
/VALID
1
/SD1_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH6 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
V-HBRIDGE
GVDD
1
2
J600
RIGHT BACK
SURROUND
SPEAKER
OUTPUT
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH5 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
V-HBRIDGE
GVDD
1
2
J500
LEFT BACK
SURROUND
SPEAKER
OUTPUT
D
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH8 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
V-HBRIDGE
GVDD
1
2
J800
SUBWOOFER
SPEAKER
OUTPUT
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH7 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
V-HBRIDGE
GVDD
1
2
J700
CENTER
SPEAKER
OUTPUT
C
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH4 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
V-HBRIDGE
GVDD
1
2
J400
RIGHT
SURROUND
SPEAKER
OUTPUT
V-HBRIDGE
GVDD
/SHUTDOWN_TAS5121
/TEMP_WARNING
PWM_P
PWM_M
/VALID
V-HBRIDGE
GVDD
CH3 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
1
2
J300
LEFT
SURROUND
SPEAKER
OUTPUT
B
V-HBRIDGE
GVDD
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH2 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
1
2
J200
RIGHT
SPEAKER
OUTPUT
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
PWM_P
PWM_M
/VALID
CH1 TAS5121 H-Bridge Output Stage
OUT_1
OUT_2
V-HBRIDGE
GVDD
1
2
J100
LEFT
SPEAKER
OUTPUT
A
TAS5518 Example Application Schematic
(Circuit is Subject To Change Without Notice)
2 1
www.ti.com
PACKAGE OPTION ADDENDUM
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
TAS5518PAG
TAS5518PAGG4
TAS5518PAGR
TAS5518PAGRG4
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package
Type
TQFP
TQFP
TQFP
TQFP
Package
Drawing
PAG
PAG
PAG
PAG
Eco Plan
(2)
Pins Package
Qty
64 160 Green (RoHS & no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-4-260C-72 HR
64 CU NIPDAU Level-4-260C-72 HR
64
160 Green (RoHS & no Sb/Br)
1500 Green (RoHS & no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
64 1500 Green (RoHS & no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
23-Mar-2011
*All dimensions are nominal
Device
TAS5518PAGR
Package
Type
Package
Drawing
TQFP PAG
Pins
64
SPQ
1500
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
24.4
A0
(mm)
13.0
B0
(mm)
13.0
K0
(mm)
P1
(mm)
1.5
16.0
W
(mm)
Pin1
Quadrant
24.0
Q2
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
23-Mar-2011
*All dimensions are nominal
Device
TAS5518PAGR
Package Type Package Drawing Pins
TQFP PAG 64
SPQ
1500
Length (mm) Width (mm) Height (mm)
346.0
346.0
41.0
Pack Materials-Page 2
PAG (S-PQFP-G64)
0,50
48
49
33
0,27
0,17
0,08
M
32
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PLASTIC QUAD FLATPACK
64 17
1 16
7,50 TYP
10,20
9,80
SQ
12,20
11,80
SQ
0,05 MIN
1,05
0,95
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Seating Plane
0,08
0,13 NOM
0,25
Gage Plane
0
°
– 7
°
0,75
0,45
4040282 / C 11/96
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