NXP MCF51CN128 32-bit ColdFire. V1 Microcontrollers Data Sheet

Freescale Semiconductor

Addendum

Document Number: QFN_Addendum

Rev. 0, 07/2014

Addendum for New QFN

Package Migration

This addendum provides the changes to the 98A case outline numbers for products covered in this book.

Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package.

To view the new drawing, go to Freescale.com and search on the new 98A package number for your device.

For more information about QFN package use, see EB806: Electrical Connection Recommendations for

the Exposed Pad on QFN and DFN Packages.

© Freescale Semiconductor, Inc., 2014. All rights reserved.

Part Number

MC68HC908JW32

MC9S08AC16

MC9S908AC60

MC9S08AC128

MC9S08AW60

MC9S08GB60A

MC9S08GT16A

MC9S08JM16

MC9S08JM60

MC9S08LL16

MC9S08QE128

MC9S08QE32

MC9S08RG60

MCF51CN128

MC9RS08LA8

MC9S08GT16A

MC9S908QE32

MC9S908QE8

MC9S08JS16

MC9S08QB8

MC9S08QG8

MC9S08SH8

MC9RS08KB12

MC9S08QG8

MC9RS08KB12

MC9S08QG8

MC9RS08KA2

Package Description

48 QFN

48 QFN

32 QFN

32 QFN

32 QFN

24 QFN

24 QFN

24 QFN

24 QFN

16 QFN

8 DFN

6 DFN

Original (gold wire) package document number

Current (copper wire) package document number

98ARH99048A 98ASA00466D

98ARL10606D

98ARH99035A

98ARE10566D

98ASA00071D

98ARL10608D

98ARL10605D

98ARE10714D

98ASA00087D

98ARE10614D

98ARL10557D

98ARL10602D

98ASA00466D

98ASA00473D

98ASA00473D

98ASA00736D

98ASA00734D

98ASA00474D

98ASA00474D

98ASA00602D

98ASA00671D

98ASA00672D

98ASA00735D

2

Addendum for New QFN Package Migration, Rev. 0

Freescale Semiconductor

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF51CN128

Rev. 4, 5/2009

MCF51CN128 ColdFire

Microcontroller

Cover: MCF51CN128

MCF51CN128

80 LQFP

14 mm

× 14 mm

64 LQFP

10 mm

× 10 mm

48 QFN

7 mm

× 7 mm

The MCF51CN128 device is a low-cost, low-power, high-performance 32-bit ColdFire V1 microcontroller (MCU) featuring 10/100 BASE-T/TX fast ethernet controller (FEC), media independent interface (MII) to connect an external physical transceiver (PHY), and multi-function external bus interface.

MCF51CN128 also has multiple communication interfaces for various ethernet gateway applications. MCF51CN128 is the first ColdFire V1 device to incorporate ethernet and external bus interface along with new features to minimize power consumption and increase functionality in low-power modes.

The MCF51CN128 features the following functional units:

• 32-bit ColdFire V1 Central Processing Unit (CPU)

– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz

CPU from 2.1 V to 1.8 V across temperature range of

–40 °C to 85 °C

– Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM

(0.76 DMIPS/MHz from flash)

– ColdFire Instruction Set Revision C (ISA_C)

– Support for up to 45 peripheral interrupt requests and 7 software interrupts

• On-Chip Memory

– 128 KB Flash, 24 KB RAM

– Flash read/program/erase over full operating voltage and temperature

– On-chip memory aliased to create a contiguous memory space with off-chip memory

– Security circuitry to prevent unauthorized access to

Peripherals, RAM, and flash contents

• Ethernet

– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet controller with direct memory access (DMA); supports half or full duplex; operation is limited to 3.0 V to 3.6 V

– MII—media independent interface to connect ethernet controller to external PHY; includes output clock for external PHY

• External Bus

– Mini-FlexBus—Multi-function external bus interface; supports up to 1 MB memories, gate-array logic, simple slave device or glueless interfaces to standard chip-selected asynchronous memories

– Programmable options: access time per chip select, burst and burst-inhibited transfers per chip select, transfer direction, and address setup and hold times

• Power-Saving Modes

– Two low-power stop modes, one of which allows limited use of some peripherals (ADC, KBI, RTC)

– Reduced-power wait mode shuts off CPU and allows full use of all peripherals; FEC can remain active and conduct DMA transfers to RAM and assert an interrupt to wake up the CPU upon completion

– Low-power run and wait modes allow peripherals to run while the voltage regulator is in standby

– Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents

– Low-power external oscillator that can be used in stop3 mode to provide accurate clock source to active peripherals

– Low-power real-time counter for use in run, wait, and stop modes with internal and external clock sources

– 6 μs typical wake-up time from stop3 mode

– Pins and clocks to peripherals not available in smaller packages are automatically disabled for reduced current consumption; no user interaction is needed

• Clock Source Options

– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 25 MHz

– Multi-Purpose Clock Generator (MCG) — Flexible clock source module with either frequency-locked-loop

(FLL) or phase-lock loop (PLL) clock options. FLL can be controlled by internal or external reference and

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

© Freescale Semiconductor, Inc., 2009. All rights reserved.

includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and voltage. PLL derives a higher accuracy clock source derived by an external reference

• System Protection

– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock

– Low-voltage detection with reset or interrupt; selectable trip points

– Illegal opcode and illegal address detection with programmable reset or exception response

– Flash block protection

• Development Support

– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and

9S12x families debug modules

– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response

– 64-entry processor status and debug data trace buffer with programmable start/stop conditions

• Peripherals

– ADC—Up to 12 channel, 12-bit resolution; 2.5

μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V

– SCI—Three modules with optional 13-bit break

– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting

– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing

– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel

– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base, time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up without external components; runs in all MCU modes

– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler

• Input/Output

– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions

– 16 keyboard interrupt (KBI) pins with selectable polarity

– Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on all output pins

– 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)

2

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Table of Contents

1 MCF51CN128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4

1.1

Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2

Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.2

Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12

3.3

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12

3.4

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13

3.5

ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14

3.6

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7

Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18

3.8

External Oscillator (XOSC) Characteristics . . . . . . . . .20

3.9

Multipurpose Clock Generator (MCG) Specifications . .21

3.10 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .23

3.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . .24

3.11.1 Receive Signal Timing Specifications . . . . . . . .24

3.11.2 Transmit Signal Timing Specifications . . . . . . . .25

3.11.3 Asynchronous Input Signal Timing Specifications25

3.11.4 MII Serial Management Timing Specifications .26

3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.12.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .28

3.12.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.12.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .32

3.12.5 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .35

3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36

4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36

6.1

80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.2

64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

6.3

48-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

List of Tables

Table 1.. MCF51CN128 Series Device Comparison . . . . . . . . . . .4

Table 2.. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .8

Table 3.. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .12

Table 4.. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12

Table 5.. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13

Table 6.. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .14

Table 7.. ESD and Latch-Up Protection Characteristics . . . . . . .14

Table 8.. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 9.. Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18

Table 10..XOSC and ICS Specifications (Temperature Range = –40 to 85

°C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 11..MCG Frequency Specifications (Temperature Range = –40 to 125

°C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 12..Mini-FlexBus AC Timing Specifications . . . . . . . . . . . .23

Table 13..Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14..Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15..MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 25

Table 16..MII Serial Management Channel Signal Timing . . . . . 26

Table 17..Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18..TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 19..SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20..12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 32

Table 21..12-bit ADC Characteristics (V

REFH

= V

DDAD

, V

REFL

=

V

SSAD

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22..Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 23..Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 24..Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 25..Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

List of Figures

Figure 1..MCF51CN128 Series Block Diagram . . . . . . . . . . . . . . 5

Figure 2..Pin Assignments in 80-Pin LQFP Package. . . . . . . . . . 6

Figure 3..Pin Assignments in 64-Pin LQFP Package. . . . . . . . . . 7

Figure 4..Pin Assignments in 48-Pin QFN Package. . . . . . . . . . . 8

Figure 5..Pull-up and Pull-down Typical Resistor Values . . . . . . 16

Figure 6..Typical Low-Side Driver (Sink) Characteristics — Low Drive

(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7..Typical Low-Side Driver (Sink) Characteristics — High

Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8..Typical High-Side (Source) Characteristics — Low Drive

(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9..Typical High-Side (Source) Characteristics — High Drive

(PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10..Typical Run I

DD

for FBE and FEI, I

DD

vs. V

DD

(ADC off, All Other Modules Enabled) . . . . . . . . . . . . . 19

Figure 11..Typical Crystal or Resonator Circuit: High Range and Low

Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12..Typical Crystal or Resonator Circuit: Low Range/Low

Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13..Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 23

Figure 14..Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 24

Figure 15..MII Receive Signal Timing Diagram . . . . . . . . . . . . . 25

Figure 16..MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 25

Figure 17..MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 25

Figure 18..MII Serial Management Channel TIming Diagram . . 26

Figure 19..Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 20..IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21..Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22..Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 28

Figure 23..SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 30

Figure 24..SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . 30

Figure 25..SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 31

Figure 26..SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 31

Figure 27..ADC Input Impedance Equivalency Diagram . . . . . . 33

3

MCF51CN128 ColdFire Microcontroller Advance Information Data Sheet, Rev. 4

Freescale Semiconductor

4

MCF51CN128 Series Comparison

1 MCF51CN128 Series Comparison

1.1

Device Comparison

The following table compares the various device derivatives available within the MCF51CN128 series.

Table 1. MCF51CN128 Series Device Comparison

MCF51CN128

Feature

80-pin 64-pin 48-pin

Flash memory size (KB)

RAM size (KB)

V1 ColdFire core equiped with BDM (background debug module) and 2X3 Crossbar switch

ADC (analog-to-digital converter) channels (12-bit)

FEC (Fast Ethernet Controller with MII Interface)

COP (computer operating properly)

IIC1 (inter-integrated circuit)

128

24

Yes

12

Yes

Yes

Yes

IIC2

IRQ (interrupt request input)

KBI (keyboard interrupts)

LVD (low-voltage detector)

MCG (multipurpose clock generator)

Port I/O

1

RGPIO (rapid general-purpose I/O)

RTC (real-time counter)

SCI1, SCI2 & SCI3 (serial communications interface)

SPI1 & SPI2 (serial peripheral interface)

16

70

16

Yes

Yes

12

Yes

Yes

54

16

Yes

Yes

Yes

6

38

8

TPM1 (Timer/PWM Module) channels

TPM2 channels

MTIM1 & MTIM2

External Timer Clocks

Mini-FlexBus

3

3

2

Yes

3

3

Yes

1

0

2

3

3

1

0

XOSC (crystal oscillator) Yes

1

2

All GPIO are muxed with other functions

TMRCLK2 is not available on the 48 pin package, although MTIM2 can be used as an internal timebase using on-chip clock sources.

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

MCF51CN128 Series Comparison

1.2

Block Diagram

The following figure shows the connections between the MCF51CN128 series pins and modules.

VDDA/

VREFH

VSSA/

VREFL

BDM

Port D:

BKGD/MS

BKGD/MS/PTD6/RGPIO6

RESET/PTC3

VDD1

VSS1

VDD2

VSS2

VDD3

VSS3

VDD4

VSS4

SIM

VREG

DBG

INTC

ColdFire V1 core

COP LVD

FLASH

128 KB

RAM

24 KB

MII

Port A:

MII_TX_CLK

MII_RX_CLK

MII_TX_EN

MII_TXD0

MII_TXD1

MII_TXD2

MII_TXD3

Port B:

MII_TX_ER

MII_RX_DV

MII_RXD0

MII_RXD1

MII_RXD2

MII_RXD3

MII_RX_ER

MII_CRS

Port C:

MII_COL

MII_MDC

MII_MDIO

FEC

VDDA

VREFH

VSSA

VREFL

ADC

Port C:

ADP3-

ADP0

Port D:

ADP8-

ADP4

Port E:

ADP11-

ADP9

TPM1

Port E:

TPM1CH2

TPM1CH1

TPM1CH0

Port B, F or H* : TPM1CL K

TPM2

Port F/H:

TPM2CH2

TPM2CH1

TPM2CH0

Port B, F or H* : TPM2CLK

RGPIO

Port F:

RGPIO15

RGPIO14

RGPIO13

RGPIO12

RGPIO11

RGPIO10

RGPIO9

RGPIO8

Port D:

RGPIO7

RGPIO6

RGPIO5

RGPIO4

RGPIO3

RGPIO2

RGPIO1

RGPIO0

Port F:

FB_D7-FB_D0

Port H:

FB_A19-FB_A16

FB_A11-FB_A8

Port G:

FB_CS1

FB_CS0

Mini-FlexBus OE

FB_RW

FB_A5-FB_A2

Port I:

FB_A15-FB_A12

FB_A7-FB_A6

Port E:

FB_A1-FB_A0

External Interrupt

Port C:

IRQ

MCG

IIC1

Port C/G:

SDA1

SCL1

IIC2

Port C/G:

SDA2

SCL2

KBI

Port E:

KBI2P7

KBI2P6

KBI2P5

KBI2P4

KBI2P3

KBI2P2

KBI2P1

KBI2P0

Port G/I:

KBI1P7

KBI1P6

KBI1P5

KBI1P4

KBI1P3

KBI1P2

KBI1P1

KBI1P0

XOSC

Port D:

EXTAL

XTAL

Port A:

CLKOUT

RTC

MTIM1

Port B, F or H* :

MTIM1CLK

MTIM2

Port B, F or H* :

MTIM2CLK

SCI1

SCI2

Port D:

RXD1

TXD1

Port D:

RXD2

TXD2

SCI3

Port E:

RXD3

TXD3

SPI1

Port C:

SS1

SPSCK1

MOSI1

MISO1

SPI2

Port D/E:

SS2

SPSCK2

MOSI2

MISO2

* TPMx and MTIMx external clocks each have the choice of being assigned to either TMRCLK1 or TMRCLK2.

Figure 1. MCF51CN128 Series Block Diagram

PTA7/MII_RX_DV/MOSI2

PTA6/MII_RXD0/MISO2

PTA5/MII_RXD1/SPSCK2

PTA4/MII_RXD2/RXD3

PTA3/MII_RXD3/TXD3

PTA2/MII_MDC/SCL2

PTA1/MII_MDIO/SDA2

PTA0/PHYCLK

PTB7/MII_TXD2/TPM2CH1

PTB6/MII_TXD1/TPM2CH0

PTB5/MII_TXD0/SPSCK1

PTB4/MII_TX_EN/MISO1

PTB3/MII_TX_CLK/MOSI1

PTB2/MII_TX_ER/SS1

PTB1/MII_RX_ER/TMRCLK1

PTB0/MII_RX_CLK/SS2

PTC7/SDA2/SPSCK1/ADP8

PTC6/SCL2/MISO1/ADP9

PTC5/MOSI1/ADP10

PTC4/IRQ/SS1/ADP11

PTC2/MII_CRS/SDA1

PTC1/MII_COL/SCL1

PTC0/MII_TXD3/TPM2CH2

PTD7/RGPIO7/SPSCK2/ADP3

BKGD/MS/PTD6/RGPIO6

PTD5/RGPIO5/XTAL

PTD4/RGPIO4/EXTAL

PTD3/RGPIO3/RXD2/ADP4

PTD2/RGPIO2/TXD2/ADP5

PTD1/RGPIO1/RXD1/ADP6

PTD0/RGPIO0/TXD1/ADP7

PTE7/KBI2P7/FB_CS0/RXD3

PTE6/KBI2P6/FB_D0/TXD3

PTE5/KBI2P5/IRQ/TPM1CH2

PTE4/KBI2P4/CLKOUT/TPM1CH1

PTE3/KBI2P3/TPM1CH0

PTE2/KBI2P2/SS2/ADP0

PTE1/KBI2P1/MOSI2/ADP1

PTE0/KBI2P0/MISO2/ADP2

PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2

PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1

PTF5/RGPIO13/FB_D4/TPM2CH0

PTF4/RGPIO12/FB_D5/TMRCLK2

PTF3/RGPIO11/FB_A16/FB_AD16

PTF2/RGPIO10/FB_A17/FB_AD17

PTF1/RGPIO9/FB_A18/FB_AD18

PTF0/RGPIO8/FB_A19/FB_AD19

PTG7/KBI1P7/FB_D1

PTG6/KBI1P6/FB_D2

PTG5/KBI1P5/FB_D3

PTG4/KBI1P4/FB_RW

PTG3/KBI1P3/FB_A5/FB_AD5/SDA1

PTG2/KBI1P2/FB_A6/FB_AD6/SCL1

PTG1/KBI1P1/FB_A7/FB_AD7/SDA2

PTG0/KBI1P0/FB_A8/FB_AD8/SCL2

PTH7/FB_A9/FB_AD9/TPM2CH2

PTH6/FB_A10/FB_AD10/TPM2CH1

PTH5/FB_A11/FB_AD11

PTH4/FB_A12/FB_AD12

PTH3/FB_D6/TPM2CH0

PTH2/FB_D7/TMRCLK1

PTH1/FB_OE

PTH0/FB_A15/FB_AD15

PTJ5/FB_A0/FB_AD0

PTJ4/FB_A1/FB_AD1

PTJ3/FB_A2/FB_AD2

PTJ2/FB_A3/FB_AD3

PTJ1/FB_A4/FB_AD4

PTJ0/FB_ALE/FB_CS1

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

5

Pin Assignments

2 Pin Assignments

This section describes the pin assignments for the available packages. See for pin availability by package pin-count.

VDD1

VSS1

PTA0/PHYCLK

PTA1/MII_MDIO/SDA2

PTA2/MII_MDC/SCL2

PTA3/MII_RXD3/TXD3

PTA4/MII_RXD2/RXD3

PTA5/MII_RXD1/SPSCK2

PTA6/MII_RXD0/MISO2

PTA7/MII_RX_DV/MOSI2

PTB0/MII_RX_CLK/SS2

PTB1/MII_RX_ER/TMRCLK1

PTF0/RGPIO8/FB_A19/FB_AD19

PTF1/RGPIO9/FB_A18/FB_AD18

PTF2/RGPIO10/FB_A17/FB_AD17

PTF3/RGPIO11/FB_A16/FB_AD16

PTH0/FB_A15/FB_AD15

PTH1/FB_OE

PTH2/FB_D7/TMRCLK1

PTH3/FB_D6/TPM2CH0

7

8

9

10

11

12

13

3

4

5

6

1

2

14

15

16

17

18

19

20

80-Pin LQFP

54

53

52

51

50

49

48

60

59

58

57

56

55

47

46

45

44

43

42

41

PTG7/KBI1P7/FB_D1

PTG6/KBI1P6/FB_D2

PTG5/KBI1P5/FB_D3

PTG4/KBI1P4/FB_RW

PTG3/KBI1P3/FB_A5/FB_AD5/SDA1

PTG2/KBI1P2/FB_A6/FB_AD6/SCL1

PTG1/KBI1P1/FB_A7/FB_AD7/SDA2

PTG0/KBI1P0/FB_A8/FB_AD8/SCL2

PTD3/RGPIO3/RXD2/ADP4

PTD2/RGPIO2/TXD2/ADP5

PTD1/RGPIO1/RXD1/ADP6

PTD0/RGPIO0/TXD1/ADP7

PTC7/SDA2/SPSCK1/ADP8

PTC6/SCL2/MISO1/ADP9

PTC5/MOSI1/ADP10

PTC4/IRQ/SS1/ADP11

VSSA

VDDA

VSS3

VDD3

6

Figure 2. Pin Assignments in 80-Pin LQFP Package

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Pin Assignments

VDD1

VSS1

PTA0/PHYCLK

PTA1/MII_MDIO/SDA2

PTA2/MII_MDC/SCL2

PTA3/MII_RXD3/TXD3

PTA4/MII_RXD2/RXD3

PTA5/MII_RXD1/SPSCK2

PTA6/MII_RXD0/MISO2

PTA7/MII_RX_DV/MOSI2

PTB0/MII_RX_CLK/SS2

PTB1/MII_RX_ER/TMRCLK1

PTF0/RGPIO8/FB_A19/FB_AD19

PTF1/RGPIO9/FB_A18/FB_AD18

PTF2/RGPIO10/FB_A17/FB_AD17

PTF3/RGPIO11/FB_A16/FB_AD16

8

9

10

11

12

13

5

6

7

1

2

3

4

14

15

16

64-Pin LQFP 41

40

39

38

37

36

48

47

46

45

44

43

42

35

34

33

PTG3/KBI1P3/FB_A5/FB_AD5/SDA1

PTG2/KBI1P2/FB_A6/FB_AD6/SCL1

PTG1/KBI1P1/FB_A7/FB_AD7/SDA2

PTG0/KBI1P0/FB_A8/FB_AD8/SCL2

PTD3/RGPIO3/RXD2/ADP4

PTD2/RGPIO2/TXD2/ADP5

PTD1/RGPIO1/RXD1/ADP6

PTD0/RGPIO0/TXD1/ADP7

PTC7/SDA2/SPSCK1/ADP8

PTC6/SCL2/MISO1/ADP9

PTC5/MOSI1/ADP10

PTC4/IRQ/SS1/ADP11

VSSA

VDDA

VSS3

VDD3

Figure 3. Pin Assignments in 64-Pin LQFP Package

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

7

Pin Assignments

VDD1 1

VSS1 2

PTA0/PHYCLK 3

PTA1/MII_MDIO/SDA2 4

PTA2/MII_MDC/SCL2 5

PTA3/MII_RXD3/TXD3 6

PTA4/MII_RXD2/RXD3 7

PTA5/MII_RXD1/SPSCK2 8

PTA6/MII_RXD0/MISO2 9

PTA7/MII_RX_DV/MOSI2 10

PTB0/MII_RX_CLK/SS2 11

PTB1/MII_RX_ER/TMRCLK1 12

48-Pin QFN

36 PTD3/RGPIO3/RXD2/ADP4

35 PTD2/RGPIO2/TXD2/ADP5

34 PTD1/RGPIO1/RXD1/ADP6

33 PTD0/RGPIO0/TXD1/ADP7

32 PTC7/SDA2/SPSCK1/ADP8

31 PTC6/SCL2/MISO1/ADP9

30 PTC5/MOSI1/ADP10

29 PTC4/IRQ/SS1/ADP11

28 VSSA

27 VDDA

26 VSS3

25 VDD3

8

Figure 4. Pin Assignments in 48-Pin QFN Package

NOTE

There is no electrical connection to the flag for 48-pin QFN packages.

Table 2. Package Pin Assignments

80-Pin 64-Pin 48-Pin Default Function

1

2

3

1

2

3

1

2

3

VDD1

VSS1

PTA0

Alt 1

—

—

PHYCLK

Alt 2

—

—

—

Alt 3

—

—

—

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Comment

—

—

—

Freescale Semiconductor

Pin Assignments

Table 2. Package Pin Assignments (continued)

80-Pin 64-Pin 48-Pin Default Function

24

25

26

27

20

21

22

23

28

29

30

31

16

17

18

19

12

13

14

15

10

11

8

9

6

7

4

5

20

21

22

23

—

17

18

19

24

25

26

27

16

—

—

—

12

13

14

15

10

11

8

9

6

7

4

5

16

17

18

19

—

13

14

15

20

21

22

23

—

—

—

—

12

—

—

—

8

9

10

11

6

7

4

5

PTH3

VDD2

VSS2

PTB2

PTB3

PTB4

PTB5

PTB6

PTB7

PTC0

PTC1

PTC2

PTA1

PTA2

PTA3

PTA4

PTA5

PTA6

PTA7

PTB0

PTB1

PTF0/RGPIO8

PTF1/RGPIO9

PTF2/RGPIO10

PTF3/RGPIO11

PTH0

PTH1

PTH2

Alt 1

—

—

—

MII_TX_ER

MII_TX_CLK

MII_TX_EN

MII_TXD0

MII_TXD1

MII_TXD2

MII_TXD3

MII_COL

MII_CRS

MII_MDIO

MII_MDC

MII_RXD3

MII_RXD2

MII_RXD1

MII_RXD0

MII_RX_DV

MII_RX_CLK

MII_RX_ER

—

—

—

—

—

—

—

Alt 2

FB_D6

—

—

SS1

MOSI1

MISO1

SPSCK1

—

—

—

—

—

—

—

TXD3

RXD3

SPSCK2

MISO2

MOSI2

SS2

—

FB_A19/FB_AD19

FB_A18/FB_AD18

FB_A17/FB_AD17

FB_A16/FB_AD16

FB_A15/FB_AD15

FB_OE

FB_D7

Alt 3

TPM2CH0

—

—

—

—

—

—

TPM2CH0

TPM2CH1

TPM2CH2

SCL1

SDA1

TMRCLK1

—

—

—

—

—

—

TMRCLK1

—

—

—

—

SDA2

SCL2

—

—

Comment

—

—

—

—

—

—

—

—

—

RGPIO_ENB selects between standard GPIO and RGPIO

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

9

Pin Assignments

Table 2. Package Pin Assignments (continued)

80-Pin 64-Pin 48-Pin Default Function

32 28 24 RESET

53

54

55

56

49

50

51

52

57

58

59

45

46

47

48

41

42

43

44

37

38

39

40

33

34

35

36

45

46

47

48

41

42

43

44

—

—

—

37

38

39

40

33

34

35

36

—

—

—

—

29

30

31

32

—

—

—

—

33

34

35

36

—

—

—

29

30

31

32

25

26

27

28

—

—

—

—

—

—

—

—

—

—

—

—

KBI1P0

KBI1P1

KBI1P2

KBI1P3

KBI1P4

KBI1P5

KBI1P6

IRQ

—

SCL2

SDA2

—

—

—

—

—

—

—

—

—

—

—

—

PTF4/RGPIO12

PTF5/RGPIO13

PTF6/RGPIO14

PTF7/RGPIO15

PTH4

PTH5

PTH6

PTH7

VDD3

VSS3

VDDA

VSSA

PTC4

PTC5

PTC6

PTC7

PTD0/RGPIO0

PTD1/RGPIO1

PTD2/RGPIO2

PTD3/RGPIO3

PTG0

PTG1

PTG2

PTG3

PTG4

PTG5

PTG6

Alt 1

PTC3

Alt 2

—

Alt 3

—

Comment

This pin is a bi-directional open drain pin and has an internal pullup. There is no clamp diode to VDD.

DSE and SRE port controls for this bit have no effect.

RGPIO_ENB selects between standard GPIO and RGPIO

FB_D5

FB_D4

TMRCLK2

TPM2CH0

FB_A14/FB_AD14 TPM2CH1

FB_A13/FB_AD13 TPM2CH2

FB_A12/FB_AD12

FB_A11/FB_AD11

—

—

FB_A10/FB_AD10 TPM2CH1

FB_A9/FB_AD9 TPM2CH2

—

—

—

—

SS1

MOSI1

MISO1

SPSCK1

—

—

—

—

ADP11

ADP10

ADP9

ADP8

TXD1

RXD1

TXD2

RXD2

FB_A8/FB_AD8

FB_A7/FB_AD7

FB_A6/FB_AD6

FB_A5/FB_AD5

FB_RW

FB_D3

FB_D2

ADP7

ADP6

ADP5

ADP4

SCL2

SDA2

SCL1

SDA1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

RGPIO_ENB selects between standard GPIO and RGPIO

—

—

—

—

—

—

—

10

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 2. Package Pin Assignments (continued)

80-Pin 64-Pin 48-Pin Default Function Alt 1 Alt 2 Alt 3 Comment

60

61

62

63

64

65

66

71

72

73

74

67

68

69

70

—

49

50

51

52

53

54

59

60

61

62

55

56

57

58

—

37

38

39

40

41

42

47

48

—

—

43

44

45

46

PTG7

VDD4

VSS4

PTD4/RGPIO4

PTD5/RGPIO5

BKGD/MS

PTD7RGPIO7

PTE0

PTE1

PTE2

PTE3

PTE4

PTE5

PTE6

PTE7

KBI1P7

—

—

—

—

PTD6/RGPIO6

—

KBI2P0

KBI2P1

KBI2P2

KBI2P3

KBI2P4

KBI2P5

KBI2P6

KBI2P7

FB_D1

—

—

—

—

—

SPSCK2

MISO2

MOSI2

SS2

—

CLKOUT

IRQ

FB_D0

FB_CS0

—

—

—

EXTAL

XTAL

—

ADP3

ADP2

ADP1

ADP0

TPM1CH0

TPM1CH1

TPM1CH2

TXD3

RXD3

—

—

—

RGPIO_ENB selects between standard GPIO and RGPIO

This pin has an internal pullup. PTD6/RGPIO6 can only be programmed as an output.

1

RGPIO_ENB selects between standard GPIO and RGPIO

—

—

—

—

—

—

—

—

75

76

77

78

63

64

—

—

—

—

—

—

PTJ0

PTJ1

PTJ2

PTJ3

FB_ALE

—

—

—

FB_CS1

FB_A4/FB_AD4

FB_A3/FB_AD3

FB_A2/FB_AD2

—

—

—

—

—

—

—

—

79 — — PTJ4 — FB_A1/FB_AD1 — —

80 — — PTJ5 — FB_A0/FB_AD0 — —

1

RGPIO_ENB selects between standard GPIO and RGPIO. When PTD6 is set as RGPIO output, and "1" is driven to PTD6 via

RGPIO function, a read of register RGPIODATA6 always returns a "0" because V1 RGPIO design looks for IO enable when the return value of RGPIO function reads data. As PTD6 is set to RGPIO output only, it returns "0" always to RGPIODATA6, athough

PTD6 pin is driven to high.

3 Electrical Characteristics

3.1

Introduction

This section contains electrical and timing specifications for the MCF51CN128 series of microcontrollers available at the time of publication.

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 11

Electrical Characteristics

3.2

Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 3. Parameter Classifications

P

These parameters are guaranteed during production testing on each individual device.

C

These parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

T

These parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D

These parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where appropriate.

3.3

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the

limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V

SS

or V

DD

) or the programmable pull-up resistor associated with the pin is enabled.

Table 4. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage

Maximum current into V

DD

Digital input voltage

Instantaneous maximum current

Single pin limit (applies to all port pins)

1, 2, 3

V

DD

I

V

I

DD

In

D

–0.3 to +3.8

120

–0.3 to V

DD

+ 0.3

± 25

V mA

V mA

1

2

3

Storage temperature range T stg

–55 to 150

°C

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V

DD

) and negative (V

SS

) clamp voltages, then use the larger of the two resistance values.

All functional non-supply pins are internally clamped to V

SS

and V

DD

.

Power supply must maintain regulation within operating V

DD range during instantaneous and operating maximum current conditions. If positive injection current (V

In

> V

DD

) is greater than

I

DD

, the injection current may flow out of V

DD

and could result in external power supply going out of regulation. Ensure external V

DD

load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).

12

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

3.4

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P

I/O the difference between actual pin voltage and V

SS

or V

DD

into account in power calculations, determine

and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and V

SS

or V

DD

will be very small.

Table 5. Thermal Characteristics

Symbol Rating

Operating temperature range

(packaged)

Maximum junction temperature

Thermal resistance

Single-layer board

48-pin QFN

64-pin LQFP

80-pin LQFP

Thermal resistance

Four-layer board

48-pin QFN

64-pin LQFP

80-pin LQFP

1

Depending on device.

T

A

T

JM

θ

JA

θ

JA

Value

T

L

to T

H

(–40 to 85 or 0 to 70)

1

95

26

50

47

81

69

60

Unit

°C

°C

°C/W

°C/W

The average chip-junction temperature (T

J

) in °C can be obtained from:

T

J

= T

A

+ (P

D

× θ

JA

) Eqn. 1 where:

T

A

θ

JA

= Ambient temperature,

= Package thermal resistance, junction-to-ambient,

P

D

= P int

+ P

I/O

× V

DD

°C

, Watts — chip internal power

°C/W

P int

P

I/O

= I

DD

= Power dissipation on input and output pins — user determined

For most applications, P

I/O is:

<< P int

and can be neglected. An approximate relationship between P

D

and T

J

(if P

I/O

is neglected)

Solving Equation 1 and Equation 2

for K gives:

P

D

= K

÷ (T

J

+ 273

°C)

Eqn. 2

K = P

D

× (T

A

+ 273

°C) + θ

JA

× (P

D

)

2

Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P

D for a known T

A

. Using this value of K, the values of P

D for any value of T

A

.

and T

J

(at equilibrium)

can be obtained by solving

Equation 1

and

Equation 2

iteratively

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 13

Electrical Characteristics

3.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete

DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.

Table 6. ESD and Latch-up Test Conditions

Model

Human

Body

Machine

Latch-up

Description

Series resistance

Storage capacitance

Number of pulses per pin

Series resistance

Storage capacitance

Number of pulses per pin

Minimum input voltage limit

Maximum input voltage limit

Symbol

R1

C

—

—

—

R1

C

—

Value

1500

100

3

0

200

3

– 2.5

7.5

Unit

Ω pF

Ω pF

V

V

Table 7. ESD and Latch-Up Protection Characteristics

No.

Rating

1

Symbol Min Max Unit

1 Human body model (HBM) V

HBM

± 2000

— V

2

3

Machine model (MM)

Charge device model (CDM)

V

MM

V

CDM

± 200

± 500

—

—

V

V

4 Latch-up current at T

A

= 85

°C

I

LAT

± 100

— mA

1

Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.

14

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

3.6

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 8. DC Characteristics

Num C Characteristic

1 — Operating Voltage

2

2

C

P

T

Output high voltage

All I/O pins, low-drive strength

All I/O pins, high-drive strength

Symbol

V

—

OH

Condition

1.8 V, I

—

Load

= –2 mA V

Min

1.8

DD

3

– 0.5

2.7 V, I

Load

= –10 mA V

DD

– 0.5

2.3 V, I

Load

= –6 mA V

DD

– 0.5

1.8V, I

Load

= –3 mA V

DD

– 0.5

C

3 D

Output high current

4

C

Output low voltage

P

T

C

Max total I

OH

for all ports

All I/O pins, low-drive strength

All I/O pins, high-drive strength

I

OHT

V

OL

1.8 V, I

2.7 V, I

2.3 V, I

1.8 V, I

—

Load

Load

Load

Load

= 2 mA

= 10 mA

= 6 mA

= 3 mA

—

—

—

—

—

5

6

D

Output low current

P Input high voltage

C

Max total I

OL

for all ports all digital inputs

I

OLT

V

IH

V

V

DD

DD

—

> 2.7 V

> 1.8 V

V

DD

> 2.7 V

V

DD

>1.8 V

—

—

0.70 x V

DD

0.85 x V

DD

—

—

0.06 x V

DD

7

8 C Input hysteresis

9 P

Input leakage current

10 P

Hi-Z (off-state) leakage current

11 P

Pull resistors

12 D

DC injection current

4, 5, 6 all digital inputs V hys all input only pins

(Per pin)

|I

In| all input/output

(per pin) all digital inputs, when enabled

Single pin limit

|I

OZ|

R

P

Total MCU limit, includes sum of all stressed pins

I

IC

13

P Input low voltage

C

C Input Capacitance, all pins

14 C POR re-arm voltage

7 all digital inputs

15 D POR re-arm time

16 P

Low-voltage detection threshold — high range

8

V

V

IL

C

In

V

POR t

POR

LVDH

9

V

V

V

IN

In

In

= V

= V

< V

V

V

SS

DD

DD

DD

DD

—

, V

or V or V

IN

> V

falling

rising

SS

SS

DD

—

—

17.5

–0.2

–5

—

0.9

10

2.15

2.24

Typ

1

—

—

—

—

—

—

—

—

—

—

—

0.1

0.1

—

—

—

—

—

—

—

—

—

1.4

—

2.32

2.39

Max

3.6

—

—

—

—

100

0.5

0.5

0.5

0.5

100

Unit

V

—

—

0.35 x V

DD

0.30 x V

DD

—

V mV

1

μA

1

52.5

0.2

5

8

1.79

—

2.45

2.49

V mA

V mA

μA k

Ω mA mA pF

V

μs

V

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

15

Electrical Characteristics

Table 8. DC Characteristics (continued)

Num C Characteristic Symbol Condition Min Typ

1

Max Unit

17

18

P

P

Low-voltage detection threshold —

low range

8

Low-voltage warning threshold — high range

8

V

V

LVDL

LVWH

V

DD

falling

V

DD

rising

V

DD

falling

V

DD

rising

1.70

1.80

2.50

2.50

1.83

1.89

2.62

2.62

1.95

2.00

2.70

2.70

V

V

19 P

Low-voltage warning threshold —

low range

8

V

LVWL

V

DD

falling

V

DD

rising

2.25

2.29

2.32

2.39

2.45

2.49

V

20 P Bandgap Voltage Reference

10

V

BG

— 1.15

1.17

1.18

V

1

Typical values are measured at 25

°C. Characterized, not tested

2

As an exception, the Fast Ethernet Controller (FEC) is only operational above the operating voltage of 3 V.

3

4

5

As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above V

LVDL

.

All functional non-supply pins are internally clamped to V

SS

and V

DD

.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.

6

Power supply must maintain regulation within operating V

DD range during instantaneous and operating maximum current conditions. If positive injection current (V

In

> V

DD

) is greater than I

DD

, the injection current may flow out of V

DD

and could result in external power supply going out of regulation. Ensure external V

DD

load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).

7

Maximum is highest voltage that POR is guaranteed.

8

Low voltage detection and warning limits measured at 1 MHz bus frequency.

9

Run at 1 MHz bus frequency

10

Factory trimmed at V

DD

= 3.3 V, Temp = 25

°C

40

35

PULL-UP RESISTOR TYPICALS

85 °C

25 °C

–40 °C

40

PULL-DOWN RESISTOR TYPICALS

85 °C

25 °C

–40 °C

35

30

30

25

25

20

1.8

2 2.2

2.4

2.6

2.8

3 3.2

3.4

3.6

V

DD

(V)

20

1.8

2.3

V

DD

2.8

(V)

Figure 5. Pull-up and Pull-down Typical Resistor Values

3.3

3.6

16

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

1.2

1

0.8

0.6

0.4

0.2

0

0

0.8

0.6

1

0.4

0.2

0

0

TYPICAL V

OL

VS I

OL

AT V

DD

= 3.3 V

85 °C

25 °C

–40 °C

TYPICAL V

OL

VS V

DD

0.2

0.15

0.1

0.05

85

25

°C, I

°C, I

–40

OL

°C, I

OL

= 2 mA

= 2 mA

= 2 mA

0

5 10

I

OL

(mA)

15 20 1 2

V

DD

(V)

3

Figure 6. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

4

85 °C

25 °C

–40 °C

TYPICAL V

OL

VS I

OL

AT V

DD

= 3.3 V

0.4

85 °C

25 °C

–40 °C

TYPICAL V

OL

VS V

DD

0.3

0.2

I

OL

= 6 mA

0.1

I

OL

= 3 mA

10 20 30

0

1 2 3

I

OL

(mA)

V

DD

(V)

Figure 7. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)

I

OL

= 10 mA

4

1.2

1

0.8

0.6

0.4

0.2

0

0

TYPICAL V

DD

– V

OH

VS I

OH

AT V

DD

= 3.3 V

85 °C

25 °C

–40 °C

0.25

0.2

0.15

TYPICAL V

DD

– V

OH

VS V

DD

AT SPEC I

OH

85

25

°C, I

°C, I

–40

OH

°C, I

OH

= 2 mA

= 2 mA

= 2 mA

0.1

0.05

0

1 –5

I

–10

OH

(mA))

–15 –20 2

V

DD

(V)

3

Figure 8. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)

4

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

17

Electrical Characteristics

0.8

0.6

0.4

0.2

0

0

0.4

TYPICAL V

DD

– V

OH

VS V

DD

AT SPEC I

OH

85 °C

25 °C

–40 °C TYPICAL V

DD

– V

OH

VS I

OH

AT V

DD

= 3.3 V

85 °C

25 °C

–40 °C

0.3

0.2

0.1

I

OH

= –6 mA

I

OH

= –3 mA

–5 –10 –15

I

OH

(mA)

–20 –25 –30

0

1 2

V

DD

(V)

3

Figure 9. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

I

OH

= –10 mA

4

3.7

Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 9. Supply Current Characteristics

Num C Parameter Symbol

V

DD

(V)

Typ

1

1

2

3

T

T

T

T

P Run supply current

FEI mode, all modules on

T

C Run supply current

FEI mode, all modules off

T

T

Run supply current

LPRS=0, all modules off

T

RI

DD

RI

DD

RI

DD

Bus

Freq

25 MHz

20 MHz

8 MHz

1 MHz

25 MHz

20 MHz

8 MHz

1 MHz

16 kHz

FBILP

16 kHz

FBELP

3.3

3.3

3.3

44

36

15.5

3.9

60

49

21

4.6

203

154

4

5

6

T

Run supply current

LPRS=1, all modules off, running from

Flash

C Wait mode supply current

FEI mode, all modules off

T

T

P

C

T

C Stop2 mode supply current

C

RI

DD

WI

DD

S2I

DD

16 kHz

FBELP

25 MHz

20 MHz

8 MHz

1 MHz n/a

3.3

3.3

3.3

1.8

50

11

4.57

2

0.73

0.35

0.35

Max

47

—

—

—

75

—

—

—

—

—

—

13.7

—

—

—

11

45

12

16.2

Unit

Temp

(

°C) mA –40 to 85

°C mA –40 to 85

°C

μA

–40 to 85

°C

μA

–40 to 85

°C

μA

–-40 to 85

°C

μA

0 to 70

°C

–40 to 85

°C

0 to 70

°C

–40 to 85

°C

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

18 Freescale Semiconductor

Electrical Characteristics

Table 9. Supply Current Characteristics (continued)

Num C Parameter Symbol

Bus

Freq

V

DD

(V)

Typ

1

7

8

9

10

T

T

C

T

C Stop3 mode supply current

No clocks active

P

C

EREFSTEN=1

IREFSTEN=1

TPM PWM

S3I

DD n/a

32 kHz

32 kHz

100 Hz

3.3

1.8

0.52

0.52

500

70

12

11

12

T

T

Low power mode adders:

SCI, SPI, or IIC

RTC using LPO

—

300 bps

1 kHz

3.3

15

200

13 T

RTC using

ICSERCLK

32 kHz 1

14 T LVD n/a 100

1

Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value.

Max

14

55

15

32.4

—

—

—

—

—

—

—

Unit

Temp

(

°C)

μA

0 to 70

°C

–40 to 85

°C

0 to 70

°C

–40 to 85

°C nA –40 to 85

°C

μA

–40 to 85

°C

μA

–40 to 85

°C

μA

–40 to 85

°C nA –40 to 85

°C

μA

–40 to 85

°C

μA

–40 to 85

°C

Figure 10. Typical Run I

DD

for FBE and FEI, I

DD

vs. V

DD

(ADC off, All Other Modules Enabled)

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

19

Electrical Characteristics

3.8

External Oscillator (XOSC) Characteristics

Reference

Figure 11 and Figure 12 for crystal or resonator circuits.

Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85

°C Ambient)

Num C Characteristic Symbol Min Typ

1

Max Unit

1

C

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0)

High range (RANGE = 1), high gain (HGO = 1)

High range (RANGE = 1), low power (HGO = 0) f lo f hi f hi

32

1

1

—

—

—

38.4

25

8 kHz

MHz

MHz

2 D

Load capacitors

Low range (RANGE=0), low power (HGO=0)

Other oscillator settings

C

1,

C

2

See Note

See Note

2

3

3

D

Feedback resistor

Low range, low power (RANGE=0, HGO=0)

2

Low range, High Gain (RANGE=0, HGO=1)

High range (RANGE=1, HGO=X)

R

F

—

—

—

—

10

1

—

—

—

M

Ω

4

5

D

C

Series resistor —

Low range, low power (RANGE = 0, HGO = 0)

2

Low range, high gain (RANGE = 0, HGO = 1)

High range, low power (RANGE = 1, HGO = 0)

High range, high gain (RANGE = 1, HGO = 1)

≥ 8 MHz

4 MHz

1 MHz

Crystal start-up time

4

Low range, low power

Low range, high power

High range, low power

High range, high power

R

S t

CSTL t

CSTH

—

—

—

—

—

—

—

—

—

—

—

0

100

0

0

0

200

400

5

15

—

—

—

0

10

20

—

—

—

—

Ω

ΚΩ ms

6 D

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

External with FLL / PLL enabled (FEE / PEE)

External with bypass (FBE.FBELP,PBE, PBELP) f extal

0.03125

0

—

—

50.33

50.33

MHz

MHz

2

3

1

4

Data in Typical column was characterized at 3.3 V, 25

°C or is typical recommended value.

Load capacitors (C

1

,C

2

), feedback resistor (R

F

) and series resistor (R

S

) are incorporated internally when RANGE=HGO=0.

See crystal or resonator manufacturer’s recommendation.

Proper PC board layout procedures must be followed to achieve specifications.

20

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

EXTAL

XOSC

R

F

XTAL

R

S

Crystal or Resonator

C

1

C

2

Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain

XOSC

EXTAL XTAL

Crystal or Resonator

Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Gain

3.9

Multipurpose Clock Generator (MCG) Specifications

Table 11. MCG Frequency Specifications (Temperature Range = –40 to 125

°C Ambient)

Symbol Min Typical Max Num C Rating

1 P

Internal reference frequency - factory trimmed at V

DD

= and temperature = 25

°C

2 P

Average internal reference frequency - untrimmed

1

3 P

Average internal reference frequency - user trimmed

4 D Internal reference startup time

5 —

DCO output frequency range -

untrimmed

1

value provided for reference: f dco_ut

= 1024 X f int_ut

6 P DCO output frequency range - trimmed

7 C

Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) f int_ft f int_ut f int_t t irefst f dco_ut f dco_t

Δf dco_res_t

—

25

31.25

—

25.6

32

—

32.768

—

—

60

33.48

—

± 0.1

—

41.66

39.06

100

42.66

40

± 0.2

Unit kHz kHz kHz us

MHz

MHz

%f dco

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

21

Electrical Characteristics

Table 11. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125

°C Ambient)

Num C Rating

8 C

Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)

9 P

Total deviation of trimmed DCO output frequency over voltage and temperature

10 C

Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 - 70

°C

11 C FLL acquisition time 2

12 D PLL acquisition time 3

13 C

Long term Jitter of DCO output clock

(averaged over 2ms interval)

4

14 D VCO operating frequency

15 D Lock entry frequency tolerance 5

16 D Lock exit frequency tolerance 6

17 D Lock time - FLL

18 D Lock time - PLL

Symbol

Δf dco_res_t

Δf dco_t

Δf dco_t t fll_acquire t pll_acquire

C

Jitter f vco

D lock

D unl t fll_lock t pll_lock

Min

—

—

—

—

—

—

7.0

± 1.49

± 4.47

—

—

Typical

± 0.2

+ 0.5

-1.0

± 0.5

—

—

0.02

—

—

—

—

—

Max

± 0.4

± 2

± 1

1

1

0.2

55.0

± 2.98

± 5.97

t fll_acquire+

1075(1/ f int_t

) t pll_acquire+

1075(1/ f pll_r ef)

Unit

%f dco

%f dco

%f dco ms ms

%f dco

MHz

%

% s s

19 D

Loss of external clock minimum frequency - RANGE = 0 f loc_low

(3/5) x f int

— — kHz

1

2

3

4

5

TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

BUS

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V

DD

and V given interval.

SS

and variation in crystal oscillator frequency increase the C

Jitter

percentage for a

Below D lock

minimum, the MCG is guaranteed to enter lock. Above D lock

maximum, the MCG does not enter lock. But if the

MCG is already in lock, then the MCG may stay in lock.

6

Below D unl

minimum, the MCG does not exit lock if already in lock. Above D unl

maximum, the MCG is guaranteed to exit lock.

22

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

3.10

Mini-FlexBus Timing Specifications

A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of

25.1666 MHz

. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used.

All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.

Table 12. Mini-FlexBus AC Timing Specifications

Num C Characteristic Min Max Unit

—

MB1

MB2

— Frequency of Operation

D Clock Period

P Output Valid

—

39.73

—

25.1666

—

20

MHz ns ns

MB3

MB4

D

P

Output Hold

Input Setup

1.0

22

—

— ns ns

MB5 D Input Hold 10 — ns

1

2

Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.

Specification is valid for all MB_D[7:0].

Notes

—

—

1

1

2

2

S0 S0 S1 S2 S3

FB_CLK

8-bit Non-Mux’d Bus

FB_A[19:16]

FB_D[7:0]

16-bit Mux’d Bus

FB_AD[19:16]

FB_AD[15:0]

MB1

ADDR[19:0]

MB2

ADDR[31:24] DATA[7:0]

ADDR[15:0]

ADDR[19:16]

DATA[15:0]

MB4

MB5

MB3

FB_R/W

FB_ALE

FB_CSn, FB_OE

Figure 13. Mini-FlexBus Read Timing

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

23

Electrical Characteristics

S0 S1 S2

FB_CLK

FB_AD[19:8]

8-bit Non-Mux’d Bus

16-bit Mux’d Bus

FB_AD[7:0]

FB_AD[19:16]

FB_AD[15:0]

FB_R/W

FB_ALE

FB_CSn

MB1

ADDR[19:8]

MB2

ADDR[7:0] DATA[7:0]

ADDR[19:16]

ADDR[15:0] DATA[15:0]

FB_OE

Figure 14. Mini-FlexBus Write Timing

S3

MB3

S0

3.11

Fast Ethernet Timing Specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.

3.11.1

Receive Signal Timing Specifications

The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.

Table 13. Receive Signal Timing

MII Mode

Num C Characteristic Unit

—

E1

E2

E3

E4

— RXCLK frequency

P RXD[3:0], RXDV, RXER to RXCLK setup

D RXCLK to RXD[3:0], RXDV, RXER hold

D RXCLK pulse width high

D RXCLK pulse width low

Min

—

5

5

35%

35%

Max

25

—

—

65%

65%

MHz ns ns

RXCLK period

RXCLK period

24

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

E4

E3 RXCLK (Input)

E1 E2

RXD[n:0]

RXDV,

RXER

Valid Data

Figure 15. MII Receive Signal Timing Diagram

3.11.2

Transmit Signal Timing Specifications

Table 14. Transmit Signal Timing

Num

—

E5

E6

E7

E8

C Characteristic

— TXCLK frequency

D

P

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

D

D

TXCLK pulse width high

TXCLK pulse width low

MII Mode

Min

—

5

—

35%

35%

Max

25

—

25

65%

65%

Electrical Characteristics

Unit

MHz ns ns t

TXCLK t

TXCLK

TXCLK (Input)

E8

E7

E6 E5

TXD[n:0]

TXEN,

TXER

Valid Data

Figure 16. MII Transmit Signal Timing Diagram

3.11.3

Asynchronous Input Signal Timing Specifications

Table 15. MII Transmit Signal Timing

Num

E9

C Characteristic

D CRS, COL minimum pulse width

Min

1.5

Max

—

Unit

TXCLK period

Freescale Semiconductor

CRS, COL

E9

Figure 17. MII Async Inputs Timing Diagram

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

25

Electrical Characteristics

3.11.4

MII Serial Management Timing Specifications

Table 16. MII Serial Management Channel Signal Timing

Num

E10

E11

E12

E13

E14

E15

C

D

D

D

D

D

D

Characteristic

MDC cycle time

MDC pulse width

MDC to MDIO output valid

MDC to MDIO output invalid

MDIO input to MDC setup

MDIO input to MDC hold

Symbol t

MDC

—

—

—

—

—

Min

400

40

—

30

5

15

Max

—

60

375

—

—

—

E10

E11

MDC (Output)

E11

E12

Valid Data

E13

MDIO (Output)

Unit ns

% t

MDC ns ns ns ns

E14 E15

MDIO (Input)

Valid Data

Figure 18. MII Serial Management Channel TIming Diagram

3.12

AC Characteristics

This section describes timing characteristics for each peripheral system.

3.12.1

Control Timing

Table 17. Control Timing

Symbol Num C

1

2

3

4

5

Rating

D

Bus frequency (t cyc

= 1/f

Bus

)

V

DD

> 2.7 V

2.7 V > V

DD

> 2.1 V

2.1 V > V

DD

> 1.8 V

D Internal low power oscillator period

D External reset pulse width

2

D Reset low drive

D

BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes f

Bus t

LPO t extrst t rstdrv t

MSSU

Min dc dc dc

700

100

34 x t cyc

500

Typ

1

—

—

—

—

—

—

—

Max Unit

50.33

40

20

1300

—

—

—

MHz

μs ns ns ns

26

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 17. Control Timing (continued)

Num C Rating Symbol Min Typ

1

Max Unit

6 D

BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes

3 t

MSH

100 — —

μs

7 D

IRQ pulse width

Asynchronous path

Synchronous path

4

2

t

ILIH, t

IHIL

100

2 x t cyc

—

—

—

— ns

8 D

Keyboard interrupt pulse width

Asynchronous path

Synchronous path

4

2

t

ILIH, t

IHIL

100

2 x t cyc

—

—

—

— ns

Port rise and fall time —

Low output drive (PTxDS = 0) (load = 50 pF)

5

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1) t

Rise

, t

Fall

—

—

16

23

—

— ns

9 C

Port rise and fall time —

High output drive (PTxDS = 1) (load = 50 pF)

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1) t

Rise

, t

Fall

—

—

5

9

—

— ns

1

2

3

4

5

10 C Stop3 recovery time, from interrupt event to vector fetch t

STPREC

— 6 10

Typical values are based on characterization data at V

DD

= 3.3 V, 25

°C unless otherwise stated.

This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not guaranteed to override reset requests from internal sources.

μs

To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t

MSH after V

DD rises above V

LVD

.

This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt request until it is explicitly negated by the interrupt service routine.

Timing is shown with respect to 20% V

DD

and 80% V

DD

levels. Temperature range –40

°C to 85 °C. t extrst

RESET PIN

Figure 19. Reset Timing t

IHIL

KBIPx

IRQ/KBIPx t

ILIH

Figure 20. IRQ/KBIPx Timing

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

27

Electrical Characteristics

3.12.2

TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 18. TPM Input Timing

No.

1

2

3

4

5

C Function

D External clock frequency

D External clock period

D External clock high time

D External clock low time

D Input capture pulse width

Symbol f

TCLK t

TCLK t clkh t clkl t

ICPW

Min

0

4

1.5

1.5

1.5

Max f

Bus

/4

—

—

—

—

Unit

Hz t cyc t cyc t cyc t cyc t

TCLK t clkh

TCLK

TPMCHn t clkl

Figure 21. Timer External Clock t

ICPW

TPMCHn t

ICPW

Figure 22. Timer Input Capture Pulse

28

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

3.12.3

SPI Timing

Table 19 and

Figure 23 through

Figure 26 describe the timing requirements for the SPI system.

Table 19. SPI Timing

No.

Min

—

1

2

3

4

5

6

7

8

9

10

11

12

C Function

D

Operating frequency

Master

Slave

D

SPSCK period

Master

Slave

D

Enable lead time

Master

Slave

D

Enable lag time

Master

Slave

D

Clock (SPSCK) high or low time

Master

Slave

D

Data setup time (inputs)

Master

Slave

D

Data hold time (inputs)

Master

Slave

D Slave access time

D Slave MISO disable time

D

Data valid (after SPSCK edge)

Master

Slave

D

Data hold time (outputs)

Master

Slave

D

Rise time

Input

Output

D

Fall time

Input

Output

Symbol f op t

SPSCK t

Lead t

Lag t

WSPSCK t

SU t

HI t a t dis t v t

HO t

RI t

RO t

FI t

FO f

Bus

/2048

0

2

4

1

/2

1

1

/2

1 t cyc

–

30 t cyc

– 30

15

15

0

25

—

—

—

—

0

0

—

—

—

—

Max f

Bus

/2 f

Bus

/4

2048

—

—

—

—

—

1024 t cyc

—

—

—

—

—

1

1

25

25

—

— t cyc

– 25

25 t cyc

– 25

25

Unit

Hz

Hz t cyc t cyc t

SPSCK t cyc t

SPSCK t cyc ns ns ns ns ns ns t cyc t cyc ns ns ns ns ns ns ns ns

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

29

Electrical Characteristics

SS

1

(OUTPUT)

2

SPSCK

(CPOL = 0)

(OUTPUT)

SPSCK

(CPOL = 1)

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

4

5 6

MSB IN

2

9

MSB OUT

2

1

4

BIT 6 . . . 1

9

BIT 6 . . . 1

LSB IN

11

12

LSB OUT

10

NOTES:

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 23. SPI Master Timing (CPHA = 0)

SS

(1)

(OUTPUT)

1

2

SPSCK

(CPOL = 0)

(OUTPUT)

4 4

SPSCK

(CPOL = 1)

(OUTPUT)

MISO

(INPUT)

9

MOSI

(OUTPUT)

PORT DATA

5

MSB IN

6

(2)

MASTER MSB OUT

(2)

12

11

BIT 6 . . . 1

10

BIT 6 . . . 1

11

12

LSB IN

MASTER LSB OUT

3

3

PORT DATA

NOTES:

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 24. SPI Master Timing (CPHA =1)

30

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

SS

(INPUT)

1 12 11 3

SPSCK

(CPOL = 0)

(INPUT)

SPSCK

(CPOL = 1)

(INPUT)

2 4 4

11 12

MISO

(OUTPUT)

7

SLAVE MSB OUT

5 6

MSB IN

9

BIT 6 . . . 1

10 10

SLAVE LSB OUT

MOSI

(INPUT)

BIT 6 . . . 1 LSB IN

NOTE:

1. Not defined but normally MSB of character just received

Figure 25. SPI Slave Timing (CPHA = 0)

SEE

NOTE

8

SS

(INPUT)

2

1

12 11

3

SPSCK

(CPOL = 0)

(INPUT)

SPSCK

(CPOL = 1)

(INPUT)

4 4

11 12

MISO

(OUTPUT)

SEE

NOTE

9

SLAVE MSB OUT

7 5 6

MSB IN

10

BIT 6 . . . 1 SLAVE LSB OUT

MOSI

(INPUT) BIT 6 . . . 1 LSB IN

NOTE:

1. Not defined but normally LSB of character just received

Figure 26. SPI Slave Timing (CPHA = 1)

8

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

31

Electrical Characteristics

3.12.4

ADC Characteristics

Table 20. 12-bit ADC Operating Conditions

C Characteristic Conditions Symb Min Typ

1

Max Unit Comment

Supply voltage Absolute

D

Delta to V

DD

(V

DD

-V

DDAD

)

2

D Ground voltage Delta to V

SS

(V

SS

-V

SSAD

)

2

D Ref Voltage High

D

D

Ref Voltage Low

Input Voltage

V

DDAD

ΔV

DDAD

ΔV

SSAD

V

V

V

REFH

REFL

ADIN

1.8

-100

-100

1.8

V

SSAD

V

REFL

—

—

0

0

V

DDAD

V

SSAD

—

V

+100

+100

V

V

3.6

DDAD

SSAD

REFH

V mV mV

V

V

V

C

Input

Capacitance

C

ADIN

4.5

5.5

pF

C Input Resistance

Analog Source

Resistance

12 bit mode f

ADCK

> 4MHz f

ADCK

< 4MHz

R

ADIN

R

AS

—

—

—

5

—

—

7

2

5 k

Ω

External to MCU

C

D

10 bit mode f

ADCK

> 4MHz f

ADCK

< 4MHz

8 bit mode (all valid f

ADCK

)

ADC Conversion

Clock Freq.

High Speed (ADLPC=0)

Low Power (ADLPC=1) f

ADCK

—

—

—

0.4

—

—

—

—

5

10

10

8.0

k

Ω

MHz

0.4

— 4.0

1

2

Typical values assume V

DDAD

= 3.3 V, Temp = 25

°C, f only and are not tested in production.

ADCK

=1.0 MHz unless otherwise stated. Typical values are for reference

DC potential difference.

32

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

R

AS

Z

AS

Electrical Characteristics

+

V

ADIN

–

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Pad leakage due to input protection

Z

ADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

R

ADIN

ADC SAR

ENGINE

V

AS

C

AS

R

ADIN

INPUT PIN

R

ADIN

INPUT PIN

R

ADIN

INPUT PIN C

ADIN

Figure 27. ADC Input Impedance Equivalency Diagram

Table 21. 12-bit ADC Characteristics (V

REFH

= V

DDAD

, V

REFL

= V

SSAD

)

Conditions C Symb Min Typ

1

Max Unit Characteristic

Supply Current

ADLPC=1

ADLSMP=1

ADCO=1

Supply Current

ADLPC=1

ADLSMP=0

ADCO=1

Supply Current

ADLPC=0

ADLSMP=1

ADCO=1

Supply Current

ADLPC=0

ADLSMP=0

ADCO=1

Supply Current Stop, Reset, Module Off

ADC

Asynchronous

Clock Source

High Speed (ADLPC=0)

Low Power (ADLPC=1)

T I

DDAD

T I

DDAD

T I

DDAD

T I

DDAD

D I

DDAD

P f

ADACK

C

—

—

—

—

—

2

1.25

120

202

288

0.532

0.007

3.3

2

—

—

—

1

0.8

5

3.3

μA

μA

μA mA

μA

MHz

Comment t

ADACK

= 1/f

ADACK

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

33

Electrical Characteristics

Table 21. 12-bit ADC Characteristics (V

REFH

= V

DDAD

, V

REFL

= V

SSAD

) (continued)

Characteristic Conditions C Symb Min Typ

1

Max Unit Comment

Conversion Time

(Including sample time)

Sample Time

Total Unadjusted

Error

Differential

Non-Linearity

Integral

Non-Linearity

Zero-Scale Error 12 bit mode

Full-Scale Error

Short Sample (ADLSMP=0)

Long Sample (ADLSMP=1)

Short Sample (ADLSMP=0)

Long Sample (ADLSMP=1)

12 bit mode

10 bit mode

8 bit mode

12 bit mode

10 bit mode

8 bit mode

12 bit mode

10 bit mode

8 bit mode

10 bit mode

8 bit mode

12 bit mode

10 bit mode

8 bit mode

3

3

P

C

P

C

T

P

T

T

P

T

T

P

T

T

P

T

T

P

T t t

E

ADC

ADS

TUE

DNL

INL

E

E

ZS

FS

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

20

40

3.5

±1.5

±0.5

±0.5

±1.0

±0.3

±1.5

±0.5

±0.3

±0.5

±0.5

23.5

±3.0

±1

±0.5

±1.75

±0.5

—

—

—

—

—

±2.5

±1.0

—

±1.0

±0.5

—

±1.0

±0.5

—

±1.5

±0.5

—

±1

±0.5

ADCK cycles

ADCK cycles

LSB

LSB

LSB

LSB

LSB

2

2

2

2

2

See the ADC chapter in the

MCF51CN128

Reference Manual for conversion time

V

V variances

Includes

Quantization

ADIN

ADIN

= V

= V

SSAD

DDAD

Quantization

Error

12 bit mode

10 bit mode

D E

Q

—

—

-1 to 0

—

—

±0.5

±0.5

LSB

2

Input Leakage

Error

8 bit mode

12 bit mode

10 bit mode

D E

IL

—

—

—

—

±2

±0.2

±0.1

—

±4

±1.2

LSB

2

Pad leakage

4

*

R

AS{test=pad leakage test}

Temp Sensor

Slope

8 bit mode

-40

°C to 25°C

25

°C to 85°C

25

°C

D m

—

—

—

1.646

1.769

—

— mV/ °C

Temp Sensor

Voltage

D V

TEMP25

— 701.2

— mV

2

3

1

4

Typical values assume V

DDAD

= 3.3 V, Temp = 25

°C, f only and are not tested in production.

ADCK

=1.0 MHz unless otherwise stated. Typical values are for reference

1 LSB = (V

REFH

- V

REFL

)/2

N

Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes

Based on input pad leakage current. Refer to pad electricals.

34

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

3.12.5

Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.

Program and erase operations do not require any special power sources other than the normal V

DD

supply. For more detailed information about program/erase operations, see the Memory section of the MCF51CN128 Reference Manual.

Table 22. Flash Characteristics

C Characteristic Symbol Min Typical Max Unit

D

Supply voltage for program/erase

-40

°C to 85 °C

V prog/erase

1.8

— 3.6

V

D Supply voltage for read operation V

Read

1.8

— 3.6

V

D Internal FCLK frequency

1 f

FCLK

150 — 200 kHz

D Internal FCLK period (1/FCLK) t

Fcyc

5 — 6.67

μs

P Longword program time (random location)

(2) t prog

9 t

Fcyc

P Longword program time (burst mode)

(2) t

Burst

4 t

Fcyc

P Page erase time

2 t

Page

4000 t

Fcyc

P Mass erase time

(2) t

Mass

20,000 t

Fcyc

D Longword program current

3

R

IDDBP

— 9.7

— mA

D Page erase current

3

R

IDDPE

—

7.6

— mA

C

Program/erase endurance

4

T

L

to T

H

T = 25

°C

= –40

°C to + 85°C

C Data retention

5

10,000

—

—

100,000

—

— cycles t

D_ret

15 100 — years

1

2

3

4

5

The frequency of this clock is controlled by a software setting.

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase.

The program and erase currents are additional to the standard run I

DD

. These values are measured at room temperatures with V

DD

= 3.3 V, bus frequency = 8.0 MHz.

Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile

Memory.

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25

°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

3.13

EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

35

Ordering Information

3.13.1

Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.

4 Ordering Information

This section contains ordering information for MCF51CN128 devices.

Table 23. Ordering Information

Freescale Part Number

1

Memory

Temperature Range

(

°C)

Package

2

Flash RAM

MCF51CN128CLK

MCF51CN128CLH

128K

128K

24K

24K

–40 to +85

–40 to +85

80-pin LQFP

64-pin LQFP

MCF51CN128CGT 128K 24K –40 to +85 48-pin QFN

1

2

See the MCF51CN128 Reference Manual (document MCF51CN128RM), for a complete description of modules included on each device.

See Table 24

for package information.

5 Package Information

Table 24. Package Descriptions

Pin Count

80

64

48

Package Type

Low Quad Flat Package

Low Quad Flat Package

Quad Flat No-Leads

Abbreviation

LQFP

LQFP

QFN

Designator

LK

LH

GT

Case No.

917A

840F

1314

Document No.

98ASS23237W

98ASS23234W

98ARH99048A

6 Mechanical Outline Drawings

The following pages are mechanical drawings for the packages described in Table 24

. For the latest available drawings, visit freescale web site ( http://www.freescale.com

) and enter the package’s document number into the keyword search box.

36

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

6.1

80-pin LQFP

Mechanical Outline Drawings

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

37

Mechanical Outline Drawings

38

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Mechanical Outline Drawings

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

39

Mechanical Outline Drawings

6.2

64-pin LQFP

40

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Mechanical Outline Drawings

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

41

Mechanical Outline Drawings

42

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

6.3

48-pin QFN

Mechanical Outline Drawings

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

43

Mechanical Outline Drawings

44

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Mechanical Outline Drawings

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

45

Mechanical Outline Drawings

46

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Revision History

7 Revision History

This section lists the changes between versions of MCF51CN128 Data Sheet document.

Table 25. Revision History

Revision Number

1

2

3

4

Date

August 2008

January 2009

January 2009

May 2009

Description of Changes

Alpha Customer Release.

Pre-Launch Release.

Launch Release.

• Changed LVDH trip and recovery values in Table 8

.

• Fixed Mini-FlexBus maximum frequency to 25.1666 MHz in

Section 3.10, “Mini-FlexBus Timing Specifications

.”

• Updated FEC feature list to describe ethernet operation between 3.0 V to 3.6 V.

• In

Table 8 , added a footnote to the operating voltage. It

describes an exception to the Fast Ethernet Controller (FEC), because it is only operational above the operating voltage of

3 V.

• Corrected Freescale part numbers in Table 23

.

• In

Table 21

, changed I

DDAD

classification to T.

Freescale Semiconductor

MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4

47

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Document Number: MCF51CN128

Rev. 4

5/2009

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