Hewlett-Packard SCSI Bus Preprocessor Interface User Manual

| 0 HEWLETT®
PACKARD
HP E2423A
SCSI Bus Preprocessor Interface
HP E2423A
SCSI Bus Preprocessor Interface
User's Guide
for the HP 1650A, HP 16508, HP 1652B, HP 1660A/61A/62A/63A,
HP 16510A, HP 165108, HP 16511B, HP 16540/16541A,D, HP 16542A, and
HP 16550A Logic Analyzers
Qu HEWLETT
PACKARD
Copyright Hewlett Packard Company 1992
Aanual Part Number E2423-90904
Microfiche Part Number E2423-90804 Printed in U.S.A November 1992
New editions are complete revisions of the manual. Update packages,
which are issued between editions, contain additional and replacement
pages to be merged into the manual by the customer. The dates on the
title page change only when a new edition is published.
A software code may be printed before the date; this indicates the version
of the software product at the time the manual or update was issued.
Many product updates and fixes do not require manual changes and,
conversely, manual corrections may be done without accompanying
product changes. Therefore, do not expect a one to one correspondence
between product updates and manual updates.
Edition 1 November 1992 E2423-90904
List of Effective Pages
The List of Effective Pages gives the date of the current edition and of any
pages changed in updates to that edition. Within the manual, any page
changed since the last edition is indicated by printing the date the changes
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Pages Effective Date
Herstellerbescheinigung
Hiermit wird bescheinigt, daB das Gerát/System
HP 1650A/B and HP 1651A/B
in Übereinstimmung mit den Bestimmungen von Postverfigung
1046/84 funkentstört ist.
Der Deutschen Bundespost wurde das Inverkehrbringen dieses
Gerätes/Systems angezeigt und die Berechtigung zur Überprüfung der
Serie auf Einhaltung der Bestimmungen eingeräumt.
Zusatzinformation für Meß- und Testgeräte
Werden Meß- und Testgeräte mit ungeschirmten Kabeln und/oder in
offenen Meßaufbauten verwendet, so ist vom Betreiber sicherzustellen,
daß die Funk-Entstörbestimmungen unter Betriebsbedingungen an
seiner Grundstücksgrenze eingehalten werden.
Manufacturer’s declaration
This is to certify that this product HP 1650A/B and HP 1651A/B meets
the radio frequency interference requirements of directive Vfg,
1046/84. The German Bundespost has been notified that this
equipment was put into circulation and was granted the right to check
the product type for compliance with these requirements.
Additional Information for Test- and Measurement Equipment
Note: If test and measurement equipment 15 operated with unshielded
cables and/or used for measurements on open set-ups, the user must
insure that under these operating conditions, the radio frequency
interference limits are met at the border of his premises.
Note: This declaration indicates compliance of this product with the German RFI
specifications stated in the German Vfg. 1046/84 directive.
Product Warranty
ро
This Hewlett-Packard product has a warranty against defects in material
and workmanship for a period of 1 year from date of shipment. During
warranty period, Hewlett-Packard Company will, at its option, either
repair or replace products that prove to be defective.
For warranty service or repair, this product must be returned to a service
facility designated by Hewlett-Packard. However, warranty service for
products installed by Hewlett-Packard and certain other products
designated by Hewlett-Packard will be performed at Buyer's facility at no
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Hewlett-Packard service travel areas, warranty service will be performed
at Buyer's facility only upon Hewlett-Packard's prior agreement and
Buyer shall pay Hewlett-Packard's round trip travel expenses.
For products returned to Hewlett-Packard for warranty service, the Buyer
shall prepay shipping charges to Hewlett-Packard and Hewlett-Packard
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returned to Hewlett-Packard from another country.
Hewlett-Packard warrants that its software and firmware designated by
Hewlett-Packard for use with an instrument will execute its programming
instructions when properly installed on that instrument. Hewlett-Packard
does not warrant that the operation of the instrument, software, or
firmware will be uninterrupted or error-free.
Limitation of
Warranty
Exclusive
Remedies
Assistance
Certification
Safety
The foregoing warranty shall not apply to defects resulting from improper
or inadequate maintenance by the Buyer, Buyer-suppiied software or
interfacing, unauthorized modification or misuse, operation outside of the
environmental specifications for the product, or improper site preparation
or maintenance.
NO OTHER WARRANTY IS EXPRESSED OR IMPLIED.
HEWLETT-PACKARD SPECIFICALLY DISCLAIMS THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE.
THE REMEDIES PROVIDED HEREIN ARE BUYER'S SOLE AND
EXCLUSIVE REMEDIES. HEWLETT-PACKARD SHALL NOT BE
LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
OR CONSEQUENTIAL DAMAGES, WHETHER BASED ON
CONTRACT, TORT, OR ANY OTHER LEGAL THEORY.
Product maintenance agreements and other customer assistance
agreements are available for Hewlett-Packard products.
For assistance, contact your nearest Hewlett-Packard Sales and Service
Office.
Hewlett-Packard Company certifies that this product met its published
specifications at the time of shipment from the factory. Hewlett-Packard
further certifies that its calibration measurements are traceable to the
United States National Bureau of Standards, to the extent allowed by the
Bureau's calibration facility, and to the calibration facilities of other
International Standards Organization members.
This product has been designed and tested according to International
Safety Requirements. To ensure safe operation and to keep the product
safe, the information, cautions, and warnings in this user's guide must be
heeded.
Table of Contents
A
Introduction
Logic Analyzers Supported
How to Use This Manual
oO
Chapter 1: Setting Up the HP E2423A
Introduction ................eeoeccecoreooo EEE EEE EEE 1-1
Duplicating the Master Disk .....0.00.000000000000 0000000000000 1-1
HP 16500A Software Compatibility ................00.000000 1-1
Equipment Supplied .....................e... eee. 1-1
Equipment Required ........... citi, 1-2
Installation Quick Reference ............... cc. iLL. 1-2
Setting Up the HP E2423A Front Panel ......................... 1-3
Connecting the HP E2423A tothe SCSIBus..................... 1-4
Connectingtothe HPE2423A .. . LL... iin... 1-6
Power Ор / Down Sequence .............eeeeocecorccreaaceno. 1-6
Setting Up the Analyzer fromthe Disk ......................... 1-10
Loading an Inverse Assembler................................ 1-11
Selecting the Correct Inverse Assembler ....................... 1-12
J
Chapter 2: Analyzing the SCSI Bus
Introduction .........oee.—eee.eeococr0srorcococarcorecerracene. 2-1
Format Specification ...........e...eeeccsrocarioarecococanoo. 2-1
Symbols and Labels ................eeeeereeorcosccscrrorecacan 2-2
Accumulating Data ..........e.eeeeeesvscorcorenereceramonrao 2-6
Listing Menu ............eooococccrercococaoreacocrareccnane, 2-6
The SCSI Bus Inverse Assemblers ............................. 2-7
Interpreting Commands ...............e—eeeeereoecosocorcocoo 2-8
Interpreting Vendor Unique and Reserved Information ........ 2-8
Interpreting Messages .............ñceeeesxesoccccecsrrrono. 2-9
Interpreting Status ..................reeeeororocororeconoo 2-10
Interpreting Data .............eeeeerervoroorooroorececemoeo 2-11
Arbitration, Select, and Reselect Phases ..................... 2-11
Attention, Resetand Bus Free ............................. 2-11
| L\ 4 (42 = à de) dE 2-11
The Trace Menu ....... iii iia, 2-12
LED Indicators ..............ee..0eee0c0scicoroceriroecocan. 2-13
Contents-1
I
Chapter 3: Additional Information
Introduction overseen csannascnonosaneonnornnseseses 3-1
CharacteristicS ..........0.00000u000 000000 EEE EEE 3-1
Clocking ................. 3-3
Interface Description ............00000000 eee ee eee eee e eee 3-6
SCSI Bus Signal to HP E2423A Connector Mapping ............-. 3-7
Servicing .........eorcererrocccaerererecarerererrr tere 3-11
E ES
Appendix A: SCSI Overview
Introduction ..........00000000 000000 00ER EEE A-1
SCSI Status Lines ...........0200000 000000 eee nee meet eee A-2
Appendix B: Troubleshooting
: "Slow or Missing Clock” ..........0..0.000000 000 00H B-1
No Activity on Activity Indicators ............- B-1
Slow Clock 000000000000 ae eee na sea a ea ae eee 10005 B-2
"No Configuration File Loaded" .............e.eeerer-55- B-2
"Selected File is Incompatible" ..........e.....ereríverrero- B-2
" Inverse Assembler Not Found" ...........ee..eeeeerooo- B-3
No Inverse Assembly ..........0000000 000000 00e eee ete ee B-3
Incorrect Inverse Assembly ...........000000000 00H B-3
"State Clock Violates Overdrive Specification” ............... B-3
Unwanted TriggerS ............0.0.0.000000000 HEHE B-3
"Waiting for Trigger" .......0....000000000 HH HT B-4
Intermittent Data Érrors ...........0.0000000 00000 B-4
Bent Pins ........00200000000000 0000000000 eee eee tete 1005 B-4
"Time from Arm Greater Than 41.93 ms... B-4
No Setup/Hold Field on Format Screen ............00004 7400 B-4
"Default Calibration Factors Loaded” (16540/41/42) ........... B-4
Contents-2
Introduction
A
The HP E2423A Small Computer Systems Interface (SCSI) Bus
Preprocessor Interface provides a complete mechanical and electrical
connection between an 8-bit or 16-bit Single-Ended or Differential
SCSI Bus system and a variety of HP logic analyzers. Switches on the
front panel allow you to the select the appropriate bus type, bus size,
and parity. LED lights as indicators allow you to look at the static
condition of the bus at a quick glance. The HP E2423A software
provides inverse assembly of activity on the buses, and configurations
for the logic analyzers.
E
Log IC The following logic analyzers are supported by the HP E2423A
An alyze rs Preprocessor Interface:
Supported HP 1650A (requires memory upgrade)
This logic analyzer provides 1 k of memory depth with either
80 channels of 25 MHz state analysis or 80 channels of 100 MHz
timing analysis.
Due to the memory requirements for the HP E2423A inverse
assemblers, the HP 1650A Logic Analyzer requires a memory
upgrade to work with the HP E2423A Preprocessor Interface. To
increase the amount of memory in your HP 1650A you must install
the 10449A memory upgrade. For more information contact your
Hewlett-Packard Sales/Service Office.
Notice that the 10449A memory upgrade only increases the inverse
assembler processing space. It does not increase the 1 k state
memory depth.
HP 1650B, HP 16528, HP 16510A, and HP 16510B
These logic analyzers provide 1 k of memory depth with either
80 channels of 35 MHz state analysis (25 MHz state analysis for the
HP 16510A) or 80 channels of 100 MHz timing analysis.
Introduction-1
Introduction-2
HP 1660A/61A/62A/63A
The HP 1660A/61A/62A/63A Logic Analyzers provide 4 k of
memory depth with 136 channels (HP 1660A), 102 channels
(HP 1661A), 68 channels (HP 1662A), or 34 channels (HP 1663A)
of 100 MHz state analysis or 250 MHz timing analysis. These logic
analyzers also support various combinations of mixed state/timing
analysis.
HP 16511B
This logic analyzer combination provides 1 k of memory depth with
either 160 channels of 35 MHz state analysis, or 80 channels of
35 MHz state analysis and 80 channels of 100 MHz timing analysis.
HP 16540A,D with one HP 16541A,D Expansion Card
This logic analyzer combination provides 4 k of memory depth
(16 k with the D version) with up to 64 channels of 100 MHz state or
timing analysis.
HP 16542A (Master Card and one expansion card)
This logic analyzer combination provides 1 M of memory depth
with 32 channels of 100 MHz state or timing analysis.
HP 16550A
This logic analyzer provides 4 k of memory depth with 102 channels
per card of 100 MHz state analysis or 250 MHz timing analysis. The
logic analyzer will also support various combinations of mixed
state/timing analysis.
How to Use
This Manual
This manual is organized into three chapters and two appendices:
Chapter 1 explains how to install and configure the HP E2423A
Preprocessor Interface to perform measurements with the
supported logic analyzers. It also contains tables listing the SCSI
command sets for the different inverse assemblers.
Chapter 2 provides reference information on the format
specification and symbols configured by the HP E2423A
software. It also provides information about the inverse
assemblers and status encoding.
Chapter 3 contains additional reference information including
the characteristics and signal mapping for the HP E2423A
Preprocessor Interface.
Appendix A contains an overview of the Small Computer Systems
Interface (SCSI). Additional information should be obtained
from the appropriate standards organization for the SCSI
Standard X3T9.2/86-109 Revision 10b.
Appendix B contains information on troubleshooting problems or
difficulties which may occur with the preprocessor interface.
Introduction-3
Setting Up the HP E2423A
|
Introduction This chapter explains how to install and configure the HP E2423A
Preprocessor Interface to perform measurements with the supported
logic analyzers.
EE A
Du plicati ng the Before you use the HP E2423A software, make a duplicate copy of the
Master Disk HP E2423A master disk. Then store the master disk and use the
back-up copy to configure your logic analyzer. This will help prevent
the possibility of losing or destroying the original files in the event the
disk wears out, is damaged, or a file is accidently deleted.
To make a duplicate copy, use the Duplicate Disk operation in the disk
menu of your logic analyzer. For more information, refer to the
reference manual for your logic analyzer.
|
HP 16500A The HP E2423A Preprocessor Interface requires HP 16500A system
Software and module software version V04.01 or higher. If your software version
vr eee is older than V04.01, load new HP 16500A system software with a
Compati bil ity version number of V04.01 or higher before loading the HP E2423 A
software.
|]
Equipment The HP E2423 A SCSI Bus Preprocessor Interface consists of the
Su pp! ied following equipment:
e The preprocessor interface hardware, which includes the
preprocessor interface circuit card.
e The inverse assembler software on a 3.5-inch disk.
e This user's guide.
HP E2423A Setting Up the HP E2423A
SCSI Bus Preprocessor Interface 1-1
Required
The minimum equipment required for SCSI Bus analysis consists of the
following items:
e An HP 1650A (with memory upgrade), HP 1650B, HP 1652B,
HP 1660A/61A/62A/63A, HP 16510A, HP 16510B, HP 16511B,
HP 16540/16541A,D, HP 16542A, or HP 16550A Logic Analyzer.
e The HP E2423A Preprocessor Interface and Inverse Assembler.
e An additional cable to connect the HP E2423A to your SCSI bus
system (see pages 1-4 and 1-5).
Installation
Quick
Reference
Caution W
The following procedure describes the major steps required to perform
measurements with the HP E2423A Preprocessor Interface. The page
numbers listed in the various steps refer you to sections in this user's
guide that offer more detailed information.
To prevent equipment damage, be sure to remove power from both the
logic analyzer and the SCSI bus devices whenever the preprocessor
interface or logic analyzer is being connected or disconnected.
Setting Up the HP E2423A
1-2
. Select the appropriate bus mode (Single-Ended or Differential),
bus size (8-bit or 16-bit), and parity on the front panel of the
HP E2423A (see page 1-3).
. Connect the logic analyzer probes to the preprocessor interface
board as listed in table 1-1 (see page 1-8 and 1-9).
_ Connect the HP E2423A SCSI Bus Preprocessor Interface to
your SCSI bus system (see page 1-4).
. Load the configuration file into the logic analyzer by loading the
appropriate file from the flexible disk (see page 1-10).
. Load the appropriate inverse assembler from the flexible disk
(see page 1-11).
HP E2423A
SCSI Bus Preprocessor interface
a
Setting Up the The HP E2423A has three switches on the front panel:
HP E2423A Bus Mode. Allows the user to test either a Single-Ended or a
Front Panel Differential Bus system. This switch setting must match the type of
SCSI bus you are currently monitoring.
Bus Size. Allows the user to select either 8-bit or 16-bit bus size.
State Parity Check. The use of the parity bit is not mandatory on a
SCSI bus system. This switch allows the user to switch off the parity
check.
ud Excessive parity errors may appear on screen if parity is on with a
Note system that does not use parity.
Te Logrce Analyzer
<
& & с
= © ®
a о =
- N -
Option 881 © 2 y
SCSI ? спа a a a
Option 002
SCSI 2 use
Cotion 083 |
SCSI 3 use
SCSI 1 ribbon copie
Figure 1-1. SCSI Preprocessor Interface Connectors
HP E2423A Setting Up the HP E2423A
SCSI Bus Preprocessor Interface 1-3
EE
Connecting the
HP E2423A to
the SCSI Bus
The connectors on the HP E2423A are tied in parallel so that all the
connectors and cable combinations can be used with a Single-Ended or
Differential Bus. Also, there are always four connectors that are not
used. These connectors may be used for additional analysis with an
oscilloscope or other measurement device.
Figure 1-1 (previous page) shows the connectors on the SCSI
Preprocessor Interface. There are three types of connectors on the
front panel:
e Two 68-pin D-Shell shielded high-density type;
e Two 50-pin D-Shell shielded high-density type; and
e Two 50-pin (25-pin dual row, 0.1" spacing) nonshielded
connectors (see Caution on next page).
You will always need at least one additional cable to connect the
HP E2423A to your SCSI bus system. The following cable/connector
options are available from your HP Sales/Service Office:
e E2423A Option 001 1 meter, 50-pin HD screw (m) to
50-pin LD bail (m). This option contains
two of the cables described above.
e E2423A Option 002 1 meter, 50-pin HD screw (m) to
50-pin HD screw (m).
e E2423A Option 003 1 meter, 68-pin HD screw (m) to
68-pin HD screw (m).
If your SCSI Bus system requires different connectors or cables than
those listed above, you will have to either make or obtain adapter
cables. HP Direct Marketing (1-800-538-8787) has a variety of cables
with different lengths, connectors, and locking technologies. They
might have a cable which meets your requirements.
The following section provides instructions for connecting the cables to
the SCSI bus and the HP E2423A Preprocessor Interface.
Setting Up the HP E2423A HP E2423A
1-4
SCS! Bus Preprocessor Interface
To connect the HP E2423A to the bus, daisy chain the connectors so
both of the matching connectors are used together (see figure 1-2).
This is accomplished by the following steps:
1. Turn off the power to the bus system and logic analyzer.
2. Disconnect one end of a cable from the bus system and connect it
to one of the connectors on the HP E2423A.
3. Connect the optional or custom cable from the matching
connector on the HP E2423A to your bus system.
4. Turn on the bus and logic analyzer.
You can also connect the HP E2423A to either end of your SCSI bus
system. Remove the termination device from one end of the SCSI bus,
and use the appropriate cable to connect the HP E2423A to the SCSI
bus. Connect the termination device to the matching connector on the
opposite side of the HP E2423A board.
Some 50-pin ribbon cables have a connector clamped in the center of
the cable for connecting devices to the SCSI bus with only a single
connection. Do not use a center connector to connect the HP E2423 A
to the SCSI bus. Since the circuitry of the HP E2423A is part of the
transmission line for the SCSI bus, a center connector will cause stub-
length violations and the SCSI bus might not operate properly. You
should always have a cable or termination device on both of the
matching connectors on the HP E2423A.
Caution Wu
rh FR
| Device 1 | i Device2 | Device 3 | | Device 4 |,
… — | —
; |
| ;
| | |
. Terminator Terminator
|
; MP E2423A :
U —
Figure 1-2. Connecting to the SCSI Bus
HP E2423A Setting Up the HP E2423A
SCSI Bus Preprocessor interface 1-5
ms
Connecting to
the HP E2423A
кое @
Connect the logic analyzer probes to the cable connectors as listed in
table 1-1. The column heads refer to the logic analyzer pods, while
designations such as P1 refer to a connector on the preprocessor
interface.
Figure 1-3 shows the relative locations of the logic analyzer cards.
HP 16542A with three or four Expansion Cards
The locations for the HP 16542A expansion cards, relative to the
Master Card, depend on the number of expansion cards used. If one
or two expansion cards are used, Card 1 is located above the Master
Card and Card 2 is located below the Master Card. If three expansion
cards are used, two of them are located above the Master Card and the
third is located below the Master Card. When four expansion cards
are used, they are located as shown in figure 1-3.
Table 1-1 shows the physical location and connections for a
one-expansion-card system.
E
Power Up /
Down Sequence
When powering up, the logic analyzer must be powered up first, and
then the target system. The logic analyzer provides the power to the
active circuits on the preprocessor interface; unpowered circuits may
cause improper operation of the target system.
When powering down, the target system should be powered down first,
and then the logic analyzer.
Setting Up the HP E2423A HP E2423A
1-6
SCSI Bus Preprocessor Interface
= 165414.0 Exponzs.:0m Card |
HP TE540A.0 Master Cora
»P 165414.0 Exponsion Core 2
MP 165424 Expansion Card |
> 16542A Expansion Core Z
MP 16%242A Moster Cord
MP 145424 Expansion Card )
WP 16542A Eupension Card 4
(see note)
MD 1EZ118 monter Cord i
~~.
=P 105118 Cxapanger Card
>
=
mo 161504 Eapans ion Coreg
=P 185584 Master Card N ©
N,
=
Figure 1-3. Logic Analyzer Card Locations
(relative locations, actual slots used may vary)
HP E2423A Setting Up the HP E2423A
SCSI Bus Preprocessor Interface 1-7
Table 1-1. Logic Analyzer Connections and Configuration Files
( HP 1650 series, HP 16510A/B, HP 16511B, HP 16540/16541A,D, HP 16550A)
Logic Analyzer File Pod 6 Pod § Pod 4 Pod 3 Pod 2 Pod 1
HP 1650A/B, | CSCSI2 -- РА РЗ Р2 P1
HP 1652B, state, Timing Timing State State
HP 16510A/B | timing DATA |STAT DATA ¡STAT
clk v
HP 16511B DSCSI2 -- -- -- Р2 Pl
Upper Card |state, State State
timing DATA STAT
clk 4
HP 16511B - -- -- Р4 P3
Lower Card Timing | Timing
DATA STAT
HP 16541A,D | ESCSI2ST P4 P3 P2 .
Exp. Card 1 state Timing Timing State
DATA STAT DATA
ESCSIZTM
HP 16540A,D |timing P1
Master Card State
STAT
clk y
HP 16550A FSCSI2 P4 P3 P2 P1
state, Timing |Timing |State State
timing DATA STAT DATA STAT
clk v
Setting Up the HP E2423A HP E2423A
1-8
SCSI Bus Preprocessor Interface
( HP 1660 series, HP 16542A)
Table 1-1. Logic Analyzer Connections and Configuration Files
Logic Analyzer File Pod 6 Pod 5 Pod 4 Pod 3 Pod 2 Pod 1
HP 16542A ESCSI2ST P2
Exp. Card 1 state | State
DATA
HP 16542A P1
Master Card State
STAT
clk y
HP 16542A |ESCSI2TM P4
Exp. Card 1 timing Timing
DATA
HP 16542A P3
Master Card Timing
STAT
HP 16604/ FSCSI2 P4 P3 P2 P1
61A/62A state, Timing |Timing [State State
timing DATA ISTAT DATA STAT
clk y
HP 1663A FSCSI2 P2 P1
(state only) State State
DATA |STAT
clk +
HP E2423A
SCSI Bus Preprocessor interface
Setting Up the HP E2423A
Setting Up the The logic analyzer is configured for SCSI bus analysis by loading the
Analyzer from appropriate configuration file. The configuration files also load the
‚ inverse assembler "ISCSIDIR." You can then load a different inverse
the Disk assembler from the list on page 1-12.
For all logic analyzers except the HP 16540/16541A,D and HP 16542A,
the same configuration file is used for state or timing analysis. For the
HP 16540/16541A,D and HP 16542A, separate configuration files are
provided for state and timing. To load the files:
1.
2.
6.
Install the HP E2423A disk in the logic analyzer front disk drive.
Select one of the following menus:
For the HP 1650-series logic analyzers, select the 1/0 Disk
Operations menu;
For the HP 16500-series and HP 1660-series logic analyzers,
select the System Front Disk menu.
. Configure the menu to "Load" the analyzer configuration from
disk.
_ For HP 16500-series and HP 1660-series logic analyzers, select
the appropriate module (such as "100/500 MHz LA" or
"Analyzer”) for the load.
_ Use the knob to select the appropriate configuration file (see
table 1-1).
Execute the load operation to load the file into the logic analyzer.
| Ш, DO NOT Autoscale the timing analyzer. The Autoscale operation will
Caution destroy the previously loaded configuration. The only way to recover
the configuration after Autoscale is to reload it from the disk.
Setting Up the HP E2423A
1-10
HP E2423A
SCSI Bus Preprocessor Interface
Loading an The following section describes the different inverse assemblers
Inverse available with the HP E2423A. To load a different inverse assembler
Assembler after loading the configuration file:
1. Install the HP E2423A disk in the front disk drive of the logic
analyzer.
2. Select one of the following menus:
e For the HP 1650-series logic analyzers, select the 1/0 Disk
Operations menu;
e For the HP 16500-series and HP 1660-series logic analyzers,
select the System Front Disk menu.
3. Configure the menu to "Load" the inverse assembler from disk.
4. For HP 16500-series and HP 1660-series logic analyzers, select
the appropriate module (such as "100/500 MHz LA" or
"Analyzer") for the load.
5. Use the knob to select the appropriate inverse assembler (see
table 1-2, next page).
6. Execute the load operation to load the file into the logic analyzer.
ug To properly load the HP E2423A inverse assemblers, Analyzer 1 of the
Note logic analyzer must be on and configured as a State machine. If
Analyzer 1 and 2 are on and configured as State machines, a field will
appear on screen to allow you to select which analyzer to load the
inverse assembler into. Load the HP E2423A inverse assembler into
Analyzer 1.
HP E2423A Setting Up the HP E2423A
SCSI Bus Preprocessor Interface 1-11
Selecting the
Correct Inverse
Assembler
Note "9
The HP E2423A has seven inverse assemblers available for SCSI Bus
system analysis. The interpretation of the SCSI command set varies in
each inverse assembler to match the applications of various device
types. Only one inverse assembler can be used at a time. Table 1-2
lists the different inverse assemblers and the devices which are
generally supported by the command sets.
There is a good possibility that your SCSI Bus system will be made up
of several different device types, and each device type will interpret the
commands differently. For example, a disk drive connected to a
communication device contains two different device types. In this
situation you may need to decide which inverse assembler will best fit
your needs. To make it easier to select the appropriate inverse
assembler, the commands for each device type are listed in tables 1-3
through 1-9. By comparing the commands for each inverse assembler,
the most appropriate inverse assembler can be selected. The
commands which are common to all devices are listed in normal type,
and the commands which vary from device to device are listed in bold
type.
A different inverse assembler can be loaded into the logic analyzer
without losing the accumulated data.
Table 1-2. Inverse Assemblers
Inverse Assembler
Devices Supported
ISCSIDIR Direct Devices, Write Once Read Multiple Devices, and Optical Devices
ISCSISEQ Sequential Devices like tape backup drives, and Scanner Devices
ISCSIPTR Printers
ISCSIPRC Processor Devices
ISCSIDSE A special application which is used when there is a Sequential Access
Device on the SCSI Bus that uses Group 0 (6 byte) commands which
communicates with a Direct Access Device that uses Group 1 (10 byte)
commands
ISCSIAMC Automatic Media Changers, and Communication Devices
ISCSICDR CD ROMs
Setting Up the HP E2423A HP E2423A
1-12
SCSI Bus Preprocessor Interface
Table 1-3. ISCSIDIR Commands
Group 0 Commands | Group 1 Commands Group 2 Commands | Group S Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready {24 Set Window 40 Change Definition {AS Play Audio
01 Rezero 25 Read Capacity 41 Write Same A6 Exchange Medium
03 Request Sense 28 Read 42 Read Sub-Channel {A8 Read
04 Format Unit 29 Read Generation |43 Read TOC A9 Play Track
05 Read Block Limits { 2A Write 44 Read Header AA Write
07 Reassign Block 2B Seek 45 Play Audio AC Erase
08 Read 2C Erase 47 Play Audio MSF | AE Write and Verify
0A Write 2D Read Update 48 Play Audio Track | AF Verify
0B Seek Block Index BO Search High
OF Read Reverse 2E Write and Verify |49 Play Audio Track |B1 Search Equal
10 Write Filemarks |2?2F Verify Relative B2 Search Low
11 Space 30 Search High 4B Pause/Resume B3 Set Limits
12 Inquiry 31 Search = 4C Log Select B5 Request Volume
13 Verify 32 Search Low 4D Log Sense Element Address
14 Recovered Buffer |33 Set Limits 55 Mode Select B6 Send Volume Tag
15 Mode Select 34 Pre-Fetch SA Mode Sense B7 Read Defect Data
16 Reserve 35 Flush Cache B8 Read Element
17 Release 36 Lock/Unlock Status
18 Copy Cache
19 Erase 37 Read Defect Data
1A Mode Sense 38 Media Scan
1B Start/Stop Unit 39 Compare
1C Receive 3A Copyand Verify
Diagnostics 3B Write Buffer
1D Send Diagnostics |3C Read Buffer
1E Prevent/Allow 3D Update Block
Removal 3E Read Long
1F Read Log 3F Write Long
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
HP E2423A
SCSI Bus Preprocessor Interface
Setting Up the HP E2423A
1-13
Table 1-4. ISCSISEQ Commands
Group 0 Commands | Groupl Commands | Group2 Commands | Group S Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready [24 Set Window 40 Change Definition |AS Play Audio
01 Rewind 25 Get Window 41 Write Same A6 Exchange Medium
03 Request Sense 28 Read 42 Read Sub-Channel|A8 Read
04 Format Unit 29 Read Generation |43 Read TOC AA Write
05 Read Block Limits |2A Send 44 Read Header AC Erase
07 Reassign Block |2B Locate 45 Play Audio AE Write and Verify
08 Read 2C Erase 47 Play Audio MSF |AF Verify
0A Write 2D Read Update 48 Play Audio Track |BO Search High
0B Seek Block Index B1 Search Equal
OF Read Reverse 2E Write and Verify |49 Play Audio Track |B2 Search Low
10 Write Filemarks |2F Verify Relative B3 Set Limits
11 Space 30 Search High 4B Pause/Resume BS Request Volume
12 Inquiry 31 Object Position 4C Log Select Element Address
13 Verify 32 Search Low 4D Log Sense B6 Send Volume Tag
14 Recovered Buffer |33 Set Limits 55 Mode Select B7 Read Defect Data
1S Mode Select 34 Read Position/Get | SA Mode Sense B8 Read Element
16 Reserve Unit Buffer Status
17 Release Unit 35 Flush Cache
18 Copy 36 Lock/Unlock
19 Erase Cache
1A Mode Sense 37 Read Defect Data
1B Load/Unload 38 Media Scan
1C Receive 39 Compare
Diagnostics 3A Copyand Verify
1D Send Diagnostics |3B Write Buffer
1E Prevent/Allow 3C Read Buffer
Removal 3D Update Block
1F Read Log 3E Read Long
3F Write Long
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
Setting Up the HP E2423A HP E2423A
1-14 SCSI Bus Preprocessor Interface
Table 1-5. ISCSIPTR Commands
Group 0 Commands
Group 1 Commands
Group 2 Commands
Group § Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready [24 Set Window 40 Change Definition | AS Play Audio
01 Rezero 25 Read Capacity 41 Write Same A6 Exchange Medium
03 Request Sense 28 Read 42 Read Sub-Channel | A8 Read
04 Format Unit 29 Read Generation |43 Read TOC AA Write
05 Read Block Limits | 2A Write 44 Read Header AC Erase
07 Reassign Block 2B Seek 45 Play Audio AE Write and Verify
08 Read 2C Erase 47 Play Audio MSF | AF Verify
0A Print 2D Read Update 48 Play Audio Track | BO Search High
0B Slew and Print Block Index B1 Search Equal
OF Read Reverse 2E Write and Verify |49 Play Audio Track |B2 Search Low
10 Sync Buffer 2F Verify Relative B3 Set Limits
11 Space 30 Search High 4B Pause/Resume B5 Request Volume
12 Inquiry 31 Search = 4C Log Select Element Address
13 Verify 32 Search Low 4D Log Sense B6 Send Volume Tag
14 Recover Buffer 33 Set Limits 55 Mode Select B7 Read Defect Data
Data 34 Pre-Fetch SA Mode Sense B8 Read Element
15 Mode Select 35 Flush Cache Status
16 Reserve 36 Lock/Unlock
17 Release Cache
18 Copy 37 Read Defect Data
19 Erase 38 Media Scan
1A Mode Sense 39 Compare
1B Stop Print 3A Copy and Verify
1C Receive 3B Write Buffer
Diagnostics 3C Read Buffer
1D Send Diagnostics |3D Update Block
1E Prevent/Allow 3E Read Long
Removal 3F Write Long
1F Read Log
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
HP E2423A
SCSI Bus Preprocessor Interface
Setting Up the HP E2423A
1-15
Group 0 Commands | Group 1 Commands | Group? Commands | Group 5S Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready |24 Set Window 40 Change Definition | AS Play Audio
01 Rezero 25 Read Capacity 41 Write Same A6 Exchange Medium
03 Request Sense 28 Read 42 Read Sub-Channel|A8 Read
04 Format Unit 29 Read Generation [43 Read TOC AA Write
05 Read Block Limits { 2A Write 44 Read Header AC Erase
07 Reassign Block [2B Seek 45 Play Audio AE Write and Verify
08 Receive 2C Erase 47 Play Audio MSF |AF Verify
0A Send 2D Read Update 48 Play Audio Track |BO Search High
0B Seek Block Index B1 Search Equal
OF Read Reverse 2E Write and Verify |49 Play Audio Track |B2 Search Low
10 Write Filemarks |2F Verify Relative B3 Set Limits
11 Space 30 Search High 4B Pause/Resume BS Request Volume
12 Inquiry 31 Search = 4C Log Select Element Address
13 Verify 32 Search Low 4D Log Sense B6 Send Volume Tag
14 Recovered Buffer |33 Set Limits 55 Mode Select B7 Read Defect Data
15 Mode Select 34 Pre-Fetch SA Mode Sense B8 Read Element
16 Reserve 35 Flush Cache Status
17 Release 36 Lock/Unlock
18 Copy Cache
19 Erase 37 Read Defect Data
1A Mode Sense 38 Media Scan
1B Start/Stop 39 Compare
1C Receive 3A Copy and Verify
Diagnostics 3B Write Buffer
1D Send Diagnostics |3C Read Buffer
1E Prevent/Allow 3D Update Block
Removal 3E Read Long
1F Read Log 3F Write Long
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
Setting Up the HP E2423A
1-16
HP E2423A
SCSI Bus Preprocessor Interface
Table 1-7. ISCSIDSE Commands
Group 0 Commands Group 1 Commands Group 2 Commands | Group 5 Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready |24 Set Window 40 Change Definition | AS Play Audio
01 Rewind 25 Read Capacity 41 Write Same A6 Exchange Medium
03 Request Sense 28 Read 42 Read Sub-Channel 1 A8 Read
04 Format Unit 29 Read Generation |43 Read TOC A9 Play Track
05 Read Block Limits {2A Write 44 Read Header AA Write
07 Reassign Block 2B Seek 45 Play Audio AC Erase
08 Read 2C Erase 47 Play Audio MSF | AE Write and Verify
0A Write 2D Read Update 48 Play Audio Track | AF Verify
0B Seek Block Index BO Search High
OF Read Reverse 2E Write and Verify |49 Play Audio Track |B1 Search Equal
10 Write Filemarks |2F Verify Relative B2 Search Low
11 Space 30 Search High 4B Pause/Resume B3 Set Limits
12 Inquiry 31 Search = 4C Log Select B5 Request Volume
13 Verify 32 Search Low 4D Log Sense Element Address
14 Recovered Buffer |33 Set Limits 55 Mode Select B6 Send Volume Tag
15 Mode Select 34 Pre-Fetch 5A Mode Sense B7 Read Defect Data
16 Reserve Unit 35 Flush Cache B8 Read Element
17 Release Unit 36 Lock/Unlock Status
18 Copy Cache
19 Erase 37 Read Defect Data
1A Mode Sense 38 Media Scan
1B Load/Unload 39 Compare
1C Receive 3A Copy and Verify
Diagnostics 3B Write Buffer
1D Send Diagnostics |3C Read Buffer
1E Prevent/Allow 3D Update Block
Removal 3E Read Long
1F Read Log 3F Write Long
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
HP E2423A
SCSI Bus Preprocessor Interface
Setting Up the HP E2423A
1-17
Table 1-8. ISCSIAMC Commands
Group 0 Commands | Group 1 Commands Group 2 Commands Group 5 Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready [24 Set Window 40 Change Definition | AS Move Medium
01 Rezero 25 Read Capacity 41 Write Same A6 Exchange Medium
03 Request Sense 28 Get Message 42 Read Sub-Channel | A8 Get Message
04 Format Unit 29 Read Generation |43 Read TOC AA Send Message
05 Read Block Limits | 2A Send Message 44 Read Header AC Erase
07 Initialize Element |2B Position to 45 Play Audio AE Write and Verify
‘Status Element 47 Play Audio MSF | AF Venfy
08 Read 2C Erase 48 Play Audio Track |BO Search High
0A Write 2D Read Update Index B1 Search Equal
0B Seek Block 49 Play Audio Track |B2 Search Low
OF Read Reverse 2E Write and Verify Relative B3 Set Limits
10 Write Filemarks |2F Verify 4B Pause/Resume BS Request Volume
11 Space 30 Search High 4C Log Select Element Address
12 Inquiry 31 Search Equal 4D Log Sense B6 Send Volume Tag
13 Very 32 Search Low 55 Mode Select B7 Read Defect Data
14 Recovered Buffer |33 Set Limits 5A Mode Sense B8 Read Element
15 Mode Select 34 Pre-Fetch — Status
16 Reserve 35 Flush Cache
17 Release 36 Lock/Unlock
18 Copy Cache
19 Erase 37 Read Defect Data
1A Mode Sense 38 Media Scan
1B_Start/Stop 39 Compare
1C Receive 3A Copyand Verify
Diagnostics 3B Write Buffer
1D Send Diagnostics |3C Read Buffer
1E Prevent/Allow 3D Update Block
Removal 3E Read Long
1F Read Log 3F Write Long
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
Setting Up the HP E2423A
1-18
HP E2423A
SCSI Bus Preprocessor Interface
Table 1-9. ISCSICDR Commands
Group 0 Commands Group 1 Commands Group 2 Commands Group 5 Commands
(6 byte) (10 byte) (10 byte) (12 byte)
00 Test Unit Ready |24 Set Window 40 Change Definition | AS Play Audio
01 Rezero 25 Read Capacity 41 Write Same A6 Exchange Medium
03 Request Sense 28 Read 42 Read Sub-Channel { A8 Read
04 Format Unit 29 Read Generation |43 Read TOC AA Write
05 Read Block Limits | 2A Write 44 Read Header AC Erase
07 Reassign Block 2B Seek X 45 Play Audio AE Write and Verify
08 Read 2C Erase 47 Play Audio MSF | AF Verify
0A Write 2D Read Update 48 Play Audio Track | BO Search High
0B Seek Block Index B1 Search Equal
OF Read Reverse 2E Write and Verify 149 Play Audio Track |B2 Search Low
10 Write Filemarks |2F Verify Relative B3 Set Limits
11 Space 30 Search High 4B Pause/Resume B5 Request Volume
12 Inquiry 31 Search = 4C Log Select Element Address
13 Verify 32 Search Low 4D Log Sense B6 Send Volume Tag
14 Recovered Buffer {33 Set Limits 55 Mode Select B7 Read Defect Data
15 Mode Select 34 Pre-Fetch SA Mode Sense B8 Read Element
16 Reserve 35 Flush Cache Status
17 Release 36 Lock/Unlock
18 Copy Cache
19 Erase 37 Read Defect Data
1A Mode Sense 38 Media Scan
1B Start/Stop 39 Compare
1C Receive 3A Copy and Verify
Diagnostics 3B Write Buffer
1D Send Diagnostics |3C Read Buffer
1E Prevent/Allow 3D Update Block
Removal 3E Read Long
1F 3F Write Long
Read Log
The commands in bold type vary from device to device; the commands in normal type are common
to all devices.
HP E2423A
SCSI Bus Preprocessor interface
Setting Up the HP E2423A
1-19
2
Analyzing the SCSI Bus
E
Introduction
Format
Specification
7
Note 9
HP E2423A
This chapter provides reference information on the format
specification and symbols configured by the HP E2423A software. It
also provides information about the inverse assemblers and LED
indicators.
The HP E2423A software sets up format specifications for the logic
analyzer. There will be some slight differences in the displays,
according to which logic analyzer you are using. For example, some of
the logic analyzers do not have a Clock Period field.
The ADDR, DATA , and DATA labels all contain the same
information. The ADDR field is required by the inverse assembler
software, but the information is not applicable for SCSI bus analysis.
The DATA _ field shows the data in hexadecimal format in the Listing
menu. The DATA field is decoded and shows the instruction in SCSI
mnemonics.
Chapter 3 lists the SCSI bus signals for the HP E2423A and their
corresponding lines to the logic analyzer.
For those logic analyzers which have a Clock Period field (HP 1650A,
HP 1650B, HP 1652B, HP 16510A, HP 16510B, and HP 16511B), the
Clock Period field should remain in the current selection (> 60 ns)
since the SCSI bus has bus cycle periods greater than 60 ns. For more
information on the Clock Period field, refer to the reference manual
for your logic analyzer.
Analyzing the SCSI Bus
SCSI Bus Preprocessor interface 2-1
Symbols and
The configuration file sets up symbol tables on the logic analyzer. The
Labels tables contain alphanumeric values which identify data patterns.
Table 2-1 lists the bits assigned to the STAT and BUSIZE labels.
Table 2-2 lists the symbols for the STAT label. Table 2-3 lists the
symbols for the PHASE label.
Table 2-1. STAT Label and BUSIZE Label Bits
Bit Signal Description
0 Vo This signal is true when data flows to the initiator and false when
data flows to the target.
1 C/D This signal is true when not in the data phase and false when in the
data phase.
2 MSG This signal is true when in the message phase and false when not
in the message phase.
3 SEL This signal is true during selection of target device.
4 BSY This signal is true when the bus is in use and false when the bus is
free or during selection of target device.
5 REQ This signal is a handshake driven by the target device.
6 ACK This signal is a handshake driven by the initiator.
7 ATN This signal is used by the initiator to request an output phase.
8 RST A true signal resets all devices on the bus.
Analyzing the SCSI Bus
2-2
HP E2423A
SCSI Bus Preprocessor Interface
Table 2-1. STAT Label and BUSIZE Label Bits (continued)
Bit Signal Description
9 LBUSPT DBP Low byte bus parity bit (odd).
10 HBUSPT DBP1 High byte bus parity bit (odd).
11 LPTYER DBP Error. This bit is true when there is a low byte parity error.
12 HPTYER DBP1 Error. This bit is true when there is a high byte parity error.
15 BUSIZE This bit sends the position of the Bus Size switch on the
(BUSIZE HP E2423A front panel.
Label)
HP E2423A Analyzing the SCSI Bus
SCSI Bus Preprocessor Interface | 2-3
Table 2-2. STAT Symbols
"О
o
=
®
3
Symbol
RST BUS FREE
RESET
BUS FREE
ARBITRATION
ATTEN ARBIT
HL PTY ERROR
L_PTY ERROR
H_PTY ERROR
SELECT
RESELECT
DATA OUT
DATA IN
COMMAND
STATUS
MSG OUT
MSG IN
DATA XFR
© = x x x x x
LUN XX XX XX OH FX XX XX
SO HO x OM OM OX OO XXX
_O OM OX Xx HH © X ©
[E
—
с оон мн ххх хх ох
<>
o H HOO OO XxX X X X X Xx 9 XxX xX X
be >» м De De D >» > >» D ох »X KK X
XX XX XX XX X »X X KK KK X
————t © © © © © © © © © © © © © © HM A
SO 5 MX »X x x x x x x x OO KK x %
ммм ммм хм ок ххх
м ом ом ом ом ом ом оо 9 XXX еж ох ><
x "09000009 Fm H XM XXHIHO XAO
SNR Pee
pi
4 x 6 ©
| MOM MM MM »X » %
|
АТМ -
ACK — |
REQ —
BSY |
SEL |
MSG |
CD — |
1/0 —
High Byte Parity Error —
Low Byte Parity Error
High Byte Parity Bit
Low Byte Parity Bit
RESET
|
a
Analyzing the SCSI Bus HP E2423A
2-4 SCSI Bus Preprocessor interface
Table 2-3. Phase Symbols
Symbol Pattern
DATA OUT 0 0 0
DATA IN 0 0 1
COMMAND 0 1 0
STAT 0 1 1
PHASE 4 1 0 0
PHASE 5 1 0 1
MSG OUT 1 1 0
MSG IN 1 1 1
MSG —
C/D
VO — —
HP E2423A Analyzing the SCSI Bus
SCSI Bus Preprocessor Interface 2-5
—_—_———"
Accumulating
Data
Note 3
Touch RUN, and as soon as there is activity on the bus the logic
analyzer will begin to accumulate data. The logic analyzer will
continue to accumulate data and will display the data when the logic
analyzer memory is full or when you touch STOP.
The logic analyzer will flash "Warning Slow Clock" when data 1s no
longer being transmitted across the bus.
SEE
Listing Menu
Analyzing the SCSI Bus
2-6
Captured data is displayed as shown in figure 2-1. Additional labels
may be viewed by rolling the display. The inverse assemblers are
constructed so that the output lists the actual commands, status
conditions, messages, and phases of the SCSI bus. The DATA _ label
lists the data in hexadecimal format, and the DATA label lists the
instructions in SCSI mnemonics.
( State/T1ming a | ( Listing | ) (Print) ( Run
[OATa_ | Pnase SCSI mnemonic 0
Beso мех | Hex 0
0
0086 Arpitrate [De07
| 008 ! Select Ath ID=00
2 00CC sgout Icent:1 y Discennect, 129160! +0
3 0028 Commd Reed (10 Dyte)
4 9000 Commd Lus0
5 9000 Comma Logice! Block AGCr=0000CE8 10K
€ 900€ Commd
г 00C8 Commg
0010 Commd
9 0000 -ormd
10 0000 Comma Trensfer Length-C010H
11 0010 Сота
12 0000 Comma
13 0004 nsg.in Cisconnect
14 00C¢C Bus Free
15 0001 Arnitrate 10200
Figure 2-1. Listing Menu
HP E2423A
SCSI Bus Preprocessor Interface
The SCSI Bus
Inverse
Assemblers
note
HP E2423A
The HP E2423A has seven inverse assemblers available for use with
various SCSI devices. These give you the flexability of selecting the
correct inverse assembler to decode any of the different device types
that are called out in the SCSI Standard X3T9.2/86-109 Revision 10b.
The command sets for the inverse assemblers are listed in tables 1-3
through 1-9.
The interpretation of the SCSI Command Sets vary in each inverse
assembler to match the applications of various device types. Only one
inverse assembler can be used at a time.
The HP E2423A inverse assemblers are designed to decode
commands, messages, phases, and status conditions for 8-bit and 16-bit
Single-Ended and Differential SCSI Bus systems. Rolling the screen
up will inverse assemble the lines as they appear on the bottom of the
screen. If you jump to another area of the screen by entering a new
line number, simply roll the screen up to inverse assemble that block of
memory.
In order to correctly inverse assemble, the first byte of a command or
message sequence must have been captured. The first byte does not
have to be on the screen. If state capture starts or ends in the middle of
a command or message byte sequence the inverse assembler will make
an error in decoding that command or message.
Each time you inverse assemble a block of memory, the analyzer will
keep that block in the inverse assembled condition. You can inverse
assemble several different blocks in the analyzer memory, but the
activity between those blocks will not be inverse assembled.
Analyzing the SCSI Bus
SCSI Bus Preprocessor Interface 2-7
Interpreting The HP E2423A inverse assemblers decode six, ten, and twelve byte
Commands commands. The first line of the command lists the hexadecimal code
of the command and the actual command. Blocks are decoded on the
byte where they begin. The second line lists the logical unit for the
selected peripheral device and lists the names of any bits that are true
(logical 1). For example, byte 1 of a command often has bit 4 as DPO,
bit 3 as FUA, and bit 1 as RelAdr. If all three of these bits were set as
true, the following information would be displayed on the second line:
DPO FUA RelAdr
The last line lists the Flag and Link conditions when they are true
(logical 1).
Interpreting = The SCSI Standard X3T9.2/86-109 Revision 10b has set aside some of
Vendor Unique the byte assignments for messages, status, and commands as either
and Reserved reserved for later definition or vendor unique. In the case of message
Information and status, the HP E2423A inverse assembler listing will display the
hexadecimal code for the information, list the information as either a
message or status, and indicate if the information is vendor unique or
reserved.
For commands, the HP E2423A inverse assembler listing will display
the hexadecimal code for the command, list the information as a
command, and indicate which group the command is from.
Analyzing the SCSI Bus HP E2423A
2-8 SCS! Bus Preprocessor Interface
Interpreting The HP E2423A inverse assemblers decode the name of the message
Messages on the first line and indicate whether the message is going into the
initiator (Msg_in) or out of the initiator (Msgout). The messages
supported by the HP E2423A are:
00h Command Complete
01h Extended Message
02h Save Data Pointer
03h Restore Pointers
04h Disconnect
05h Initiator Detected Error
06h Abort
07h Message Reject
08h No Operation
09h Message Parity Error
OAh Linked Command Complete
OBh Linked Command Complete (with Flag)
OCh Bus Device Reset
ODh Abort Tag
OEh Clear Queue
OFh Initiate Recovery
10h Release Recovery
11h Terminate I/O Process
20h Simple Queue Tag
21h Head of Queue Tag
22h Ordered Queue Tag
23h Ignore Wide Residue
80h - FFh Identify
® e € * & € € € се сое ео вое ее еее
uy Identify messages include a logic unit specifier.
Note
HP E2423A Analyzing the SCSI Bus
SCSI Bus Preprocessor Interface 2-9
Interpreting Status
Analyzing the SCSI Bus
2-10
Extended Messages. Most messages are only one byte long, but
extended messages may be up to 256 bytes long. When the HP E2423A
inverse assemblers decode an extended message, the name of the
message is shown on the first line along with "xmsg” to identify it as an
extended message. Also, Msg_in or Msgout appears on the first line to
indicate whether the message is going into the initiator or out of the
initiator.
Each extended message will also include information specific to that
message on the first line:
e Modify Data Pointer includes the message arguments,
Synchronous Data Transfer Request includes the transfer period
and offset as a hexadecimal byte;
Extended Identify includes a logical unit number,
Wide Data Transfer Request includes the transfer width as a
hexadecimal byte.
The next line shows the length of the extended message in hexadecimal,
and the third line lists the message code. For a complete description of
specific extended messages, refer to the SCSI Standard X3T9.2/86-109
Revision 10b, Section 5.5.
The HP E2423A inverse assemblers decode all status conditions. Since
status is only one byte, the actual status is listed following the status
identifier. The status values supported by the HP E2423A inverse
assemblers are:
Good
Check Condition
Condition Met
Busy
Intermediate
Intermediate/Condition Met
Reservation Conflict
Command Terminated
Queue Full
HP E2423A
SCSI Bus Preprocessor Interface
Interpreting Data Since the data going across the bus is totally dependent and defined by
the user, the HP E2423A inverse assemblers can only indicate whether
the data is going into the initiator (Dat_in) or out of the initiator
(Datout). The rest of the data information cannot be interpreted by
the HP E2423A.
Arbitration, When an Arbitration, Select, or Reselect phase occurs, the HP E2423A
Select, and inverse assemblers identify the phase and list the interface device that
Reselect Phases is involved. For example:
Arbitr ID =3
indicates that interface device 3 has started an Arbitration phase.
Attention, Reset The HP E2423A inverse assemblers will display the Attention bit (Atn)
and Bus Free for every state in which the Attention bit is asserted true.
The Reset bit (Rst) will be displayed for every state where it 15 asserted
true. If the Reset bit becomes true while the SCSI bus is in the Bus
Free state, the state is displayed as "Reset Bus Free." Otherwise, a true
Reset bit is displayed as "Reset."
The Bus Free state is displayed as "Bus Free." If a Reset occurs while
the bus is free, the state is displayed as "Reset Bus Free."
Parity Error When the inverse assembler detects a parity error, it stops inverse
assembly until the next valid state.
If a parity error is detected on the first line of a command, status, or
message, then that line is not decoded. If the parity error is detected
after the first line, the command or message is decoded.
uy If parity is selected for the HP E2423A and parity is not used in your
Note SCSI Bus system, excess parity errors will appear on the listing display.
HP E2423A Analyzing the SCSI Bus
SCSI Bus Preprocessor Interface 2-11
The Trace Menu
Note и
Analyzing the SCSI Bus
2-12
The configuration files provided with the HP E2423A set up the Trace
Specification so that only five lines of data are stored for each data
transfer. Figure 2-2 shows the Trace Specification. The events which
occur in sequences 1, 2, and 3 are as follows:
In the following descriptions, Phases refers to the type of information
being transferred (data or commands), while State refers to a single
line of information on the logic analyzer screen.
1. Sequence 1 defines the starting point of state storage in the logic
analyzer memory. ‘While storing "no state” indicates that storage
will not begin until the specified trigger. If this is changed to
‘While storing "anystate™, the logic analyzer will use half of the
memory to store pretrigger states and half of the memory to store
posttrigger states.
2. Sequence 2 stores the states after the trigger. However, it will
only store five consecutive data phases. After the fifth data phase
it moves to sequence 3. You can change the number of data
phases that are stored by changing the 5 to the desired number.
3. Sequence 3 filters out the data phases while it looks for a non
data phase. When a non data phase occurs, it stores that phase
and transfers control back to sequence 2.
You can count the number of data phases that are filtered out in
sequence 3 by setting the Count window to "STATES." The number of
filtered data phases will be displayed on the first line after the five data
states. The time lapse between states can be observed by setting the
Count window to "TIME." However, the STATES and TIME
selections reduce the state storage memory by one half.
For further information on changing the Trace menu specifications,
refer to your logic analyzer operating manual.
HP E2423A
SCSI Bus Preprocessor Interface
2
3
u
(stetesTiming a) a (rece +) 1 ( Print
Sequence Levels
While sloring “ne sole
TRIGGER on
Branches
1
unie storing “enystete” Per Love
Then fing ~ 11909 Eon
Else on 20° yo to" leve) 2 oun
Store “ed”
Prestore
On “m0” ge 10 leve! 2
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(259%) (ARSITRATION ) (ets 0 )( eds 0
Fo) (Emer) (we т) (8)
Figure 2-2. Trace Screen
LED Indicators Three LED light bars of 10 LEDs each are used as front panel
indicators of the static condition of the bus.
e One group for Data; and
e One group for Status.
The following LEDs are provided for Data: data bits O through 15, two
Parity, and two Parity Error. Parity Error is not one of the SCSI signal
lines; it is generated by internal hardware of the preprocessor
interface when a parity error occurs and the front panel State Parity
Error switch is on.
Nine SCSI Status lines are shown on the other LED light bar. These
include I/O, C/D, MSG, and the SCSI phases.
HP E2423A Analyzing the SCSI Bus
SCSI Bus Preprocessor Interface 2-13
3
Additional Information
_—_—_—_—_—_—_—_—_—_—_—
Introduction This chapter contains additional reference information including the
characteristics and signal mapping for the HP E2423A Preprocessor
Interface.
PL
Characteristics The following characteristics are not specifications, but are typical
operating characteristics for the HP E2423A Preprocessor Interface.
These characteristics are included as additional information for the
user.
Bus Compatibility: 8-bit and 16-bit Single-Ended and Differential SCSI Bus systems
containing any of the device types specified in the SCSI Standard
X3T9.2/86-109 Revision 10b.
SCSI Standard
Supported: X3T9.2/86-109 Revision 10b.
SCSI Device Types
Supported: Direct Access Devices, Write Once Read Multiple Devices, and
Accessories Required:
Available Options:
HP E2423A
Optical Devices (ISCSIDIR)
Sequential Devices (ISCSISEO)
Printers (ISCSIPTR)
Processor Devices (ISCSIPRC)
Sequential Devices using Group 0 (6 byte) commands communicating
with a Direct Access Device using Group 1 (10 byte)
commands (ISCSIDSE)
Automatic Media Changers (ISCSIAMC)
CD ROM Devices (ISCSICDR)
Adapter cables may be required for some SCSI bus systems
Option 001 1 meter, 50-pin HD screw (m) to 50-pin LD bail (m).
This option consists of two cables.
Option 002 1 meter, 50-pin HD screw (m) to 50-pin HD screw (m).
Option 003 1 meter, 68-pin HD screw (m) to 68-pin HD screw (m).
Additional Information
SCSI Bus Preprocessor Interface 3-1
Maximum Bus Speeds:
Timing Specifications:
Signal Line Loading:
Bus Cycles Interpreted:
Power Requirements:
Logic Analyzer Required:
Number of Probes Used:
Environmental
Temperature:
Altitude:
Humidity:
Additional information
3-2
10 MHz
Meets all timing specifications set forth in SCSI ANSI Specification
X3T9.2/86-109, Revision 10b.
0.4 mA TTL Low at 0.5 V.
Arbitration
Select/Reselect
Commands
Messages
Status
Reset
Bus Free
0.80 A at +5 Vdc max, supplied by the logic analyzer.
HP 1650A (with HP 10449A memory upgrade), HP 1650B,
HP 1652B, HP 1660A/61A/62A/63A, HP 16510A, HP 165108,
HP 16511B, HP 16540/16541A,D (Master Card and one expansion
card), HP 16542A (Master Card and one expansion card),
or HP 16550A.
Two for state or timing, four for both.
Operating: Ого +55 degrees C (+32 to +131 degrees F)
Nonoperating: -40 to +75 degrees C (-40 to +167 degrees F)
Operating: 4600 m (15,000 ft)
Nonoperating: 15,300 m (50,000 ft)
To 90% noncondensing. Avoid sudden, extreme temperature changes
which could cause condensation within the instrument.
HP E2423A
SCSI Bus Preprocessor Interface
Clocki ng The SCSI bus signals are sampled and routed to the logic analyzer so
that all signals for a bus cycle are sent to the logic analyzer at the same
time. Since the SCSI bus signals become active at different times
throughout the bus cycle, some of the signals are latched by the
preprocessor interface, while others are connected directly to the logic
analyzer. When the logic analyzer is clocked, the latched and straight
through signals are all read at the same time.
The 16 Data bus lines plus the two Parity bits and the two Parity Error
bits that are generated by the preprocessor interface hardware are
sampled by internal latches. The I/O, C/D and MSG signals are
latched internally at the same time. The outputs of these latches are
then read at a later time when the logic analyzer receives its clock.
The Attention, Reset, Busy and Select signals are not latched internally
but are connected directly to the logic analyzer. These signals are
sampled after the signals listed in the previous paragraph. Figure 3-1
shows the latching and clocking cycle for the HP E2423A.
Arbitration Phase. The SCSI bus is sampled by the HP E2423A
Preprocessor Interface 800 ns after both BUSY and SELECT become
active. The logic analyzer is clocked 40 ns after these signals are
sampled.
SELECT or
ARBITRATION . RESELECT : INFORMATION PHASE
PHASE PHASE
p——— ACTIVE HIGH
ACTIVE HIGH
SELECT ARBITRATION ;
©: :
[5 ' .
*, ' 1
> РА ,
a Он
| mo ALT IVE HICH
© ICLENING interne! Е2423А
+ CL»
(a) Ena!yZer gets c'oches м1 507 1624 200)
Figure 3-1. HP E2423A Latching and Clocking Timing
HP E2423A Additional information
SCSI Bus Preprocessor Interface 3-3
Select and Reselect Phase. Internal latching takes place at the
beginning of the select phase when BUSY becomes negated. The logic
analyzer is clocked when BUSY becomes active at the end of the
SELECT phase.
Information Phases. When the SCSI bus is transferring data and
instructions, the handshake lines determine the clock. Figure 3-2 and
table 3-1 show the latching and clocking for the information phase.
Command, Status, and Message Phases. Internal latching takes place
when the Request handshake goes active. The logic analyzer is clocked
when the Acknowledge line goes inactive (negated).
Data In Phase. Request is the only controlling signal for the Data In
phase. Internal latching takes place on the active edge of Request. The
analyzer is clocked on the negating edge of Request.
Data Out Phase. Acknowledge is the only controlling signal for the
Data Out phase. Internal latching takes place on the active edge of
Acknowledge. The analyzer is clocked on the negating edge of
Acknowledge.
Bus Free. The E2423A waits for 400 ns after both BUSY and SELECT
are negated. Then the bus 1s sampled. First a latching operation takes
place, and 40 ns later the logic analyzer is clocked. IF RESET is active,
a Reset Bus Free is displayed of the analyzer screen. Otherwise only a
Bus Free is displayed on screen.
Reset. The RESET signal is sampled along with all other signals
during the bus active phases. If in the Bus Free condition and a reset
takes place, a latching operation takes place with a logic analyzer clock
following 40 ns later.
Additional Information HP E2423A
3-4 SCSI Bus Preprocessor Interface
Lg 190 ns MIN —————
над In ——— 38ns —
MIN | MIN
REQUEST
HP E2423A
| | |
e О =
—E TX
| -— ——
E On y ——=e—— 38ns
NIN | MIN
1099 ^% Мм]М ————-———
ACKNOWLEDGE
} | i
2513 ————— 1 ON =
SETUP TIME | MOLO
— TX
Figure 3-2. Request and Acknowledge Timing
Vi D/A
Table 3-1. Latching and Clocking for Information Phases
Phase Internal Latching Analyzer Clocked
Command Status MSG | 1 (see drawing above) 4
Data In 1 2
Data Out 3 4
Additional Information
SCSI Bus Preprocessor Interface 3-5
Interface The HP E2423A provides a complete mechanical and electrical
Description interface between the logic analyzer and an 8-bit or 16-bit SCSI bus
P system. This interface allows the logic analyzer to capture and decode
all of the activities on the SCSI bus. The SCSI bus is observed by high
impedance comparitors on the HP E2423A. The outputs of these
comparitors go directly to the logic analyzer for timing analysis.
For state analysis, the SCSI bus phase activities are decoded by the
Phase Detection Logic. The logic analyzer clock is sent out at the
correct times to capture the data.
, TO LOGIC ANALYZER
—— TIMING INPUTS
|| |
————m
q N INPUT N
ses! BUS > DATA LINES LATCHES 7
— |
2
_ PARITY PARITY
—
/ COMPARATORS
| ERROR > STATE INPUT
|
ERROR
DETECTION PARITY ERROR TO
LA SWITCH LOGIC ANALYZER
| Se | LOGIC
PHASE
LÀ OETECTION — ANALYZER
MISC/ 10343806
esr ———;———]—]—]—;—;
Figure 3-3. HP E2423A Block Diagram
Additional Information HP E2423A
3-6 SCSI Bus Preprocessor interface
SCSI Bus The following table describes the electrical interconnections
Si gna Ito implemented with the HP E2423A Preprocessor Interface. Since the
pods on the logic analyzer may be numbered differently than the other
HP E2423A logic analyzers, refer to table 1-1 to correlate the pod numbers.
Connector
Mapping
ug The interconnections implemented for state analysis with the
Note HP E2423A are not direct interconnections. The HP E2423A
Preprocessor Interface places digital circuitry between SCSI bus
signals and the logic analyzer input on pods 1 and 2. For timing
analysis, the interconnections are straight through.
HP E2423A Additional Information
SCSI Bus Preprocessor Interface 3-7
Table 3-2. Logic Anaiyzer to SCSi Signal Connections
Preprocessor Pod Logic Analyzer Probe SCSI Bus Signal Analysis Type
1 0 1/0 State
1 1 CD State
1 2 MSG State
1 3 SEL State
1 4 BSY State
1 5 REQ State
1 6 ACK State
1 7 ATN State
1 8 RESET State
1 9 LBUSPT State
1 10 HBUSPT State
1 11 LPTYER State
1 12 HPTYER State
1 (Blank ) State
1 14 (Blank ) State
1 BUSIZE State
2 0 Data 0 State
2 1 Data 1 State
2 2 Data 2 State
2 3 Data 3 State
2 4 Data 4 State
2 5 Data 5 State
2 6 Data 6 State
2 7 Data 7 State
Additional information HP E2423A
3-8 SCSI Bus Preprocessor Interface
Table 3-2. Logic Analyzer to SCSI Signal Connections (continued)
Preprocessor Pod Logic Analyzer Probe SCSI Bus Signal Analysis Type
2 8 Data 8 State
2 9 Data 9 State
2 10 Data 10 State
2 11 Data 11 State
2 12 Data 12 State
2 13 Data 13 State
2 14 Data 14 State
2 15 Data 15 State
3 0 I/O Timing
3 1 C/D Timing
3 2 MSG Timing
3 3 SEL Timing
3 4 BSY Timing
3 5 REQ Timing
3 6 ACK Timing
3 7 ATN Timing
3 8 RESET Timing
3 9 LBUSPT Timing
3 10 HBUSPT Timing
3 11 LPTYER Timing
3 12 HPTYER Timing
3 13 (Blank ) Timing
3 14 (Blank ) Timing
3 15 BUSIZE Timing
HP E2423A
SCSI Bus Preprocessor Interface
Additional Information
3-9
continued)
Preprocessor Pod | Logic Analyzer Probe SCSI Bus Signal Analysis Type
4 0 Data 0 Timing
4 1 Data 1 Timing
4 2 Data 2 Timing
4 3 Data 3 Timing
4 4 Data 4 Timing
4 5 Data 5 Timing
4 6. Data 6 Timing
4 7 Data 7 Timing
4 8 Data 8 Timing
4 9 Data 9 Timing
4 10 Data 10 Timing
4 11 Data 11 Timing
4 12 Data 12 Timing
4 13 Data 13 Timing
4 14 Data 14 Timing
4 15 Data 15 Timing
HP E2423A
Additional Information
3-10
SCSI Bus Preprocessor Interface
Se rvicing The repair strategy for the HP E2423A is board replacement.
However, table 3-3 lists some mechanical parts that may be replaced if
they are damaged or lost. Contact your nearest Hewlett-Packard
Sales/Service Office for further information on servicing the board.
Exchange assemblies are available when a repairable assembly is
returned to Hewlett-Packard. These assemblies have been set up on
the "Exchange Assembly” program. This allows you to exchange a
faulty assembly with one that has been repaired, calibrated, and
performance verified by the factory. The cost is significantly less than
that of a new assembly.
Table 3-3. Replaceable Parts
HP Part Number | Description
E2423-69501 Exchange Board/Cable Assembly
E2423-66501 Circuit Board/Cable Assembly
E2423-68702 Inverse Assembler Disk Pouch
5062-3383 Option 001 Cable (SCSI One, 8-bit)
8120-5548 Option 002 Cable (SCSI Two, 8-bit)
A1658-62018 Option 003 Cable (SCSI Three, 16-bit)
For a complete description of the optional cables listed in table 3-3, see
page 1-4. These cables can be ordered from your Hewlett-Packard
Sales/Service Office or from HP Direct Marketing (1-800-538-8787).
HP Direct Marketing also has a variety of cables which might meet an
unusual connector requirement.
HP E2423A Additional Information
SCSI Bus Preprocessor interface 3-11
A
SCSI Overview
Introduction The Small Computer Systems Interface (SCSI) is a standard that may
be used for fast transfers of data between computers and peripherals.
The standard hardware of the 8-bit or 16-bit SCSI Bus is a 50- or
68-wire cable that interconnects up to a maximum of 8 or 16 devices on
the bus. By definition there are 8 or 16 data lines with one or two
parity bits. Parity is odd and the use of the parity is optional for SCSI.
There are two SCSI Bus Types:
e Single-Ended; and
e Differential.
The Single-Ended bus runs at TTL levels with a logical 1 (active) being
a low level on the bus. The Differential bus uses two lines per signal
with the lines moving between approximately 2 and 3 volts.
Each device on the bus is assigned a device number of 0 through 15. If
there is a condition of more than one device asking for the bus at one
time, the highest priority device gets the bus. The device priority is in
the following order, with 7 the highest and 8 the lowest priority: 7, 6, 5,
4,3,2,1,0,15, 14, 13, 12, 11, 10, 9, 8. Each device is assigned one line
on the data bus for a device ID.
With SCSI, the host computer is not the bus controller. The device that
the host calls is the bus controller. Most often this is a mass storage
device.
The host computer is called the INITIATOR and the device that the
host calls on the bus 1s called the TARGET.
HP E2423A SCSI Overview
SCSI Bus Preprocessor Interface A-1
SCSI Status Lines Nine status lines are defined by the SCSI Standard X3T9.2/86-109
Revision 10b:
1/0;
C/D;
MESSAGE;
BUSY;
SELECT;
REQUEST;
ACKNOWLEDGE;
ATTENTION; and
RESET.
There are also ten phases defined by the SCSI standard. These are not
timing phases, but conditions of the bus action. They are:
ARBITRATION;
SELECT;
RESELECT;
DATA OUT;
DATA IN;
COMMAND;
STATUS;
MESSAGE OUT;
MESSAGE IN; and
BUS FREE.
SCSI Overview HP E2423A
A-2 SCSI Bus Preprocessor Interface
I/O, C/D, and Message. The I/O, C/D, and Message Status lines define
six of these phases of the SCSI Bus (see table A-1).
Busy. The bus is considered free when the Busy and Select lines are
inactive. An initiator asks for the bus by driving Busy active and driving
its identification (ID) line active on the data lines. If no other device
with a higher priority drives the line, then the initiator signals that it has
the bus by driving Select active. This is called the Arbitration Phase.
The parity bit is not tested in the Arbitration Phase.
Select. After the initiator has the bus and drives Select active it then
drives the ID line of the device it is calling (the target) active and
releases Busy. The device being called responds by driving Busy active.
The Initiator at this point releases Select. Select is not used for any
other purpose. This is called the Select or Reselect phase. Reselect is
when the Target is calling the Initiator. This is accomplished by driving
the I/O line active after the Arbitration phase. The target device 1s now
in control of the Busy line and is the only device that can release the
bus. At this point the bus is ready to transfer information.
Request and Acknowledge. These are handshake lines. Request is
driven by the target and Acknowledge is driven by the initiator. These
handshakes are used to transfer information between devices in either
direction. The information that is transferred between devices is
enveloped in one of six phases that are determined by the setting of the
three lines: 1/O, C/D, and Message (see table A-1).
Attention. Since the target is in control of the bus lines, the Attention
line (Atn) is used by the Initiator to request to send a Message or a
Command.
Reset. This 15 used to reset the bus to a Bus Free State and reset the
devices that are on the bus.
us The SCSI standard includes over 82 commands, 9 Status conditions,
Note and 25 Messages in its instruction set and has room for more to be
added. The bus is defined to be capable of transferring 10 Megabytes
per second using an 8-bit bus or 20 Megabytes per second using a
16-bit bus.
HP E2423A SCSI Overview
SCSI Bus Preprocessor interface A-3
SCSI Overview
A-4
Table A-1. Phases
Message
C/D
Name of Phase
=
©
ja => =; ны С © © ©
pd ++ O O = OO
Data Out
Data In
Command
Status
Phase 4
Phase 5
Message Out
Message In
| © = © > © Но ©
HP E2423A
SCSI Bus Preprocessor Interface
B
Troubleshooting
E
If you encounter difficulties while making measurements, use this
section to guide you through some possible solutions. Each heading
lists a problem you may encounter, along with some possible solutions.
Error messages which may appear on the logic analyzer are listed
below in quotes " ". Symptoms are listed without quotes.
If you are still having difficulties after trying the suggestions below,
please contact your local Hewlett-Packard service center for additional
assistance.
"Slow or Missing This error message might occur if the logic analyzer cards are not
Clock" firmly seated in the HP 16500/16501 frame. Ensure that the cards are
firmly seated.
This error might also occur if the target system is not running properly.
Ensure that the target system is on and operating properly.
If the error message persists, check the that the logic analyzer pods are
connected to the proper connectors, as listed in table 1-1. -
For HP 1650A and HP 16510A Logic Analyzers, check the
preprocessor interface power fuse in the logic analyzer.
No Activity on On the HP 1650A, HP 1651A, and HP 16510A Logic Analyzers if there
Activity Indicators is no activity the fuse which allows power to the preprocessor interface
is probably blown. Check the fuse in the logic analyzer. On the other
logic analyzers, if there is no activity, one of the cables, board
connections, or preprocessor interface connections is probably loose.
Check all connections.
HP E2423A Troubleshooting
SCSI Bus Preprocessor Interface B-1
Slow Clock If you have the preprocessor interface hooked up and running and
observe a slow clock or no activity, the +5 V suppiy coming {rom thé
analyzer may not be getting to the preprocessor interface.
To check the +5 V supply coming from the analyzer, disconnect one of
the logic analyzer cables from the HP E2423A and measure across pins
1 and 2 or pins 39 and 40 (see figure B-1).
o If +5 V isn’t observed across these pins, check the internal
preprocessor fuse or current limiting circuit on the logic analyzer.
For information on checking this fuse or circuit, refer to the
service manual for your logic analyzer.
e If +5 V is observed across these pins and you feel confident that
the +5 V is getting to the preprocessor interface, contact your
nearest Hewlett-Packard Sales/Service Office for information on
servicing the board.
2 (GND)
01650E67
Figure B-1. Pinout of the Logic Analyzer Cable
"No Configuration Verify that the appropriate module has been selected from the Load
File Loaded" {module} from File {filename} in the HP 16500 disk operation menu.
Selecting Load {All} will cause incorrect operation when loading most
preprocessor interface configuration files.
"Selected File is The logic analyzer displays this message if you try to load a
Incompatible” configuration file for the wrong module. Ensure that you are loading
the appropriate configuration file for your logic analyzer.
Troubleshooting HP E2423A
B-2 SCSI Bus Preprocessor interface
". .. Inverse
Assembler Not
Found"
No Inverse
Assembly
incorrect Inverse
Assembly
"State Clock
Violates Overdrive
Specification”
Note A
Unwanted
Triggers
HP E2423A
SCSI Bus Preprocessor Interface
This error occurs if you rename or delete the inverse assembler file that
is attached to the configuration file. Ensure that the inverse assembler
file is not renamed or deleted.
Verify that the inverse assembler has been synchronized by placing an
opcode at the top of the display (not at the input cursor) and pressing
the Invasm key (see "Inverse Assembler” in Chapter 2).
This problem is usually caused by a hardware problem in the target
system. A locked status line will often cause incorrect or incomplete
inverse assembly.
e Check the activity indicators for status lines locked in a high or
low state.
e Verify that the STAT and DATA format labels have not been
modified from their default values. These labels must remain as
they are configured by the configuration file.
eo Verify that storage qualification has not excluded storage of all
the needed opcodes and operands.
At least one 16-channel pod in the state analysis measurement stored a
different number of states before trigger than the other pods. This is
usually caused by sending a clocking signal to the state analyzer that
does not meet all of the specified conditions, such as minimum period,
minimum pulse width, or minimum amplitude. Poor pulse shaping
could also cause this problem.
The error message "State Clock Violates Overdrive Specification”
should only occur for HP 1650A,B, HP 1652B, HP 16510A,B, and
HP 16511B Logic Analyzers with the Clock Period field set to <60 ns.
If this error message is observed with the Clock Period set to >60 ns,
you may have a faulty logic analyzer. If a failure is suspected in your
logic analyzer, contact your nearest Hewlett-Packard Sales/Service
Office for information on servicing the instrument.
Unwanted triggers can be caused by unexecuted prefetches. Add the
prefetch queue depth to the trigger address to avoid this problem.
Troubleshooting
B-3
"Waiting for
Trigger”
Intermittent Data
Errors
Bent Pins
"Time from Arm
Greater Than
41.93 ms."
No Setup/Hold
Field on Format
Screen
"Default
Calibration
Factors Loaded"
(16540/41/42)
Troubleshooting
B-4
If a trigger pattern is specified, this message indicates that the specified
trigger pattern did not occur. Verify thai the triggering pattern is
correctly set.
If a "don't care” trigger condition is set, this message on an
HP 1650A,B, HP 1652B, or HP 16510A,B Logic Analyzer indicates
that the pattern duration is probably set to less than ( <) instead of
greater than (>). Since a "don’t care" pattern is always true, the "less
than" condition is never satisfied. Set the trace menu correctly for the
measurement that is desired. |
This problem is usually caused by incorrect signal levels. Adjust the
threshold level of the data pod. Use an oscilloscope to check the signal
integrity of the data lines, as needed.
Bent pins on the preprocessor interface, pin protectors, or adapters
can cause system errors or inverse assembly errors. Ensure all pins are
properly aligned and making contact.
The state/timing analyzers have a counter to keep track of the time
from when an analyzer is armed to when it triggers. The width and
clock rate of this counter allow it to count for up to 41.93 ms before it
overflows. Once the counter has overflowed, the system does not have
the data it needs to calculate the time between module triggers. The
system must know this time to be able to display data from multiple
modules on a single screen.
The HP 16540/16541A,D or HP 16542A Logic Analyzer cards are not
calibrated. Refer to your logic analyzer reference manual for
procedures to calibrate the cards.
The default calibration file for the logic analyzer was loaded. The logic
analyzer must be calibrated when using HP 16540A,D, HP 16541A,D
or HP 16542A cards. Refer to your logic analyzer manual for
procedures to calibrate the master clocking system, and ensure that the
"cal factors" file is saved.
HP E2423A
SCSI Bus Preprocessor Interface
PART NUMBER: E2423-90904
Print Date: November 1992
Reorder No. or
Manual Part No.
E2423-90904
E1192
æ Printed on
Recycled Paper
Гл HEWLETT”
PACKARD
Printed in USA
||
LIMA ARDEN
E2423-90904
">