Microdata Micro 400 Computer Reference Manual

Microdata
Micro 400 Computer Reference Manual
MICRO 400 COMPUTER
REFERENCE MANUAL
71 - 2 - 0400 - 001
March 1971
Microdata Corporation
644 East Young Street
Santa Ana, California 92705
© 1971! Microdata Printed in USA.
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TABLE OF CONTENTS
INTRODUCTION
SYSTEM FEATURES
ORGANIZATION
CENTRAL PROCESSOR
INSTRUCTIONS |
INSTRUCTION FORMAT
Memory Reference |
Memory Reference Indexed
Jump and Jump Mark Commands
Memory Test/Modify Instructions
General Skip Instructions
Input/Output Instruction Format
Control Instruction Format
Arithmetic/Logical Instructions
Halt
INPUT/OUTPUT INSTRUCTION IMPLEMENTATION
MEMORY
PROGRAM INTERRUPT
CONTROL PANEL
REGISTER SELECT
DATA ENTRY SWITCHES
MEMORY SELECT
STEP
RUN
INIT (Initialize)
POWER ON/OFF INDICATOR AND SWITCH
TELETYPE
OPERATION
TAPE
PAPER
RIBBON
TELETYPE OUTPUT
TELETYPE INPUT
SKIP IF TELETYPE READER IS READY
SKIP IF TELETYPE WRITER IS READY
DIRECT MEMORY ACCESS (DMA)
DMA INTERFACE
START DMA CYCLE
Transfer Out Of Memory
Single or Additional DMA Cycles
DMA CYCLE
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TABLE OF CONTENTS (continued)
APPENDIX A - INSTRUCTION LISTING
APPENDIX B - I/O INTERFACE
APPENDIX C - LEFT OUT INTENTIONALLY
APPENDIX D - CONNECTOR LISTING
APPENDIX E - CONVERSION TABLES
APPENDIX F - LEFT OUT INTENTIONALLY
APPENDIX G - FRONT PANEL USAGE
APPENDIX H - BOOTSTRAP ROUTINE
11
1.
0
INTRODUCTION
The MICRO 400 is a very low cost, high performance
general purpose processor designed to fill the gap
between special purpose digital hardware and the
mini computer. Basic design considerations were
given to optimizing the processor for application
to such tasks as peripheral control, data communi-
cations, instrumentation, process control and auto-
matic test. With powerful computing ability, easy
interfacing and modular design, the MICRO 400 is
truly a systems component. The central processor
1s designed on one board 12-1/2 inches by 18 inches
and is interconnected to all other systems components
via the unique MICRObus concept using an easily-
handled, easily-constructed flat cable rather than a
back plane.
The MICRO 400 offers a number of additional features
not available on other computers. The MICRObus
interconnects all systems components including cen-
tral processor, memory and special peripheral con-
trollers by means of a simple flat wire cable. The
standard Peripheral Data Bus is designed to take full
advantage of a wide range of peripheral
1-1
device controllers. Base Register addressing 1s an
optional feature not available on any other mini computer.
This feature allows offset addressing (operand plus offset)
to 65,536 words of memory and provides total program relocat-
ability on both the object level as well as the absolute level.
Memory is expandable from a basic 1,024 words of
core memory to 65,536 words of core memory, Also,
read only memory is available as an option and
directly replaces core memory for implementation.
The ability of the MICRO 400 to adapt to the host
system is an excellent criteria for determining true
systems compatibility. The design philosophy behind
the MICRO 400 is not only to provide the capabilities
needed in a mini computer but to allow the user to
choose the particular capability needed for his
application. If a feature is needed initially it can
be provided as a low cost factory option. If the
need is uncertain the same feature can easily be
added in the field as an option.
SYSTEM FEATURES
Some of the standard features available with the
MICRO 400 central processor include:
Multi-Accumulator Arithmetic
105 Program Instructions
Up to 32 Peripheral Devices
Direct and Index Addressing
Memory Directly Addressable in 4096 pages
Iwo's Complement Arithmetic
Local Operator's Control Panel (removable)
Maintenance Programs
Utility Debug Programs
Full Line of Peripherals and Systems Interfaces
Microbus Interconnection
Programmed 1/0 bus
Priority Interrupts
Some of the optional features available with the
MICRO 400 central processor include:
Base Register Addressing to 65K Words
Automatic I/O
Power Fail Protection from Run or Halt
2.
CENTRAL PROCESSOR
The central processor is the control unit for the
entire system. It governs all peripheral input/
output equipment, performs all the arithmetic,
logical and data handling operations, and sequences
the program. It is connected to the memory by the
MICRObus and to the peripheral equipment by either
the MICRObus or the Peripheral Data bus. The
processor handles words of 8-bits which are stored
in memory with a maximum capacity of 65,536 words
in memory. Words in memory are used by the central
processor as instructions in a program, as addresses,
or as operands, i,e., data for the program. The
processor performs a program by executing instruc-
tions retrieved from consecutive memory locations
as counted by the 12-bit program counter. At the
end of each memory cycle the program counter 1s
incremented by one so that the next byte 1s normally
taken from the next consecutive location in memory.
Sequential program flow is altered by changing the
contents of the program counter, either by incrementing
two extra times in a skip instructions, or by replacing
its contents with the values specified by a jump
instruction. The other internal registers in the
2-1
central processor include the two accumulators,
(A register and the B register). Data can be moved
in either direction between any memory location and
elther accumulator. All arithmetic and logical oper-
ations are performed on the operands contained in the
accumulators with the result appearing in one of
those accumulators. Associated with the accumulators
1s the overflow flip-flop which indicates when an
arithmetic overflow occurs out of the most signifi-
cant bit during an arithmetic instruction. Also
associated with the accumulators is the Link flip-
flop which indicates that a carry occurs out of the
most significant register position. Transfers to
and from peripheral devices are also made through
the accumulators.
On the MICRO 400 front panel is a set of data
switches through which the operator or maintenance
man can supply words and addresses to the program.
The front panel also has a number of control
switches that allow the operator to start and stop
the central processor, to deposit the contents of
the data switches in any memory location or accumu-
lator, and to display the contents of any location or
accumulator in the data indicators. The 12 indicators
on the front panel can display the contents of the
program counter, the accumulators, or the memory
data register. The remaining lights display internal
control conditions that are useful in program de-
bugging. A complete description of the operator's
control panel 1s contained in Section V.
INSTRUCTIONS
Instructions that move data to and from memory or the
peripherals, use one of the accumulators as a source or
destination while addressing a memory location or an input/
output device as the other destination or source. The arith-
metic and logical instructions do not have to reference memory,
they simply address the two accumulators, either or both
of which may supply operands, and one of which may re-
ceive the result. Therefore the memory is used for
storage of the program and permanent data while all
calculations are carried out in the accumulators. This
reduces considerably the amount of data movement as
compared with a single accumulator system, and saves
instructions.
The input/output hardware allows addressing of up to 32
peripheral devices. A single instruction can transfer
a word between an accumulator and a device and at the
same time control the device operation. Included in the
I/O system are facilities for program interrupt and for
Direct Memory high speed data transfers. The program
interrupt facilitates processor control of the peripheral
equipment by allowing any device to interrupt the normal
program execution and receive service on a priority basis,
The processor acknowledges an interrupt request by
responding to an address in memory that is provided by
the interrupting device. This address in memory will
contain a Jump and Mark command that sequences the program
to the appropriate interrupt service routine. The Jump
and Mark command also will store the contents of the
Program Counter in the interrupt service routine for
exit back to the interrupted program.
Devices requiring high speed data flow, such as magnetic
tape or discs, can gain direct access to memory through
the Direct Memory Access Channel without requiring the
execution of any program instructions or processor con-
trol. The program simply pauses while the memory access
is being made and then resumes normal program execution.
Throughout this manual all numbers representing instruc-
tion words, register contents, memory addresses and any
numbers appearing 1n program examples are hexadecimal
unless otherwise specified. Computer words are represented
by two hexadecimal digits. The use of numbers in the
text to specify quantities of objects such as words or
locations, to count steps in an operation, bit positions
etc. employs standard decimal notation. Where necessary
for clarity, base suffixes will be used as in the example
shown.
17510 = AF, ¢
$1AB = Hex 1AB
As described in the introduction, the MICRO 400
functions by executing instructions retrieved from
consecutive memory locations as counted by the 12-bit
program counter.
The instructions to be executed have
many variations, but can generally be classified as
follows:
INSTRUCTION TYPE
Load/Store
Accumulators
Modify Memory
Jump, Jump and
Mark
ACTION
Data 1s transferred from one memory
location or one accumulator. Either
may be the source of the data, the
other is the destination.
One memory location 1s affected.
The contents of this memory location
are either shifted, rotated/not
rotated, and interogated for various
skip conditions. During the shift,
new data may be shifted into the
memory location from various sources.
The contents of the program counter
are altered to affect a change in
program sequencing. The Jump and
Mark accomplishes the same thing how-
ever it writes the old contents of the
program counter into the locations
specified by the altered program
counter.
INSTRUCTION TYPE ACTION
Arithmetic, Logical The two accumulators are affected.
One or both may contain operands.
For arithmetic, both are operand
sources and one is destination.
For logical, only one accumulator
1s specified.
Input/Output Similar to Transfer Data however
memory 1s not involved. One
accumulator and one I/0 device are
specified. Data is transferred in
either direction, and device control
can be initiated, or device status
can be tested for selected conditions.
Control Similar to arithmetic/logical except
no accumulator is involved.
Instructions in the first three classes are considered
Memory Reference instructions. These instructions must
address memory to fetch or store operands, or store the
contents of the program counter.
The load/store accumulator commands contain the complete
12-bit operand address necessary to load or store
accumulator data anywhere in a 4096 word page. Indexing
is also available to modify the effective operand address.
In the latter case, the instruction contains an 8-bit
literal bias or displacement which is added to the
2-7
address value in the 16-bit index register to
extend the operand addressing to 65,536 words
of memory.
The Modify Memory Commands contain an 8-bit address to
directly address the first 256 words of the effective
4096 word page.
The Jump and Jump and Mark Commands are divided into 4
categories: Jump in Current Page (JPC), Jump in Extended
Page (JPE), Jump and Mark in Current Page (JMC) and Jump
and Mark in Extended Page (JME). The page size 1s 4096
words, page 0 is the low order 4096 words of memory and
page 1 is the second 4096 words of an 8192 word memory
system. The Jump Current commands are used to alter
the contents of the program counter without altering
the page pointer, while the Jump Extended commands will
switch from page 0 to page 1 or from page 1 to page 0.
The Jump and Mark command stores the contents of the
program counter. in the jump address and jump address
plus one. In addition, the upper 4 bits of the two
words of data stored as the Mark address are stored as
a Jump Command so the return address becomes a stand-
2.
2.
alone subroutine exit. Either the JPC or JPE op codes
will be stored depending on whether the Jump and Mark
command executed was a JMC or JME.
INSTRUCTION FORMAT
There are eight basic formats for instruction words in
the MICRO 400. Six of these formats are two byte
commands and two are one byte. Byte one of the command
will always contain the operation code and is the first
byte fetched from memory during execution.
Memory Reference
LDA ADDR Load A from Memory
LDB ADDR Load B from Memory
STA ADDR Store A into Memory
STB ADDR Store B into Memory
BYTE ONE BYTE TWO
ALD/ 7
1 der f/B ADDRESS
7 6 5 4 3 2 1 0 7 6 54 32171 0
Where: ADDR is a 12 bit address of the operand in
a 4096 word page.
Bits 4 and 5 of the first byte determine source/destina-
tion for the command. Bit 5=0 indicates memory source,
bit 5=1 indicates accumulator source.
2-9
‚д.
Bit 4=0 indicates accumulator A, and bit 4=1 indicates
accumulator B.
Bits 0 through 3 of byte one and bits 1 through 7 of
byte two form the memory address with bit zero of the
second byte being the least significant address bit.
Memory Reference Indexed
LDA BIAS,X(,M) Load A from Memory Indexed
LDB BIAS,X(,M) Load B from Memory Indexed
STA BIAS,X(,M) Store A into Memory Indexed
STB BIAS,X(,M) Store B into Memory Indexed
BYTE ONE | | BYTE TWO
01 LIN parm BIAS
76 54 3721 0 7 6 5141 3710
Where: BIAS is an 8-bit value (0-255) which is
added to the selected Index register to
form the operand address.
X selects index register 1 or 2.
M is an optional index modifier field
I - increment index by one
D- decrement index by one
blank - no change to index
‚2.
Bits three and four of byte one decode as follows:
00 = no auto increment or decrement
01 = auto decrement
10 = auto increment
Bits one ‘and two of byte one decode as follows:
00
01
|
10
11
load accumulator A
load accumulator B
store accumulator A
store accumulator B
Bit zero of byte one decodes the use of index register
one (0) or the optional index register two (1).
Jump and Jump Mark Commands
JPC ADDR Jump within current 4096 page
JPE ADDR Jump within extended 4096 page
JMC ADDR Jump Mark within current 4096 page
JME ADDR Jump Mark within extended 4096 page
I BYTE ONE BYTE TWO
GE ] |
| 1 IMR | ADDRESS
7 6 5 4 3 2 1 0 7 6 54 3 21 0
Where: ADDR is a 12-bit address.
=
Bits 4 and 5 of byte one decode as follows:
00 = Jump in current page
01 = Jump into extended page and Switch page select
10 = Jump and Mark in Current Page
11 = Jump and Mark into extended page and Switch page select
‚2.4 Memory Test/Modify Instructions
Skip SER ADDR
SOR ADDR
SPM ADDR
SMM ADDR
Shift Memory RCS ADDR
RCZ ADDR
RCO ADDR
RCA ADDR
Skip if memory is Even, Rotate memory”
Skip if memory is Odd, Rotate memory*
Skip if Positive Memory
Skip 1f Minus Memory
Right shift one place, copy sense flip-flop
Right shift one place, Copy Zero
Right shift one place, Copy One
Right shift one place, Copy least
significant bit of the A Accumulator
Where: ADDR is an 8-bit address of the first 256 words
of the current 4096 word page.
BYTE ONE BYTE TWO
jo 1 0 1 1| FUNCTION ADDRESS
—76 54 3721 076 514 3 2 1 0
*Rotation of memory will take place regardless of
whether memory is odd or even.
2.
Bits zero through two of byte one decode the memory
modification that occurs as follows:
21
000 = Skip 1f even, rotate memory right one
001 = Skip if odd, rotate memory right one
010 = Skip if positive, do not rotate
011 = Ski
p if negative, do not rotate
100 = Right shift memory one, copy sense flip-flop
101 = Right shift memory one, copy z
ето
110 = Right shift memory one, copy one
111 = Right shift memory one, copy LS bit of A
General S
kip Instructions
SNZ LIT
SNO LIT
SMZ LIT
SMO LIT
Skip if all of the
Skip if any of the
Skip 1f all of the
Skip if any of the
selected
selected
selected
selected
N-class
N-class
M-class
M-class
conditions
conditions
conditions
conditions
are Zero
is One
are Zero
is One
N or M class
Where: LIT is an 8-bit literal mask for the
conditions.
BYTE ONE BYTE TWO
GROUP
0 1 0 0 SELECT MASK BITS |
7 6 5 4 3 2 1 0 7 6 5 4 3 2 0
Bits zero through 3 of byte one are
1000-Examine group
1001-Examine group
1010-Examine group
1011-Examine group
2-15
(N), skip if all
(N), skip if any
(M), skip if all
(M), skip if any
decoded as follows:
condition(s) are zero
condition 1s true
condition(s) are zero
condition 1s true
‚2.
N-Class Conditions
Bit Source
0 Most Significant Bit of A
1 Least Significant Bit of A
2 A Register Not Zero
3 Overflow
4 Most Significant Bit of B
5 Least Significant Bit of B
6 B Register Not Zero
7 Link
M-Class Conditions
Bit Source
0 Interrupt Enabled
1 Sense Response
2 Teletype Read Ready
3 Teletype Write Ready
4 X1 Register Low Order 8 Bits Equal Zero*
5 X2 Register Low Order 8 Bits Equal Zero*
6 Sense Switch one Not Set
7 Sense Switch two Not Set
*Note - See Instructions SI1, SD1, SI2, SD2 for full definition.
Input/Output Instruction Format
Input/output instruction format is described below:
In the format box, Function (F) and Device address (D)
are referred to only as F and D. The programmer must
substitute a valid three bit code for F and a five
bit code for D. Also, in the case of Data Output
and Data Input, the programmer must specify which
accumulator he is requesting. A one in byte one, bit
two will select accumulator B; a zero, accumulator A.
SEN F,D Sense
EXC F,D External Control
DIA F,D Data Input into the A Register
DOA F,D Data Output from the A Register
DIB F,D Data Input into the B Register
DOB F,D Data Output from the B Register
Where: F is a 3 bit function code
D is a 5 bit device address
EXC F,D EXTERNAL CONTROL
BYTE ONE BYTE TWO
O 1 0 1 0 X 0 1 CF D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
Perform the control function specified by F in
device D.
2-15
SEN F,D SENSE DEVICE STATUS
| BYTE ONE BYTE TWO |
| 0 1 0 1 0 X оо F D
~ 7 6 5 4 3 2 1 0 7 6 5 1 3 2 1 0
Set the central processor sense flip-flop according
to the state of F in device D.
(DIA F,D) (DIB F,D) DATA TRANSFER INTO ACCUMULATOR A OR 8
BYTE ONE BYTE TWO
0 1 0 1 dB/A 1 0| F D
760543 23 1 0-76 5 4 3 710
Bring data into accumulator A or B from device D.
F may be used to control the type of data from device
D such as status word, true data, or special data.
F may also be used to specify action by the device.
(DOA F,D) (DOB F,D) DATA TRANSFER OUT OF ACCUMULATOR A OR B
BYTE ONE | BYTE TWO
0 1 0 1 OB/A| 1 1 F D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Transfer the contents of accumulator A or B to the
device specified by D. Special control may be
exercised in the device by F.
.2.
.2.
. 2.
Control Instruction Format
O 1 0 0) FUNCTION
4 3 2 1 0
Bits zero through three provide the following specific
functions:
Mnemonic 3210
SOF 0000 = Set Overflow Flip-flop
ROF 0001 = Reset Overflow Flip-flop
EIN 0010 = Enable INterrupts
DIN 0011 = Disable INterrupts
NOP 0101 = No OPeration
SSF 0110 = Set Sense Flip-flop
RSF 0111 = Reset Sense Flop-flop
Halt
Halts the computer. The program counter register (P)
will contain the address of the next byte after the
HALT, STEP mode will be selected.
Arithmetic/Logical Instructions
The one byte arithmetic/logical instructions are executed
in the accumulators. One or both of which are operand
sources and one of which is a destination. Execution
time is one cycle (1.6 microseconds).
2-17
The link and overflow flip-flops may be affected by
the Arithmetic/Logical instructions.
ARITHMETIC
FUNCTION
7 6 5 4 3 2 1 0
0 0
MICRO 482 INSTRUCTION LISTING
ARITHMETIC -—----—— ae LLE 0 0
ADD
SUBTRACT
AND
INCLUSIV= OR
EXCLUSIVZ OR
LEFT SHIFT
RIGHT SHIFT
COMPLEMENT
INCREMENT
DECRZMENT
COPY
CLEAR
SET
LINK
MNEMONIC
A3A
AAB
S3A
SAA
N3A
NAB
O3A
OAB
X3A
LSA
LSB
RSA
RSB
RRA
RRB
OCA
OCB
TCA
TB
IAA
1 AB
138
DAA
DAB
D3B
CAB
CBA
CLA
CLB
POA
РОВ
‚ МОА
MOB
CLL
LCB
INSTRUCTION FORMAT:
OP CODE
12
09
14
22
1E
3B
29
9D
2D
11
BA
1F
SF
BF
er
28
24
26
34
16
31
3e
19
21
Be
39
2B
21
96
17
97
18
98
PE
—38
SCRIPTION
ADD 3 TD A
ADD A TO B
SUBTRACT B FROM A TO
SUBTRACT A FROM 3 TO
AND 3 WITH A TO A
AND A WITH 3 TO 3
INCLUSIVE OR B WITH A TO
INCLUSIVE OR A WITH B TO
EXCLUSIVE OR B.WITH A TO
LEFT SHIFT A ONE BITs INSERT vw
LEFT SHIFT B ONE 31Ts INSERT ©
RIGHT SHIFT A ONE BITs,INSERT 3
RIGHT SHIFT B ONE BITs INSERT 3
RIGHT ROTATE A ONE BIT
RIGHT ROTATE В ONZ BIT
ONES COMPLEMENT A
ONES COMPLEMENT 3
TWOS COMPLEMENT A
TWOS COMPLEMENT 3
INCREMENT A BY 1 TO A
INCREMENT A BY 1 TO В
INCREMENT В BY 1 ТО В
DECREMENT A BY 1 TO A
DECREMENT A BY 1 TO B
DICREMENT В BY 1 TO B
COPY A INTO B
COPY В INTO A
CLEAR A TO ZERO
CLEAR B TO ZERO
POSITIVE ONE TO A
POSITIVE ONE TO 3
MINUS ONE TO. A
MINUS ONE TO B
CLEAR LINK BIT TO ZERO
SET LINK BIT AND SLZAR В
XXX
* NOTE — AFFECT ON LINK/OVERFLOW BITS
S - LINK ALWAYS SET
R - LINK ALWAYS RESET
A - LINK AFFECTED (MAY 3E SET OR RESET) AND
OVERFLOW MAY BE SET
2-19
x L'INK/
OVERFLOW
A
3
A
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2.
INPUT/OUTPUT INSTRUCTION IMPLEMENTATION
The input/output instructions control all transfers
of data to and from the peripheral equipment, and
also perform various operations within the central
processor. Instructions in this class are all two
byte instructions and the format is discussed in this
section. Bits three through seven of byte one are
the operation code while bits zero through two are the
specific input/output operation code (transfer data
in, transfer data out, external control, and sense).
For this discussion, "input of data" always refers to
the transfer of data from a peripheral device into the
central processor while an "output" command transfers data
out of the central processor to a peripheral device.
Bits five through seven of byte two of the input/output
instruction contain special control bits that will be
discussed later in this section. Bits zero through
four contain device address bits that select the device
that is to respond to the instruction. This format
thus allows for 32 codes to be used for device
selection. A table in Appendix B lists all devices
for which codes have been assigned. Every device
controller has a five bit device selection network that
decodes the device address bits so that only the addressed
device responds to the signals sent by the processor over
the input/output bus.
2.
INPUT/OUTPUT INSTRUCTION FORMAT
Input/output instruction format is described below:
In the format box, function (F) ‘and device address (D)
are referred to only as F and D. The programmer must
substitute a valid three bit code for F and a five
bit code for D. Also, in the case of Data Output and
Data Input, the programmer must specify which accumulator
he is requesting. A one in byte one bit two will select
accumulator B, a zero, accumulator A.
EXC F,D EXTERNAL CONTROL
BYTE ONE | BYTE TWO
3
|
i
0 1 0 1 0 X 0 1 F : D
7 6 54 3 21 0 7 6 5 4 3 2 1 0
{
Perform the control function specified by F in device
D.
SEN F,D SENSE DEVICE STATUS
BYTE ONE BYTE TWO
0 1 0 1 0 X 0 0 F D
76 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Set the central processor sense flip-flop according to
the state of F in device D.
DIX F,D DATA TRANSFER INTO ACCUMULATOR A OR B
BYTE ONE | — BYTE TWO
0 1 0 1 OB/A 1 0 Fo D |
| |
I 6 5 4 3 2 1 0 7 6 Er 17
Bring data into accumulator A or B from device D.
F may be used to control the type of data from
device D such as status word, true data, or special
data. F may also be used to specify action by the
device
DOX F,D DATA TRANSFER OUT OF ACCUMULATOR A OR B
— BYTE ONE — BYTE TWO
0 1 0 1 08/4111 F | D
|
76 543210 76 51437170
Transfer the contents of accumulator A or B to the
device specified by D. Special control may be exercised
in the device by F.
To place a device in operation, (assume an output of
data is to be accomplished) the central processor first
will test for a device ready condition. This will be
done by either the Sense command or an input of status
word from the device. When a true ready response is
received, the first character of data will be trans-
ferred to the device controller. This will typically
cause the device controller to write the data on the
peripheral device (paper tape for example). At the
same time, as soon as the device controller has
accepted the data from the central processor,
it will set the "busy" or "not ready" condition until
all peripheral device action has taken place. At
that time, the "busy" condition will be cleared and a
“ready” signal made available for the next transfer of
data.
| TEST DEVICE | BUSY
READY |
J READY
| TRANSFER |
DATA OUT
y
EXIT @—2 | MORE DATA TO TRANSFER]
$ YES
CENTRAL PROCESSOR GETS
NEW DATA OUT OF MEMORY
FOR NEXT OUTPUT
INSTRUCTION
Ep
| START AGAIN
FIGURE 2-1
The above procedure is of course the most inefficient
for optimum use of the central processor. To optimize
program execution, an interrupt would be used to allow
the central processor to execute instructions in the
program instead of hanging in a small program loop
waiting for the peripheral device to become ready. This
would result in the following flow chart. Interrupts
will be discussed in detail later in this section.
When all the data has been transferred, the program
will generally inform the device in some manner;
possibly by not allowing any further interrupts until
new data is available for output.
2-24
|
SET DEVICE INTERRUPT
ENABLE CONDITION
ине неон но
v
NORMAL PROGRAM EXECUTION
TD
des, de
INTERRUPT FROM DEVICE ——. <——
REQUESTING DATA OCCURS —_
HERE (MAY OCCUR AT ANY
TIME.)
!
!
}
Y
FURTHER INTERRUPTS ARE
AUTOMATICALLY DISABLED
AND THE CENTRAL PROCESSOR
TRANSFERS TO THE I/O
SUBROUTINE.
NORMAL PROGRAM
EXECUTION CONTINUES
I/O SUBROUTINE SAVES CPU
STATUS AND ACCUMULATORS.
I/0 SUBROUTINE EXECUTES
THE DATA SERVICE TO THE
REQUESTING DEVICE.
1/0 SUBROUTINE RESTORES
CPU STATUS AND ACCUMULATORS
ENABLES INTERRUPTS AND
RETURNS TO THE PROGRAM THAT
WAS INTERRUPTED.
FIGURE 2-2
MEMORY
From the programmer's standpoint, all of memory is a
set of contiguous 8-bit word length locations whose
addresses range from hexadecimal $0000 to a maximum
of $FFFF depending on the memory configuration for a
particular installation. An address of $FFFF represents
the maximum memory size of 65,5364 words of storage.
However, the memory is actually made up of a number of
memory modules each having a capacity of 1024, 4096,
or 8192 (decimal) words. The configuration can also
contain read-only memory modules for the storage of
unalterable programs or data. From the programmer's
viewpoint read only memory differs only in that its
contents cannot be altered.
4.
0
PROGRAM INTERRUPT
The devices on the I/O bus are assigned priority for
control of external interrupts and for Automatic 1/0
operations. The priority is achieved by the physical
location of the device controller on the I/O bus. That
is to say the first device on the I/O bus has the highest
priority and the last unit on the I/O bus the lowest.
This is achieved by the signal PROT that passes priority
down through the bus from one controller to the other.
Before a controller can make an interrupt request (IREQ)
it must receive priority from the next higher controller
in the chain. A controlier never passes priority along
to a lower priority controller while making a request.
Interrupt requests from peripheral controllers are
carried on the Interrupt Request Line (IREQ) of the I/O
Bus. The central processor will recognize the IREQ at
the end of the current instruction in process and will
respond with the Interrupt Acknowledge signal (IACK).
During the period IACK, the peripheral controller will
drive the I/O bus lines EB00 through EB07 with its device
address shifted left one to provide the interrupt response
address. The shift in the address is necessary to allow
the peripheral device to select an even numbered
address to provide as the interrupt response address.
For example, the following chart gives the interrupt
response address available to peripheral device number
OF.
DEVICE ADDRESS RESPONSE ADDRESS |
OF (0000 1111) 1E(0001 1110)
It must be emphasized that the Interrupt REQuest (IREQ)
occurs in a completely asynchronous fashion with regard
to the sequencing of a program in the MICRO 400. It
can occur at any time during an instruction but must
wait until the end of the instruction to be recognized.
This dictates that the longest wait for interrupt
acknowledge will be the time necessary to complete the
longest instruction, the Jump and Mark command, plus
queing time which is 1.2 microseconds. This command
requires 4 cycle times (6.4 microseconds) to complete
its execution, therefore the maximum wait will be
6.4 microseconds plus 1.2 microseconds or 7.6 micro-
seconds. The minimum wait will be 1.2 microseconds.
4-2
In addition, Interrupt Enable must be set before the
central processor can recognize any interrupts other
than the Powerfail/Restart interrupts. The Interrupt
Enable condition is set and reset by the one word
control commands outlined in Section 2.2
EIN 01000010
7654037770
ENABLE INTERRUPT FORMAT
DIN 01000011
76543210
DISABLE INTERRUPT FORMAT
In the process of recognizing an interrupt, the
central processor automatically disables further
interrupts. It is necessary to do an Enable
Interrupt command before any further interrupts
will be acknowledged.
Note that when base register addressing is being used
the "EBL" (extended base to lower Base) and the "LEB"
(lower Base to extended base) instructions inhibit all
interrupts (including power failure) until after the
following extended jump (either "JPE" or "JME"). Thus
the execution time for the EBL, LEB commands (3.2usec.)
and any interspersed instructions must be considered in
the timing analysis for interrupt responses.
4-3
CENTRAL PROCESSOR
PERIPHERAL DEVICE CONTROLLER
т DEVICE CONTROLLER
/ REQ REQUESTS INTERRUPT
CENTRAL PROCESSOR
ACKNOWLEDGES REQUEST ТАСК J |
DEVICE CONTROLLER SENDS
INTERRUPT ADDRESS TO
CENTRAL PROCESSOR
‘ EB00-EBO7 € |
CENTRAL PROCESSOR TAKES
ADDRESS AS THE INTERRUPT
RESPONSE ADDRESS AND
JUMPS TO THE INTERRUPT
SUBROUTINE REQUESTED
BY THE DEVICE
e
IREQ MAXIMUM
7.6 MICROSECONDS
IACK
ADDRESS DRIVE
MICROSECONDS
FIGURE 4-1
= BEGINS INTERRUPT
SERVICE AT THIS POINT.
INTERRUPT CONTROL SIGNAL SEQUENCING
PROGRAM IN PROCESS
200
201
202
203
INTERRUPT FROM DEVICE 204 Sa |
ADDRESS 06 OCCURS AT \
THIS TIME 205 NEXT INSTRUCTION ADDRESS
— FORCED TO OC, CONTENTS OF
206 PROGRAM COUNTER REMAIN 204
RETURN TO ORIGINAL OC JUMP, MARK
PROGRAM EXECUTION ) OD TO LOCATION 100
—e 100 EXIT (MARKED JUMP y
STORE CONTENTS OF PROGRAM
101 To LOCATION 204) COUNTER (204) AT LOCATIONS
J 100 AND 101, BEGIN PROGRAM
102 \ EXECUTION AT LOCATION 102
103 q |
INTERRUPT
104 | SERVICE
105 ROUTINE
DD
120 JUMP
121 TO LOCATION 100
VW)
FIGURE 4-2
INTERRUPT SEQUENCING
CONTROL PANEL
The control panel is illustrated in Figure 5-1. The
indicators in the upper right section display control
conditions, while the indicators directly above the
data switches display the accumulators, memory data or
the program counter. The data switches can best be
visualized as a hardware register through which the
operator can supply addresses and data to the processor.
The "up" position of the data switch represents a one.
The four switches on the right side of the operator's
panel (EXC, STEP, INIT, RUN) are momentary contact
spring return switches. They provide control signals
to initiate action in the central processor.
NOTE
Since the control panel is not necessary
to maintain central processor operation,
it may be removed and all operator control
initiated from the teletype using the TOS
(teletype operating system) or from a special
systems console. The auto bootstrap option
would be required for startup without the
front panel.
RUN
INITIALIZE
POWER
STEP =
EXECUTE
SELECT MEMORY DISPLAY
SELECT MEMORY ENTER
SELECT ACCUMULATOR 3"
SELECT ACCUMULATOR A
DATA SWITCH ZERO (SSI)
DATA SWITCH ONE (SS2)
DATA SWITCH TWO
DATA SWITCH THREE
DATA SWITCH FOUR see
DATA SWITCH FIVE
DATA SWITCH SEVEN
PROGRAM COUNTER BIT EIGHT
PROGRAM COUNTER BIT NINE
PROGRAM COUNTER BIT TEN— ———
PROGRAM COUNTER BIT ELEVEN
FIGURE 5-1
CONTROL
SWITCHES
I a
DATA SWITCHES
REGISTER
SELECT
SWITCHES
OGRAM
COUNTER
“
A
DATA
SWITCHES
FOR ENTRY OF
UPPER FOUR BITS
OF PR
rt
LA
FO
o
+
EL
CONTROL PANEL SWITCH LOCATOR
All register and memory entry or display must be
performed in the step mode. All switches except
step and data entry switches zero and one, which are
used as sense switches, are interlocked so they have
no effect in the run mode.
INDICATORS
When any indicator is lit, the associated function
is in the true (1) state. The indicators can display
useful information in the run mode but most can change
too rapidly to be valid. They are therefore discussed in
terms of information displayed in the step mode.
There are 16 indicators on the MICRO 400 control panel.
The eight DB indicators display the contents of the
selected register; A, B, P, or Memory Data. The four
PR indicators display the upper four bits of the P
register in conjunction with the DB indicators dis-
playing the low order eight bits. The PR indicators
are only lit when P is selected for display. The
control conditions OVFL (overflow), Link, Step and Run
are also displayed.
5.
5.
5.
2
REGISTER SELECT
The A, B, P and MD registers can be controlled from
the control panel. The P register is displayed when
the A, B, Memory Enter and Memory Display switches are all
in the off (down) position. The front panel data
switch contents can then be transferred to the P
register by depressing the EXC switch. The A, Bor
Memory Data register can be selected by raising the
respective switch. When the A or B register is selected,
the Contents of that register are displayed. When
Memory ENT or Memory DIS are selected, the contents of
the Memory Data register are displayed. Except for
Memory DIS, the data switch contents can be transferred
to the selected register by depressing the EXC switch.
With Memory DIS selected, the contents of the memory
cell addressed by the program counter will be displayed
by depressing the EXC switch.
~ DATA ENTRY SWITCHES
Eight alternate action switches are used to enter data
into the selected register or into memory. Four addi-
tional switches are associated with the upper 4-bits
of the P register. Data Entry Switches zero and one also
serve as sense switches in the RUN and instruction STEP modes.
MEMORY SELECT
The contents of memory can be displayed or altered from
the front panel. The address of the memory location is
5-4
5.4
loaded into the P register. When ENT is selected and
the EXC switch is depressed, the contents of P will
be strobed into the memory address (MA) register and the
contents of the eight data switches will be strobed into
the memory data (MD) register and stored in core.
When DIS is selected and the EXC switch is momentarily
depressed, the contents of P are transferred to the MA
register and the memory data contained in that location
are strobed into the MD register and displayed on the
control panel. The STEP switch increments P without
executing instructions as long as either the ENT or
DIS memory switch is selected, therefore when successive
addresses are to be displayed or altered, the STEP
switch can be used.
STEP
When the computer is in step mode and neither the
memory or register select switches are selected,
depressing the step switch will cause the next
instruction (as addressed by P register) to be
executed.
When the computer is in the run mode, depressing the
Step switch will cause the computer to enter the step
mode.
The Step switch will also perform an increment P if
either the memory DIS or memory ENT switches are
selected. Instructions are not executed in this mode.
RUN
If the memory ENT or DIS switches are not selected
and the computer is in the Step mode, momentarily
depressing the Run switch will cause the computer to
enter the run mode.
INIT (Initialize)
The INIT is functional only in the step mode and is
used to initialize the computer and external devices.
POWER ON/OFF INDICATOR AND SWITCH
The power on/off switch controls the relay that
switches AC to the power supply and AC sequencer.
The power on indicator is lighted by the same 12
VAC that is used to switch the relay when power is
available to the CPU and memory (+5, +12 volts).
5-6
SENSE SWITCHES SS1 AND SS2
The SS1, SS2 and STEP switches are the only switches
active in the RUN mode. In the STEP mode, during
data entry operations, the SS1 and SS2 switches are
data switches bit 0 and 1. In stepping through a
program or in the RUN mode, they are used as sense
switches, and may be interrogated by the SKIP commands to
cause breakpoint or branching of a control program.
If the control panel has been removed, the SSI, $S2
response will always be not set.
‚ О
‚ 1
TELETYPE
Three teletypewriter models are available for use
with the MICRO 400, the ASR 33 TY, KSR 33 and KSR 35,
all of which are capable of speeds up to ten characters
per second. The program can type out characters and
can read in the characters produced when keys are
struck at the keyboard. With an ASR the program can
also punch characters from paper tape.
The teletype is really two distinct devices in that its
input and output functions are separated. When the
program does an output command and places a character
in the teletype controller output buffer, it causes the
teletype to print the character. Striking a key places
the code for the associated character in the controller
input buffer where it can be retrieved by the program,
but it does nothing at the teletype unless the program
sends the code back as an output.
OPERATION
A KSR is actually two independent devices, keyboard and
printer, which can be operated simultaneously. An ASR
is really four devices, keyboard, printer, reader and
punch, which can be operated in various combinations.
Power must be turned on by the operator. On the 33 and
35 the switch is beside the keyboard and is labeled
LINE/OFF/LOCAL or ON/OFF and has an unmarked third
position opposite ON. When this switch 1s set to
6-1
LOCAL or the unmarked position, power is on but the
machine is off line and can be used like a typewriter.
Moreover, in an ASR turning on the punch allows the
operator to punch a tape from the keyboard, and running
the reader allows a tape to control the printer (if
the punch is also on, it duplicates the tape).
Turning the switch to LINE or ON connects the unit to
the computer and separates its input and output functions.
Thus any information transmitted to the computer from
the keyboard affects the printer only insofar as the
computer sends it back. Turning on the reader places
it under program control, and turning on the punch
causes it to punch whatever is sent to the printer by
the computer.
The only control on the reader is a 3-position switch.
When the switch is in the FREE position, the tape can
be moved by hand freely through the reader mechanism.
The STOP position engages the reader clutch so the tape
is stationary but the reader is still off. Turning the
switch to START causes the reader to read the tape if
the unit is in local, but places it under program control
if on line.
The operator controls the punch by means of four push-
buttons. The two on the right turn the punch on and off.
Pressing the REL button releases the tape so it can be
6-2
moved by hand through the punch mechanism. Pressing
B. SP. moves the tape backward one frame so the operator
can delete a frame that is incorrect by striking the
rubout key. Pressing HERE IS with the keyboard in local
punches twenty lines of blank tape (lines with only a
feed hole punched).
The: keyboard resembles that of a standard typewriter.
Codes for printable characters on the upper parts of
‘the key tops on the 33 and 35 are transmitted by using
the shift key; most control codes require use of the
control key. The control key is used for some control
characters, but many have separate keys. Note also that
both the keyboard arrangement and the labels differ
somewhat. On all models the line feed spaces the paper
vertically at six lines to the inch, and must be combined
with a return to start a new line. The local advance
(feed) and return keys affect the printer directly and
do not transmit codes. Appendix E lists the complete
teletype code, ASCII characters, key combinations, and
differences among the several models.
On the 33 and 35 is a repeat button REPT. Pressing
this button and striking any character key causes
transmission of the corresponding code so long as REPT
is held down. Characters that require the shift key
may also. be repeated in this manner, but there 1s no
repetition of control characters.
6-3
Teletype manuals supplied with the equipment give
complete, illustrated descriptions of the procedures
for loading paper and tape, changing the ribbon, and
setting horizontal and vertical tabs. Setting tabs is
usually left for maintenance personnel; in any event,
the best and easiest way to learn how to do any of
these things is to have someone who knows show you
how. However, as a precautionary measure we describe
here the things you may have to do yourself.
TAPE
The tape moves in the reader from back to front with
the feed holes closer to the left edge. To load tape,
set the switch to FREE, release the cover guard by
opening the latch at the right, place the tape so that
the sprocket wheel teeth engage the feed holes, close
the cover guard, and set the switch to STOP.
To load tape in the punch, raise the cover, feed-the
tape manually from the top of the roll into the guide
at the back, move the tape through the punch by turning
the friction wheel, then close the cover. Turn on the
punch with the unit in local and punch about two feet
of leader by pressing HERE IS or the control, shift and
P keys to generate null codes.
6.
‚ 5
PAPER
The 33 printer has an 8-1/2-inch roll of paper at the
back. Printed sections can be torn off against the
edge of the glass window in front of the platen. To
replenish the paper, snap open the cover, remove the
old roll and slip a new one in its place. Draw the
paper from the roll around the platen as in an ordinary
typewriter.
The 35 printer has a sprocket feed and uses 8-1/2 X 11
fanfold form paper. The supply is held in a tray at
the back. To replenish it, first remove the upper
cover by pressing the cover release button on the right
side. To free the remaining old paper for removal, lift
the paper guides by pushing the handle marked PUSH at
the right of the platen. To insert new paper from the
tray, bring it up below the platen at the rear, line
up the holes at the edges of the paper with the sprockets,
and press line feed (in local) to draw the paper under
the platen.
RIBBON
Replace the ribbon whenever it becomes worn or frayed
or the printing becomes too light. Disengage the old
ribbon from the ribbon guides on either side of the
type block, and remove the reels by lifting the spring
clips on the reel spindles and pulling the reels off.
Remove the old ribbon from one of the reels and
replace the empty reel on one side of the machine;
install a new recl on the other side. Push down both
reel spindle spring clips to secure the reels. Un-
wind the fresh ribbon from the inside of the supply
reel, over the guide roller, through the two guides
on either side of the type block, out around the other
guide roller, and back onto the inside of the takeup
reel. Engage the hook on the end of the ribbon over
the point of the arrow in the hub. Wind a few turns
of the ribbon to make sure that the reversing eyelet
has been wound onto the spool. Make sure the ribbon 1s
seated properly and feeds correctly in operation.
TELETYPE OUTPUT
An output to the teletype requires only one transfer
instruction. This command will transfer the contents
of either accumulator and also initiates the printing
of the character. The device code address 1s 00 and
no control codes are used.
DOB TTY, TRANSFER DATA OUT OF B TO TELETYPE
BYTE ONE BYTE TWO
oc 1 0 1 1 HO 0 ÿ 0 0 O
5 4 3 2 1 0 7
6.
If Byte One bit two were a zero, the contents of
A would be transferred and the mnemonic would be
DOA TTY. If the punch is on, the character will be
printed and also punched on tape.
The Model 33 and 35 can type or punch up to ten
characters per second. After the DOB or DOA command,
the program must send the next character 9.09 milli-
seconds later to maintain maximum rate.
TELETYPE INPUT
Reception from the keyboard requires no initiating
action by the program; striking a key transmits the
code for the character serially into the input buffer
of the teletype controller and sets the Reader Ready
flag. However, under program control, a start reader code
may be transmitted to the teletype to start reading paper
tape. This will cause the reader to start moving the tape to
read all eight channels from the next line on tape and
transmit the line serially into the buffer. (The
presence of a hole in the tape produces a one in the
buffer.) When the character is brought into an accumulator,
tape channel 1 corresponds to bit position zero.
DIB TTY, DATA TRANSFER INTO B FROM THE TELETYPE
BYIE ONE BYTE TWO
O 1 0 1 0 1 1 AO 0 0 ÿ 0 0 0 O
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
6.
If byte one bit two were a zero, the accumulator A
would be selected.
SKIP IF TELETYPE READER READY IS SET (SRS)
BYTE ONE BYTE TWO
0 0 1 0 0
A
Y O
Two choices of Reader Ready test may be made, ready
or not ready. If byte one bit zero is a zero the
skip condition would be NOT READY. The Skip if Reader
Ready command will cause a program skip if a character
1s in the teletype buffer. The Transfer in of this
character will clear the reader ready flag in the
controller.
SKIP IF TELETYPE WRITE READY IS SET (SWS)
BYTE ONE BYTE TWO
0 1 0 0 1 0 1 0 0 0 0 1 0 0 O
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Two choices of Writer Ready test may be made, ready or
not ready. If Byte one bit zero is a zero the skip
condition would be not ready. The Skip if Writer Ready
command will cause a skip if the teletype is ready to
accept an output of data to the printer and punch.
7.
0
DIRECT MEMORY ACCESS (DMA)
The maximum rate for data transfers between external
devices and core memory could be no greater than 77,000
words per second if the transfers were executed under
program control. To allow data transfer rates up to
625,000 words per second, a Direct Memory Access (DMA)
Channel is available as an option. The DMA option
makes a channel available through which data can be
transferred automatically using one processor eycle
(1.6us) per word. At data rates lower than 625,000
words per second, the DMA channel frees processor time
to allow execution of a program sequenced with data
transfers for a device.
The program cannot affect the DMA channel because there
are no instructions for it; instead, the program sets
up the device (via the input/output bus) to use the
channel. Then, when the device requires data service,
it requests access to the memory via the DMA request
line. At the beginning of every memory cycle, the
processor synchronizes and recognizes any requests
for memory access that are being made. This assures
no more than 1.6 microseconds wait for DMA and as
long as the DMA request remains true, every memory
cycle is available.
7-1
The device requesting DMA service must supply the
necessary control signals as well as address to the
memory unit. As an option for the MICRO 400 the
Block Automatic Transfer (BAT) is available to
simplify use of the DMA channel. The BAT supplies
control and sequences the memory address for all
standard peripheral devices using the DMA channel.
The following data is presented for a better understand-
ing of how the DMA channel operates and as design data
for the systems engineer. See Appendix D for specific
connector layout and pin listings.
DMA INTERFACE
The DMA option conditions certain control functions and
upper address lines. The I/O board is required to allow
transfers of address and data through it.
ADLD: The Address Load Enable is used to gate
the address bits 00-07 through the I/O
Interface to the memory.
DMRQ -: The DMA Request Line is used to request
a DMA cycle. DMRQ- cannot be issued until
the response DMRS is not busy.
DMRS -:: The DMA Response Line is used to determine
if the DMA is in use.
DMMS :
DMCR :
DAIG:
DMIS:
DMOS:
The DMA Memory Start is used to initiate
the memory cycle. DMMS strobes the address
in the address register on its leading edge.
The DMA Clear Write is used when a transfer
into memory is desired.
The Data In Gate is used to gate the data
bits 00 ——» 07 through the I/O interface.
The Data in Strobe is used to strobe the
data bits 00 —# 07 into the memory data
register.
The Data Out Strobe is used to gate the
data bits 00 —® 07 from the memory data
register through the I/O interface to the
external device.
EBO0O-—»EBO7: The I/O data bus is used to transfer
address bits 00 —e 07 to the memory address
register and transfer data bits 00 ——» 07
to/from the memory data register.
DMO 8 —#DM15: The DMA address bits 08 —» 15 are
transferred as follows: Bits 08 —® 11 are
transferred to the memory and bits 12 — 15
are transferred to the Base Register Module
to select which 4K module the DMA cycle is
for.
. 2
‚д.
START DMA CYCLE
Check if DMA 1s being used (DMRS will be high if not
in use). If DMRS is high, a DMA request (Lower DMRQ)
can be made. DMRS will go low when the CPU has accep-
ted the DMRQ, There 1s a maximum of 1.6 microseconds
and a minimum of "O'" microseconds from DMRQ to DMRS.
Address load (ADLD) must precede memory start (DMMS)
by 50 nanoseconds minimum and anything greater than
50 nanoseconds is acceptable. During ADLD place the
address of the memory location that is to be accessed
on the Address Bus (DMO8 ——» DM15) (Most Significant
8 bits) and the I/O Data Bus (EBOO ——# EB07) (Least
Significant 8 bits).
DMMS can be applied from 50 nanoseconds minimum to
300 nanoseconds maximum after the DMRS. If this is
not followed, time will be lost since the DMA total
cycle will take longer than 1.6 microseconds.
Transfer Into Memory
If the transfer is into the memory the clear write
flag (DMCR) must be issued and be stabilized by 300
nanoseconds maximum after the leading edge of DMMS
and remain stable for 1 microsecond.
The data to be stored into the memory must be placed
on the Data Bus (EBOO — e EB07) during DAIG which is
500 nanoseconds maximum after the leading edge of DMMS
and must be removed by 1.3 Microseconds after the leading
edge of DMMS, DAIG is 400 nanoseconds wide. DAIG- is
7-4
‚д.
‚2.
issued 200 nanoseconds maximum after the leading edge
of DAIG and is used to direct set the data into the memory
data register. DMIS must be 100 nanoseconds minimum
wide and must be totally windowed by DAIG - with 100
nanoseconds minimum margin from the trailing edge.
Transfer Out Of Memory
Data from the memory data register is gated to the
data bus (EBOO ep EBO7) by the data from memory
enable (DMOS). The leading edge of DMOS must be a
minimum of 500 nanoseconds from the leading edge of
DMMS and DMOS must be removed by 1.3 microseconds from
the leading edge of DMMS. The data at the external
device will be stable 100 nanoseconds after the leading
edge of DMOS and during the rest of DMOS.
Single or Additional DMA Cycles
If a single DMA cycle is desired DMRQ must be removed
by 1.1 microseconds after the leading edge of DMMS.
If additional DMA cycles are desired DMRQ is held low.
7-5
7.3.
7.3.
7.3.
7.3.
DMA CYCLE
The DMA cycle requires the following operations.
See Figure B-4.
Check if DMA is being used (DMRS will be high if not
in use). If so, make a DMA request (Lower DMRQ).
Detect that the CPU is waiting to perform a DMA cycle
(DMRS will go low).
Put the address of the memory location that is to be
accessed on the Address Bus (Most Significant 8 bits)
and the Data Bus (Lease Significant 8 bits).
At least 300 nanoseconds after 7.3.2 apply a memory
start pulse (DMMS) which has a duration of 100 nano-
seconds minimum (200 nanoseconds maximum).
The clear write flag (DMCR) must be stablized by
300 nanoseconds maximum after the leading edge of
DMMS and remain stable for one microsecond.
If data is to be stored into the memory, it must be
put on the Data Bus during DAIG which is 500 nano-
seconds maximum after the leading edge of DMMS and
removed before starting a new memory cycle.
If a clear write cycle (store cycle) is being execu-
ted, the data to memory strobe (DMIS) must be sent
100 nanoseconds minimum (200 nanoseconds maximum)
after the leading edge of DMMS. It must be 100 nano-
seconds wide minimum; 200 nanoseconds maximum.
7-6
7.3.10
Data from the memory is gated to the data bus (DBOO--
DBO7) by the data from memory enable (DMOS), 500
nanoseconds from the leading edge of DMMS. The data
at the external device will be stable 100 nanoseconds
after the leading edge of DMOS.
If an additional DMA cycle is desired, start at 7.2.3.
If no additional DMA cycles are desired, release the
DMRQ signal 1.2 microseconds after the last DMMS.
The data from memory will remain on the D-bus as long
as DMOS is present. Therefore, DMOS must be removed
before the next memory address is required.
CENTRAL PROCESSOR
HJ-6 DMA CONNECTOR
DMO 8
PERIPHERAL DEVICE
DMO 9
HIGH ORDER EIGHT
DM10
ADDRESS LINES
DM11
(LOW ORDER 8
DM12
ADDRESS LINES ARE
DM1 5
EBOO-EBO7 IN THE
DM14
I/0 BUS)
DM15
ADDRESS LOAD
ADLD
DMA REQUEST
DMRQ
CPU ACKNOWLEDGE
DMRS
MEMORY START
DMMS
CLEAR WRITE
DMCR
DATA TO MEMORY STROBE
DMIS
DATA FROM MEMORY ENABLE
DMOS
DATA TO MEMORY ENABLE
DAIG
— 5% 6 £2 76 Z Eb &
CENTRAL PROCESSOR
HJ-5 I/0 BUS CONNECTOR
STANDARD |
1/0 BUS
FIGURE 7-1
DMA BUS AND STANDARD 1/0 BUS RELATIONSHIP
7-8
nanoseconds | b | |
to 500 1000 1600
50ns min. — + Lee
ADLD
DMMS 20025 as max] | | |
write | |
DMCR read | stable
DMOS — - —!
DAIG u * — I.
DMIS LU
DMRQ | 4—— 1.115 ——| о
DMRS Must remove DMRQ by this
time if only one DMA cycle
—| 4+—0 min. is desired.
4—1.6us max.
NOTE: Signals are shown ground true as they appear on
the I/0 bus.
FIGURE B-4
DMA CYCLE TIMING
7-9
APPENDIX A
INSTRUCTION LISTING
MICRO 4020 INSTRUCTION LISTING
ARITHMETIC —-————-——-———-—-——-———— — 0 A0 rrr rere ee
DESCRIPTION x LINK/
OVERFLOW
ADD
SUSTRACT
AND
INCLUSIVE OR
EXCLUSIVE OR
LEFT SHIFT
RIGHT SHIFT
COMPLEMENT
INCREMENT
DECREMENT
COPY
CLEAR
SET
L INK
MNEMONIC
ABA
AAB
SBA
SAA
NBA
NAB
OBA
CAB
XBA
LSA
LSB
RSA
RSB
RRA
RRB
OCA
OCB
TCA
TCB
I AA
I AB
IBB
DAA
DAB
DBB
CAB
CBA
CLA
CLB
PDA
POB
MOA
MOB
CLL
LCB
INSTRUCTION FORMAT:
OF CODE
12
29
14
ce
1E
3B
ed
9D
¿D
11
DA
1F
3F
DE
er
2 В
24
сб
34
16
31
Se
19
21
0e
39
zB
21
B6
17
D 7
18
98
BE
50
ADD В TI A
ADD A T9 В
SUBTRACT B FROM A TO A
UBTRACT A FROM В TO A
AND B WITH A TO A
AND A WITH B TO 3
INCLUSIVE OR B WITH A TO À
INCLUSIVE OR A WITH 8 TO B
EXCLUSIVE OR B WITH A TO A
LEFT SHIFT A ONE BITs INSERT w
LEFT SHIFT B ONE BITs INSERT 4
RIGHT SHIFT A ONE BITs INSERT 3
RIGHT SHIFT B ONE BIT sINSERT 3
RIGHT ROTATE A ONE BIT
RIGHT ROTATE B ONE BIT
ONES COMPLEMENT
ONES COMPLEMENT
TWOS COMPLEMENT
TWOS COMPLEMENT
Ww > W >
INCREMENT
INCREMENT
INCREMENT
BY
BY
BY
TO
TO
TO
нон
О =С КЕ МЕ МТ
D=CREMENT
D=CREMENT
TO
TO
TO
BY
BY
BY
UD>D> W>>
per
TUD WO
CIPY A INTO B
COPY В INTO A
CLEAR A TO ZERO
CLEAR B TO ZERO
PISITIVE ONE TO A
POSITIVE ONE TO B
MINUS ONE TO A
MINUS ONE TO B
CLEAR LINK BIT TO ZERO
SET LINK BIT AND CLEAR 56
XXX
* NOTE — AFFECT ON LINK/OVERF LOW BITS
S - LINK ALWAYS SET
R - LINK ALWAYS RESET
A - LINK AFFECTED (MAY 3E SIT OR RESET) AND
OVERFLOW MAY BE SET
A
A
x = > >
Ai
{ > >
>>> >>> >>00 |
nw хх
A DX 0
nD
MICRO 429 INSTRUCTION LISTING
aller EE mms SEES gue SEES queje E a io e CU Suge SER age i que TENS ARES AE SU O слышим es A. E A GES ERNE EES Emel E: mes Gi SE A Ue ido eo de EEE Ee — —w 5 EEE
MEMORY REFERENCE
MNE MONI C OP CODE DESCRIPTION
LDA xx X LIAD A FROM MEMORY
LDB xx X*X LOAD В FROM MEMORY
STA XX xx STORE A INTO MEMORY
STB % % *X STORE B INTO MEMORY
INSTRUCTION FORMAT: XXX ADDR (DIRECT ADDRESSING)
: XXX 31AS»X (>M) (INDEXED)
WHERE: ADDR IS A 1z BIT ADDRESS OF OPERAND IN 4K PAGE
2 BIAS IS AN & BIT VALUE (3-255) WHICH IS ADDED
TO THE SELECTED INDEX REGISTER TO FORM
THE OPERAND ADDRESS
: Хх IS '"4' OR *21 AND SELECTS DISIRED INDEX
: M (OPTIONAL) INDEX MODIFIER
21° INCREMENT INDEX BY 1
'D* DECREMENT INDEX BY 1
BIT FORMAT JF UPPER BYTE OF INSTRUCTIONS?
INSTRUCTION DIRECT INDEXED
BIT 7654 3218 7654 3218
LDA 1999 AAAA 311M MBX
LDB 1021 AAAA 811M M31X
STA 1018 AAAA 311M M10X
STB 1911 AAAA 311M M11X
WHERE: A 15 UPPER 4 BITS OF 1z BIT ADDRESS
2 MM IS INDEX MODIFIER
22 — NO CHANGE TO INDEX
#1 - DECREMENT SELECTED INDEX BY ONE
18 - INCREMENT SELECTED INDEX BY ONE
2 X IS INDEX SELECTION BIT
à —- USE INDEX REGISTER 1 (X1)
1 —-— USE INDEX REGISTER Z (X2)
DETAIL LOAD/STORE INSTRUCTION FORMATS
A-REGISTER FORMATS E-REGISTER FORMATS
MNEMONIC OPERAND O? CODE MNEMINIC OPERAND OP CODE
.DA ADDR 8X XX L DB A DDR - XX
LDA BIAS»1 68 XX LDB BIASs1 6 XX
СОА BIASsZ2 61 XX LDB BIASs2 63 XX
L DA BIAS»1»D 68 XX LDB BIASs1sD 6A XX
LDA BIASsZ2sD 69 XX LDB BIASsZ2sD 6B XX
LDA BIAS ,1sl 70 XX L DB BIAS sis! 72 XX
LDA BIAS 22] 71 XX L DB BIASsZ2s 1 73 XX
STA ADDR AX XX STE ADDR 3X XX
STA BIAS»1 64 XX STB BIASs1 66 XX
STA BIAS»2 65 XX STE BIAS»£2 57 XX
STA BIAS»1sD 6C XX STB В1А4 5, 1, 0 6E XX
STA BIASsZ2sD ED XX STB BIASsZsD 6F XX
STA BIASsliol 74 XX STB BIASs1s 1 76 XX
STA BIASsZ2s1 75 XX STB BIASsZs 1 77 XX
MICRO 488 INSTRUCTION LISTING
SKIPS nn
D=SCRIPTION
MNE MONIC OP CODE
SAP 48 31
SAE 48 22
Saz 48 34
SIN 48 38
SBP 48 13
SBE 48 28
SBZ 48 43
SUN 46 89
SAM 49 31
SAO 49 BZ
SAN 49 34
535 49 28
SBM 49 12
SBO 49 29
SBN 49 42
SLS 49 82
SIN ЧА 31
SSN ЧА BZ
SRN GA a4
S WN 4A 28
Sii GA 18
501 UA 28
SN1 UA 43
SNZ 4A 8p
SIS UB 31
555 4B 22
SRS 45 34
SWS UB 28
512 UB 18
502 ЧВ 23
551 4B 43
552 48 89
INSTRUCTION FORMAT:
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIF
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
SKIP
XXX
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
A POSITIVE (OR ZERO)
A IS EVEN
A IS ZERO
OVERFLOW NOT SET
3 POSITIVE (COR ZERO)
3 IS EVEN
3 IS ZERO
LINK NOT SET
A IS MINUS
A IS OCD
A 15 NOT ZERO
OVERFLOW IS SET
3 IS MINUS
3 1S OLD
3 IS NOT ZERO
LINK IS SET
INTERRUPT-ENABLE NOT SET
SENSE RESPONSE NOT SET
TTY READ READY NOT SET
TTY WRITE READY NOJT SIT
X1L=8 9 INCREMENT X1 EY 1x
X1lL=3s DECR=MENT Xi BY 1x
SENSE SWITCH 1 NOT SET
SENSE SWITCH 2 NOT SET
INTERRUPT-ENABLE IS SET
SENSE RESPONSE IS SET
TTY READ READY IS SET
TTY WRITE RZADY 13 SET
X2L=Bs INCREMENT XZ BY 1x
X2L=0s DECREMENT X2 EY 1x
SENSE SWITCH 1 IS SET
SENSE SWITCH 2 IS SET
NOTE — IF THE SKIP CONDITION IS TRUE» THE FOLLOWING
TWO 3YTES WILL BE
SK IPPEDe
* NOTE — THE SKIP CONDITION IS TESTED PRIOR TO THE
INCREMENTING OR DECREMENTINGe
DECREMENTING OCCURS WHETHER THE LOWER BYTE OF THE
INDEX IS ZERO OR NOTe
THE INCKEMENTING OR
MICRO 498 INSTRUCTION LISTING
GENERAL SKIPS--—--——————2 0 C0 CS Sa rr ce rere rer me ce cr — ee mee €
MNEMONIC OP CODE
SNZ ug XX
SNO 49 XX
SMZ ЧА XX
SMO 4B XX
INSTRUCTION FORMAT:
D=SCRIPTION
SKIP IF ALL OF THE SELECTED
N-GROUP CONDITIONS ARE ZERO
SKIP IF ANY OF THE SELECT =D
N-GROUP CONDITIONS IS ONE»
SKIP IF ALL OF THE SELECTED
M-GROUP CONDITIONS ARE ZEROe
SKIP IF ANY OF THz SELECTED
M-GROUP CONDITIONS IS ONE»
XXX LIT
WHERE: LIT IS AN 8 BIT LITERAL CONDITION MASK
N-GROUP CONDI TIONS
M-GROUP CONDITIONS
(I
IT SOURCE
0 MOST SIGNIFICANT BIT OF A
1 LEAST SIGNIFICANT BIT OF A
г ZERO IF A ZERO
3 OVERFLOW
4 MOST SIGNIFICANT BIT OF B
5 LEAST SIGNIFICANT BIT OF 3
6 ZERO IF B ZERO
7 LINK
IT SOURCE
0 INTERRUPTS ENABLED FLIP-FLOP
1 SENSE RESPONSE FLIP-FLOP
z TTY READ READY
3 TTY WRITE READY
4 SEE INSTRUCTIONS SI1» SI2
5 SEE INSTRUCTIONS 501» 502
6 ZERO IF SENSE SWITCH 1 SET
7 ZERO IF SENSE SWITCH 2 SET
JUMPS ----———— o rr rr mm rrr re rr mm 0 0 0 mmm ma
MNE MONIC OP CODE
JPC CX XX
JPE DX XX
JMC EX XX
JME FX XX
INSTRUCTION FORMAT:
WHE RE 2
D=SCRIPTION
JUMP WITHIN CURRENT 4K PAGE
JIJMP TO EXTENDED 4K PAGE x
JUMP & MARK IN CURRENT 4K PAGE
JUMP & MARK TO EXTENDED 4K PAGE *
XXX ADDR
ADDR 1S 12 BIT ADDRESS IN 4K PAGE
x NOTE — EXTENDED JUMPS ENABLE BASE REGISTER ADDRESSING
AND TOGGLE THE BASE REGISTER SELECTION PRIOR
TO THE JUMP UNLESS PRECEDED BY AN 'EBL' OR 'LEB?
INSTRUCTION.
MICRO 488 INSTRUCTION LISTING
INP UT / OUT PUT mm mm mm mm mm mee eee ee ee eee CCS н--
MNE MONI C
SEN
EXC
DIA
DIA
DIB
DOB
INSTRUCTION FORMAT:
OP CODE
58
51
52
53
56
57
XX
XX
XX
XX
XX
XX
DESCRIPTION
SENSE
EXTERNAL CONTROL
DATA INPUT INTO A
DATA OUTPUT FROM A
DATA INPUT INTO 3
DATA OUTPUT FROM B
XXX FD
WHERE: F IS A 3 BIT FUNCTION CODE
®° DIS A 5 BIT DEVICE ADDRESS
CONTROL === mmm mm mm re ee ee ee ee o o
MEMORY MODIF Y/SKIP—-—————— —— — = 000 000 D ee ce
OP CODE
SKIP
SHIFT MEMORY
MNE MONI C
HLT
SIF
ROF
EIN
DIN
NOP
SSF
RSF
INSTRUCTION FORMAT:
MNEMONIC
SER
SOR
SPM
SMM
RCS
RCZ
RCO
RCA
INSTRUCTION FORMAT:
OP CODE
29
4d
ai
42
43
45
46
47
58
59
SA
58
5C
5D
DE
SF
XX
XX
XX
XX
XX
XX
XX
XX
DESCRIPTION
HALT
S=T OVERFLOW FLIP-FLOP
RESET OVERFLOW FLIP-FLOP
ENABLE INTERRUPTS
DISABLE INTERRUPTS
NJ OPERATION
SIT SENSE FLIP-FLOP
R=SET SENSE FLIP-FLOP
XXX
— dr Lo EE EE TY
DESCRIPTION
SKIP IF EVENs ROTATE MEMORY *
SKIP IF ODDs ROTATE MEMORY *
SKIP IF POSITIVE MEMORY
SKIP IF MINUS MEMORY
RIGHT SHIFT» COPY SENSE
RIGHT SHIFT» COPY ZERO
RIGHT SHIFTs COPY ONE
RIGHT SHIFT s COPY LEAST
SIGNIFICANT BIT OF A
XXX AD DK
WHERE: ADDR IS AN 8 BIT ADDRESS OF THE FIRST 256
BYTES OF THE CURRENT 4K PAGE
NOTE — THE MEMORY WORD IS CIRCULARLY ROTATED TO
THE RIGHT ONE BIT POSITIONe THE SKIP CONDITION IS
TESTED PRIOR TO MEMORY ROTATIONe ROTATION WILL TAKE
PLACE REGARDLESS OF WHETHER THE SKIP CONDITION IS
TRUE OR FALSE
A-5
MICRO 43P INSTRUCTION LISTING
SPECIAL BASE-REGISTER/INDEX INSTRUCTIONS -----——- A
© MNEMONIC OP CODE CISCRIPTION
TRANSFER TRA * HHH TRANSFER 3YTE BETWEEN CPU AND BRM
INSTRUCTION FORMAT: TA Sab
WHERE: S IS THE MNEMONIC FOR ThE SOURCE REGISTER
e D IS THE MNEMONIC FOR THE DESTINATION REGISTER
NOTZ - S AND D MUST BE FROM DIFFERENT MNEMONIC SETS
(SEE PELOW)
BIT FORMAT OF TRANSFER CTRA) INSTRUCTIONS:
FIRST BYTE SECOND BYTE
BIT 7654 3219 7654 32139
TRA 30191 BALD HRN3 1410
WHERE: A IS ACCUMULATOR SELECTION
(9=A ACCUMULATORs 1=5 ACCUMULATOR )
D 1S DIRECTION JF TRANSFER
(3=BRM TO CPU», 1=CPU TO BKM )
H IS REGISTER HALF SELECTION
(3=LOWER 8 BITSs 1=UPPER & BITS )
X 15 REGISTER TYPE SELECTION
(3=BASE REGISTERs 1=INDEX REGISTER)
N IS REGISTER NUMBER
(3= X1 OR Els 1= X2 OR Bz )
DETAIL TRANSFER INSTRUCTION FORMATS
A-RZGISTER FORMATS B-REGISTER FORMATS
MNEMONIC OPERANL OP CODE MNEMONIC OPERAND OP CODE
TRA X1L9A 22 ЧА TRA X1L »B 26 HA
TRA X2L sA 52 6A TRA XZL sB 26 6A
TRA X1U sA 52 CA TRA X1U 93 26 CA
TRA X2U 9A 52 EA TRA X CU #8 56 EA
TRA A 9X1L 23 HA TRA BsX1iL 57 GA
TRA A 9X2L 23 6A TRA BsX2L 57 6A
TRA À sX1U 53 CA TRA BsX1U 57 CA
TRA As X2U 53 EA TRA BsX2U 57 EA
TRA B1iL sA 52 VA TRA BiL sB 56 DA
TRA B2L sA 52 ¿A TRA BZL »B 26 ZA
TRA B1U»A 52 ВА TA B1U »B 26 8A
TRA B2U sA 52 AA TRA B ZU »B 26 AA
TRA A »B1L 53 BA TRA BsB1L 27 VA
TRA AsB2L 53 ZA TA BsB2L 27 ZA
TRA AsB1U 53 G&A TRA B »61U 57 8A
TRA AsB2U 53 AA TRA Ba 52U 27 AA
MICRO 448 INSTRUCTION LISTING
SPECIAL BASE REGISTER/INDEX INSTRUCTIONS - (CCONTINUED)----------=----—=-
MNEMONIC OP CODE DESCRIPTION
CLEAR CLR xx xx CLEAR BRM REGISTER TO ZERO
INSTRUCTION FORMAT: CLR REG
WHERE: REG IS A BRM MNEMONIC (SEE BELOW)
BIT FORMAT OF CLEAR (CLR) INSTRUCTIONS:
FIRST BYTE SECOND BYTE
BIT 7654 3218 7654 3218
CLR 0191 2201 HRN3 1210
WHERE: H 1$ REGISTER HALF SELECTION
(8=LOWER 8 BITSs 1=UPPER 8 BITS )
R IS REGISTER TYPE SELECTION
(9=BASE REGISTERs 1=INDEX REGISTER)
N IS REGISTER NUMBER
(2= X1 OR Bis 1= X2 OR BZ )
BRM MNEMONICS (BASE-REGISTER/INDEX MODULE)
'X1U "XL" INDEX 1
'X2U? 'XzL" INDEX 2
'B1U? 'B1L' BASE 1
'B2U' 'BzL! BASE 2
DETAIL CLEAR INSTRUCTION FORMATS
MNEMONIC OPERAND OP CODE DESCRIPTION
CLR ва 51 ВА CLEAR BASE 1 LOWER TO ZERO
CLR B2L 51 ZA CLEAR BASE 2 LOWER TO ZERO
CLR XiL 51 4A CLEAR INDEX 1 LOWER TO ZERO
CLR XaL 51 6A CLEAR INDEX Z LOWER TO ZERO
CLR BAU 51 8A CLEAR BASE 1 UPPER TO ZERO
CLR B2U 51 AA CLEAR BASE 2 UPPER TO ZERO
CLR X1U 51 CA CLEAR INDEX 1 UPPER TO ZERO
CLR — X2U 51 EA CLEAR INDEX 2 UPPER TO ZERO
MICRO 483 INSTRUCTION LISTING
SPECIAL BASE REGISTER/INDEX INSTRUCTIONS — (CONTINUED) cm mr mm ee
DESCRIPTION
MNEMONI C
SET sB1
SLE
SEL
SEM
LEB
EBL
NOTE - THE
EXTENDED JUMP
INSTRUCTION FORMAT:
x NOTE - ‘LEB?
‘EBL?
OP CODE
50
59
58
59
51
51
2A
GA
8A
88
28
4B
SET SENSE
SET SENSE
SIT SENSE
SIT SENSE
SIT "LEB®
SET *EBL'
IF
IF
IF
IF
x
*
BASE 1 NOT ENABL =D
'LEB? SET
'EBL' SET
IN EXTENDED MEMORY
'EBL' COMMAND ALSO INHIBITS THE NEXT
(JME »JPE) FROM TOGGLING THE
BASE REGISTER SELECTIONe
XXX
IS LOWER CORE TO EXTENDED 3ASE FLIP-FLOP
IS EXTENDED BASE TO LOWER COXE FLIP-FLOP
INSTRUCTION TIMING=—— =m mre mm rr mr me rm rr re er me mmm mmm So Se me ——
FUNCTION
ARITHMETIC
CLEAR REGISTER
CONTROL
INPUT
JUMP
JUMP MARK
LOAD/STORE DIRECT
LOAD/STORE
OUTPUT
SHIFT
SKIP
INDEXED
MEMORY MODIFY/SKIP
TRANSFER REGISTER
(BRM)
(BRM)
TIME (CYCLE)
NANe-=eNUNUUEZNNRPEN”
(1 CYCLE EQUALS 1e6 MICROSECONDS)
(4 IF SKIP OCCURS)
(3 IF SKIP OCCURS)
MICRO 488 INSTRUCTIONS MNEMONIC SEQUENCE
INSTRUCTION
AAB
ABA
CAB
CBA
CLA
CLB
CLL
CLR B1L
CLR B2L
CLR X1L
CLR X2L
CLR В1 4
CLR B2U
CLR X1U
CLR X ZU
DAA
DAB
DBB
DIA FD
D IB F sD
DIN
DIA F sD
DOB F sD
E3L
EIN
EXC F sD
HLT
IAA
IAB
IBB
JMC ADDR
JME ADDR
JPC ADDR
JPE ADDR
LCB
LDA ADDR
LDA BIASs1
LDA BIAS»2
L DA BIASs1sD
LDA BIASs2sD
LDA BIASs1s1
СОА
BIASs 2s1
09
12
39
28
ci
06
DE
21
21
51
51
51
51
51
51
18
21
De
52
56
43
53
57
51
42
51
08
OP CODE
ВА
2A
4A
6A
8A
AA
CA
EA
XX
XX
XX
XX
48
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
DESCRIPTION
ADD A TO B
ADD 3 TO A
COPY A INTO B
COPY B INTO A
CLEAR A TO ZERO
CLEAR B TO ZERO
CLEAR LINK BIT TO ZERO
CLEAR BASE 1 LOWER TO ZERO
CLEAR BASE 2 LOWER TO ZERO
CLEAR INDEX 1 LOWER TO ZERO
CLEAR INDEX Z LOWER TO ZERO
CLEAR BASE 1 UPPER TO ZERO
CLEAR BASE 2 UPPER TO ZERO
CLEAR INDEX 1 UPPER TO ZERO
CLEAR INDEX Z UPPER TO ZERO
DECREMENT A BY 1 TO
DECREMENT A BY 1 TO
DECREMENT B BY 1 TO
DATA INPUT INTO A
DATA INPUT INTO 3
DISABLE INTERRUPTS
DATA
0
UTPUT FROM A
DATA OUTPUT FROM B
SET
ENABL
E
*EBL?
INTERRUPTS
EXTERNAL CONTROL
HALT
INCREMENT
A BY 1 TO
INCREMENT A BY 1 TO
INCREMENT B BY 1 TO
A
B
B
A
B
B
JUMP £ MARK IN CURRENT UK PAGE
JUMP & MARK TO EXTENDED 4K PAGE
JUMP WITHIN CURRENT UK PAGE
JUMP TO EXTENDED 4K PAGE
SIT LINK BIT AND CLZAR B
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
> >> >> >>
FROM MEMORY
INDEXED BY X1
INDEXED BY X2
INDEXED BY X1
INDEXED BY X2
INDEXED BY X1
INDEXED BY X2
DECRIMENT X1
DECR=MENT Xz
INCREMENT X1
INCREMENT Xz
MICRI 488 INSTRUCTIONS MNEMONIC SEQUENCE
INSTRUCTION
LDB
LDB
LDB
LDB
LDB
LDB
LIB
LEB
LSA
LSB:
MOA
MOB
NAB
NBA
NOP
OAB
OBA
OCA
OCB
POA
POB
RCA
RCO
RCS
RCZ
ROF
RRA
RRB
RSA
RSB
RSF
SAA
SAE
SAM
SAN
SAO
SAP
SAZ
SBA
SBE
SBM
ADDR
BIAS»1
BIASsZ
BIAS»1sD
BIASs2sD
BIAS is
BIASs 22
ADDR
ADDR
ADDR
A DDR
9X
62
65
EA
EB
72
73
51
11
ЙА
18
28
3B
1E
45
BD
29
a
94
17
07
OP CODE
XX
XX
XX
XX
XX
XX
XX
28
XX
XX
XX
B82
gi
ay
Be
31
94
20
10
DESCRIPTION
LOAD B FROM MEMORY
LOAD B INDEXED BY X1
LOAD B INDEXED BY XZ
LOAD 3 INDEXED BY X1 DECRZMENT X1
LOAD B INDEXED BY X2 DECRZMENT Xe
LOAD 3 INDEXED BY X1 INCREMENT Xi
LOAD 3 INDEXED BY X2 INCR=McNT Xz
SET LEB?
LZFT SHIFT A ONE 31Ts INSERT В
LEFT SHIFT В
MINUS ONE TO
MINUS ONE TO
AND A WITH
AND B WITH
NO OPERATION
INCLUSIVE OR
INCLUSIVE OR
ONES COMPLEM
ONES COMPLEM
POSITIVE ONE
POSITIVE ONE
RIGHT SHIFT,
SIGNIFICANT
RIGHT SHIFT,
RIGHT SHIFT»
RIGHT SHIFT,
RESET OVERFL
RIGHT ROTATE
RIGHT ROTATE
RIGHT SHIFT
RIGHT SHIFT
RESET SENSE
SUBTRACT A
SKIP IF A
SKIP IF A
SKIP IF A
SKIP IF A
SKIP IF A
SKIP IF A
SUBTRACT B
SKIP IF В
SKIP IF B
0 >
TO B
TO A
> ©
A WITH B
B WITH A
ENT A
ENT B
TO A
To B
COPY LEAST
BIT OF A
COPY ONE
COPY SENSE
COPY ZERO
OW FLIP-FLOP
A ONE BIT
B ON= BIT
A ONE BITs
B ONE BITs
FLIP-FLOP
FROM B TO
IS EVEN
IS MINUS
IS NOT ZERO
IS OCD
POSITIVE (OR
IS ZERO
FROM A TO
IS EVEN
IS MINUS
ONE BITs INSERT B
TO B
TO A
INSERT Y
INSERT ©
ZERO)
A-10
INSTRUCTION
S3N
530
SIP
S3Z
581
501
502
SEL
SEM
SEN
SIR
SIN
SIS
sn
512
SLE
SLN
SLS
SMM
SMO
SMZ
SNO
SNZ
SN1
SNZ
SOF
SON
SOR
5925
SPM
SRN
SRS
SSF
SSN
SSS
551
552
MICRI 42% INSTRUCTIONS MNEMONIC SEQUENCE
F sD
ADDR
ADDR
LIT
LIT
LIT
LIT
ADDR
ADDR
49
49
48
48
Эй
ЧА
4g
Эй
58
Эй
58
ЧА
4B
4A
48
50
48
49
58
4B
UA
49
48
ЧА
ЧА
40
48
59
49
SA
GA
48
46
4A
4B
4B
4B
IP CODE
49
20
19
Ча
CA
28
28
8A
8B
XX
XX
01
21
18
13
GA
82
82
XX
XX
XX
XX
XX
Чо
80
98
XX
28
XX
24
au
97
Be
43
80
DESCRIPTION
SKIP IF 8 IS NOT ZERO
SKIP IF B IS OLD
SKIP IF 8 POSITIVE (OR ZERO)
SKIP IF 3 IS ZERO
SET SENSE IF BASE 1 NOT ENABLED
SKIP IF X1L=8s DECREMENT X1 BY 1
SKIP IF X2L=0s DECRZMENT X2 BY 1
SET SENSE IF 'EBL! SET
SET SENSE IF IN EXTENDED MEMORY
SENSE
SKIP IF EVENs ROTATZ MEMORY
SKIP IF INTERRUPT-ENABLE NOT SET
SKIP IF INTERRUPT-ENASLE IS SET
SKIP IF X1L=2, INCREMENT X1 BY 1
SXIP IF X2L=3s INCREMENT XZ BY 1
ET SENSE IF "LEG! SET
SKIP IF LINK NOT SET
SKIP IF LINK IS SET
SKIP IF MINUS MEMORY
SKIP IF ANY OF THE SELECTED
M-GROUP CONDITIONS IS ONE
SKIP IF ALL OF THE SELECTED
M-GROUP CONDITIONS ARE ZERO
SKIP IF ANY OF THE SELECTED
N-GROUP CONDITIONS IS ONE
SKIP IF ALL OF THE SELECTED
N-GROUP CONDITIONS ARE ZERO
SKIP IF SENSE SWITCH 1 NOT SET
SKIP IF SENSE SWITCH 2 NOT 3ET
SET OVERFLOW FLIP-FLOP
SKIP IF OVERFLOW NOT SET
SKIP IF 0DDs ROTATE MEMORY
SKIP IF OVERFLOW IS SET
SKIP IF POSITIVE MEMORY
SKIP IF TTY READ READY NOT SET
SKIP IF TTY READ READY IS SET
SET SENSE FLIP-FLOP
SKIP IF SENSE RESPONSE NOT SET
SKIP IF SENSE RESPONSE IS SET
SKIP IF SENSE SWITCH 1 IS SET
SKIP IF SENSE SWITCH 2 IS SET
MICRO 438 INSTRUCTIONS MNEMONIC SEQUENCE
INSTRUCTION
STA ADDR
STA BIASs1
STA BIASsZ
STA BIAS»1sD
STA BIAS 23D
STA BIAS is]
STA BIASs Zo
STB A DDR
STB BIASs1
STB BIAS»e
STB BIASs1sD
STB BIASs2sD
STB BIASs1sl
STB BIAS»Zsl
SWN
SWS
TCA
TCB
TRA X1L sA
TRA X2L2A
TRA X1U sA
TRA X2U » À
TRA AsX1L
TRA AsX2L
TRA A sX1U
TRA A »X2U
TRA X1L»B
TRA X2L 928
TRA X1U »B
TRA X 2U »B
TRA BsX1iL
TRA Ba X2L
TRA B X1U
TRA BsX2U
TRA BiL sA
TRA B2L sA
TRA B1UsA
TRA B2UsA
TRA A »B1L
TRA AsBel
TRA AsB1U
TRA A sB 2U
TRA B1L»B
TRA B 2L »B
TRA BiUsB
TRA B 2U »B
TRA BsB1L
TRA BsB2L
TRA BsB1U
TRA BsB2U
XBA
AX
64
65
6C
6D
74
75
BX
66
67
6E
6F
76
77
4A
4B
26
34
52
52
52
52
53
53
55
53
56
56
56
56
57
57
57
57
52
52
52
52
23
23
23
53
56
56
56
56
57
57
57
57
2D
oP CODE
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
98
28
GA
6A
CA
EA
4A
6A
CA
EA
4A
6A
CA
EA
GA
6A
CA
EA
BA
2A
8A
AA
DA
2A
8A
AA
BA
2A
8A
AA
BA
2A
8A
AA
DESCRIP
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
STORE
ооо юр > > > > => >
TWIS COMPLEMENT
TWOS COMPLEMENT
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TION
INTO MEMORY
INDEXED
INDEXED
INDEXED
INDEXED
INDE XED
INDE XE D
BY X1
BY Xe
BY X1
BY X2
BY X1
BY X2
INTO MEMORY
INDEXED
INDEXED
BY X1
BY X2
INDEXED BY X1
INDEXED
INDEXED
BY X2
BY X1
INDEXED BY X2 INC
TTY WRITE READY NOT SET
TTY WRITE READY IS SET
x1L TO
X2L TO
X1U TO
x2U TO
A TO X1L
A TO XeL
A TO XiU
A TO X2U
X1L TO B
x2L TO B
x1U TO B
x2U TO B
B TO X1L
E TO X2L
B TO X1U
B TO X2U
BiL TO A
B2L TO A
B1U TO A
B2U TO A
A TO BiL
A TO B2L
A TO B1U
A TO B2U
BiL TO B
B2L TO B
B1U TO B
B2U TO B
& TO BÎL
B TO B2L
B TO BiU
B TO B2U
> > > > >
EXCLUSIVE OR B
DECREMENT
DECREMENT
INCREMENT
INCREMENT
DECRIZMENT
DECRZMENT
INCREMENT
INCREMENT
WITH A TO A
A-12
X1
Xz
x1
Xe
MICRI 488 INSTRUCTIONS OP CODE SEQUENCE
INSTRUCTION OP CODE DESCRIPTION
HLT 20 HALT
DAB 91 DECREMENT A BY 1 TO B
UBB Oe DECREMENT B BY 1 TO B
OCB 94 ONES COMPLEMENT 3
CLB 06 CLEAR В TO ZERO
PIB 97 POSITIVE ONE TO 3
MOB 98 MINUS ONE TO B
AAB 99 AD A TO B
LSB ВА L=FT SHIFT В ONZ BITs INSERT В
OAB 9D INCLUSIVE OR A WITH В TO B
CLL ВЕ CLEAR LINK BIT TO ZERO
RRA BF RIGHT ROTATE A ONE BIT
DAA 10 DECREMENT A BY 1 TO A
LSA 11 LEFT SHIFT A ONZ BIT, INSERT 8
ABA 12 ADD B TO A
SBA 14 SUBTRACT B FROM A TO A
IAA 16 INCREMENT A BY 1 TO A
POA 17 POSITIVE ONE TO A
MOA 18 MINUS ONE TO A
NBA 1E AND 3 WITH A TO A
RSA | 1F RIGHT SHIFT A ONE BIT, INSERT 8
OCA a ONES COMPLEMENT A
CLA 21 CLEAR A TO ZERO
SAA 22 SUBTRACT A FROM 3 TO A
TCA c6 TWO'S COMPLEMENT A
OBA 29 INCLUSIVE OR В WITH A TO A
CBA 2B COPY B INTO A
XBA 2D EXCLUSIVE OR B WITH A TO A
RRB er RIGHT ROTATE B ONE BIT
LCB 30 SET LINK BIT AND CLZAR B
IAB 31 INCREMENT A BY 1 TO B
IBB 32 INCREMENT В BY 1 То В
TCB 34 TWO'S COMPLEMENT B
CAB 39 COPY A INTO B
NAB SB AND A WITH B TO B
RSB SF RIGHT SHIFT В ONE BITs INSERT Y
SOF 49 SET OVERFLOW FLIP-FLOP
ROF 41 RESET OVERFLOW FLIP-FLOP
EIN 42 ENABLE INTERRUPTS
DIN 43 DISABLE INTERRUPTS
NOP 45 NO OPERATION
SSF 46 SET SENSE FLIP-FLOP
RSF 47 RESET SENSE FLIP-FLOP
A-13
MICRD 488 INSTRUCTIONS OP CIDE SEQUENCE
INSTRUCTION OP CODE DESCRIPTION
SAP 48 81 SKIP IF A POSITIVE COR ZERO)
SAE 48 Be SKIP IF A IS EVEN
SAZ 48 B4 SKIP IF A IS ZERO
SON 48 08 SKIP IF OVERFLOW NOT SET
SBP 48 10 SKIP IF B POSITIVE (OR ZERO)
SBE 48 28 SKIP IF B IS EVEN
SBZ 48 4p SKIP IF B IS ZERO
SLN 48 89 SKIP IF LINK NOT SET
SNZ LIT 48 XX SKIP IF ALL OF THE SELECTED
N-GROUP CONDITIONS ARE ZERO
SAM 49 81 SKIP IF A IS MINUS
SAO 49 82 SKIP IF A IS ODD
SAN 49 84 SKIP IF A IS NOT ZERO
595 49 08 SKIP IF OVERFLOW IS SET
SBM 49 10 SKIP IF B IS MINUS
sBO 49 23 SKIP IF В IS 000
SBN 49 4p SKIP IF В 15 NOT ZERO
SLS 49 89 SKIP IF LINK IS SET
SNO LIT 49 XX SKIP IF ANY OF THz SELECTED
N-GROUP CONDITIONS IS ONE
SIN ЧА 81 SKIP IF INTERRUPT-ENABLE NOT SET
SSN ЧА 02 SKIP IF SENSE RESPONSE NOT SET
SRN GA 84 SKIP IF TTY READ READY NOT SET
SKN 4A 38 SKIP IF TTY WRITE READY NOT SET
511 ЧА 19 SKIP IF X1L=Pps INCREMENT X1 BY 1
501 4A 20 SKIP IF X1L=8, DESRZMENT X1 BY 1
SN1 4A 49 SKIP IF SENSE SWITCH 1 NOT SET
SNe 4A 80 SKIP IF SENSE SWITCH 2 NOT SET
SMZ LIT ЧА XX SKIP IF ALL OF THZ SELECTED
M-GROUP CONDITIONS ARE ZERO
SIS 48 81 SKIP IF INTERRUPT-ENABLE IS SET
SSS 48 BZ SKIP IF SENSE RESPONSE IS SET
SRS 48 04 SKIP IF TTY READ READY IS ScT
SWS 48 98 SKIP IF TTY WRITE READY IS SET
S12 4B 19 SKIP IF X2L=Bs INCREMENT X2 EY 1
502 4B 20 SKIP IF X2L=@s DECRZMENT X2 BY 1
551 4B 4p SKIP IF SENSE SWITCH 1 IS SET
552 48 88 SKIP IF SENSE SWITCH 2 IS SET
S MO LIT 48 XX SKIP IF ANY OF THz SELECTED
M-GROUP CONDITIONS IS ONE
531 58 2A SIT SENSE IF BASE 1 NOT ENABLED
SLE 50 UA SET SENSE IF '"LEB' SET
SEL 58 8A SET SENSE IF '"EBL' SET
SEM 29 8B SET SENSE IF IN EXTENDED MEMORY
SEN Е „0 58 XX S=NSE
A-14
MICRO 48% INSTRUCTIONS OP CODE SEQUENCE
INSTRUCTION
CLR BL
CLR B2L
LEB
CLR XiL
EBL
CLR X2L
CLR B1U
CLR B2U
CLR Xiu
CLR X ZU
EXC F sD
TRA BAL »А
TRA B2L sA
TRA XI1LsA
TRA X2L sA
TRA BiUsA
TRA B2UsA
TRA X1UsA
TRA X2U9A
DIA F sD
TRA AsB1L
TRA AsBe2lL
TRA A X1L
TRA AsX2L
TRA A sB1U
TRA 'AsB?U
TRA AsX1U
TRA AsX2U
DOA F sD
TRA Bil sB
TRA B2LsB
TRA X1L »B
TRA X2L »B
TRA BiUsB
TRA B2U sB
TRA X1U »B
TRA X ZU »B
DIB F sD
TRA BsB1L
TRA BsB2L
TRA BaX1L
TRA BsX2L
TRA BsB1U
TRA BsB2U
TRA B X1U
TRA BaX2U
DOB F 9D
51
51
51
51
51
51
51
51
51
51
51
52
52
52
OP CODE
BA
CA
2B
UA
4B
6A
8A
AA
CA
EA
XX
BA
2A
ЧА
6A
8A
AA
CA
EA
XX
BA
СА
ЧА
6A
8A
AA
CA
EA
XX
BA
CA
GA
6A
8A
AA
CA
EA
XX
BA
2A
4A
6A
8A
AA
CA
EA
XX
DESCRIPTION
CLEAR BASE 1 LOWER TO ZERO
CLEAR BASE 2 LOWER TO ZERO
SET "LEB®
CLEAR INDEX
SET EBL?
CLZAR INDEX 2 LOWER TO ZERO
CLEAR BASE 1 UPPER TO ZERO
CLEAR BASE 2 UPPER TO ZERO
1 LOWER
TO ZERO
CLEAR INDEX 1 UPPER TO ZERO
CLEAR INDEX 2 UPPER TO ZERO
EXTERNAL
TRANSF ER
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
CONT
BL
B2L
X1L
X2L
BLU
B 2U
X1U
Xx QU
DATA INPUT IN
TRANSF ER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TO
TO
TO
TO
TO
TO
TO
TO
> > > > > > > >
ROL
TO
TO
TO
TO
TO
TO
TO
TO
TO
>> >>> >>> >
B1L
B2L
X1L
XZL
B1U
BeU
X1U
X2U
DATA OUTPUT FROM
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
TRANSFER
Bil
B2L
X1L
X2L
B1U
B2U
X1U
X ZU
DATA INPUT IN
TRANSF ER
TRANSF ER
TRANSFER
TRANSFER
TRANSF ER
TRANSFER
TRANSFER
TRANSFER
DATA OUTPUT FROM B
TO
TO
TO
TO
TO
TO
TO
TO
OO Own U
TO
TO
TO
TO
TO
TO
TO
TO
TO
ооо о 0
B1L
B2L
XiL
XZL
B1U
B2U
X1U
XZU
o
A-15
MICRO 43D INSTRUCTIONS OP CODE SEQUENCE
INSTRUCTION OP CODE DESCRIPTION
S=R ADDR 58 XX SKIP IF EVENs ROTATE MEMORY
SOR ADDR 59 XX SKIP IF ODDs ROTAT= MEMORY
SPM A DDR 5A XX SKIP IF POSITIVE MEMORY
SMM ADDR 58 XX SKIP IF MINUS MEMORY
RCS ADDR 5C XX RIGHT SHIFT» COPY SENSE
REZ ADDR SD XX RIGHT SHIFT, COPY ZERO
RCO ADDR 5E XX RIGHT SHIFT, COPY ONE
RCA ADDR 5F XX RIGHT SHIFTs COPY LEAST
SIGNIFICANT BIT OF A
LDA BIASs1 68 XX LOAD A INDEXED BY X1
LDA BIASsZ 61 XX LOAD A INDEXED BY X2
LDB BIAS»1 62 XX LOAD 8 INDEXED BY X1
LDB BIASsZ 65 XX LOAD В INDEXED BY X2
STA BIASs1 64 XX STORE A INDEXED BY X1
STA BIAS»2 65 XX STORE A INDEXED BY Xe
STB BIAS,1 66 XX STORE B INDEXED BY X1
STB BIAS»2 67 XX STORE В INDEXED BY X2
L DA BIASs1sD 68 XX LOAD A INDEXED BY X1 DETRIMENT Xi
LDA BIASs2sD 69 XX LOAD A INDEXED BY X2 DECRZMENT Xz
LDB BIASs1sD 6A XX LOAD В INDEXED BY X1 DECRZMENT X1
LDB BIASs2sD 6B XX LOAD B INDEXED BY X2 DECR=MENT Xz
STA BIASs1s0 6C XX STORE A INDEXED BY Xi DECRZMENT X1
STA BIASs2sD 6D XX STORE A INDEXED BY X2 DECR:MENT Xz
STB BIASs1sD 6E XX STORE В INDEXED BY Xi DECRZMENT Xi
STB BIASs2sD 6F XX STORE В INDEXED BY X2 DECREMENT Xe
LDA BIASsis1 78 XX LOAD: A INDEXED BY X1 INCREMENT X1
LDA BIASsZ2s1 71 XX LOAD. A INDEXED BY X2 INCREMENT X&
LDB BIASslsl 72 XX LOAD $8 INDEXED BY X1 INCR=MENT X1
LDB BIASs2s1 73 XX LOAD В INDEXED BY X2 INCREMENT Xc
STA BIAS 12] 74 XX STORE A INDEXED BY X1 INCREMENT X1
STA BIAS»2,I 72 XX STORE A INDEXED BY X2 INCREMENT Xz
STB В1А5»1 о 1 76 XX STORE B INDEXED BY X1 INCREMENT Xi
STB BIAS 2.1 77 XX STORE B INDEXED BY X2 INCREMENT Xz
LDA ADDR BX XX LOAD A FROM MEMORY
LDB ADDR 9X XX LOAD B FROM MEMORY
STA ADDR AX XX STORE A INTO MEMORY
STB ADDR BX XX STORE B INTO MEMORY
JPC ADDR CX XX JUMP WITHIN CURRENT 4K PAGE
JPE ADDR DX XX JUMP TO EXTENDED ЧК PAGE
JMC ADDR EX XX JUMP & MARK IN CURRENT ЧК PAGE
JME ADDR FX XX JUMP & MARK TO EXTENDED 4K PAGE
A-16
APPENDIX B
1/0 INTERFACE
APPENDIX B
INTRODUCTION
This document describes the Micro 400 I/0 Interface
and its operation, timing diagrams are given to
assist in understanding it.
INPUT/OUTPUT BUS
The Micro 400 communicates with peripheral device
options on a word parallel I/O bus as shown in
Figures B-2 and B-3.
Information exchanges with peripheral devices are
normally synchronized and sequenced by a peripheral
device controller. For discussion in this manual, a
peripheral device option includes not only the device
but the controller which is necessary to the operation
of that device.
The standard I/O bus consists of the E-bus, the I-bus,
the C-bus and five control lines: I/0 Enable (IOEN),
I/O Strobe (IOST), Initialize (INIT), Interrupt (IREQ),
and Interrupt Acknowledge (IACK).
FUNCTIONAL DESCRIPTION
INTERFACE DEFINITION
Signal Buses
E-Bus: an 8-bit bidirectional data bus that is used
to transfer data to or from the controller.
The E-bus is active only during IOEN.
C-Bus: an 8-bit unidirection bus that is used to trans-
fer the device address CBOO + CBO4 and function
code information CBOS + CB07 contained in the
instruction being executed to the controller.
The contents of the C-bus are meaningful only
during the time of IOEN.
F-Bus: a 2-bit unidirection bus that is used to
transfer the command states data input trans-
fer, data output transfer, execute, and sense
information contained in the instruction being
executed to the controller. The contents of the
F-bus are meaningful only during the time of.
IOEN.
2
‚1.
‚1.
‚1.
2
4
Control Lines
IOEN:
IOST:
INIT:
CLCK:
The I/0 enable signal is 800 nanoseconds wide
and is used as a window during which time
typical controller action takes place. All
other time periods are indeterminate.
The I/0 strobe signal is 100 nanoseconds wide
and occurs 600 nanoseconds after the start of
IOEN. It is used as follows:
a. Data on the E-bus to the controller is
strobed into storage registers on the
trailing edge of IOST.
b. Data on the E-bus from the controller is
strobed into the CPU on the leading edge
of IOST.
c. An indication that the sense response has
been sampled.
d. Execution of external control functions
should be accomplished with IOST.
The initialize signal is used to reset the
controllers connected to the 1/0. It is
activated by the front panel reset switch
or other options which control reset.
A 5 MHz, 50% duty cycle, clock useful for
timing and setting control functions in the
controller. The phase relationship to IOEN
is always the same.
Priority Line
PROT:
Priority out line. A Low (0V) level which
indicates that the first controller attached
can make an interrupt or BATIO request.
Interrupt Lines
IREQ: :
IACK::
Interrupt Request line. A Low (0V) indicates
an interrupt request is being made. It is
conditioned in the controller by the priority
chain and a interrupt enable/disable flip-flop.
Interrupt Acknowledge line. A Low (OV)
indicates an interrupt acknowledge is being
made and that the controller should place its
device address times 2 on the E-bus.
2.
I/0 COMMAND TIMING DESCRIPTION
The MICRO 400 I/O structure provides four basic types
of I/0 commands for control of peripheral device
options. These are:
a. Data Input Transfer
b. Data Output Transfer
C. External Control
d. Sense
As can be seen by examination of the 1/0 timing diagram
in Figure 2.1, all input/output operations occur in the
same manner and have identical timing diagrams.
The following paragraphs discuss the operations asso-
ciated with each command type.
NOTE: Logic levels as discussed in the following sections
are as they appear on the bus. The bus is ground
true, + 5 false.
Data Input Transfer
The timing diagram in Figure B-1 can be used to under-
stand the basic transfer of data into the MICRO 400
from an external device. When a DIA (or DIB) is executed
the MICRO 400 begins to communicate with the addressed
controller at time Ty.
At To the C-bus is driven by the MICRO 400 with the
portion of the DIA command word that contains device
address (CBOO + CBO4) and control code (CBO5 = CBO7)
information.
At To time the I-bus (IBOO, IBO1) is driven with the
portion of the DIA command word that defines that this
is to be a command, in this instance IBOO will be true
and IBO1 will be false.
At To the IOEN signal is driven and alerts the addressed
device controller to place data on the E-bus.
From time To to Tg00 the E-bus is driven by the ad-
dressed device controller with the data to be trans-
ferred to the MICRO 400. It must be stable by time
1600-
At Tego > T 700 IOST is driven. In the case of DIA,
the IOST informs the external device that the incoming
data has been sampled. Thus it may be used for any
housekeeping chore required by the peripheral device
controller. B-3
TT
6 7
0 0
0 00
v | и
IOEN «<—800ns ——»
—
+ 600ns —' :
| 1051 —| 4-100ns
le > E-Bus, C-Bus and F-Bus enabled.
7 Data from controller is strobed
into CPU register.
Data from CPU register is strobed
into controller storage.
NOTE: Logic levels shown are as they appear on the
I/0 bus. Ground true, +5 false.
FIGURE B-1
‚д.
‚2.
2
At Tggp the E-bus, I-bus, C-bus, .and IOEN are removed
from the I/0 bus.
Date Output Transfer
The timing diagram in Figure B-1 can be used to under-
stand the basic transfer of data out of the MICRO 400
and to a peripheral device controller. Assume that
this is a DOA from register A, and that it already
contains the data we intend to transfer out. When a
DOA (or DOB) is executed the MICRO 400 begins to commu-
nicate with addressed controller at time To.
At To the C-bus is driven with the portion of the DOA
command word that contains device address (CBOO > CBO4)
and control code (CBO5 + CBO7) information.
At lg time the I-bus (IBOO, IBO1) is driven with the
portion of the DOA command word that defines that this
is to be a command, in this instance IBOO will be false
and IBOl will be false.
At To the IOEN signal is driven and alerts the addressed
device controller to prepare to accept the data on the
E-bus.
At T, the E-bus is driven with the data contained in
register A.
At T IOST is driven. In the case of DOA,
> 170
the ТО т shé8%4a be used to strobe the data on the E-bus
into a holding register in the peripheral device controller.
Ât Tgop the E-bus, F-bus, C-bus, and IOEN are removed
from the I/O bus.
External Control (EXC)
The timing diagram in Figure B-1 can be used to under-
stand the basic external control command sequence.
The EXC will cause a prescribed action to take place
inside the peripheral device controller or possibly
an action inside the peripheral device; i.e., read
cards, rewind tape, write EOF, etc.
At Tg the C-bus is driven with the portion of the
EXC command word that contains device address
(CBOO + CBO4) and control code (CBOS + CB07)
information.
2.
2.
At To time the F-bus (FBOO, FBO1) is driven with the
portion of the EXC command word that defines that this
is to be a command, in this instance FBOO is false and
FBO1 is true.
At To the IOEN signal is driven and alerts the addressed
controller to interrogate the C-bus for control codes.
No action on the E-bus should occur during the EXC.
At T600 > T IOST is driven. In the case of EXC,
it may be used to strobe the external code generated
by the decode of CBO5, CBO6, and CBO7 during IOEN time.
At Tang the C-bus, F-bus, and IOEN are removed from
the 1/0 bus.
Sense (SEN)
The timing diagram in Figure B-I can be used to under-
stand the basic Sense command sequence. The SEN command
will cause a signal from the controlier to be inter-
rogated. The condition status will cause EBOO to be
driven and the MICRO 400 to respond accordingly.
At Tg the C-bus is driven with the portion of the SEN
command word that contains device address (CBOO + CBO4)
and control code (CBOS + CB07) information
At To time the F-bus (FBOO, FBO1) is driven with the
portion of the SEN command word that defines that this
is to be a command, in this instance FBOO is true and
FBOl is true.
At To the IOEN signal is driven and alerts the ad-
dressed controller to interrogate the condition and
drive the signal EBOO accordingly.
At To the E-bus is enabled but the only action that
should occur on the E-bus during the SEN 1s the
condition on EBOO placed there by the peripheral device.
At T600 + T7090 IOST is driven. In the case of SEN,
the ÍOST serves no specific purpose in the device
controller. It may be used for any housekeeping chore
required by the device controller.
At Tg00 the E-bus, C-bus, F-bus and IOEN are removed
from the I/O bus.
B-6
CENTRAL PROCESSOR
Bi-Directional
Data Bus
Uni-Directional
Function Bus
Uni-Directional
Device Code Bus
External Interrupt
Termination Voltage
Termination Ground
Clock
Initialize
Interrupt Acknowledge
Priority Out
EB00
PERIPHERAL DEVICE CONTROLLER
EBO1
EB02
EB03
EB04
EBOS
EB06
EB07
FB00
FBO1
IOEN
IOST
CBOO
‚4434 444411441
CBO1
CBO2
CBOS
CBO4
CBOS
CBOG
CBO7
444144414}
IREQ
e
TVCC
TGRD
CLCK
INIT
IACK
PROT
Y Y Y Y Y y
FIGURE B-2
STANDARD INPUT/OUTPUT DATA BUS
B-7
BYTE ONE BYTE TWO
—p CB01 Device Address bit one
»CB02 Device Address bit two
—»CB03 Device Address bit three
bCBO4 Device Address hit four
—»CBOS Control hit one
_pCB06 Control bit two
—»CB097 Control bit three
IINSTRUC| CON- DEVICE
lo 101 O TTON TROL| ADDRESS ACCUMULATOR
76543 10765473210 6543210
~ — }
EROO 1/0 data bit zero
O
= | EBO1 1/0 data bit one
с сл EBO2 1/0 data bit two
3 tri
= > —< > EBO3 1/0 data bit three
< a — «> ЕВ04 1/0 data bit four
О
9 = _¢—» EBOS 1/0 data hit five
= = —«—» EBO6 1/0 data hit six
= —«» ЕВ07 1/0 data hit seven
>|
o
A —» CB00 Device Address bit zero
>
O
>.
to
$ -Я qUNDIA
—»I1B00 Instruction bit zero
»IB0O1 Instruction bit one
Input/Output instruction and accumulator relationship to the Input/Output bus.
Logic levels appearing on the bus will be ground true(le ground =
( +
гл
И
2.
2.
‚4.
4.
PRIORITY DETERMINATION
Relative priority 1s determined by a hardwired priority
chain consisting of the Priority IN (PRIN) and Priority
Out (PROT) lines. This priority chain determines the
priority for interrupt and Block Automatic transfer
1/0 (BATIO). Before a controller can make an interrupt
or BATIO request, it must receive priority from the next
higher priority controller on the chain in the form of
a ground signal on the PRIN line. A Low PRIN (OV)
indicates the controller can make a request. If the
controller does not make a request, it makes PROT Low
(OV). PROT is Low (OV) from the I/0 board.
INTERRUPT
Interrupt Request
Interrupt request (IREQ) is conditioned by three terms:
(a) the interrupt enable/disable flip-flop in the
controller, (b) the priority in (PRIN) in the con-
troller, and (c) the interrupt enable/disable flip-flop
in the CPU. If both the CPU and controller interrupt
flip-flop are enabled and PRIN is low, a controller
can make IREQ low and it will receive the Interrupt
Acknowledge within a maximum of 4 3/4 cycles (7.6 usec).
Interrupt Acknowledge
When the interrupt acknowledge (IACK) is received it
indicates that the CPU is making an instruction fetch at
memory locations hex 00 and hex 01 unless modified by
the controller address. When the controller receives
IACK 1t places its device address times 2 on the
E-bus during the entire time of IACK. This action will
modify the memory locations that the instruction is
being fetched from. For example, if the controller
device address is hex 08 the two memory locations fetched
will be hex 10 and hex 11. This interrupt location
contains a jump and mark instruction which will provide
the exit to the interrupt routine and provide for the
return to the normal program.
Interrupt Timing
Conditions: CPU and controller interrupt enable flip-
flops are set.
PRIN
IREQ — ; -
a 7! DELAY MAX. 7.6 us, MIN. 1.2 usec
IACK _ |
nly LA — Lo ÇA
400ns Yoons”
CONTROLLER PLACES |+ > 0 us —— |
DEVICE ADDRESS X2
ON E-BUS DURING
THIS TIME FIGURE B-4
NOTE: Logic levels shown are as they appear on the I/O
bus. Ground true, + 5 volts false.
CBO1
CB02— 9 DEVICE ADDRESS#
DEVICE ADDRESS DECODE
(ABC) Control Code
(ABC) Control Code
(ABC) Control Code 0
CBOS (ABC) Control Code 1
(ABC) Control Code 2
1 OF 8 —
CBO6 | (ABC) Control Code 3
DECODER —
(ABC) Control Code 4
‚CB07 (ABC) Control Code 5
6
7
CONTROL CODE DECODE
The IB00 and IBOl signals as they appear on the 1/0
Bus produce the following equations (ground true).
I BOO --1B00 + TBOT = Data Transfer In
1 OF 4 TBOO . ТВОТ = Data Transfer Out
I BO1 DECODER - [B00 - IBO] = Sense
TIBOO - IBO1 = External Control
COMMAND CODE DECODE
*The device address is a predetermined binary code and the detecting
gate structure must be connected for proper decoding.
FIGURE B-7
BASIC CONTROLLER DECODING
B-11
DISCRETE RECEIVER CIRCUIT
+5VDC +12VDC
100 ohm 1Kohm
INPUT ~~ = Y
2N23
FROM Vs 09%A
1/0 BUS —
— Y TO LOGIC
5.1Kohm
-12VDC
INPUT
FROM
1/0 BUS
This discrete circuit has very desirable noise rejection
characteristics for a long cable run and is recommended
for any cable length exceeding twenty feet.
This cir-
cuit 1s non-inverting.
FIGURE B-8
+SVDC IC RECEIVER CIRCUIT
<
100 ohm
8 C TO LOGIC
— 1 1/6 7404
This receiver circuit is to be used only when the I/0
bus cable length is less than twenty feet. It is an
inverting circuit.
FIGURE B-8
DISCRETE DRIVER CIRCUIT
1
Lo]
OUTPUT DRIVE
A 2N2369A TO 1/0 BUS
LOGIC INPUT
100 ohm | ré
This driver is relatively insensitive to the affects
of cable length and is recommended for cable runs over
twenty feet. The driver inverts the signal into it,
therefore to achieve ground true on the bus the input
must be +5 volt true.
FIGURE B-9
IC DRIVER CIRCUIT
OUT.PUT DRIVE
LOGIC INPUT > {jTo 1/0 BUS
O]
|| —{]
1/2 74451
The IC driver is recommended for cable runs of twenty
feet or less. The IC driver does not invert the signal,
therefore ground true in results in ground true out.
FIGURE B-10
Device Add.|
Ext. Control
I/O Enable
External Control 0
Control Code 0
External Control 1
Control Code 1
External Co ntrol 2
Control Code 2
То
External Control 3
Control Code 3
External Control 4
Control Code 4
ОС
External Control 5
Control Code 5
External Control 6
Control Code 6
|
TT
External Control 7
Control Code 7
FIGURE B-11
EXTERNAL CONTROL COMMAND
Device Address
Sense
I/O Enable
Control Code 0
Condition 0 *
To EB00 Line Driv Control Code 1
(EBOO is interrogated
by the MICRO 400 as
sense response)
Condition 1
Control Code 2
Condition à *
Control Code 3
Condition 3
Control Code 4
Condition 4 +
Control Code 5
Condition 5 *
Control Code 6
Condition 6
Control Code 7
Condition 7 *
These are controller functions to be sensed; i.e. beginning of tape,
ready, not ready, etc.
FIGURE B-12 - SENSE COMMAND
B-15
Device Address
Data Transfer In
\/
1/0 Enable
7” EBOO
Data Bit O
EB01 |
Data Bit 1
EB02 |
Data Bit 2
EB03 ®
Data Bit 3
To 1/0 Bus
Line Drivers <
EB04
Data Bit 4
EB05 ,
Data Bit 5
EB06 +
Data Bit 6
EB07
— Data Bit 7
FIGURE B-13
DATA INPUT COMMAND
B-16
Device Add.
Data Tra
Ц
1/0 Enable. |
1/0 Strobe
From I/O Bus
or
I/O Bus Line
Recelvers as
Logic
Requirements
Dictate
*Note 1: A quad latch holding register is shown.
—]= ьанеаациы
Ne
Y
EBGO
EBO1
_EB02 |
EBO3
EB04
EBO5
EB06
EBOY
FFOO
FFO1
FFO02
FF03
FFO04
FF05
ITIL]
FF06
YY
FEO7
FIGURE B-14
DATA OUTPUT COMMAND
B-17
Ol Ol Ol © Ol © ©! O
Ol
APPENDIX C
LEFT BLANK INTENTIONALLY
APPENDIX D
CONNECTOR LISTING
2A 115 VAC
SB Fuse
115 VAC
Switched 1 0A
Maximum
to 115 VAC
REAR VIEW
Teletype H-77 Oo]
Connector MH —]
DMA
Connector
_|
[UTILITY | [ H-J4 |
Input/Output Utility
Connector
FRONT VIEW
(With Front Panel Removed and
all Intercabling Removed)
dd adi | ны? Hd 99 5
do EN
= 4 E-J2 5
TL
MEMORY BOARD
| J-J1 |
Power
Supply
S1
On/
Off
FIGURE D-1
M400 CPU CONNECTOR LOCATOR
FUNCTION: Connect CPU H-J2 to Front Panel F-J1 & F-J2
NAME: Control Panel Connector
Pin No. Mnemonic Description Pin No. Mnemonic Description
01 АВОЗ - ADDRESS BIT 05 26 АВО! - ADDRESS BIT 01
02 AB00- ADDRESS BIT 00 27 AB02- ADDRESS BIT 02
03 PBO00+ RREG BIT 0 ENABLE TERM 28 PB02+ P REGISTER BIT 02
04 PHAZ- TIMING TERM 29 PB03+ PP REGISTER BIT 03
05 SPARE 30 PB01+ ГР REGISTER BIT 01
06 12 VAC LAMP VOLTAGE 31 12 VAC LAMP VOLTAGE
07 12 VAC LAMP VOLTAGE RETURN 32 12 VAC |LAMP VOLTAGE RETURN
08 GRD GROUND
09 GRD GROUND 33 GRD GROUND
10 +5V +5 VDC 34 GRD GROUND
11 OVFF+ OVERFLOW FLIP-FLOP 35 +5V +5 VDC
12 RUNF- RUN FLIP-FLOP 36 TIM À- TIMING TERM
13 DBO03- DATA BIT 03 37 SPARE
14 SS01 + SENSE SWITCH 01 38 RUNE+ RUN FLIP-FLOP
15 DBO00- DATA BIT 00 39 DB01- DATA BIT O1
16 DB02- DATA BIT 02 40 DB04- DATA BIT 04
17 DPEN- DISPLAY P REG ENABLE 41 DBO05- DATA BIT 05
18 RUNE- RUN FLIP-FLOP 42 SS02+ SENSE SWITCH 02
19 STPE- STEP FLIP-FLOP 43 DBO7- DATA BIT 07
20 MEST - MEMORY ENTER IN STEP 44 DB06- DATA BIT 06
21 LDAD- DISPLAY A ENABLE 45 12 VAC LAMP VOLTAGE
22 LBEN- LOAD B ENABLE 46 CRYF+ CARRY FLIP-FLOP
23 LAEN- LOAD A ENABLE 47 DAIS- IDATA IN STROBE TO MEMORY
24 LDBD- DISPLAY B ENABLE 48 LPUE- LOAD P REG ENABLE
25 RSET - RESET CPU IN STEP 49 DSPF- DISPLAY P REG
50 CLWR- [CLEAR WRITE ENABLE
FIGURE D-2
CPU CONNECTOR H-J2
FUNCTION: Connect CPU H-J3 to Power Supply J-J1
NAME: Power Connector
Pin No. Mnemonic Description Pin No.| Mnemonic Description
01 GRD 26 GRD
02 A 27 A
03 28
04 Logic Ground 29
05 30 Logic Ground
06 31
07 32
08 Y 33 Vv
09 GRD 34 GRD
10 PFSN Power Fail Sense 35 PFSN Power Fail Sense
11 DASV Data Save 36 DASV Data Save
12 +5V 37 +5V
13 +5V 38 +5V
14 +5V 39 +5V
15 +5V Logic Voltage +5 VDC 40 +5V Logic Voltage +5 YDC
16 +5V 41 +5V
17 +5V 42 +5V
18 +5V 43 +5V
19 REMS Remote Switch 44 REMS Remote Switch
20 +12V 45 +12V
21 +12V Memory Voltage +12 VDC 46 +12V Memory Voltage +12 VDC
22 +12V | 47 +12V
23 +12. 6AC Lamp Voltage Return 48 +12. 6 AC} Lamp Voltage Return
24 +12. 6AC Lamp Voltage 49 +12. 6 AC Lamp Voltage
25 -12V Memory Voltage -12 VDC 50 -12V Memory Voltage -12 VDC
Figure D-3
CPU CONNECTOR H-J3, MEMORY CONNECTOR E-J2 & POWER SUPPLY CONNECTOR J-J1
FUNCTION: DIRECT MEMORY ACCESS HJÓ
Pin No. Mnemonic | Description Pin No. Mnemonic Description
01 +5VDC Terminating Voltage 26 SPECIAL
02 +5VDC Terminating Voltage 27 GROUND
03 +5VDC Terminating Voltage 28 DM11 Memory Address Bit ll
04 +5VDC Terminating Voltage 29 GROUND
05 GROUND 30 DM10 Memory Address Bit 10
06 DM15 Memory Address Bit 15 31 GROUND
07 GROUND 32 DMO9 Memory Address Bit 09
08 DM14 Memory Address Bit 14 33 GROUND
09 GROUND 34 DMO 8 Memory Address Bit 08
10 DM13 Memory Address Bit 13 35 GROUND
11 GROUND 36 DMRO DMA Request
12 DM12 Memory Address Bit 12 37 GROUND
13 GROUND 38 DMIS Data to Memory Strobe
14 SPARE 39 GROUND
15 GROUND 40 DMCR Clear Write Enable
16 SPARE 41 GROUND :
17 GROUND 42 DMMS | Memory Start Pulse
18 SPARE. 43 GROUND
19 GROUND 44 DMOS Data From Memory Enable
20 SPARE 45 GROUND
21 GROUND 46 DAIG Data to Memory Enable
22 SPARE 47 GROUND
23 GROUND 48 ADLD Address Load Enable
24 SPECIAL 49 GROUND
25 GROUND 50 DMRS CPU DMA Acknowledge
FIGURE D-4
FUNCTION: INPUT/OUTPUT
Pin No. Mnemonic Description Pin No. Mnemonic Description
01 +5 VOLTS Terminating Voltage 26 [OST 1/0 Strobe
02 +5 VOLTS Terminating Voltage 27 GRND Ground
03 +5 VOLTS Terminating Voltage 28 IOEN 1/0 Enable
04 +5 VOLTS Terminating Voltage 29 GRND Ground
05 ! TACK Interrupt Acknowledge 30 . FBO1 Function Bit 01
06 i GRND Ground 31 ; GRND Ground -
07 ; PROT Priority Out 32 ‚ ЕВОО Function Bit 00 |
08 ; CLCK 5 Mhz Clock 33 . GRND Ground
09 : GRND Ground 34 . EBO7 Data Bus Bit 07 |
10 ' СВО7 Control Bit 3 35 ; GRND Ground |
11 : GRND Ground 36 - EBO6 Data Bus Bit 06 |
12 ' СВОб Control Bit 2 37 ~ GRND Ground |
13 | GRND Ground 38 EBOS Data Bus Bit 05 |
14 - CBOS Control Bit 1 38 ~ GRND Ground |
15 GRND Ground 40 - EBO4 Data Bus Bit 04
16 . CBO4 Device Address Bit 04 4 - GRND Ground
17 GRND Ground 42 . EBO3 Data Bus Bit 03
1 18 - CBO3 Device Address Bit 03 43 GRND Ground
1 19 ; GRND Ground 44 EBO2 Data Bus Bit 02
| 20 : CBO2 Device Address Bit 02 45 GRND Ground
| 21 ‚СЕМ Ground 46 . EBO1 Data Bus Bit 01
|! 22 > CBO1 Device Address Bit 01 47 GRND Ground
123 : GRND Ground 48 EBOO Data Bus Bit 00
| 24 , CBOO Device Address Bit 00 49 ‚СЕ Ground
25 i GRND Ground | 50 IREQ Interrupt Request
| i
Figure D-5
INPUT/OUTPUT CONNECTOR HJ5
FUNCTION; Connect CPU HJ1 to Memory EJ1
NAME: Memory Data Bus Connector
ГР: №. Mnemonic] Description Mnemonic
01 SPARE GRD
02 BRME Special Ext. Address
03 SP13 Special Ext. Address
04 SPARE
05 DASV Data Save
06 BUSY Memory Busy
07 SKL2 Memory Modify
08 SKR1 Memory Modify
09 SKRO Memory Modify
10 DAIS Data In Strobe
11 DAOS Data Out Strobe
12 CLWR Clear Write
13 MSTR Memory Start
14 ABOO Address Bit 8
15 ABO1 Address Bit 9
16 АВО2 Address Bit 10
17 АВО5 Address Bit 11
18 DBOO Data Bit 0,Address Bit 0
19 DBO1 Data Bit 1,Address Bit 1
20 DBO 2 Data Bit 2,Address Bit 2
21 DBOS Data Bit 3,Address Bit 3
22 DBO4 Data Bit 4,Address Bit 4
23 DBOS Data Bit 5,Address Bit 5
24 DBO6 Data Bit 6,Address Bit 6
25 DBO7 Data Bit 7,Address Bit 7 GRD
Figure D-6
CPU CONNECTOR HJ1 AND MEMORY CONNECTOR EJ1
APPENDIX E
CONVERSION TABLES
HEXADECIMAL ARITHMETIC
ADDITION TABLE
] 2 3 4 5 6 7 8 9 A B C D E F
02 03 04 05 06 07 08 09 0A OB oC OD ОЕ ОЕ 10
03 04 05 06 07 08 09 0A OB OC OD OE OF 10 11
04 05 06 07 08 09 0A ОВ OC OD OE OF 10 11 12
05 06 07 08 09 0A 0B OC 0D OE OF 10 11 12 13
06 07 08 09 OA 08 OC OD OE OF 10 11 12 13 14
07 08 09 0A OB OC OD OF OF 10 11 12 13 14 15
08 09 0A ОВ OC oD OF OF 10 11 12 13 14 15 16
09 OA OB OC OD OE OF 10 11 12 13 14 15 16 17
0A ОВ OC OD OF OF 10 11 12 13 14 15 16 17 18
ОВ 0C oD OF OF 10 11 12 13 14 15 16 17 18 19
OC OD OE OF 10 11 12 13 14 15 16 17 18 19 1A
OD OE OF 10 11 12 13 14 15 16 17 18 19 1A 18
ОЕ ОЕ 10 11 12 13 14 15 16 17 18 19 IA 18 IC
OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D
10 11 12 13 14 15 16 17 18 19 1A 18 1C 1D IE
MULTIPLICATION TABLE
2 3 4 5 6 7 8 9 A B C D E F
04 06 08 0A OC ОЕ 10 12 14 16 18 1A 1C 1E
06 09 oC OF 12 15 18 18 IE 21 24 27 2A 2D
08 OC 10 14 18 IC 20 24 28 20 30 34 38 3C
04 OF 14 19 IE 23 28 2D 32 37 3C 41 46 48
OC 12 18 IE 24 284 30 36 3C 42 48 4E 54 5A
OF 15 IC 23 2A 31 38 ЗЕ 46 AD 54 58 62 69
10 18 20 28 30 38 40 48 50 58 60 68 70 78
12 18 24 20 36 3F 48 51 5A 63 6C 75 7E 87
14 IE 28 32 3C 46 50 5A 64 6E 78 82 8C 9%
16 21 20 37 42 4D 58 63 6E 79 84 8F 9A AS
18 24 30 3C 48 54 60 6C 78 84 90 920 AS B4
IA 27 34 4 4E 58 68 75 82 8F 9C A9 B6 C3
IC 2A 38 46 54 62 70 TE 8C 9A — AS B6 c4 D2
1E 2B 3C 48 5A 69 78 87 96 AS B4 C3 D2 El
The table below provides for direct conversions between hexa-
decimal integers in the range O—FFF and decimal integers in
For conversion of larger integers, the
the range 0—4095.
HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE
table values may be added to the following figures:
Hexadecimal fractions may be converted to decimal fractions
as follows:
|. Express the hexadecimal fraction as an integer times
167, where n is the number of significant hexadecimal
Hexadecimal Decimal Hexadecimal Decimal places to the right of the hexadecimal point.
01 000 4 096 20 000 131 072 0. CA9BF3), = CA9 BF3,, x 1676
02 000 8 192 30 000 196 608
03 000 12 288 40 000 262 144 2. Find the decimal equivalent of the hexadecimal integer
04 000 16 384 50 000 327 680
05 000 20 480 60,000 393 216 CA? BF3 13 278 19516
06 000 24 576 70 000 458 752
07 000 28 672 80 000 524 288 3. Multiply the decimal equivalent by 167"
08 000 32 768 70 000 589 824
09 000 36 864 AO 000 655 360 13 278 195
OA 000 40 960 BO 000 720 896 x 596 046 448 x 10-16
ОВ 000 45 056 СО 000 786 432 0.791 442 096, 0)
OC 000 49 152 DO 000 851 968
0D 000 53 248 EO 000 717 504 Decimal fractions may be converted to hexadecimal fractions
OE 000 57 344 FO 000 783 040 by successively multiplying the decimal fraction by 1610:
OF 000 61 440 100 000 1 048 576 After each multiplication, the integer portion is removed to
10 000 65 536 200 000 2 097 152 form a hexadecimal fraction by building to the right of the
11 000 69 632 300 000 3 145 728 hexadecimal point. However, since decimal arithmetic is
12 000 74 728 400 000 4 194 304 used in this conversion, the integer portion of each product
13 000 77 824 500 000 5 242 880 must be converted to hexadecimal numbers.
14 000 81 920 600 000 6 291 456
15 000 86 016 700 000 7 340 032 Example: Convert 0.8951( to its hexadecimal equivalent
16 000 90 112 800 000 8 388 608 a 0.895
17 000 94 208 900 000 9 437 184 |
18 000 98 304 A00 000 10 485 760 DE
19 000 102 400 BOO 000 11 534 336 |
1A 000 106 496 C00 000 12 582 912 51% 20
18 000 110 592 DOO 000 13 631 488
IC 000 114 688 E00 000 14 680 064 Do
1D 000 118 784 FOO 000 15 728 640 /
1E 000 122 880 1 000 000 16 777 216
IF 000 126 976 2.000 000 33 554 432 0.ESTE E 720
0 ] 2 3 4 5 6 7 8 9 A B C D E F
000 | 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015
010 | 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031
020 | 0032 0033 0034 0035 0036 0037 0038 0039 0040 0041 40042 0043 0044 0045 0046 0047
030 | 0048 0049 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 0060 0061 0062 0063
040 | 0064 0065 0066 0067 0068 0069 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079
050 | 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 0090 0091 0092 0093 0094 0095
060 | 0096 0097 0098 0099 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 0110 0111
070 | 0112 0113 0114 0115 0116 0117 0118 0119 0120 0121 0122 0123 0124 0125 0126 0127
080 | 0128 0129 0130 0131 0132 0133 0134 0135 0136 0137 0138 0139 0140 0141 0142 0143
090 | 0144 0145 0146 0147 0148 0149 0150 0151 0152 0153 0154 0155 0156 0157 0158 0159
0А0 | 0160 0161 0162 0163 0164 0165 0166 0167 0168 0169 0170 0171 0172 0173 0174 0175
0BO | 0176 0177 0178 0179 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 0190 019]
OCO | 0192 0193 0194 0195 0196 0197 0198 0199 0200 0201 0202 0203 0204 0205 0206 0207
ODO | 0208 0209 0210 0211 0212 0213 0214 0215 0216 0217 0218 0219 0220 0221 0222 0223
OEO | 0224 0225 0226 0227 0228 0229 0230 0231 0232 0233 0234 0235 0236 0237 0238 0239
OFO | 0240 0241 0242 0243 0244 0245 0246 0247 0248 0249 0250 0251 0252 0253 0254 0255
HEXADECIMAL - DECIMAL INTEGER CONVERSION TABLE (cont. )
0 2 3 4 5 6 7 8 9 A B C D E F
100 | 0256 0257 0258 0259 0260 0261 0262 0263 0264 0265 0266 0267 0268 0269 0270 0271
110 | 0272 0273 0274 0275 0276 0277 0278 0279 0280 0281 0282 0283 0284 0285 0286 0287
120 | 0288 0289 0290 0291 0292 0293 0294 0295 0296 0297 0298 0299 0300 0301 0302 0303
130 | 0304 0305 0306 0307 0308 0309 0310 0311 0312 0313 0314 0315 0316 -0317 0318 0319
140 | 0320 0321 0322 0323 0324 0325 0326 0327 0328 0329 0330 0331 0332 0333 0334 0335
150 | 0336 0337 0338 0339 0340 0341 0342 0343 0344 0345 0346 0347 0348 0349 0350 0351
160 | 0352 0353 0354 0355 0356 0357 0358 0359 0360 0361 0362 0363 0364 0365 0366 0367
170 | 0368 0369 0370 0371 0372 0373 0374 0375 0376 0377 0378 0379 0380 0381 0382 0383
180 | 0384 0385 0386 0387 0388 0389 0390 0391 0392 0393 0394 0395 0396 0397 0398 0399
170 | 0400 0401 0402 0403 0404 0405 0406 0407 0408 0409 0410 0411 0412 0413 0414 0415
IAQ | 0416 0417 0418 0419 0420 0421 0422 0423 0424 0425 0426 0427 0428 0429 0430 0431
180 | 0432 0433 0434 0435 0436 0437 0438 0439 0440 0441 0442 0443 0444 0445 0446 0447
ICO | 0448 0449 0450 0451 0452 0453 0454 0455 0456 0457 0458 0459 0460 0461 0462 0463
100 | 0464 0465 0466 0467 0468 0469 0470 0471 0472 0473 0474 0475 0476 0477 0478 0479
1EO | 0480 0481 0482 0483 0484 0485 0486 0487 0488 0489 0490 049] 0492 0493 0494 0495
\FO 0496 0497 0498 0499 0500 0501 0502 0503 0504 0505 0506 0507 0508 0509 0510 0511
200 | 0512 0513 0514 0515 0516 0517 0518 0519 0520 0521 0522 0523 0524 0525 0526 0527
210 | 0528 0529 0530 0531 0532 0533 0534 0535 0536 0537 0538 0539 0540 0541 0542 0543
220 | 0544 0545 0546 0547 0548 0549 0550 0551 0552 0553 0554 0555 0556 0557 0558 0559
230 | 0560 0561 0562 0563 0564 0565 0566 0567 0568 0569 0570 0571 0572 0573 0574 0575
240 | 0576 0577 0578 0579 0580 0581 0582 0583 0584 0585 0586 0587 0588 0589 0590 0591
250 | 0592 0593 0594 0595 0596 0597 0598 0599 0600 0601 0602 0603 0604 0605 0606 0607
260 | 0608 0609 0610 061] 0612 0613 0614 0615 0616 0617 0618 0619 0620 0621 0622 0623
270 | 0624 0625 0626 0627 0628 0629 0630 063] 0632 0633 0634 0635 0636 0637 0638 0639
280 | 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 0652 0653 0654 0655
290 | 0656 0657 0658 0659 0660 0661 0662 0663 0664 0665 0666 0667 0668 0669 0670 0671
2A0 | 0672 0673 0674 0675 0676 0677 0678 0679 0680 0681 0682 0683 0684 0685 0686 0687
280 | 0688 0689 0690 069! 0692 -0693 0694 0695 0696 0697 0698 0699 0700 0701 0702 0703
2C0 | 0704 0705 0706 0707 0708 0709 0710 0711 0712 0713 0714 0715 0716 0717 0718 0719
2D0 | 0720 0721 0722 0723 0724 0725 0726 0727 0728 0729 0730 0731 0732 0733 0734 0735
260 | 0736 0737 0738 0739 0740 0741 0742 0743 0744 0745 0746 0747 0748 0749 0750 075]
2F0 | 0752 0753 0754 0755 0756 0757 0758 0759 0760 0761 0762 0763 0764 0765 0766 0767
30C | 0768 0769 0770 077] 0772 0773 0774 0775 0776 0777 0778 0779 0780 0781 0782 0783
310 | 0784 0785 0786 0787 0788 0789 0790 0791 0792 0793 0794 0795 0796 0797 0798 0799
320 | 0800 0801 0802 0803 0804 0805 0806 0807 0808 0809 0810 0811 0812 0813 0814 0815
330 | 0816 0817 0818 0819 0820 0821 0822 0823 0824 0825 0826 0827 0828 0829 0830 0831
340 | 0832 0833 0834 0835 0836 0837 0838 0839 0840 0841 0842 0843 0844 0845 0846 0847
350 | 0848 0849 0850 0851 0852 0853 0854 0855 0856 0857 0858 0859 0860 0861 0862 0863
360 | 0864 0865 0866 0867 0868 0869 0870 0871 0872 0873 0874 0875 0876 0877 0878 0879
3/0 | 0880 0881 0882 0883 0884 0885 0886 0887 0888 0889 0890 0891 0892 0893 0894 0895
380 | 089% 0897 0898 0899 0900 0901 0902 0903 0904 0905 0906 0907 0908 0909 0910 0911
390 | 0912 0913 0914 0915 0916 0917 0918 0919 0920 0921 0922 0923 0924 0925 0926 0927
ЗАО | 0928 0929 0930 0931 0932 0933 0934 0935 0936 0937 0938 0939 0940 0941 0942 0943
380 | 0944 0945 0946 0947 0948 0949 0950 0951 0952 0953 0954 0955 0956 0957 0958 0959
3CO | 0960 0961 0962 0963 0964 0965 0966 0967 0968 0969 0970 0971 0972 0973 0974 0975
300 | 0976 0977 0978 0979 0980 0981 0982 0983 0984 0985 0986 0987 0988 0989 0990 0991
3EO | 0992 0993 0994 0995 0996 0997 0998 0999 1000 1001 1002 1003 1004 1005 ‘1006 1007
3F0 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023
HEXADECIMAL - DECIMAL INTEGER CONVERSION TABLE (cont.
0 1 2 3 4 5 6 7 8 9 A B С D E F
400 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039
410 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055
420 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071
430 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
440 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
450 1104 1105 1106 1107 1108 1109 1110 111] 1112 1113 1114 1115 1116 1117 1118 1119
460 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
470 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 115]
480 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
490 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183
4A0 | 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199
480 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 121] 1212 1213 1214 1215
4C0 | 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231
ADO | 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
4E0 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263
4F0 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
500 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295
510 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
520 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
530 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
540 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359
550 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
560 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423
590 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439
5A0 | 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455
>BO 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
5С0 | 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487
5D0 | 1488 1489 1490 1491 1492 1493 14% 1495 1496 1497 1498 1499 1500 1501 1502 1503
5EO 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519
FO 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535
600 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551
610 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
620 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
630 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599
640 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615
650 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631
660 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647
670 1648 1649 1620 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
680 1664 1665 1666 1667 1668 1669 1670 1671 16/2 16/3 1674 1675 1676 1677 1678 1679
690 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695
6A0 | 16% 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1/11
680 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727
ECO | 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743
EDO | 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
ÓEO 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775
6F0 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791
HEXADECIMAL - DECIMAL INTEGER CONVERSION TABLE (cont. )
0 ] 2 3 4 5 6 7 8 9 A B C D E F
700 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807
710 | 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
720 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839
730 | 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 .1850 1851 1852 1853 1854 1855
740 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
750 | 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887
760 | 1888 1889 1890 1891 1892 1873 1894 1895 1896 1897 1898 1899 1900 19201 1902 1903
770 | 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1718 1919
780 | 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
790 | 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951
740 | 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967
780 | 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
7C0 | 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999
700 | 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
7E0 | 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031
7F0 | 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047
800 | 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
810 | 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079
820 | 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
830 | 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
840 | 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127
850 | 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143
860 | 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159
870 | 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175
880 | 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191
890 | 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207
8А0 | 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223
8B0 | 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239
BCO | 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255
8D0 | 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
BEO | 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287
8F0 | 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303
900 | 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319
910 | 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335
920 | 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351
930 | 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367
940 | 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
950 | 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399
960 | 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415
970 | 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431
780 | 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447
990 | 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463
FAO | 2464 2465 2466 2467 2468 2469 2470 247] 2472 2473 2474 2475 2476 2477 2478 2479
780 | 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495
9CO | 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511
9DO | 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527
9E0 | 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543
PFO | 2544 2545 2546 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559
2547
HEXADECIMAL - DECIMAL INTEGER CONVERSIÓN TABLE (cont.)
0 ! 2 3 4 5 6 7 8 9 A B C D E г
А00 | 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575
А10 | 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591
А20 | 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607
A30 | 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623
А40 | 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639
А50 | 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655
A60 | 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 26/0 2671
А70 | 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687
ABO | 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2/00 2701 2702 2703
A90 | 2704 2705 2706 2707 2708 2709 2/10 2711 2712 2713 2714 2715 2716 2717 2718 2719
AAO | 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735
ABO | 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751
ACO | 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767
ADO | 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783
AEO | 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799
AFO | 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815
BOO | 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831
B10 | 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2343 2844 2845 2846 2847
B20 | 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863
B30 | 2864 2865 2866 2867 2868 2869 28/0 2871 2872 2873 2874 2875 2876 2877 2878 2879
B40 | 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895
B50 | 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911
B6O | 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927
B70 | 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943
В80 | 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959
B90 | 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975
BAO | 2976 2977 2978 2979 2980 2781 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991
BBO | 2992 2993 2994 2995 2996 2997 2998 2999: 3000 3001 3002 3003 3004 3005 3006 3007
BCO | 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023
BDO | 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039
BEO | 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055
BFO | 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071
C00 | 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 13082 3083 3084 3085 3086 3087
C10 | 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103
C20 | 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119
C30 | 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135
C40 | 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151
C50 | 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167
C60 | 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183
C70 | 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199
C80 | 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215
C90 | 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 323!
CAO | 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247
CBO | 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263
CCO | 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279
CDO | 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295
CEO | 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311
CFO | 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327
HEXADECIMAL - DECIMAL INTEGER CONVERSION TABLE (cont. )
0 i 2 3 4 5 6 7 8 9 A B C E F
DOO | 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343
DIO | 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359
020 | 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375
D30 | 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391
D40 | 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407
D50 | 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423
D60 | 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439
D70 | 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455
D80 | 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471
D90 | 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487
DAO | 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503
DBO | 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519
DCO | 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535
DDO | 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551
DEO | 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567
DFO | 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583
EOC | 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599
E10 | 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615
E20 | 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631
E30 | 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647
E40 | 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663
ESO | 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679
E60 | 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695
E70 | 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711
ESO | 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727
E90 | 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743
EAO | 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759
EBO | 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775
ECO | 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791
EDO | 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807
EEO | 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823
EFO | 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839
FOO | 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855
F10 | 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871
F20 | 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887
F30 | 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903
F40 | 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919
F50 | 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935
F60 | 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951
F70 | 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967
FBO | 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983
F90 | 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999
FAO | 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015
FBO | 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031
FCO | 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047
FDO | 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063
FEO | 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 40/9
FFO | 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095
HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
.00 00 00 90°
.01 00 00 00
‚02 00 00 00
‚03 00 00 00
‚04 00 00 00
‚05 00 00 00
.06 00 00 00
.07 00 00 00
.08 00 00 00
.09 00 00 00
.0A 00 00 00
.08 00 00 00
‚ОС 00 00 00
.0D 00 00 00
.OE 00 00 00
‚OF 00 00 00
.10 00 00 00
.11 00 00 00
.12 00 00 00
.13 00 00 00
.14 00 00 00
.15 00 00 00
.16 00 00 00
.17 00 00 00
.18 00 00 00
.19 00 00 00
ТА 00 00 00
.18 00 00 00
.1C 00 00 00
.1D 00 00 00
.1E 00 0000
.1F 00 00 00
.20 00 00 00
.21 00 00 00
.22 00 00 00
.23 00 00 00
.24 00 00 00
.25 00 00 00
.26 00 00 00
.27 00 00 00
.28 00 00 00
.29 00 00 00
.2A 00 00 00
.2B 00 00 00
.2C 00 00 00
.2D 00 00 00
.2E 00 00 00
.2F 00 00 00
.30 00 00 00
.31 00 00 00
.32 00 00 00
.33 00 00 00
‚34 00 00 00
‚35 00 00 00
.36 00 00 00
.37 00 00 00
.38 00 00 00
.37 00 00 00
.3A 00 00 00
.3B 00 00 00
.3C 00 00 00
.3D 00 00 00
‚ЗЕ 00 00 00
‚ЗЕ 00 00 00
. 00000 00000
.00390 62500
.00781 25000
01171 87500
‚01562 50000
‚01953 12500
‚02343 75000
‚02734 37500
‚03125 00000
‚03515 62500
‚03906 25000
‚04296 87500
‚04687 50000
‚05078 12500
‚05468 75000
‚05859 37500
‚06250 00000
‚06640 62500
‚07031 25000
‚07421 87500
‚07812 50000
‚08203 12500
‚08593 75000
‚08984 37500
‚09375 00000
‚09765 62500
‚10156 25000
‚10546 87500
‚10937 50000
‚11328 12500
‚11718 75000
‚12109 37500
‚12500 00000
‚12890 62500
‚13281 25000
‚13671 87500
. 14062 50000
. 14453 12500
. 14843 75000
. 15234 37500
. 15625 00000
.16015 62500
.16406 25000
16796 87500
‚17187 50000
‚17578 12500
‚17968 75000
‚18359 37500
‚18750 00000
‚19140 62500
‚19531 25000
‚19921 87500
‚20312 50000
‚20703 12500
‚21093 75000
‚21484 37500
‚21875 00000
‚22265 62500
‚22656 25000
‚23046 87500
‚23437 50000
‚23828 12500
‚24218 75000
‚24609 37500
‚40 00 00 00
.41 00 00 00
.42 00 00 00
.43 00 00 00
.44 00 00 00
‚45 00 00 00
.46 00 00 00
.47 00 00 00
.48 00 00 00
‚49 00 00 00
.4A 00 00 00
.48 00 00 00
.4C 00 00 00
.4D 00 00 00
‚АЕ 00 00 00
.4F 00 00 00
50 00 00 00
.51 00 00 00
.52 00 00 00
‚53 00 00 00
.54 00 00 00
‚55 00 00 00
‚56 00 00 00
.57 00 00 00
.58 00 00 00
‚59 00 00 00
.5A 00 00 00
.58 00 00 00
‚5С 00 00 00
‚50 00 00 00
‚5Е 00 00 00
.5F 000000
.60 00 00 00
61 00 00 00
.62 00 00 00
.63 00 00 00
.64 00 00 00
.65 00 00 00
.66 00 00 00
.67 00 00 00
.68 00 00 00
‚69 00 00 00
‚6А 00 00 00
.68 00 00 00
.6C 00 00 00
.6D 00 00 00
.6E 00 00 00
‚SF 00 00 00
.70 00 00 00
.71 00 00 00
.72 00 0000
.73 00 00 00
.74 00 00 00
.75 00 00 00
‚76 00 00 00
.77 00 00 00
‚78 00 00 00
‚79 00 00 00
‚ЛА 00 00 00
.78 00 00 00
.7C 00 00 00
.7D 00 00 00
.7E 00 00 00
.7F 00 00 00
.25000 00000
.25390 62500
.25781 25000
‚26171 87500
‚26562 50000
‚26953 12500
‚27 343 75000
‚27734 37500
‚28125 00000
‚28515 62500
‚28906 25000
‚29296 87500
‚29687 50000
‚30078 12500
‚30468 75000
‚30859 37500
‚31250 00000
‚31640 62500
‚32031 25000
‚32421 87500
‚32812 50000
‚33203 12500
„33593 75000
‚33984 37500
‚34375 00000
‚34765 62500
‚35156 25000
‚35546 87500
‚35937 50000
‚36328 12500
‚36718 75000
‚37109 37500
‚37500 00000
‚37890 62500
‚38281 25000
‚38671 87500
‚39062 50000
‚39453 12500
‚39843 75000
‚40234 37500
‚40625 00000
‚41015 62500
‚41406 25000
‚41795 87500
‚42187 50000
‚42578 12500
42968 75000
43359 3/7500
‚43750 00000
‚44140 62500
.44531 25000
‚44921 87500
‚45312 50000
‚45703 12500
‚46093 75000
‚46484 37500
‚46875 00000
47265 62500
47656 25000
‚48046 87500
‚48437 50000
‚48828 12500
‚49218 75000
‚49609 37500
‚80 00 00 00
.81 00 00 00
‚82 00 00 00
.83 00 00 00
.84 00 00 00
.85 00 00 00
.86 00 00 00
.87 00 00 00
.88 00 00 00
.89 00 00 00
.8A 00 00 00
.88 00 00 00
.8C 00 00 00
8D 00 00 00
.8E 00 00 00
.8F 00 00 00
.90 00 00 00
.21 00 00 00
.92 00 00 00
‚93 00 00 00
‚94 00 00 00
‚95 00 00 00
.96 00 00 00
.97 00 00 00
.78 00 00 00
.99 00 00 00
.9A 00 00 00
.78 00 00 00
.9C 00 00 00
.90 00 00 00
‚ЭЕ 00 00 00
.9F 00 00 00
‚АО 00 00 00
.Al 00 00 00
.A2 00 00 00
‚АЗ 00 00 00
.A4 00 00 00
.AS 00 00 00
‚Аб 00 00 00
‚А7 00 00 00
.A8 00 00 00
‚AS 00 00 00
.AA 00 00 00
.AB 00 00 00
.AC 00 00 00
.AD 00 00 00
.AE 00 00 00
.AF 00 00 00
.BO 00 00 00
.B1 00 00 00
.B2 00 00 00
.B3 00 00 00
.B4 00 00 00
.B5 00 00 00
.B6 00 00 00
‚ВУ 00 00 00
.B8 00 00 00
.B? 00 00 00
.BA 00 00 00
.BB 00 00 00
.BC 00 00 00
.BD 00 00 00
.BE 00 00 00
.BF 00 00 00
‚50000 00000
‚50390 62500
‚50781 25000
‚51171 87500
‚31562 50000
‚51953 12500
‚52343 75000
‚52734 37500
‚53125 00000
‚53515 62500
‚53906 25000
‚54296 87500
‚54687 50000
.55078 12500
‚55468 75000
‚55859 37500
‚56250 00000
‚36640 62500
‚57031 25000
‚57421 87500
‚57812 50000
‚58203 12500
‚58593 75000
‚58984 37500
‚59375 00000
‚59765 62500
‚60156 25000
‚60546 87500
‚60937 50000
‚61328 12500
‚61718 75000
‚62109 37500
‚62500 00000
‚62890 62500
‚63281 25000
‚63671 87500
‚64062 50000
‚64453 12500
‚64843 75000
‚65234 37500
‚65625 00000
‚66015 62500
‚66406 25000
66796 87500
.67 187 50000
‚67578 12500
‚67 968 75000
‚68359 37500
‚68750 00000
‚69140 62500
‚69531 25000
69921 87500
‚70312 50000
„70703 12500
‚71093 75000
71484 37500
.71875 00000
.72265 62500
‚72656 25000
‚73046 87500
‚73437 50000
‚73828 12500
74218 75000
‚74609 37500
.CO 00 00 00
.C1 00 00 00
.C2 00 00 00
.C3 00 00 00
.C4 00 00 00
.C5 00 00 00
.Có 00 00 00
.C7 00 00 00
.C8 00 00 00
.C? 00 00 00
‚СА 00 00 00
‚СВ 00 00 00
‚СС 00 00 00
.CD 00 00 00
.CE 00 00 00
.CF 00 00 00
.DO 00 00 00
.D1 00 00 00
.D2 00 00 00
.D3 00 00 00
.D4 00 00 00
.D5 00 00 00
.Dó 00 00 00
.D7 00 00 00
.D8 00 00 00
.D? 00 00 00
.DA 00 00 00
.DB 00 00 00
.DC 00 00 00
‚DD 00 00 00
.DE 00 00 00
.DF 00 00 00
.EO 00 00 00
.ET 00 00 00
.E2 00 00 00
.E3 00 00 00
.E4 00 00 00
.ES 00 00 00
.E6 00 00 00
.E7 00 00 00
.E8 00 0000
.E9 000000
.EA 00 00 00
‚EB 00 0000
.EC 00 00 00
.ED 00 00 00
.EE 00 00 00
.EF 00 00 00
.FO 00 00 00
.F1 0000 00
.F2 00 00 00
F3 00 00 00
.F4 00 00 00
.F5 00 00 00
.F6 00 00 00
.F7 00 00 00
.F8 00 00 00
.F$ 00 00 00
.FA 00 00 00
.F8 00 00 00
‚РС 00 00 00
.FD 00 00 00
.FE 00 00 00
FF 00 00 00
.75000 00000
.75390 62500
‚75781 25000
‚76171 87500
‚76562 50000
‚76953 12500
77343 75000
.77734 37500
.78125 00000
.78515 62500
‚/8906 25000
‚79296 87500
79687 50000
.80078 12500
‚80468 75000
‚80859 37500
‚81250 00000
‚81640 62500
‚82031 25000
‚82421 87500
‚82812 50000
‚83203 12500
‚83593 75000
‚83984 37500
‚84375 00000
‚84765 62500
‚85156 25000
‚85546 87500
‚85937 50000
‚86328 12500
‚86718 75000
‚87109 37500
‚87500 00000
‚87890 62500
‚88281 25000
‚88671 87500
‚89062 50000
‚89453 12500
‚89843 75000
‚90234 37500
‚90625 00000
‚91015 62500
‚91406 25000
‚91796 87500
‚92187 50000
‚92578 12500
‚92968 75000
‚93359 37500
‚93750 00000
‚94140 62500
‚94531 25000
‚94921 87500
‚95312 50000
‚95703 12500
‚96093 75000
‚96484 37500
‚96875 ©0000
‚97265 62500
‚97656 25000
‚ 98046 87500
.78437 50000
.78828 12500
‚79218 75000
.99609 37500
HEXADECIMAL - DECIMAL FRACTION CONVERSION TABLE (cont. )
.00 FF 00 00
Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal
.00 00 00 00 .00000 00000 .00 40 00 00 ‚00097 65625 .00 80 00 00 .00195 31250 .00 CO 00 00 ‚00292 96875
.00 01 00 00 .00001 52587 .0041 0009 ‚00099 18212 ‚00 81 00 00 ‚0019 83837 .00 C1 00 00 ‚00294 49462
‚00 02 00 00 ‚00003 05175 ‚00 42 00 00 ‚00100 70800 ‚00 82 00 00 ‚00198 36425 .00 C2 00 00 .00296 02050
.00 03 00 00 .00004 57763 .00 43 00 00 .00102 23388 .0083 00 00 .00199 89013 .00 C3 00 00 .00297 54638
.00 04 00 00 .00006 10351 .00 44 00 00 .00103 75976 .0084 00 00 .00201 41601 .00 C4 00 00 ‚00299 07225
‚00 05 00 00 ‚00007 62939 ‚00 45 00 00 ‚00105 28564 .00 85 00 00 ‚00202 94189 ‚00 С5 00 00 ‚00300 59814
‚00 06 00 00 ‚00009 15527 ‚00 46 00 00 ‚00106 81152 ‚00 86 00 00 ‚00204 46777 .00 C6 00 00 ‚00302 12402
‚00 07 00 00 ‚00010 68115 ‚00 47 00 00 ‚00108 33740 ‚00 87 00 00 ‚00205 99365 .00 C7 00 00 .00303 64790
.00 08 00 00 .00012 20703 .00 48 00 00 .00109 86328 ‚00 88 00 00 ‚00207 51953 .00 C8 00 00 ‚00305 17578
‚00 09 00 00 ‚00013 73291 ‚00 49 00 00 .00111 38916 ‚00 89 00 00 .00209 04541 .00 C9 00 00 .00306 70166
.00 OA 00 00 .00015 25878 .00 4A 00 00 .00112 91503 .00 8A 00 00 .00210 57128 .00 CA 00 00 .00308 22753
.00 08 00 00 ‚00016 78466 .00 4B 00 00 .00114 44091 .00 88 00 00 ‚00212 09716 .00 CB 00 00 .00309 75341
.00 OC 00 00 .00018 31054 ‚00 4С 00 00 ‚00115 96679 .00 8C 00 00 ‚00213 62304 .00 CC 00 00 .00311 27929
.00 OD 00 00 ‚00019 83642 ‚00 4D 00 00 .00117 49267 .00 8D 00 00 .00215 14892 .00 CD 00 00 ‚00312 80517
‚00 ОЕ 00 00 .0002! 36230 ‚00 4Е 00 00 ‚00119 01855 ‚00 8Е 00 00 ‚00216 67480 ‚00 СЕ 00 00 ‚00314 33105
.00 OF 00 00 .00022 88818 .00 4F 00 00 ‚00120 54443 ‚00 8F 00 00 .00218 20068 .00 CF 00 00 .00315 85693
.00 10 0000 ‚00024 41406 ‚00 50 00 00 ‚00122 07031 ‚00 20 00 00 00219 72656 .00 DO 00 00 .00317 38281
0011 0000 .00025 93994 .00 51 0000 .00123 59619 ‚00 91 00 00 ‚00221 25244 .00 D1 00 00 ‚00318 90869
‚00 12 00 00 ‚00027 46582 ‚00 52 00 00 ‚00125 12207 ‚00 92 00 00 ‚00222 77832 .00 D2 00 00 .00320 43457
.00 13 0000 .00028 99169 .00 53 0000 .00126 64794 .00 93 00 00 .00224 30419 .00 D3 00 00 .00321 96044
.00 14 00 00 .00030 51757 .00 54 00 00 .00128 17382 ‚00 94 00 00 .00225 83007 .00 D4 00 00 .00323 48632
‚00 15 00 00 ‚00032 04345 ‚00 55 00 00 ‚00129 69970 ‚00 95 00 00 ‚00227 35595 ‚00 D5 00 00 ‚00325 01220
.00 16 0000 .00033 56933 .00 56 00 00 .00131 22558 .00 96 00 00 .00228 88183 .00 D6 0000 .00326 53808
.00 17 00 00 .00035 09521 .00 57 0000 .00132 75146 ‚00 97 00 00 .00230 40771 .00 D7 00 00 .00328 06396
‚00 18 00 00 ‚00036 62109 ‚00 58 00 00 ‚00134 27734 ‚00 98 00 00 ‚00231 93359 ‚00 08 00 00 ‚00329 58984
.00 19 00 00 .00038 14697 .00 59 00 00 .00135 80322 ‚00 99 0000 .00233 45947 .00 D9 00 00 .00331 11572
‚00 1A 00 00 .00039 67285 .00 5A 00 00 .00137 32910 .00 9A 00 00 .00234 98535 .00 DA 00 00 .00332 64160
.00 1B 00 00 .00041 19873 .00 58 00 00 .00138 85498 .00 98 00 00 .00236 51123 .00 DB 00 00 .00334 16748
.00 IC 0000 ‚00042 72460 .00 5C 00 00 .00140 38085 ‚00 9С 00 00 ‚00238 03710 ‚00 DC 00 00 .00335 69335
.00 1D 00 00 .00044 25048 .00 5D 00 00 .00141 90673 .00 9D 00 00 .00239 56298 .00 DD 00 00 .00337 21923
.00 1E 0000 .00045 77636 .00 SE 0000 .00143 43261 .00 9E 00 00 .00241 08886 .00 DE 00 00 .00338 74511
.00 1F 0000 .00047 30224 .00 5F 0000 .00144 95849 .00 9F 00 00 ‚00242 61474 .00 DF 00 00 .00340 27099
.00 20 00 00 .00048 82812 .00 60 00 00 .00146 48437 .00 AO 00 00 .00244 14062 .00 EO 00 00 ‚00341 79687
‚00 21 00 00 ‚00050 35400 ‚00 61 00 00 ‚00148 01025 .00 Al 00 00 .00245 66650 .00 El 0000 .00343 32275
‚00 22 00 00 .00051 87988 .00 62 00 00 ‚00149 53613 ‚00 A2 00 00 .00247 19238 .00 E2 00 00 .00344 84863
.00 23 0000 .00053 40576 .00 63 00 00 .00151 06201 .00 A3 00 00 .00248 71826 .00 E3 00 00 .00346 37451
‚00 24 00 00 ‚00054 93164 ‚00 64 00 00 ‚00152 58789 ‚00 А4 00 00 ‚00250 24414 ‚00 Е4 00 00 ‚00347 90039
‚00 25 00 00 ‚00056 45751 .00 65 00 00 ‚00154 11376 .00 AS 00 00 .00251 77001 .00 ES 0000 .00349 42626
‚00 26 00 00 ‚00057 98339 ‚00 66 00 00 ‚00155 63964 .00 A6 00 00 .00253 29589 .00 E6 00 00 .00350 95214
.00 27 00 00 .00059 50927 ‚00 67 00 00 ‚00157 16552 .00 А7 00 00 ‚00254 82177 ‚00 ЕУ 00 00 ‚00352 47802
‚00 28 00 00 .00061 03515 ‚00 68 00 00 ‚00158 69140 ‚00 АВ 00 00 ‚00256 34765 ‚00 Е8 00 00 ‚00354 00390
‚00 29 00 00 ‚00062 56103 .00 69 00 00 00160 21728 ‚00 A9 00 00 .00257 87353 .00 EY 00 00 .00355 52978
.00 2A 00 00 .00064 08691 .00 6A 00 00 ‚00161 74316 .00 AA 00 00 .00259 39941 .00 EA 00 00 .00357 05566
.00 2B 0000 .00065 61279 .00 6B 00 00 ‚00163 26904 .00 AB 00 00 .00260 92529 .00 EB 00 00 .00358 58154
.00 2C 00 00 .00067 13867 .00 6C 00 00 ‚00164 79492 .00 AC 00 00 ‚00262 45117 .00 EC 00 00 ‚00360 10742
.00 2D 00 00 .00068 66455 .00 6D 00 00 .00166 32080 .00 AD 00 00 .00263 97705 .00 ED 00 00 .00361 63330
.00 2E 0000 .00070 19042 .00 6E 00 00 .00167 84667 .00 AE 00 00 ‚00265 50292 .00 EE 00 00 ‚00363 15917
.00 2F 00 00 .00071 71630 .00 6F 00 00 .00169 37255 .00 AF 00 00 .00267 02880 ‚00 EF 00 00 ‚00364 68505
.00 30 0000 .00073 24218 .00 70 00 00 .00170 89843 .00 BO 00 00 ‚00268 55468 ‚00 FO 00 00 .00366 21093
.00 31 0000 .00074 76806 .00 71 0000 .00172 42431 .00 B1 0000 .00270 08056 .00 F1 00 00 .00367 73681
.00 32 00 00 ‚00076 29394 ‚00 72 00 00 ‚00173 95019 .00 B2 00 00 ‚00271 60644 ‚00 Е2 00 00 .00369 26269
‚00 33 00 00 ‚00077 81982 ‚00 73 00 00 ‚00175 47607 ‚00 B3 00 00 .00273 13232 .00 F3 0000 .00370 78857
.00 34 00 00 .00079 34570 .0074 00 00 .00177 00195 .00 B4 00 00 .00274 65820 .00 F4 00 00 .00372 31445
.00 35 0000 ‚00080 87158 ‚00 75 00 00 ‚00178 52783 ‚00 85 00 00 ‚00276 18408 ‚00 F5 0000 .00373 84033
.00 36 00 00 .00082 39746 .00 76 0000 .00180 05371 .00 B6 0000 .00277 70996 .00 Fó 00 00 .00375 36621
.00 37 0000 .00083 92333 .00 77 0000 .00181 57958 .00 87 00 00 .00279 23583 .00 F7 00 00 .00376 89208
.00 38 00 00 .00085 44921 .00 78 00 00 .00183 10546 .00 B8 00 00 ‚00280 76171 .00 F8 00 00 .00378 41796
‚00 39 00 00 ‚00086 97509 ‚00 79 00 00 ‚00184 63134 .00 B? 00 00 ‚00282 28759 .00 F9 00 00 .00379 94384
.00 3A 00 00 .00088 50097 .00 7A 00 00 .00186 15722 .00 BA 00 00 .00283 81347 .00 FA 00 00 .00381 46972
.00 3B 00 00 .00090 02685 .00 7B 00 00 .00187 68310 .00 BB 00 00 .00285 33935 .00 FB 0000 .00382 99560
‚00 3С 00 00 ‚00091 55273 ‚00 7С 00 00 .00189 20898 .00 BC 00 00 ‚00286 86523 00 FC 00 00 ‚00384 52148
.00 3D 00 00 ‚00093 07861 .00 7D 00 00 .00190 73486 .00 BD 00 00 .00288 39111 .00 FD 00 00 .00386 04736
.00 3E 00 00 .00094 60449 .00 7E 00 00 .00192 26074 .00 BE 00 00 .00289 91699 .00FE 0000 .00387 57324
.00 3F 0000 .00096 13037 .00 7F 0000 .00193 78662 .00 BF 0000 .00291 44287 .00389 09912
E-9
HEXADECIMAL - DECIMAL FRACTION CONVERSION TABLE (cont. }
Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal
‚00 00 00 00 ‚00000 00000 ‚00 00 40 00 ‚00000 38146 .00 00 80 00 .00000 76293 .00 00 CO 00 .00001 14440
.00 00 01 00 .00000 00596 .00 00 41 00 .00000 38743 .00 0081 00 .00000 76887 ‚00 00 СТ 00 ‚00001 15036
‚00 00 02 00 ‚00000 01192 ‚00 00 42 00 ‚00000 39339 ‚00 00 82 00 ‚00000 77 486 .00 00 C2 00 .00001 15633
.00 00 03 00 ‚00000 01788 ‚00 00 43 00 ‚00000 39935 ‚00 00 83 00 ‚00000 78082 .00 00 C3 00 .00001 16229
.00 00 04 00 .00000 02384 .00 00 44 00 .00000 40531 .00 00 84 00 .00000 78678 .00 00 C4 00 .00001 16825
.00 00 05 00 .00000 02980 ‚00 00 45 00 ‚00000 41127 ‚00 00 85 00 ‚00000 79274 0000 C5 00 .00001 17421
.00 00 06 00 .00000 03576 .00 00 46 00 .00000 41723 ‚00 00 86 00 ‚00000 79870 ‚00 00 G6 00 ‚00001 18017
‚00 00 07 00 ‚00000 04172 ‚00 00 47 00 ‚00000 42319 ‚00 00 87 00 ‚00000 80466 ‚00 00 С7 00 ‚00001 18613
‚00 00 08 00 ‚00000 04768 ‚00 00 48 00 ‚00000 42915 ‚00 00 88 00 ‚00000 81062 .00 00 C8 00 .00001 19209
.00 00 09 00 .00000 05364 .00 00 49 00 .00000 43511 .00 00 89 00 .00000 81658 .00 00 C9 00 .00001 17805
.00 00 0A 00 .00000 05960 .00 00 4A 00 .00000 44107 .00 00 8A 00 .00000 82254 .00 00 CA 00 ‚00001 20401
.00 00 0B 00 .00000 06556 .00 00 48 00 .00000 44703 .00 00 8B 00 .00000 82850 ‚00 00 СВ 00 ‚00001 20997
.00 00 0C 00 .00000 07152 .00 00 4C 00 .00000 45299 .00 00 8C 00 .00000 83446 .00 00 CC 00 .00001 21593
.00 00 0D 00 .00000 07748 -.00 00 4D 00 .00000 45895 .00 00 8D 00 .00000 84042 .00 00 CD 00 .00001 22189
.00 00 OE 00 .00000 08344 .00 00 4E 00 ‚00000 4649] .00 00 8E 00 .00000 84638 .00 00 CE 00 .00001 22785
.00 00 OF 00 .00000 08940 .00 00 4F 00 .00000 47087 .00 00 8F 00 .00000 85234 .00 00 CF 00 .00001 23381
.00 00 10 00 .00000 09536 ‚00 00 50 00 ‚00000 47683 ‚00 00 90 00 ‚00000 85830 .00 00 DO 00 .00001 23977
.00 00 11 00 .00000 10132 .00 00 51 00 .00000 48279 .00 0091 00 .00000 86426 .00 00 DI 00 .00001 24573
‚00 00 12 00 ‚00000 10728 ‚00 00 52 00 ‚00000 48875 ‚00 00 92 00 ‚00000 87022 .00 00 D2 00 .00001 25169
.00 00 13 00 .00000 11324 ‚00 00 53 00 ‚00000 49471 ‚00 00 93 00 ‚00000 87618 .00 00 D3 00 ‚00001 25765
.00 00 14 00 .00000 11920 .00 00 54 00 .00000 50067 .00 00 94 00 .00000 88214 .00 00 D4 00 .00001 26361
.00 0015 00 .00000 12516 .00 00 55 00 .00000 50663 .00 00 95 00 .00000 88810 .00 00 D5 00 .00001 26957
.00 00 16 00 .00000 13113 .00 00 56 00 .00000 51259 .00 00 96 00 .00000 89406 .00 00 D6 00 ‚00001 27553
.00 00 17 00 .00000 13709 ‚00 00 57 00 ‚00000 51856 ‚00 00 97 00 ‚00000 90003 .00 00 D7 00 .00001 28149
.00 0018 00 .00000 14305 .00 00 58 00 .00000 52452 .00 00 98 00 .00000 90599 .00 00 D8 00 ‚00001 28746
‚00 00 19 00 ‚00000 14901 ‚00 00 59 00 .00000 53048 .00 00 99 00 .00000 91195 .00 00 D? 00 ‚00001 29342
.00 00 1A 00 ‚00000 15497 .00 00 5A 00 ‚00000 53644 ‚00 00 9А 00 ‚00000 91791 .00 00 DA 00 ‚00001 29938
‚00 00 18 00 ‚00000 16093 ‚00 00 58 00 ‚00000 54240 ‚00 00 98 00 ‚00000 92387 .00 00 DB 00 .00001 30534
.00 00 1C 00 ,00000 16687 .00 00 5C 00 .00000 54836 .00 00 9C 00 .00000 92983 .00 00 DC 00 .00001 31130
.00 00 1D 00 .00000 17285 .00 00 3D 00 ‚00000 55432 .00 00 9D 00 .00000 93579 .00 00 DD 00 .00001 31726
‚00 00 1Е 00 ‚00000 17881 ‚00 00 5Е 00 ‚00000 56028 ‚00 00 9E 00 ‚00000 94175 ‚00 00 DE 00 ‚00001 32322
‚00 00 1Е 00 ‚00000 18477 ‚00 00.5F 00 .00000 56624 .00 00 9F 00 .00000 94771 .00 00 DF 00 .00001 32918
.00 00 20 00 .00000 19073 .00 00 60 00 .00000 57220 ‚00 00 АО 00 ‚00000 95367 ‚00 00 ЕО 00 ‚00001 33514
‚00 00 21 00 ‚00000 19669 ‚00 00 61 00 .00000 57816 .00 00 AT 00 .00000 95963 .00 00 El 00 .00001 34110
.00 00 22 00 .00000 20265 .00 00 62 00 .00000 58412 ‚00 00 А2 00 ‚00000 96559 ‚00 00 E2 00 .00001 34706
.00 00 23 00 ‚00000 20861 .00 00 63 00 .00000 59008 .00 00 A3 00 .00000 97155 .00 00 E3 00 .00001 35302
.00 00 24 00 .00000 21457 .00 00 64 00 .00000 59604 .00 00 A4 00 .00000 97751 .00 00 E4 00 .00001 35898
.00 00 25 00 ‚00000 22053 ‚00 00 65 00 ‚00000 60200 ‚00 00 А5 00 ‚00000 98347 .00 00 ES 00 .00001 36494
.00 00 26 00 .00000 22649 .00 00 66 00 .00000 60796 .00 00 A6 00 .00000 98943 .00 00 E6 00 .00001 37090
.00 00 27 00 .00000 23245 .00 00 67 00 .00000 61392 .00 00 A7 00 .00000 99539 .00 00 EZ 00 .00001 37686
.00 00 28 00 .00000 23841 ‚00 00 68 00 ‚00000 61988 ‚00 00 А8 00 ‚00001 00135 ‚00 00 Е8 00 ‚00001 38282
‚00 00 29 00 ‚00000 24437 ‚00 00 69 00 ‚00000 62584 .00 00 A? 00 .00001 00731 .00 00 EY 00 .00001 38878
.00 00 2A 00 .00000 25033 .00 00 6A 00 .00000 63180 .00 00 AA 00 .00001 01327 .00 00 EA 00 .00001 39474
‚00 00 28 00 ‚00000 25629 ‚00 00 68 00 ‚00000 63776 ‚00 00 АВ 00 ‚00001 01923 ‚00 00 ЕВ 00 ‚00001 40070
‚00 00 2C 00 ‚00000 26226 .00 00 6C 00 .00000 64373 .00 00 AC 00 .00001 02519 .00 00 EC 00 .00001 40666
.00 00 2D 00 .00000 26822 .00 00 6D 00 .00000 64969 .00 00 AD 00 ‚00001 03116 .00 00 ED 00 .00001 41263
.00 00 2E 00 .00000 27418 .00 00 6E 00 .00000 65565 .00 00 AE 00 .00001 03712 .00 00 EE 00 .00001 41859
.00 00 2F 00 .00000 28014 .00 00 6F 00 .00000 66161 .00 00 AF 00 .00001 04308 ‚00 00 ЕР 00 ‚00001 42455
‚00 00 30 00 ‚00000 28610 ‚00 00 70 00 ‚00000 66757 .00 00 BO 00 ‚00001 04904 .00 00 FO 00 .00001 43051
.00 00 31 00 .00000 29206 .00 0071 00 .00000 67353 .00 00 B1 00 .00001 05500 .00 00 F1 00 .00001 43647
.00 00 32 00 .00000 29802 .00 0072 00 .00000 67949 .00 00 82 00 .00001 06096 .00 00 F2 00 .00001 44243
.00 00 33 00 .00000 30398 ‚00 00 73 00 ‚00000 68545 ‚00 00 B3 00 ‚00001 06692 ‚00 00 F3 00 ‚00001 44839
.00 00 34 00 ‚00000 30994 ‚00 00 74 00 ‚00000 69141 ‚00 00 84 00 ‚00001 07288 .00 00 F4 00 .00001 45435
.00 00 35 00 .00000 31590 .00 0075 00 .00000 69737 .00 00 B5 00 ‚00001 07884 .00 00 F5 00 ‚00001 4603]
.00 00 36 00 .00000 32186 .000076 00 .00000 70333 .00 00 B6 00 .00001 08480 .00 00 F6 00 ‚00001 46627
‚00 00 37 00 ‚00000 32782 ‚00:00 77 00 ‚00000 70929 .00 00 B7 00 .00001 09076 .00 00 F7 00 .00001 47223
.00 00 38 00 .00000 33378 .00 0078 00 .00000 71525 .00 00 B8 00 .00001 09672 .00 00 F8 00 .00001 47819
.00 00 39 00 .00000 33974 .00 00 79 00 .00000 72121 .00 00 B9 00 .00001 10268 .00 00 F9 00 .00001 48415
.00 00 3A 00 .00000 34570 .00 00 7A 00 .00000 72717 .00 00 BA 00 .00001 10864 .00 00 FA 00 .00001 49011
‚00 00 38 00 ‚00000 35166 ‚00 00 7В 00 ‚00000 73313 .00 00 BB 00 .00001 11460 ‚00 00 ЕВ 00 ‚00001 49607
.00 00 3C 00 .00000 35762 .00 007€ 00 .00000 73909 .00 00 BC 00 .00001 12056 .00 00 FC 00 .00001 50203
.00 00 3D 00 .00000 36358 .00 00 7D 00 .00000 74505 .00 00 BD 00 .00001 12652 .00 00 FD 00 .00001 50799
.00 00 3E 00 .00000 36954 .00 00 7E 00 .00000 75101 .00 00 BE 00 .00001 13248 .00 00 FE 00 ‚00001 51395
‚00 00 3F 00 ‚00000 37550 ‚00 00 7Е 00 ‚00000 75697 .00 00 BF 00 .00001 13844 .00 00 FF 00 ‚00001 51991
10
HEXADECIMAL - DECIMAL FRACTION CONVERSION TABLE (cont.)
Hexadecimal Decimal Hexadecimal Decimal He.:adecimal Decimal Hexadecimal Decimal
.00 00 00 00 .00000 00000 .00 00 00 40 .00000 00149 .00 00 00 80 .00000 00298 .00 00 00 CO .00000 00447
.00 00 00 01 .00000 00002 .00 00 00 41 .00000 00151 .00 00 00 81 .00000 00300 .00 00 00 C1 .00000 00449
.00 00 00 02 .00000 00004 .00 00 00 42 .00000 00153 .00 00 00 82 .00000 00302 .00 00 00 C2 .00000 00451
.00 00 00 03 .00000 00006 .00 00 00 43 .00000 00155 .00 00 00 83 .00000 00305 .00 00 00 C3 .00000 00454
.00 00 00 04 .00000 00009 .00 00 00 44 .00000 00158 .00 00 00 84 .00000 00307 .00 00 00 C4 .00000 00456
.00 00 00 05 .00000 00011 .00 00 00 45 .00000 00160 .00 00 00 85 .00000 00309 .00 00 00 C5 .00000 00458
.00 00 00 06 .00000 00013 ‚ 00 00 00 46 ‚00000 00162 ‚00 00 00 86 .00000 00311 .00 00 00 Có .00000 00461
.00 00 00 07 .00000 00016 .00 00 00 47 .00000 00165 .00 00 00 87 .00000 00314 .00 00 00 C7 .00000 00463
.00 00 00 08 .00000 00018 .00 00 00 48 .00000 00167 .00 00 00 88 .00000 00316 .00 00 00 C8 ‚00000 00465
.00 00 00 09 .00000 00020 .00 00 00 49 ‚00000 00169 .00 00 00 89 .00000 00318 .00 00 00 C9 ‚00000 00467
‚00 00 00 ОА ‚00000 00023 ‚00 00 00 4A ‚00000 00172 ‚00 00 00 ВА ‚00000 00321 ‚00 00 00 CA ‚00000 00470
.00 00 CD 0B .00000 00025 .00 00 00 48 .00000 00174 .00 00 00 8B .00000 00323 .00 00 00 CB .00000 00472
.00 00 00 OC .00000 00027 .00 00 00 4C .00000 00176 .00 00 00 8C .00000 00325 .00 00 00 CC .00000 00474
.00 00 00 0D .00000 00030 .00 00 00 4D .00000 00179 .00 00 00 8D .00000 00328 .00 00 00 CD .00000 00477
.00 00 00 OE .00000 00032 .00 00 00 4E .00000 00181 .00 00 00 8E ..00000 00330 .00 00 00 CE .00000 00479
.00 00 00 OF .00000 00034 .00 00 00 4F .00000 00183 .00 00 00 8F .00000 00332 .00 00 00 CF .00000 00481
.00 00 00 10 .00000 00037 .00 00 00 50 .00000 00186 .00 00 00 90 ‚00000 00335 .00 00 00 DO .00000 00484
.0C 00 00 11 .00000 00039 .00 00 00 51 .00000 00188 .00 00 00 91 .00000 00337 .00 00 00 D1 .00000 00486
‚00 00 00 12 ‚00000 00041 ‚00 00 00 52 ‚00000 00190 ‚00 00 00 92 ‚00000 00339 ‚00 00 00 D2 ‚00000 00488
.00 00 00 13 .00000 00044 .00 00 00 53 .00000 00193 .00 00 00 93 .00000 00342 .00 00 00 D3 .00000 00491
.00 00 00 14 ‚00000 00046 .00 00 00 54 .00000 00195 .00 00 00 94 .00000 00344 .00 00 00 D4 .00000 00493
.00 0000 15 .00000 00048 .00 00 00 55 .00000 00197 .00 00 00 95 .00000 00346 .00 00 00 D5 .00000 00495
.00 00 00 16 .00000 00051 .00 00 00 56 .00000 00200 .00 00 00 96 .00000 00349 .00 00 00 Dé ‚00000 00498
.00 00 00 17 .00000 00053 .00 00 00 57 .00000 00202 .00 00 00 97 .00000 00351 .00 00 00 D7 .00000 00500
.00 00 00 18 .00000 00055 .00 00 00 58 .00000 00204 .00 00 00 98 .00000 00353 .00 00 00 D8 .00000 00502
‚00 00 00 19 ‚00000 00058 ‚00 00 00 59 ‚00000 00207 .00 00 00 99 .00000 00356 .00 00 00 D9 .00000 00505
.00 00 00 1A .00000 00060 .00 00 00 5A .00000 00209 .00 00 00 9A .00000 00358 .00 00 00 DA .00000 00507
.00 00 00 1B .00000 00062 .00 00 00 5B .00000 00211 .00 00 00 9B .00000 00360 .00 00 00 DB .00000 00509
.00 00 00 1C .00000 00065 .00 00 00 5C .00000 00214 .00 00 00 9C .00000 00363 .00 00 00 DC .00000 00512
.00 00 00 1D .00000 00067 .00 00 00 5D .00000 00216 .00 00 00 9D .00000 00365 .00 00 00 DD .00000 00514
.00 00 00 1E ‚00000 00069 .00 00 00 5E .00000 00218 .00 00 00 9Е ‚00000 00367 .00 00 00 DE .00000 00516
.000000 IF .00000 00072 .00 00 00 5F .00000 00221 .00 00 00 9F .00000 00370 .00 00 00 DF .00000 00519
.00 00 00 20 .00000 00074 .00 00 00 60 .00000 00223 .00 00 00 40 .00000 00372 .00 00 00 EO .00000 00521
.00 00 00 21 .00000 00076 .00 00 00 61 ‚00000 00225 .00 00 00 Al .00000 00374 .00 00 00 El .00000 00523
.00 00 00 2? .00000 00079 .00 00 00 6? .00000 00228 .00 00 00 A2 .00000 00377 .00 00 00 E? .00000 00526
.00 00 00 23 .00000 00081 .00 00 00 63 .00000 00230 .00 00 00 A3 .00000 00379 .00 00 00 E3 .00000 00528
.00 00 00 24 .00000 00083 .00 00 00 64 .00000. 00232 .00 00 00 A4 .00000 00381 .00 00 00 Е4 .00000 00530
.00 00 00 25 .00000 00086 .00 00 00 65 .00000 00235 .00 00 00 AS .00000 00384 .00 00 00 ES .00000 00533
.00 00 00 26 .00000 00088 .00 00 00 66 .00000 00237 .00 Q0 00 A6 .00000 00386 .00 00 00 Eó .00000 00535
.00 00 00 27 .00000 00090 .00 00 00 67 .00000 00239 .00 00 00 A7 .00000 00388 .00 00 00 E7 .00000 00537
.00 00 00 28 .00000 00093 .00 00 00 68 .00000 00242 .00 00 00 A8 ‚00000 00391 .00 00 00 ES .00000 00540
.00 00 00 29 .00000 00095 .00 00 00 69 .00000 00244 .00 00 00 A9 .00000 00393 .00 00 00 E? .00000 00542
.00 00 00 2A .00000 00097 .00 00 00 6A .00000 00246 .00 00 00 AA .00000 00395 .00 00 00 EA .00000 00544
.00 00 00 28 .00000 00100 ‚00 00 00 6В ‚00000 00249 ‚00 00 00 АВ ‚00000 00398 ‚00 00 00 EB ‚00000 00547
‚00 00 00 2C ‚00000 00102 ‚00 00 00 6C ‚00000 00251 ‚00 00 00 АС ‚00000 00400 .00 00 00 EC .00000 00549
.00 00 00 2D .00000 00104 .00 00 00 6D .00000 00253 .00 00 00 AD .00000 00402 .00 00 00 ED .00000 00551
.00 00 00 2E .00000 00107 .00 00 00 6E .00000 00256 .00 00 00 AE .00000 00405 .00 00 00 EE .00000 00554
.00 00 00 2F .00000 00109 .00 00 00 6F .00000 00258 .00 00 00 AF .00000 00407 .00 00 00 EF .00000 00556
.00 00 00 30 .00000 00111 .00 00 00 70 .00000 00260 .00 00 00 BO ‚00000 00409 ‚00 00 00 FO ‚00000 00558
.00 00 00 31 .00000 00114 .00 00 00 71 .00000 00263 .00 00 00 BI .00000 00412 .00 00 00 FI .00000 00561
.00 00 00 32 .00000 00116 .00 00 00 72 .00000 00265 .00 00 00 B2 .00000 00414 .00 00 00 F2 .00000 00563
.00 00 00 33 .00000 00118 .00 00 00 73 .00000 00267 .00 00 00 B3 .00000 00416 .00 00 00 F3 ‚00000 00565
.00 00 00 34 ‚00000 00121 ‚00 00 00 74 ‚90000 00270 .00 00 00 B4 .00000 00419 .00 00 00 F4 .00000 00568
.00 00 00 35 .00000 00123 .00 00 00 75 .00000 00272 .00 00 00 B5 .00000 00421 .00 00 00 F5 .00000 00570
.00 00 00 36 .00000 00125 ‚00 00 00 76 ‚00000 00274 .00 00 00 B6 .00000 00423 .00 00 00 F6 .00000 00572
.00 00 00 37 .00000 00128 .00 00 00 77 .00000 00277 .00 00 00 B7 .00000 00426 .00 00 00 F7 .00000 00575
.00 00 00 38 .00000 00130 .00 00 00 78 .00000 00279 .00 00 00 B8 .00000 00428 .00 00 00 F8 .00000 00577
.00 00 00 39 .00000 00132 ‚00 00 00 79 ‚00000 00281 .00 00 00 B9 .00000 00430 .00 00 00 F9 .00000 00579
.00 00 00 3A .00000 00135 .00 00 00 7A .00000 00284 .00 00 00 BA .00000 00433 .00 00 00 FA =— .00000 00582
.00 00 00 3B .00000 00137 .00 00 00 7B .00000 00286 .00 00 00 BB .00000 00435 .00 00 00 FB .00000 00584
.00 00 00 3C .00000 00139 .00 00 00 7C .00000 00288 .00 00 00 BC .00000 00437 .00 00 00 FC .00000 00586
.00 00 00 3D .00000 00142 .00 00 00 7D .00000 00291 .00 00 00 BD .00000 00440 .00 00 00 FD .00000 00589
.00 00 00 3E .00000 00144 ‚00 00 00 7E ‚00000 00293 ‚00 00 00 ВЕ ‚00000 00442 .00 00 00 FE ‚00000 00591
.00 00 00 3F .00000 00146 .00 00 00 7F .00000 00295 .00 00 00 BF .00000 00444 .00 00 00 FF .00000 00593
E-11
Constant
In2
99102
J10
In 10
MATHEMATICAL CONSTANTS
Decimal Value
3.14159
0.31830
1.77245
1.14472
2.71828
0.36787
1.64872
0.43429
1.44269
0.57721
-0.54953
1.41421
0.69314
0.30102
3.16227
2.30258
26535
78861
38509
78858
18284
74411
12707
44819
50408
56649
93129
35623
71805
99956
76601
50929
89793
83790
05516
49 400
59045
71442
00128
03252
88963
01533
81645
73095
59945
63981
68379
94046
Hexadecimal Value
3.243F
0.517C
1.C5BF
1.250D
2.B7E]
0.5E2D
1.A612
0.6F2D
1.7154
0.93C4
-0.8CAE
1.6A09
0.B172
0.4D10
3.298B
2.4D76
6 À 89
C187
891C
048F
5163
58D9
98E2
ЕС55
7653
67E4
BC]
E668
17F8
4D42
075C
3777
O > No
35
70
140
281
tv
17
34
68
137
274
549
099
199
398
796
592
184
368
737
474
1
2
4
8
16
33
67
134
268
536
073
147
294
589
179
359
719
438
877
755
511
023
046
093
186
372
744
488
(N
4
8
16
32
65
131
262
524
048
097
194
388
777
554
108
217
435
870
741
483
967
934
869
738
476
953
906
813
627
255
511
022
044
088
177
355
2
1
2
4
8
16
32
64
128
256
512
024
048
096
192
384
768
536
072
144
288
576
152
304
608
216
432
864
728
456
912
824
648
296
592
184
368
736
472
944
888
776
552
104
208
416
832
664
328
976 710 656
ww ro — ©
=) С“ ло
10
11
12
13
14
15
16
17
18
19
20
2
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
© © © < © OO © oO OO
oO OO
© © © ©
oO OO
OO OO
© © © —
oO © © ©
oO OO
oO Oo ©
OO OO
TABLE OF POWERS OF TWO
‚ 062
‚ 031
‚ 015
. 007
. 003
. 001
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
. 000
‚ 000
. 000
. 000
000
. 000
000
. 000
. 000
000
000
. 000
. 000
. 000
. 000
5
25
625
812
906
953
976
48€
244
122
061
030
015
007
003
001
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
030
000
000
000
000
000
000
000
25
125
562
281
140
070
035
517
258
629
814
907
953
476
238
119
059
029
014
007
003
001
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
625
312
156
578
789
394
697
348
674
837
418
209
604
802
901
450
725
862
931
465
232
116
058
029
014
007
003
001
000
000
000
000
000
000
000
000
000
25
125
062
531
265
632
316
158
579
289
644
322
161
580
290
645
322
661
830
415
207
103
551
275
637
818
909
454
227
113
056
028
014
007
003
5
25
625
812
406
203
101
550
775
387
193
596
298
149
574
287
643
321
660
830
915
957
978
989
494
747
373
686
843
421
210
105
25
125
562
781
390
695
847
923
461
230
615
307
653
826
913
456
228
614
807
403
701
350
675
837
418
709
854
427
5
25
625
312
656
828
914
957
478
739
869
934
467
733
366
183
091
545
5
25
125
062
031
515
257
628
814
407
703
851
425
712
856
772 928
886
443
721
860
430
464
232
616
808
404
715 202
357
601
552 713 678 800
E-15
5
25
625
812
906
453
226
613
806
903
951
475
237
118
059
029
014
007
003
001
500
25
125
562
281
640
320
660
830
915
957
478
739
869
434
717
858
929
5
25
625
3125
156 25
078 125
039 062 5
519 531 25
759 765 625
379 8828125
689 941 406 25
844 970 703 125
422 485 351 5625
711 242675 781 25
355 621 337 890 625
STANDARD CHARACTER CODES
SYMBOL ASCII EBCDIC HOLLERITH SYMBOL ASCII EBCDIC HOLLERITH
(HEX) (HEX) (029) (026) (HEX) (HEX) (029) (026)
blank АО 40 blank @ CO re 8-4 0-8-2
A1 SA 11-8-2 A C1 C1 12-1
; A2 7F 8-7 0-8-5 B C2 C2 12-2
# A3 78 0-3 0-8-7 C C3 C3 12-3
$ A4 5B 11-8-3 D C4 C4 12-4
% Ab 6C 0-8-4 11-8-7 E C5 C5 12-5
& A6 50 12 12-8-7 F C6 C6 12-6
A7 7D 8-5 8-4 G C7 C7 12-7
( A6 4D 12-85 0-84 H C8 C8 12-8
) A9 5D 11-8-5 12-84 | C9 C9 12-9
* AA 5C 11-84 J CA D1 11-1
+ AB 4E 1286 12 K CB D2 11-2
AC 68 0-8-3 L CC D3 11-3
— AD 60 11 M CD D4 11-4
. AE 4B 12-8-3 N CE D5 11-5
/ AF 61 0-1 O CF DE 11-6
0 BO FO 0 P DO D7 11-7
1 B1 F1 1 Q D1 D8 11-8
2 B2 F2 2 R D2 D9 11-9
3 B3 F3 3 S D3 E2 0-2
4 B4 F4 4 T D4 E3 0-3
5 B5 F5 5 U D5 E4 0-4
6 B6 F6 6 V D6 E5 0-5
7 B7 F7 7 W D7 E6 0-6
8 B8 F8 8 X D8 E7 0-7
9 B9 F9 9 Y D9 E8 0-8
: BA ТА 8-2 8-5 Z DA E9 0-9
; BB DE 11-8-6 [ DB 4F 12-87 12-8-5
< BC 4C 12-84 12-86 \ DC 4A 12-82 0-86
= BD 7E 8-6 8-3 ] DD SF 11-87 11-8-5
> BE 6E 0-8-6 8-6 1 DE 6D 0-8-5 8-7
? BF 6F 0-8-7 12-8-2 — DF 6A 0-8-2 8-2
TELETYPE CONTROL AND TRANSMISSION CODES
FUNCTION ASCII
NULL 80
SOM (Print on) 81
EAO 82
EOM 83
EOT (Print off) 84
WRU 85
RU 86
BELL 87
FEO 88
H.TAB 89
LINE FEED BA
V.TAB 8B
FORM 8C
CARRIAGE RETURN 8D
SO 8E
Si 8F
DCO 90
X-ON (Reader on) 91
TAPE (Punch on) 92
X-OFF (Reader off) 93
TAPE OFF (Punch off) 94
ERROR 95
SYNC 96
LEM 97
SO 98
51 99
52 9A
S3 9B
S4 9C
55 9D
S6 OE
S7 OF
APPENDIX F
LEFT BLANK INTENTIONALLY
APPENDIX G
FRONT PANEL USAGE
APPENDIX G
CONTROL PANEL USAGE
Loading or examining a program provides an excellent
example of sequential operations on consecutive memory
locations from the control panel. Any sequence of
control panel operations must begin with supplying the
initial address to the program counter. Assume the
- program to be examined starts at location 3F0. With all
register select switches off, place 3F0 in the PR and DB
switches, and depress EXC. This will place the contents
of the switches into the program counter to provide a
starting address. Then the following switch settings
produce the effects listed.
EXAMINE MEMORY AND MAKE CHANGES
SWITCH POSITION ACTION
Memory DIS selected, EXC Contents of location 3F0 displayed
a Ш H , STEP " " " 3F1 a
" " " , STEP " " " 3F2 "
'" " " , STEP " " " 3F3 Ш
" '" " , STEP '" " " 3F4 Ш
'" " '" , STEP " " " 3F5 Ш
Memory DIS deselected (assume contents of 3F5 to be in error.)
Contents of data switches written
into location 3F5 and displayed
Memory ENT selected, EXC
Memory ENT deselected
Memory DIS selected, STEP Contents of location 3F6 displayed
La tt te , STEP 1 La 1! 3F 7 tt
1! ft "1 STEP rt tt rt 3F 8 LU
>
The contents of the program counter can be examined at
any time by deselecting the memory DIS switch.
LOAD DATA INTO MEMORY AND EXAMINE
SWITCH POSITION ACTION
Memory ENT selected, EXC Contents of data switches dis-
played and written into location 3FO
Memory ENT selected, STEP Increment program counter to 3F1
and display contents of 3F1
Memory ENT selected, EXC Contents of data switches displayed
and written into location 3F1
Memory ENT selected, STEP Increment program counter to 3F2
and display contents of 3F2
(assume contents of 3F2 are already
correct)
Memory ENT selected, STEP Increment program counter to 3F3
and display contents of 3F3
Memory ENT selected, EXC Contents of data switches displayed
and written into location 3F3
Memory ENT selected, STEP Increment program counter to 3F4
and display contents of 3F4
The contents of the program counter can be examined at
any time by deselecting the Memory ENT switch.
STARTING A PROGRAM
Load the starting address into the program counter as
explained above, with all register select switches
down, depress the INIT switch momentarily and then depress
RUN. The INIT switch will clear any Link or OVFL flags,
G-2
and provide a reset to the I/O controllers. Depressing
the RUN switch will start the central processor execut-
ing instructions beginning at the starting address
contained in the program counter. The central processor
will remain in the run mode until halted by a Halt command
or depressing the Step switch,
STEPPING THROUGH A PROGRAM
Load the starting address into the program counter as
explained above. Depress the INIT switch momentarily.
With all register select swtiches down, depressing the
STEP switch will execute one instruction at a time.
The central processor may be placed in the RUN mode at
any time by depressing the RUN switch and then halted
by depressing the STEP switch. Stepping of the program
may continue from that point.
CHANGING THE CONTENTS OF THE ACCUMULATORS
Place the desired accumulator select switch (A or B)
in the up position. At that time, depressing the EXC
switch momentarily will take the contents of the DB
data switches into the selected accumulator.
If both accumulator select switches are up, the contents
of the DB data switches will be loaded into both accumulators
at the same time. This feature is useful for clearing both
accumulators from only one EXC action.
APPENDIX H
THE BOOTSTRAP ROUTINE
THE BOOTSTRAP ROUTINE
1.0
To load programs from the teletype, a small bootstrap
program must first be loaded by hand. It loads a more
complex program, the binary loader, which will load
all other programs. The binary loader is normally left
in the machine so that this operation is done only once.
Using the "step through memory" feature as explained
in Appendix G, load the following bootstrap program.
All program codes and addresses are hexadecimal. A
number annotated X'100' indicates hexadecimal 100,
also $100 indicates hexadecimal 100.
HEX HEX
ADDRESS LABEL CODE MNEMONICS COMMENTS
F31 BEG 53 DOA TTY Turn On Reader
F32 00
F33 BP 2 02 DBB Decrement B Register
F34 BF STB WSL Store "B" in Working
F35 3D | Store Lower
F36 TRR 4B SRS Skip if Reader Ready
F37 04
F38 CF JPC TRR Jump Back to See If
F39 36 Reader Ready
F3A 52 DIA TTY Input Reader Character to
F3B 00 the A Register
F3C AF STA XX Store the A Register
F3D WSL AF at WSL
F3E CE JPC BP2 Jump Back to
F3F 33 Get New Word
H-1
‚ 2
With the first fully punched line of the binary
loader -tape placed over the teletype reader pins
>
close the reader cap.
First Fully Punched Line
| kK—— Blank Tape
Reader Pins
FIGURE H-1
Follow the procedure outlined below to load the binary
loader program.
A. Set the "B" register to $00
Push "B" switch up ("A", "ENT" and "DIS" down).
Set "DB" switches to $00.
Depress and release "EXC" switch.
B. Set the "A" register to $11.
Push up only the "A" switch ("B", "ENT'" and "DIS" down).
Set the "DB" switches equal to $11.
Depress and release the "EXC" switch.
С. Set the "P" register to F3l.
Push down the "A", "B'", "ENT" and "DIS" switches.
Set the "PR" and "DB" switches to F31.
Depress and release the "EXC" switch.
D. Depress and release the "INIT" (Initialize) switch.
E. Depress and release the "Run" switch.
F. The computer will turn the reader on and start
loading tape.
SYSTEM FEATURES
Some of the standard features available with the
MICRO 400 central processor include:
Multi-Accumulator Arithmetic
105 Program Instructions
Up to 32 Peripheral Devices
Direct and Index Addressing
Memory Directly Addressable in 4096 pages
Two's Complement Arithmetic
Local Operator's Control Panel (removable)
Maintenance Programs
Utility Debug Programs
Full Line of Peripherals and Systems Interfaces
Microbus Interconnection
Programmed 1/0 bus
Priority Interrupts
Some of the optional features available with the
MICRO 400 central processor include:
Base Register Addressing to 65K Words
Automatic I/O
Power Fail Protection from Run or Halt
ORGANIZATION
The MICRO 400 is organized around a single bus and consists
of five 8-bit registers, two 12-bit registers and one 16-
bit register. All information transmitted within the
processor to and from all registers and to and from
memory is transmitted in parallel on one data bus.
The data on this bus at any one time are under the
control of logic in the central processor. When the
contents of one register are placed on the bus they
are presented to the inputs of all registers and
memory and are strobed into the proper destination
by the control unit. This organization optimizes
the MICRO 400 for maximum data throughtput and for
minimum elapsed time between successive bus trans-
fers. This unique organization makes possible
the MICRObus concept.
The core memory is modular in 1024 or 4096 byte
increments. Each module containing its own data and
address registers. Memory addressing may be extended
to 65,536 bytes with the Base Register Module option.
1-4
FIGURE 1
M400 CPU, MEMORY, POWER SUPPLY
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1-5
1
FRONT PANEL INTERCONNECT
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