Scientific Micro Systems OMTI 8000 Series Data Controller Reference Manual

 OMTI 8000 SERIES
IBM PC AT
INTELLIGENT DATA CONTROLLERS
REFERENCE MANUAL
JUNE 1986
Scientific Micro Systems. Inc.
OMTI 8000 SERIES
IBM PC AT
INTELLIGENT DATA CONTROLLERS
. REFERENCE MANUAL
JUNE 1986
PUBLICATION NO. 3001241
IBM PC AT
INTELLIGENT DATA CONTROLLERS
REFERENCE MANUAL
Models :
OMTI 8100
OMTT 8200
OMTI 8500
ONMTI 8600
SCIENTIFIC MICRO SYSTEMS, INC.
339 North Bernardo Aveaue
P.O. Box 7777
Mountain View
CALIFORNIA 94039
TEL: 615-964-5700
TWX: 910-3379-6577
TLX: 172555 SMS MNTV
FAX 415 964 4168
Copyright 1986 SCIENTIFIC MICRO SYSTEMS, INC.
Al Rights Reserved
PRINTED IN THE UNITED STATES OF AMERICA
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DOCUMENT NUMBER: 3001241
REVISION: D
Date of this Revisioc: June 20, 1956
OMTI 8000
TABLE OF CONTENTS
SECTION 1 : INTRODUCTION
1.1. Product Descnpnon
1.2. Number and Type of Dnives supported
1.3. Specificanon
SECTION 2 : CONFIGURATION AND INSTALLATION
=.1. Unpackang and Inspecnon
2.2. System Confiruranon
=.3. Board Preparanon
SECTION 3 : HOST ELECTRICAL INTERFACE
3.1. Inroducnon
3.2. VO Cnanne! Pin Assignmen:
3.3. VO Cnanne! Sirnai Descnpaon
3. 2 Conzolle: hHaroware Architecture
SECTION 4 : HOST/CONTROLLER SOFTWARE INTERFACE
«.1. Overvies:
4.2. Fixec Disk Registers
4.3. Fixed Disk Communicauon Protoco:
#. Fiopny Disk Kegisiers
+ 5. Fioppy Disk Protoco:
N £ : FIXED DISK FUNCTIONS
. Commanc Descnptor Block (COB)
. Control Bvte
. Status Register
. Fixed Disk Commands
SECTION 6 : FLOPPY DISK FUNCTIONS
6.1. Fioppy Disk Command Summary
6.2. Descnipoon of Symbols
65 Fioppv Commands
6.4. CommanZ Status Registers
APPENDIX A Sense Code Summary and Description
APPENDIX B lnterieave Scheme
APPENDIX C BIOS instaliation Procedure
LIST OF FIGURES
1.1 Funcnona! Organization (Block Diagram)
2.1 Connector ant Jumper Locations
LIST OF TABLES
1-1 Number and Type or drives supported
2-1 Jumper Assignments
2-2 Connector Assignment
2-3 LED Meaning
4-1 l'O Por: Addresses
4-2 l'O Regsters
4-3 Fioppy Disk Kegisters
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SECTION 1
INTRODUCTION
1.1. PRODUCT DESCRIPTION
The OMTI 8000 Series is a combination of Winchester disk and floppy disk controller for IBM AT
Bus compatible computers (16 bit data path). The OMTI 8000 Series is contained on a single PCB
th-* nlugs into an empty slot of the motherboard of the computer.
The OMTI 8000 Series uses SMS' scpticticated VLSI circuitry to provide many advanced features.
These include:
- Concurrent support for both ESDI (Enhanced Standard Drive Interface) and
ST412 compatible winchester disk drives
- Support for high capacity (1.6 Megabyte) floppies
- High performance (1:1 interleave on disk, 1.6 Megabyte/second transfer on AT Bus)
- SKbvte buffer minimum.
- 48 bit Error Correction Code on ESDI drives, 32 bit ECC on ST412 drives
- Concurrent data operations on winchester and floppy disk
- Supports both programmed I/O and DMA data transfers
The above and other features make the OMTI 8000 Series double controller an exceptional value
that many have come to expect from SMS’ family of data storage products.
BIOS issues : The OMT] 8000 Series 15 fully AT bus and hardware compatible but, because the
BIOS (Basic Input/Output System) is not contzined on the OMTI 8000, it is the host's
responsibility to ensure software compatibility. The BIOS on the IBM AT will operate correctly
with the floppy portion of the OMTI 8800 however in order to provide higher performance the
fixed disk command set differs from the IBM controller. The BIOS must therefore be modified to
support this enhanced command set and ensure full software compatibility.
As an option SMS provides two EPROMs BIOS to make the 8000 series fully compatible with the
IBM controller.
12 NUMBER AND TYPE OF DRIVES SUPPORTED
Table 1-1
Model 8100 8200 8500 8600
Number of drives 2 max 4 max 2 max 4 max
Winchesters up to 2 up to 2 upto2 upto2
ESDI drives no no supponed supported
Flexible disks 0 upto 2 0 upto2
8000 Series - Page 1-1
13 SPECIFICATION
131. Features per Peripherals
WINCHESTER DISKS.
- Operates one or two hard or soft sectored ST412 compatible or ESD] Winchester disk(s).
The disk can be fixed or removeable. ESD] drives may transfer dat at a rate of up to 10
Mbit/sec.
- Supports 256, 512, 1024 ог 1056 bytes/sector.
- Supports programmable sector interieave indudine a 1:1 interieave.
- Addresses up to 2045 tracks and 16 heads.
- Supports overlapped seek.
- Word (16 bits) width data transfer on AT bus.
- Supports both programmed 1/0 and DMA data transfers.
= =
FLOPPY DISKS
- Operates one or two floppy disk drives
- Supports 48, 96 TPI drives plus the high density AT compatible drives.
- Supports 250, 300, or 500 K bits:sec transfer rate including dual rotational speed fioppies
- Hos: has direct access to floppy disk controller chip (NEC76$ or equivalent)
1.3.2 Physical Specifications
Width 3.9 inches
Length 13.25 inches
Height .15 inches
8000 Series - Page 1-2
1.33 Environmenta! Specifications
Operating Storage
Temperature Ою 50 де; С 401075 deg C
Relanve Humidity 10 to 95% N.C. 10 to 905% Noncondensme
Maximum Wet Bulb 30 deg C Noncondensing
Alumide 0 to 10,000 ft 0 to 15,000 fr
1.34. Power Requirements
Voltage 4.75 to 5.25 Y DC
Maximum nipple anc noise 100 mv
Maximum current drawn 15 Amp
Figure 1.1
SYSTEM 1/0
CHANNE INTERFACE
Byte tc
word
Logic
i
Data /
Centre]
Ador ess
1/0 Decode
Legic
& Buffers
Buffered mest Data
OMTI 8000 Series
IBM PC AT Controller Block Diagram
8000 Seres - Page 1-3
SECTION?
CONFIGURATION AND INSTALLATION
~1 UNPACKING AND INSPECTION
Upon receipt of your ONT] 8000 Senes Data Controliers, inspec: the packaging for evidence of
damage dunn; transi. Open the package and inspect the controlier board for visibie damage such
as scraiches, loose components, or broken connectors. If there 15 damage, immediateiy notify the
camer's agent and Sciendfic Micro Systems’ customer service representative. Compare the items
listed on your ongina! Purchase Order to the actual contents of the package and the packang list
LI discrepencies exist, notify you SMS customer service representanve.
Retair the shipping conzmer and packing material for examination (if it has been damaged), or
for reuse when remming the controller board 10 the factory.
~2 SYSTEM CONFIGURATION
The OMT] 800C Senes Daz Controllers are designed to plug directly into anv unused location ог
the system motnerdoarc. Tne peripherals are connected to the controlier bv ribbon cabies.
After your board is mounted; connect the cabies to the disk drive. Refer to Figure 2-1 for the
locanon of connectors on vour board. Pan 1 on ali connectors is specified by a square soider pac,
visible on the soldered side of the board.
The connector's recommended part numbers are as follows:
J2 anc J7 - AMP P/N 88373-3 (-34pin)
J3 and J4 - ANP P/N 869041 (-20pin)
~3 BOARD PREPARATION |
The appropriate boarc lzyout, connecto: Jocations, and jumper locations for the OMTI 8000
Senes Controller are iliustarec in Figure 2-1. Use Table 2-1 to ensure tha: the factory insraliec
Jumpers are correctly In piace.
The OMTI 8000 Series has jumpers which allow the controller to be easily integrated into
differer: systems.
Jumpers W1 through W7 specify parameters of the system-controlier interface typically used by 2
BIOS.
Jumpers W8 through W15 specify drive paramer=rs to be used by the controlier.
Tabie 2-1 defines the jumpers in detail.
8000 Senes - Page 2-1
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= ©
JUMPERS se
Wil O wv
¥/o Wi
- 5
Fo
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CA
JUMPERS
523 24,25 TE | RAM
FLOPPY — Hi. ~~
CONNECTOR | - =
FINCHESTER <
CONNECTORS | | 2
N -
JUMPERS _| = —
F15 tt FE
= ©
~ ©
8
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-
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E Connector Key
Pin 15 on JZ
Pin 5 On J7
Figure 2.1 Connector end
Jumper locations
Jumper Assignments
0 = No jumper installed 1 = Jumper installed * = As shipped
Ww 4 ХЗ wz Wl D . fi . a
0 0 0 0 (Host assigns jumper value)
We WS WZ Winchester 10 port base address
0 01 0320x
0 1 1 032471
1 0 1 03287
1 1 1 032CH
0 о 0 01 Абу;
0 1 0 О! Аян
1 0 0 OLASH
1 1 О. 01ACY
W7 Flonnv did: TO nart base address
0 0370;
1* 03F0y
8000 Series - Page 2-3
WI WS Byies per sector
0” 0 512 (17 Sectors per track)
0 1 512 (18 Sectors per track)
] 0 1024 ( 9 Sectors per track)
] 1 1056 (9 Sectors per track)
LUNO | LUN 1
WI10 Sector type | W13 Sector type
|
0* Soft sectored | 0* Soft sectored
1 Hart sectored | 1 Hard sectored
|
WI11 Drive dass | W14 Drive dass
|
0* ST412 compatible | 0* ST412 compatible
| 1 ESDI compatible
|
1 ESDI compatible
W12 Drivetvpe | W15 Drivs type
|
0" Fixed | 0* Fixed
1 Removeable | 1 Removeable
W21, W23, W24, W25 Reserved
Table 2-2 Connector Assignment
J2 FIXED DISK (34 pin)
J3 FIXED DISK - LUN 0 (20 pin)
Já FIXED DISK - LUN ] (20 pin)
J7 FLOPPY DISK (34 pin)
LED Meaning
Self test diagnostics are run when the unit is powered on. If the LED goes out the diagnostics
have passed. If the self test detects a failure the LED will remain on.
8000 Series - Page 2-4
SECTION 3
HOST ELECTRICAL INTERFACE
3.1. INTRODUCTION
The OMTI 8000 Series are electricaliv and mechanically compatible with the bus or Input/Output
channel used in the IBM AT computer. Physically this Input/Output channel 1s contained on two
card edge connectors on the OMTI 8000 Senes.
The Input/Output channel provides the necessary hardware interface to the host CPU to allow и 10
communicate with the controller.
32 INPUT/QUTPUT CHANNEL PIN ASSIGNMENT
The following figures summarize pin assignments for the Input/Output channel] connectors.
INPUT/OUTPUT CHANNEL (COMPONENT SIDE of 62 pin EDGE CONNECTOR)
| VO Signal Name Input/Output |
| |
| Al -VO CHCK 1 |
| A2 SD7 VO |
| A3 SD6 VO |
| A4 SDS VO |
| AS $04 Vo |
| A6 SD3 VO |
| A7 SD2 VO |
| AB SD] Vo |
| AS SDO VO |
| AIO VO CH RDY 1 |
| All AEN O |
| Al SA19 VO |
| Al3 SAE VO |
| Ald SAl7 VO |
| AlS SAI6 Vo |
| Alb SAI1S VO |
| Al SAl4 VO |
| Ale SA3 Vo |
| AlS SAl2 VO |
| A20 SAll Vo |
| 421 SA10 Vo |
| AZ SAS VO |
| A23 SAE VO |
| A24 SA7 LO |
| A25 SA6 VO |
| A26 SAS VO |
| A27 SAL VO |
| A28 SA3 VO |
| A29 SA? VO |
| A30 SA1 VO |
| АЗ! SAO VO |
|
— 8000 Series - Page 3-1
Input/Output Channel (SOLDER SIDE of 62 pin EDGE CONNECTOR)
| VO Pin Signal Name VO
|
| Bi GND Ground
| B2 RESET DRV O
| B3 +5 Vdc Power
| B4 IRQ9 J
| BS -5 Vdc Power
| B6 DRQ2 1
| B7 -12 Vdc Power
| B8 -OWS I
| B9 +12 Vdc Power
| B10 GND Ground
| Bll -SMEMW O
| В12 -SMEMR O
| B13 -IOW VO
| Bl4 -JOR VO
| BIS -DACK3 O
| B16 DRQ3 I
| B17 -DACK] O
| B18 DRQ1 1
| B19 -Refresh VO
| B20 CLK O
| B21 IRQ7 I
| B2 IRQS 1
| B23 IRQS I
| B24 IRQs 1
| B25 IRQ3 J
| B26 -DACK2 O
| B27 TIC O
| B28 BALE O
| B2°C +5 Vdc Power
| B30 OSC O
| B31 GND Ground
|
8000 Series - Page 3-2
TZ A A DT EZ A A A MAA E EA ED A do A LD TL] LA E A a ea A ma E DD DD E E — nag. are SO
——
Input/Output Channe (COMPONENT SIDE of 36 pin EDGE CONNECTOR)
| VO Pin Signal Name VO
|
| CI -SBHE VO
| C2 LA23 VO
| C3 LA22 VO
| C4 LA2] VO
| CS LA20 VO
| C6 LA19 VO
ji C7 LA18 VO
| C8 LA17 VO
| C9 -MEMR VO
| C10 -MEMW Vo
| Cl] SDOS Vo
| C12 SDO9 VO
| C13 SD10 Vo
| Clé SD11 Vo
| C15 SD12 VO
| C16 SD13 VO
| C17 SD14 VO
| C18 SDI15 VO
|
Input/Output Channel (SOLDER SIDE of 36 pin EDGE CONNECTOR)
STD a EL A a M— G— AA CNT —— ——— — —;—— — ES mt AE «Шт
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VO Pin Signal Name vo
Di -MEM CS16 I
D2 -VO CS 16 1
D3 IRQ10 I
D4 IRQI1 I
DS IRQ12 I
D6 IRQ13 I
D7 IRQI4 - I
Dg -DACKO O
D9 DRQO 1
D10 -DACKS O
11. DROS }
D12 -DACK6 O
D13 DROS6 I
D14 -DACK7 O
D15 DRQ7 1
D16 +5 Vdc Power
D17 «MASTER I
D18 GND GND
TE lili Gi das o dio — — SR Sa a E Di CD da SE ii Sn одна
8000 Senes - Page 3-3
33 INPUT/QUTPUT CHANNEL SIGNAL DESCRIPTION
The following is a description of the system board s INPUT/OUTPUT channel signals. All signal
lines are TTL-compatible. Input’Output adapters should be designed with a maximum of two
jow-power Shottky (LS) loads per line.
SAO through SA19 (Input/Output)
Address bits O through 19 are used to address memory anc Input/Output devices within the
system. These 20 address lines. in addition to LA 17 through LA23, allow access of up to 16Mb
of memory. SAO through SA19 are gated on the svstem bus when "BALE" is high and arc
latched on the falling edge of "BALE." These signals are generated by the microprocessor Or
DMA Controller. They also may be driven by other microprocessors or DMA controllers that
reside on the Input/Output channel.
LA17 through LA23 (Input/Output)
These signals (unlaiched) are used to address memory and Input/Output devices within the
svstem. They give the system up 10 16Mb of addressability. These signals are vaiid when
“BALE” is high. LA17 through LA23 are not latched dunng microprocessor cycles and therefore
do not stay valid for the whole cycle. Their purpose is to generate memory decodes for 1 wait-
state memory cycles. These decodes should be latched by Input/Output adapters on the falling
edge of "BALE." These signals also may be driven by other microprocessors or DMA controllers
that reside on the Input/Output channel. Note that it 15 these signals that are decoded by the
Input/Output adapter to generate "MEM CS16" for 16 bit, 1 wait -state memory cycles.
CLK (Output)
This is the 6-MHz system clock. It is 2 synchronous microprocessor cycle clock with a cycle time
of 16° nanoseconds. The clock has a 50% duty cycle. This signal should only be used for
synchronization. Ii is not intended for uses requiring a fixed frequency. |
RESET DRY (Output)
“Reset drive" is used to reset or initialize system logic at power-up ume or during a low line-
voliage outage. This signal 1s active high.
SDY through SD15 (Input/Output) ‘
These signals provide bus bits O through 15 for the microprocessor, memory, and Input/Output
devices. DO is the least-significant bit and DIS is the most significant bit. All &-bit devices on
the Input/Output channel should use DO through D7 for communications to the microprocessor.
The 16-bit devices will use DO through DIS. To support 8-bit devices, the cata on DE through
D:$ will be gated to DO through D7 during 8-bit transfers 10 these devices; 10-bit microprocessor
transfers to $-bit devices will be converted to two 6-bit transfers.
BALE (Output)(buffered)
" Address latch enable" is provided by the 82288 Bus Controller ant is used on the system board
to laten valid addresses and memorv decodes from the microprocessor. It is available to the
Inpu: Output channel as an indicator of 2 valid microprocessor or DMA address (when used with
AEN"). Microprocessor addresses SAO through SA19 are latched with the falling edge of
“BALE” "BALE" is forced high during DMA cycles. Note: that "BALE" is usually used by the
10 adapter only to lawch the LA17-LAZS adaress lines (or the decode of LA17-LA23 that indicates
an address match for the JO adapter). "BALE" may not occur on all E-bit InpuYOurput cycles
(which use only address lines SAO-SA9 for device decoding) or on some §-bit memory transfers.
8000 Series - Page 3-5
Input’ Output CH RDY' (Input)
"Input/Output channel ready” is pulied low (not ready) by a memory or Input/Output device 10
lengthen Input/Output memory cvcles. Any slow device using this line should drive 1t low
immediately upon detecting its valid address and a Read or Write command. Machine cycles are
extended by an integral number of clock cycles (167 nanoseconds). This signal should be held
Jow for no more than 2.5 microseconds.
IRQUIRQ7. IRQ9-IRQ12 and IRQ 14 through 15 (Input)
Interrupt Requests 3 through 7, 9 through 12, and 14 through are used to signal the
microprocessor that an Input/Output device needs attention. This interrupt requests are
priorinzed, with JRQY through IRQ 12 and IRQ 14 through IRQ15 having the highest priority
(IRQ9 is the highest) and IRQ3 through IRQ7 having the lowest priority (IRQ7 15 the lowest).
An interrupt request is generated when an IRQ ime is raised from low to high. The line must be
held high until the microprocessor acknowledges the interrupt request (Interrupt Service routine).
Interrupt 13 is used on the system board and is not availabie on the Input/Output channel.
Interrupt 8 is used for the real-ume clock.
-JOR (Input/Output)
‘Input/Output Read’ instructs an Input/Output device to drive its data onto the daiabus. lt may be
driven bv the system microprocessor or DMA controller, or by a microprocessor or DMA
controller resident on the Input/Output channel. This signal 15 acuve low.
-JOW (Input/Output)
“Input/Output Write" instructs an Input/Output device to read the data on the data bus. lt may be
driven by any microprocessor or DMA controlier inthe system. This signal 15 active low.
-SMEMR (Output) -MEMR (Input/Output)
These signals instruct the memory devices to drive datz onto the data bus. "-SMEMR" 15 active
oniv when the memory decode is within the low 1Mb of memory space. "-MEMR" is active on
all memory read cycles. "-MEMR" may be driven by any microprocessor or DMA controller in
the svstem. -SMEMR" is derived from ".MEMR" and the decode of the low 1 Mb of memory.
When a microprocessor on the Input/Output channel wishes to drive "-MEMR". it must have the
address lines valid on the bus fo: one system clock period before driving *-M EMR active. Both
signals are active LOW.
SMEMW (Output) -MEMW (Input/Output)
These signals instruct the memory devices to store the data present on the data bus. "-SMEMW™
is active onlv when the memory decode is within the low 1M» of the memory space. "-MEMW”
is active on all memory read cvcles. “-MEMW™ may be driven by any microprocessor or DMA
controlier in the system. "-SMEMW” is denved from ".MEMW" and the decodz of the low 1Mb
of memory. When = microprocessor on the Input/Output channel wishes to drive "-MEMW" 11
must have the adcress lines valid on the bus for one system clock period before driving “-
MEMW" active. Both signals are active low.
DRQ0-DRQ3 and DROS-DRO7 (Input) :
DMA Requests O through 3 and 5 through 7 are asynchronous channel requests used by
peripheral devices and the Input/Output channel microprocessors to gain DMA service (or conto!
of the system). They are prioritizec, with "DRQO" aving the highes: priority and "DRQ7" having
the lowest. A request is generated by bringing a DRQ line 10 an acuve ievel. A DRQ line must be
held high until the corresponding "DMA Request Acknowledge” (DACK) line goes active.
"DRQO" through "DRQ3" will perform 8-bit DMA transfers: "DRQS" through "DRQ7T" will
perform 16-bit transfers. "DRQ4" 1s used on the system board and is no: availabie on the
Input/Output channel.
8000 Series - Page 3-5
-DACK to -DACK3 and -DACKS to -DACK7 (Output)
-DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests (DRQ) through
DRQ?7). They are active low.
AEN (Output)
“Address Enable" 15 used to degate the microprocessor and other devices from the Input/Output
channel 10 allow DMA transfers to take place. When this line is active, the DMA controlier has
control of the address bus, the data-bus READ command Lines (memory and Input/Output, and
the Write command Lines (memory and Input/Output).
-REFRESH (Input/Output)
This signal 1s used to indicate a refresh cycle and can be driven by a microprocessor on the
Input/Output channel.
T/C (Output)
“Terminal Count” provides a pulse when the terminal count for any DMA channel is reached.
-SBHE (Input/Output)
"Bus High Enable” indicates a transfer of data on the upper byte of the data bus, SDS through
SD15. Sixteen-bit devices use "-SBHE" to condition data bus buffers tied to SD8 through SD15.
-SBHE AND SAO ENCODINGS:
-SBHE SAO FUNCTION
0 0 WORD TRANSFER
0 ] BYTE TRANSFER ON SD8-SD15
] 0 BYTE TRANSFER ON SDO-SD7
1 RESERVED
-MASTER (Input)
This signal 15 used with DRQ line to gain control of the system. A processor or DMA controller
on the Input/Output channel may issu 2a DRQ to 2 DMA channel in cascade mode aná receive z "-
DACK”. Upon receiving the "-DACK", an Input/Output microprocessor may pull "-MASTER"
low, which will allow it 10 contro! the system address, datz, and contro! lines (2 condition known
as tri-stale). After -MASTER" is low, the Input/Output microprocessor must wait one system
clock period before driving the address and datz lines, and two ciock periods before issuing 2
Kead or Write command. If this signa! is held low for more than 15 microseconds, system
memory may be lost because of a lack of refresh.
-MEM CS16 (Input)
"-MEM16 Chip Select” signals the system board if the present data transfer is 2 1 wait-state, 16-
‘bit memory cycle. It mus: be derived from the decode of LA17 through LA23. Note that this
requires tha: al] 16-t:1 memorv devices must occupy at least 128 kbyies of address space on the
Bus anc must not decode the SA address lines as a condition to driving “-MEM CS16” as the SA
lines are not valid in ume to meet the "-MEM CS16" timing reguirements. "-MEM CS16" should
be driven with an open-collector or tri-state driver capable of sinking 20 mA.
8000 Series - Page 3-6
-Input/Output CS16 (Input)
"Input/Output 16 bit Chip Select” signals the system board that the present data transfer 1s a 16-
bit, 1 wait-state, Input/Output cycle. It is derived from an address decode. "Input/Output CS16”
is active low and should be driven with an open collector or tri-state driver capable of sinking
20mA.
OSC (Output)
"Oscillator (OSC) is a high-speed clock with a 70 nanosecond period (14.31818 MHz). This
signal is not synchronous with the system clock. lt has a 50% duty cycle.
-OWS (Input)
The "Zero Wait State" (-OWS) signal tells the microprocessor that it can complete the present bus
cvcle without inserting any additonal wait cycles. In order to run a memory cvcle to a 16-bit
device without wait cycles, "-OWS" is derived from an address decode gated with a Read or
Write command. In order to run 2 memory cycie to an 6-bit device with a minimum of two wait
states, "-OWS" should be driven active one system clock after the Read or Write command 1s
active gated with the address decode for the device. Memory Read and Write commands to an 5-
bit device are active on the falling edge of the system clock. Note that "-OWS5” must be
synchronous to the system clock (CLK) and meet specific set-up ant hold timing requirements to
prevent undesirable system malfunction. (see secnon 3.1.2.) "-OWS" is active low and should be
driven with an open coliector or tri-state driver capable of sinkang 20mA.
3.4 CONTROLLER HARDWARE ARCHITECTURE
The OMTI 800 Series are partitioned into two distinct sections - the fioppy disk logic anc the
Winchester disk: logic. These two sections share th: same physical PCB boarc but are otherwise
independent This aliows full concurrent operations between these two sections. For example,
DMA data transfer could be occurTing a: the same time programmed Input/Output datz transfers are
occurring on the fixed disk.
8000 Series - Page 3-7
SECTION 4
HOST/CONTROLLER SOFTWARE INTERFACE
4.1 OVERVIEW
From the perspective of sofrware executing on the host the OMTI 8000 Series look like two
independent controliers
- one controller for the floppy disk
- and one controller for the fixed disk. |
The host communicates with the OMTI 8000 Senes through two independent sets of registers
- One set for the floppy
- and the Other set for the fixed disk.
The host can issue commands, such as READ, via these registers following a specific protocol.
A typical sequence of events for the host to issue commands to the OMTTI 8000 Series controller
would be :
1) Set up a "Command Descriptor Block" or CDB in memory which contains information
required by the controlier.
2) Send the CDB to the controller by writing it one byte at a time to the 1O register.
3) Receive or send data if required via programmed 1/0 or DMA.
4) Receive status via the VO register set
A list of commands, their functions and the forma: of the CDB 15 given in:
Section 5 for the Fixed disk,
Section 6 for the Floppy disk,
The following sections describe the two register sets anc the prococol the host mus! follow when
reading or wntng these registers.
42 FIXED DISK REGISTERS
There are four registers (or VO ports) that the host uses to access the fixed disk. The registers have
different meanings when. they are read or writter.. Tnese recisters are normally located ar the l'O
address listed in table 4-2 but maybe altered by jumpers described in Section 2. Table 4-1 list these
registers ang table 4-2 describes these registers in more detail.
8000 Senes - Page 4-1
Table 4-1 OMTI 8000 Series VO Port Addresses
REGISTERS
PORT | READ | WRITE
320H | DATA IN ¡DATA OUT
3215 | STATUS | RESET (Function)
322H | CONFIGURATION | SELECT (Function)
323 IN/A | MASK
Table 4-2 OMTI 8000 Series VO Registers
REGISTER
DEFINITION
Data-InTnis 15 an 6 or 16 bit register depending on the state of the controlier (determined by the
Data Out
Status
C/D bitin the STATUS register). It is used to read data a word at a time, or status
(no: SENSE data) a bvte at 2 ime. When the C/D bit is 1 only bits 0-7 are valid.
When C/D 15 0 all 16 bits are valid with bits 6-15 containing byte 1 and bits 0-7
containing byte 0.
This 15 an 6 bit o7 16 bit register depending on the state of the controller
(determinec by the C/D bit in the STATUS register). It is used to write data a word
l 2 nme or commands a byte at a time. When the C/D bit is 1 only bits 0-7 are
valid When C/D 1s Oall bits are valid with bits 8-15 containing byte 1 and bits 0-7
containing byte 0.
Used to send bit significant contro! information from the controller to the system.
B1: 7 Not Used (Set to 1) Bit 6 Not Used (Set to 1) Bit § IREQ (Interrupt Request?)
0 = No Interrupt
] = Command Complete
L the Interrupt Enable bit of the MASK byte has been previously set, this bit is
set when the controlier enters the STATUS State. Thus bit is set with IRQ14 on
the System Bit 4 DREQ (DMA Request)
О = No DMA Kegues:
1 = ОМА Сус!е Requested
If the DMA ENABLE bit of the MASK BYTE has been previousiv set, and if the
controller 1s in the DATA State, this bit 1 se: along with DRQ3 on the System Bus
when z byte transfer 15 required to or from the system.
B1:5 BSY (Busy)
U= Controller is Idie
1 = Controller Selected
Bi: 2 C/D (Command Data)
0 = Word being transferred is date status.
1 = Byte being transferred is a command or status byte
NOTE: This bit can be used to determine if word or byte transfers are being done.
When C/D 1s | then only bits 0-7 are used in the Data In or Date Out register.
When CD 15 0 then all 16 bits in the Data In and Data Out register zre valid. In this
case byte 015 in bits 8-15 anc byre ] is in bits 0-7.
8000 Senes - Page 4-2
CONFIG-
URATION
SELECT
MASK
Bit 1 VO (In/Out)
0 = Direction of transfer is from the host to the controller.
1 = Direction of mansfer is from the controlier to the Host
Bit 0 REQ (Request)
0 = No Transfer Required
1 = Request transfer of one byte or Word via Data In 07 Data Out register.
Writing any value to this register will cause the controller to be reset
WARNING The host mast wait 100 usec after 8 -RESET before
issuing a SELECT.
Used to send the status of the drive configuration jumpers to the system
Typically, these are used by 2 BIOS to specify the type of drive(s) anacned to the
controller.
Bits 7-4 = not used (Set to 1)
Ви 3 = W4
В1: 2 = W3
Bit] = W2
Bit0=W]
Writing anv value to this register will cause the controller to begin a Selecuon
Sequence and request a command transfer.
Enables and disables interrupts anc DMA transfers.
Bits 7-2 Not used.
Bit] INTERRUPT ENABLE
0 = No system interrupt at data transfer completion.
1 = System interrupt at data transfer completion.
Bit0 DMAENABLE
0 = DMA not enabled. (Programmed VO mode)
1 = DREQ is gated onto system bus on DRQ3 and DREQ set in STATUS
register
43 FIXED DISK COMMUNICATION PROTOCOL
The fixed disk portion of the OMT] 8000 Series has six logical states which the host sequences
through wher issuing command. These sates are ©
IDLE
SELECTION
DATA
STATUS
The RESET STATE is entered by applving power to the controlier (power - on -rese1). by the reset
signa! on the system bus, Or by wnting the RESET Recister (por 321). During this phase. tne
conzolier will initialize itself. will se: default parameters (ST412) to the LUNs, will de-asseri all
contro! functions ané ciear al} bits in the STATUS register. It will then enter the 1Cie siate.
WARNING: The host must wait 100 usec after a -RESET before issuing a SELECT.
8000 Senes - Page 4-3
The IDLE STATE is the only time the controller will respon to 2 select request. When the
SELECT register (port 322) is wntten by the system, the controller enters the seiechon state.
During the SELECTION STATE, the controller responds to a selection request bv asserung the
BSY bit (bit 3) in the STATUS register (port 321). The controller then enters the command state.
The COMMAND STATE is when the controller requests the command bytes to be transferred
from the system. Firs, the C/D bit (bit 2) of the STATUS register is sei. Then the REQ bit (bit 0)
of the STATUS register is set, asking for the first command byte to be written to the DATA OUT
register (port 320) in BYTE mode (bits 0-7). When the command byte is wnten. the controlier de-
asserts the REQ bit and moves the command byte into its buffer. This handshakang 15 repeated
until ali command bytes are transferred. C/D is then de-asserted and the data state 1s entered.
The DATA STATE is when data is transferred to or from the system. If no datz is required. the
status state is entered. Data can be rransferred in either programmed mode VO mode or DMA word
mode, as defined by the DMA ENABLE bit in the MASK register. In the programmed VO mode,
data is transferred by handshaking in the same fashion as the command transfer. When the
controlier requires a word to be transferred, it will set the REQ bit in the STATUS byte.
Depending on the direction of transfer (as defined by the VO bit in the STATUS byte), the system
must either write a word to the DATA OUT register or read a word from the DATA IN register.
Either action will cause REQ to be cleared. These steps will be repeated until ali the data required
by the controller has been transferred.
If the DMA ENABLE bit in the MASK byte has been previously set, data will be transferred in
DMA mode. When the controlier requires a word to be transferred. it will set the DRQ7 bit on the
svstem bus, requesting 2 DMA cycle. Tne DREQ bit of the STATUS byte is also set After the
de:z word has been transferred, DACK7 from the system will clear DRQ7. The DMA transfer will
proceed in this fashion until ali of the data required by the controller has been ransferrec.
During the STATUS STATE. the controller will place a STATUS register in the datz in register
bits 0-7. See Secnon 5.3 for detailed information on the STATUS byte.
The controller sets the C/D bit and the VO bit in the STATUS byte. If the INTERRUPT ENABLE
bit was previousiv set in the MASK register, the REQ bit is set in the STATUS bvte, along with
TRQ14 on the system bus. When the STATUS byte is read from the DATA IN register, the
controller ciears the IREQ and IRQI4 (if enabled), clears CD, VO, anc BSY bits in the STATUS
Kegisters, and enters the 1die state.
8000 Senes - Page 4-4
44 FLOPPY DISK REGISTERS
There are five IO registers (eight bits) which the host accesses to communicate with the floppy
disk poruons of the OMT] 8000 Seres controlier. Tne address of these registers is selectable (re:
Section 3) to be either at the primary or secondary location as shown m table 4-3.
Table 4-3
| I’O Address | | |
| Primary Secondary | Read | Write |
{ |
| | | | |
| 3F2H | 3725 | N/A | Digital Output |
E
| 3F4H | 374 | Main Status | N/A |
a
| 3F5H | 3751 | Data Register | Data Register |
| | | | |
| 3F6H | 376H | N/A | Additonal Control |
ha E
| 3F7H | 377 | Digital Input | Diskette Control |
| | | Register | Register |
| |
The host uses the Main Status Register and Datz Register 10 issue commands to and receive status
from the controller. The Digital Input, Digital Output and Diskette Contro! Register, Additional
Control Registers are used to contro) the specific drive functions as shown:
Kegister — Definition
Drgnal Output This 15 an output only register Used 10 CONDO, Grve MOIOTS, anve seiecuon,
intermupts’DMA and reset. All bits arecieared when a channel reset occurs.
Bit 7
B:: €
E: 5
E::4
E:: 3
Bi: 2
Bi: ]
B:: 0
Reserved
Reserved
Drive B Moto: Enable when 1
Dive A Motor Enable when 1
Interru>:s and DMA enable when 1
Kese: 1:0ppy disk function when 0. The floppy disk function comes outof
rese: wnen this bit 15 se: to ]
Keserved
Seiect Dnive-A. A 0 selects drive A, 2 1 selects drive B
Digital Input This 15 an input only register used by the host to ge: fioppy drive information
Ви 7 This bit is received from pir. 34 of the floppy disk control cable and is
nomally usec for diskene change status.
Bits O through 6 are Reserved.
8000 Series - Page 4-5
Diskette Control This is an output only register which givesthe controller data rate
information. All bits are cleared when a channel reset occurs.
Bits 2-7 Reserved.
Bits 10 Data Rate
0 0 500 Kbits/sec
0 1 300 Kbits/sec
10 250 Kbits/sec
1 1 Reserved
Additional
Control The diskette additional control register is an output-only register user to
control the fioppy write precompensation anc the disk dnve dual motor
speed control.
Bit 7 Reserved
Bit 6 Reserved
Bit S Floppy Interface Pin 6
Bit 4 Fioppy Interface Pin 4
Bit3 Fioppy Interface Pin 2 (Dual Speed Fioppy Control)
Bi: 2 Fioppy Write Precompensation 2
Bit 1 Fioppy Write Precompensation ]
Bit 0 Fioppy Write Precompensation 0
FLOPPY WRITE PRECOMPENSATION TABLE
BITS 0-2 FLOPPY DISKETTE DATA RATE
PRECOMPBIT S00KBPI 300KBPI 250RBPI
2 1 0 PRECOMP PRECOMP PRECOMP
0 0 0 Ons Ons Ons
0 0 1 62.5ns 104.2ns 125ns
0 1 0 12515 20€.3ns 250ns
0 1 1 187.5ns 312.5ns 375ns
1 0 0 250ns 416.7ns 500ns
1 0 1 250ns 416.7ns 500ms
1 1 0 312.5ns 520.6ns 625ns
1 1 1 312.5ns 520.8п5 625ns
Al bits in this register are cleared by a channel reset to insure compatability with other controllers.
Main Status
This is a read only register used in conjuntion with the Data register to transfer
command to the controller.
Bit 7 Reoues: fo: Master (RQM). Indicates that the datz register 1s ready to
send or receive date This bit must be used by the host to perform handshaking
functions between the host anc controlier. This bit is cicarec by reading or
writing the Da:2 Kegister.
Bir 6 Date In/Out (DIO) indicates direcuon of datz transfer. 17 DIO = ] then
transfer is from the Date Register to the hos: 1 DIO = 0 then 1: is from the host
to tne Data Register.
8000 Series - Page 4-6
Bit5 Non-DMA mods when 1. This can occur only dunng execution phase.
Bit4 When 1 the controller is busy executing a command.
Bit 3,2 Reserved
Bit! Drive B is in the Seek mode when 1.
BitO Drive A is in the Seck mode when 1.
Data This register is used to transfer information to/from the host. This register can
be logically viewed as several registers in a stack with only one presented al any
ume. Data bvtes are read out of or written into the Data register in order to
program a command or obtain the results after the execunon 0! a command.
4.5 FLOPPY DISK PROTOCOL
The host sends commands to the controller by sending several bytes of informauon to the
controlier (via the Data register) synchronized with bis 6 and 7 in the Status register. Tne sending
of command data is caliec the command phase. The controller then goes "Busy" and executes the
command (the command phase). Upon completion of the command the controlier becomes ‘noi
busy" and results may be obtained from the Data register again synchronized with bit 6 anc 7 in the
Status register. Fioppy commands, parameters and results are listec in secuon 6.0.
8000 Senes - Page 4-7
SECTION §
FIXED DISK FUNCTIONS
5.1 COMMANDS
5.L1 COMMAND DESCRIPTOR BLOCK (CDB)
The processor specifies the operation or command to be executed by the controller bv sending 6
or 10 bytes calied a Command Descriptor Block (CDB) as foliows -
6 Byte COMMAND FORMAT
Bit | 7 | 6 | Ss | 4 | 3 | 2 | 2] 0 |
Byte | | | | | | | |
O | Command Class | Operation Code |
— !
1 | CM | O | LUN | Head Number |
— |
21 C09 | Cos | Sector Number |
] ——
3 | Cylinder low (C 07-C 00) |
4 | | Interieave or Biock Count |
—
5 | Control Byte ~~ ° |
Byre O Bits 7,6 and § identify the class of the command. I
Bits 4,3,2,1, O contain the command Opcode.
Byte 1 Bi: 7 identifies bit 10 of the disk Cylinder number (MSB)
E:: 6 15 no! used.
B:: 5 identifies the Logica) Unit Number (LUN).
Bits 4,3,2,1, O contain tne disk head number to be selected.
Byte 2 Bits 7 and 6 conzain bits 9 and & respectively of the disk cylinder number.
Bits 5,4,3,2,1, 0 contain the disk sector number
Byte 3 Bits 7,€,5,4,3,2,1, O are the eight Jeast significant bits of the disk cylinder number.
Byte 4 Bits 765,422.11. 0 specify the Interleave Factor for the FORMAT command or
tne Biock Count for disk VO commands.
Byte 5 Bits 7,6,5 contain the command Control Byte.
Bits 4,3,2,1,0 are not used.
Refe: to the COPY command for the forma: of the 10 byte CDB.
8000 Series - Page 5-1
£12 COMMAND SET SUMMARY
COMMANDS COMMON to ALL MODELS
COMMANDS CODE Length in Bvies (b) or Blocks (B)
(HEX) COMMAND DATA
TEST DRIVE READY 00 6 0
RECALIBRATE 01 6 0
REQUEST SENSE 03 6 4(b)
FORMAT DRIVE 04 6 0
READ VERIFY 05 6 0
FORMAT TRACK 06 6 0
FORMAT BAD TRACK 07 6 0
READ 08 6 1-256(B)
WRITE 0A 6 1-256(B)
SEER ОВ 6 0
READ ECC BURST ERROR LENGTH 0D 6 1(b)
READ DATA FROM SECTOR BUFFER = 6 1(B)
WRITE DATA TO SECTOR BUFFER OF 6 1(B)
ASSIGN ALTERNATE TRACK 11 6 4(b)
CHANGE CARTRIDGE 1B 6 0
READ DATA TO BUFFER 1E 6 Up to buffer size
WRITE DATA FROM BUFFER 1F 6 Up to buffer size
COPY 20 10 1-256(B)
RAM DIAGNOSTICS EO 6 0
READ ID E2 6 4(b)
DRIVE DIAGNOSTIC E3 6 0
CONTROLLER INT. DIAGNOSTIC Ел 6 0
READ LONG ES 6 1(B)+4 or 6(b)
WRITE LONG E6 6 1(B)+4 or 6(d)
COMMAND SPECIFIC to the STS06/412 drievs
INITIALIZE DRIVE CHARACTERISTICS OC 6 8(b)
COMMANDS SPECIFIC to the ESDI drives.
CHECK TRACK FORMAT 10 6 0
READ ESDIDZFECT LIST 37 6 256 (b)
READ CAPACITY EC 6 100)
8000 Series - Page 5-2
2 CONTROL BYTE
The Command Contro: Bvte is the las: Byte in the CDB. It specifies the eo: TECOVETY procedure
dune the command execunoc.
CONTROL BYTE FORMAT
Bi: :
|
U dA 1) 03 My
Bi: 7
Bis §
>
R i EBI с | x x | SS S
= RETRY option
= ECC option on daz ECC erro: (READ command)
= FORMAT BUFFER opuor.
= PHYSICAL ADDRESS CONVERSION opuon
= Don't are
= STEP Opzon
(RY DISABLE RETRY. ¥ this bit is se: to 1, the controlier will no: perform ans remes.
Upoa encounterme an eror, tne conolier Will tertmunate the command Dv indicauns tna: gn
€or occured 1 Ins Stans register Bit 7 1s valid for those commands involvinc remes.
1 ts bit1s ser to C. tne controlie- will perform up 10 8 remes. 1 any of the remes 1s
successfull, the coNTOLE- wil 42001 10 Process tne next recuestes biock (if any). If me
TE=165 25€ NO! successful. the convolier wil teminate the COMmans Бу ndicanng tha: an
€ToT occured 1 the Stns register
The remy algontars 15 ¢ remes, 1 recalibration, 4 remes.
(E) DISABLE ECC (Error Correction Code. valid durine READ commands) If this bi: is
E: 10 1, the cosrolie will terminar: the commanc upon encountenne az ECC empor zer
periosmung remes (i enabled: Y the dara error 1s correctable, the correctes dat 15
transferred to the hos.
D thus bit is set to C, the conrrolier enabies Its error correction scheme (ECC ) for reac
remes. The convolier wil terminate the commanc upon encountening zn uncomesz sie ECC
error after performung resis (i enabled). If no errors occur, the command 15 termunzies
WILE NO error reporte in the Sanus register.
(B) ENABLE FORMAT BUFFER If this bit is ser 10 1. the controller will use the daz
conned in the controlier ca buffer when formztung each den fiel£ No daz is ansierrec
from the host gunine the FORMAT command A WRITE DATA BUFFER command should
be issued prior Lo tre FORMAT command to specify the dez Перс
If this bit 15 ser 1 0), the controller wili write a "6H parem ın each dae field dunng z
FORMAT command.
(C) ENABLE SECTOR ADDRESS CONVERSION. 1f this bit is se: 10 2. ne conrolie-
“iL perform à sector address CONVETSION Dased Oz 16 heads pe- cviinde-. The numper 0“
$SCLOCS рег rack uses in tne conversion is bases On the SECTORS PER TRACK Jumpers
(W10 and WY; see Tabis. This Conversion is useft] when thems is 2 Cifferen: number of
$105 per Track (ESDI ) than the DOS is using (17).
1 this bir 15 ser 10 0, me conrouer will NOT conver: the sector address contained in the
CDB.
8000 Series - Page 5-3
Waming : The INITIALIZE DRIVE CHARACTERISTICS command (OCH) must include the true
number o“ heads value of the d-ive (no: 16 as used fo: the conversion).
Bits 2,1,0. These bits define the STEP option as follows :.
Bis 2 1 0
0 0 0 3 milliseconds per step.
0 0 1 10 microseconds, buffered step
0 1 0 25 microseconds, buffered step
0 1 ] 50 microseconds, buffered step
1 0 0 200 microseconds, buffered step
1 0 1 70 microseconds, buffered step
1 1 0 3 milliseconds per step
1 ] 1
5 miliseconds per step
3 STATUS REGISTER
Stars is avaliable to the hos: in the Datz Register during the Status State at the end of a command.
К mdicates whether or not an ero- Was detected during executor of the command.
B:l 7161 5 | о L 2 1 1 1 |
| 0 1 0 LUN | 0 1 STE Ге | 0 |
E = Command status
Bit 1 € - Command status. À value of zero indicates à successfully compisted command. A
value of one indicates an abnormal condibon was encountered gurmg the command
execunon and caused command terminanon anc ending sims with the Commend
Status Condition (bit 1) set to one.
$ = Error Recovery Status
Bi: 2,3 (S) Erro: Recovery Status (valid only for commands which read dar from the disk)
Bit 32
0 0 No CITO? recovery
О 1 One rery accomplished
10 Mort thar one retry accomplished successfully
1 1 Error correction done successfully
NOTE: Oz multiple sector transfers, these bits wil refiect the worst ECC Rery
CounvCorrection. 1 one Rerry is done successfully on more than one SECIO:, then
Bits 3,2=01 respecuvely. If more than one Retry is done successfully on at leas:
one sector, then bir 3,2 = 10 respecuvely. If ECC was applet on any secto-
regardiess of the Rerry count, bits 3,2=11 respectively.
Bit 5 Indicates the LUN address of the device associated with this command.
Bits 7,6,4,0. Set to zero.
8000 Series - Page 5-4
5.4 FIXED DISK COMMANDS
The following commands can be issued to the controller.
5.4.1 TEST DRIVE READY Command (005)
This command selects the LUN specified and retums a zero status in the Status Register to indicate
that the unit is selected, ready and seek (ST drives) or seek/command (ESDI drives) is complete. in
the case of a unit with a removable disk, zero status also indicates that a carmdge is instalied. The
controller will wait up to 50 seconds for the drive to come ready.
Bt] 7 | 6 | 5 | 4 | 31 2. 1. 1. 1 0 |
Byte | | | | | | | | |
ор 0 0 0 0 0 о о e |
Do O0 | LUN O 0 0 0 о |
2 pla 5 | Zero value |
"Te щи
5.42 RECALIBRATE Command (01y)
ST drives : The drive specified by the LUN is stepped toward the outside cylinder unn either:
1. Track Zero signal 1s detected or
2. More steps have been issued than available cylinders for the device type.
The controlier issues one step pulse, waits for seek complete, and tests the Track 000 signal.
For LUNs assigned as Removable drive the RECALIBRATE command is performed by issuing
the number of step pulses equal to the number of cylinders specified for this dnve plus © at the
buffered rate anc then wainng for the Track 000 signal.
ESDI drives : This command selects the LUN specified and issues a recalibrate to cylinder zero.
Bal 7 | 6 | 5S | 4 | 3 1 2 1 1. 1 0O |
Byre | | | | | | | | |
ог 0 0 0 0 0 о 0 1
] | 0 о | LUN O 0 0 0 0 |
2 | Zero value |
3 | Zero value |
4 | Zero value |
51 o 0 0 0 0 | $ S s |
8000 Series - Page 5-5
5.4.3 REQUEST SENSE Command (03y)
Tnis command retums four sense bytes of information for the specifie¢ Logical Unit Number
during the Data In phase of the command execution. The sense is valid for the Command Status
(e) just presented to the host dunng the Status Suate of the previous unsuccessfully completed
command. Sense datz will be cleared upon reception of any subsequent command issued to the
controller.
The Error code byte (Byte 0) of the Sense Data 15 always valid. however, the sector address
(defined by bvtes 1, 2 and 3) 1s only valid if the previous command terminatec in CITO. Bit 7 set 10
] indicates the valıditv of the sector address. If bit 7 is set to 0, the sector address is not valid. Four
sense bytes are retwrned dunng the Dat In State of the command execution.
Bi| 7 | 6 | 5 ji 4 |] 3 1 2} |
Byte | | | | | | | | |
ор 0 0 0 0 0 0 1 1 |
| 0 0 | LUN | Zero value |
2 | Zero Value |
3 | Zero Value |
4 Zero Value |
5 | o 0 1 C | © 0 0 0 о |
SENSE DATA FORMAT
Bel 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Byte | | | | | | | | |
0 | - SENSE CODE |
1 | CO | 0 |} LUN | HEAD NUMBER |
2 ' CO | Cos | SECTOR NUMBER |
3 | CYLINDER LOW (C 07 to C 00) |
SENSE DATA WORD FORMAT
Bi: nad e e 7 € $ 4 3 2 1 0
Word | | | | | | | | | | | | | | | |
ог СЮ 10 LUN HEADNUMBER | SENSE CODE QU
1 | CYLINDER LOW C 07-C 00 | С09 |С08| SECTOR NUMBER
See APPENDIX A for SENSE Codes
8000 Series - Page 5-6
5.4.4 FORMAT DRIVE Command (04,4)
This command causes the specified Logical Unit Number (LUN) to be formatted using the
Interleave Factor specified in byte 4. Formatting starts at the specified track and proceeds until the
last track of the unit is formatted. Each track 1s formatted from index to index. The first sector
formatted is always sector Zero. An interleave factor of Zero is set equal to one. Track and cylinder
overfiow is handled automancally by the controller.
If bit 6 of the Control Byte is set to 0, all data fields are written with the pattem "6C y”. If bit 6 of
the Control Bvte is set to 1, ali data fields are written with the pattern contained in the controller
data buffer. This allows "worst case” patterns to be written by executing 2a WRITE DATA
BUFFER command prior to the FORMAT command.
The FORMAT command does NOT handie media defects. For verification of format, see the
READ VERIFY command or the CHECK TRACK FORMAT command (ESDI drives only). For
mediz defect handling, see the ASSIGN ALTERNATE TRACK command, or the FORMAT BAD
TRACK Command.
= «нь
Brel 7 | 6 | S | 4 | 31 21 111 0 |
Byte | | | | | | | | |
0; 0 To 0 0 0 1 0 6 |
| C10 | O | LUN | HEAD NUMBER |
2 | Cos | COS | © 0 0 0 0 о |
3 | - CYLINDER LOW (C 0710 C 00) |
4 | © 0 о | INTERLEAVE VALUE |
SI RI BI CIO 0 | $ S S |
T
5.45 READ VERIFY Command (05y)
This command verifies ID and DATA integrity of the recorded data starting at the specified address
and for the block count specified This command functions exactly as the READ command with the
exception of no datz transfer to the host
Bil 7 | 6 | 5S | 4 | 3 | 2 1 1 1 0 |
Byte | | | | | | | | |
0 | о 0 0 0 0 1 0 a
1] C10 | O0 | LUN | HEAD NUMBER |
2 | Co | Cos | SECTOR NUMBER |
3 | CYLINDER LOW (C 0710 C 00) |
4 | BLOCK COUNT |
s| RI El €C | © о т $ S s |
8000 Senes - Page 5-7
5.4.6 FORMAT TRACK Command (06g)
This command causes the track specified to be formated using the interleave factor defined in Byte
4. The track is written staring with index. The first sector after index is always sector zero.
Interleave factor of zero 15 sei to one. If bit 6 of the contro] byte is set to zero, all the data fields are
written with "6Cy”. If bit 6 of the contro! byte is set to one, data fields are written with whatever
data is is the data buffer. This allows "worst case” patterns to be wntten by first executing a WRITE
DATA BUFFER command
== = z—-— = —— =
Bl 7 | 6 | 5 | 4 | 31 21 11 01
Byte | | | | | | | | |
ог 0 0 0 0 0 1 1 о |
1 CO | O | LUN | HEAD NUMBER |
2 | CO | Cos | Zero value |
3 | CYLINDER LOW (C 07 to C 00) |
4 | 0 0 о | INTERLEAVE VALUE |
5
R | B | C | о 0 | 5 S S |
54.7 FORMAT BAD TRACK Command (07g)
This command is identcal to the FORMAT TRACK command excep: that the defective track
fiag is set in the ID field All subsequent accesses to the sectors on this track will result in Bad
track Fiag set errors.
Bl 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bye | | | | | | | | |
0j 0 0 0 0 0 1 1 1 |
i ji C0 | 0 | LUN | HEAD NUMBER |
2 | С09 | COS | Zero value |
3 | CYLINDER LOW (C 07 to C 00) |
4 | 0 0 0 | INTERLEAVE VALUE |
SI RI BI Elo els S s |
8000 Series - Page 5-8
5.4.8 READ Command (08)
This command causes the number of blocks specified by byte 4 to be transferred from the specified
LUN to the host. The command executes an implied seek to the starung sector specified. Up to
256 blocks can be transferred with a single READ command (If byte 4 is equal to zero, 256 sectors
will be transferred).
Bl 7 | 6 | 5 | 4 | 3 | 2 | 1 1 0 |
Byte | | | | | | | | |
010 To о 0 1 0 о о
| сю | O | LUN | HEAD NUMBER |
21C0 | COS | SECTOR NUMBER |
3 CYLINDER LOW (C 07 10 C 00) |
4 | BLOCK COUNT | |
5| R | E | C | oO о | $ S S |
— 2 dur — rie. a cl A 0 SME AR SER o A
5.49 WRITE Command (0AR)
This command causes the number of blocks specified by byte 4 to be trunsferréc from the host to
the specified LUN. The command executes an implied seek to the starung sector specified Up to
256 blocks can be transferred with a single WRITE command (If byte 4 15 equal to zero, 256
sectors will be transferred).
Bi] 7 | 6 | 5 | 4 | 3 | 2 | 1 i 0 |
Bye | | | | | | | | |
o | 0 о 0 0 1 0 100
| Cio | O0 | LUN | HEAD NUMBER
2 | Co | Cos | SECTOR NUMBER |
3 | CYLINDER LOW (C 07 10 C 00) |
é | BLOCK COUNT |
5i R | 0 } C | © 0 | S S S |
— Er Se a = due dj ся ЧН
8000 Series - Page 5-9
£.4.10 SEEK Command (0BY)
This command causes the device addressed by the LUN to be physically positioned to the cylinder
as defined in bytes one to three. No attempt to verify seek position is made until a READ or
WRITE command is issued. Complenon status is returned to the host immediately after issuing all
required step pulses or immediately after issuing the command (ESDI drives only). This allows
overlap seek operations.
Bel 7 | 6 | 5 1 4 | 3 | 2 | 1 | © 1
Byte | | | | | | | | |
“o | 0 0 0 0 1 0 1 1
Tico 1 ol LUN | HEAD NUMBER |
2 | Co | Cos | Zero value |
3 | CYLINDER LOW (C 07 to C 00) |
va | 0 0 0 0 0 0 0 о |
EI RI OI CIO 0 | S S s |
B000 Series - Page 5-10
£4.11 INITIALIZE DRIVE CHARACTERISTICS Command (OCH) not valid for ESDI drives.
This command allows the host to specify disk drive parameters for the specified LUN. This aliows
the controller to communicate with a wide vanety of drives from the same or difierent vendors. The
associated Parameter List, including all characteristics of the drive connected. 1s sent to the
controlier during the Data Out phase of the command execution. There is no access to the dnve
during execution of this command.
Bel 7.1 6 1 5 | 4 1 3 1 21 11 O |
Byte | | | | | | | | |
CL 0 0 0 1 1 o 0 |
| 0 | LUN | 0 0 0 0 о |
"2 through 5 Zero value |
During the Data Out phase of the command 8 bytes are sent as foliows:
Parameter Block Bvte Format
BR e Ys | 4 1 31 21 1 1 0
Byte | | | | | | | | |
© | Maximum Number of Cvlinders (MSB) |
1 | Maximum Number of Cylinders (LSB) |
2 | Maximum Number o7 Heads |
3 | Start Reduced Write Current Cylinder (MSB) |
4 | Start Reduced Write Current Cylinder (LSB) |
5 | Start Write Precompensation Cylinder (VSB) |
6 | Start Write Precompensation Cylinder (LSB) |
7 | Set to zero. |
Parameter Block Word Format
Bit da 13 12 1 109 8 7 6 5 4 3 2 1 —o
Word | | | | | | | | 1 1 | | | j |
0 | Maximum Number Cylinder (LSB) | - Maximum Number Cylinder (MSB) _
1 | Start Reduced Wr. Current (MSB) | Maximum Number of Heads
2 | Start Write Precomp. (MSB) | Start Reduced Wr. Current (LSB)
3 Zero Value | Start Write Precomp. (LSB)
8000 Series - Page 5-11
BYTES 0-1 (Word 0) - NUMBER OF CYLINDERS : Thus word specifies the maximum number
of cylinders on the Disk drive. The controller is capable to address up to 2048 cylinders.
BYTE 2 (LSB of WORD 1) - NUMBER OF HEADS : The value of this byte specifies the number
of user heads on the Disk drive. The controller accepts a maximum of up to 16 heads with a value
of 15 (OFy). Any value greater than 07y causes the reduced write Current (WST) function to be
disabled.
BYTES 34 (MSB of WORD 1. LSB of WORD 2) - START REDUCED WRITE CURRENT
CYLINDER : These 2 bytes specify the cylinder address where reduced write current 1s first
applied. Reduced write Current is applied to all cylinders greater than or equal to the value of these
2 bytes. This function is disabled for Removable and Fixed/Removable dnves.
BYTES &6 (MSB of WORD 2, LSB of WORD 3) - START WRITE PRECOMPENSATION
CYLINDER : These 2 byes specify the cylinder address where Tite precompensation is firs:
applied. Write precompensauon 15 anplied to all cylinders greater than or equal to the value of these
2 bytes. The amount of write precompensanon 1s 12 nanoseconds.
5.4.12 READ ECC BURST ERROR LENGTH Command (0D)
This command returns one word of data during the Datz In phase of the command execution. This
word contains the length of the ECC error detected during the most recent correctable data field
error. The length can range from 1 through 5 bits corrected for ST drives or from 1 to 11 bits
corrected for ESDI drives. This command allows the host to decide on the validitv of the correctec
data. I: is used in conjunction with the Disable ECC bit set on à READ commanc
аа а .— a. — q— ur
‘рая чаи фары от ЧН чин. чин Чье —
Bel 71.1 6 | 5S 1 4 | 3 21 1 1 O!
Bvie | | | | | | | | |
ol 0 0 0 0 1 1 “0 1 |
1 rough 5 Zero value |
Bi: | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Ву | | | | | | | | |
01 ECC error length о |
8000 Series - Page 5-12
5.4.13 READ DATA FROM SECTOR BUFFER Command (0Ey) |
Datz from the controller buffer is returned to the host. The number of data bytes returned is equal to
the jumper selectable sector size times the block count specified in byte 4 of the device contro! block
up to a maximum block count as follows:
Sector Size Block or Sector Count
512 15
1024 7
1056 7
This command is normally used immediately after a Read Data to Sector Buffer (IE) command
has been issued to enhance performance when data transfers are done using programmed МО.
The controller does not access the disk drive duning the execution of this command.
"Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Byte | | | | | | | | |
0 a 0 0 0 0 1 1 1 0 |
1 | Zero value |
2 | Zero value |
3 | Zero value |
4 | BLOCK COUNT |
5 | Zero value |
The READ BUFFER Command can also be used to model and srarus information about the
controller. If a READ BUFFER COmmand is issued after a RESET 15 done (before any other
command) the firs: XX bytes in the buffer contain the following irformation.
HEX Address Contents
00 through 0D * EXOVW.WMMDDYY
ОЕ " OF ROM checksum Word
10-b:t 0 ==" ROM checksum error
11-bit 0 === Processor Register error
12-bu Q === Buffer Ram error
13-bit 0 === Sequencer Register File Error
14-bits 7 & 6 0-0 8K buffer size
0-1 16K buffer size
1-0 32K buffer size
1-1 64K buffersize
15-1F Reserved
20-2F LUN 0 Default Values **
30-3F LUN 1 Default Values *=
404 Rserved
$0-5Е LUN 3 Default Values *=
8000 Series - Page 5-13
x = 1 for 8100. 2 for 8200. 5 for £500. 6 for 8600
W = Revision level ** Default Values ««# Valid only after a POWER ON or if a
MM = Month occurred diagnostic error (305) on
DD = Day the previous POWER ON or RESET.
YY = Year
LUN DEFAULT VALUES
Address Winchester Disk
Byte O 00
1 00
2 00
3 00
4 Cvlinder High 01
5 Cylinder Low 31
6 Head Count 03
5 SectTrack (depends on Jumpers) ?
§ Write Precompensauon 00
9 80
10 Reduce Write Current 00
1] 80
12 Step High 3C
13 Siep Low 09
14 Reserved 00
15 LUN FLAG (see below) 82
LUN FLAG Bute, Bit Assigmment (Byte 15 of LUN Default Values)
Bit 7 Reserved
Bit0& 1 BLOCKSIZE
O0 = 512 Bytes/sect (17 sect/rrack)
Oi = 512 Bvies/sect (18 secvrrack)
10 = 1026 Bvies/sect
11 = 1056 Bytes/sect
Bits 3 & 2 Reserved
Bit 4 ( = Soft Sector forma!
| = Hard Sector forma:
Bits 5 & 6 DRIVETYPE
00 = Standard ST506'412 (Fixed)
01= ESDI (Fixed)
10 = Sencar ST306'412 (Removeable)
1 1 = ESDI (Removeable)
8009 Series - Pace 5-14
5.4.14 WRITE DATA TO SECTOR BUFFER Command (0F y)
This command causes data to be written from the host to the controliers buffer. The number of data
bytes that can be written is limited 10 the jumper selectable sector size umes the block count
specified in byte 4 of the device control block up to a maximum block count as follows:
Sector Size Block or Sector Count
256 31
512 15
1024 7
1056 7
The controller does not access the disk drive during the execution of this commanc.
Bil 7 | 6 | 5 | 4 | 3 | 2 { 11 0 |
Byte | | | | | | | | |
oO; 0 0 0 0 1 1 1 1 |
1 | Zero value |
l
2 | Zero value |
J 3 | Zero value |
- |
& | BLOCK COUNT |
|
5 | Zero value
£4.15 CHECK TRACK FORMAT Command (0Fyy). Valid for ESDI drives only.
This command checks the integrity of the track specified against CRC, ECC value.
Bal 7 | 6 | 5-1 4 | 3 | 2 | 1 | 0 |
Byte | | | | | | | | |
0 | 0 0 0 1 0 0 0 0 |
] | сю | O : LUN | HEAD NUMBER |
2 | CO9 | CO | Zero Value |
3 | CYLINDER LOW (C 07 to C 00) |
4 | 0 0 0 0 0 0 0 о |
SI RI OI CIO о | S S Ss |
8000 Senes - Page 5-15
5.4.16 ASSIGN ALTERNATE TRACK Command (11)
This command is used to assign an alternate wack to the track specified in bytes 110 3, so that
any future accesses to the blocks on the specified track cause the controller to automatically
access those blocks on the alternate track. This command sets flags in the ID field and
writes the alternate track address in all blocks on the specified track. The alternate track 1s
then formatted with flags set to indicate that this track has been assigned as an alternate track
Future direct accesses to the alternate track will result in an error. Interleave factor Of zero 1s set
to onc.
We Seer SE Sm e E WE CE ido SEA Sry ЧМ e e
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Byte | | | | | | | | |
ie e el 0 0 0 1 |
Em 1 0 7 Lun | HEAD NUMBER |
2 | Co | Cos | Zero Value |
3 | CYLINDER LOW (C07 to C 00) |
6 0 0 о | INTERLEAVE VALUE |
5} R } B 1 C | © 0 | $ S S |
A GS SE Ee EN Si Ee gee i SE чина» се ан о —
EE GAT. CHEN. ME SE EE. STE Gime Ge Smee GU WE Se Se Se SE Че. Sle We AEE SESS GER She SRM Sn. Sy НН ОЛ
The following 4 bytes (2 words), represenung the alternate track address, are sent 10 the controller
during the Data Out phase of the command execution.
Ee «E > A we SS Sal Wier Sew ED AD SWE Ms SEP A A di dae WE VU E. A DA TA A A A o Se SSE SE
LL TE. ЧЕРИ SP a m dal le
ap я аи Gu den vio E ана —
EE mm Se ee GE GR GU E Ao VE Pv Gm ES New a i Se w—
Bi | 7 | 6 | 5 | 4 | 3 | 2 | 1 i 0 |
Byte | | | | | | | | |
pc oo 0 | HEADNUMBER |
2 | CO | COS | Zero Value |
2 | CYLINDER LOW (C 07 to C 00) |
3 Zero Value |
—— — EEE ME ER a a A Eg DS da A Us lee GE GR Ts E e EUA E ae e Ms Sr SW WE Gi Sow TU e e A A SEE E A ЧЕН we ЧАН oS Ch SRE WR TE
i een nue — ee Emm — Mr GP de di dr MA Ee gm Gls EE WS WR SE GE SE Er SE SE UNA ее o fi i AD hi DE SE SE SS. SE SP SG ee Se Ee we dime Sew dive SEI EES. GE me SE GME EL AED AE ОН ЧН
Note : Data written on the ongine) track 2s well as on the alternate track will be destrovec. The
controller dogs not check if the track assigned as alternate track has been previously used as
alternate track for another rack. A tack assigned as an alizrnate mzy not have an alternate track
assigned to 1L
8000 Senes - Pare 5-16
ALTERNATE TRACK ADDRESS - Descriptor Biodk - Word Format
Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0
Word | | jp 1 | jL 1 1 | j 1 1 | |
0 | CO9 | COS! Zero Value CIONO O | HEAD Number
] | Zero Value | CYLINDER LOW C07- C00
£4.17 START/STOP Command (1A) Valid for ESDI drives only.
Е E Ба
Bi| 7 | 6 1 5 | 4 | 3 | 2 | 1 | 0 |
Bye | | | | | | | | |
0 | 0 0 0 1 1 0 1 о |
| о | LUN | Zero Value |
2 | Zero Value |
3 Zero Value |
5 | Zero Value | START |
5 | | Zero Value |
To star the unit the Start bit shall be set to one.
To stop the unit, the Start bit shall be se: to zero.
This command returns status immediately after receiving the command bytes, then does not wait for
the star or stop spindie operanon to compiere.
5.4.18 CHANGE CARTRIDGE Command (1B y)
This comman¿ is valid only for Removable disk drives. The command causes the "Change
Cartridge ” line (J2-Fin 2) to be assented for 2 period of one (1) millisecond.
Bil 7 | 6 | 5 | 4 | 3 1 2 | 1 1 0 |
Byte | | | | | | | | |
ог 0 0 0 1 1 0 ] 1 |
1 through § Zero Value |
8000 Senes - Page 5-17
5.4.19 READ DATA TO BUFFER (IE)
This command reads data from the disk to the controller's buffer. It does not transfer the data to the
hos: The number of data blocks that can be read is limited by the controller's Buffer size as
follows:
Sector Size Biock or Sector Count
512 15
1024 7
1056 7
This command can be used in conjunction with the READ DATA FROM BUFFER to enhance
performance when data transfer is done in programmed VO mode.
Bal 7 1 6 1 S | 4 | 3 1 2 | 1 | 0 |
Byte | | | | | | | | |
CH) e e 0 1 1 1 1 0 |
1 | сю | © | LUN | HEAD NUMBER |
2 | CO | Cos | SECTOR NUMBER |
3 | CYLINDER LOW (C 07 to C 00) |
4 | BLOCK COUNT |
si R | E | C | © 0 | S S s |
5.420 WRITE DATA FROM BUFFER (1FH)
This command writes daz from the controller's buffe- to the disk. The number of sectors written 1s
specified by the block count parameter but 15 limitec by the controlier's buffer size as foliows:
Sector Size Block or Sector Count
512 15
1024 7
1056 7
An eto will be returned if the block count exceeds the above Limits.
"Bil 7 1 6 1 5 | & | 3 1 2 | 1 1 0 |
Evt | | | | | | | | |
oi; 0 0 0 ] 1 1 ] 1 |
1 | C0 | O | LUN | HEAD NUMBER |
2 | CO | COS | SECTOR NUMBER |
31 CYLINDER LOW (C 07 10 C 00) |
& | BLOCK COUNT |
s| R | E | C | © 0 | S < S |
— — di === = == = = == сено еше шк кин te ús a ce ee ve te Пт ПШ ПЕ 4+ 1 +14 + T+ + 1 3 T+ ++ e tt
8000 Series - Page 5-18
5421 COPY Command (20H)
This command copies a specified number of blocks (byte 4) from a Source LUN to a Destination
LUN. Source and Destination LUN may be the same. Block sizes on both Source anc
Destination LUN's must be identical. No data is transferred to the host.
Bit! 7 1 6 1 5 1 4 1 3 1 2 1 1100
Byte | | | | | | | | |
010 0 1% 0 0 0 0 |
1 CIO y SOURCELUN | HEAD NUMBER |
2 ee ico] SECTOR NUMBER a
| CYLINDER LOW (C 07 to C 00) |
a | BLOCK COUNT |
51 C10 | DEST.LUN | HEAD NUMBER 1
6 | CO | Cos | SECTOR NUMBER |
7 | CYLINDER LOW (C 07 to C00) 1
5 | Zero Value |
1 R | E | € 1 0 0 | 5 S S |
Note: If source and destination LUNs have different Step rates, the step rate specified in the contro:
byte should be the slower of ths two.
8000 Series - Page 5-19
8.422 READ ESDI DEFECT LIST Command (37g)
This command cause the specified Logical Unit Number (LUN) to return 256 bytes of drive
manufacturer recorded DEFECT LIST dunng the Data In phase of the command execution. Only
the list for the specified HEAD will be remmed.
A — аль» ноль ие
Bal 7 | 6 1 S | 4 | 3 1 2 1 11 0
Byte | | | | | | | | |
0] © 0 1 1 0 1 1 1 |
] | O | 0 | LUN | HEAD NUMBER |
2 | Zero Value |
3 | Zero Value |
4 | Zero value |
5 | Zero Value |
DEFECT LIST Data Format
Header
Bit] 7 | 6 1 5 1 4 | 3 1 2 1 1 1 01
Byte | | | | | | | | |
o MONTH |
] | DAY |
2 | YEAR |
3 | HEAD NUMBER |
4 | Zero Vajue |
5 | Zero Vajue |
8000 Series - Page 5-20
Defect Descriptor Format
6 | CYLINDER (MSB) |
7 | CYLINDER (LSB) |
8 | BYTE COUNT FROM INDEX (MSB) |
9 | BYTE COUNT FROM INDEX (LSB) |
10 | ERROR LENGTH (IN BITS) |
Each defect is hsted with a 5 bytes field as described above.
End of List Format
xx | FFy 7 |
xx-3 | FF |
хх-2 | FFy |
xx- 1 FFy |
xx | Fry |
Five FFy bytes indicate the end of the DEFECT LIST. .
The maximum number of defects is 50 per bead.
5.423 RAM DIAGNOSTIC Command (E0y;)
This command performs à pattem test on the internal controller buffer.
Be| 7 | 6 | 5 | 4 | 3 | 2 | 1 1 07
Byte | | | | | | | | |
ог 1 1 1 0 0 0 0 о |
1 through: 5 Zero Value |
8000 Series - Page 5-21
5.424 READ ID Command (E2y)
This command returns 4 bytes (2 words) of the ID field of the sector specified during the Data In
phase of the command execution. Only one sector 1s processed per READ ID command.
BR e Y s 1 a 1 ad 21 1 1 01
Byte | | | | | | | | |
0 BE 1 1 о 0 1 0 |
1 | сю | O | LUN | HEAD NUMBER |
2 | CO | Cos | Zero Value |
EX | CYLINDER LOW (C 07 to C 00) |
4 | Zero Value |
SL RI OI CIO 0 | 5 5 s |
READ ID Descriptor Block
Bul 7 1 60 5 1 4 | 3 | 2 } 1 1 0 1
Byte | | | | | | | | |
0 | © 0 0 0 O | CIO | CO9 | Cos |
= CYLINDER LOW (C 07 to C 00) |
2 | FLAGS | 0 | HEAD NUMBER |
3 |
SECTOR NUMBER |
READ ID Descriptor Block - Word Format
Bi: 15 12 13 12 11 10 6 8 7 6 54 3210
Word | | | | | | | | | | | | | | | | |
0 CYLINDER LOW C07-C00 0 0 0 0 0 :CI0/C09;C08
1 SECTOR NUMBER | FLAGS | 0 |HEADNUMBE
A a ES — че «ные цао Мио ЧН — e — — ij di = _ НН Ч, =
8000 Seres - Page 5-22
Byte 2, HEADS! FLAGS bit are defined as follows :
Bi: 0 = Head ]
Bit ] = Head 2
Bit 2 = Head 4
В: 3 = Head §
Bi: 4 = 0
Bit § = Alternate Track Flag
Ви 6 = Bac Track with Alternate Assigned
Bit 7 = Bad Track
5.425 DRIVE DIAGNOSTIC Command (E3y)
This commané causes the controller to perform the following drive funcnons; recalibrate
sequennally seek to every track and read sector 0.
BNO 1060105104 13 Y |
Byte | | | | | | | | |
aa Ш 0 о To 1
1 108 LUN | © 0 0 0 о |
a " Zero Value |
3 Zero Value |
a i Zero Value |
Si OR 160008 0 0 | 5 S S |
5.426 CONTROLLER INTERNAL DIAGNOSTICS Command (Edy)
Tnis command causes the controller 10 perform some intemal diagnostics including ROM
Checksum RAM tes: Sequencer test and ZE self tes: See Appendix A SENSE code type 3 for
Ceraiiec error codes.
Bi] 7 16 15 1 4 1 315 | 1 1 0 |
Byte | | | | | | | | !
0] 1 1 1 0 0 1 0 0 |
|
— 0 “ve a ajo Mu de
8000 Series - Page 5-23
5.4.27 READ LONG Command (ESy)
This command returns the Block size equal to the jumper selectec sector size (512, 1024 or
1056) of data plus 4 bytes (for ST506/412 dnves) or 6 bytes (for ESD] dnves) of ECC data
Bil 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Byte | | | | | | | | |
o| 1 1 1 0 0 1 0 1 |
1 | Cl0 | 0 | LUN | HEAD NUMBER |
2 CO | Cos | SECTOR NUMBER |
3 | CYLINDER LOW (C 07 to C 00) |
4 BLOCK COUNT |
5; R |} 0 } C } © 0 | $ S S |
— — — te A
5.428 WRITE LONG Command (E6y)
This command requires the Block size to be equal to the jumper selected sector size (512, 1024 or
1056) of data plus 4 bytes (for ST506/412 drives) or 6 bytes (for ESDI drives) of ECC data.
Wy Are. “ario des ЧОН o al «Ц
Bit | 7 | 6 | 5 4 + 3 | 2 | 1 | |
Byte | | | | | | | | |
о 1 1 1 0 Ш 1 1 0 |
1] C10 | 0 | LUN | HEAD NUMBER |
2 | Co | Cos | SECTOR NUMBER |
3 | CYLINDER LOW (C 07 to C 00) |
4 | BLOCK COUNT |
5j] R } © | C 1 © 0 | 5 S S |
8000 Series - Page 5-24
5.429 READ CONFIGURATION Command (ECy) valid for ESDI drives only.
This command returns to the host the drive configuration.
— — =>
dlls — — ae
Bi | 7 | 6 1 5 | 46 | 3 | 2 | 1 | 0
Byte | | | | | | | | |
o | Operation Code o]
Logical Unit Number | Reserved |
2 throu ghé| Reserved
s Го гого | 0 | O | O | 0 |LNK |
HARD and SOFT SECTORED Drives
0 | NUMBER OF CYLINDERS (MSB) - |
1] NUMBER OF CYLINDERS (LSB)(-1) И
2 NUMBER OF HEADS (-1) |
3 NUMBER OF SECTORS (-1) |
4 DRIVE CONFIGURATION WORD (MSB) |
Un
DRIVE CONFIGURATION WORD (LSB) |
mo a o E
6 ISG AFTER INDEX |
| БОРТ SECTORED Drives
7 PLO SYNC Field (ID) À
8 | PLO SYNC Field (DATA) |
9 | ISG AFTER SECTOR |
HARD SECTORED Drives
7 | PLO SYNC Field IDDATA) a
8 | ISG AFTER SECTO:!: |
© | Zero Value |
8000 Series - Page 5-25
DRIVE CONFIGURATION WORD (Bytes 4 anc 5):
The following tables lists the supported functhons of the ESDI drive configuration.
Byte 4
ESDI TAPE Drive
Bits
FORMAT SPEED TOLERANCE GAPREQUIRED 6,146
TRACK OFFSET OPTION AVAILABLE 5.13
DATA STROBE OPTION
ROTATIONAL SPEED TOLERANCE IS>05%
TRANSFER RATE T > 10 MHZ
TRANSFER RATE T = 10 MHZ
TRANSFER RATE T = 5 MHZ
Byte 5
ESDI REMOVABLE MEDIA
ESD! FIXED MEDIA
ESDI MOTOR START/STOP OPTION
HEAD SWITCHING TIME > 15 MICROSECONDS
RLL ENCODED, NOT MFM
ESD! SOFT SECTORED
ESD] HARD SECTORED
Reserved
С) — LU) fa Un On 4
PLO SYNC Field, ISG after INDEX and ISG after SECTOR :
Bytes 6, 7,8,9
CHECK CONDITION status.
Supported
Not supported as yet
Not supported as yet
Supported
No: Supported
Supported
Supported
Supported
Supported
Supported
Supported
Controller ignores
Supported
Supporied
The controller accepts a value of up to 255 or FF for each of these fields.
8000 Senes - Page 5-26
SECTION 6
FLOPPY DISK FUNCTIONS
6.1 FLOPPY DISK COMMAND SUMMARY
The following is a List of commands that may be issued to the Floppy section of the disk controlier.
READ DATA
FORMAT A TRACK
SCAN EQUAL
SCAN LOW OR EQUAL
SCAN HIGH OR EQUAL
RECALIBRATE
SENSE INTERRUPT STATUS
SPECIFY
SENSE DRIVE STATUS
SEEK
INVALID
6.2 DESCRIPTION OF SYMBOLS
The foliowing are descriptions of the Symbols used in the "Command Definitions” lar. - In this
section.
AO Address Line 0- AO selects the main status register, and a 1 selects the data register.
C Cylindez Number-Contains the current or selected cylinder number in binary notation.
D Da:a-Contains the data pañern to be written t0 a sector.
D7-DO | Date Bus-An 8-bi: data bus in which D7 is the most significant bit and DO is the least-
significant
DIL Data Length- When N is 00, DTL is the data length to be read from or writien to a
sector.
EOT End of Track- The final sector number on a cylinder.
GPL Gap Length - The length of gap 3 (spacing between sectors excluding the VCO
synchronous field).
XL
Head Address - The head number, either O or 1, as specified in the ID field.
HD Head - The selected head number, either Dor 1. (5=HD in all command woms).
8000 Series - Page 6-1
HUT
MF
MT
NCN
ND
PCN
RW
SC
SRT
STO-STI
STP
USO-US1
Head Load Time - The head load time in the selected drive (2 10 256 miliiseconds
increments for the 1.2Moyte drive and 6 to 512 milliseconds in 4 milhsecond increments
for the 320K-byte drive).
Head Unload Time - The head unload time after a read or wnite operation (0 to 240
milliseconds in 16 millsecone increments for the 1.2M-bvie érive anc 0 10 480 mill:-
seconds in 32 millisecond increments for the 320K-bvte drive.
FM or MFM Mode - AO selects FM mode and a 1 selects MFM. ( MFM is selected only
if it is implemented).
Multitrack - Al selects multitrack operation. (Both HDO and HD1 will be read or
written).
Number - The number of data bytes written in a Sector.
New Cylinder - The new cylinder number for a seek operation.
Non-Data Mode - This indicates an operation in the non-data mode.
Present Cylinder Number - The cvlinder number at the completion of a Sense interTupi
status command (present position of tne head).
Record - The sector number 10 be read or WIEN.
Read Write - This stands for either a read’ or ‘write’ signal.
Sector - The number of sectors per evlinder.
Skip - This stands for skip deleted-data address mark.
This 4 bit byte indicates the stepping rate for the diskette drive as foliows:
1.2M-Byte Diskette Drive
1111 1 millisecond
1110 2 milliseconds
1101 3 milliseconds
320K-Bvte Diskette Dnve
1111 2 miliiseconds
1110 4 miliiseconcs
1101 6 milliseconds
Status O- Status 3 - One of the four recisters that stores 521$ information after 2
command is completes.
Scan Test - If STP is 1. the datz 10 contiruous sectors 15 compared with the Cate sen! by
the processor Curing à Scan operation. 12 STP»s 2, then alternate séctors a+ read anc
compares.
Uni: Select - The selected énive- number encoded the same as bits D and 1 of the digital
output register (DOR).
8000 Series - Page 6-2
63 FLOPPY COMMANDS
The following arc commands that may be issued 10 the fioppy section of controller.
NOTE: An X is used to indicate a dont care condinon
6.3.1 READ DATA command
Command Pnase : The following bytes arc issued by the processor in the command phase:
MT MF SK O 0 1 1 0
X X X X X HD US? USO
H
R
N
EOT
GPL
DTL
Res Phase : The following bytes arc issued by the controller in the result phase:
STI
ST2
C
H
R
N
6.3.2 FORMAT A TRACK Command
Command Phase: Tne following bytes are issued by the processor in the command phase :
0 MF O 0 ] 0 0
x X X X X HD US1 USO
SC
GPL
D
Rest Phase: The following bytes arc issued by the controller in the result phase:
ST1
ST2
C
H
R
N
6.3.3 SCAN EQUAL Command
Command Phase: The following bytes are issued by the processor in the command phase:
] 0 0 0 ]
MF SK
X X X X HD US! USO
QT
GPL
8000 Series - Page 6-3
Result Phase: The following bytes are issued by the controller in the result phase:
STO
ST]
ST
C
H
R
N
6.3.4 SCAN LOW OR EQUAL Command
Command Pnase: The following bytes are issued by the processor in the command phase:
MT MF SK 1] 1 0 0 1
¢ ‹ X X X HD US1 USO
RQ THEO
de
>
Result Phase: The following bytes are issued by the controller in the result phase:
STO
STI
32
C
H
R
N
6.2.5 SCAN HIGH OR EQUAL Command
Command Phrase: The following bytes are issued by the processor in the commanc phase:
MI MF SK 1 1 1 0 1
X X X X X HD US] USO
GEO
GPL
STP
Resul: Pnase: The following bytes are issued by the controller in the result phase:
STO
ST]
77507
8000 Senes - Page 6-4
6.3.6 RECALIBRATE Command
Command Phase: The following bytes are issued by the processor in the command phase:
0 0 0 0 0 1 ] ]
X X X X X 0 US1 Uso
Result Phase: This command has no result phase.
6.3.7 SENSE INTERRUPT STATUS Command
Command Pnase: The following bytes are issued by the processor in the command phase:
0 0 0 0 ] 0 0 0
Result Phase: The following bytes are issued by the controller in the result phase:
STO
PCN
6.3.8 SPECIFY Command
Command Phase: The following bytes are issued by the processor in the command phase:
0 O 0 0 0 0 ] ]
( SRT )( HUT )
( HLT ) ND
Result Phase: This command has no result phase.
6.3.9 SENSE DRIVER STATUS Command
Command Phase: Tne following bvtes are issued Dy the processor in the command phase:
0 0 0 0 0 0 1 0
X X X X X HD US! Uso
Result Phase: The following bytes are issued by the controller in the resul: phase:
ST3
€.3.10 SEEK Command
Command Pnase: The following bytes are issued by the processor in the command phase:
0 0 0 0 1 ] ] ]
X X X X X HD US1 150
NCN
Result Phase: This command has no resul: phase.
6.3.11 INVALID Command
Command Phase: The foliowin £ bytes are issued by the processor in the command phase:
Invalid Codes
X X X X X ED US! USO
Result Phase: The following bytes are issued by the controller in the result phase:
STO
8000 Series - Page 6-5
6.4 COMMAND STATUS REGISTERS
Tne foliowing is information about the command status registers STO through ST3.
6.4.1 Command Status Register O (STO)
The following are bit defmitions for command status register 0.
Bit 7-Bit 6
BitS
Bit 4
Bit 3 and 2
Bit )-Bit O
Interrupt Code (IC)
00 Norma! Termination of Command (NT) - The command was completed and
properiy executed.
01 Abrupt Termunaton of Command (AT) - The execution of the command was
stared but not successfully completed.
10 Invalid Command Issue (IC) - The issued command was never started.
11 Abnormal termination because, during the execution of a command, the
ready’ signal from the diskette dnve changed state.
Seek End (SE) - Set to 1 when the controller completes the Seek command
Equipment Check (EC) Set if a fault’ signal is received from the diskette drive, or
if the 'track-0' signal fails to occur after 77 step pulses (Recalibrate Commanc).
Not Used - Always zero
Unit select 1 and 2 (US 1 and 2) - Indicate a drive's unit number at interrupt.
6.4.2 Command Status Register 1 (ST1)
The foliowing are bit definitions for command status registers 1.
Bu 7
Bit 6
В!! 5
Bit 4
End of Cylinder (EC) - Se: when the controller tries to gain access to a sector of 2
cyimder.
Not Used-Always 0.
Data Error (DE) - Set when the controlier detects a CRC error in either the ID field o:
the data field.
Overrun (OR) - Se: if the controller is not serviced by the main system within a
certain ume dim dunng data transfers.
| Not Used - This bit is always ser to O.
No Datz (ND) - Se: if the controlier cannot find the setor specified in the ID register
during the execution of z Keac Datz, Write Dejetec Daz, or Scan Commanc. This
fiag 1s also set if the controlier canno: reas ne ID fieic without an error during the
execunon of 2 Read ID command or if the starting sector cannot be found dunng the
execution of 2 Read Cylinder command.
8000 Series - Page 6-6
Bit 1
Bit 0
Not Writeable (NW) - Set if the controller detects a ‘write-protect’ signal from the
diskette drive during execution o? a Wnte Datz, Write Deleted Data. or Format
Cylinder command.
Missing Address Mark (MA) - Set if the controller cannot detect the ID address
mark. At the same time, the MD of status register 2 15 set
6.4.3 Command Status Register 2 (ST2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not Used - Always zero.
s«#scontrol Mark (CM) - This flag is set if the controller encounters a sector that has
2 deleted data-address mark during execution of à Read Data or Scan command.
Data Error in Data Field (DD) - Se: if the controller detects an error in the data.
Wrong Cylinder (WC) - This flag is related to ND (no data) and when the contents
of C on the medium are different from that stored in the ID register, this flag 1s set.
Scan Equal Hit (SH) - Set if the connguous sector data equals the processor datz
during the execution of a Scan command.
Scan Not Satisfied (SN) - Set if the controller canno: find a sector on the cylinder
tha: meets the condition during a Scan commanc.
Bad Cylinder (BC) - Related to ND: when the contents of C on the medium are
different from tha: stored in the ID register, and the contents of C is FF, tms fiac 15
ser.
Missing Address Mark in Data Field (MD) Set if the controller cannot fincz data
address mark or a deleted data address mark when datz is read from the Medium.
6.4.4 Command Status Register 3 (ST3)
Tne following are bit definitions for command Status register 3.
Bit7
Bit 6
Ви 5
Bit 4
Bi: 3
Bu 2
В: 1
Bit 0
Not used - always zero.
Write Protect (WP) - Status of the 'write-protect' signal from the diskette drive.
Not used - always Zerc.
Track 0 (TO) - Status of the ready’ signal from the diskette drive.
No: usec - always zero.
Head Address (HD) - Status of the ‘side-select' signal to the diskette Cave.
Not used - always zero.
Not used - always 1.
8000 Series - Page 6-7
APPENDIX A
SENSE CODE SUMMARY AND DESCRIPTION
SENSE BYTES
At compieuon of a command. if the Status Resister reports an error condition (Bit 1 set), the
system may issue a REQUEST SENSE command (03,4) during which four sense bytes are returned
(Byte O through 3 as follows).
SENSE DATA BYTE FORMAT
Bi| 7 1 6 | 5 1 < | 3 1 2 1 1108
Bye | | | | | | | | |
ANT EG
1] C10 | 0 | LUN | . HEADNUMBER |
2 | CO | C6 | SECTOR NUMBER |
3 CYLINDER LOW (C 00-C 07) |
SENSE DATA WORD FORMAT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word | | | | | | | | | | | | | | | |
0 CIÓN O LUN) HEADNO. [AV] 0 | TYPE | CODE
1 | CYLINDER LOW C07-CO00 |C091C08| SECTOR NUMBER
= = seu Ee Re i EL ME EN = то
AV = Address Valid. If set, indicates that the error code in byte 0 applies to the sector address in
bytes 1,2,3.
SENSE TYPE (Bits 5 and 4 of Byte 0 or Word 0):
5 4
C O Drive Errors
0 1 Daz errors
1 0 Command Errors
1 1 Diagnostic Errors
8000 Series Appendix - Page A-1
ТУРЕ 0 - DRIVE ERRORS
5 4 3 2 1 0
0 0 0 000 No error
00 0 0 O01 No Index
00 O 01 0 Noseckcommandcomplete
0 0 0 01 1 Write/Dnive Fault
00 0100 Drive not selected’ not ready
0 0 0110 No track or cvlinder zero found
00 1 0 0 0 Seekcommandin progress
0 0 1 0 0 1 Cartridge changed
TYPE 1- DATA ERRORS
5 4 5 2 1 0
0 1 0 0 0 © ID CRC error (ESD]), ID ECC error (ST412)
0 1 0 0 0 1 Uncorrectable Data Error
0 1 0 010 ID address Mark not found
0 1 Cc 011 Data address mark found
0 1 0 100 Sector not found
0 1 O 1 01] Seek error
0 1 O 1 1 0 Seguencer/DMA failure
0 1 O 1 11 Write protected
0 1 1 000 Correctable Data Error
0 1 1 0 0 1 Bad track encountered
0 1 1 010 Diegal Interieave Factor
0 1 1100 Unable to read Alrernate Track cata
Dliegal access to an alternate track
0 1 1 1 0 1 Aliernate or Вас Track Already Assigned
0 1110 No Alienate Track Found
0 1 1 1 1 1 Alternate Assigned To liself
TYPE 2- COMMAND ERRORS
5 4 3 210
i C ¢ ¢ 0 0 Invalid Commanc
1 0 0 001 Illegal Disk Address
1 0 0 01 0 Ilegal Funcnonfo: Dave Type
1 0 0 0 1 1 Volume Overfiow
TYPE 3- DIAGNOSTIC ERRORS
5 € 3 2 1
0
0 RAM emo:
1
0
0 ZE firmware checksum/interna] diagnostic error
8000 Series Appendix - Page A-2
DESCRIPTION OF ERROR CODES
TYPE 0 - ERROR CODE DESCRIPTIONS
00
01
02
No error or no sense information. Indicates that there is no specific sense information to
be reported for the designated Logical Umit Number. Thus is the case for the successful
completion of the previous command. If a REQUEST SENSE command 1s 1ssued when
there 1s no error, the Sense information reported specifies the last Sector Address processed.
No Index. This indicates that during a FORMAT command, no INDEX signal was
received from the Logical Unit Number selected within three seconds.
No Seek/Command Complete. This indicates that no SEEK COMPLETE (OMT] 5510
anc 5527) signal or the SEER/COMMAND COMPLETE (OMTI €510) signal was
received from the Logical Unit Number selected within three seconds.
Write Drive Fault. This indicates that during a WRITE/FORMAT command. a fault
condinon occured. Refer to the disk drive specification for all possible condinons relanng to
this error.
Drive Not Selected Not Ready. This error occurs when the specified drive di¢ not retumn
tne DRIVE SELECTED signa! or the DRIVE READY signal. Reasons for this error vary
from dave to dnve, however, a common fault is the select configuranon jumpers located on
the dnve. Absence of cartndge or medium inserted in 2 removable drive may also cause
this error.
No Track zero or Cylinder zero found. This indicates that during a RECALIBRATION
(command or if remes are enabled) no Track or Cylinder zero was detected by the drive.
This error occurs if the controlier issued 5 steps more than the oz! number of cylinder
as currently defined for this Logical Unit Number, and did not detec: the TRACK ZERO or
CYLINDER ZERO signal from the drive.
Multiple Drives Selected. This indicates that the controller detected multipie DRIVE
SELECTED signals when it anempted to seject the specified Logical Unit Number.
Seek/Command in progress. This indicates that a seek or command is in progress. This
error code 1s only returned in response 10 2 TEST UNIT READY command. The controller
will report this error for every TEST UNIT READY command issued until! the seek or
command bas complerec.
Cartridge Changed. This indicates that the cartridge has been changed since the last access
to the specihed Logical Unit Number. This error code may only occur on Removabie type
drives.
TYPE 1- ERROR CODE DESCRIPTION
10
ID CRC .This indicates that at least one ID field on the specified track has a CRC erro.
This error can oniv occur on 2 CHECK TRACK FORMAT commanc. If a CRC error was
encountered on 2a READ or WRITE command, a RECORD NOT FOUND error will be
теропес. Tras is because there is no sure way to determine if the ID in error is the one the
controller is searching for.
8000 Senes Appendix - Page A-3
1]
12
13
14
15
16
17
18
19
1A
1C
1D
Uncorrectable Data ECC. This indicates that a data ECC error was detected which was
uncorrectable. The sector in error 1s NOT transferred to the HOST and the command is
terminated without exhausting the block count. The data can be recovered by issuing the
READ DATA BUFFER command provided that no other command reguinng the data
buffer has been issued
ID Address Mark Not Found. This indicates tha: the controller was unable to detect any
ADDRESS MARK signals from the selected Logical Unit Number.
Data Address Mark Not Found. This indicates that the controller was able to locate the
sector specified but was unable to locate the data address mark associated with iL
Record Not Found . This indicates that the controller was able 10 locate the correct cylinder
and head numbers but was unable to locate the correct sector. An ID CRC error can also
generate this error.
Seek . This indicates that a mis-compare of the cylinder and/or head occured berween the
specified sector address and the actual sector address recorded on the tack selected
Sequencer/DMA. This indicates tha: 2 sequencer/DMA overrun/underrun error occured.
Tnese functions are internal to the conrolier and inform about a serious hardware failure.
Write Protected. This indicates that during 2 WRITEFORMAT command, the controller
detected 2 WRITE PROTECTED signal from the selected Logica! Unit Number.
Correctable ECC. This indicates that 2 READ command was issued with the DISABLE
ECC bi: SET and a correctabie ECC was encountered. The corrected data will be
ransferres to the HOST: however. the command will be terminated exhaustinc the block
count A READ ECC BURST LENGTH command will specify the length of the ECC
error. If the DISABLE ECC bit was cieare<, the controller will automatically correct the
data error and continue the commanc as if no date error had occurred.
Bad Track Encountered. This indicates that the specified tack has previously beer
formatted with: the BAD TRACK FLAG set in the ID fielc. 1:15 no: possible 10 access datz
on this track znd the command will be terminatec.
Ilegal Interieave Factor. This indicates that 2 FORMAT/CHECK TRACK FORMAT
command was issued with an INTERLEAVE FACTOR greater thar the number of secioss
on the track or dunng 2 CHECK TRACK FORMAT command. the recorded interieave
factor dió nor ma:ch the INTERLEA VE FACTOR specified in tne CDE.
Legal Access To An Alternated Track/Unable To Read The Alternate Track Address. This
ing:cates ina: 2 direct access 10 an alternate track was апетир!ес or upon detecong Ie
ALTERNATE anc BAD TRACK fiags bo:h SET in an ID fielé tne controler was unable to
rea the alternate track data specifying the destinanon cylinder.
Alternate of Bad Track Already Assigned. This indicates tha: the destination track 07 2
FORMAT ALTERNATE TR<.CK commanc has previously been formaued as as aliema::
destination or bac. In order tc -se the specified rack as an aiternate desunatior,, 2
FORMAT TRACE commant must be issue.
No Alternate Track Found. This indicates thz* the controller was directed to an alienate
wack but did no: find the ALTERNATE bit SET in the ID field.
8000 Senes Appendix - Page A-4
IF Diegal Alternate Track Address. This indicates that a FORMAT ALTERNATE TRACK
command was issued with the source and destination sector addresses equal.
TYPE 2 - ERROR CODE DESCRIPTION
20 Invalid Command. This mdicates tha: the controller decoded 2 command code that it
does not support.
21 Dlegal Disk Address. This indicates that the controller received a command with a
Sector Address beyond the capacity of the drive. Check the number of cylinders, heads
and sector size that the drive is configured for.
ta
+
Hlega! Function for Drive Type. This indicates that a Change Cartridge command (HEX
1B) was issued to a LUN assigned as a Fixed drive type.
23 Volume Overflow. This indicates that after the commencement of à multiblock command,
| the end of volume was reached.
TYPE 3- ERROR CODE DESCRIPTION
30 RAM error. This indicates that the controller detected a dara error with its interna! RAM
buffer of 8K bytes.
3] EPROM Checksum'Interna] Diagnostic error. This indicates that a checksum error was
detected in the EPROM or the controller detected a Data Error in this sequencer register file.
8000 Series Appendix - Расе A-5
> NL Y
E> nn. а
ZO
On
hue! ju
ON Un
© ION N HS
ка a ja a It DO ION DNS
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APPENDIX B
INTERLEAVE SCHEME
512 BYTE SECTORS - 17 SECTORS PER TRACK
INTERLEAVE FACTOR
01 2 3 4 5 6 7 8
LOGICAL SECTOR NUMBERS
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7 E
< 4 6 8 10 12 14 16
3 6 9 12 15 ] ] 1
4 8 12 16 1 7 8 9
5 10 15 ] 6 13 15 -
6 12 ] 5 11 2 2 10
7 14 4 9 16 8 9 3
8 16 7 13 2 14 16 11
9 1 10 2 7 3 3 4
10 13 6 12 9 10 12
1] 5 16 10 3 15 4 5
12 7 2 14 8 4 11 13
13 9 5 5 13 10 5 6
14 11 8 7 4 16 12 16
15 13 11 11 5 5 6 7
16 15 14 15 14 11 13 15
1024 BYTE SECTORS - 9 SECTORS PER TRACK
INTERLEAVE FACTOR
01 2 3 4
LOGICAL SECTOR NUMBERS
0 0 0 C
1 2 3 4
2 4 6 $
3 6 ] 1
4 8 ¿ 5
5 ] 7 2
6 3 2 6
7 5 5 10
$ 7 6 3
Nowe: Interieave factor of zero will be se: to ons.
Interleave factors greater than one ha!! the tota! number of sectors per track are noi recommended.
8000 Senes Appendix - Page B-1
ACK
ADDR
ATN
BIOS
BSY
D LUN
DP
DRVR
ECC
EPROM
ED
ID
VO
LSB
ABBREVIATIONSMNEMONICS
Acknowledge
Address
Address Mark
Attention
Basic input/output System
Busy
Contro! Data
Command Descriptor Block
Cyclic Redundancy Check
Cylinder
Data Bit
Desunanon Logica) Unit Number
Datz Panty
Driver
Erro: Correction Code
Eraseable Programmable Read only Memory
Flexible Disk Controller
Head
Identificanon
Input/Output
Leas! Significant Bit
LSTTL Low-Power Schottky Transistor-Transistor Logic
LUN
MFM
MHz
Logica! Unit Number
Modified Frequency Modulation
Megaherz
8000 Senes Appendix - Page B-2
ns
PHY
RAM
RCVR
REQ
RST
SEC
S LUN
TP]
TIL
us
УСО
VLSI
WSI
XCVR
Nanoseconc
Non-Retum 10 Zero
Physical
Random Access Memory
Receiver.
Regues:
Reset
Sector
Selec:
Source Logical Unit Number
Track Per Inch
Track
Transistor-Transistor Logic
Mucrosecong
Volzee Control Osciliaro:
Very Large Scale Inxgration
Equivalen: to: Reduced Write Current
Transceiver
8000 Series Appendix - Pagz B-3
8000 Series Appendix - Page B=
APPENDIX C
BIOS INSTALLATION PROCEDURE
The 8000 Senes controllers may be delivered as an option with two (2) EPROMs containing an
IBM PCAT DOS companble BIOS. The EPROMS art inserted in the empty sockets on the PC
mother board.
IBM AT (256K):
ES E a
- the eprom labeled "EVEN ADDRESSES"
should be inserted into the socke: marked 1017.
- the eprom labeled "ODD ADDRESSES”
should be inserted into the socket marked U37.
TANDY 3000 (128K) :
- the eprom labeled "EVEN ADDRESSES"
should be inserted into the socket! marked U60.
- the eprom labeled "ODD ¿DDRESSES"
should be inserted into the socket marked USS.
To install the BIOS in other AT compatibles, please contact SMS teca-ical support for socket
locanons.
You may attach up to two (2) ESDI Winchester drives gr up to two (2) ST412 Winchester drives to
ше 8000 Series conroliez. You may ©; may not mix ESD] anc ST412 type drives. Jumper setungs
fo: ESDUST412 drive types are shown below. j
"NT ®
Tne £200 anc 8600 controllers provide floppy disk support which is fully AT bus and hardware
compauble. Therefore, you may remove the AT Wimnci-sterMfioppy controlier (if installed) and
connect the fioppy cabie to connector J7 on the 8200 or 8600 controller to suppor: the floppy drive.
To enable fioppy suppors jumper W7 must be installec
I you aircady have a Winchester disk (non-ESDI) attached to IBM AT controlier and you wish to
attack an ESDI drive to the E500 or 8600 conroliez, you may leave the AT controlier in place. In
this case, only one of the two controliers should control the floppy drive. To avoid conflicts
berween the two floppy conrolisrs, gone of the two controllers must be strapped for the secondary
fioppy base I/O address anc the pther for the primary fioppy base VO address.
To set the AT controlier to :
- the secondary base address, a jumper mus! be instaliedin E1-E2.
Then the 2500 or 860 controller mus: be set 10 :
- tne primary base address, with the jumper WY installed.
To set the 8500 or 8600 controller to :
- the secondary base address, jumper WY must be removed.
Then the AT conolier must be set to :
- the primary base address, 2 jumper must be instalied in E2-E3.
8000 Senes Appendix - Page C-1
NOTE: IBM's SETUP utility
should NOT be informed of the presence of any Hard disks
attached 10 the 8000 Series controller. This utility 1s only concerned with those dnves (if any)
which are attached to the AT controlier. Thus, if the only Hard Disk (s) instalied in the system 15
(are) attached to the 8000 Senes controller, the number of Hard Disks in the system must be
reported as zero (0) when ininalizing the system configuration parameters in the SETUP, utility.
IBM DOS version 3.1 has imbedded code in the system file IBMBIO.COM intended to patch
certain AT Fixed Disk BIOS probiems. This code, in certain instances. insists on talking to the AT
controlier and therefore will not access the R000 Series controllers properly. The system file must
be patched in order to avoid
Tne recommended patch is as follows Ç
this imbedded AT controller specific code.
- - TN а ..
+
he prohlem exists only in TRMDOS AL Picas: irnors this paich if you arc momins O7 an AT
comnaghie under MS-DOS:
In order to edit IBM.BIO.COM, you must change the atrribute byte ir the directory entry for tha:
file in order to make it appear as 2 non-hidden, read/write file. Use DEBUG.COM to do this (all
required keyboarc input appears underscored):
DERUG
„LCS:000 40
-D AN
. E Al 5
- NIIX:AOB 20
CW eS:0 0040
- Q
DIR TRMBIO.COM
DEBUC IEVBIO.CON
- D13DD
FE 12
- XXXX:13DD 2
- W
- writing xxxx bytes
-Q
DEBUG
„1 CS-000 49
-D AD
LT
- хххх:А0ОВ 27
. W CS-00040
-Q
: LOAD 1ST 40H ABSOLUTE SECTORS INTO CS:0
: CS:AOO SHOULD POINT TO DIRECTORY ENTRY
FOR IBMBIO
. CHANGE ATTRIBUTE BYTE TO A 20H
- WRITE THE 1ST 40H SECTORS BACK OUT
; EXIT DEBUG
- THIS FILE SHOULD NOW SHOW UP IN YOUR
DIRECTORY
- GOINTO DEBUG WITE THE FILE
. AN ASCII DATE MARKER SHOULD APPEAR:
01/10/84
. CHANGE THE DATE MARKER
; EXIT DEBUG
: LOAD IST 40H ABSOLUTE SECTORS INTO CS:0
- CS:A00 SHOULD POINT TO DIRECTORY ENTRY FOR
IBMBIO
- CHANGE ATTRIBUTE BYTE BACK TO WHATIT
WAS!
. WRITE THE 1ST 40H SECTORS BACK OUT
. EXIT DEBUG
This concludes the required pach.
8000 Series Appendix - Page C-2
DRIVE TYPE JUMPER SETTINGS (W1,W2, W3,and Wa)
1) ESDI drive(s) - All four (4) jumpers must be on. The drive characteristics for an ESDI drive are
provideC by the dnve itself. These characteristics will be stored in the uppermost 1K of system
RAM which will be protected by the BIOS from use by the system or any applications.
2) ST412 drive(s) - The remaining fifteen (15) combinations of settings for jumpers W1, W2, W'3,
and Wá define the following drive types :
JUMPERS DRIVEMODEL #CYL #HEADS
W4 W3 W2 WI
1 1 1 1 ****THIS SETTING USED BY ESD] DRIVES****
11] 1 0 MAXTOR XT1140 018 15
11 0 1 VERTEX 170 987 7
CYNTHIA 570
1] 0 0 CDC 9415-36 697 5
1 0 ] 1 RODIME 352 306 4
MICROSCIENCE HH312
1 0 1 0 SEAGATE ST4051 977 5
1 0 0 ] SEAGATE ST4038 733 5
1 o 0 0 CMI 6640 640 6
TULIN 240
RODIME 203E
0 1 1 ] CMI 6426 640 4
TULIN 226
RODIME 202E
о 1 ] 0 QUANTUM 540 512 8
0 1 0 1 DMA 360 612 2
O 3 0 0 MINISCRIBE 30123212 612 2
о 0 ] ] SEAGATE ST4026 615 4
0 0 1 0 ST225 PT925 (COGITO) ‘612 4
CMI 3426
0 © 0 ] SEAGATE ST419 306 6
CMI 5619
0 0 0 0 SEAGATE ST412/212 306 4
CMI 5412
LAPINE 3522
8000 Series Appendix - Page C-3
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